increase rom to 128 from 64HEADmaster

3 files changed, 103 insertions, 5 deletions

diff --git a/Makefile b/Makefile
index 70e8c94..c181cf9 100644
--- a/Makefile
+++ b/Makefile
@@ -1,12 +1,21 @@
 CC = riscv32-none-elf-gcc
 CP = riscv32-none-elf-objcopy
-CFLAGS = -fno-pic -nostdlib -fno-delete-null-pointer-checks --param=min-pagesize=0 -O3 -march=rv32i -mabi=ilp32 -Wall -Wextra -pedantic
+CFLAGS = -fno-pic -nostdlib -fno-delete-null-pointer-checks --param=min-pagesize=0 -O0 -march=rv32i -mabi=ilp32 -Wall -Wextra -pedantic
 
-SRC = fibonacci.c
+SRC_fib = fibonacci.c
+SRC_rom = rom_large.s
 ROM = riscvtest_rom_image.txt
 
-all: 
-        ${CC} ${CFLAGS} ${SRC}
+all: fibonacci
+
+fibonacci: 
+        ${CC} ${CFLAGS} ${SRC_fib}
+        ${CP} -j .text -O binary a.out /dev/stdout \
+        | od -t x4 -w4 - | cut -d' ' -f2 | head -n -1 \
+        > ${ROM}
+
+rom_large:
+        ${CC} ${CFLAGS} ${SRC_rom}
         ${CP} -j .text -O binary a.out /dev/stdout \
         | od -t x4 -w4 - | cut -d' ' -f2 | head -n -1 \
         > ${ROM}
diff --git a/riscvsingle.sv b/riscvsingle.sv
index 7436ed6..d078176 100644
--- a/riscvsingle.sv
+++ b/riscvsingle.sv
@@ -131,7 +131,7 @@ endmodule
 module imem(input  logic [31:0] a,

             output logic [31:0] rd);

 

-  logic [31:0] ROM[63:0];

+  logic [31:0] ROM[127:0];

 

   // Initialize the program memory

   // Simulator : ok

diff --git a/rom_large.s b/rom_large.s
new file mode 100644
index 0000000..e368519
--- /dev/null
+++ b/rom_large.s
@@ -0,0 +1,89 @@
+main:   addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x0, x0, 0
+        addi x1, x0, 300
+        sw x1, 0(x0)
+done:   bne x0, x1, done