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authorvin <git@vineetk.net>2025-03-24 16:46:05 -0400
committervin <git@vineetk.net>2025-03-25 16:31:35 -0400
commit70477dad47f985f68ce05668911939b0374ea364 (patch)
tree3eeb02465846dc3ffb3168f52d130b1d6eaae407
parent341ffb58d33ed5f0ce4743ec0881e11964589966 (diff)
refactor PCSrc assignment and add bne instruction
-rw-r--r--riscvsingle.sv11
1 files changed, 10 insertions, 1 deletions
diff --git a/riscvsingle.sv b/riscvsingle.sv
index e2c1baa..fc9c830 100644
--- a/riscvsingle.sv
+++ b/riscvsingle.sv
@@ -229,7 +229,16 @@ module controller(input logic [6:0] op,
229 ALUSrc, RegWrite, Jump, ImmSrc, ALUOp); 229 ALUSrc, RegWrite, Jump, ImmSrc, ALUOp);
230 aludec ad(op[5], funct3, funct7b5, ALUOp, ALUControl); 230 aludec ad(op[5], funct3, funct7b5, ALUOp, ALUControl);
231 231
232 assign PCSrc = Branch & Zero | Jump; 232// assign PCSrc = Branch & Zero | Jump;
233 always_comb
234 if (Branch)
235 case (funct3)
236 3'b000: PCSrc = Zero;
237 3'b001: PCSrc = ~Zero;
238 default: PCSrc = 1'bx;
239 endcase
240 else
241 PCSrc = Jump;
233endmodule 242endmodule
234 243
235module maindec(input logic [6:0] op, 244module maindec(input logic [6:0] op,