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| author | vin <git@vineetk.net> | 2025-03-10 16:20:23 -0400 |
|---|---|---|
| committer | vin <git@vineetk.net> | 2025-03-10 16:20:23 -0400 |
| commit | c7a70e1962a7b6d8dfd524d39f42a7f31261450f (patch) | |
| tree | 19832f8c0fc5cac58ef0c9637585685cf3756f6c | |
| parent | 011da633434a7506fac317abcbbe07ef8a7277ab (diff) | |
use relative filepath for ROM and RAM
| -rw-r--r-- | riscvsingle.sv | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscvsingle.sv b/riscvsingle.sv index f536718..91fbe19 100644 --- a/riscvsingle.sv +++ b/riscvsingle.sv | |||
| @@ -135,7 +135,7 @@ module imem(input logic [31:0] a, | |||
| 135 | // Simulator : ok | 135 | // Simulator : ok |
| 136 | // Hardware : For FPGA ok, non-FPGA we need a 3rd party solution to program the FLASH memory (ROM) | 136 | // Hardware : For FPGA ok, non-FPGA we need a 3rd party solution to program the FLASH memory (ROM) |
| 137 | initial | 137 | initial |
| 138 | $readmemh("C:\\Users\\onur\\Desktop\\CE_Lab2\\CEL_PROJECT\\riscvtest_rom_image.txt", ROM); | 138 | $readmemh("riscvtest_rom_image.txt", ROM); |
| 139 | 139 | ||
| 140 | assign rd = ROM[a[31:2]]; // word aligned | 140 | assign rd = ROM[a[31:2]]; // word aligned |
| 141 | endmodule | 141 | endmodule |
| @@ -169,7 +169,7 @@ module dmem(input logic clk, we, | |||
| 169 | // Simulator : ok | 169 | // Simulator : ok |
| 170 | // Hardware : For FPGA ok, non-FPGA we need a 3rd party solution to program the DATA memory (RAM) | 170 | // Hardware : For FPGA ok, non-FPGA we need a 3rd party solution to program the DATA memory (RAM) |
| 171 | initial | 171 | initial |
| 172 | $readmemh("C:\\Users\\onur\\Desktop\\CE_Lab2\\CEL_PROJECT\\riscvtest_ram_image.txt", RAM); | 172 | $readmemh("riscvtest_ram_image.txt", RAM); |
| 173 | 173 | ||
| 174 | endmodule | 174 | endmodule |
| 175 | 175 | ||
