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authorvin <git@vineetk.net>2025-03-10 15:41:13 -0400
committervin <git@vineetk.net>2025-03-10 15:41:13 -0400
commitf697bf76970fc1d264d52afd7e0e28d64f209e82 (patch)
tree08f56d8219b7a14382a6ab9b2227898e01424450
initial payload
Diffstat
-rw-r--r--CEL_PROJECT.qpf6
-rw-r--r--CEL_PROJECT.qsf285
-rw-r--r--CEL_PROJECT.sdc86
-rw-r--r--CEL_PROJECT.v38
-rw-r--r--my_computer_tb.v23
-rw-r--r--riscvsingle.sv390
-rw-r--r--riscvtest.s33
-rw-r--r--riscvtest_ram_image.txt1024
-rw-r--r--riscvtest_rom_image.txt21
9 files changed, 1906 insertions, 0 deletions
diff --git a/CEL_PROJECT.qpf b/CEL_PROJECT.qpf
new file mode 100644
index 0000000..475032c
--- /dev/null
+++ b/CEL_PROJECT.qpf
@@ -0,0 +1,6 @@
1DATE = "03:53:12 February 25, 2025"
2QUARTUS_VERSION = "16.0.0"
3
4# Revisions
5
6PROJECT_REVISION = "CEL_PROJECT"
diff --git a/CEL_PROJECT.qsf b/CEL_PROJECT.qsf
new file mode 100644
index 0000000..e18bca1
--- /dev/null
+++ b/CEL_PROJECT.qsf
@@ -0,0 +1,285 @@
1#============================================================
2# Build by Terasic System Builder
3#============================================================
4
5set_global_assignment -name FAMILY "MAX 10 FPGA"
6set_global_assignment -name DEVICE 10M50DAF484C7G
7set_global_assignment -name TOP_LEVEL_ENTITY "CEL_PROJECT"
8set_global_assignment -name ORIGINAL_QUARTUS_VERSION "16.0.0"
9set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
10set_global_assignment -name PROJECT_CREATION_TIME_DATE "03:53:12 FEBRUARY 25,2025"
11set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
12set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
13set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
14set_global_assignment -name SDC_FILE CEL_PROJECT.SDC
15
16#============================================================
17# CLOCK
18#============================================================
19set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
20set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
21set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
22set_location_assignment PIN_N5 -to ADC_CLK_10
23set_location_assignment PIN_P11 -to MAX10_CLK1_50
24set_location_assignment PIN_N14 -to MAX10_CLK2_50
25
26#============================================================
27# SEG7
28#============================================================
29set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
30set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
31set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
32set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
33set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
34set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
35set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
36set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
37set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
38set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
39set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
40set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
41set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
42set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
43set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
44set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
45set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
46set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
47set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
48set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
49set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
50set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
51set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
52set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
53set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
54set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
55set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
56set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
57set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
58set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
59set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
60set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
61set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
62set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
63set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
64set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
65set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
66set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
67set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
68set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
69set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
70set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
71set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
72set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
73set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
74set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
75set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
76set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
77set_location_assignment PIN_C14 -to HEX0[0]
78set_location_assignment PIN_E15 -to HEX0[1]
79set_location_assignment PIN_C15 -to HEX0[2]
80set_location_assignment PIN_C16 -to HEX0[3]
81set_location_assignment PIN_E16 -to HEX0[4]
82set_location_assignment PIN_D17 -to HEX0[5]
83set_location_assignment PIN_C17 -to HEX0[6]
84set_location_assignment PIN_D15 -to HEX0[7]
85set_location_assignment PIN_C18 -to HEX1[0]
86set_location_assignment PIN_D18 -to HEX1[1]
87set_location_assignment PIN_E18 -to HEX1[2]
88set_location_assignment PIN_B16 -to HEX1[3]
89set_location_assignment PIN_A17 -to HEX1[4]
90set_location_assignment PIN_A18 -to HEX1[5]
91set_location_assignment PIN_B17 -to HEX1[6]
92set_location_assignment PIN_A16 -to HEX1[7]
93set_location_assignment PIN_B20 -to HEX2[0]
94set_location_assignment PIN_A20 -to HEX2[1]
95set_location_assignment PIN_B19 -to HEX2[2]
96set_location_assignment PIN_A21 -to HEX2[3]
97set_location_assignment PIN_B21 -to HEX2[4]
98set_location_assignment PIN_C22 -to HEX2[5]
99set_location_assignment PIN_B22 -to HEX2[6]
100set_location_assignment PIN_A19 -to HEX2[7]
101set_location_assignment PIN_F21 -to HEX3[0]
102set_location_assignment PIN_E22 -to HEX3[1]
103set_location_assignment PIN_E21 -to HEX3[2]
104set_location_assignment PIN_C19 -to HEX3[3]
105set_location_assignment PIN_C20 -to HEX3[4]
106set_location_assignment PIN_D19 -to HEX3[5]
107set_location_assignment PIN_E17 -to HEX3[6]
108set_location_assignment PIN_D22 -to HEX3[7]
109set_location_assignment PIN_F18 -to HEX4[0]
110set_location_assignment PIN_E20 -to HEX4[1]
111set_location_assignment PIN_E19 -to HEX4[2]
112set_location_assignment PIN_J18 -to HEX4[3]
113set_location_assignment PIN_H19 -to HEX4[4]
114set_location_assignment PIN_F19 -to HEX4[5]
115set_location_assignment PIN_F20 -to HEX4[6]
116set_location_assignment PIN_F17 -to HEX4[7]
117set_location_assignment PIN_J20 -to HEX5[0]
118set_location_assignment PIN_K20 -to HEX5[1]
119set_location_assignment PIN_L18 -to HEX5[2]
120set_location_assignment PIN_N18 -to HEX5[3]
121set_location_assignment PIN_M20 -to HEX5[4]
122set_location_assignment PIN_N19 -to HEX5[5]
123set_location_assignment PIN_N20 -to HEX5[6]
124set_location_assignment PIN_L19 -to HEX5[7]
125
126#============================================================
127# KEY
128#============================================================
129set_instance_assignment -name IO_STANDARD "3.3 V Schmitt Trigger" -to KEY[0]
130set_instance_assignment -name IO_STANDARD "3.3 V Schmitt Trigger" -to KEY[1]
131set_location_assignment PIN_B8 -to KEY[0]
132set_location_assignment PIN_A7 -to KEY[1]
133
134#============================================================
135# LED
136#============================================================
137set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
138set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
139set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
140set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
141set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
142set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
143set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
144set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
145set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
146set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
147set_location_assignment PIN_A8 -to LEDR[0]
148set_location_assignment PIN_A9 -to LEDR[1]
149set_location_assignment PIN_A10 -to LEDR[2]
150set_location_assignment PIN_B10 -to LEDR[3]
151set_location_assignment PIN_D13 -to LEDR[4]
152set_location_assignment PIN_C13 -to LEDR[5]
153set_location_assignment PIN_E14 -to LEDR[6]
154set_location_assignment PIN_D14 -to LEDR[7]
155set_location_assignment PIN_A11 -to LEDR[8]
156set_location_assignment PIN_B11 -to LEDR[9]
157
158#============================================================
159# SW
160#============================================================
161set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
162set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
163set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
164set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
165set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
166set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
167set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
168set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
169set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
170set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
171set_location_assignment PIN_C10 -to SW[0]
172set_location_assignment PIN_C11 -to SW[1]
173set_location_assignment PIN_D12 -to SW[2]
174set_location_assignment PIN_C12 -to SW[3]
175set_location_assignment PIN_A12 -to SW[4]
176set_location_assignment PIN_B12 -to SW[5]
177set_location_assignment PIN_A13 -to SW[6]
178set_location_assignment PIN_A14 -to SW[7]
179set_location_assignment PIN_B14 -to SW[8]
180set_location_assignment PIN_F15 -to SW[9]
181
182#============================================================
183# GPIO, GPIO connect to GPIO Default
184#============================================================
185set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
186set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
187set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
188set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
189set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
190set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
191set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
192set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
193set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
194set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
195set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
196set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
197set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
198set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
199set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
200set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
201set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
202set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
203set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
204set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
205set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
206set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
207set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
208set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
209set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
210set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
211set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
212set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
213set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
214set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
215set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
216set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
217set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
218set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
219set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
220set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
221set_location_assignment PIN_V10 -to GPIO[0]
222set_location_assignment PIN_W10 -to GPIO[1]
223set_location_assignment PIN_V9 -to GPIO[2]
224set_location_assignment PIN_W9 -to GPIO[3]
225set_location_assignment PIN_V8 -to GPIO[4]
226set_location_assignment PIN_W8 -to GPIO[5]
227set_location_assignment PIN_V7 -to GPIO[6]
228set_location_assignment PIN_W7 -to GPIO[7]
229set_location_assignment PIN_W6 -to GPIO[8]
230set_location_assignment PIN_V5 -to GPIO[9]
231set_location_assignment PIN_W5 -to GPIO[10]
232set_location_assignment PIN_AA15 -to GPIO[11]
233set_location_assignment PIN_AA14 -to GPIO[12]
234set_location_assignment PIN_W13 -to GPIO[13]
235set_location_assignment PIN_W12 -to GPIO[14]
236set_location_assignment PIN_AB13 -to GPIO[15]
237set_location_assignment PIN_AB12 -to GPIO[16]
238set_location_assignment PIN_Y11 -to GPIO[17]
239set_location_assignment PIN_AB11 -to GPIO[18]
240set_location_assignment PIN_W11 -to GPIO[19]
241set_location_assignment PIN_AB10 -to GPIO[20]
242set_location_assignment PIN_AA10 -to GPIO[21]
243set_location_assignment PIN_AA9 -to GPIO[22]
244set_location_assignment PIN_Y8 -to GPIO[23]
245set_location_assignment PIN_AA8 -to GPIO[24]
246set_location_assignment PIN_Y7 -to GPIO[25]
247set_location_assignment PIN_AA7 -to GPIO[26]
248set_location_assignment PIN_Y6 -to GPIO[27]
249set_location_assignment PIN_AA6 -to GPIO[28]
250set_location_assignment PIN_Y5 -to GPIO[29]
251set_location_assignment PIN_AA5 -to GPIO[30]
252set_location_assignment PIN_Y4 -to GPIO[31]
253set_location_assignment PIN_AB3 -to GPIO[32]
254set_location_assignment PIN_Y3 -to GPIO[33]
255set_location_assignment PIN_AB2 -to GPIO[34]
256set_location_assignment PIN_AA2 -to GPIO[35]
257
258#============================================================
259# End of pin assignments by Terasic System Builder
260#============================================================
261
262
263set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
264set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
265set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
266set_global_assignment -name SYSTEMVERILOG_FILE riscvsingle.sv
267set_global_assignment -name VERILOG_FILE my_computer_tb.v
268set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
269set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
270set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
271set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
272set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
273set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
274set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
275set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
276set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
277set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
278set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
279set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
280set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH my_computer_tb -section_id eda_simulation
281set_global_assignment -name EDA_TEST_BENCH_NAME my_computer_tb -section_id eda_simulation
282set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id my_computer_tb
283set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME my_computer_tb -section_id my_computer_tb
284set_global_assignment -name EDA_TEST_BENCH_FILE my_computer_tb.v -section_id my_computer_tb
285set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
diff --git a/CEL_PROJECT.sdc b/CEL_PROJECT.sdc
new file mode 100644
index 0000000..7267c16
--- /dev/null
+++ b/CEL_PROJECT.sdc
@@ -0,0 +1,86 @@
1#**************************************************************
2# This .sdc file is created by Terasic Tool.
3# Users are recommended to modify this file to match users logic.
4#**************************************************************
5
6#**************************************************************
7# Create Clock
8#**************************************************************
9create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
10create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
11create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
12
13#**************************************************************
14# Create Generated Clock
15#**************************************************************
16derive_pll_clocks
17
18
19
20#**************************************************************
21# Set Clock Latency
22#**************************************************************
23
24
25
26#**************************************************************
27# Set Clock Uncertainty
28#**************************************************************
29derive_clock_uncertainty
30
31
32
33#**************************************************************
34# Set Input Delay
35#**************************************************************
36
37
38
39#**************************************************************
40# Set Output Delay
41#**************************************************************
42
43
44
45#**************************************************************
46# Set Clock Groups
47#**************************************************************
48
49
50
51#**************************************************************
52# Set False Path
53#**************************************************************
54
55
56
57#**************************************************************
58# Set Multicycle Path
59#**************************************************************
60
61
62
63#**************************************************************
64# Set Maximum Delay
65#**************************************************************
66
67
68
69#**************************************************************
70# Set Minimum Delay
71#**************************************************************
72
73
74
75#**************************************************************
76# Set Input Transition
77#**************************************************************
78
79
80
81#**************************************************************
82# Set Load
83#**************************************************************
84
85
86
diff --git a/CEL_PROJECT.v b/CEL_PROJECT.v
new file mode 100644
index 0000000..082b5de
--- /dev/null
+++ b/CEL_PROJECT.v
@@ -0,0 +1,38 @@
1module CEL_PROJECT(
2
3 //////////// CLOCK //////////
4 input ADC_CLK_10,
5 input MAX10_CLK1_50,
6 input MAX10_CLK2_50,
7
8 //////////// SEG7 //////////
9 output [7:0] HEX0,
10 output [7:0] HEX1,
11 output [7:0] HEX2,
12 output [7:0] HEX3,
13 output [7:0] HEX4,
14 output [7:0] HEX5,
15
16 //////////// KEY //////////
17 input [1:0] KEY,
18
19 //////////// LED //////////
20 output [9:0] LEDR,
21
22 //////////// SW //////////
23 input [9:0] SW,
24
25 //////////// GPIO, GPIO connect to GPIO Default //////////
26 inout [35:0] GPIO
27);
28
29
30wire [31:0] my_PC, my_rd;
31
32assign clk = ~KEY[1]; //ADC_CLK_10;
33
34my_computer U1(.clk(clk), .reset(~KEY[0]), .my_sw(SW[7:0]), .my_rd(my_rd), .my_PC(my_PC)); // Excluding comments 200+ lines of "code"
35
36assign LEDR = SW[9] ? my_PC : my_rd;
37
38endmodule
diff --git a/my_computer_tb.v b/my_computer_tb.v
new file mode 100644
index 0000000..3c37728
--- /dev/null
+++ b/my_computer_tb.v
@@ -0,0 +1,23 @@
1`timescale 1ns/1ps
2
3module my_computer_tb();
4
5 reg clk, reset;
6
7 // instantiate device to be tested
8 my_computer U1(.clk(clk), .reset(reset), .my_sw(0), .my_rd(), .my_PC());
9
10 always
11 begin
12 #5; clk <= ~clk;
13 end
14
15 initial
16 begin
17 reset <= 1; clk = 1;
18 #22; reset <= 0;
19 #1000;
20 $stop;
21 end
22
23endmodule \ No newline at end of file
diff --git a/riscvsingle.sv b/riscvsingle.sv
new file mode 100644
index 0000000..f536718
--- /dev/null
+++ b/riscvsingle.sv
@@ -0,0 +1,390 @@
1// riscvsingle.sv
2
3// RISC-V single-cycle processor
4// From Section 7.6 of Digital Design & Computer Architecture
5// 27 April 2020
6// David_Harris@hmc.edu
7// Sarah.Harris@unlv.edu
8
9// run 210
10// Expect simulator to print "Simulation succeeded"
11// when the value 25 (0x19) is written to address 100 (0x64)
12
13// Single-cycle implementation of RISC-V (RV32I)
14// User-level Instruction Set Architecture V2.2 (May 7, 2017)
15// Implements a subset of the base integer instructions:
16// lw, sw
17// add, sub, and, or, slt,
18// addi, andi, ori, slti
19// beq
20// jal
21// Exceptions, traps, and interrupts not implemented
22// little-endian memory
23
24// 31 32-bit registers x1-x31, x0 hardwired to 0
25// R-Type instructions
26// add, sub, and, or, slt
27// INSTR rd, rs1, rs2
28// Instr[31:25] = funct7 (funct7b5 & opb5 = 1 for sub, 0 for others)
29// Instr[24:20] = rs2
30// Instr[19:15] = rs1
31// Instr[14:12] = funct3
32// Instr[11:7] = rd
33// Instr[6:0] = opcode
34// I-Type Instructions
35// lw, I-type ALU (addi, andi, ori, slti)
36// lw: INSTR rd, imm(rs1)
37// I-type ALU: INSTR rd, rs1, imm (12-bit signed)
38// Instr[31:20] = imm[11:0]
39// Instr[24:20] = rs2
40// Instr[19:15] = rs1
41// Instr[14:12] = funct3
42// Instr[11:7] = rd
43// Instr[6:0] = opcode
44// S-Type Instruction
45// sw rs2, imm(rs1) (store rs2 into address specified by rs1 + immm)
46// Instr[31:25] = imm[11:5] (offset[11:5])
47// Instr[24:20] = rs2 (src)
48// Instr[19:15] = rs1 (base)
49// Instr[14:12] = funct3
50// Instr[11:7] = imm[4:0] (offset[4:0])
51// Instr[6:0] = opcode
52// B-Type Instruction
53// beq rs1, rs2, imm (PCTarget = PC + (signed imm x 2))
54// Instr[31:25] = imm[12], imm[10:5]
55// Instr[24:20] = rs2
56// Instr[19:15] = rs1
57// Instr[14:12] = funct3
58// Instr[11:7] = imm[4:1], imm[11]
59// Instr[6:0] = opcode
60// J-Type Instruction
61// jal rd, imm (signed imm is multiplied by 2 and added to PC, rd = PC+4)
62// Instr[31:12] = imm[20], imm[10:1], imm[11], imm[19:12]
63// Instr[11:7] = rd
64// Instr[6:0] = opcode
65
66// Instruction opcode funct3 funct7
67// add 0110011 000 0000000
68// sub 0110011 000 0100000
69// and 0110011 111 0000000
70// or 0110011 110 0000000
71// slt 0110011 010 0000000
72// addi 0010011 000 immediate
73// andi 0010011 111 immediate
74// ori 0010011 110 immediate
75// slti 0010011 010 immediate
76// beq 1100011 000 immediate
77// lw 0000011 010 immediate
78// sw 0100011 010 immediate
79// jal 1101111 immediate immediate
80
81
82// This part is modified by Dr.Toker
83module my_computer(input logic clk, reset,
84 input logic[ 9:0] my_sw,
85 output logic[31:0] my_rd,
86 output logic[31:0] my_PC
87);
88
89 logic [31:0] PC, Instr, ReadData, WriteData, DataAddr;
90 logic MemWrite;
91
92 // instantiate processor
93 riscvsingle rvsingle(clk, reset, PC, Instr, MemWrite, DataAddr,
94 WriteData, ReadData);
95 // program memory - ROM
96 imem imem(PC, Instr);
97
98 // data memort - RAM
99 dmem dmem(clk, MemWrite, DataAddr, WriteData, ReadData, my_sw, my_rd);
100
101 assign my_PC = PC;
102
103endmodule
104
105// =======================================================================
106// NEW STUFF ABOUT MEMORIES - MUST REVIEW FIRST
107// =======================================================================
108
109module regfile(input logic clk,
110 input logic we3,
111 input logic [ 4:0] a1, a2, a3,
112 input logic [31:0] wd3,
113 output logic [31:0] rd1, rd2);
114
115 logic [31:0] rf[31:0];
116
117 // three ported register file
118 // read two ports combinationally (A1/RD1, A2/RD2)
119 // write third port on rising edge of clock (A3/WD3/WE3)
120 // register 0 hardwired to 0
121
122 always_ff @(posedge clk)
123 if (we3) rf[a3] <= wd3;
124
125 assign rd1 = (a1 != 0) ? rf[a1] : 0;
126 assign rd2 = (a2 != 0) ? rf[a2] : 0;
127endmodule
128
129module imem(input logic [31:0] a,
130 output logic [31:0] rd);
131
132 logic [31:0] ROM[63:0];
133
134 // Initialize the program memory
135 // Simulator : ok
136 // Hardware : For FPGA ok, non-FPGA we need a 3rd party solution to program the FLASH memory (ROM)
137 initial
138 $readmemh("C:\\Users\\onur\\Desktop\\CE_Lab2\\CEL_PROJECT\\riscvtest_rom_image.txt", ROM);
139
140 assign rd = ROM[a[31:2]]; // word aligned
141endmodule
142
143// This part is modified by Dr. Toker
144module dmem(input logic clk, we,
145 input logic [31:0] a, wd,
146 output logic [31:0] rd,
147 input logic [ 7:0] my_sw,
148 output logic [31:0] my_rd);
149
150 logic [31:0] RAM[127:0];
151
152 assign rd = RAM[a[31:2]]; // word aligned
153
154 always_ff @(posedge clk)
155 begin
156 if (we) RAM[a[31:2]] <= wd;
157
158 // Used only for simulation, does not correspond to ANY hardware
159 if (we)
160 $display("Write RAM[%08x]=%08x at %t", a[31:2], wd, $time);
161 else
162 $display("Read RAM[%08x]=%08x at %t", a[31:2], rd, $time);
163
164 end
165
166 assign my_rd = RAM[my_sw[7:2]];
167
168 // Initialize the program memory
169 // Simulator : ok
170 // Hardware : For FPGA ok, non-FPGA we need a 3rd party solution to program the DATA memory (RAM)
171 initial
172 $readmemh("C:\\Users\\onur\\Desktop\\CE_Lab2\\CEL_PROJECT\\riscvtest_ram_image.txt", RAM);
173
174endmodule
175
176module flopr #(parameter WIDTH = 8)
177 (input logic clk, reset,
178 input logic [WIDTH-1:0] d,
179 output logic [WIDTH-1:0] q);
180
181 always_ff @(posedge clk, posedge reset)
182 if (reset) q <= 0;
183 else q <= d;
184endmodule
185
186// =======================================================================
187// OLD STUFF - Component Instantiation or New Combinatorial Designs
188// =======================================================================
189
190module riscvsingle(input logic clk, reset,
191 output logic [31:0] PC,
192 input logic [31:0] Instr,
193 output logic MemWrite,
194 output logic [31:0] ALUResult, WriteData,
195 input logic [31:0] ReadData);
196
197 logic ALUSrc, RegWrite, Jump, Zero;
198 logic [1:0] ResultSrc, ImmSrc;
199 logic [2:0] ALUControl;
200
201 controller c(Instr[6:0], Instr[14:12], Instr[30], Zero,
202 ResultSrc, MemWrite, PCSrc,
203 ALUSrc, RegWrite, Jump,
204 ImmSrc, ALUControl);
205 datapath dp(clk, reset, ResultSrc, PCSrc,
206 ALUSrc, RegWrite,
207 ImmSrc, ALUControl,
208 Zero, PC, Instr,
209 ALUResult, WriteData, ReadData);
210endmodule
211
212module controller(input logic [6:0] op,
213 input logic [2:0] funct3,
214 input logic funct7b5,
215 input logic Zero,
216 output logic [1:0] ResultSrc,
217 output logic MemWrite,
218 output logic PCSrc, ALUSrc,
219 output logic RegWrite, Jump,
220 output logic [1:0] ImmSrc,
221 output logic [2:0] ALUControl);
222
223 logic [1:0] ALUOp;
224 logic Branch;
225
226 maindec md(op, ResultSrc, MemWrite, Branch,
227 ALUSrc, RegWrite, Jump, ImmSrc, ALUOp);
228 aludec ad(op[5], funct3, funct7b5, ALUOp, ALUControl);
229
230 assign PCSrc = Branch & Zero | Jump;
231endmodule
232
233module maindec(input logic [6:0] op,
234 output logic [1:0] ResultSrc,
235 output logic MemWrite,
236 output logic Branch, ALUSrc,
237 output logic RegWrite, Jump,
238 output logic [1:0] ImmSrc,
239 output logic [1:0] ALUOp);
240
241 logic [10:0] controls;
242
243 assign {RegWrite, ImmSrc, ALUSrc, MemWrite,
244 ResultSrc, Branch, ALUOp, Jump} = controls;
245
246 always_comb
247 case(op)
248 // RegWrite_ImmSrc_ALUSrc_MemWrite_ResultSrc_Branch_ALUOp_Jump
249 7'b0000011: controls = 11'b1_00_1_0_01_0_00_0; // lw
250 7'b0100011: controls = 11'b0_01_1_1_00_0_00_0; // sw
251 7'b0110011: controls = 11'b1_xx_0_0_00_0_10_0; // R-type
252 7'b1100011: controls = 11'b0_10_0_0_00_1_01_0; // beq
253 7'b0010011: controls = 11'b1_00_1_0_00_0_10_0; // I-type ALU
254 7'b1101111: controls = 11'b1_11_0_0_10_0_00_1; // jal
255 default: controls = 11'bx_xx_x_x_xx_x_xx_x; // non-implemented instruction
256 endcase
257endmodule
258
259module aludec(input logic opb5,
260 input logic [2:0] funct3,
261 input logic funct7b5,
262 input logic [1:0] ALUOp,
263 output logic [2:0] ALUControl);
264
265 logic RtypeSub;
266 assign RtypeSub = funct7b5 & opb5; // TRUE for R-type subtract instruction
267
268 always_comb
269 case(ALUOp)
270 2'b00: ALUControl = 3'b000; // addition
271 2'b01: ALUControl = 3'b001; // subtraction
272 default: case(funct3) // R-type or I-type ALU
273 3'b000: if (RtypeSub)
274 ALUControl = 3'b001; // sub
275 else
276 ALUControl = 3'b000; // add, addi
277 3'b010: ALUControl = 3'b101; // slt, slti
278 3'b110: ALUControl = 3'b011; // or, ori
279 3'b111: ALUControl = 3'b010; // and, andi
280 default: ALUControl = 3'bxxx; // ???
281 endcase
282 endcase
283endmodule
284
285module datapath(input logic clk, reset,
286 input logic [1:0] ResultSrc,
287 input logic PCSrc, ALUSrc,
288 input logic RegWrite,
289 input logic [1:0] ImmSrc,
290 input logic [2:0] ALUControl,
291 output logic Zero,
292 output logic [31:0] PC,
293 input logic [31:0] Instr,
294 output logic [31:0] ALUResult, WriteData,
295 input logic [31:0] ReadData);
296
297 logic [31:0] PCNext, PCPlus4, PCTarget;
298 logic [31:0] ImmExt;
299 logic [31:0] SrcA, SrcB;
300 logic [31:0] Result;
301
302 // next PC logic
303 flopr #(32) pcreg(clk, reset, PCNext, PC);
304 adder pcadd4(PC, 32'd4, PCPlus4);
305 adder pcaddbranch(PC, ImmExt, PCTarget);
306 mux2 #(32) pcmux(PCPlus4, PCTarget, PCSrc, PCNext);
307
308 // register file logic
309 regfile rf(clk, RegWrite, Instr[19:15], Instr[24:20],
310 Instr[11:7], Result, SrcA, WriteData);
311 extend ext(Instr[31:7], ImmSrc, ImmExt);
312
313 // ALU logic
314 mux2 #(32) srcbmux(WriteData, ImmExt, ALUSrc, SrcB);
315 alu alu(SrcA, SrcB, ALUControl, ALUResult, Zero);
316 mux3 #(32) resultmux(ALUResult, ReadData, PCPlus4, ResultSrc, Result);
317endmodule
318
319
320module adder(input [31:0] a, b,
321 output [31:0] y);
322
323 assign y = a + b;
324endmodule
325
326module extend(input logic [31:7] instr,
327 input logic [1:0] immsrc,
328 output logic [31:0] immext);
329
330 always_comb
331 case(immsrc)
332 // I-type
333 2'b00: immext = {{20{instr[31]}}, instr[31:20]};
334 // S-type (stores)
335 2'b01: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]};
336 // B-type (branches)
337 2'b10: immext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
338 // J-type (jal)
339 2'b11: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
340 default: immext = 32'bx; // undefined
341 endcase
342endmodule
343
344module mux2 #(parameter WIDTH = 8)
345 (input logic [WIDTH-1:0] d0, d1,
346 input logic s,
347 output logic [WIDTH-1:0] y);
348
349 assign y = s ? d1 : d0;
350endmodule
351
352module mux3 #(parameter WIDTH = 8)
353 (input logic [WIDTH-1:0] d0, d1, d2,
354 input logic [1:0] s,
355 output logic [WIDTH-1:0] y);
356
357 assign y = s[1] ? d2 : (s[0] ? d1 : d0);
358endmodule
359
360module alu(input logic [31:0] a, b,
361 input logic [2:0] alucontrol,
362 output logic [31:0] result,
363 output logic zero);
364
365 logic [31:0] condinvb, sum;
366 logic v; // overflow
367 logic isAddSub; // true when is add or subtract operation
368
369 assign condinvb = alucontrol[0] ? ~b : b;
370 assign sum = a + condinvb + alucontrol[0];
371 assign isAddSub = ~alucontrol[2] & ~alucontrol[1] |
372 ~alucontrol[1] & alucontrol[0];
373
374 always_comb
375 case (alucontrol)
376 3'b000: result = sum; // add
377 3'b001: result = sum; // subtract
378 3'b010: result = a & b; // and
379 3'b011: result = a | b; // or
380 3'b100: result = a ^ b; // xor
381 3'b101: result = sum[31] ^ v; // slt
382 3'b110: result = a << b[4:0]; // sll
383 3'b111: result = a >> b[4:0]; // srl
384 default: result = 32'bx;
385 endcase
386
387 assign zero = (result == 32'b0);
388 assign v = ~(alucontrol[0] ^ a[31] ^ b[31]) & (a[31] ^ sum[31]) & isAddSub;
389
390endmodule
diff --git a/riscvtest.s b/riscvtest.s
new file mode 100644
index 0000000..19dc756
--- /dev/null
+++ b/riscvtest.s
@@ -0,0 +1,33 @@
1# riscvtest.s
2# Sarah.Harris@unlv.edu
3# David_Harris@hmc.edu
4# 27 Oct 2020
5#
6# Test the RISC-V processor.
7# add, sub, and, or, slt, addi, lw, sw, beq, jal
8# If successful, it should write the value 25 to address 100
9
10# RISC-V Assembly Description Address Machine Code
11main: addi x2, x0, 5 # x2 = 5 0 00500113
12 addi x3, x0, 12 # x3 = 12 4 00C00193
13 addi x7, x3, -9 # x7 = (12 - 9) = 3 8 FF718393
14 or x4, x7, x2 # x4 = (3 OR 5) = 7 C 0023E233
15 and x5, x3, x4 # x5 = (12 AND 7) = 4 10 0041F2B3
16 add x5, x5, x4 # x5 = (4 + 7) = 11 14 004282B3
17 beq x5, x7, end # shouldn't be taken 18 02728863
18 slt x4, x3, x4 # x4 = (12 < 7) = 0 1C 0041A233
19 beq x4, x0, around # should be taken 20 00020463
20 addi x5, x0, 0 # shouldn't happen 24 00000293
21around: slt x4, x7, x2 # x4 = (3 < 5) = 1 28 0023A233
22 add x7, x4, x5 # x7 = (1 + 11) = 12 2C 005203B3
23 sub x7, x7, x2 # x7 = (12 - 5) = 7 30 402383B3
24 sw x7, 84(x3) # [96] = 7 34 0471AA23
25 lw x2, 96(x0) # x2 = [96] = 7 38 06002103
26 add x9, x2, x5 # x9 = (7 + 11) = 18 3C 005104B3
27 jal x3, end # jump to end, x3 = 0x44 40 008001EF
28 addi x2, x0, 1 # shouldn't happen 44 00100113
29end: add x2, x2, x9 # x2 = (7 + 18) = 25 48 00910133
30 sw x2, 0x20(x3) # mem[100] = 25 4C 0221A023
31done: beq x2, x2, done # infinite loop 50 00210063
32
33 \ No newline at end of file
diff --git a/riscvtest_ram_image.txt b/riscvtest_ram_image.txt
new file mode 100644
index 0000000..9e78f77
--- /dev/null
+++ b/riscvtest_ram_image.txt
@@ -0,0 +1,1024 @@
100000000
200000001
300000002
400000003
500000004
600000005
700000006
800000007
900000008
1000000009
110000000A
120000000B
130000000C
140000000D
150000000E
160000000F
1700000010
1800000011
1900000012
2000000013
2100000014
2200000015
2300000016
2400000017
2500000018
2600000019
270000001A
280000001B
290000001C
300000001D
310000001E
320000001F
3300000020
3400000021
3500000022
3600000023
3700000024
3800000025
3900000026
4000000027
4100000028
4200000029
430000002A
440000002B
450000002C
460000002D
470000002E
480000002F
4900000030
5000000031
5100000032
5200000033
5300000034
5400000035
5500000036
5600000037
5700000038
5800000039
590000003A
600000003B
610000003C
620000003D
630000003E
640000003F
6500000040
6600000041
6700000042
6800000043
6900000044
7000000045
7100000046
7200000047
7300000048
7400000049
750000004A
760000004B
770000004C
780000004D
790000004E
800000004F
8100000050
8200000051
8300000052
8400000053
8500000054
8600000055
8700000056
8800000057
8900000058
9000000059
910000005A
920000005B
930000005C
940000005D
950000005E
960000005F
9700000060
9800000061
9900000062
10000000063
10100000064
10200000065
10300000066
10400000067
10500000068
10600000069
1070000006A
1080000006B
1090000006C
1100000006D
1110000006E
1120000006F
11300000070
11400000071
11500000072
11600000073
11700000074
11800000075
11900000076
12000000077
12100000078
12200000079
1230000007A
1240000007B
1250000007C
1260000007D
1270000007E
1280000007F
12900000080
13000000081
13100000082
13200000083
13300000084
13400000085
13500000086
13600000087
13700000088
13800000089
1390000008A
1400000008B
1410000008C
1420000008D
1430000008E
1440000008F
14500000090
14600000091
14700000092
14800000093
14900000094
15000000095
15100000096
15200000097
15300000098
15400000099
1550000009A
1560000009B
1570000009C
1580000009D
1590000009E
1600000009F
161000000A0
162000000A1
163000000A2
164000000A3
165000000A4
166000000A5
167000000A6
168000000A7
169000000A8
170000000A9
171000000AA
172000000AB
173000000AC
174000000AD
175000000AE
176000000AF
177000000B0
178000000B1
179000000B2
180000000B3
181000000B4
182000000B5
183000000B6
184000000B7
185000000B8
186000000B9
187000000BA
188000000BB
189000000BC
190000000BD
191000000BE
192000000BF
193000000C0
194000000C1
195000000C2
196000000C3
197000000C4
198000000C5
199000000C6
200000000C7
201000000C8
202000000C9
203000000CA
204000000CB
205000000CC
206000000CD
207000000CE
208000000CF
209000000D0
210000000D1
211000000D2
212000000D3
213000000D4
214000000D5
215000000D6
216000000D7
217000000D8
218000000D9
219000000DA
220000000DB
221000000DC
222000000DD
223000000DE
224000000DF
225000000E0
226000000E1
227000000E2
228000000E3
229000000E4
230000000E5
231000000E6
232000000E7
233000000E8
234000000E9
235000000EA
236000000EB
237000000EC
238000000ED
239000000EE
240000000EF
241000000F0
242000000F1
243000000F2
244000000F3
245000000F4
246000000F5
247000000F6
248000000F7
249000000F8
250000000F9
251000000FA
252000000FB
253000000FC
254000000FD
255000000FE
256000000FF
25700000100
25800000101
25900000102
26000000103
26100000104
26200000105
26300000106
26400000107
26500000108
26600000109
2670000010A
2680000010B
2690000010C
2700000010D
2710000010E
2720000010F
27300000110
27400000111
27500000112
27600000113
27700000114
27800000115
27900000116
28000000117
28100000118
28200000119
2830000011A
2840000011B
2850000011C
2860000011D
2870000011E
2880000011F
28900000120
29000000121
29100000122
29200000123
29300000124
29400000125
29500000126
29600000127
29700000128
29800000129
2990000012A
3000000012B
3010000012C
3020000012D
3030000012E
3040000012F
30500000130
30600000131
30700000132
30800000133
30900000134
31000000135
31100000136
31200000137
31300000138
31400000139
3150000013A
3160000013B
3170000013C
3180000013D
3190000013E
3200000013F
32100000140
32200000141
32300000142
32400000143
32500000144
32600000145
32700000146
32800000147
32900000148
33000000149
3310000014A
3320000014B
3330000014C
3340000014D
3350000014E
3360000014F
33700000150
33800000151
33900000152
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34100000154
34200000155
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34600000159
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3480000015B
3490000015C
3500000015D
3510000015E
3520000015F
35300000160
35400000161
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35600000163
35700000164
35800000165
35900000166
36000000167
36100000168
36200000169
3630000016A
3640000016B
3650000016C
3660000016D
3670000016E
3680000016F
36900000170
37000000171
37100000172
37200000173
37300000174
37400000175
37500000176
37600000177
37700000178
37800000179
3790000017A
3800000017B
3810000017C
3820000017D
3830000017E
3840000017F
38500000180
38600000181
38700000182
38800000183
38900000184
39000000185
39100000186
39200000187
39300000188
39400000189
3950000018A
3960000018B
3970000018C
3980000018D
3990000018E
4000000018F
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40200000191
40300000192
40400000193
40500000194
40600000195
40700000196
40800000197
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41000000199
4110000019A
4120000019B
4130000019C
4140000019D
4150000019E
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420000001A3
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450000001C1
451000001C2
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460000001CB
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490000001E9
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500000001F3
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55000000225
55100000226
55200000227
55300000228
55400000229
5550000022A
5560000022B
5570000022C
5580000022D
5590000022E
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56100000230
56200000231
56300000232
56400000233
56500000234
56600000235
56700000236
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56900000238
57000000239
5710000023A
5720000023B
5730000023C
5740000023D
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724000002D3
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728000002D7
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732000002DB
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735000002DE
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741000002E4
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748000002EB
749000002EC
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751000002EE
752000002EF
753000002F0
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755000002F2
756000002F3
757000002F4
758000002F5
759000002F6
760000002F7
761000002F8
762000002F9
763000002FA
764000002FB
765000002FC
766000002FD
767000002FE
768000002FF
76900000300
77000000301
77100000302
77200000303
77300000304
77400000305
77500000306
77600000307
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7810000030C
7820000030D
7830000030E
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78700000312
78800000313
78900000314
79000000315
79100000316
79200000317
79300000318
79400000319
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7960000031B
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7990000031E
8000000031F
80100000320
80200000321
80300000322
80400000323
80500000324
80600000325
80700000326
80800000327
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81000000329
8110000032A
8120000032B
8130000032C
8140000032D
8150000032E
8160000032F
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82100000334
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82600000339
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8320000033F
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83800000345
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84200000349
8430000034A
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85300000354
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87200000367
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88300000372
88400000373
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8920000037B
8930000037C
8940000037D
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90000000383
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90300000386
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9080000038B
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9110000038E
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940000003AB
941000003AC
942000003AD
943000003AE
944000003AF
945000003B0
946000003B1
947000003B2
948000003B3
949000003B4
950000003B5
951000003B6
952000003B7
953000003B8
954000003B9
955000003BA
956000003BB
957000003BC
958000003BD
959000003BE
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961000003C0
962000003C1
963000003C2
964000003C3
965000003C4
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969000003C8
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972000003CB
973000003CC
974000003CD
975000003CE
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978000003D1
979000003D2
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981000003D4
982000003D5
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984000003D7
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998000003E5
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1000000003E7
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1004000003EB
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1007000003EE
1008000003EF
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1011000003F2
1012000003F3
1013000003F4
1014000003F5
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1016000003F7
1017000003F8
1018000003F9
1019000003FA
1020000003FB
1021000003FC
1022000003FD
1023000003FE
1024000003FF \ No newline at end of file
diff --git a/riscvtest_rom_image.txt b/riscvtest_rom_image.txt
new file mode 100644
index 0000000..43e784b
--- /dev/null
+++ b/riscvtest_rom_image.txt
@@ -0,0 +1,21 @@
100500113
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40023E233
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80041A233
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13402383B3
140471AA23
1506002103
16005104B3
17008001EF
1800100113
1900910133
200221A023
2100210063 \ No newline at end of file
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-03 04:54:13 +0000