diff options
| author | vin <git@vineetk.net> | 2025-03-10 15:41:13 -0400 |
|---|---|---|
| committer | vin <git@vineetk.net> | 2025-03-10 15:41:13 -0400 |
| commit | f697bf76970fc1d264d52afd7e0e28d64f209e82 (patch) | |
| tree | 08f56d8219b7a14382a6ab9b2227898e01424450 /CEL_PROJECT.sdc | |
initial payload
Diffstat (limited to 'CEL_PROJECT.sdc')
| -rw-r--r-- | CEL_PROJECT.sdc | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/CEL_PROJECT.sdc b/CEL_PROJECT.sdc new file mode 100644 index 0000000..7267c16 --- /dev/null +++ b/CEL_PROJECT.sdc | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | #************************************************************** | ||
| 2 | # This .sdc file is created by Terasic Tool. | ||
| 3 | # Users are recommended to modify this file to match users logic. | ||
| 4 | #************************************************************** | ||
| 5 | |||
| 6 | #************************************************************** | ||
| 7 | # Create Clock | ||
| 8 | #************************************************************** | ||
| 9 | create_clock -period "10.0 MHz" [get_ports ADC_CLK_10] | ||
| 10 | create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50] | ||
| 11 | create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50] | ||
| 12 | |||
| 13 | #************************************************************** | ||
| 14 | # Create Generated Clock | ||
| 15 | #************************************************************** | ||
| 16 | derive_pll_clocks | ||
| 17 | |||
| 18 | |||
| 19 | |||
| 20 | #************************************************************** | ||
| 21 | # Set Clock Latency | ||
| 22 | #************************************************************** | ||
| 23 | |||
| 24 | |||
| 25 | |||
| 26 | #************************************************************** | ||
| 27 | # Set Clock Uncertainty | ||
| 28 | #************************************************************** | ||
| 29 | derive_clock_uncertainty | ||
| 30 | |||
| 31 | |||
| 32 | |||
| 33 | #************************************************************** | ||
| 34 | # Set Input Delay | ||
| 35 | #************************************************************** | ||
| 36 | |||
| 37 | |||
| 38 | |||
| 39 | #************************************************************** | ||
| 40 | # Set Output Delay | ||
| 41 | #************************************************************** | ||
| 42 | |||
| 43 | |||
| 44 | |||
| 45 | #************************************************************** | ||
| 46 | # Set Clock Groups | ||
| 47 | #************************************************************** | ||
| 48 | |||
| 49 | |||
| 50 | |||
| 51 | #************************************************************** | ||
| 52 | # Set False Path | ||
| 53 | #************************************************************** | ||
| 54 | |||
| 55 | |||
| 56 | |||
| 57 | #************************************************************** | ||
| 58 | # Set Multicycle Path | ||
| 59 | #************************************************************** | ||
| 60 | |||
| 61 | |||
| 62 | |||
| 63 | #************************************************************** | ||
| 64 | # Set Maximum Delay | ||
| 65 | #************************************************************** | ||
| 66 | |||
| 67 | |||
| 68 | |||
| 69 | #************************************************************** | ||
| 70 | # Set Minimum Delay | ||
| 71 | #************************************************************** | ||
| 72 | |||
| 73 | |||
| 74 | |||
| 75 | #************************************************************** | ||
| 76 | # Set Input Transition | ||
| 77 | #************************************************************** | ||
| 78 | |||
| 79 | |||
| 80 | |||
| 81 | #************************************************************** | ||
| 82 | # Set Load | ||
| 83 | #************************************************************** | ||
| 84 | |||
| 85 | |||
| 86 | |||