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authorvin <git@vineetk.net>2025-03-10 15:41:13 -0400
committervin <git@vineetk.net>2025-03-10 15:41:13 -0400
commitf697bf76970fc1d264d52afd7e0e28d64f209e82 (patch)
tree08f56d8219b7a14382a6ab9b2227898e01424450 /my_computer_tb.v
initial payload
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1`timescale 1ns/1ps
2
3module my_computer_tb();
4
5 reg clk, reset;
6
7 // instantiate device to be tested
8 my_computer U1(.clk(clk), .reset(reset), .my_sw(0), .my_rd(), .my_PC());
9
10 always
11 begin
12 #5; clk <= ~clk;
13 end
14
15 initial
16 begin
17 reset <= 1; clk = 1;
18 #22; reset <= 0;
19 #1000;
20 $stop;
21 end
22
23endmodule \ No newline at end of file