1 files changed, 10 insertions, 1 deletions

diff --git a/riscvsingle.sv b/riscvsingle.sv
index e2c1baa..fc9c830 100644
--- a/riscvsingle.sv
+++ b/riscvsingle.sv
@@ -229,7 +229,16 @@ module controller(input  logic [6:0] op,
              ALUSrc, RegWrite, Jump, ImmSrc, ALUOp);

   aludec  ad(op[5], funct3, funct7b5, ALUOp, ALUControl);

 

-  assign PCSrc = Branch & Zero | Jump;

+//  assign PCSrc = Branch & Zero | Jump;

+  always_comb

+    if (Branch)

+       case (funct3)

+         3'b000: PCSrc = Zero;

+         3'b001: PCSrc = ~Zero;

+         default: PCSrc = 1'bx;

+       endcase

+    else

+      PCSrc = Jump;

 endmodule

 

 module maindec(input  logic [6:0] op,