diff options
| author | vin <git@vineetk.net> | 2024-07-04 14:17:40 -0400 |
|---|---|---|
| committer | vin <git@vineetk.net> | 2024-07-04 14:17:40 -0400 |
| commit | 4ccf9f5cee97c8c2191660a5632ab2da60757f97 (patch) | |
| tree | fd7c3668d904c3c9024401c396e9ca905d932971 | |
| parent | c4fc40a036293a8f5899800ad3ecb1d24ba77bc4 (diff) | |
add preliminary implementation of the unofficial opcodes
| -rw-r--r-- | cpu.c | 91 | ||||
| -rw-r--r-- | cpu.h | 2 | ||||
| -rw-r--r-- | opcodes.h | 106 |
3 files changed, 111 insertions, 88 deletions
| @@ -128,8 +128,8 @@ opcode_mem(enum addressing_mode mode) | |||
| 128 | break; | 128 | break; |
| 129 | case AM_REL: | 129 | case AM_REL: |
| 130 | val = arg + regs.pc; | 130 | val = arg + regs.pc; |
| 131 | if ((regs.pc + 1) & 0xFF00 != val & 0xFF00) | 131 | if (((regs.pc + 1) & 0xFF00) != (val & 0xFF00)) |
| 132 | page_crossed = true; | 132 | val -= 0x0100; |
| 133 | break; | 133 | break; |
| 134 | case AM_IMM: | 134 | case AM_IMM: |
| 135 | case AM_ABS: | 135 | case AM_ABS: |
| @@ -703,133 +703,158 @@ TYA(uint16_t arg) | |||
| 703 | void | 703 | void |
| 704 | AAC(uint16_t arg) | 704 | AAC(uint16_t arg) |
| 705 | { | 705 | { |
| 706 | NOP(0); | 706 | AND(arg); |
| 707 | |||
| 708 | regs.status.carry = regs.status.negative; | ||
| 707 | } | 709 | } |
| 708 | 710 | ||
| 709 | void | 711 | void |
| 710 | AAX(uint16_t arg) | 712 | SAX(uint16_t arg) |
| 711 | { | 713 | { |
| 712 | NOP(0); | 714 | uint8_t tmp = regs.x & regs.a; |
| 715 | memwrite(arg, tmp); | ||
| 713 | } | 716 | } |
| 714 | 717 | ||
| 715 | void | 718 | void |
| 716 | ARR(uint16_t arg) | 719 | ARR(uint16_t arg) |
| 717 | { | 720 | { |
| 718 | NOP(0); | 721 | uint8_t tmp = arg & regs.a; |
| 722 | |||
| 723 | AND(arg); | ||
| 724 | ROR_acc(0); | ||
| 725 | |||
| 726 | if ((tmp & (1 << 5)) != 0 && (tmp & (1 << 6)) != 0) | ||
| 727 | SEC(0), CLV(0); | ||
| 728 | else if ((tmp & (1 << 5)) == 0 && (tmp & (1 << 6)) == 0) | ||
| 729 | CLC(0), CLV(0); | ||
| 730 | else if ((tmp & (1 << 5)) != 0) | ||
| 731 | CLC(0), regs.status.overflow = 1; | ||
| 732 | else if ((tmp & (1 << 6)) != 0) | ||
| 733 | SEC(0), regs.status.overflow = 1; | ||
| 719 | } | 734 | } |
| 720 | 735 | ||
| 721 | void | 736 | void |
| 722 | ASR(uint16_t arg) | 737 | ASR(uint16_t arg) |
| 723 | { | 738 | { |
| 724 | NOP(0); | 739 | AND(arg); |
| 740 | LSR_acc(0); | ||
| 725 | } | 741 | } |
| 726 | 742 | ||
| 727 | void | 743 | void |
| 728 | ATX(uint16_t arg) | 744 | ATX(uint16_t arg) |
| 729 | { | 745 | { |
| 730 | NOP(0); | 746 | AND(arg); |
| 747 | TAX(0); | ||
| 731 | } | 748 | } |
| 732 | 749 | ||
| 733 | void | 750 | void |
| 734 | AXA(uint16_t arg) | 751 | AXA(uint16_t arg) |
| 735 | { | 752 | { |
| 736 | NOP(0); | 753 | uint8_t tmp = regs.x & regs.a & 7; |
| 754 | memwrite(arg, tmp); | ||
| 737 | } | 755 | } |
| 738 | 756 | ||
| 739 | void | 757 | void |
| 740 | AXS(uint16_t arg) | 758 | AXS(uint16_t arg) |
| 741 | { | 759 | { |
| 742 | NOP(0); | 760 | regs.x &= regs.a; |
| 761 | regs.x -= arg; | ||
| 762 | |||
| 763 | regs.status.carry = arg <= regs.x; | ||
| 764 | STATUS_UPDATE_NZ(regs.x); | ||
| 743 | } | 765 | } |
| 744 | 766 | ||
| 745 | void | 767 | void |
| 746 | DCP(uint16_t arg) | 768 | DCP(uint16_t arg) |
| 747 | { | 769 | { |
| 748 | NOP(0); | 770 | uint8_t tmp = peek(arg) - 1; |
| 749 | } | 771 | memwrite(arg, tmp); |
| 750 | 772 | ||
| 751 | void | 773 | regs.status.carry = tmp <= regs.a; |
| 752 | DOP(uint16_t arg) | 774 | STATUS_UPDATE_NZ(tmp); |
| 753 | { | ||
| 754 | NOP(0); | ||
| 755 | } | 775 | } |
| 756 | 776 | ||
| 757 | void | 777 | void |
| 758 | ISC(uint16_t arg) | 778 | ISC(uint16_t arg) |
| 759 | { | 779 | { |
| 760 | NOP(0); | 780 | INC(arg); |
| 781 | SBC(peek(arg)); | ||
| 761 | } | 782 | } |
| 762 | 783 | ||
| 763 | void | 784 | void |
| 764 | KIL(uint16_t arg) | 785 | KIL(uint16_t arg) |
| 765 | { | 786 | { |
| 787 | /* TODO: figure out how to stop interpret(), I guess with global bool */ | ||
| 766 | NOP(0); | 788 | NOP(0); |
| 767 | } | 789 | } |
| 768 | 790 | ||
| 769 | void | 791 | void |
| 770 | LAR(uint16_t arg) | 792 | LAR(uint16_t arg) |
| 771 | { | 793 | { |
| 772 | NOP(0); | 794 | regs.a = regs.x = regs.sp = regs.a & regs.sp; |
| 795 | |||
| 796 | STATUS_UPDATE_NZ(regs.a); | ||
| 773 | } | 797 | } |
| 774 | 798 | ||
| 775 | void | 799 | void |
| 776 | LAX(uint16_t arg) | 800 | LAX(uint16_t arg) |
| 777 | { | 801 | { |
| 778 | NOP(0); | 802 | LDA(arg); |
| 803 | LDX(arg); | ||
| 779 | } | 804 | } |
| 780 | 805 | ||
| 781 | void | 806 | void |
| 782 | RLA(uint16_t arg) | 807 | RLA(uint16_t arg) |
| 783 | { | 808 | { |
| 784 | NOP(0); | 809 | ROL(arg); |
| 810 | AND(arg); | ||
| 785 | } | 811 | } |
| 786 | 812 | ||
| 787 | void | 813 | void |
| 788 | RRA(uint16_t arg) | 814 | RRA(uint16_t arg) |
| 789 | { | 815 | { |
| 790 | NOP(0); | 816 | ROR(arg); |
| 817 | ADC(peek(arg)); | ||
| 791 | } | 818 | } |
| 792 | 819 | ||
| 793 | void | 820 | void |
| 794 | SLO(uint16_t arg) | 821 | SLO(uint16_t arg) |
| 795 | { | 822 | { |
| 796 | NOP(0); | 823 | ASL(arg); |
| 824 | ORA(arg); | ||
| 797 | } | 825 | } |
| 798 | 826 | ||
| 799 | void | 827 | void |
| 800 | SRE(uint16_t arg) | 828 | SRE(uint16_t arg) |
| 801 | { | 829 | { |
| 802 | NOP(0); | 830 | LSR(arg); |
| 831 | EOR(arg); | ||
| 803 | } | 832 | } |
| 804 | 833 | ||
| 805 | void | 834 | void |
| 806 | SXA(uint16_t arg) | 835 | SXA(uint16_t arg) |
| 807 | { | 836 | { |
| 808 | NOP(0); | 837 | memwrite(arg, regs.x & ((arg & 0xFF00) + 1)); |
| 809 | } | 838 | } |
| 810 | 839 | ||
| 811 | void | 840 | void |
| 812 | SYA(uint16_t arg) | 841 | SYA(uint16_t arg) |
| 813 | { | 842 | { |
| 814 | NOP(0); | 843 | memwrite(arg, regs.x & ((arg & 0xFF00) + 1)); |
| 815 | } | ||
| 816 | |||
| 817 | void | ||
| 818 | TOP(uint16_t arg) | ||
| 819 | { | ||
| 820 | NOP(0); | ||
| 821 | } | 844 | } |
| 822 | 845 | ||
| 823 | void | 846 | void |
| 824 | XAA(uint16_t arg) | 847 | XAA(uint16_t arg) |
| 825 | { | 848 | { |
| 849 | /* TODO: apparently the exact operation is unknown */ | ||
| 826 | NOP(0); | 850 | NOP(0); |
| 827 | } | 851 | } |
| 828 | 852 | ||
| 829 | void | 853 | void |
| 830 | XAS(uint16_t arg) | 854 | XAS(uint16_t arg) |
| 831 | { | 855 | { |
| 832 | NOP(0); | 856 | regs.sp = regs.a & regs.x; |
| 857 | memwrite(arg, regs.sp & ((arg & 0xFF00) + 1)); | ||
| 833 | } | 858 | } |
| 834 | 859 | ||
| 835 | static void | 860 | static void |
| @@ -877,8 +902,6 @@ interpret(void) | |||
| 877 | printf("$%02X,Y", arg); | 902 | printf("$%02X,Y", arg); |
| 878 | break; | 903 | break; |
| 879 | case AM_REL: | 904 | case AM_REL: |
| 880 | printf("$%04X", regs.pc + arg); | ||
| 881 | break; | ||
| 882 | case AM_ABS: | 905 | case AM_ABS: |
| 883 | printf("$%04X", arg); | 906 | printf("$%04X", arg); |
| 884 | break; | 907 | break; |
| @@ -64,7 +64,7 @@ void TYA(uint16_t arg); | |||
| 64 | 64 | ||
| 65 | /* UNOFFICIAL OPCODES */ | 65 | /* UNOFFICIAL OPCODES */ |
| 66 | void AAC(uint16_t arg); | 66 | void AAC(uint16_t arg); |
| 67 | void AAX(uint16_t arg); | 67 | void SAX(uint16_t arg); |
| 68 | void ARR(uint16_t arg); | 68 | void ARR(uint16_t arg); |
| 69 | void ASR(uint16_t arg); | 69 | void ASR(uint16_t arg); |
| 70 | void ATX(uint16_t arg); | 70 | void ATX(uint16_t arg); |
| @@ -189,23 +189,23 @@ struct opcode opcodes[0x100] = { | |||
| 189 | /* unofficial opcodes: https://www.nesdev.org/undocumented_opcodes.txt */ | 189 | /* unofficial opcodes: https://www.nesdev.org/undocumented_opcodes.txt */ |
| 190 | [0x0B] = { "AAC", AAC, 2, 2, false, false, false, true, AM_IMM }, | 190 | [0x0B] = { "AAC", AAC, 2, 2, false, false, false, true, AM_IMM }, |
| 191 | [0x2B] = { "AAC", AAC, 2, 2, false, false, false, true, AM_IMM }, | 191 | [0x2B] = { "AAC", AAC, 2, 2, false, false, false, true, AM_IMM }, |
| 192 | [0x87] = { "AAX", AAX, 2, 3, false, false, false, true, AM_ZP }, | 192 | [0x87] = { "SAX", SAX, 2, 3, false, true, false, true, AM_ZP }, |
| 193 | [0x97] = { "AAX", AAX, 2, 4, false, false, false, true, AM_ZP_Y }, | 193 | [0x97] = { "SAX", SAX, 2, 4, false, true, false, true, AM_ZP_Y }, |
| 194 | [0x83] = { "AAX", AAX, 2, 6, false, false, false, true, AM_IND_X }, | 194 | [0x83] = { "SAX", SAX, 2, 6, false, true, false, true, AM_IND_X }, |
| 195 | [0x8F] = { "AAX", AAX, 3, 4, false, false, false, true, AM_ABS }, | 195 | [0x8F] = { "SAX", SAX, 3, 4, false, true, false, true, AM_ABS }, |
| 196 | [0x6B] = { "ARR", ARR, 2, 2, false, false, false, true, AM_IMM }, | 196 | [0x6B] = { "ARR", ARR, 2, 2, false, false, false, true, AM_IMM }, |
| 197 | [0x4B] = { "ASR", ASR, 2, 2, false, false, false, true, AM_IMM }, | 197 | [0x4B] = { "ASR", ASR, 2, 2, false, false, false, true, AM_IMM }, |
| 198 | [0xAB] = { "ATX", ATX, 2, 2, false, false, false, true, AM_IMM }, | 198 | [0xAB] = { "ATX", ATX, 2, 2, false, false, false, true, AM_IMM }, |
| 199 | [0x9F] = { "AXA", AXA, 3, 5, false, false, false, true, AM_ABS_Y }, | 199 | [0x9F] = { "AXA", AXA, 3, 5, false, true, false, true, AM_ABS_Y }, |
| 200 | [0x93] = { "AXA", AXA, 2, 6, false, false, false, true, AM_IND_Y }, | 200 | [0x93] = { "AXA", AXA, 2, 6, false, true, false, true, AM_IND_Y }, |
| 201 | [0xCB] = { "AXS", AXS, 2, 2, false, false, false, true, AM_IMM }, | 201 | [0xCB] = { "AXS", AXS, 2, 2, false, false, false, true, AM_IMM }, |
| 202 | [0xC7] = { "DCP", DCP, 2, 5, false, false, false, true, AM_ZP }, | 202 | [0xC7] = { "DCP", DCP, 2, 5, false, true, false, true, AM_ZP }, |
| 203 | [0xD7] = { "DCP", DCP, 2, 6, false, false, false, true, AM_ZP_X }, | 203 | [0xD7] = { "DCP", DCP, 2, 6, false, true, false, true, AM_ZP_X }, |
| 204 | [0xCF] = { "DCP", DCP, 3, 6, false, false, false, true, AM_ABS }, | 204 | [0xCF] = { "DCP", DCP, 3, 6, false, true, false, true, AM_ABS }, |
| 205 | [0xDF] = { "DCP", DCP, 3, 7, false, false, false, true, AM_ABS_X }, | 205 | [0xDF] = { "DCP", DCP, 3, 7, false, true, false, true, AM_ABS_X }, |
| 206 | [0xDB] = { "DCP", DCP, 3, 7, false, false, false, true, AM_ABS_Y }, | 206 | [0xDB] = { "DCP", DCP, 3, 7, false, true, false, true, AM_ABS_Y }, |
| 207 | [0xC3] = { "DCP", DCP, 2, 8, false, false, false, true, AM_IND_X }, | 207 | [0xC3] = { "DCP", DCP, 2, 8, false, true, false, true, AM_IND_X }, |
| 208 | [0xD3] = { "DCP", DCP, 2, 8, false, false, false, true, AM_IND_Y }, | 208 | [0xD3] = { "DCP", DCP, 2, 8, false, true, false, true, AM_IND_Y }, |
| 209 | [0x04] = { "NOP", NOP, 2, 3, true, false, false, true, AM_ZP }, | 209 | [0x04] = { "NOP", NOP, 2, 3, true, false, false, true, AM_ZP }, |
| 210 | [0x14] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, | 210 | [0x14] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, |
| 211 | [0x34] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, | 211 | [0x34] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, |
| @@ -217,9 +217,9 @@ struct opcode opcodes[0x100] = { | |||
| 217 | [0x82] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | 217 | [0x82] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, |
| 218 | [0x89] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | 218 | [0x89] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, |
| 219 | [0xC2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | 219 | [0xC2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, |
| 220 | [0xD4] = { "NOP", NOP, 2, 4, false, false, false, true, AM_ZP_X }, | 220 | [0xD4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, |
| 221 | [0xE2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, | 221 | [0xE2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM }, |
| 222 | [0xF4] = { "NOP", NOP, 2, 4, false, false, false, true, AM_ZP_X }, | 222 | [0xF4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X }, |
| 223 | [0xE7] = { "ISC", ISC, 2, 5, false, false, false, true, AM_ZP }, | 223 | [0xE7] = { "ISC", ISC, 2, 5, false, false, false, true, AM_ZP }, |
| 224 | [0xF7] = { "ISC", ISC, 2, 6, false, false, false, true, AM_ZP_X }, | 224 | [0xF7] = { "ISC", ISC, 2, 6, false, false, false, true, AM_ZP_X }, |
| 225 | [0xEF] = { "ISC", ISC, 3, 6, false, false, false, true, AM_ABS }, | 225 | [0xEF] = { "ISC", ISC, 3, 6, false, false, false, true, AM_ABS }, |
| @@ -239,50 +239,50 @@ struct opcode opcodes[0x100] = { | |||
| 239 | [0xB2] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | 239 | [0xB2] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, |
| 240 | [0xD2] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | 240 | [0xD2] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, |
| 241 | [0xF2] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, | 241 | [0xF2] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE }, |
| 242 | [0xBB] = { "LAR", LAR, 3, 4, false, false, true, true, AM_ABS_Y }, | 242 | [0xBB] = { "LAR", LAR, 3, 4, true, false, true, true, AM_ABS_Y }, |
| 243 | [0xA7] = { "LAX", LAX, 2, 3, false, false, false, true, AM_ZP }, | 243 | [0xA7] = { "LAX", LAX, 2, 3, true, false, false, true, AM_ZP }, |
| 244 | [0xB7] = { "LAX", LAX, 2, 4, false, false, false, true, AM_ZP_Y }, | 244 | [0xB7] = { "LAX", LAX, 2, 4, true, false, false, true, AM_ZP_Y }, |
| 245 | [0xAF] = { "LAX", LAX, 3, 4, false, false, false, true, AM_ABS }, | 245 | [0xAF] = { "LAX", LAX, 3, 4, true, false, false, true, AM_ABS }, |
| 246 | [0xBF] = { "LAX", LAX, 3, 4, false, false, true, true, AM_ABS_Y }, | 246 | [0xBF] = { "LAX", LAX, 3, 4, true, false, true, true, AM_ABS_Y }, |
| 247 | [0xA3] = { "LAX", LAX, 2, 6, false, false, false, true, AM_IND_X }, | 247 | [0xA3] = { "LAX", LAX, 2, 6, true, false, false, true, AM_IND_X }, |
| 248 | [0xB3] = { "LAX", LAX, 2, 5, false, false, true, true, AM_IND_Y }, | 248 | [0xB3] = { "LAX", LAX, 2, 5, true, false, true, true, AM_IND_Y }, |
| 249 | [0x1A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | 249 | [0x1A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, |
| 250 | [0x3A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | 250 | [0x3A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, |
| 251 | [0x5A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | 251 | [0x5A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, |
| 252 | [0x7A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | 252 | [0x7A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, |
| 253 | [0xDA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | 253 | [0xDA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, |
| 254 | [0xFA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, | 254 | [0xFA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE }, |
| 255 | [0x27] = { "RLA", RLA, 2, 5, false, false, false, true, AM_ZP }, | 255 | [0x27] = { "RLA", RLA, 2, 5, true, true, false, true, AM_ZP }, |
| 256 | [0x37] = { "RLA", RLA, 2, 6, false, false, false, true, AM_ZP_X }, | 256 | [0x37] = { "RLA", RLA, 2, 6, true, true, false, true, AM_ZP_X }, |
| 257 | [0x2F] = { "RLA", RLA, 3, 6, false, false, false, true, AM_ABS }, | 257 | [0x2F] = { "RLA", RLA, 3, 6, true, true, false, true, AM_ABS }, |
| 258 | [0x3F] = { "RLA", RLA, 3, 7, false, false, false, true, AM_ABS_X }, | 258 | [0x3F] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_X }, |
| 259 | [0x3B] = { "RLA", RLA, 3, 7, false, false, false, true, AM_ABS_Y }, | 259 | [0x3B] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_Y }, |
| 260 | [0x23] = { "RLA", RLA, 2, 8, false, false, false, true, AM_IND_X }, | 260 | [0x23] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_X }, |
| 261 | [0x33] = { "RLA", RLA, 2, 8, false, false, false, true, AM_IND_Y }, | 261 | [0x33] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_Y }, |
| 262 | [0x67] = { "RRA", RRA, 2, 5, false, false, false, true, AM_ZP }, | 262 | [0x67] = { "RRA", RRA, 2, 5, true, true, false, true, AM_ZP }, |
| 263 | [0x77] = { "RRA", RRA, 2, 6, false, false, false, true, AM_ZP_X }, | 263 | [0x77] = { "RRA", RRA, 2, 6, true, true, false, true, AM_ZP_X }, |
| 264 | [0x6F] = { "RRA", RRA, 3, 6, false, false, false, true, AM_ABS }, | 264 | [0x6F] = { "RRA", RRA, 3, 6, true, true, false, true, AM_ABS }, |
| 265 | [0x7F] = { "RRA", RRA, 3, 7, false, false, false, true, AM_ABS_X }, | 265 | [0x7F] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_X }, |
| 266 | [0x7B] = { "RRA", RRA, 3, 7, false, false, false, true, AM_ABS_Y }, | 266 | [0x7B] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_Y }, |
| 267 | [0x63] = { "RRA", RRA, 2, 8, false, false, false, true, AM_IND_X }, | 267 | [0x63] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_X }, |
| 268 | [0x73] = { "RRA", RRA, 2, 8, false, false, false, true, AM_IND_Y }, | 268 | [0x73] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_Y }, |
| 269 | [0xEB] = { "SBC", SBC, 2, 2, false, false, false, true, AM_IMM }, | 269 | [0xEB] = { "SBC", SBC, 2, 2, false, false, false, true, AM_IMM }, |
| 270 | [0x07] = { "SLO", SLO, 2, 5, false, false, false, true, AM_ZP }, | 270 | [0x07] = { "SLO", SLO, 2, 5, true, true, false, true, AM_ZP }, |
| 271 | [0x17] = { "SLO", SLO, 2, 6, false, false, false, true, AM_ZP_X }, | 271 | [0x17] = { "SLO", SLO, 2, 6, true, true, false, true, AM_ZP_X }, |
| 272 | [0x0F] = { "SLO", SLO, 3, 6, false, false, false, true, AM_ABS }, | 272 | [0x0F] = { "SLO", SLO, 3, 6, true, true, false, true, AM_ABS }, |
| 273 | [0x1F] = { "SLO", SLO, 3, 7, false, false, false, true, AM_ABS_X }, | 273 | [0x1F] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_X }, |
| 274 | [0x1B] = { "SLO", SLO, 3, 7, false, false, false, true, AM_ABS_Y }, | 274 | [0x1B] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_Y }, |
| 275 | [0x03] = { "SLO", SLO, 2, 8, false, false, false, true, AM_IND_X }, | 275 | [0x03] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_X }, |
| 276 | [0x13] = { "SLO", SLO, 2, 8, false, false, false, true, AM_IND_Y }, | 276 | [0x13] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_Y }, |
| 277 | [0x47] = { "SRE", SRE, 2, 5, false, false, false, true, AM_ZP }, | 277 | [0x47] = { "SRE", SRE, 2, 5, true, true, false, true, AM_ZP }, |
| 278 | [0x57] = { "SRE", SRE, 2, 6, false, false, false, true, AM_ZP_X }, | 278 | [0x57] = { "SRE", SRE, 2, 6, true, true, false, true, AM_ZP_X }, |
| 279 | [0x4F] = { "SRE", SRE, 3, 6, false, false, false, true, AM_ABS }, | 279 | [0x4F] = { "SRE", SRE, 3, 6, true, true, false, true, AM_ABS }, |
| 280 | [0x5F] = { "SRE", SRE, 3, 7, false, false, false, true, AM_ABS_X }, | 280 | [0x5F] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_X }, |
| 281 | [0x5B] = { "SRE", SRE, 3, 7, false, false, false, true, AM_ABS_Y }, | 281 | [0x5B] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_Y }, |
| 282 | [0x43] = { "SRE", SRE, 2, 8, false, false, false, true, AM_IND_X }, | 282 | [0x43] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_X }, |
| 283 | [0x53] = { "SRE", SRE, 2, 8, false, false, false, true, AM_IND_Y }, | 283 | [0x53] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_Y }, |
| 284 | [0x9E] = { "SXA", SXA, 3, 5, false, false, false, true, AM_ABS_Y }, | 284 | [0x9E] = { "SXA", SXA, 3, 5, false, true, false, true, AM_ABS_Y }, |
| 285 | [0x9C] = { "SYA", SYA, 3, 5, false, false, false, true, AM_ABS_X }, | 285 | [0x9C] = { "SYA", SYA, 3, 5, false, true, false, true, AM_ABS_X }, |
| 286 | [0x0C] = { "NOP", NOP, 3, 4, true, false, false, true, AM_ABS }, | 286 | [0x0C] = { "NOP", NOP, 3, 4, true, false, false, true, AM_ABS }, |
| 287 | [0x1C] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | 287 | [0x1C] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, |
| 288 | [0x3C] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | 288 | [0x3C] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, |
| @@ -291,5 +291,5 @@ struct opcode opcodes[0x100] = { | |||
| 291 | [0xDC] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | 291 | [0xDC] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, |
| 292 | [0xFC] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, | 292 | [0xFC] = { "NOP", NOP, 3, 4, true, false, true, true, AM_ABS_X }, |
| 293 | [0x8B] = { "XAA", XAA, 2, 2, false, false, false, true, AM_IMM }, | 293 | [0x8B] = { "XAA", XAA, 2, 2, false, false, false, true, AM_IMM }, |
| 294 | [0x9B] = { "XAS", XAS, 3, 5, false, false, false, true, AM_ABS_Y }, | 294 | [0x9B] = { "XAS", XAS, 3, 5, false, true, false, true, AM_ABS_Y }, |
| 295 | }; | 295 | }; |
