commit 01e6e1ad0d0252ae4279a94cbf21deee8300965e
parent fe95a0356ebe488c2fa337db35a2b49f0535e40d
Author: Vineet Kumar <git@vineetk.net>
Date: Mon, 1 Jun 2026 15:24:22 -0400
add basic exception signals
Diffstat:
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -62,20 +62,29 @@ typedef enum logic [2:0] {WB_NONE, // no register writeback
WB_IMM // LUI writes back an immediate value
} wbsrc_t;
+// very rudimentary. privileged spec (chapter 3) defines this formally, but left to implementation
+// on unprivileged spec.
+typedef enum logic [1:0] {EXC_NONE,
+ EXC_ILL_INST, // illegal instruction
+ EXC_CALL, // ECALL
+ EXC_BKPT // EBREAK
+} exception_t;
+
typedef struct packed {
- aluop_t aluop;
+ aluop_t aluop;
aluop1src_t aluop1src;
aluop2src_t aluop2src;
- memop_t memop;
- pcsrc_t pcsrc;
- branchop_t branchop;
- wbsrc_t wbsrc;
+ memop_t memop;
+ pcsrc_t pcsrc;
+ branchop_t branchop;
+ wbsrc_t wbsrc;
+ exception_t exception;
} ctrl_t;
module stage_decode
(input logic [31:0] inst,
input logic [31:0] regfile [0:31],
- output ctrl_t ctrl,
+ output ctrl_t ctrl,
output logic [31:0] imm,
output logic [31:0] rs1_val,
output logic [31:0] rs2_val,
@@ -279,7 +288,8 @@ module stage_decode
memop: MEM_NONE,
pcsrc: PC_SEQ,
branchop: BRANCH_NONE,
- wbsrc: WB_NONE};
+ wbsrc: WB_NONE,
+ exception: EXC_NONE};
unique case (name)
// rv32i
LUI: ctrl.wbsrc = WB_IMM;
@@ -509,17 +519,14 @@ module stage_decode
ctrl.aluop2src = ALUOP2_REG;
ctrl.wbsrc = WB_ALU;
end
- // MISC-MEM instructions are basically NOPs
+ // MISC-MEM instructions are basically NOPs on single-hart system
FENCE: ;
FENCE_TSO: ;
PAUSE: ;
// SYSTEM instructions do traps
- ECALL: begin
- ctrl.aluop = ALU_NONE;
- end
- EBREAK: begin
- ctrl.aluop = ALU_NONE;
- end
+ ECALL: ctrl.exception = EXC_CALL;
+ EBREAK: ctrl.exception = EXC_BKPT;
+ default: ctrl.exception = EXC_ILL_INST;
endcase
end