rv32g-core

commit 452fc47fa674c4c686416465b9c939568df910fa
parent b1da71976298dbebb4c5acef8b37d2973d44e47a
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  6 Jul 2026 17:40:51 +0530

stop simulation when illegal instruction encountered

Diffstat:
M
rtl/tb_rv32g.sv
 | 
4
+++-

1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv
@@ -73,7 +73,9 @@ module tb_rv32g
    always_ff @(posedge clk) begin
      if ((!imem_valid && rstN) ||
 	 (cycle_cnt > 0 && imem_data == 32'b0) ||
-	 exception == EXC_ILL_INST) begin
+	 (cycle_cnt > 0 && rstN && exception == EXC_ILL_INST)) begin
+     // if ((!imem_valid && rstN) ||
+     // 	 (cycle_cnt > 0 && imem_data == 32'b0)) begin
        $finish();
      end
    end