rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 56b8baf09f4372bae891e08a3a93fff1741fe48c
parent 55ea46312b825c0c2c238bb14f6c853a334c6a3e
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon, 13 Jul 2026 10:12:55 +0530

remove tb prematurely exiting on ecall/ebreak

Diffstat:
Mrtl/tb_rv32g.sv | 8+-------
1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv @@ -83,13 +83,7 @@ module tb_rv32g parameter int MAX_CYCLES = 10000; always_ff @(posedge clk) begin if (exception == EXC_ILL_INST && seen_first_real_inst) begin - $display("!!! Program terminated (exception ILL_INST at PC %h) !!!", pc_out); - $finish(); - end - - if (exception == EXC_CALL || exception == EXC_BKPT) begin - $display("*** Program finished (exception %s) at cycle %0d ***", - exception == EXC_CALL ? "ECALL" : "EBREAK", cycle_cnt); + $display("!!! Program terminated (exception ILL_INST at PC %h), inst: %h !!!", pc_out, dut.ifid_reg.inst); $finish(); end