rv32g-core

commit 6a78ab80cc3de152aca15c5dcf416ba2c3cb3c6a
parent 3b842277ef7a42858e7de7cd9fc8dca5800753a0
Author: Vineet Kumar <git@vineetk.net>
Date:   Fri,  7 Aug 2026 12:31:13 +0530

increase cache_size to 2K words from 256 to better use BSRAM

Recovery-Origin: e9130fb4b9c4d689af6886ff9fa73b5aa19eebb6
Recovery-Status: reconstructed history

Reimplemented the one-line cache-size change from its reflog message and intact before/after source.

Diffstat:
M
rtl/stage_fetch.sv
 | 
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rtl/stage_fetch.sv b/rtl/stage_fetch.sv
@@ -11,7 +11,7 @@ module stage_fetch
 `define USE_ICACHE
 `ifdef USE_ICACHE
 
-   localparam			    CACHE_SIZE = 256;		    // words
+   localparam			    CACHE_SIZE = 2048;		    // words
    localparam			    IDX_WIDTH = $clog2(CACHE_SIZE);
    localparam			    TAG_WIDTH = 32 - IDX_WIDTH - 2; // only be byte offset