commit 8211eeff31624249a8a6b65081b8f31f3fe0325e
parent b912995e94db9b6dad3d569897771ac3336e66ea
Author: Vineet Kumar <git@vineetk.net>
Date: Sun, 31 May 2026 19:04:13 -0400
define control signals
Diffstat:
| M | rtl/stage_decode.sv | | | 82 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---- |
1 file changed, 78 insertions(+), 4 deletions(-)
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -1,7 +1,81 @@
+// TODO move main typedefs to package
+typedef enum logic [3:0] {// rv32i
+ ALU_NONE,
+ ALU_ADD,
+ ALU_SUB,
+ ALU_XOR,
+ ALU_OR,
+ ALU_AND,
+ ALU_SLL,
+ ALU_SRL,
+ ALU_SRA,
+ ALU_SLT,
+ ALU_SLTU
+ // TODO rv32m
+ // ALU_MUL,
+ // ALU_DIV,
+ // ALU_REM,
+ // TODO rv32a
+ // TODO rv32f
+ // TODO rv32d
+} aluop_t;
+
+typedef enum logic [1:0] {ALUOP1_NONE,
+ ALUOP1_REG, // pretty much every intruction except AUIPC
+ ALUOP1_PC // AUIPC is special :)
+} aluop1src_t;
+
+typedef enum logic [1:0] {ALUOP2_NONE,
+ ALUOP2_REG, // R-type and S-type instructions
+ ALUOP2_IMM // sign-extended immediate for I-type and JALR
+} aluop2src_t;
+
+typedef enum logic [3:0] {MEM_NONE,
+ MEM_LB,
+ MEM_LH,
+ MEM_LW,
+ MEM_LBU,
+ MEM_LHU,
+ MEM_SB,
+ MEM_SH,
+ MEM_SW
+} memop_t;
+
+typedef enum logic [2:0] {BRANCH_NONE,
+ BRANCH_BEQ,
+ BRANCH_BNE,
+ BRANCH_BLT,
+ BRANCH_BGE,
+ BRANCH_BLTU,
+ BRANCH_BGEU
+} branchop_t;
+
+typedef enum logic [1:0] {PC_SEQ, // PC = PC + 4 (regular)
+ PC_IMM, // PC = PC + imm (branch and jal)
+ PC_ALU // PC = rs1 + imm (jalr)
+} pcsrc_t;
+
+typedef enum logic [2:0] {WB_NONE, // no register writeback
+ WB_PC, // JAL writes using PC adder
+ WB_ALU, // R-type and I-type instructions
+ WB_MEM, // All load instructions
+ WB_IMM // LUI writes back an immediate value
+} wbsrc_t;
+
+typedef struct packed {
+ aluop_t aluop;
+ aluop1src_t aluop1src;
+ aluop2src_t aluop2src;
+ memop_t memop;
+ pcsrc_t pcsrc;
+ branchop_t branchop;
+ wbsrc_t wbsrc;
+} ctrl_t;
+
module stage_decode
(input logic [31:0] inst,
input logic [31:0] regfile [0:31],
- output logic [31:0] ctrl,
+ output ctrl_t ctrl,
output logic [31:0] imm,
output logic [31:0] rs1_val,
output logic [31:0] rs2_val,
@@ -110,8 +184,8 @@ module stage_decode
always_comb begin
unique case (opcode)
// rv32i
- OPCODE_LUI: inst_type = ITYPE;
- OPCODE_AUIPC: inst_type = ITYPE;
+ OPCODE_LUI: inst_type = UTYPE;
+ OPCODE_AUIPC: inst_type = UTYPE;
OPCODE_JAL: inst_type = JTYPE;
OPCODE_JALR: inst_type = ITYPE;
OPCODE_BRANCH: inst_type = BTYPE;
@@ -201,7 +275,7 @@ module stage_decode
always_comb begin
case (name)
// rv32i
- default: ctrl = '0;
+ default: ctrl = {default:0};
endcase
end
