rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 96ed6dba8e30b9ae0fc2758d6ac7fd7ff59d56ba
parent 8ff59035f7ac85e58ee138217a3d3674e38d8d6b
Author: Vineet Kumar <git@vineetk.net>
Date:   Sat, 22 Aug 2026 05:01:32 +0530

remove addi to nop decoding because of comparison

Recovery-Origin: e55684bbb758547c693fabd693e1e8bdd122542a
Recovery-Status: reconstructed history

Removed the reconstructed explicit ADDI-as-NOP special case, reaching the hash-verified final stage_decode.sv. Original intermediate commit object is missing.

Diffstat:
Mrtl/stage_decode.sv | 9+--------
1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv @@ -120,14 +120,7 @@ module stage_decode ctrl.wbsrc = WB_ALU; unique case (funct3) // rv32i; done in same order as it appears in chapter 36 of unprivileged manual - 3'b000: begin - if (rd_num == 0 && rs1_num == 0 && imm == 0) begin - ctrl.aluop = ALU_NONE; - ctrl.aluop1src = ALUOP1_NONE; - ctrl.aluop2src = ALUOP2_NONE; - ctrl.wbsrc = WB_NONE; - end else ctrl.aluop = ALU_ADD; - end + 3'b000: ctrl.aluop = ALU_ADD; 3'b010: ctrl.aluop = ALU_SLT; 3'b011: ctrl.aluop = ALU_SLTU; 3'b100: ctrl.aluop = ALU_XOR;