rv32g-core

commit 97385bda2d364514abda2a3df050a2122a88d572
parent 43a3c59161d6e8f700143d96eae06e25bd830f99
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  8 Jun 2026 14:53:46 -0400

fix instruction decoding in decoding logic to not use initial assignment

basically what it seemed to previously do was it stayed on the first
instruction and never updated afterward since it wasn't in a
combinational block

Diffstat:
M
rtl/stage_decode.sv
 | 
19
+++++++++++++------

1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -8,15 +8,22 @@ module stage_decode
     output logic [31:0]	rs2_val,
     output logic [4:0]	rd_num);
 
-   logic [6:0]	funct7 = inst[31:25];
-   logic [4:0]	rs2_num = inst[24:20];
-   logic [4:0]	rs1_num = inst[19:15];
-   logic [2:0]	funct3 = inst[14:12];
-   opcode_t	opcode = opcode_t'(inst[6:0]);
+   logic [6:0]	funct7;
+   logic [4:0]	rs2_num;
+   logic [4:0]	rs1_num;
+   logic [2:0]	funct3;
+   opcode_t	opcode;
    inst_type_t  inst_type;
    inst_name_t  name;
 
-   assign rd_num = inst[11:7];
+   always_comb begin
+     funct7 = inst[31:25];
+     rs2_num = inst[24:20];
+     rs1_num = inst[19:15];
+     funct3 = inst[14:12];
+     rd_num = inst[11:7];
+     opcode = opcode_t'(inst[6:0]);
+   end
 
    // parse the type for each instruction
    always_comb begin