rv32g-core

commit d233e76dcd37b3d6773d865129119f9c0afbf921
parent 0697dae7c278f7d3b076fb1617d6c155b63e31fc
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  1 Jun 2026 15:53:28 -0400

group control signals together when decoding based on major opcode

Diffstat:
M
rtl/stage_decode.sv
 | 
248
++++++++++++++++++-------------------------------------------------------------

1 file changed, 55 insertions(+), 193 deletions(-)
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -208,235 +208,97 @@ module stage_decode
 	      branchop:  BRANCH_NONE,
 	      wbsrc:     WB_NONE,
 	      exception: EXC_NONE};
-     unique case (name)
-       // rv32i
-       LUI: ctrl.wbsrc = WB_IMM;
-       AUIPC: begin
+     // the major opcodes share the same signals, just operation varies based on funct
+     unique case (opcode)
+       OPCODE_LUI: ctrl.wbsrc = WB_IMM;
+       OPCODE_AUIPC: begin
          ctrl.aluop = ALU_ADD;
          ctrl.aluop1src = ALUOP1_PC;
          ctrl.aluop2src = ALUOP2_IMM;
          ctrl.wbsrc = WB_ALU;
        end
-       JAL: begin
+       OPCODE_JAL: begin
          ctrl.pcsrc = PC_IMM;
          ctrl.wbsrc = WB_PC;
        end
-       JALR: begin
+       OPCODE_JALR: begin
 	 ctrl.aluop = ALU_ADD;
 	 ctrl.aluop1src = ALUOP1_REG;
 	 ctrl.aluop2src = ALUOP2_IMM;
          ctrl.pcsrc = PC_ALU;
          ctrl.wbsrc = WB_PC;
        end
-       BEQ: begin
+       OPCODE_BRANCH: begin
          ctrl.aluop = ALU_SUB;
 	 ctrl.aluop1src = ALUOP1_REG;
 	 ctrl.aluop2src = ALUOP2_REG;
 	 ctrl.pcsrc = PC_IMM;
-	 ctrl.branchop = BRANCH_BEQ;
-       end
-       BNE: begin
-         ctrl.aluop = ALU_SUB;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.pcsrc = PC_IMM;
-	 ctrl.branchop = BRANCH_BNE;
-       end
-       BLT: begin
-         ctrl.aluop = ALU_SUB;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.pcsrc = PC_IMM;
-	 ctrl.branchop = BRANCH_BLT;
-       end
-       BGE: begin
-         ctrl.aluop = ALU_SUB;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.pcsrc = PC_IMM;
-	 ctrl.branchop = BRANCH_BGE;
-       end
-       BLTU: begin
-         ctrl.aluop = ALU_SUB;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.pcsrc = PC_IMM;
-	 ctrl.branchop = BRANCH_BLTU;
-       end
-       BGEU: begin
-         ctrl.aluop = ALU_SUB;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.pcsrc = PC_IMM;
-	 ctrl.branchop = BRANCH_BGEU;
-       end
-       LB: begin
-         ctrl.aluop = ALU_ADD;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.memop = MEM_LB;
-	 ctrl.wbsrc = WB_MEM;
        end
-       LH: begin
+       OPCODE_LOAD: begin
          ctrl.aluop = ALU_ADD;
 	 ctrl.aluop1src = ALUOP1_REG;
 	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.memop = MEM_LH;
 	 ctrl.wbsrc = WB_MEM;
        end
-       LW: begin
+       OPCODE_STORE: begin
          ctrl.aluop = ALU_ADD;
 	 ctrl.aluop1src = ALUOP1_REG;
 	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.memop = MEM_LW;
-	 ctrl.wbsrc = WB_MEM;
-       end
-       LBU: begin
-         ctrl.aluop = ALU_ADD;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.memop = MEM_LBU;
-	 ctrl.wbsrc = WB_MEM;
-       end
-       LHU: begin
-         ctrl.aluop = ALU_ADD;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.memop = MEM_LHU;
-	 ctrl.wbsrc = WB_MEM;
-       end
-       SB: begin
-         ctrl.aluop = ALU_ADD;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.memop = MEM_SB;
-       end
-       SH: begin
-         ctrl.aluop = ALU_ADD;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.memop = MEM_SH;
-       end
-       SW: begin
-         ctrl.aluop = ALU_ADD;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.memop = MEM_SW;
-       end
-       ADDI: begin
-         ctrl.aluop = ALU_ADD;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SLTI: begin
-         ctrl.aluop = ALU_SLT;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SLTIU: begin
-         ctrl.aluop = ALU_SLTU;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.wbsrc = WB_ALU;
        end
-       XORI: begin
-         ctrl.aluop = ALU_XOR;
+       OPCODE_OP_IMM: begin
 	 ctrl.aluop1src = ALUOP1_REG;
 	 ctrl.aluop2src = ALUOP2_IMM;
 	 ctrl.wbsrc = WB_ALU;
        end
-       ORI: begin
-         ctrl.aluop = ALU_OR;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       ANDI: begin
-         ctrl.aluop = ALU_AND;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SLLI: begin
-         ctrl.aluop = ALU_SLL;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SRLI: begin
-         ctrl.aluop = ALU_SRL;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SRAI: begin
-         ctrl.aluop = ALU_SRA;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_IMM;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       ADD: begin
-         ctrl.aluop = ALU_ADD;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SUB: begin
-         ctrl.aluop = ALU_SUB;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SLL: begin
-         ctrl.aluop = ALU_SLL;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SLT: begin
-         ctrl.aluop = ALU_SLT;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SLTU: begin
-         ctrl.aluop = ALU_SLTU;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       XOR: begin
-         ctrl.aluop = ALU_XOR;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SRL: begin
-         ctrl.aluop = ALU_SRL;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       SRA: begin
-         ctrl.aluop = ALU_SRA;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       OR: begin
-         ctrl.aluop = ALU_OR;
-	 ctrl.aluop1src = ALUOP1_REG;
-	 ctrl.aluop2src = ALUOP2_REG;
-	 ctrl.wbsrc = WB_ALU;
-       end
-       AND: begin
-         ctrl.aluop = ALU_AND;
+       OPCODE_OP: begin
 	 ctrl.aluop1src = ALUOP1_REG;
 	 ctrl.aluop2src = ALUOP2_REG;
 	 ctrl.wbsrc = WB_ALU;
        end
+       OPCODE_MISC_MEM: ;
+       OPCODE_SYSTEM: ;
+       default: ;
+     endcase
+     
+     unique case (name)
+       // rv32i
+       LUI: ;
+       AUIPC: ;
+       JAL: ;
+       JALR: ;
+       BEQ: ctrl.branchop = BRANCH_BEQ;
+       BNE: ctrl.branchop = BRANCH_BNE;
+       BLT: ctrl.branchop = BRANCH_BLT;
+       BGE: ctrl.branchop = BRANCH_BGE;
+       BLTU: ctrl.branchop = BRANCH_BLTU;
+       BGEU: ctrl.branchop = BRANCH_BGEU;
+       LB: ctrl.memop = MEM_LB;
+       LH: ctrl.memop = MEM_LH;
+       LW: ctrl.memop = MEM_LW;
+       LBU: ctrl.memop = MEM_LBU;
+       LHU: ctrl.memop = MEM_LHU;
+       SB: ctrl.memop = MEM_SB;
+       SH: ctrl.memop = MEM_SH;
+       SW: ctrl.memop = MEM_SW;
+       ADDI: ctrl.aluop = ALU_ADD;
+       SLTI: ctrl.aluop = ALU_SLT;
+       SLTIU: ctrl.aluop = ALU_SLTU;
+       XORI: ctrl.aluop = ALU_XOR;
+       ORI: ctrl.aluop = ALU_OR;
+       ANDI: ctrl.aluop = ALU_AND;
+       SLLI: ctrl.aluop = ALU_SLL;
+       SRLI: ctrl.aluop = ALU_SRL;
+       SRAI: ctrl.aluop = ALU_SRA;
+       ADD: ctrl.aluop = ALU_ADD;
+       SUB: ctrl.aluop = ALU_SUB;
+       SLL: ctrl.aluop = ALU_SLL;
+       SLT: ctrl.aluop = ALU_SLT;
+       SLTU: ctrl.aluop = ALU_SLTU;
+       XOR: ctrl.aluop = ALU_XOR;
+       SRL: ctrl.aluop = ALU_SRL;
+       SRA: ctrl.aluop = ALU_SRA;
+       OR: ctrl.aluop = ALU_OR;
+       AND: ctrl.aluop = ALU_AND;
        // MISC-MEM instructions are basically NOPs on single-hart system
        FENCE: ;
        FENCE_TSO: ;