rv32g-core

commit dafb90c3fb697598b3c8972cc5602b5ffa24228b
parent 57387869f290867fc0691098e3d1633c18c8bd17
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  9 Jun 2026 14:45:00 -0400

change finish condition of testbench to include '0 inst

Diffstat:
M
rtl/tb_rv32g.sv
 | 
7
++++++-

1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv
@@ -67,6 +67,11 @@ module tb_rv32g
 		  .dmem_rdata, .dmem_wdata,
 		  .dmem_we, .dmem_be);
 
-   always if (!imem_valid) $finish();
+   always_ff @(posedge clk) begin
+//     if ((!imem_valid && rstN) || (cycle_cnt > 0 && exception == EXC_ILL_INST)) begin
+     if ((!imem_valid && rstN) || (cycle_cnt > 0 && imem_data == 32'b0)) begin
+       $finish();
+     end
+   end
 
 endmodule