rv32g-core

commit dd1ae9ee4aa0872f82646e895d2a79df07cdff8d
parent 882db63ddf63461fedb7bbfc77c3b0f385a858bc
Author: Vineet Kumar <git@vineetk.net>
Date:   Sun,  7 Jun 2026 18:57:34 -0400

print current cycle

Diffstat:
M
rtl/tb_rv32g.sv
 | 
16
++++++++++++++--

1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv
@@ -3,6 +3,7 @@ timeunit 1ns; timeprecision 1ps;
 module tb_rv32g
   ();
 
+   // DUT (design-under-test) ports
    logic	clk;
    logic	rstN;
 
@@ -19,6 +20,9 @@ module tb_rv32g
    logic	dmem_we;
    logic [3:0]	dmem_be;
 
+   // debug stuff
+   int		cycle_cnt = 0;
+
    // 100 MHz clock generation
    // T = 1/f/2 = 1/(100*10^6)/2 = 1e-8/2 = 5ns
    initial forever #5ns clk = ~clk;
@@ -37,9 +41,17 @@ module tb_rv32g
      $display("Reset now deactivated");
    end
 
+   // negedge clk instead of posedge clk to avoid race-condition
+   // prints the current cycle going into the hart
+   always @(negedge clk or posedge rstN) begin
+     if (!rstN) cycle_cnt <= 0;
+     else cycle_cnt <= cycle_cnt + 1;
+     $display("Cycle: %d", cycle_cnt);
+   end
+
    assign imem_data = imem[imem_addr >> 2];
-   assign dmem_data = dmem[dmem_addr];
-   assign imem_valid = (imem_data !== 32'h00000000 && imem_data !== 32'hffffffff) ? 1 : 0;
+   assign dmem_data = dmem[dmem_addr >> 2];
+   assign imem_valid = (imem_data !== 32'h0000_0000 && imem_data !== 32'hffff_ffff) ? 1 : 0;
 
    rv32g_hart dut(.clk, .rstN,
 		  .imem_addr, .imem_data, .imem_valid,