implement all of the nestest unofficial opcodes and fix branch cycles
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parent
4ccf9f5cee
commit
e1cdd73868
19
cpu.c
19
cpu.c
@ -127,9 +127,7 @@ opcode_mem(enum addressing_mode mode)
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val = (arg + regs.y) % 256;
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break;
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case AM_REL:
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val = arg + regs.pc;
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if (((regs.pc + 1) & 0xFF00) != (val & 0xFF00))
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val -= 0x0100;
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val = (int8_t)arg + regs.pc;
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break;
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case AM_IMM:
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case AM_ABS:
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@ -174,6 +172,9 @@ branch(uint16_t addr, bool cond)
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return;
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cycles++;
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if (((regs.pc + 1) & 0xFF00) != (addr & 0xFF00))
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cycles++;
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regs.pc = addr;
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}
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@ -277,7 +278,7 @@ BRK(uint16_t arg)
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{
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/* TODO: push regs.pc and regs.status to stack and load IRQ vector */
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regs.status.brk = 1;
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// exit(0);
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exit(0);
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}
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void
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@ -771,11 +772,11 @@ DCP(uint16_t arg)
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memwrite(arg, tmp);
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regs.status.carry = tmp <= regs.a;
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STATUS_UPDATE_NZ(tmp);
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STATUS_UPDATE_NZ(regs.a - tmp);
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}
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void
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ISC(uint16_t arg)
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ISB(uint16_t arg)
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{
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INC(arg);
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SBC(peek(arg));
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@ -807,7 +808,7 @@ void
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RLA(uint16_t arg)
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{
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ROL(arg);
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AND(arg);
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AND(peek(arg));
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}
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void
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@ -821,14 +822,14 @@ void
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SLO(uint16_t arg)
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{
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ASL(arg);
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ORA(arg);
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ORA(peek(arg));
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}
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void
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SRE(uint16_t arg)
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{
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LSR(arg);
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EOR(arg);
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EOR(peek(arg));
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}
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void
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2
cpu.h
2
cpu.h
@ -72,7 +72,7 @@ void AXA(uint16_t arg);
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void AXS(uint16_t arg);
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void DCP(uint16_t arg);
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void DOP(uint16_t arg);
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void ISC(uint16_t arg);
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void ISB(uint16_t arg);
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void KIL(uint16_t arg);
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void LAR(uint16_t arg);
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void LAX(uint16_t arg);
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70
opcodes.h
70
opcodes.h
@ -220,13 +220,13 @@ struct opcode opcodes[0x100] = {
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[0xD4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X },
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[0xE2] = { "NOP", NOP, 2, 2, false, false, false, true, AM_IMM },
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[0xF4] = { "NOP", NOP, 2, 4, true, false, false, true, AM_ZP_X },
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[0xE7] = { "ISC", ISC, 2, 5, false, false, false, true, AM_ZP },
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[0xF7] = { "ISC", ISC, 2, 6, false, false, false, true, AM_ZP_X },
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[0xEF] = { "ISC", ISC, 3, 6, false, false, false, true, AM_ABS },
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[0xFF] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_X },
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[0xFB] = { "ISC", ISC, 3, 7, false, false, false, true, AM_ABS_Y },
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[0xE3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_X },
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[0xF3] = { "ISC", ISC, 2, 8, false, false, false, true, AM_IND_Y },
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[0xE7] = { "ISB", ISB, 2, 5, false, true, false, true, AM_ZP },
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[0xF7] = { "ISB", ISB, 2, 6, false, true, false, true, AM_ZP_X },
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[0xEF] = { "ISB", ISB, 3, 6, false, true, false, true, AM_ABS },
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[0xFF] = { "ISB", ISB, 3, 7, false, true, false, true, AM_ABS_X },
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[0xFB] = { "ISB", ISB, 3, 7, false, true, false, true, AM_ABS_Y },
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[0xE3] = { "ISB", ISB, 2, 8, false, true, false, true, AM_IND_X },
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[0xF3] = { "ISB", ISB, 2, 8, false, true, false, true, AM_IND_Y },
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[0x02] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE },
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[0x12] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE },
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[0x22] = { "KIL", KIL, 1, 0, false, false, false, true, AM_NONE },
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@ -252,35 +252,35 @@ struct opcode opcodes[0x100] = {
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[0x7A] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE },
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[0xDA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE },
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[0xFA] = { "NOP", NOP, 1, 2, false, false, false, true, AM_NONE },
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[0x27] = { "RLA", RLA, 2, 5, true, true, false, true, AM_ZP },
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[0x37] = { "RLA", RLA, 2, 6, true, true, false, true, AM_ZP_X },
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[0x2F] = { "RLA", RLA, 3, 6, true, true, false, true, AM_ABS },
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[0x3F] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_X },
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[0x3B] = { "RLA", RLA, 3, 7, true, true, false, true, AM_ABS_Y },
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[0x23] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_X },
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[0x33] = { "RLA", RLA, 2, 8, true, true, false, true, AM_IND_Y },
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[0x67] = { "RRA", RRA, 2, 5, true, true, false, true, AM_ZP },
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[0x77] = { "RRA", RRA, 2, 6, true, true, false, true, AM_ZP_X },
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[0x6F] = { "RRA", RRA, 3, 6, true, true, false, true, AM_ABS },
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[0x7F] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_X },
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[0x7B] = { "RRA", RRA, 3, 7, true, true, false, true, AM_ABS_Y },
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[0x63] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_X },
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[0x73] = { "RRA", RRA, 2, 8, true, true, false, true, AM_IND_Y },
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[0x27] = { "RLA", RLA, 2, 5, false, true, false, true, AM_ZP },
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[0x37] = { "RLA", RLA, 2, 6, false, true, false, true, AM_ZP_X },
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[0x2F] = { "RLA", RLA, 3, 6, false, true, false, true, AM_ABS },
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[0x3F] = { "RLA", RLA, 3, 7, false, true, false, true, AM_ABS_X },
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[0x3B] = { "RLA", RLA, 3, 7, false, true, false, true, AM_ABS_Y },
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[0x23] = { "RLA", RLA, 2, 8, false, true, false, true, AM_IND_X },
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[0x33] = { "RLA", RLA, 2, 8, false, true, false, true, AM_IND_Y },
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[0x67] = { "RRA", RRA, 2, 5, false, true, false, true, AM_ZP },
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[0x77] = { "RRA", RRA, 2, 6, false, true, false, true, AM_ZP_X },
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[0x6F] = { "RRA", RRA, 3, 6, false, true, false, true, AM_ABS },
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[0x7F] = { "RRA", RRA, 3, 7, false, true, false, true, AM_ABS_X },
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[0x7B] = { "RRA", RRA, 3, 7, false, true, false, true, AM_ABS_Y },
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[0x63] = { "RRA", RRA, 2, 8, false, true, false, true, AM_IND_X },
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[0x73] = { "RRA", RRA, 2, 8, false, true, false, true, AM_IND_Y },
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[0xEB] = { "SBC", SBC, 2, 2, false, false, false, true, AM_IMM },
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[0x07] = { "SLO", SLO, 2, 5, true, true, false, true, AM_ZP },
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[0x17] = { "SLO", SLO, 2, 6, true, true, false, true, AM_ZP_X },
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[0x0F] = { "SLO", SLO, 3, 6, true, true, false, true, AM_ABS },
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[0x1F] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_X },
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[0x1B] = { "SLO", SLO, 3, 7, true, true, false, true, AM_ABS_Y },
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[0x03] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_X },
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[0x13] = { "SLO", SLO, 2, 8, true, true, false, true, AM_IND_Y },
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[0x47] = { "SRE", SRE, 2, 5, true, true, false, true, AM_ZP },
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[0x57] = { "SRE", SRE, 2, 6, true, true, false, true, AM_ZP_X },
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[0x4F] = { "SRE", SRE, 3, 6, true, true, false, true, AM_ABS },
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[0x5F] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_X },
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[0x5B] = { "SRE", SRE, 3, 7, true, true, false, true, AM_ABS_Y },
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[0x43] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_X },
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[0x53] = { "SRE", SRE, 2, 8, true, true, false, true, AM_IND_Y },
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[0x07] = { "SLO", SLO, 2, 5, false, true, false, true, AM_ZP },
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[0x17] = { "SLO", SLO, 2, 6, false, true, false, true, AM_ZP_X },
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[0x0F] = { "SLO", SLO, 3, 6, false, true, false, true, AM_ABS },
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[0x1F] = { "SLO", SLO, 3, 7, false, true, false, true, AM_ABS_X },
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[0x1B] = { "SLO", SLO, 3, 7, false, true, false, true, AM_ABS_Y },
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[0x03] = { "SLO", SLO, 2, 8, false, true, false, true, AM_IND_X },
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[0x13] = { "SLO", SLO, 2, 8, false, true, false, true, AM_IND_Y },
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[0x47] = { "SRE", SRE, 2, 5, false, true, false, true, AM_ZP },
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[0x57] = { "SRE", SRE, 2, 6, false, true, false, true, AM_ZP_X },
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[0x4F] = { "SRE", SRE, 3, 6, false, true, false, true, AM_ABS },
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[0x5F] = { "SRE", SRE, 3, 7, false, true, false, true, AM_ABS_X },
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[0x5B] = { "SRE", SRE, 3, 7, false, true, false, true, AM_ABS_Y },
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[0x43] = { "SRE", SRE, 2, 8, false, true, false, true, AM_IND_X },
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[0x53] = { "SRE", SRE, 2, 8, false, true, false, true, AM_IND_Y },
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[0x9E] = { "SXA", SXA, 3, 5, false, true, false, true, AM_ABS_Y },
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[0x9C] = { "SYA", SYA, 3, 5, false, true, false, true, AM_ABS_X },
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[0x0C] = { "NOP", NOP, 3, 4, true, false, false, true, AM_ABS },
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