add blt and bge

1 files changed, 13 insertions, 6 deletions

diff --git a/riscvsingle.sv b/riscvsingle.sv
index fc9c830..ed8504a 100644
--- a/riscvsingle.sv
+++ b/riscvsingle.sv
@@ -233,8 +233,10 @@ module controller(input  logic [6:0] op,
   always_comb

     if (Branch)

        case (funct3)

-         3'b000: PCSrc = Zero;

-         3'b001: PCSrc = ~Zero;

+         3'b000: PCSrc = Zero;  // beq

+         3'b001: PCSrc = ~Zero; // bne

+         3'b100: PCSrc = Zero; // blt

+         3'b101: PCSrc = ~Zero; // blt

          default: PCSrc = 1'bx;

        endcase

     else

@@ -260,7 +262,7 @@ module maindec(input  logic [6:0] op,
       7'b0000011: controls = 11'b1_00_1_0_01_0_00_0; // lw

       7'b0100011: controls = 11'b0_01_1_1_00_0_00_0; // sw

       7'b0110011: controls = 11'b1_xx_0_0_00_0_10_0; // R-type 

-      7'b1100011: controls = 11'b0_10_0_0_00_1_01_0; // beq

+      7'b1100011: controls = 11'b0_10_0_0_00_1_01_0; // B-type

       7'b0010011: controls = 11'b1_00_1_0_00_0_10_0; // I-type ALU

       7'b1101111: controls = 11'b1_11_0_0_10_0_00_1; // jal

       default:    controls = 11'bx_xx_x_x_xx_x_xx_x; // non-implemented instruction

@@ -279,7 +281,8 @@ module aludec(input  logic       opb5,
   always_comb

     case(ALUOp)

       2'b00:                ALUControl = 4'b0000; // addition

-      2'b01:                ALUControl = 4'b0001; // subtraction

+      2'b01:                ALUControl = {funct3[2], 3'b001}; // branching

+      // (funct3[2] is used because it's set in blt/bge but not beq/bne

       default: case(funct3) // R-type or I-type ALU

                  3'b000:  if (RtypeSub) 

                             ALUControl = 4'b0001; // sub

@@ -402,7 +405,11 @@ module alu(input  logic [31:0] a, b,
       default: result = 32'bx;

     endcase

 

-  assign zero = (result == 32'b0);

+   always_comb

+     case (alucontrol)

+       4'b1001: zero = a < b;             // blt and bge

+       default: zero = (result == 32'b0); // beq and bne

+     endcase

+

   assign v = ~(alucontrol[0] ^ a[31] ^ b[31]) & (a[31] ^ sum[31]) & isAddSub;

-  

 endmodule