commit c5ccd5c22f22cbbc265555559c7eefd06428398b
parent 6927c5bdc6009b2acb05a2a7d176003447340a34
Author: vin <git@vineetk.net>
Date: Thu, 20 Mar 2025 16:30:16 -0400
add shift instructions (sll, srl, sra, and immediates)
Diffstat:
| M | riscvsingle.sv | | | 50 | ++++++++++++++++++++++++++++---------------------- |
1 file changed, 28 insertions(+), 22 deletions(-)
diff --git a/riscvsingle.sv b/riscvsingle.sv
@@ -198,7 +198,7 @@ module riscvsingle(input logic clk, reset,
logic ALUSrc, RegWrite, Jump, Zero;
logic [1:0] ResultSrc, ImmSrc;
- logic [2:0] ALUControl;
+ logic [3:0] ALUControl;
controller c(Instr[6:0], Instr[14:12], Instr[30], Zero,
ResultSrc, MemWrite, PCSrc,
@@ -220,7 +220,7 @@ module controller(input logic [6:0] op,
output logic PCSrc, ALUSrc,
output logic RegWrite, Jump,
output logic [1:0] ImmSrc,
- output logic [2:0] ALUControl);
+ output logic [3:0] ALUControl);
logic [1:0] ALUOp;
logic Branch;
@@ -262,25 +262,30 @@ module aludec(input logic opb5,
input logic [2:0] funct3,
input logic funct7b5,
input logic [1:0] ALUOp,
- output logic [2:0] ALUControl);
+ output logic [3:0] ALUControl);
logic RtypeSub;
assign RtypeSub = funct7b5 & opb5; // TRUE for R-type subtract instruction
always_comb
case(ALUOp)
- 2'b00: ALUControl = 3'b000; // addition
- 2'b01: ALUControl = 3'b001; // subtraction
+ 2'b00: ALUControl = 4'b0000; // addition
+ 2'b01: ALUControl = 4'b0001; // subtraction
default: case(funct3) // R-type or I-type ALU
3'b000: if (RtypeSub)
- ALUControl = 3'b001; // sub
+ ALUControl = 4'b0001; // sub
else
- ALUControl = 3'b000; // add, addi
- 3'b010: ALUControl = 3'b101; // slt, slti
- 3'b100: ALUControl = 3'b100; // xor, xori
- 3'b110: ALUControl = 3'b011; // or, ori
- 3'b111: ALUControl = 3'b010; // and, andi
- default: ALUControl = 3'bxxx; // ???
+ ALUControl = 4'b0000; // add, addi
+ 3'b001: ALUControl = 4'b0110; // sll, slli
+ 3'b010: ALUControl = 4'b0101; // slt, slti
+ 3'b100: ALUControl = 4'b0100; // xor, xori
+ 3'b101: if (RtypeSub)
+ ALUControl = 4'b1000; // sra, srai
+ else
+ ALUControl = 4'b0111; // srl, srli
+ 3'b110: ALUControl = 4'b0011; // or, ori
+ 3'b111: ALUControl = 4'b0010; // and, andi
+ default: ALUControl = 4'bxxxx; // ???
endcase
endcase
endmodule
@@ -290,7 +295,7 @@ module datapath(input logic clk, reset,
input logic PCSrc, ALUSrc,
input logic RegWrite,
input logic [1:0] ImmSrc,
- input logic [2:0] ALUControl,
+ input logic [3:0] ALUControl,
output logic Zero,
output logic [31:0] PC,
input logic [31:0] Instr,
@@ -361,7 +366,7 @@ module mux3 #(parameter WIDTH = 8)
endmodule
module alu(input logic [31:0] a, b,
- input logic [2:0] alucontrol,
+ input logic [3:0] alucontrol,
output logic [31:0] result,
output logic zero);
@@ -376,14 +381,15 @@ module alu(input logic [31:0] a, b,
always_comb
case (alucontrol)
- 3'b000: result = sum; // add
- 3'b001: result = sum; // subtract
- 3'b010: result = a & b; // and
- 3'b011: result = a | b; // or
- 3'b100: result = a ^ b; // xor
- 3'b101: result = sum[31] ^ v; // slt
- 3'b110: result = a << b[4:0]; // sll
- 3'b111: result = a >> b[4:0]; // srl
+ 4'b0000: result = sum; // add
+ 4'b0001: result = sum; // subtract
+ 4'b0010: result = a & b; // and
+ 4'b0011: result = a | b; // or
+ 4'b0100: result = a ^ b; // xor
+ 4'b0101: result = sum[31] ^ v; // slt
+ 4'b0110: result = a << b[4:0]; // sll
+ 4'b0111: result = a >> b[4:0]; // srl
+ 4'b1000: result = $signed(a) >>> b[4:0]; // srl
default: result = 32'bx;
endcase
