rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 26ae3798b9234e981551a99392e5dcd1ada184bf
parent 10f35c6bdf802e170ba5dfa529cb8d1665af7784
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  4 Aug 2026 15:32:00 +0530

remove github:riscv-software-src/riscv-tests submodule

Diffstat:
D.gitmodules | 3---
Dtests/riscv-tests | 1-
2 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/.gitmodules b/.gitmodules @@ -1,3 +0,0 @@ -[submodule "tests/riscv-tests"] - path = tests/riscv-tests - url = https://github.com/riscv-software-src/riscv-tests/ diff --git a/tests/riscv-tests b/tests/riscv-tests @@ -1 +0,0 @@ -Subproject commit 34e6b6d1e7936b526075432fb730d89148623484