rv32g-core

commit 10f35c6bdf802e170ba5dfa529cb8d1665af7784
parent 9923ef798058d98b7ac10e83812c8081abdc465a
Author: Vineet Kumar <git@vineetk.net>
Date:   Sun, 26 Jul 2026 16:27:33 +0530

pipeline register reset's pc should use BASE_ADDR const

Diffstat:
M
rtl/rv32g_hart.sv
 | 
5
+++--

1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -89,7 +89,7 @@ module rv32g_hart
      if (!rstN) begin
        // NOP by default
        idex_reg <= '0;
-       idex_reg.pc <= pc_reg;
+       idex_reg.pc <= BASE_ADDR;
      end else if (if_stall) begin
        // insert NOP
        idex_reg <= '0;
@@ -133,7 +133,7 @@ module rv32g_hart
    always_ff @(posedge clk) begin
      if (!rstN) begin
        exmem_reg <= '0;
-       exmem_reg.pc <= idex_reg.pc;
+       exmem_reg.pc <= BASE_ADDR;
      end else begin
        exmem_reg.alu_out <= ex_alu_out;
        exmem_reg.rs2_val <= idex_reg.rs2_val;
@@ -165,6 +165,7 @@ module rv32g_hart
    always_ff @(posedge clk) begin
      if (!rstN) begin
        memwb_reg <= '0;
+       memwb_reg.pc <= BASE_ADDR;
      end else begin
        memwb_reg.alu_out <= exmem_reg.alu_out;
        memwb_reg.mem_out <= mem_mem_out;