rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
Log | Files | Refs | LICENSE

commit 32fe040d304c97cd13c82b9cd44e1fe5a0082245
parent f9320e371da369ef1b75e072dee542f86c6c12f4
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  8 Jun 2026 16:14:53 -0400

increase tb imem to 1K and dmem to 4K

Diffstat:
Mrtl/tb_rv32g.sv | 4++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv @@ -7,12 +7,12 @@ module tb_rv32g logic clk; logic rstN; - logic [31:0] imem [0:1023]; + logic [31:0] imem [0:2047]; logic [31:0] imem_addr; logic [31:0] imem_data; logic imem_valid; - logic [31:0] dmem [0:1023]; + logic [31:0] dmem [0:4095]; logic [31:0] dmem_addr; logic [31:0] dmem_data; logic dmem_valid;