rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit 34a9291bb58c54a908fd48f3f69abc9fd5ff62d6
parent 97385bda2d364514abda2a3df050a2122a88d572
Author: Vineet Kumar <git@vineetk.net>
Date:   Mon,  8 Jun 2026 15:07:18 -0400

fix faulty nop detection in decoding

this caused rv32ui-p-addi test to fail previously

Diffstat:
Mrtl/stage_decode.sv | 6+++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv @@ -219,13 +219,13 @@ module stage_decode SH: ctrl.memop = MEM_SH; SW: ctrl.memop = MEM_SW; ADDI: begin - if (imm != 'b0 && rs1_val != 'b0) begin - ctrl.aluop = ALU_ADD; - end else begin // handle nop by doing a nop + if (rd_num == 0 && rs1_num == 0 && imm == 0) begin // handle nop by doing a nop ctrl.aluop = ALU_NONE; ctrl.aluop1src = ALUOP1_NONE; ctrl.aluop2src = ALUOP2_NONE; ctrl.wbsrc = WB_NONE; + end else begin + ctrl.aluop = ALU_ADD; end end SLTI: ctrl.aluop = ALU_SLT;