rv32g-core

commit 3f985ccdd3b60c810fa0cd95a62f990cdbbef21c
parent 9ac7b30411ff32d47929d3a33f070f2c46696589
Author: Vineet Kumar <git@vineetk.net>
Date:   Fri, 24 Jul 2026 14:14:08 +0530

switch pipeline registers to sync reset

Diffstat:
M
rtl/rv32g_hart.sv
 | 
44
++++++++++++++++++++++----------------------

1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -85,7 +85,7 @@ module rv32g_hart
 			 .rs1_val(dec_rs1_val), .rs2_val(dec_rs2_val),
 			 .rd_num(dec_rd_num));
    // ID/EX pipeline register
-   always_ff @(posedge clk or negedge rstN) begin
+   always_ff @(posedge clk) begin
      if (!rstN) begin
        // NOP by default
        idex_reg <= '0;
@@ -130,21 +130,21 @@ module rv32g_hart
 			   .out(ex_alu_out),
 			   .branch_taken(ex_branch_taken));
    // EX/MEM pipeline register
-   always_ff @(posedge clk or negedge rstN) begin
+   always_ff @(posedge clk) begin
      if (!rstN) begin
-       exmem_reg = '0;
-       exmem_reg.pc = idex_reg.pc;
+       exmem_reg <= '0;
+       exmem_reg.pc <= idex_reg.pc;
      end else begin
-       exmem_reg.alu_out = ex_alu_out;
-       exmem_reg.rs2_val = idex_reg.rs2_val;
-       exmem_reg.pc = idex_reg.pc;
-       exmem_reg.imm = idex_reg.imm;
-       exmem_reg.rd_num = idex_reg.rd_num;
-       exmem_reg.branch_taken = ex_branch_taken;
-       exmem_reg.branchop = idex_reg.ctrl.branchop;
-       exmem_reg.memop = idex_reg.ctrl.memop;
-       exmem_reg.wbsrc = idex_reg.ctrl.wbsrc;
-       exmem_reg.pcsrc = idex_reg.ctrl.pcsrc;
+       exmem_reg.alu_out <= ex_alu_out;
+       exmem_reg.rs2_val <= idex_reg.rs2_val;
+       exmem_reg.pc <= idex_reg.pc;
+       exmem_reg.imm <= idex_reg.imm;
+       exmem_reg.rd_num <= idex_reg.rd_num;
+       exmem_reg.branch_taken <= ex_branch_taken;
+       exmem_reg.branchop <= idex_reg.ctrl.branchop;
+       exmem_reg.memop <= idex_reg.ctrl.memop;
+       exmem_reg.wbsrc <= idex_reg.ctrl.wbsrc;
+       exmem_reg.pcsrc <= idex_reg.ctrl.pcsrc;
      end
      // if (!dmem_valid && ctrl.memop != MEM_NONE) begin
      //   // TODO stall
@@ -162,16 +162,16 @@ module rv32g_hart
 		      .mem_out(mem_mem_out),
 		      .dmem_addr, .dmem_rdata, .dmem_wdata, .dmem_we, .dmem_be);
    // MEM/WB pipeline register
-   always_ff @(posedge clk or negedge rstN) begin
+   always_ff @(posedge clk) begin
      if (!rstN) begin
-       memwb_reg = '0;
+       memwb_reg <= '0;
      end else begin
-       memwb_reg.alu_out = exmem_reg.alu_out;
-       memwb_reg.mem_out = mem_mem_out;
-       memwb_reg.pc = exmem_reg.pc;
-       memwb_reg.imm = exmem_reg.imm;
-       memwb_reg.rd_num = exmem_reg.rd_num;
-       memwb_reg.wbsrc = exmem_reg.wbsrc;
+       memwb_reg.alu_out <= exmem_reg.alu_out;
+       memwb_reg.mem_out <= mem_mem_out;
+       memwb_reg.pc <= exmem_reg.pc;
+       memwb_reg.imm <= exmem_reg.imm;
+       memwb_reg.rd_num <= exmem_reg.rd_num;
+       memwb_reg.wbsrc <= exmem_reg.wbsrc;
      end
      // else ; // TODO I need to think of what else should happen
    end