rv32g-core

commit 43306a63fb75f3320de54b7909f6d2003cd1872a
parent 043c769061311f11e349da2aeeff74d7993d4656
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  2 Jun 2026 14:58:26 -0400

add nop

Diffstat:
M
rtl/stage_decode.sv
 | 
11
++++++++++-

1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -208,7 +208,16 @@ module stage_decode
        SB: ctrl.memop = MEM_SB;
        SH: ctrl.memop = MEM_SH;
        SW: ctrl.memop = MEM_SW;
-       ADDI: ctrl.aluop = ALU_ADD;
+       ADDI: begin
+	 if (imm != 'b0 && rs1_val != 'b0) begin
+	   ctrl.aluop = ALU_ADD;
+	 end else begin // handle nop by doing a nop
+	   ctrl.aluop = ALU_NONE;
+	   ctrl.aluop1src = ALUOP1_NONE;
+	   ctrl.aluop2src = ALUOP2_NONE;
+	   ctrl.wbsrc = WB_NONE;
+	 end
+       end
        SLTI: ctrl.aluop = ALU_SLT;
        SLTIU: ctrl.aluop = ALU_SLTU;
        XORI: ctrl.aluop = ALU_XOR;