rv32g-core

commit 043c769061311f11e349da2aeeff74d7993d4656
parent 2bd38ff833475a49673216b0d9f9f12d0bb643d6
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  2 Jun 2026 14:58:18 -0400

replace writeback for loop with foreach

Diffstat:
M
rtl/stage_writeback.sv
 | 
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rtl/stage_writeback.sv b/rtl/stage_writeback.sv
@@ -12,7 +12,7 @@ module stage_writeback
 
    always_ff @(posedge clk or negedge rstN) begin
      if (!rstN) begin
-       for (int i = 0; i < 32; i++) regfile[i] <= '0;
+       foreach (regfile[i]) regfile[i] <= '0;
      end else if (rd_num != 0) begin
        unique case (wbsrc)
 	 WB_NONE: ;