rv32g-core

commit 564723b1aa15d081506e9ebba9c05fd5a9da6296
parent f75f946e047adfd2344e183e6f2b4f31ea153180
Author: Vineet Kumar <git@vineetk.net>
Date:   Fri,  3 Jul 2026 21:19:15 +0530

exit simulation on EXC_ILL_INST again

Diffstat:
M
rtl/tb_rv32g.sv
 | 
5
+++--

1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv
@@ -71,8 +71,9 @@ module tb_rv32g
 		  .dmem_we, .dmem_be);
 
    always_ff @(posedge clk) begin
-//     if ((!imem_valid && rstN) || (cycle_cnt > 0 && exception == EXC_ILL_INST)) begin
-     if ((!imem_valid && rstN) || (cycle_cnt > 0 && imem_data == 32'b0)) begin
+     if ((!imem_valid && rstN) ||
+	 (cycle_cnt > 0 && imem_data == 32'b0) ||
+	 exception == EXC_ILL_INST) begin
        $finish();
      end
    end