rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit f75f946e047adfd2344e183e6f2b4f31ea153180
parent ff697575ef55ed75410e7966dd0db8e57b073162
Author: Vineet Kumar <git@vineetk.net>
Date:   Thu, 18 Jun 2026 16:58:45 -0400

increase icache depth to 8K words

Diffstat:
Mrtl/rv32g_pkg.sv | 4++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtl/rv32g_pkg.sv b/rtl/rv32g_pkg.sv @@ -1,7 +1,7 @@ package rv32g_pkg; parameter BASE_ADDR = 32'h8000_0000; - //parameter CACHE_DEPTH = 4096; - parameter CACHE_DEPTH = 64; + parameter CACHE_DEPTH = 8192; + //parameter CACHE_DEPTH = 64; typedef logic [31:0] reg_t;