rv32g-core

commit 5f15f69a4fa7550162b0f666e55801e102168c3d
parent 7bf7051954fa3b626c579b331b72f0078c6c8691
Author: Vineet Kumar <git@vineetk.net>
Date:   Wed, 10 Jun 2026 20:45:38 -0400

comment out unused async resets in hart to remove comb. rst LUTs

this reduced LUTs by nearly 4k and also increased fmax to 19 (from 17) and 29 (from 25) MHz for a
nice +15% boost by just doing tihs.

Diffstat:
M
rtl/rv32g_hart.sv
 | 
38
+++++++++++++++++---------------------

1 file changed, 17 insertions(+), 21 deletions(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -31,29 +31,23 @@ module rv32g_hart
    reg_t	mem_out;
    logic	branch_taken;
    
-   // FIXME slang complains about async sensitivity. can be removed if writeback's same reset has no issue.
-   // always_ff @(posedge clk or negedge rstN) begin
-   //   if (!rstN) begin
-   //     for (int i = 0; i < 32; i++) regfile[i] <= '0;
-   //   end
-   // end
-
    stage_fetch u_fetch(.clk, .rstN, .flush_i(ctrl.fence_flush), .pc, .imem_addr, .imem_data, .inst);
    always_ff @(posedge clk or negedge rstN) begin
      $display("IF:  pc: %h, next_pc: %h, imem_valid: %d, imem[%h]: %h, inst: %h", pc, next_pc, imem_valid, imem_addr, imem_data, inst);
      if (!rstN) pc <= BASE_ADDR;
      else if (imem_valid) pc <= next_pc;
-     else begin
-       // TODO (pipeline) IF/ID stall. if no instruction, just wait?
-     end
+     // else begin
+     //   // TODO (pipeline) IF/ID stall. if no instruction, just wait?
+     // end
    end
 
    stage_decode u_decode(.inst, .regfile, .ctrl, .imm, .rs1_val, .rs2_val, .rd_num);
    // TODO ID/EX pipeline register
-   always_ff @(posedge clk or negedge rstN) begin
+//   always_ff @(posedge clk or negedge rstN) begin
+   always_ff @(posedge clk) begin
      $display("ID:  inst: %h, ctrl: %h, imm: %h, rs1_val: %h, rs2_val: %h, rd_num: %d", inst, ctrl, imm, rs1_val, rs2_val, rd_num);
-     if (!rstN) ; // TODO reset pipeline register
-     else if (ctrl.exception != EXC_NONE) begin
+//     if (!rstN) ; // TODO reset pipeline register
+     if (ctrl.exception != EXC_NONE) begin
        // TODO handle exceptions
        unique case (ctrl.exception)
 	 EXC_NONE: ;
@@ -72,22 +66,24 @@ module rv32g_hart
 			   .out(alu_out),
 			   .imm, .pc, .rs1_val, .rs2_val, .branch_taken);
    // TODO EX/MEM pipeline register
-   always_ff @(posedge clk or negedge rstN) begin
+//   always_ff @(posedge clk or negedge rstN) begin
+   always_ff @(posedge clk) begin
      $display("EX:  op: %h, op1src: %d, op2src: %d, branchop: %d, out: %h, branch_taken: %d", ctrl.aluop, ctrl.aluop1src, ctrl.aluop2src, ctrl.branchop, alu_out, branch_taken);
-     if (!rstN) ; // TODO reset pipeline register
-     else if (!dmem_valid && ctrl.memop != MEM_NONE) begin
-       // TODO stall
-     end
+//     if (!rstN) ; // TODO reset pipeline register
+     // if (!dmem_valid && ctrl.memop != MEM_NONE) begin
+     //   // TODO stall
+     // end
    end
    // TODO stall when dmem_valid is 0 and ctrl.memop != 0. find out what else needs to be done in between stages
    
    stage_memory u_mem(.memop(ctrl.memop), .alu_out, .rs2_val,
 		      .dmem_addr, .dmem_rdata, .dmem_wdata, .dmem_we, .dmem_be, .mem_out);
    // TODO MEM/WB pipeline register
-   always_ff @(posedge clk or negedge rstN) begin
+//   always_ff @(posedge clk or negedge rstN) begin
+   always_ff @(posedge clk) begin
      $display("MEM: memop: %h, dmem_addr: %h, dmem_rdata: %h, dmem_wdata: %h, dmem_we: %d, dmem_be: %b, mem_out: %h", ctrl.memop, dmem_addr, dmem_rdata, dmem_wdata, dmem_we, dmem_be, mem_out);
-     if (!rstN) ; // TODO reset pipeline register
-     else ; // TODO I need to think of what else should happen
+     // if (!rstN) ; // TODO reset pipeline register
+     // else ; // TODO I need to think of what else should happen
    end
    // TODO find out what else needs to be done in between stages