commit 61d17e4035ae8cc359c1f812c5318e85e25a911b
parent 8211eeff31624249a8a6b65081b8f31f3fe0325e
Author: Vineet Kumar <git@vineetk.net>
Date: Sun, 31 May 2026 21:48:37 -0400
assign control signals for all non-SYSTEM RV32I instructions
they need me to find where in privileged isa defines what exceptions
I should raise and stuff
Diffstat:
| M | rtl/stage_decode.sv | | | 248 | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- |
1 file changed, 246 insertions(+), 2 deletions(-)
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -273,9 +273,253 @@ module stage_decode
// set control signals based on instruction name
always_comb begin
- case (name)
+ ctrl = '{aluop: ALU_NONE,
+ aluop1src: ALUOP1_NONE,
+ aluop2src: ALUOP2_NONE,
+ memop: MEM_NONE,
+ pcsrc: PC_SEQ,
+ branchop: BRANCH_NONE,
+ wbsrc: WB_NONE};
+ unique case (name)
// rv32i
- default: ctrl = {default:0};
+ LUI: ctrl.wbsrc = WB_IMM;
+ AUIPC: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_PC;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ JAL: begin
+ ctrl.pcsrc = PC_IMM;
+ ctrl.wbsrc = WB_PC;
+ end
+ JALR: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.pcsrc = PC_ALU;
+ ctrl.wbsrc = WB_PC;
+ end
+ BEQ: begin
+ ctrl.aluop = ALU_SUB;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.pcsrc = PC_IMM;
+ ctrl.branchop = BRANCH_BEQ;
+ end
+ BNE: begin
+ ctrl.aluop = ALU_SUB;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.pcsrc = PC_IMM;
+ ctrl.branchop = BRANCH_BNE;
+ end
+ BLT: begin
+ ctrl.aluop = ALU_SUB;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.pcsrc = PC_IMM;
+ ctrl.branchop = BRANCH_BLT;
+ end
+ BGE: begin
+ ctrl.aluop = ALU_SUB;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.pcsrc = PC_IMM;
+ ctrl.branchop = BRANCH_BGE;
+ end
+ BLTU: begin
+ ctrl.aluop = ALU_SUB;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.pcsrc = PC_IMM;
+ ctrl.branchop = BRANCH_BLTU;
+ end
+ BGEU: begin
+ ctrl.aluop = ALU_SUB;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.pcsrc = PC_IMM;
+ ctrl.branchop = BRANCH_BGEU;
+ end
+ LB: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.memop = MEM_LB;
+ ctrl.wbsrc = WB_MEM;
+ end
+ LH: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.memop = MEM_LH;
+ ctrl.wbsrc = WB_MEM;
+ end
+ LW: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.memop = MEM_LW;
+ ctrl.wbsrc = WB_MEM;
+ end
+ LBU: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.memop = MEM_LBU;
+ ctrl.wbsrc = WB_MEM;
+ end
+ LHU: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.memop = MEM_LHU;
+ ctrl.wbsrc = WB_MEM;
+ end
+ SB: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.memop = MEM_SB;
+ end
+ SH: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.memop = MEM_SH;
+ end
+ SW: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.memop = MEM_SW;
+ end
+ ADDI: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SLTI: begin
+ ctrl.aluop = ALU_SLT;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SLTIU: begin
+ ctrl.aluop = ALU_SLTU;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ XORI: begin
+ ctrl.aluop = ALU_XOR;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ ORI: begin
+ ctrl.aluop = ALU_OR;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ ANDI: begin
+ ctrl.aluop = ALU_AND;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SLLI: begin
+ ctrl.aluop = ALU_SLL;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SRLI: begin
+ ctrl.aluop = ALU_SRL;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SRAI: begin
+ ctrl.aluop = ALU_SRA;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_IMM;
+ ctrl.wbsrc = WB_ALU;
+ end
+ ADD: begin
+ ctrl.aluop = ALU_ADD;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SUB: begin
+ ctrl.aluop = ALU_SUB;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SLL: begin
+ ctrl.aluop = ALU_SLL;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SLT: begin
+ ctrl.aluop = ALU_SLT;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SLTU: begin
+ ctrl.aluop = ALU_SLTU;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ XOR: begin
+ ctrl.aluop = ALU_XOR;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SRL: begin
+ ctrl.aluop = ALU_SRL;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ SRA: begin
+ ctrl.aluop = ALU_SRA;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ OR: begin
+ ctrl.aluop = ALU_OR;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ AND: begin
+ ctrl.aluop = ALU_AND;
+ ctrl.aluop1src = ALUOP1_REG;
+ ctrl.aluop2src = ALUOP2_REG;
+ ctrl.wbsrc = WB_ALU;
+ end
+ // MISC-MEM instructions are basically NOPs
+ FENCE: ;
+ FENCE_TSO: ;
+ PAUSE: ;
+ // SYSTEM instructions do traps
+ ECALL: begin
+ ctrl.aluop = ALU_NONE;
+ end
+ EBREAK: begin
+ ctrl.aluop = ALU_NONE;
+ end
endcase
end
