rv32g-core

commit 6e3e57beecc47d358c5706f7eef0efc2ee64ea3d
parent dafb90c3fb697598b3c8972cc5602b5ffa24228b
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  9 Jun 2026 14:45:23 -0400

move unified memory read to be combinational for single-cycle

otherwise doing registered read on single-cycle instead of pipelined
causes rv32ui-p-fence_i to fail

Diffstat:
M
rtl/unified_memory.sv
 | 
6
+++++-

1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/rtl/unified_memory.sv b/rtl/unified_memory.sv
@@ -25,6 +25,11 @@ module unified_memory
 
      imem_data = (imem_idx < CACHE_DEPTH) ? mem[imem_idx] : '0;
      imem_valid = (imem_idx < CACHE_DEPTH) ? 1'b1 : 1'b0;
+
+     // TODO switch back to registered read once pipelined.
+     // single-cycle hart requires combinational same-cycle read.
+     // otherwise it causes tests like rv32ui-p-fence_i to fail.
+     dmem_rdata = (dmem_idx < CACHE_DEPTH) ? mem[dmem_idx] : '0;
    end
 
    always_ff @(posedge clk) begin
@@ -34,7 +39,6 @@ module unified_memory
          if (dmem_be[b]) mem[dmem_idx][b << 3 +: 8] <= dmem_wdata[b << 3 +: 8];
        end
      end
-     dmem_rdata <= (dmem_idx < CACHE_DEPTH) ? mem[dmem_idx] : '0;
    end
    
 endmodule