rv32g-core

commit 95b479231c2f5959608a338830ef10baa65446f7
parent da699fe51c52c7d42d4ed55683d322115117b376
Author: Vineet Kumar <git@vineetk.net>
Date:   Thu,  4 Jun 2026 18:33:22 -0400

replace casez with case inside

apparently latter replaced former in systemverilog

Diffstat:
M
rtl/stage_decode.sv
 | 
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -52,7 +52,7 @@ module stage_decode
 
    // parse what the actual instruction
    always_comb begin
-     casez ({funct7, funct3, opcode})
+     case ({funct7, funct3, opcode}) inside
        // rv32i
        {7'b???????, 3'b???, OPCODE_LUI}: name = LUI;
        {7'b???????, 3'b???, OPCODE_AUIPC}: name = AUIPC;