commit da699fe51c52c7d42d4ed55683d322115117b376
parent 4bef323217454349b806321de1a4fb30a4374b13
Author: Vineet Kumar <git@vineetk.net>
Date: Wed, 3 Jun 2026 16:06:36 -0400
add resources and LLM disclosure to README
Diffstat:
| M | README.org | | | 77 | ++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------- |
1 file changed, 52 insertions(+), 25 deletions(-)
diff --git a/README.org b/README.org
@@ -1,23 +1,21 @@
* rv32g-core
-This aims to be a fully pipelined, synthesizable RV32G (IMAFD +
-Zicsr + Zifencei extensions) RISC-V core written in
-SystemVerilog. It's designed as a passion project towards making a CPU
-of my very own, as part of a larger goal of making a portable computer
-with all ICs designed by me.
+This aims to be a fully pipelined, synthesizable RV32G (IMAFD + Zicsr + Zifencei
+extensions) RISC-V core written in SystemVerilog. It's designed as a passion
+project towards making a CPU of my very own, as part of a larger goal of making
+a portable computer with all ICs designed by me.
** Goals
-It will be implementing a standard-compliant RISC-V core without
-custom ISA extensions as per the RISC-V ISA Unprivileged Architecture
-Manual (Version 20260120). The design process would be starting with a
-minimal single-cycle RV32I core with verification through making a 5-7
-pipeline to adding full G-extension support. The core should be able
-to run at 250 MHz and have low power usage.
+It will be implementing a standard-compliant RISC-V core without custom ISA
+extensions as per the RISC-V ISA Unprivileged Architecture Manual (Version
+20260120). The design process would be starting with a minimal single-cycle
+RV32I core with verification through making a 5-7 pipeline to adding full
+G-extension support. The core should be able to run at 250 MHz and have low
+power usage.
Possibly the only thing I will include from the RISC-V ISA Privileged
-Architecture Manual is with regards to the SYSTEM instructions so that
-a more mainstream EEI like FreeRTOS and Linux (with enough memory)
-could potentially run on it. I may change my mind regarding this later
-on.
+Architecture Manual is with regards to the SYSTEM instructions so that a more
+mainstream EEI like FreeRTOS and Linux (with enough memory) could potentially
+run on it. I may change my mind regarding this later on.
*** ISA Support
- Base: RV32I (32-bit Integer Base ISA)
@@ -40,13 +38,42 @@ on.
9. SDRAM controller
** Target Platforms
-- FPGA: GW5A-LV25MG121 on a Sipeed Tang Primer 25K board (Yosys,
- nextpnr, openFPGALoader)
- - Has 23k LUTs and a silicon fabric of 300 MHz. I'm aiming for 200
- MHz at the minimum.
- - Would use the on-chip 1008Kb BSRAM and board's 2x32Mb SDRAM
- (Winbond W9825G6KH-6)
-- ASIC: SkyWater 130nm PDK via LibreLane Classic Flow (wraps Yosys and
- OpenROAD)
- - Would start tapeout of it after all goals met and using it faces
- no issues with FPGA
+- FPGA: GW5A-LV25MG121 on a Sipeed Tang Primer 25K board (Yosys, nextpnr,
+ openFPGALoader)
+ - Has 23k LUTs and a silicon fabric of 300 MHz. I'm aiming for 200 MHz at the
+ minimum.
+ - Would use the on-chip 1008Kb BSRAM and board's 2x32Mb SDRAM (Winbond
+ W9825G6KH-6)
+- ASIC: SkyWater 130nm PDK via LibreLane Classic Flow (wraps Yosys and OpenROAD)
+ - Would start tapeout of it after all goals met and using it faces no issues
+ with FPGA
+
+* Resources Used
+- [[https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf][RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version
+ 20260120)]]
+ - used as the source of truth for what the functionality should be and what to
+ include
+- [[https://docs.riscv.org/reference/isa/_attachments/riscv-privileged.pdf][RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Version
+ 20260120)]]
+ - for finding out some of the underspecified instructions should normally do
+ like the SYSTEM ones
+- Stuart Sutherland's [[https://sutherland-hdl.com/books_and_guides.html#RTL%20Book]["RTL Modeling with SystemVerilog For Simulation and
+ Synthesis: Using SystemVerilog for ASIC and FPGA Design"]]
+ - for properly learning SystemVerilog and its best practices since my
+ bachelor's courses did not teach Verilog well
+- Chris Spear's and Greg Tumbush's [[https://link.springer.com/book/10.1007/978-1-4614-0715-7]["SystemVerilog for Verification: A Guide to
+ Learning the Testbench Language Features"]]
+ - for properly learning how to make a testbench
+- David Patterson's and John Hennessy's "Computer Organization and Design: MIPS
+ Edition"
+ - this edition was used because I already owned it after taking my computer
+ architecture class (we didn't use the newer RISC-V edition)
+ - for understanding how the datapath would look like in a traditional RISC
+ architecture and how pipelining works
+- [[https://github.com/riscv-software-src/riscv-tests][Official RISC-V Unit Tests]]
+ - would later be used in the testbenches to verify the hart
+
+* LLM Disclosure
+No LLM assistance was used in the writing of any of the code, so that I could
+properly learn RTL and to take control of the actual design, not using other
+people's work without attribution.
