rv32g-core

commit ad9c2331c5cac454638c37f5cfaa7a8e21fe5636
parent cc90ca030e0a259c08c3594e8863a84ff8f3837b
Author: Vineet Kumar <git@vineetk.net>
Date:   Sun, 26 Jul 2026 16:26:42 +0530

stop using I-cache until I fix pipelining

Diffstat:
M
rtl/stage_fetch.sv
 | 
3
++-

1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/rtl/stage_fetch.sv b/rtl/stage_fetch.sv
@@ -7,7 +7,8 @@ module stage_fetch
    output logic [31:0] imem_addr,
    output logic [31:0] inst);
 
-`define USE_ICACHE // TODO ifdef can be removed once pipelined with BSRAM
+// FIXME currently extra cycle from BSRAM is not handled
+//`define USE_ICACHE // TODO ifdef can be removed once pipelined with BSRAM
 `ifdef USE_ICACHE
 
    localparam			    CACHE_SIZE = 256;		    // words