rv32g-core

commit cc90ca030e0a259c08c3594e8863a84ff8f3837b
parent ee09c9c5256dc0acdda766cd402000535e7ee169
Author: Vineet Kumar <git@vineetk.net>
Date:   Sun, 26 Jul 2026 16:26:14 +0530

exit sim on a 32'b0 after any real inst

Diffstat:
M
rtl/tb_rv32g.sv
 | 
8
+++++++-

1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv
@@ -105,7 +105,13 @@ module tb_rv32g
        endcase
      end
 
-     if (exception == EXC_ILL_INST && seen_first_real_inst) begin
+     // if (exception == EXC_ILL_INST && seen_first_real_inst) begin
+     //   $display("!!! Program terminated (exception ILL_INST at PC %h), inst: %h !!!",
+     // 		pc_out, dut.ifid_reg.inst);
+     //   $finish();
+     // end
+
+     if (exception == EXC_ILL_INST && seen_first_real_inst && dut.ifid_reg.inst == 32'b0) begin
        $display("!!! Program terminated (exception ILL_INST at PC %h), inst: %h !!!",
 		pc_out, dut.ifid_reg.inst);
        $finish();