rv32g-core

commit ca88f5c5782dfc55a075fdff71544eb389da85f8
parent 1384860501c9f2aa08e81a6a7754614107877ac8
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  9 Jun 2026 18:44:39 -0400

try fixing the icache's aliasing

Diffstat:
M
rtl/stage_fetch.sv
 | 
19
+++++++++++++------

1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/rtl/stage_fetch.sv b/rtl/stage_fetch.sv
@@ -9,14 +9,23 @@ module stage_fetch
 
    localparam		 CACHE_SIZE = 256; // words
    localparam		 IDX_WIDTH = $clog2(CACHE_SIZE);
+   localparam		 TAG_WIDTH = 32 - IDX_WIDTH - 2; // only be byte offset
 
    logic [31:0]		 cache [0:CACHE_SIZE-1];
    logic		 valid [0:CACHE_SIZE-1];
    logic [IDX_WIDTH-1:0] idx;
-   logic [31:0]		 cached_inst;
+   logic [TAG_WIDTH-1:0] tag_mem [0:CACHE_SIZE-1];
+   logic [TAG_WIDTH-1:0] tag_pc;
+   logic		 hit;
 
-   assign imem_addr = pc;
-   assign idx = pc[IDX_WIDTH+1:2];
+   always_comb begin
+     imem_addr = pc;
+     idx = pc[IDX_WIDTH+1:2];
+     tag_pc = pc[31:IDX_WIDTH+2];
+
+     hit = valid[idx] && (tag_mem[idx] == tag_pc);
+     inst = (hit) ? cache[idx] : imem_data;
+   end
 
    always_ff @(posedge clk or negedge rstN) begin
      if (!rstN) begin // async flush
@@ -26,12 +35,10 @@ module stage_fetch
      end else begin // cache miss :(
        if (!valid[idx] || cache[idx] !== imem_data) begin
          cache[idx] <= imem_data;
+	 tag_mem[idx] <= tag_pc;
          valid[idx] <= 1;
        end
      end
    end
 
-   assign cached_inst = valid[idx] ? cache[idx] : imem_data;
-   assign inst = cached_inst;
-
 endmodule: stage_fetch