rv32g-core

commit 1384860501c9f2aa08e81a6a7754614107877ac8
parent 6e3e57beecc47d358c5706f7eef0efc2ee64ea3d
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  9 Jun 2026 18:44:22 -0400

implement better testing infrastructure

Diffstat:
M
.gitignore
 | 
1
+
A
.gitmodules
 | 
3
+++
M
Makefile
 | 
87
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------
D
rom.txt
 | 
287
-------------------------------------------------------------------------------
M
rtl/tb_rv32g.sv
 | 
7
+++++--
A
tests/elf2hex
 | 
12
++++++++++++
A
tests/riscv-tests
 | 
1
+

7 files changed, 85 insertions(+), 313 deletions(-)
diff --git a/.gitignore b/.gitignore
@@ -1,2 +1,3 @@
 #*
 obj_dir
+tests/.test_list
diff --git a/.gitmodules b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "tests/riscv-tests"]
+	path = tests/riscv-tests
+	url = https://github.com/riscv-software-src/riscv-tests/
diff --git a/Makefile b/Makefile
@@ -1,44 +1,83 @@
 SRCDIR := rtl
 OBJDIR := obj_dir
 
-PKG_SRC := ${SRCDIR}/rv32g_pkg.sv
-TB_SRC := ${SRCDIR}/tb_rv32g.sv
-SV_SRCS := ${SRCDIR}/rv32g_hart.sv ${wildcard ${SRCDIR}/stage_*.sv} ${SRCDIR}/unified_memory.sv
+PKG_SRC   := ${SRCDIR}/rv32g_pkg.sv
+TB_SRC    := ${SRCDIR}/tb_rv32g.sv
+SV_SRCS   := ${SRCDIR}/rv32g_hart.sv ${wildcard ${SRCDIR}/stage_*.sv} ${SRCDIR}/unified_memory.sv
+
+# tests
+TEST_DIR   := tests/riscv-tests/isa
+SIM        := $(OBJDIR)/Vtb_rv32g
+ELF2HEX    := tests/elf2hex
+LOG_DIR    := $(TEST_DIR)/logs
+TEST_LIST  := $(TEST_DIR)/test_list
+
+# main
+.PHONY: all lint synth sim_compile sim tests clean clean-tests
 
 all: lint synth
 
-lint: ${PKG_SRC} ${SV_SRCS}
+lint: $(PKG_SRC) $(SV_SRCS)
 	verilator --lint-only --timing \
 	    +1800-2023ext+.sv \
 	    --top tb_rv32g \
-	    ${PKG_SRC} ${TB_SRC} ${SV_SRCS}
+	    $(PKG_SRC) $(TB_SRC) $(SV_SRCS)
 
 synth:
-	yosys -m slang -p 'read_slang ${PKG_SRC} ${SV_SRCS}; synth_gowin -top rv32g_hart'
+	yosys -m slang -p 'read_slang $(PKG_SRC) $(SV_SRCS); synth_gowin -top rv32g_hart'
 
-sim_compile: lint ${PKG_SRC} ${TB_SRC} ${SV_SRCS}
+sim_compile: lint $(PKG_SRC) $(TB_SRC) $(SV_SRCS)
 	verilator --binary --exe --build --timing \
 	    --top tb_rv32g \
 	    -j 0 -o Vtb_rv32g \
 	    --trace-fst \
-	    ${PKG_SRC} ${TB_SRC} ${SV_SRCS}
+	    $(PKG_SRC) $(TB_SRC) $(SV_SRCS)
 
 sim: sim_compile
-	./${OBJDIR}/Vtb_rv32g
-
-tests: sim_compile
-	cd tests/isa && \
-	make XLEN=32 && \
-	rm -f *.dump && \
-	for i in rv32ui-*; do \
-	    riscv32-unknown-elf-objcopy -O binary $$i file.bin; \
-	    hexdump -v -e '1/4 "%08x\n"' file.bin >$$i.hex; \
-	    rm file.bin; \
-	done && \
-	for i in rv32ui-*.hex; do \
-	    echo $$i; \
-	    ../../${OBJDIR}/Vtb_rv32g $$i; \
-	done
+	./$(SIM)
+
+# tests
+$(TEST_DIR)/%.hex: $(TEST_DIR)/% | $(TEST_LIST)
+	find ${TEST_DIR} -type f -executable -exec $(ELF2HEX) {} \;
+
+$(TEST_DIR)/%.pass: $(TEST_DIR)/%.hex sim_compile
+	@mkdir -p $(LOG_DIR)
+	@printf "%20s: " $(basename $(notdir $<))
+	@pass=$$(readelf -s $(basename $<) | awk '/pass$$/ {print $$2}'); \
+	 fail=$$(readelf -s $(basename $<) | awk '/fail$$/ {print $$2}'); \
+	 $(SIM) +rom=$< > $(LOG_DIR)/$*.log; \
+	 if grep -q "^IF:  pc: $$fail" $(LOG_DIR)/$*.log; then \
+	     echo "fail"; \
+	 elif grep -q "^IF:  pc: $$pass" $(LOG_DIR)/$*.log; then \
+	     echo "pass"; \
+	 else \
+	     echo "ERROR (neither pass nor fail address reached)"; \
+	     exit 1; \
+	 fi
+	@touch $@
+
+$(TEST_LIST):
+	@cd $(TEST_DIR) && \
+	$(MAKE) -k XLEN=32 || true && \
+	$(RM) *.dump && \
+	names=$$(for f in rv32ui-*; do \
+	          [ -f "$$f" ] && [ ! "$$f" = "*.dump" ] && echo "$${f}"; \
+	        done | tr '\n' ' ') && \
+	echo "TEST_NAMES := $$names" > $(notdir $@)
+
+-include $(TEST_LIST)
+TEST_TARGETS := $(addprefix $(TEST_DIR)/,$(addsuffix .pass,$(TEST_NAMES)))
+
+# build and run all tests
+.PHONY: tests
+tests: $(TEST_LIST) $(TEST_TARGETS)
+	@echo ${TEST_LIST}
+	@echo "All tests ran."
+
+# clean
+clean-tests:
+	$(RM) $(TEST_DIR)/*.hex $(TEST_DIR)/*.pass $(TEST_DIR)/*.log $(TEST_LIST)
 
 clean:
-	rm -rf ${OBJDIR}
+	rm -rf $(OBJDIR)
+	$(MAKE) clean-tests
diff --git a/rom.txt b/rom.txt
@@ -1,287 +0,0 @@
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-01428293
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-00200193
-00000693
-00068713
-00000393
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-00300193
-00100693
-00168713
-00200393
-26771263
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-80068713
-800003b7
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-00000693
-7ff68713
-7ff00393
-1e771e63
-00900193
-800006b7
-fff68693
-00068713
-800003b7
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-7ff38393
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-00000693
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-fff00393
-16771e63
-00e00193
-fff00693
-00168713
-00000393
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-00f00193
-fff00693
-fff68713
-ffe00393
-14771a63
-01000193
-800006b7
-fff68693
-00168713
-800003b7
-12771e63
-01100193
-00d00593
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-01800393
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-01200193
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-00000013
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-fe5212e3
-01600393
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-00000213
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-fe5216e3
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diff --git a/rtl/tb_rv32g.sv b/rtl/tb_rv32g.sv
@@ -23,6 +23,8 @@ module tb_rv32g
 
    exception_t	exception;
 
+   string	rom_filename;
+
    // debug stuff
    int		cycle_cnt = 0;
 
@@ -34,8 +36,9 @@ module tb_rv32g
    end
 
    initial begin
-     $display("Reading rom.txt");
-     $readmemh("rom.txt", u_mem.mem);
+     if (!$value$plusargs("rom=%s", rom_filename)) rom_filename = "rom.txt";
+     $display("Reading rom from %s", rom_filename);
+     $readmemh(rom_filename, u_mem.mem);
 
      rstN = 0;
      imem_addr = 0;
diff --git a/tests/elf2hex b/tests/elf2hex
@@ -0,0 +1,12 @@
+#!/bin/sh
+riscv32-unknown-elf-objcopy -O verilog --verilog-data-width=4 "${1}" file.bin;
+awk '
+  /^@/ {
+    base = 0x20000000
+    addr = strtonum("0x" substr($0,2))
+    idx = addr - base
+    printf "@%X\n", idx
+    next
+  }
+  { gsub(/ /, "\n"); print }' file.bin >"${1}".hex
+rm file.bin
diff --git a/tests/riscv-tests b/tests/riscv-tests
@@ -0,0 +1 @@
+Subproject commit 34e6b6d1e7936b526075432fb730d89148623484