commit ee09c9c5256dc0acdda766cd402000535e7ee169
parent 3f985ccdd3b60c810fa0cd95a62f990cdbbef21c
Author: Vineet Kumar <git@vineetk.net>
Date: Fri, 24 Jul 2026 14:14:17 +0530
remove erroneous basic pipelining complete mention in readme
It's not done yet, it still has errors that need to be ironed out.
Diffstat:
1 file changed, 0 insertions(+), 3 deletions(-)
diff --git a/README.org b/README.org
@@ -66,9 +66,6 @@ run on it. I may change my mind regarding this later on.
- July 8, 2026: Zicsr and PRIV-MRET Completed
- clock speed and LUT4s after PnR (cache_depth=64):
- With instruction memory cache: ~40.3 MHz, 154.7k LUT4, 8440 RAM16SDP4
-- July 12, 2026: Basic 5-stage Pipeline Completed
- - clock speed and LUT4s after PnR (cache_depth=8192)
- - With instruction memory cache: ~203.9 MHz, 929 LUT4, 8 RAM16SDP4, 1 BSRAM
* Resources Used
- [[https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf][RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (Version
