rv32g-core

commit dce248adc7f59090c3035d6d395da4c0f9bbef72
parent ca88f5c5782dfc55a075fdff71544eb389da85f8
Author: Vineet Kumar <git@vineetk.net>
Date:   Tue,  9 Jun 2026 19:01:06 -0400

write data memory according to the byte location

Diffstat:
M
rtl/stage_memory.sv
 | 
32
++++++++++++++++++++++++--------

1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/rtl/stage_memory.sv b/rtl/stage_memory.sv
@@ -44,20 +44,36 @@ module stage_memory
        MEM_LHU: mem_out = {16'b0, hdata};
        MEM_SB: begin
 	 unique case (alu_out[1:0])
-	   2'b00: dmem_be = 4'b0001;
-	   2'b01: dmem_be = 4'b0010;
-	   2'b10: dmem_be = 4'b0100;
-	   2'b11: dmem_be = 4'b1000;
+	   2'b00: begin
+	     dmem_be = 4'b0001;
+	     dmem_wdata = {24'b0, rs2_val[7:0]};
+	   end
+	   2'b01: begin
+	     dmem_be = 4'b0010;
+	     dmem_wdata = {16'b0, rs2_val[7:0], 8'b0};
+	   end
+	   2'b10: begin
+	     dmem_be = 4'b0100;
+	     dmem_wdata = {8'b0, rs2_val[7:0], 16'b0};
+	   end
+	   2'b11: begin
+	     dmem_be = 4'b1000;
+	     dmem_wdata = {rs2_val[7:0], 24'b0};
+	   end
 	 endcase
-	 dmem_wdata = rs2_val;
 	 dmem_we = 1;
        end
        MEM_SH: begin
 	 unique case (alu_out[1])
-	   1'b0: dmem_be = 4'b0011;
-	   1'b1: dmem_be = 4'b1100;
+	   1'b0: begin
+	     dmem_be = 4'b0011;
+	     dmem_wdata = {16'b0, rs2_val[15:0]};
+	   end
+	   1'b1: begin
+	     dmem_be = 4'b1100;
+	     dmem_wdata = {rs2_val[15:0], 16'b0};
+	   end
 	 endcase
-	 dmem_wdata = rs2_val;
 	 dmem_we = 1;
        end
        MEM_SW: begin