rv32g-core

commit dd7a05cc0e99dde0c7c9db643ffbe2bacf84d186
parent 81967b075efc78e269e45871a96782d240537724
Author: Vineet Kumar <git@vineetk.net>
Date:   Sun, 31 May 2026 16:48:01 -0400

switch decoding to using major opcode enum

Diffstat:
M
rtl/stage_decode.sv
 | 
59
+++++++++++++++++++++++++++++++++++++++++++++++------------

1 file changed, 47 insertions(+), 12 deletions(-)
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -17,6 +17,7 @@ module stage_decode
      inst_type_t;
 
    typedef enum {INVALID,
+		 // rv32i
 		 LUI,
 		 AUIPC,
 		 JAL,
@@ -60,11 +61,45 @@ module stage_decode
 		 EBREAK}
      inst_name_t;
 
+   // based off of Unprivileged ISA Chapter 36 Table 72 (no reserved)
+   typedef enum logic [6:0] {OPCODE_INVALID = 'b0000000,
+			     // rv32i/m
+			     OPCODE_LOAD = 'b0000011,
+			     OPCODE_STORE = 'b0100011,
+			     OPCODE_BRANCH = 'b1100011,
+			     OPCODE_JALR = 'b1100111,
+			     OPCODE_JAL = 'b1101111,
+			     OPCODE_MISC_MEM = 'b0001111,
+			     OPCODE_OP_IMM = 'b0010011,
+			     OPCODE_OP = 'b0110011,
+			     OPCODE_SYSTEM = 'b1110011,
+			     OPCODE_AUIPC = 'b0010111,
+			     OPCODE_LUI = 'b0110111,
+			     // rv32f/d
+			     OPCODE_LOAD_FP = 'b0000111,
+			     OPCODE_STORE_FP = 'b0100111,
+			     OPCODE_OP_FP = 'b1010011,
+			     OPCODE_MADD = 'b1000011,
+			     OPCODE_MSUB = 'b1000111,
+			     OPCODE_NMADD = 'b1001111,
+			     OPCODE_NMSUB = 'b1001011,
+			     // rv32a
+			     OPCODE_AMO = 'b0101111,
+			     // rv32v
+			     OPCODE_OP_V = 'b1010111,
+			     OPCODE_OP_VE = 'b1110111,
+			     // custom
+			     OPCODE_CUSTOM_0 = 'b0001011,
+			     OPCODE_CUSTOM_1 = 'b0101011,
+			     OPCODE_CUSTOM_2 = 'b1011011,
+			     OPCODE_CUSTOM_3 = 'b1111011}
+				    opcode_t;
+
    logic [6:0]	funct7 = inst[31:25];
    logic [4:0]	rs2_num = inst[24:20];
    logic [4:0]	rs1_num = inst[19:15];
    logic [2:0]	funct3 = inst[14:12];
-   logic [6:0]	opcode = inst[6:0];;
+   opcode_t	opcode = opcode_t'(inst[6:0]);
    inst_type_t  inst_type;
    inst_name_t  name;
 
@@ -74,17 +109,17 @@ module stage_decode
    always_comb begin
      unique case (opcode)
        // rv32i
-       'b0000011: inst_type = ITYPE;
-       'b0001111: inst_type = ITYPE;
-       'b0010011: inst_type = ITYPE;
-       'b0010111: inst_type = ITYPE;
-       'b0100011: inst_type = STYPE;
-       'b0110011: inst_type = RTYPE;
-       'b0110111: inst_type = ITYPE;
-       'b1100011: inst_type = BTYPE;
-       'b1100111: inst_type = ITYPE;
-       'b1101111: inst_type = JTYPE;
-       'b1110011: inst_type = ITYPE;
+       OPCODE_OP: inst_type = RTYPE;
+       OPCODE_OP_IMM: inst_type = ITYPE;
+       OPCODE_AUIPC: inst_type = ITYPE;
+       OPCODE_LUI: inst_type = ITYPE;
+       OPCODE_BRANCH: inst_type = BTYPE;
+       OPCODE_JAL: inst_type = JTYPE;
+       OPCODE_JALR: inst_type = ITYPE;
+       OPCODE_LOAD: inst_type = ITYPE;
+       OPCODE_STORE: inst_type = STYPE;
+       OPCODE_MISC_MEM: inst_type = ITYPE;
+       OPCODE_SYSTEM: inst_type = ITYPE;
        default: inst_type = INVALIDTYPE;
      endcase
    end