rv32g-core

commit 81967b075efc78e269e45871a96782d240537724
parent 7efe51f2eeacbb4b6b0d533e3384317b3fed7585
Author: Vineet Kumar <git@vineetk.net>
Date:   Sun, 31 May 2026 15:58:30 -0400

start working on decoding logic

Diffstat:
M
rtl/rv32g_hart.sv
 | 
12
++++++++----
A
rtl/stage_decode.sv
 | 
108
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

2 files changed, 116 insertions(+), 4 deletions(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -11,10 +11,12 @@ module rv32g_hart
    output logic [31:0] dmem_wdata,
    output logic	       dmem_we);
 
+   typedef logic [31:0] reg_t;
+
    // x0 to x31
-   logic [31:0] regfile [0:31];
-   logic [31:0]	pc;
-   logic [31:0] next_pc;
+   reg_t regfile [0:31];
+   reg_t	pc;
+   reg_t next_pc;
    logic [31:0] inst;
    logic	ctrl;	// TODO change to struct
    
@@ -33,7 +35,9 @@ module rv32g_hart
      end
    end
 
-   // TODO stage_decode  u_decode(.*);
+   stage_decode u_decode(.inst, .regfile, .ctrl, .imm, .rs1_val, .rs2_val, .rd_num);
+
+
    // TODO stage_execute u_execute(.*);
    // TODO stage_mem     u_mem(.*);
    // TODO stage_wb      u_wb(.*);
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -0,0 +1,108 @@
+module stage_decode
+  (input logic [31:0]  inst,
+   input logic [31:0]  regfile [0:31],
+   output logic [31:0] ctrl,
+   output logic [31:0] imm,
+   output logic [31:0] rs1_val,
+   output logic [31:0] rs2_val,
+   output logic [4:0]  rd_num);
+
+   typedef enum logic [3:0] {INVALIDTYPE,
+			     RTYPE,
+			     ITYPE,
+			     STYPE,
+			     BTYPE,
+			     UTYPE,
+			     JTYPE}
+     inst_type_t;
+
+   typedef enum {INVALID,
+		 LUI,
+		 AUIPC,
+		 JAL,
+		 JALR,
+		 BEQ,
+		 BNE,
+		 BLT,
+		 BGE,
+		 BLTU,
+		 BGEU,
+		 LB,
+		 LH,
+		 LBU,
+		 LHU,
+		 SB,
+		 SH,
+		 SW,
+		 ADDI,
+		 SLTI,
+		 SLTIU,
+		 XORI,
+		 ORI,
+		 ANDI,
+		 SLLI,
+		 SRLI,
+		 SRAI,
+		 ADD,
+		 SUB,
+		 SLL,
+		 SLT,
+		 SLTU,
+		 XOR,
+		 SRL,
+		 SRA,
+		 OR,
+		 AND,
+		 FENCE,
+		 FENCE_TSO,
+		 PAUSE,
+		 ECALL,
+		 EBREAK}
+     inst_name_t;
+
+   logic [6:0]	funct7 = inst[31:25];
+   logic [4:0]	rs2_num = inst[24:20];
+   logic [4:0]	rs1_num = inst[19:15];
+   logic [2:0]	funct3 = inst[14:12];
+   logic [6:0]	opcode = inst[6:0];;
+   inst_type_t  inst_type;
+   inst_name_t  name;
+
+   assign rd_num = inst[11:7];
+
+   // parse the type for each instruction
+   always_comb begin
+     unique case (opcode)
+       // rv32i
+       'b0000011: inst_type = ITYPE;
+       'b0001111: inst_type = ITYPE;
+       'b0010011: inst_type = ITYPE;
+       'b0010111: inst_type = ITYPE;
+       'b0100011: inst_type = STYPE;
+       'b0110011: inst_type = RTYPE;
+       'b0110111: inst_type = ITYPE;
+       'b1100011: inst_type = BTYPE;
+       'b1100111: inst_type = ITYPE;
+       'b1101111: inst_type = JTYPE;
+       'b1110011: inst_type = ITYPE;
+       default: inst_type = INVALIDTYPE;
+     endcase
+   end
+
+   // parse the (sign-extended) immediate value
+   // based off of Unprivileged ISA Section 2.3 Figure 1
+   always_comb begin
+     unique case (inst_type)
+       ITYPE: imm = {{20{inst[31]}}, inst[31:20]};
+       STYPE: imm = {{20{inst[31]}}, inst[31:25], inst[11:7]};
+       BTYPE: imm = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], '0};
+       UTYPE: imm = inst[31:12] << 12;
+       JTYPE: imm = {{12{inst[31]}}, inst[19:12], inst[20], inst[30:25], inst[24:21], '0};
+       default: imm = '0;
+     endcase
+   end
+
+   assign rs1_val = regfile[rs1_num];
+   assign rs2_val = regfile[rs2_num];
+
+endmodule: stage_decode