rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit e430c49fa9aa74e23e9aaea96bb9a88ede26115b
parent 8b56d0a6a6b0256eff987ce8fa89a176d9fc6738
Author: Vineet Kumar <git@vineetk.net>
Date:   Sat, 11 Jul 2026 14:56:15 +0530

ignore rom.txt in .gitignore

Diffstat:
M.gitignore | 1+
1 file changed, 1 insertion(+), 0 deletions(-)

diff --git a/.gitignore b/.gitignore @@ -5,3 +5,4 @@ design.json design_pnr.json *.rpt runs/ +rom.txt