rv32g-core

Pipelined, synthesizable, and fabricable RISC-V core in SystemVerilog+Yosys+OpenROAD
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commit e47093efc32ef69a2bdc66a837d437e1958bd158
parent 364ec7627b3932d642f2b4bf813b7493e721ed1e
Author: Vineet Kumar <git@vineetk.net>
Date:   Sat, 11 Jul 2026 18:30:16 +0530

make unified memory have registered reads again

Diffstat:
Mrtl/unified_memory.sv | 15++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/rtl/unified_memory.sv b/rtl/unified_memory.sv @@ -23,18 +23,15 @@ module unified_memory always_comb begin imem_idx = (imem_addr - BASE_ADDR) >> 2; dmem_idx = (dmem_addr - BASE_ADDR) >> 2; - - imem_data = (imem_idx < CACHE_DEPTH) ? mem[imem_idx] : '0; - imem_valid = (imem_idx < CACHE_DEPTH) ? 1'b1 : 1'b0; - - // TODO switch back to registered read once pipelined. - // single-cycle hart requires combinational same-cycle read. - // otherwise it causes tests like rv32ui-p-fence_i to fail. - dmem_rdata = (dmem_idx < CACHE_DEPTH) ? mem[dmem_idx] : '0; - dmem_valid = (dmem_idx < CACHE_DEPTH) ? 1'b1 : 1'b0; end always_ff @(posedge clk) begin + imem_valid <= (imem_idx < CACHE_DEPTH) ? 1'b1 : 1'b0; + dmem_valid <= (dmem_idx < CACHE_DEPTH) ? 1'b1 : 1'b0; + + imem_data <= (imem_idx < CACHE_DEPTH) ? mem[imem_idx] : '0; + dmem_rdata <= (dmem_idx < CACHE_DEPTH) ? mem[dmem_idx] : '0; + // for self-modifying memory if (dmem_we && dmem_idx < CACHE_DEPTH) begin for (int b = 0; b < 4; b++) begin