rv32g-core

commit 364ec7627b3932d642f2b4bf813b7493e721ed1e
parent a5c4877aa2e01078002f5d1d3ed3fbe73578e005
Author: Vineet Kumar <git@vineetk.net>
Date:   Sat, 11 Jul 2026 18:30:05 +0530

fix synth errors

Diffstat:
M
rtl/rv32g_hart.sv
 | 
16
+++++++++++-----
M
rtl/stage_decode.sv
 | 
1
+

2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -107,7 +107,9 @@ module rv32g_hart
        idex_reg.rd_num <= dec_rd_num;
        idex_reg.csr_addr <= dec_csr_addr;
      end
+   end
 
+   always_ff @(posedge clk) begin
      if (idex_reg.ctrl.exception != EXC_NONE) begin
        // TODO handle exceptions. might need moving.
        unique case (idex_reg.ctrl.exception)
@@ -145,10 +147,12 @@ module rv32g_hart
 			   .csr_out(exmem_reg.csr_out));
    // EX/MEM pipeline register
    always_ff @(posedge clk or negedge rstN) begin
-     $display("EX:  op: %h, op1src: %d, op2src: %d, branchop: %d, out: %h, branch_taken: %d",
-	      idex_reg.ctrl.aluop, idex_reg.ctrl.aluop1src, idex_reg.ctrl.aluop2src,
-	      idex_reg.ctrl.branchop, exmem_reg.alu_out, exmem_reg.branch_taken);
      if (!rstN) exmem_reg = '0;
+     else begin
+       $display("EX:  op: %h, op1src: %d, op2src: %d, branchop: %d, out: %h, branch_taken: %d",
+		idex_reg.ctrl.aluop, idex_reg.ctrl.aluop1src, idex_reg.ctrl.aluop2src,
+		idex_reg.ctrl.branchop, exmem_reg.alu_out, exmem_reg.branch_taken);
+     end
      // if (!dmem_valid && ctrl.memop != MEM_NONE) begin
      //   // TODO stall
      // end
@@ -167,9 +171,11 @@ module rv32g_hart
 		      .dmem_addr, .dmem_rdata, .dmem_wdata, .dmem_we, .dmem_be);
    // MEM/WB pipeline register
    always_ff @(posedge clk or negedge rstN) begin
-     $display("MEM: memop: %h, dmem_addr: %h, dmem_rdata: %h, dmem_wdata: %h, dmem_we: %d, dmem_be: %b, mem_out: %h",
-	      exmem_reg.memop, dmem_addr, dmem_rdata, dmem_wdata, dmem_we, dmem_be, memwb_reg.mem_out);
      if (!rstN) memwb_reg = '0;
+     else begin
+       $display("MEM: memop: %h, dmem_addr: %h, dmem_rdata: %h, dmem_wdata: %h, dmem_we: %d, dmem_be: %b, mem_out: %h",
+		exmem_reg.memop, dmem_addr, dmem_rdata, dmem_wdata, dmem_we, dmem_be, memwb_reg.mem_out);
+     end
      // else ; // TODO I need to think of what else should happen
    end
    // TODO find out what else needs to be done in between stages
diff --git a/rtl/stage_decode.sv b/rtl/stage_decode.sv
@@ -159,6 +159,7 @@ module stage_decode
 	      exception:   EXC_NONE,
 	      fence_flush: 1'b0,
 	      is_mret:     1'b0};
+     csr_addr = '0;
 
      // the major opcodes share the same signals, just operation varies based on funct
      unique case (opcode)