rv32g-core

commit f3051150934a71265497e9b012df43c53349aca4
parent fe8d12d6d81cb3e47b2308224cec6d855cdd6e5c
Author: Vineet Kumar <git@vineetk.net>
Date:   Thu, 28 May 2026 23:01:02 -0400

add skeleton hart's top-level module with regfile

Diffstat:
A
rtl/rv32g_hart.sv
 | 
31
+++++++++++++++++++++++++++++++

1 file changed, 31 insertions(+), 0 deletions(-)
diff --git a/rtl/rv32g_hart.sv b/rtl/rv32g_hart.sv
@@ -0,0 +1,31 @@
+module rv32g_hart
+  (input logic	       clk,
+   input logic	       rstN,
+
+   output logic [31:0] imem_addr,
+   input logic [31:0]  imem_data,
+
+   output logic [31:0] dmem_addr,
+   input logic [31:0]  dmem_data,
+   output logic [31:0] dmem_wdata,
+   output logic	       dmem_we);
+
+   // x0 to x31
+   logic [31:0][31:0] regfile;
+   logic [31:0]	      pc;
+
+   // x0 is hardwired to 0
+   always_comb regfile[0] = 'd0;
+
+   always_ff @(posedge clk or negedge rstN) begin
+     if (!rstN);		// TODO handle reset stuff
+     else begin
+       // TODO instruction fetch
+       // TODO instruction decode
+       // TODO execution
+       // TODO memory
+       // TODO register writeback
+     end
+   end
+
+endmodule: rv32g_hart