70937cd61f
replace tabs with spaces to better match nestest.log
2024-07-20 20:27:55 -04:00
ca5a09cd94
fix warnings and move cpu registers+flags to header
2024-07-07 13:04:16 -04:00
3e0563ce05
add nestest.nes and log that was used for testing the CPU
2024-07-04 15:19:45 -04:00
e1cdd73868
implement all of the nestest unofficial opcodes and fix branch cycles
2024-07-04 15:06:15 -04:00
4ccf9f5cee
add preliminary implementation of the unofficial opcodes
2024-07-04 14:17:40 -04:00
c4fc40a036
start implementing unofficial opcodes
2024-07-04 12:11:53 -04:00
5cd467eaf6
achieve cycle accuracy for official opcodes
...
Now, the unofficial opcodes can be implemented, and then the PPU and
APU.
2024-07-04 11:18:38 -04:00
d57acb77c7
finalize trace logging to match nestest.log minus PPU cycles
2024-07-03 21:49:27 -04:00
4fcc8d48f4
improve branching cycle accuracy
2024-07-03 20:40:57 -04:00
2236e79556
fix SBC bug in the rewrite and improve logging
2024-07-03 19:56:36 -04:00
d8bb5a5ccf
call opcode function pointer instead of using switch case
...
Also improve logging.
2024-07-03 19:22:00 -04:00
a4b39966ae
start refactoring opcode defs into an array
2024-06-30 19:10:29 -04:00
f28733401e
combine macro for updating N and Z status flags
2024-06-30 15:46:25 -04:00
47b8fac273
fix alignment of logging with ABS_X and ZP_X
2024-06-30 15:20:30 -04:00
4525490beb
fix indirect JMP bug where the high byte does not increment out of page
...
https://old.reddit.com/r/EmuDev/comments/15plfes/having_an_issue_with_nestest_on_my_6502_emulator/jvyck7k/
With this, it seems that all official opcodes run as nestest expects.
Now, it's the unofficial opcodes that need to be implemented.
2024-06-30 15:20:03 -04:00
718f89c9c5
fix incorrect argument for INC
...
Perhaps a refactor is in order for the arguments to the opcodes.
2024-06-30 09:54:05 -04:00
30fe238d42
rename README to README.md
2024-06-30 09:37:31 -04:00
45c2312976
fix incorrect argument for ASL and LSR
2024-06-30 08:58:20 -04:00
99082b5528
fix JSR, RTS, and RTI
...
JSR was pushing 1 too high PC and RTS was 1 too low
RTI was only pulling the low byte of PC
2024-06-30 07:56:08 -04:00
5535e5de70
change SBC to be ADC with one's complement instead of two's
...
It seems that is what was expected when run with nestest.
2024-06-30 06:28:41 -04:00
4b7fae0010
fix status flag ordering shenanigans
2024-06-29 09:51:49 -04:00
5d36aeb885
fix ADC bug where V is calculated with new A instead of old A
2024-06-29 09:51:12 -04:00
f16ab6cb6d
fix status register to match nestest
2024-06-28 18:15:37 -04:00
3977ab2a5d
improve logging and JMP indirect
2024-06-28 18:15:34 -04:00
c1a42045e6
fix more bugs
2024-06-28 10:28:53 -04:00
09692f45f6
fix JSR and RTS bug
...
The stack's PUSH and PULL weren't proper and JSR was reading wrong
argument it seems.
2024-06-28 10:18:01 -04:00
3ebdeab784
start logging instructions as nestest.log has done
2024-06-28 10:17:37 -04:00
6a5b0b728e
start fixing bugs with memory access
...
So this is why tests should be written while writing the program
and instructions instead of all at once later. If this were all to be
rewritten (which it probably will), I should add tests for each opcode
instead of waiting until the end for ROM loading support.
2024-06-17 15:11:45 +05:30
77d37dd455
implement basic iNES and Mapper 0 ROM loading
...
It seems like the test ROM loads fine but the instructions are not,
but that's exactly what the test ROM is for I suppose.
2024-06-17 14:46:46 +05:30
1f6e3b054c
replace bit comparisons with 0 from greater than to not equal
...
They're both the same and the compiler might have already optimized it
away. It also conveys the message better in my opinion.
2024-06-16 17:11:51 +05:30
745496ccd1
add memory mirroring for system and ppu memory
2024-06-11 15:38:58 +05:30
44273e69b9
add separate implied/accumulator functions for certain opcodes
2024-06-11 15:08:53 +05:30
142e35ff69
remove opcode json converter helper scripts
...
They were only used to automate writing the boilerplate for each
instruction. They're not needed at the moment and they were using
65c02 instructions instead of 6502 anyways.
2024-06-11 14:43:41 +05:30
a3189d90af
add jsr, rti, rts
2024-06-10 23:27:14 +05:30
3412a03a5e
implement untested most of stack-related opcodes
2024-06-10 23:27:11 +05:30
dbb952a52b
add lsr, rol, ror
2024-06-10 14:33:12 +05:30
ebdf50cdf3
implement tay, txa, tya
2024-06-10 14:28:13 +05:30
454276a50c
implement sta, stx, sty
2024-06-10 14:28:13 +05:30
e07d5917a1
implement se?() opcodes and remove extra 65c02 opcodes
2024-06-10 14:28:07 +05:30
23008662ce
implement more instructions
2024-06-09 22:50:33 +05:30
68ecbce235
add opcode_mem() function to return memory address and not pre-peek
...
Of course all of these opcodes need to be tested later...
2024-06-09 22:15:21 +05:30
c417bf2276
add memory writing functions
2024-06-09 16:07:09 +05:30
4db0a8163e
implement some more instructions and branching?
2024-06-09 16:02:04 +05:30
858cbfba48
fix potential adc overflow flag bug
2024-06-09 15:35:31 +05:30
76b9059b2e
add blank todo opcode functions based on opcode json
2024-06-09 13:11:05 +05:30
207c6903f5
programmatically create switch cases for opcodes based on opcode json
...
The JSON is from https://github.com/ericTheEchidna/65C02-JSON/ and
saved me a lot of time from writing the cases for each opcode by hand.
2024-06-09 13:08:31 +05:30
72e29b3d25
move addressing mode parsing into separate function
2024-06-08 22:08:51 +05:30
1ac30a026b
add adc and actually fix peek/16
2024-06-08 17:41:17 +05:30
bd85b80ba7
fix peek
2024-06-04 17:48:34 +05:30
36a8eefd00
shorten addressing mode enum names
2024-06-04 16:16:48 +05:30
