commit f697bf76970fc1d264d52afd7e0e28d64f209e82
Author: vin <git@vineetk.net>
Date: Mon, 10 Mar 2025 15:41:13 -0400
initial payload
Diffstat:
9 files changed, 1911 insertions(+), 0 deletions(-)
diff --git a/CEL_PROJECT.qpf b/CEL_PROJECT.qpf
@@ -0,0 +1,6 @@
+DATE = "03:53:12 February 25, 2025"
+QUARTUS_VERSION = "16.0.0"
+
+# Revisions
+
+PROJECT_REVISION = "CEL_PROJECT"
diff --git a/CEL_PROJECT.qsf b/CEL_PROJECT.qsf
@@ -0,0 +1,285 @@
+#============================================================
+# Build by Terasic System Builder
+#============================================================
+
+set_global_assignment -name FAMILY "MAX 10 FPGA"
+set_global_assignment -name DEVICE 10M50DAF484C7G
+set_global_assignment -name TOP_LEVEL_ENTITY "CEL_PROJECT"
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "16.0.0"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "03:53:12 FEBRUARY 25,2025"
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name SDC_FILE CEL_PROJECT.SDC
+
+#============================================================
+# CLOCK
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
+set_location_assignment PIN_N5 -to ADC_CLK_10
+set_location_assignment PIN_P11 -to MAX10_CLK1_50
+set_location_assignment PIN_N14 -to MAX10_CLK2_50
+
+#============================================================
+# SEG7
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
+set_location_assignment PIN_C14 -to HEX0[0]
+set_location_assignment PIN_E15 -to HEX0[1]
+set_location_assignment PIN_C15 -to HEX0[2]
+set_location_assignment PIN_C16 -to HEX0[3]
+set_location_assignment PIN_E16 -to HEX0[4]
+set_location_assignment PIN_D17 -to HEX0[5]
+set_location_assignment PIN_C17 -to HEX0[6]
+set_location_assignment PIN_D15 -to HEX0[7]
+set_location_assignment PIN_C18 -to HEX1[0]
+set_location_assignment PIN_D18 -to HEX1[1]
+set_location_assignment PIN_E18 -to HEX1[2]
+set_location_assignment PIN_B16 -to HEX1[3]
+set_location_assignment PIN_A17 -to HEX1[4]
+set_location_assignment PIN_A18 -to HEX1[5]
+set_location_assignment PIN_B17 -to HEX1[6]
+set_location_assignment PIN_A16 -to HEX1[7]
+set_location_assignment PIN_B20 -to HEX2[0]
+set_location_assignment PIN_A20 -to HEX2[1]
+set_location_assignment PIN_B19 -to HEX2[2]
+set_location_assignment PIN_A21 -to HEX2[3]
+set_location_assignment PIN_B21 -to HEX2[4]
+set_location_assignment PIN_C22 -to HEX2[5]
+set_location_assignment PIN_B22 -to HEX2[6]
+set_location_assignment PIN_A19 -to HEX2[7]
+set_location_assignment PIN_F21 -to HEX3[0]
+set_location_assignment PIN_E22 -to HEX3[1]
+set_location_assignment PIN_E21 -to HEX3[2]
+set_location_assignment PIN_C19 -to HEX3[3]
+set_location_assignment PIN_C20 -to HEX3[4]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_E17 -to HEX3[6]
+set_location_assignment PIN_D22 -to HEX3[7]
+set_location_assignment PIN_F18 -to HEX4[0]
+set_location_assignment PIN_E20 -to HEX4[1]
+set_location_assignment PIN_E19 -to HEX4[2]
+set_location_assignment PIN_J18 -to HEX4[3]
+set_location_assignment PIN_H19 -to HEX4[4]
+set_location_assignment PIN_F19 -to HEX4[5]
+set_location_assignment PIN_F20 -to HEX4[6]
+set_location_assignment PIN_F17 -to HEX4[7]
+set_location_assignment PIN_J20 -to HEX5[0]
+set_location_assignment PIN_K20 -to HEX5[1]
+set_location_assignment PIN_L18 -to HEX5[2]
+set_location_assignment PIN_N18 -to HEX5[3]
+set_location_assignment PIN_M20 -to HEX5[4]
+set_location_assignment PIN_N19 -to HEX5[5]
+set_location_assignment PIN_N20 -to HEX5[6]
+set_location_assignment PIN_L19 -to HEX5[7]
+
+#============================================================
+# KEY
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3 V Schmitt Trigger" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3 V Schmitt Trigger" -to KEY[1]
+set_location_assignment PIN_B8 -to KEY[0]
+set_location_assignment PIN_A7 -to KEY[1]
+
+#============================================================
+# LED
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_location_assignment PIN_A8 -to LEDR[0]
+set_location_assignment PIN_A9 -to LEDR[1]
+set_location_assignment PIN_A10 -to LEDR[2]
+set_location_assignment PIN_B10 -to LEDR[3]
+set_location_assignment PIN_D13 -to LEDR[4]
+set_location_assignment PIN_C13 -to LEDR[5]
+set_location_assignment PIN_E14 -to LEDR[6]
+set_location_assignment PIN_D14 -to LEDR[7]
+set_location_assignment PIN_A11 -to LEDR[8]
+set_location_assignment PIN_B11 -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_location_assignment PIN_C10 -to SW[0]
+set_location_assignment PIN_C11 -to SW[1]
+set_location_assignment PIN_D12 -to SW[2]
+set_location_assignment PIN_C12 -to SW[3]
+set_location_assignment PIN_A12 -to SW[4]
+set_location_assignment PIN_B12 -to SW[5]
+set_location_assignment PIN_A13 -to SW[6]
+set_location_assignment PIN_A14 -to SW[7]
+set_location_assignment PIN_B14 -to SW[8]
+set_location_assignment PIN_F15 -to SW[9]
+
+#============================================================
+# GPIO, GPIO connect to GPIO Default
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
+set_location_assignment PIN_V10 -to GPIO[0]
+set_location_assignment PIN_W10 -to GPIO[1]
+set_location_assignment PIN_V9 -to GPIO[2]
+set_location_assignment PIN_W9 -to GPIO[3]
+set_location_assignment PIN_V8 -to GPIO[4]
+set_location_assignment PIN_W8 -to GPIO[5]
+set_location_assignment PIN_V7 -to GPIO[6]
+set_location_assignment PIN_W7 -to GPIO[7]
+set_location_assignment PIN_W6 -to GPIO[8]
+set_location_assignment PIN_V5 -to GPIO[9]
+set_location_assignment PIN_W5 -to GPIO[10]
+set_location_assignment PIN_AA15 -to GPIO[11]
+set_location_assignment PIN_AA14 -to GPIO[12]
+set_location_assignment PIN_W13 -to GPIO[13]
+set_location_assignment PIN_W12 -to GPIO[14]
+set_location_assignment PIN_AB13 -to GPIO[15]
+set_location_assignment PIN_AB12 -to GPIO[16]
+set_location_assignment PIN_Y11 -to GPIO[17]
+set_location_assignment PIN_AB11 -to GPIO[18]
+set_location_assignment PIN_W11 -to GPIO[19]
+set_location_assignment PIN_AB10 -to GPIO[20]
+set_location_assignment PIN_AA10 -to GPIO[21]
+set_location_assignment PIN_AA9 -to GPIO[22]
+set_location_assignment PIN_Y8 -to GPIO[23]
+set_location_assignment PIN_AA8 -to GPIO[24]
+set_location_assignment PIN_Y7 -to GPIO[25]
+set_location_assignment PIN_AA7 -to GPIO[26]
+set_location_assignment PIN_Y6 -to GPIO[27]
+set_location_assignment PIN_AA6 -to GPIO[28]
+set_location_assignment PIN_Y5 -to GPIO[29]
+set_location_assignment PIN_AA5 -to GPIO[30]
+set_location_assignment PIN_Y4 -to GPIO[31]
+set_location_assignment PIN_AB3 -to GPIO[32]
+set_location_assignment PIN_Y3 -to GPIO[33]
+set_location_assignment PIN_AB2 -to GPIO[34]
+set_location_assignment PIN_AA2 -to GPIO[35]
+
+#============================================================
+# End of pin assignments by Terasic System Builder
+#============================================================
+
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE riscvsingle.sv
+set_global_assignment -name VERILOG_FILE my_computer_tb.v
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH my_computer_tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME my_computer_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id my_computer_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME my_computer_tb -section_id my_computer_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE my_computer_tb.v -section_id my_computer_tb
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
diff --git a/CEL_PROJECT.sdc b/CEL_PROJECT.sdc
@@ -0,0 +1,86 @@
+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+
diff --git a/CEL_PROJECT.v b/CEL_PROJECT.v
@@ -0,0 +1,38 @@
+module CEL_PROJECT(
+
+ //////////// CLOCK //////////
+ input ADC_CLK_10,
+ input MAX10_CLK1_50,
+ input MAX10_CLK2_50,
+
+ //////////// SEG7 //////////
+ output [7:0] HEX0,
+ output [7:0] HEX1,
+ output [7:0] HEX2,
+ output [7:0] HEX3,
+ output [7:0] HEX4,
+ output [7:0] HEX5,
+
+ //////////// KEY //////////
+ input [1:0] KEY,
+
+ //////////// LED //////////
+ output [9:0] LEDR,
+
+ //////////// SW //////////
+ input [9:0] SW,
+
+ //////////// GPIO, GPIO connect to GPIO Default //////////
+ inout [35:0] GPIO
+);
+
+
+wire [31:0] my_PC, my_rd;
+
+assign clk = ~KEY[1]; //ADC_CLK_10;
+
+my_computer U1(.clk(clk), .reset(~KEY[0]), .my_sw(SW[7:0]), .my_rd(my_rd), .my_PC(my_PC)); // Excluding comments 200+ lines of "code"
+
+assign LEDR = SW[9] ? my_PC : my_rd;
+
+endmodule
diff --git a/my_computer_tb.v b/my_computer_tb.v
@@ -0,0 +1,23 @@
+`timescale 1ns/1ps
+
+module my_computer_tb();
+
+ reg clk, reset;
+
+ // instantiate device to be tested
+ my_computer U1(.clk(clk), .reset(reset), .my_sw(0), .my_rd(), .my_PC());
+
+ always
+ begin
+ #5; clk <= ~clk;
+ end
+
+ initial
+ begin
+ reset <= 1; clk = 1;
+ #22; reset <= 0;
+ #1000;
+ $stop;
+ end
+
+endmodule
+\ No newline at end of file
diff --git a/riscvsingle.sv b/riscvsingle.sv
@@ -0,0 +1,390 @@
+// riscvsingle.sv
+
+// RISC-V single-cycle processor
+// From Section 7.6 of Digital Design & Computer Architecture
+// 27 April 2020
+// David_Harris@hmc.edu
+// Sarah.Harris@unlv.edu
+
+// run 210
+// Expect simulator to print "Simulation succeeded"
+// when the value 25 (0x19) is written to address 100 (0x64)
+
+// Single-cycle implementation of RISC-V (RV32I)
+// User-level Instruction Set Architecture V2.2 (May 7, 2017)
+// Implements a subset of the base integer instructions:
+// lw, sw
+// add, sub, and, or, slt,
+// addi, andi, ori, slti
+// beq
+// jal
+// Exceptions, traps, and interrupts not implemented
+// little-endian memory
+
+// 31 32-bit registers x1-x31, x0 hardwired to 0
+// R-Type instructions
+// add, sub, and, or, slt
+// INSTR rd, rs1, rs2
+// Instr[31:25] = funct7 (funct7b5 & opb5 = 1 for sub, 0 for others)
+// Instr[24:20] = rs2
+// Instr[19:15] = rs1
+// Instr[14:12] = funct3
+// Instr[11:7] = rd
+// Instr[6:0] = opcode
+// I-Type Instructions
+// lw, I-type ALU (addi, andi, ori, slti)
+// lw: INSTR rd, imm(rs1)
+// I-type ALU: INSTR rd, rs1, imm (12-bit signed)
+// Instr[31:20] = imm[11:0]
+// Instr[24:20] = rs2
+// Instr[19:15] = rs1
+// Instr[14:12] = funct3
+// Instr[11:7] = rd
+// Instr[6:0] = opcode
+// S-Type Instruction
+// sw rs2, imm(rs1) (store rs2 into address specified by rs1 + immm)
+// Instr[31:25] = imm[11:5] (offset[11:5])
+// Instr[24:20] = rs2 (src)
+// Instr[19:15] = rs1 (base)
+// Instr[14:12] = funct3
+// Instr[11:7] = imm[4:0] (offset[4:0])
+// Instr[6:0] = opcode
+// B-Type Instruction
+// beq rs1, rs2, imm (PCTarget = PC + (signed imm x 2))
+// Instr[31:25] = imm[12], imm[10:5]
+// Instr[24:20] = rs2
+// Instr[19:15] = rs1
+// Instr[14:12] = funct3
+// Instr[11:7] = imm[4:1], imm[11]
+// Instr[6:0] = opcode
+// J-Type Instruction
+// jal rd, imm (signed imm is multiplied by 2 and added to PC, rd = PC+4)
+// Instr[31:12] = imm[20], imm[10:1], imm[11], imm[19:12]
+// Instr[11:7] = rd
+// Instr[6:0] = opcode
+
+// Instruction opcode funct3 funct7
+// add 0110011 000 0000000
+// sub 0110011 000 0100000
+// and 0110011 111 0000000
+// or 0110011 110 0000000
+// slt 0110011 010 0000000
+// addi 0010011 000 immediate
+// andi 0010011 111 immediate
+// ori 0010011 110 immediate
+// slti 0010011 010 immediate
+// beq 1100011 000 immediate
+// lw 0000011 010 immediate
+// sw 0100011 010 immediate
+// jal 1101111 immediate immediate
+
+
+// This part is modified by Dr.Toker
+module my_computer(input logic clk, reset,
+ input logic[ 9:0] my_sw,
+ output logic[31:0] my_rd,
+ output logic[31:0] my_PC
+);
+
+ logic [31:0] PC, Instr, ReadData, WriteData, DataAddr;
+ logic MemWrite;
+
+ // instantiate processor
+ riscvsingle rvsingle(clk, reset, PC, Instr, MemWrite, DataAddr,
+ WriteData, ReadData);
+ // program memory - ROM
+ imem imem(PC, Instr);
+
+ // data memort - RAM
+ dmem dmem(clk, MemWrite, DataAddr, WriteData, ReadData, my_sw, my_rd);
+
+ assign my_PC = PC;
+
+endmodule
+
+// =======================================================================
+// NEW STUFF ABOUT MEMORIES - MUST REVIEW FIRST
+// =======================================================================
+
+module regfile(input logic clk,
+ input logic we3,
+ input logic [ 4:0] a1, a2, a3,
+ input logic [31:0] wd3,
+ output logic [31:0] rd1, rd2);
+
+ logic [31:0] rf[31:0];
+
+ // three ported register file
+ // read two ports combinationally (A1/RD1, A2/RD2)
+ // write third port on rising edge of clock (A3/WD3/WE3)
+ // register 0 hardwired to 0
+
+ always_ff @(posedge clk)
+ if (we3) rf[a3] <= wd3;
+
+ assign rd1 = (a1 != 0) ? rf[a1] : 0;
+ assign rd2 = (a2 != 0) ? rf[a2] : 0;
+endmodule
+
+module imem(input logic [31:0] a,
+ output logic [31:0] rd);
+
+ logic [31:0] ROM[63:0];
+
+ // Initialize the program memory
+ // Simulator : ok
+ // Hardware : For FPGA ok, non-FPGA we need a 3rd party solution to program the FLASH memory (ROM)
+ initial
+ $readmemh("C:\\Users\\onur\\Desktop\\CE_Lab2\\CEL_PROJECT\\riscvtest_rom_image.txt", ROM);
+
+ assign rd = ROM[a[31:2]]; // word aligned
+endmodule
+
+// This part is modified by Dr. Toker
+module dmem(input logic clk, we,
+ input logic [31:0] a, wd,
+ output logic [31:0] rd,
+ input logic [ 7:0] my_sw,
+ output logic [31:0] my_rd);
+
+ logic [31:0] RAM[127:0];
+
+ assign rd = RAM[a[31:2]]; // word aligned
+
+ always_ff @(posedge clk)
+ begin
+ if (we) RAM[a[31:2]] <= wd;
+
+ // Used only for simulation, does not correspond to ANY hardware
+ if (we)
+ $display("Write RAM[%08x]=%08x at %t", a[31:2], wd, $time);
+ else
+ $display("Read RAM[%08x]=%08x at %t", a[31:2], rd, $time);
+
+ end
+
+ assign my_rd = RAM[my_sw[7:2]];
+
+ // Initialize the program memory
+ // Simulator : ok
+ // Hardware : For FPGA ok, non-FPGA we need a 3rd party solution to program the DATA memory (RAM)
+ initial
+ $readmemh("C:\\Users\\onur\\Desktop\\CE_Lab2\\CEL_PROJECT\\riscvtest_ram_image.txt", RAM);
+
+endmodule
+
+module flopr #(parameter WIDTH = 8)
+ (input logic clk, reset,
+ input logic [WIDTH-1:0] d,
+ output logic [WIDTH-1:0] q);
+
+ always_ff @(posedge clk, posedge reset)
+ if (reset) q <= 0;
+ else q <= d;
+endmodule
+
+// =======================================================================
+// OLD STUFF - Component Instantiation or New Combinatorial Designs
+// =======================================================================
+
+module riscvsingle(input logic clk, reset,
+ output logic [31:0] PC,
+ input logic [31:0] Instr,
+ output logic MemWrite,
+ output logic [31:0] ALUResult, WriteData,
+ input logic [31:0] ReadData);
+
+ logic ALUSrc, RegWrite, Jump, Zero;
+ logic [1:0] ResultSrc, ImmSrc;
+ logic [2:0] ALUControl;
+
+ controller c(Instr[6:0], Instr[14:12], Instr[30], Zero,
+ ResultSrc, MemWrite, PCSrc,
+ ALUSrc, RegWrite, Jump,
+ ImmSrc, ALUControl);
+ datapath dp(clk, reset, ResultSrc, PCSrc,
+ ALUSrc, RegWrite,
+ ImmSrc, ALUControl,
+ Zero, PC, Instr,
+ ALUResult, WriteData, ReadData);
+endmodule
+
+module controller(input logic [6:0] op,
+ input logic [2:0] funct3,
+ input logic funct7b5,
+ input logic Zero,
+ output logic [1:0] ResultSrc,
+ output logic MemWrite,
+ output logic PCSrc, ALUSrc,
+ output logic RegWrite, Jump,
+ output logic [1:0] ImmSrc,
+ output logic [2:0] ALUControl);
+
+ logic [1:0] ALUOp;
+ logic Branch;
+
+ maindec md(op, ResultSrc, MemWrite, Branch,
+ ALUSrc, RegWrite, Jump, ImmSrc, ALUOp);
+ aludec ad(op[5], funct3, funct7b5, ALUOp, ALUControl);
+
+ assign PCSrc = Branch & Zero | Jump;
+endmodule
+
+module maindec(input logic [6:0] op,
+ output logic [1:0] ResultSrc,
+ output logic MemWrite,
+ output logic Branch, ALUSrc,
+ output logic RegWrite, Jump,
+ output logic [1:0] ImmSrc,
+ output logic [1:0] ALUOp);
+
+ logic [10:0] controls;
+
+ assign {RegWrite, ImmSrc, ALUSrc, MemWrite,
+ ResultSrc, Branch, ALUOp, Jump} = controls;
+
+ always_comb
+ case(op)
+ // RegWrite_ImmSrc_ALUSrc_MemWrite_ResultSrc_Branch_ALUOp_Jump
+ 7'b0000011: controls = 11'b1_00_1_0_01_0_00_0; // lw
+ 7'b0100011: controls = 11'b0_01_1_1_00_0_00_0; // sw
+ 7'b0110011: controls = 11'b1_xx_0_0_00_0_10_0; // R-type
+ 7'b1100011: controls = 11'b0_10_0_0_00_1_01_0; // beq
+ 7'b0010011: controls = 11'b1_00_1_0_00_0_10_0; // I-type ALU
+ 7'b1101111: controls = 11'b1_11_0_0_10_0_00_1; // jal
+ default: controls = 11'bx_xx_x_x_xx_x_xx_x; // non-implemented instruction
+ endcase
+endmodule
+
+module aludec(input logic opb5,
+ input logic [2:0] funct3,
+ input logic funct7b5,
+ input logic [1:0] ALUOp,
+ output logic [2:0] ALUControl);
+
+ logic RtypeSub;
+ assign RtypeSub = funct7b5 & opb5; // TRUE for R-type subtract instruction
+
+ always_comb
+ case(ALUOp)
+ 2'b00: ALUControl = 3'b000; // addition
+ 2'b01: ALUControl = 3'b001; // subtraction
+ default: case(funct3) // R-type or I-type ALU
+ 3'b000: if (RtypeSub)
+ ALUControl = 3'b001; // sub
+ else
+ ALUControl = 3'b000; // add, addi
+ 3'b010: ALUControl = 3'b101; // slt, slti
+ 3'b110: ALUControl = 3'b011; // or, ori
+ 3'b111: ALUControl = 3'b010; // and, andi
+ default: ALUControl = 3'bxxx; // ???
+ endcase
+ endcase
+endmodule
+
+module datapath(input logic clk, reset,
+ input logic [1:0] ResultSrc,
+ input logic PCSrc, ALUSrc,
+ input logic RegWrite,
+ input logic [1:0] ImmSrc,
+ input logic [2:0] ALUControl,
+ output logic Zero,
+ output logic [31:0] PC,
+ input logic [31:0] Instr,
+ output logic [31:0] ALUResult, WriteData,
+ input logic [31:0] ReadData);
+
+ logic [31:0] PCNext, PCPlus4, PCTarget;
+ logic [31:0] ImmExt;
+ logic [31:0] SrcA, SrcB;
+ logic [31:0] Result;
+
+ // next PC logic
+ flopr #(32) pcreg(clk, reset, PCNext, PC);
+ adder pcadd4(PC, 32'd4, PCPlus4);
+ adder pcaddbranch(PC, ImmExt, PCTarget);
+ mux2 #(32) pcmux(PCPlus4, PCTarget, PCSrc, PCNext);
+
+ // register file logic
+ regfile rf(clk, RegWrite, Instr[19:15], Instr[24:20],
+ Instr[11:7], Result, SrcA, WriteData);
+ extend ext(Instr[31:7], ImmSrc, ImmExt);
+
+ // ALU logic
+ mux2 #(32) srcbmux(WriteData, ImmExt, ALUSrc, SrcB);
+ alu alu(SrcA, SrcB, ALUControl, ALUResult, Zero);
+ mux3 #(32) resultmux(ALUResult, ReadData, PCPlus4, ResultSrc, Result);
+endmodule
+
+
+module adder(input [31:0] a, b,
+ output [31:0] y);
+
+ assign y = a + b;
+endmodule
+
+module extend(input logic [31:7] instr,
+ input logic [1:0] immsrc,
+ output logic [31:0] immext);
+
+ always_comb
+ case(immsrc)
+ // I-type
+ 2'b00: immext = {{20{instr[31]}}, instr[31:20]};
+ // S-type (stores)
+ 2'b01: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]};
+ // B-type (branches)
+ 2'b10: immext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
+ // J-type (jal)
+ 2'b11: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
+ default: immext = 32'bx; // undefined
+ endcase
+endmodule
+
+module mux2 #(parameter WIDTH = 8)
+ (input logic [WIDTH-1:0] d0, d1,
+ input logic s,
+ output logic [WIDTH-1:0] y);
+
+ assign y = s ? d1 : d0;
+endmodule
+
+module mux3 #(parameter WIDTH = 8)
+ (input logic [WIDTH-1:0] d0, d1, d2,
+ input logic [1:0] s,
+ output logic [WIDTH-1:0] y);
+
+ assign y = s[1] ? d2 : (s[0] ? d1 : d0);
+endmodule
+
+module alu(input logic [31:0] a, b,
+ input logic [2:0] alucontrol,
+ output logic [31:0] result,
+ output logic zero);
+
+ logic [31:0] condinvb, sum;
+ logic v; // overflow
+ logic isAddSub; // true when is add or subtract operation
+
+ assign condinvb = alucontrol[0] ? ~b : b;
+ assign sum = a + condinvb + alucontrol[0];
+ assign isAddSub = ~alucontrol[2] & ~alucontrol[1] |
+ ~alucontrol[1] & alucontrol[0];
+
+ always_comb
+ case (alucontrol)
+ 3'b000: result = sum; // add
+ 3'b001: result = sum; // subtract
+ 3'b010: result = a & b; // and
+ 3'b011: result = a | b; // or
+ 3'b100: result = a ^ b; // xor
+ 3'b101: result = sum[31] ^ v; // slt
+ 3'b110: result = a << b[4:0]; // sll
+ 3'b111: result = a >> b[4:0]; // srl
+ default: result = 32'bx;
+ endcase
+
+ assign zero = (result == 32'b0);
+ assign v = ~(alucontrol[0] ^ a[31] ^ b[31]) & (a[31] ^ sum[31]) & isAddSub;
+
+endmodule
diff --git a/riscvtest.s b/riscvtest.s
@@ -0,0 +1,33 @@
+# riscvtest.s
+# Sarah.Harris@unlv.edu
+# David_Harris@hmc.edu
+# 27 Oct 2020
+#
+# Test the RISC-V processor.
+# add, sub, and, or, slt, addi, lw, sw, beq, jal
+# If successful, it should write the value 25 to address 100
+
+# RISC-V Assembly Description Address Machine Code
+main: addi x2, x0, 5 # x2 = 5 0 00500113
+ addi x3, x0, 12 # x3 = 12 4 00C00193
+ addi x7, x3, -9 # x7 = (12 - 9) = 3 8 FF718393
+ or x4, x7, x2 # x4 = (3 OR 5) = 7 C 0023E233
+ and x5, x3, x4 # x5 = (12 AND 7) = 4 10 0041F2B3
+ add x5, x5, x4 # x5 = (4 + 7) = 11 14 004282B3
+ beq x5, x7, end # shouldn't be taken 18 02728863
+ slt x4, x3, x4 # x4 = (12 < 7) = 0 1C 0041A233
+ beq x4, x0, around # should be taken 20 00020463
+ addi x5, x0, 0 # shouldn't happen 24 00000293
+around: slt x4, x7, x2 # x4 = (3 < 5) = 1 28 0023A233
+ add x7, x4, x5 # x7 = (1 + 11) = 12 2C 005203B3
+ sub x7, x7, x2 # x7 = (12 - 5) = 7 30 402383B3
+ sw x7, 84(x3) # [96] = 7 34 0471AA23
+ lw x2, 96(x0) # x2 = [96] = 7 38 06002103
+ add x9, x2, x5 # x9 = (7 + 11) = 18 3C 005104B3
+ jal x3, end # jump to end, x3 = 0x44 40 008001EF
+ addi x2, x0, 1 # shouldn't happen 44 00100113
+end: add x2, x2, x9 # x2 = (7 + 18) = 25 48 00910133
+ sw x2, 0x20(x3) # mem[100] = 25 4C 0221A023
+done: beq x2, x2, done # infinite loop 50 00210063
+
+
+\ No newline at end of file
diff --git a/riscvtest_ram_image.txt b/riscvtest_ram_image.txt
@@ -0,0 +1,1024 @@
+00000000
+00000001
+00000002
+00000003
+00000004
+00000005
+00000006
+00000007
+00000008
+00000009
+0000000A
+0000000B
+0000000C
+0000000D
+0000000E
+0000000F
+00000010
+00000011
+00000012
+00000013
+00000014
+00000015
+00000016
+00000017
+00000018
+00000019
+0000001A
+0000001B
+0000001C
+0000001D
+0000001E
+0000001F
+00000020
+00000021
+00000022
+00000023
+00000024
+00000025
+00000026
+00000027
+00000028
+00000029
+0000002A
+0000002B
+0000002C
+0000002D
+0000002E
+0000002F
+00000030
+00000031
+00000032
+00000033
+00000034
+00000035
+00000036
+00000037
+00000038
+00000039
+0000003A
+0000003B
+0000003C
+0000003D
+0000003E
+0000003F
+00000040
+00000041
+00000042
+00000043
+00000044
+00000045
+00000046
+00000047
+00000048
+00000049
+0000004A
+0000004B
+0000004C
+0000004D
+0000004E
+0000004F
+00000050
+00000051
+00000052
+00000053
+00000054
+00000055
+00000056
+00000057
+00000058
+00000059
+0000005A
+0000005B
+0000005C
+0000005D
+0000005E
+0000005F
+00000060
+00000061
+00000062
+00000063
+00000064
+00000065
+00000066
+00000067
+00000068
+00000069
+0000006A
+0000006B
+0000006C
+0000006D
+0000006E
+0000006F
+00000070
+00000071
+00000072
+00000073
+00000074
+00000075
+00000076
+00000077
+00000078
+00000079
+0000007A
+0000007B
+0000007C
+0000007D
+0000007E
+0000007F
+00000080
+00000081
+00000082
+00000083
+00000084
+00000085
+00000086
+00000087
+00000088
+00000089
+0000008A
+0000008B
+0000008C
+0000008D
+0000008E
+0000008F
+00000090
+00000091
+00000092
+00000093
+00000094
+00000095
+00000096
+00000097
+00000098
+00000099
+0000009A
+0000009B
+0000009C
+0000009D
+0000009E
+0000009F
+000000A0
+000000A1
+000000A2
+000000A3
+000000A4
+000000A5
+000000A6
+000000A7
+000000A8
+000000A9
+000000AA
+000000AB
+000000AC
+000000AD
+000000AE
+000000AF
+000000B0
+000000B1
+000000B2
+000000B3
+000000B4
+000000B5
+000000B6
+000000B7
+000000B8
+000000B9
+000000BA
+000000BB
+000000BC
+000000BD
+000000BE
+000000BF
+000000C0
+000000C1
+000000C2
+000000C3
+000000C4
+000000C5
+000000C6
+000000C7
+000000C8
+000000C9
+000000CA
+000000CB
+000000CC
+000000CD
+000000CE
+000000CF
+000000D0
+000000D1
+000000D2
+000000D3
+000000D4
+000000D5
+000000D6
+000000D7
+000000D8
+000000D9
+000000DA
+000000DB
+000000DC
+000000DD
+000000DE
+000000DF
+000000E0
+000000E1
+000000E2
+000000E3
+000000E4
+000000E5
+000000E6
+000000E7
+000000E8
+000000E9
+000000EA
+000000EB
+000000EC
+000000ED
+000000EE
+000000EF
+000000F0
+000000F1
+000000F2
+000000F3
+000000F4
+000000F5
+000000F6
+000000F7
+000000F8
+000000F9
+000000FA
+000000FB
+000000FC
+000000FD
+000000FE
+000000FF
+00000100
+00000101
+00000102
+00000103
+00000104
+00000105
+00000106
+00000107
+00000108
+00000109
+0000010A
+0000010B
+0000010C
+0000010D
+0000010E
+0000010F
+00000110
+00000111
+00000112
+00000113
+00000114
+00000115
+00000116
+00000117
+00000118
+00000119
+0000011A
+0000011B
+0000011C
+0000011D
+0000011E
+0000011F
+00000120
+00000121
+00000122
+00000123
+00000124
+00000125
+00000126
+00000127
+00000128
+00000129
+0000012A
+0000012B
+0000012C
+0000012D
+0000012E
+0000012F
+00000130
+00000131
+00000132
+00000133
+00000134
+00000135
+00000136
+00000137
+00000138
+00000139
+0000013A
+0000013B
+0000013C
+0000013D
+0000013E
+0000013F
+00000140
+00000141
+00000142
+00000143
+00000144
+00000145
+00000146
+00000147
+00000148
+00000149
+0000014A
+0000014B
+0000014C
+0000014D
+0000014E
+0000014F
+00000150
+00000151
+00000152
+00000153
+00000154
+00000155
+00000156
+00000157
+00000158
+00000159
+0000015A
+0000015B
+0000015C
+0000015D
+0000015E
+0000015F
+00000160
+00000161
+00000162
+00000163
+00000164
+00000165
+00000166
+00000167
+00000168
+00000169
+0000016A
+0000016B
+0000016C
+0000016D
+0000016E
+0000016F
+00000170
+00000171
+00000172
+00000173
+00000174
+00000175
+00000176
+00000177
+00000178
+00000179
+0000017A
+0000017B
+0000017C
+0000017D
+0000017E
+0000017F
+00000180
+00000181
+00000182
+00000183
+00000184
+00000185
+00000186
+00000187
+00000188
+00000189
+0000018A
+0000018B
+0000018C
+0000018D
+0000018E
+0000018F
+00000190
+00000191
+00000192
+00000193
+00000194
+00000195
+00000196
+00000197
+00000198
+00000199
+0000019A
+0000019B
+0000019C
+0000019D
+0000019E
+0000019F
+000001A0
+000001A1
+000001A2
+000001A3
+000001A4
+000001A5
+000001A6
+000001A7
+000001A8
+000001A9
+000001AA
+000001AB
+000001AC
+000001AD
+000001AE
+000001AF
+000001B0
+000001B1
+000001B2
+000001B3
+000001B4
+000001B5
+000001B6
+000001B7
+000001B8
+000001B9
+000001BA
+000001BB
+000001BC
+000001BD
+000001BE
+000001BF
+000001C0
+000001C1
+000001C2
+000001C3
+000001C4
+000001C5
+000001C6
+000001C7
+000001C8
+000001C9
+000001CA
+000001CB
+000001CC
+000001CD
+000001CE
+000001CF
+000001D0
+000001D1
+000001D2
+000001D3
+000001D4
+000001D5
+000001D6
+000001D7
+000001D8
+000001D9
+000001DA
+000001DB
+000001DC
+000001DD
+000001DE
+000001DF
+000001E0
+000001E1
+000001E2
+000001E3
+000001E4
+000001E5
+000001E6
+000001E7
+000001E8
+000001E9
+000001EA
+000001EB
+000001EC
+000001ED
+000001EE
+000001EF
+000001F0
+000001F1
+000001F2
+000001F3
+000001F4
+000001F5
+000001F6
+000001F7
+000001F8
+000001F9
+000001FA
+000001FB
+000001FC
+000001FD
+000001FE
+000001FF
+00000200
+00000201
+00000202
+00000203
+00000204
+00000205
+00000206
+00000207
+00000208
+00000209
+0000020A
+0000020B
+0000020C
+0000020D
+0000020E
+0000020F
+00000210
+00000211
+00000212
+00000213
+00000214
+00000215
+00000216
+00000217
+00000218
+00000219
+0000021A
+0000021B
+0000021C
+0000021D
+0000021E
+0000021F
+00000220
+00000221
+00000222
+00000223
+00000224
+00000225
+00000226
+00000227
+00000228
+00000229
+0000022A
+0000022B
+0000022C
+0000022D
+0000022E
+0000022F
+00000230
+00000231
+00000232
+00000233
+00000234
+00000235
+00000236
+00000237
+00000238
+00000239
+0000023A
+0000023B
+0000023C
+0000023D
+0000023E
+0000023F
+00000240
+00000241
+00000242
+00000243
+00000244
+00000245
+00000246
+00000247
+00000248
+00000249
+0000024A
+0000024B
+0000024C
+0000024D
+0000024E
+0000024F
+00000250
+00000251
+00000252
+00000253
+00000254
+00000255
+00000256
+00000257
+00000258
+00000259
+0000025A
+0000025B
+0000025C
+0000025D
+0000025E
+0000025F
+00000260
+00000261
+00000262
+00000263
+00000264
+00000265
+00000266
+00000267
+00000268
+00000269
+0000026A
+0000026B
+0000026C
+0000026D
+0000026E
+0000026F
+00000270
+00000271
+00000272
+00000273
+00000274
+00000275
+00000276
+00000277
+00000278
+00000279
+0000027A
+0000027B
+0000027C
+0000027D
+0000027E
+0000027F
+00000280
+00000281
+00000282
+00000283
+00000284
+00000285
+00000286
+00000287
+00000288
+00000289
+0000028A
+0000028B
+0000028C
+0000028D
+0000028E
+0000028F
+00000290
+00000291
+00000292
+00000293
+00000294
+00000295
+00000296
+00000297
+00000298
+00000299
+0000029A
+0000029B
+0000029C
+0000029D
+0000029E
+0000029F
+000002A0
+000002A1
+000002A2
+000002A3
+000002A4
+000002A5
+000002A6
+000002A7
+000002A8
+000002A9
+000002AA
+000002AB
+000002AC
+000002AD
+000002AE
+000002AF
+000002B0
+000002B1
+000002B2
+000002B3
+000002B4
+000002B5
+000002B6
+000002B7
+000002B8
+000002B9
+000002BA
+000002BB
+000002BC
+000002BD
+000002BE
+000002BF
+000002C0
+000002C1
+000002C2
+000002C3
+000002C4
+000002C5
+000002C6
+000002C7
+000002C8
+000002C9
+000002CA
+000002CB
+000002CC
+000002CD
+000002CE
+000002CF
+000002D0
+000002D1
+000002D2
+000002D3
+000002D4
+000002D5
+000002D6
+000002D7
+000002D8
+000002D9
+000002DA
+000002DB
+000002DC
+000002DD
+000002DE
+000002DF
+000002E0
+000002E1
+000002E2
+000002E3
+000002E4
+000002E5
+000002E6
+000002E7
+000002E8
+000002E9
+000002EA
+000002EB
+000002EC
+000002ED
+000002EE
+000002EF
+000002F0
+000002F1
+000002F2
+000002F3
+000002F4
+000002F5
+000002F6
+000002F7
+000002F8
+000002F9
+000002FA
+000002FB
+000002FC
+000002FD
+000002FE
+000002FF
+00000300
+00000301
+00000302
+00000303
+00000304
+00000305
+00000306
+00000307
+00000308
+00000309
+0000030A
+0000030B
+0000030C
+0000030D
+0000030E
+0000030F
+00000310
+00000311
+00000312
+00000313
+00000314
+00000315
+00000316
+00000317
+00000318
+00000319
+0000031A
+0000031B
+0000031C
+0000031D
+0000031E
+0000031F
+00000320
+00000321
+00000322
+00000323
+00000324
+00000325
+00000326
+00000327
+00000328
+00000329
+0000032A
+0000032B
+0000032C
+0000032D
+0000032E
+0000032F
+00000330
+00000331
+00000332
+00000333
+00000334
+00000335
+00000336
+00000337
+00000338
+00000339
+0000033A
+0000033B
+0000033C
+0000033D
+0000033E
+0000033F
+00000340
+00000341
+00000342
+00000343
+00000344
+00000345
+00000346
+00000347
+00000348
+00000349
+0000034A
+0000034B
+0000034C
+0000034D
+0000034E
+0000034F
+00000350
+00000351
+00000352
+00000353
+00000354
+00000355
+00000356
+00000357
+00000358
+00000359
+0000035A
+0000035B
+0000035C
+0000035D
+0000035E
+0000035F
+00000360
+00000361
+00000362
+00000363
+00000364
+00000365
+00000366
+00000367
+00000368
+00000369
+0000036A
+0000036B
+0000036C
+0000036D
+0000036E
+0000036F
+00000370
+00000371
+00000372
+00000373
+00000374
+00000375
+00000376
+00000377
+00000378
+00000379
+0000037A
+0000037B
+0000037C
+0000037D
+0000037E
+0000037F
+00000380
+00000381
+00000382
+00000383
+00000384
+00000385
+00000386
+00000387
+00000388
+00000389
+0000038A
+0000038B
+0000038C
+0000038D
+0000038E
+0000038F
+00000390
+00000391
+00000392
+00000393
+00000394
+00000395
+00000396
+00000397
+00000398
+00000399
+0000039A
+0000039B
+0000039C
+0000039D
+0000039E
+0000039F
+000003A0
+000003A1
+000003A2
+000003A3
+000003A4
+000003A5
+000003A6
+000003A7
+000003A8
+000003A9
+000003AA
+000003AB
+000003AC
+000003AD
+000003AE
+000003AF
+000003B0
+000003B1
+000003B2
+000003B3
+000003B4
+000003B5
+000003B6
+000003B7
+000003B8
+000003B9
+000003BA
+000003BB
+000003BC
+000003BD
+000003BE
+000003BF
+000003C0
+000003C1
+000003C2
+000003C3
+000003C4
+000003C5
+000003C6
+000003C7
+000003C8
+000003C9
+000003CA
+000003CB
+000003CC
+000003CD
+000003CE
+000003CF
+000003D0
+000003D1
+000003D2
+000003D3
+000003D4
+000003D5
+000003D6
+000003D7
+000003D8
+000003D9
+000003DA
+000003DB
+000003DC
+000003DD
+000003DE
+000003DF
+000003E0
+000003E1
+000003E2
+000003E3
+000003E4
+000003E5
+000003E6
+000003E7
+000003E8
+000003E9
+000003EA
+000003EB
+000003EC
+000003ED
+000003EE
+000003EF
+000003F0
+000003F1
+000003F2
+000003F3
+000003F4
+000003F5
+000003F6
+000003F7
+000003F8
+000003F9
+000003FA
+000003FB
+000003FC
+000003FD
+000003FE
+000003FF
+\ No newline at end of file
diff --git a/riscvtest_rom_image.txt b/riscvtest_rom_image.txt
@@ -0,0 +1,21 @@
+00500113
+00C00193
+FF718393
+0023E233
+0041F2B3
+004282B3
+02728863
+0041A233
+00020463
+00000293
+0023A233
+005203B3
+402383B3
+0471AA23
+06002103
+005104B3
+008001EF
+00100113
+00910133
+0221A023
+00210063
+\ No newline at end of file
