remove more unused libraries

314 files changed, 0 insertions, 104490 deletions

diff --git a/.gitmodules b/.gitmodules
index fd505ff02c..1ea746a446 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,9 +1,3 @@
 [submodule "lib/lufa"]
 	path = lib/lufa
 	url = https://github.com/qmk/lufa
-[submodule "lib/vusb"]
-	path = lib/vusb
-	url = https://github.com/qmk/v-usb
-[submodule "lib/printf"]
-	path = lib/printf
-	url = https://github.com/qmk/printf
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h
deleted file mode 100644
index 4be7e8c848..0000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/arm_math.h
+++ /dev/null
@@ -1,7226 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_math.h
- * Description:  Public header file for CMSIS DSP Library
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * Introduction
-   * ------------
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * Using the Library
-   * ------------
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
-   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
-   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
-   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
-   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
-   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
-   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
-   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
-   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
-   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
-   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
-   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
-   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
-   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
-   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
-   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
-   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
-   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
-   * 
-   *
-   * Examples
-   * --------
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * Toolchain Support
-   * ------------
-   *
-   * The library has been developed and tested with MDK-ARM version 5.14.0.0
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * Building the Library
-   * ------------
-   *
-   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
-   * - arm_cortexM_math.uvprojx
-   *
-   *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
-   *
-   * Pre-processor Macros
-   * ------------
-   *
-   * Each library project have differant pre-processor macros.
-   *
-   * - UNALIGNED_SUPPORT_DISABLE:
-   *
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
-   * ARM_MATH_CM7 for building the library on cortex-M7.
-   *
-   * - ARM_MATH_ARMV8MxL:
-   *
-   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
-   * on ARMv8M Mainline target.
-   *
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
-   *
-   * - __DSP_PRESENT:
-   *
-   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
-   *
-   * <hr>
-   * CMSIS-DSP in ARM::CMSIS Pack
-   * -----------------------------
-   *
-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
-   * |File/Folder                   |Content                                                                 |
-   * |------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
-   *
-   * <hr>
-   * Revision History of CMSIS-DSP
-   * ------------
-   * Please refer to \ref ChangeLog_pg.
-   *
-   * Copyright Notice
-   * ------------
-   *
-   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* ignore some GCC warnings */
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-#endif
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
-  #include "core_cm7.h"
-  #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM4)
-  #include "core_cm4.h"
-  #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM3)
-  #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-  #include "core_cm0.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
-  #include "core_cm0plus.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MBL)
-  #include "core_armv8mbl.h"
-  #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MML)
-  #include "core_armv8mml.h"
-  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
-    #define ARM_MATH_DSP
-  #endif
-#else
-  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31          (0x100)
-#define DELTA_Q15          0x5
-#define INDEX_MASK         0x0000003F
-#ifndef PI
-  #define PI               3.14159265358979f
-#endif
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define FAST_MATH_TABLE_SIZE  512
-#define FAST_MATH_Q31_SHIFT   (32 - 10)
-#define FAST_MATH_Q15_SHIFT   (16 - 10)
-#define CONTROLLER_Q31_SHIFT  (32 - 9)
-#define TABLE_SPACING_Q31     0x400000
-#define TABLE_SPACING_Q15     0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING         0xB60B61
-
-  /**
-   * @brief Macro for Unaligned Support
-   */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-    #define ALIGN4
-#else
-  #if defined  (__GNUC__)
-    #define ALIGN4 __attribute__((aligned(4)))
-  #else
-    #define ALIGN4 __align(4)
-  #endif
-#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-  } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#if   defined ( __CC_ARM )
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __GNUC__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ICCARM__ )
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#elif defined ( __TI_ARM__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-  #define CMSIS_INLINE
-
-#elif defined ( __CSMC__ )
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#elif defined ( __TASKING__ )
-  #define __SIMD32_TYPE __unaligned int32_t
-  #define CMSIS_UNUSED
-  #define CMSIS_INLINE
-
-#else
-  #error Unknown compiler
-#endif
-
-#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
-#define __SIMD64(addr)        (*(int64_t **) & (addr))
-
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
-                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
-                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
-  q63_t x,
-  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-/*
-  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
-  #define __CLZ __clz
-  #endif
- */
-/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
-  CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
-  q31_t data);
-
-  CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
-  q31_t data)
-  {
-    uint32_t count = 0;
-    uint32_t mask = 0x80000000;
-
-    while ((data & mask) == 0)
-    {
-      count += 1u;
-      mask = mask >> 1u;
-    }
-
-    return (count);
-  }
-#endif
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
-   */
-
-  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
-  q31_t in,
-  q31_t * dst,
-  q31_t * pRecipTable)
-  {
-    q31_t out;
-    uint32_t tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t) (__CLZ( in) - 1));
-    }
-    else
-    {
-      signBits = ((uint32_t) (__CLZ(-in) - 1));
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >> 24);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-    {
-      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
-      tempVal = 0x7FFFFFFFu - tempVal;
-      /*      1.31 with exp 1 */
-      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
-      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-  }
-
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
-  q15_t in,
-  q15_t * dst,
-  q15_t * pRecipTable)
-  {
-    q15_t out = 0;
-    uint32_t tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if (in > 0)
-    {
-      signBits = ((uint32_t)(__CLZ( in) - 17));
-    }
-    else
-    {
-      signBits = ((uint32_t)(__CLZ(-in) - 17));
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >>  8);
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-    {
-      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
-      tempVal = 0x7FFFu - tempVal;
-      /*      1.15 with exp 1 */
-      out = (q15_t) (((q31_t) out * tempVal) >> 14);
-      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-  }
-
-
-  /*
-   * @brief C custom defined intrinisic function for only M0 processors
-   */
-#if defined(ARM_MATH_CM0_FAMILY)
-  CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
-  q31_t x,
-  uint32_t y)
-  {
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++)
-    {
-      posMax = posMax * 2;
-    }
-
-    if (x > 0)
-    {
-      posMax = (posMax - 1);
-
-      if (x > posMax)
-      {
-        x = posMax;
-      }
-    }
-    else
-    {
-      negMin = -posMax;
-
-      if (x < negMin)
-      {
-        x = negMin;
-      }
-    }
-    return (x);
-  }
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
-  /*
-   * @brief C custom defined intrinsic function for M3 and M0 processors
-   */
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
-    q31_t r = 0, s = 0;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
-  uint32_t x,
-  uint32_t y)
-  {
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
-  int32_t x,
-  int32_t y)
-  {
-    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
-  }
-
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
-  uint32_t x,
-  uint32_t y,
-  uint32_t sum)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
-  uint32_t x,
-  uint32_t y,
-  uint64_t sum)
-  {
-/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
-  uint32_t x,
-  uint32_t y)
-  {
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-  }
-
-
-  /*
-   * @brief C custom defined SXTB16 for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
-  uint32_t x)
-  {
-    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
-                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
-  }
-
-  /*
-   * @brief C custom defined SMMLA for M3 and M0 processors
-   */
-  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
-  int32_t x,
-  int32_t y,
-  int32_t sum)
-  {
-    return (sum + (int32_t) (((int64_t) x * y) >> 32));
-  }
-
-#if 0
-  /*
-   * @brief C custom defined PKHBT for unavailable DSP extension
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
-  uint32_t x,
-  uint32_t y,
-  uint32_t leftshift)
-  {
-    return ( ((x             ) & 0x0000FFFFUL) |
-             ((y << leftshift) & 0xFFFF0000UL)  );
-  }
-
-  /*
-   * @brief C custom defined PKHTB for unavailable DSP extension
-   */
-  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
-  uint32_t x,
-  uint32_t y,
-  uint32_t rightshift)
-  {
-    return ( ((x              ) & 0xFFFF0000UL) |
-             ((y >> rightshift) & 0x0000FFFFUL)  );
-  }
-#endif
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed.
-   */
-  void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in]  S          points to an instance of the Q15 FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * <code>numTaps</code> is not a supported value.
-   */
-  arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 FIR structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in]  S          points to an instance of the floating-point FIR structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
-   * @param[in]     numTaps    Number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of samples that are processed at a time.
-   */
-  void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q15;
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_casd_df1_inst_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float64_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f64;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-  } arm_matrix_instance_q31;
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]   pSrcA  points to the first input matrix structure
-   * @param[in]   pSrcB  points to the second input matrix structure
-   * @param[out]  pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15, complex,  matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Q31, complex, matrix multiplication.
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_cmplx_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  pSrc  points to the input matrix
-   * @param[out] pDst  points to the output matrix
-   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA   points to the first input matrix structure
-   * @param[in]  pSrcB   points to the second input matrix structure
-   * @param[out] pDst    points to output matrix structure
-   * @param[in]  pState  points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]  pSrcA  points to the first input matrix structure
-   * @param[in]  pSrcB  points to the second input matrix structure
-   * @param[out] pDst   points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  pSrc   points to the input matrix
-   * @param[in]  scale  scale factor
-   * @param[out] pDst   points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst);
-
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]  pSrc        points to input matrix
-   * @param[in]  scaleFract  fractional portion of the scale factor
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-  arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData);
-
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData);
-
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] S         points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows     number of rows in the matrix.
-   * @param[in]     nColumns  number of columns in the matrix.
-   * @param[in]     pData     points to the matrix data array.
-   */
-  void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];     /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;          /**< The proportional gain. */
-    float32_t Ki;          /**< The integral gain. */
-    float32_t Kd;          /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] S               points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] S  is an instance of the floating-point PID Control structure
-   */
-  void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] S   points to an instance of the Q31 PID Control structure
-   */
-
-  void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] S               points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   */
-  void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] S  points to an instance of the q15 PID Control structure
-   */
-  void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t *pData;   /**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t *pData;        /**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_mult_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-  q31_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
-  void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc);
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q15;
-
-void arm_cfft_q15(
-    const arm_cfft_instance_q15 * S,
-    q15_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q31;
-
-void arm_cfft_q31(
-    const arm_cfft_instance_q31 * S,
-    q31_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_f32;
-
-  void arm_cfft_f32(
-  const arm_cfft_instance_f32 * S,
-  float32_t * p1,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  arm_status arm_rfft_init_q15(
-  arm_rfft_instance_q15 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst);
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  arm_status arm_rfft_init_q31(
-  arm_rfft_instance_q31 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-typedef struct
-  {
-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-    uint16_t fftLenRFFT;             /**< length of the real sequence */
-    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
-  } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-   arm_rfft_fast_instance_f32 * S,
-   uint16_t fftLen);
-
-void arm_rfft_fast_f32(
-  arm_rfft_fast_instance_f32 * S,
-  float32_t * p, float32_t * pOut,
-  uint8_t ifftFlag);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    float32_t normalize;                 /**< normalizing factor. */
-    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;               /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize);
-
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q31_t normalize;                     /**< normalizing factor. */
-    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer);
-
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-  typedef struct
-  {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q15_t normalize;                     /**< normalizing factor. */
-    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-  arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize);
-
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
-   * @param[in]     pState         points to state buffer.
-   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
-   */
-  void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer);
-
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_add_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_sub_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  scale      scale factor to be applied
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_scale_f32(
-  float32_t * pSrc,
-  float32_t scale,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q7(
-  q7_t * pSrc,
-  q7_t scaleFract,
-  int8_t shift,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q15(
-  q15_t * pSrc,
-  q15_t scaleFract,
-  int8_t shift,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]  pSrc        points to the input vector
-   * @param[in]  scaleFract  fractional portion of the scale value
-   * @param[in]  shift       number of bits to shift the result by
-   * @param[out] pDst        points to the output vector
-   * @param[in]  blockSize   number of samples in the vector
-   */
-  void arm_scale_q31(
-  q31_t * pSrc,
-  q31_t scaleFract,
-  int8_t shift,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]  pSrc       points to the input buffer
-   * @param[out] pDst       points to the output buffer
-   * @param[in]  blockSize  number of samples in each vector
-   */
-  void arm_abs_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t blockSize,
-  float32_t * result);
-
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  uint32_t blockSize,
-  q31_t * result);
-
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]  pSrcA      points to the first input vector
-   * @param[in]  pSrcB      points to the second input vector
-   * @param[in]  blockSize  number of samples in each vector
-   * @param[out] result     output result returned here
-   */
-  void arm_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q7(
-  q7_t * pSrc,
-  int8_t shiftBits,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q15(
-  q15_t * pSrc,
-  int8_t shiftBits,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_shift_q31(
-  q31_t * pSrc,
-  int8_t shiftBits,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_f32(
-  float32_t * pSrc,
-  float32_t offset,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q7(
-  q7_t * pSrc,
-  q7_t offset,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q15(
-  q15_t * pSrc,
-  q15_t offset,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[in]  offset     is the offset to be added
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_offset_q31(
-  q31_t * pSrc,
-  q31_t offset,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  pSrc       points to the input vector
-   * @param[out] pDst       points to the output vector
-   * @param[in]  blockSize  number of samples in the vector
-   */
-  void arm_negate_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a floating-point vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q7 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Copies the elements of a Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a floating-point vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector.
-   * @param[in]  value      input value to be filled
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-  void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q15(
-          q15_t * pSrcA,
-          uint32_t srcALen,
-          q15_t * pSrcB,
-          uint32_t srcBLen,
-          q15_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
-   */
-  void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-    /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
-   */
-  void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q7 sequences
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-  arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc  points to the block of input data.
-   * @param[out] pDst  points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   */
-  void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
-   * @param[in]     numTaps    number of coefficients in the filter.
-   * @param[in]     M          decimation factor.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-  arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of input samples to process per call.
-   */
-  void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L          upsample factor.
-   * @param[in]     numTaps    number of filter coefficients in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficient buffer.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     blockSize  number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-  arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
-   */
-  void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_stereo_df2T_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f64;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_stereo_df2T_f32(
-  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  S          points to an instance of the filter data structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_biquad_cascade_df2T_f64(
-  const arm_biquad_cascade_df2T_instance_f64 * S,
-  float64_t * pSrc,
-  float64_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_stereo_df2T_init_f32(
-  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] S          points to an instance of the filter data structure.
-   * @param[in]     numStages  number of 2nd order stages in the filter.
-   * @param[in]     pCoeffs    points to the filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   */
-  void arm_biquad_cascade_df2T_init_f64(
-  arm_biquad_cascade_df2T_instance_f64 * S,
-  uint8_t numStages,
-  float64_t * pCoeffs,
-  float64_t * pState);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] pState     points to the state buffer.   The array is of length numStages.
-   */
-  void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S          points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.  The array is of length numStages.
- */
-  void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages  number of stages in the filter.
-   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[out] pDst       points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize  number of samples to process per call.
- */
-  void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] S          points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to the coefficient buffer.
-   * @param[in] pState     points to the state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] S          points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;         /**< step size that control filter coefficient updates. */
-    float32_t energy;     /**< saves previous frame energy. */
-    float32_t x0;         /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] S          points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   */
-  void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
-    q15_t energy;         /**< saves previous frame energy. */
-    q15_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in]  pSrc       points to the block of input data.
-   * @param[in]  pRef       points to the block of reference data.
-   * @param[out] pOut       points to the block of output data.
-   * @param[out] pErr       points to the block of error data.
-   * @param[in]  blockSize  number of samples to process.
-   */
-  void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps    number of filter coefficients.
-   * @param[in] pCoeffs    points to coefficient buffer.
-   * @param[in] pState     points to state buffer.
-   * @param[in] mu         step size that controls filter coefficient updates.
-   * @param[in] blockSize  number of samples to process.
-   * @param[in] postShift  bit shift applied to coefficients.
-   */
-  void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-   /**
-   * @brief Correlation of Q15 sequences
-   * @param[in]  pSrcA     points to the first input sequence.
-   * @param[in]  srcALen   length of the first input sequence.
-   * @param[in]  pSrcB     points to the second input sequence.
-   * @param[in]  srcBLen   length of the second input sequence.
-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   */
-  void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-
-  void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-
-  void arm_correlate_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in]  pSrcA     points to the first input sequence.
-   * @param[in]  srcALen   length of the first input sequence.
-   * @param[in]  pSrcB     points to the second input sequence.
-   * @param[in]  srcBLen   length of the second input sequence.
-   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   */
-  void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
- /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA      points to the first input sequence.
-   * @param[in]  srcALen    length of the first input sequence.
-   * @param[in]  pSrcB      points to the second input sequence.
-   * @param[in]  srcBLen    length of the second input sequence.
-   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   */
-  void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in]  pSrcA    points to the first input sequence.
-   * @param[in]  srcALen  length of the first input sequence.
-   * @param[in]  pSrcB    points to the second input sequence.
-   * @param[in]  srcBLen  length of the second input sequence.
-   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   */
-  void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  pSrc        points to the block of input data.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   */
-  void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  pSrc         points to the block of input data.
-   * @param[out] pDst         points to the block of output data
-   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
-   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   */
-  void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     pCoeffs    points to the array of filter coefficients.
-   * @param[in]     pState     points to the state buffer.
-   * @param[in]     pTapDelay  points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   */
-  void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta   input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cos output.
-   */
-  void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCosVal);
-
-
-  /**
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees
-   * @param[out] pSinVal  points to the processed sine output.
-   * @param[out] pCosVal  points to the processed cosine output.
-   */
-  void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  pSrc        points to the input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   *
-   * \par
-   * \image html PID.gif "Proportional Integral Derivative Controller"
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.
-   * The proportional value determines the reaction to the current error,
-   * the integral value determines the reaction based on the sum of recent errors,
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
-   * A separate instance structure must be defined for each PID Controller.
-   * There are separate instance structure declarations for each of the 3 supported data types.
-   *
-   * \par Reset Functions
-   * There is also an associated reset function for each data type which clears the state array.
-   *
-   * \par Initialization Functions
-   * There is also an associated initialization function for each data type.
-   * The initialization function performs the following operations:
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.
-   *
-   * \par
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
-   *
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the fixed-point versions of the PID Controller functions.
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] S   is an instance of the floating-point PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
-  arm_pid_instance_f32 * S,
-  float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] S  points to an instance of the Q31 PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 64-bit accumulator.
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
-   * Thus, if the accumulator result overflows it wraps around rather than clip.
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
-  arm_pid_instance_q31 * S,
-  q31_t in)
-  {
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] S   points to an instance of the Q15 PID Control structure
-   * @param[in]     in  input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using a 64-bit internal accumulator.
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
-  arm_pid_instance_q15 * S,
-  q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-#if defined (ARM_MATH_DSP)
-    __SIMD32_TYPE *vstate;
-
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    vstate = __SIMD32_CONST(S->state);
-    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-  }
-
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * src,
-  arm_matrix_instance_f32 * dst);
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  src   points to the instance of the input floating-point matrix structure.
-   * @param[out] dst   points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-  arm_status arm_mat_inverse_f64(
-  const arm_matrix_instance_f64 * src,
-  arm_matrix_instance_f64 * dst);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]  Ia       input three-phase coordinate <code>a</code>
-   * @param[in]  Ib       input three-phase coordinate <code>b</code>
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
-  float32_t Ia,
-  float32_t Ib,
-  float32_t * pIalpha,
-  float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-  }
-
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]  Ia       input three-phase coordinate <code>a</code>
-   * @param[in]  Ib       input three-phase coordinate <code>b</code>
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
-  q31_t Ia,
-  q31_t Ib,
-  q31_t * pIalpha,
-  q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pIa,
-  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
-  }
-
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version
-   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out] pIa     points to output three-phase coordinate <code>a</code>
-   * @param[out] pIb     points to output three-phase coordinate <code>b</code>
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pIa,
-  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  pSrc       input pointer
-   * @param[out] pDst       output pointer
-   * @param[in]  blockSize  number of samples to process
-   */
-  void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
-   * from the stationary to the moving reference frame and control the spatial relationship between
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]  Ialpha  input two-phase vector coordinate alpha
-   * @param[in]  Ibeta   input two-phase vector coordinate beta
-   * @param[out] pId     points to output   rotor reference frame d
-   * @param[out] pIq     points to output   rotor reference frame q
-   * @param[in]  sinVal  sine value of rotation angle theta
-   * @param[in]  cosVal  cosine value of rotation angle theta
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pId,
-  float32_t * pIq,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-  }
-
-
-  /**
-   * @brief  Park transform for Q31 version
-   * @param[in]  Ialpha  input two-phase vector coordinate alpha
-   * @param[in]  Ibeta   input two-phase vector coordinate beta
-   * @param[out] pId     points to output rotor reference frame d
-   * @param[out] pIq     points to output rotor reference frame q
-   * @param[in]  sinVal  sine value of rotation angle theta
-   * @param[in]  cosVal  cosine value of rotation angle theta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pId,
-  q31_t * pIq,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]  Id       input coordinate of rotor reference frame d
-   * @param[in]  Iq       input coordinate of rotor reference frame q
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]  sinVal   sine value of rotation angle theta
-   * @param[in]  cosVal   cosine value of rotation angle theta
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
-  float32_t Id,
-  float32_t Iq,
-  float32_t * pIalpha,
-  float32_t * pIbeta,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for   Q31 version
-   * @param[in]  Id       input coordinate of rotor reference frame d
-   * @param[in]  Iq       input coordinate of rotor reference frame q
-   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]  sinVal   sine value of rotation angle theta
-   * @param[in]  cosVal   cosine value of rotation angle theta
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
-  q31_t Id,
-  q31_t Iq,
-  q31_t * pIalpha,
-  q31_t * pIbeta,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   *
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table
-   * if x is below input range and returns last value of table if x is above range.
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
-   * @param[in]     x  input sample to process
-   * @return y processed output sample.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
-  arm_linear_interp_instance_f32 * S,
-  float32_t x)
-  {
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t *pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if (i < 0)
-    {
-      /* Iniatilize output for below specified range as least output value of table */
-      y = pYData[0];
-    }
-    else if ((uint32_t)i >= S->nValues)
-    {
-      /* Iniatilize output for above specified range as last output value of table */
-      y = pYData[S->nValues - 1];
-    }
-    else
-    {
-      /* Calculation of nearest input values */
-      x0 = S->x1 +  i      * xSpacing;
-      x1 = S->x1 + (i + 1) * xSpacing;
-
-      /* Read of nearest output values */
-      y0 = pYData[i];
-      y1 = pYData[i + 1];
-
-      /* Calculation of output */
-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-  }
-
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q31 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
-  q31_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (q31_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* shift left by 11 to keep fract in 1.31 format */
-      fract = (x & 0x000FFFFF) << 11;
-
-      /* Read two nearest output values from the index in 1.31(q31) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-      /* Convert y to 1.31 format */
-      return (y << 1u);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q15 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
-  q15_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (int32_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if (index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-      y = ((q63_t) y0 * (0xFFFFF - fract));
-
-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-      y += ((q63_t) y1 * (fract));
-
-      /* convert y to 1.15 format */
-      return (q15_t) (y >> 20);
-    }
-  }
-
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] pYData   pointer to Q7 Linear Interpolation table
-   * @param[in] x        input sample to process
-   * @param[in] nValues  number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
-  q7_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0)
-    {
-      return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-    if (index >= (nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index and are in 1.7(q7) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1];
-
-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-      y = ((y0 * (0xFFFFF - fract)));
-
-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-      y += (y1 * fract);
-
-      /* convert y to 1.7(q7) format */
-      return (q7_t) (y >> 20);
-     }
-  }
-
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  sin(x).
-   */
-  float32_t arm_sin_f32(
-  float32_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q31_t arm_sin_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  sin(x).
-   */
-  q15_t arm_sin_q15(
-  q15_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x  input value in radians.
-   * @return  cos(x).
-   */
-  float32_t arm_cos_f32(
-  float32_t x);
-
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q31_t arm_cos_q31(
-  q31_t x);
-
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x  Scaled input value in radians.
-   * @return  cos(x).
-   */
-  q15_t arm_cos_q15(
-  q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate, and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in    input value.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
-  float32_t in,
-  float32_t * pOut)
-  {
-    if (in >= 0.0f)
-    {
-
-#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
-      *pOut = __sqrtf(in);
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-      *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined(__GNUC__)
-      *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
-      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-#else
-      *pOut = sqrtf(in);
-#endif
-
-      return (ARM_MATH_SUCCESS);
-    }
-    else
-    {
-      *pOut = 0.0f;
-      return (ARM_MATH_ARGUMENT_ERROR);
-    }
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut);
-
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out] pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const int32_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  int32_t * dst,
-  int32_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (int32_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value  */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q15_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q15_t * dst,
-  q15_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (q15_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q7_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if (wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q7_t * dst,
-  q7_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if (dst == (q7_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if (rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output value.
-   */
-  void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  pSrc        points to the complex input vector
-   * @param[out] pDst        points to the real output vector
-   * @param[in]  numSamples  number of complex samples in the input vector
-   */
-  void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult);
-
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult);
-
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   * @param[out] realResult  real part of the result returned here
-   * @param[out] imagResult  imaginary part of the result returned here
-   */
-  void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult);
-
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  pSrcCmplx   points to the complex input vector
-   * @param[in]  pSrcReal    points to the real input vector
-   * @param[out] pCmplxDst   points to the complex output vector
-   * @param[in]  numSamples  number of samples in each vector
-   */
-  void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] result     is output pointer
-   * @param[in]  index      is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * result,
-  uint32_t * index);
-
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[in]  blockSize  is the number of samples to process
-   * @param[out] pResult    is output pointer
-   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
-   */
-  void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-  void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  pSrcA       points to the first input vector
-   * @param[in]  pSrcB       points to the second input vector
-   * @param[out] pDst        points to the output vector
-   * @param[in]  numSamples  number of complex samples in each vector
-   */
-  void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q31 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q15 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector.
-   * @param[in]  pSrc       points to the floating-point input vector
-   * @param[out] pDst       points to the Q7 output vector
-   * @param[in]  blockSize  length of the input vector
-   */
-  void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  pSrc       is input pointer
-   * @param[out] pDst       is output pointer
-   * @param[in]  blockSize  is the number of samples to process
-   */
-  void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate.
-  * @param[in]     Y  interpolation coordinate.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
-  const arm_bilinear_interp_instance_f32 * S,
-  float32_t X,
-  float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-  }
-
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
-  arm_bilinear_interp_instance_q31 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
-    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
-    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return ((q31_t)(acc << 2));
-  }
-
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
-  arm_bilinear_interp_instance_q15 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return ((q15_t)(acc >> 36));
-  }
-
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] S  points to an instance of the interpolation structure.
-  * @param[in]     X  interpolation coordinate in 12.20 format.
-  * @param[in]     Y  interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
-  arm_bilinear_interp_instance_q7 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return ((q7_t)(acc >> 40));
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
-    a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
-    a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
-    a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if   defined ( __CC_ARM )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("push")         \
-       _Pragma ("O1")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define LOW_OPTIMIZATION_EXIT \
-       _Pragma ("pop")
-  #else
-    #define LOW_OPTIMIZATION_EXIT
-  #endif
-
-  /* Enter low optimization region - place directly above function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
-  #define LOW_OPTIMIZATION_ENTER \
-       __attribute__(( optimize("-O1") ))
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define LOW_OPTIMIZATION_EXIT
-
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h
deleted file mode 100644
index 8b989f851a..0000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_compiler.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_compiler.h
- * @brief    CMSIS compiler generic header file
- * @version  V5.0.1
- * @date     30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include <stdint.h>
-
-/*
- * ARM Compiler 4/5
- */
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-
-/*
- * ARM Compiler 6 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
-
-  #ifndef   __ASM
-    #define __ASM                     __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                  inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE           static inline
-  #endif
-
-  #include <cmsis_iar.h>
-
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN               __noreturn
-  #endif
-  #ifndef   __USED
-    #define __USED                    __root
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                    __weak
-  #endif
-  #ifndef   __UNALIGNED_UINT32
-    __packed struct T_UINT32 { uint32_t v; };
-      #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                  __packed
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT           __packed struct
-  #endif
-
-
-/*
- * TI ARM Compiler
- */
-#elif defined ( __TI_ARM__ )
-  #include <cmsis_ccs.h>
-
-  #ifndef   __ASM
-    #define __ASM                     __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                  inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE           static inline
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN               __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                    __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                    __attribute__((weak))
-  #endif
-  #ifndef   __UNALIGNED_UINT32
-    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)              __attribute__((aligned(x)))
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                  __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT           struct __attribute__((packed))
-  #endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-  #ifndef   __ASM
-    #define __ASM                     __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                  inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE           static inline
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN               __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                    __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                    __attribute__((weak))
-  #endif
-  #ifndef   __UNALIGNED_UINT32
-    struct __packed__ T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)              __align(x)
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                  __packed__
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT           struct __packed__
-  #endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
-   #include <cmsis_csm.h>
-
- #ifndef   __ASM
-    #define __ASM                     _asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                  inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE           static inline
-  #endif
-  #ifndef   __NO_RETURN
-    // NO RETURN is automatically detected hence no warning here
-    #define __NO_RETURN
-  #endif
-  #ifndef   __USED
-    #warning No compiler specific solution for __USED. __USED is ignored.
-    #define __USED
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                    __weak
-  #endif
-  #ifndef   __UNALIGNED_UINT32
-    @packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                  @packed
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT           @packed struct
-  #endif
-
-
-#else
-  #error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h
deleted file mode 100644
index 074cd7ab32..0000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/cmsis_gcc.h
+++ /dev/null
@@ -1,1899 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_gcc.h
- * @brief    CMSIS compiler GCC header file
- * @version  V5.0.1
- * @date     02. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE           static inline
-#endif
-#ifndef   __NO_RETURN
-  #define __NO_RETURN               __attribute__((noreturn))
-#endif
-#ifndef   __USED
-  #define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpacked"
-#pragma GCC diagnostic ignored "-Wattributes"
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-#pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                  __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT           struct __attribute__((packed, aligned(1)))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
-  return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#else
-  (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-//{
-//  __ASM volatile ("nop");
-//}
-#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-//{
-//  __ASM volatile ("wfi");
-//}
-#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-//{
-//  __ASM volatile ("wfe");
-//}
-#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-//{
-//  __ASM volatile ("sev");
-//}
-#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
-#else
-  int32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-  return(result);
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h b/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h
deleted file mode 100644
index 2da78d3983..0000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/CMSIS/Include/core_cm4.h
+++ /dev/null
@@ -1,2103 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
- #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM4_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000U
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt b/lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt
deleted file mode 100644
index 8dada3edaf..0000000000
--- a/lib/arm_atsam/packs/arm/cmsis/5.0.1/LICENSE.txt
+++ /dev/null
@@ -1,201 +0,0 @@
-                                 Apache License
-                           Version 2.0, January 2004
-                        http://www.apache.org/licenses/
-
-   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
-
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-      direction or management of such entity, whether by contract or
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-      outstanding shares, or (iii) beneficial ownership of such entity.
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-      reproduction, and distribution of the Work otherwise complies with
-      the conditions stated in this License.
-
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-      any Contribution intentionally submitted for inclusion in the Work
-      by You to the Licensor shall be under the terms and conditions of
-      this License, without any additional terms or conditions.
-      Notwithstanding the above, nothing herein shall supersede or modify
-      the terms of any separate license agreement you may have executed
-      with Licensor regarding such Contributions.
-
-   6. Trademarks. This License does not grant permission to use the trade
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-      except as required for reasonable and customary use in describing the
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-
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-   Unless required by applicable law or agreed to in writing, software
-   distributed under the License is distributed on an "AS IS" BASIS,
-   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-   See the License for the specific language governing permissions and
-   limitations under the License.
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld
deleted file mode 100644
index 1c63547863..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld
+++ /dev/null
@@ -1,185 +0,0 @@
-/**
- * \file
- *
- * \brief Linker script for running in internal FLASH on the SAMD51J18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-/*rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000*/
-  rom      (rx)  : ORIGIN = 0x00004000, LENGTH = 0x0003C000
-  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
-  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
-  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
-
-/* The heap size used by the application. */
-HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x800;
-
-_srom = ORIGIN(rom);
-_lrom = LENGTH(rom);
-_erom = ORIGIN(rom) + LENGTH(rom);
-_sram = ORIGIN(ram);
-_lram = LENGTH(ram);
-_eram = ORIGIN(ram) + LENGTH(ram);
-
-/* Section Definitions */
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        _sfixed = .;
-        KEEP(*(.vectors .vectors.*))
-        *(.text .text.* .gnu.linkonce.t.*)
-        *(.glue_7t) *(.glue_7)
-        *(.rodata .rodata* .gnu.linkonce.r.*)
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-
-        /* Support C constructors, and C destructors in both user code
-           and the C library. This also provides support for C++ code. */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-
-        . = ALIGN(4);
-        _efixed = .;            /* End of text section */
-    } > rom
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    PROVIDE_HIDDEN (__exidx_start = .);
-    .ARM.exidx :
-    {
-      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > rom
-    PROVIDE_HIDDEN (__exidx_end = .);
-
-    . = ALIGN(4);
-    _etext = .;
-
-    .relocate : AT (_etext)
-    {
-        . = ALIGN(4);
-        _srelocate = .;
-        *(.ramfunc .ramfunc.*);
-        *(.data .data.*);
-        . = ALIGN(4);
-        _erelocate = .;
-    } > ram
-
-    .bkupram (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sbkupram = .;
-        *(.bkupram .bkupram.*);
-        . = ALIGN(8);
-        _ebkupram = .;
-    } > bkupram
-
-    .qspi (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sqspi = .;
-        *(.qspi .qspi.*);
-        . = ALIGN(8);
-        _eqspi = .;
-    } > qspi
-
-    /* .bss section which is used for uninitialized data */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _sbss = . ;
-        _szero = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        . = ALIGN(4);
-        _ebss = . ;
-        _ezero = .;
-    } > ram
-
-    /* .heap section for syscalls */
-    .heap (NOLOAD) :
-    {
-        . = ALIGN(4);
-        _end = .;
-        end = .;
-        _heap_start = .;
-        . = . + HEAP_SIZE;
-        _heap_end = .;
-    } > ram
-
-    /* stack section */
-    .stack (NOLOAD):
-    {
-        . = ALIGN(8);
-        _sstack = .;
-        . = . + STACK_SIZE;
-        . = ALIGN(8);
-        _estack = .;
-    } > ram
-
-    . = ALIGN(4);
-    _end = . ;
-}
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h
deleted file mode 100644
index 80801fc128..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * \file
- *
- * \brief Component version header file
- *
- * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
- *
- * \license_start
- *
- * \page License
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \license_stop
- *
- */
-
-#ifndef _COMPONENT_VERSION_H_INCLUDED
-#define _COMPONENT_VERSION_H_INCLUDED
-
-#define COMPONENT_VERSION_MAJOR 1
-#define COMPONENT_VERSION_MINOR 0
-
-//
-// The COMPONENT_VERSION define is composed of the major and the minor version number.
-//
-// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
-// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION
-// is at least 8 digits long.
-//
-#define COMPONENT_VERSION 00010000
-
-//
-// The build number does not refer to the component, but to the build number
-// of the device pack that provides the component.
-//
-#define BUILD_NUMBER 70
-
-//
-// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
-//
-#define COMPONENT_VERSION_STRING "1.0"
-
-//
-// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
-//
-// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
-//
-//     "%Y-%m-%d %H:%M:%S"
-//
-//
-#define COMPONENT_DATE_STRING "2017-08-09 09:59:41"
-
-#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
-
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h
deleted file mode 100644
index 24623d00ac..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h
+++ /dev/null
@@ -1,598 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for AC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_AC_COMPONENT_
-#define _SAMD51_AC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR AC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_AC Analog Comparators */
-/*@{*/
-
-#define AC_U2501
-#define REV_AC                      0x100
-
-/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CTRLA_OFFSET             0x00         /**< \brief (AC_CTRLA offset) Control A */
-#define AC_CTRLA_RESETVALUE         _U_(0x00)    /**< \brief (AC_CTRLA reset_value) Control A */
-
-#define AC_CTRLA_SWRST_Pos          0            /**< \brief (AC_CTRLA) Software Reset */
-#define AC_CTRLA_SWRST              (_U_(0x1) << AC_CTRLA_SWRST_Pos)
-#define AC_CTRLA_ENABLE_Pos         1            /**< \brief (AC_CTRLA) Enable */
-#define AC_CTRLA_ENABLE             (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
-#define AC_CTRLA_MASK               _U_(0x03)    /**< \brief (AC_CTRLA) MASK Register */
-
-/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W  8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  START0:1;         /*!< bit:      0  Comparator 0 Start Comparison      */
-    uint8_t  START1:1;         /*!< bit:      1  Comparator 1 Start Comparison      */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  START:2;          /*!< bit:  0.. 1  Comparator x Start Comparison      */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CTRLB_OFFSET             0x01         /**< \brief (AC_CTRLB offset) Control B */
-#define AC_CTRLB_RESETVALUE         _U_(0x00)    /**< \brief (AC_CTRLB reset_value) Control B */
-
-#define AC_CTRLB_START0_Pos         0            /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
-#define AC_CTRLB_START0             (_U_(1) << AC_CTRLB_START0_Pos)
-#define AC_CTRLB_START1_Pos         1            /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
-#define AC_CTRLB_START1             (_U_(1) << AC_CTRLB_START1_Pos)
-#define AC_CTRLB_START_Pos          0            /**< \brief (AC_CTRLB) Comparator x Start Comparison */
-#define AC_CTRLB_START_Msk          (_U_(0x3) << AC_CTRLB_START_Pos)
-#define AC_CTRLB_START(value)       (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
-#define AC_CTRLB_MASK               _U_(0x03)    /**< \brief (AC_CTRLB) MASK Register */
-
-/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t COMPEO0:1;        /*!< bit:      0  Comparator 0 Event Output Enable   */
-    uint16_t COMPEO1:1;        /*!< bit:      1  Comparator 1 Event Output Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t WINEO0:1;         /*!< bit:      4  Window 0 Event Output Enable       */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t COMPEI0:1;        /*!< bit:      8  Comparator 0 Event Input Enable    */
-    uint16_t COMPEI1:1;        /*!< bit:      9  Comparator 1 Event Input Enable    */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t INVEI0:1;         /*!< bit:     12  Comparator 0 Input Event Invert Enable */
-    uint16_t INVEI1:1;         /*!< bit:     13  Comparator 1 Input Event Invert Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t COMPEO:2;         /*!< bit:  0.. 1  Comparator x Event Output Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t WINEO:1;          /*!< bit:      4  Window x Event Output Enable       */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t COMPEI:2;         /*!< bit:  8.. 9  Comparator x Event Input Enable    */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t INVEI:2;          /*!< bit: 12..13  Comparator x Input Event Invert Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} AC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_EVCTRL_OFFSET            0x02         /**< \brief (AC_EVCTRL offset) Event Control */
-#define AC_EVCTRL_RESETVALUE        _U_(0x0000)  /**< \brief (AC_EVCTRL reset_value) Event Control */
-
-#define AC_EVCTRL_COMPEO0_Pos       0            /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
-#define AC_EVCTRL_COMPEO0           (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
-#define AC_EVCTRL_COMPEO1_Pos       1            /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
-#define AC_EVCTRL_COMPEO1           (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
-#define AC_EVCTRL_COMPEO_Pos        0            /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
-#define AC_EVCTRL_COMPEO_Msk        (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
-#define AC_EVCTRL_COMPEO(value)     (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
-#define AC_EVCTRL_WINEO0_Pos        4            /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
-#define AC_EVCTRL_WINEO0            (_U_(1) << AC_EVCTRL_WINEO0_Pos)
-#define AC_EVCTRL_WINEO_Pos         4            /**< \brief (AC_EVCTRL) Window x Event Output Enable */
-#define AC_EVCTRL_WINEO_Msk         (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
-#define AC_EVCTRL_WINEO(value)      (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
-#define AC_EVCTRL_COMPEI0_Pos       8            /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
-#define AC_EVCTRL_COMPEI0           (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
-#define AC_EVCTRL_COMPEI1_Pos       9            /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
-#define AC_EVCTRL_COMPEI1           (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
-#define AC_EVCTRL_COMPEI_Pos        8            /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
-#define AC_EVCTRL_COMPEI_Msk        (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
-#define AC_EVCTRL_COMPEI(value)     (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
-#define AC_EVCTRL_INVEI0_Pos        12           /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
-#define AC_EVCTRL_INVEI0            (_U_(1) << AC_EVCTRL_INVEI0_Pos)
-#define AC_EVCTRL_INVEI1_Pos        13           /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
-#define AC_EVCTRL_INVEI1            (_U_(1) << AC_EVCTRL_INVEI1_Pos)
-#define AC_EVCTRL_INVEI_Pos         12           /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
-#define AC_EVCTRL_INVEI_Msk         (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
-#define AC_EVCTRL_INVEI(value)      (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
-#define AC_EVCTRL_MASK              _U_(0x3313)  /**< \brief (AC_EVCTRL) MASK Register */
-
-/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
-    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTENCLR_OFFSET          0x04         /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
-#define AC_INTENCLR_RESETVALUE      _U_(0x00)    /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define AC_INTENCLR_COMP0_Pos       0            /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
-#define AC_INTENCLR_COMP0           (_U_(1) << AC_INTENCLR_COMP0_Pos)
-#define AC_INTENCLR_COMP1_Pos       1            /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
-#define AC_INTENCLR_COMP1           (_U_(1) << AC_INTENCLR_COMP1_Pos)
-#define AC_INTENCLR_COMP_Pos        0            /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
-#define AC_INTENCLR_COMP_Msk        (_U_(0x3) << AC_INTENCLR_COMP_Pos)
-#define AC_INTENCLR_COMP(value)     (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
-#define AC_INTENCLR_WIN0_Pos        4            /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
-#define AC_INTENCLR_WIN0            (_U_(1) << AC_INTENCLR_WIN0_Pos)
-#define AC_INTENCLR_WIN_Pos         4            /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
-#define AC_INTENCLR_WIN_Msk         (_U_(0x1) << AC_INTENCLR_WIN_Pos)
-#define AC_INTENCLR_WIN(value)      (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
-#define AC_INTENCLR_MASK            _U_(0x13)    /**< \brief (AC_INTENCLR) MASK Register */
-
-/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
-    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTENSET_OFFSET          0x05         /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
-#define AC_INTENSET_RESETVALUE      _U_(0x00)    /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
-
-#define AC_INTENSET_COMP0_Pos       0            /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
-#define AC_INTENSET_COMP0           (_U_(1) << AC_INTENSET_COMP0_Pos)
-#define AC_INTENSET_COMP1_Pos       1            /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
-#define AC_INTENSET_COMP1           (_U_(1) << AC_INTENSET_COMP1_Pos)
-#define AC_INTENSET_COMP_Pos        0            /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
-#define AC_INTENSET_COMP_Msk        (_U_(0x3) << AC_INTENSET_COMP_Pos)
-#define AC_INTENSET_COMP(value)     (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
-#define AC_INTENSET_WIN0_Pos        4            /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
-#define AC_INTENSET_WIN0            (_U_(1) << AC_INTENSET_WIN0_Pos)
-#define AC_INTENSET_WIN_Pos         4            /**< \brief (AC_INTENSET) Window x Interrupt Enable */
-#define AC_INTENSET_WIN_Msk         (_U_(0x1) << AC_INTENSET_WIN_Pos)
-#define AC_INTENSET_WIN(value)      (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
-#define AC_INTENSET_MASK            _U_(0x13)    /**< \brief (AC_INTENSET) MASK Register */
-
-/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0                       */
-    __I uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1                       */
-    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    __I uint8_t  WIN0:1;           /*!< bit:      4  Window 0                           */
-    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x                       */
-    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    __I uint8_t  WIN:1;            /*!< bit:      4  Window x                           */
-    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_INTFLAG_OFFSET           0x06         /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define AC_INTFLAG_RESETVALUE       _U_(0x00)    /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define AC_INTFLAG_COMP0_Pos        0            /**< \brief (AC_INTFLAG) Comparator 0 */
-#define AC_INTFLAG_COMP0            (_U_(1) << AC_INTFLAG_COMP0_Pos)
-#define AC_INTFLAG_COMP1_Pos        1            /**< \brief (AC_INTFLAG) Comparator 1 */
-#define AC_INTFLAG_COMP1            (_U_(1) << AC_INTFLAG_COMP1_Pos)
-#define AC_INTFLAG_COMP_Pos         0            /**< \brief (AC_INTFLAG) Comparator x */
-#define AC_INTFLAG_COMP_Msk         (_U_(0x3) << AC_INTFLAG_COMP_Pos)
-#define AC_INTFLAG_COMP(value)      (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
-#define AC_INTFLAG_WIN0_Pos         4            /**< \brief (AC_INTFLAG) Window 0 */
-#define AC_INTFLAG_WIN0             (_U_(1) << AC_INTFLAG_WIN0_Pos)
-#define AC_INTFLAG_WIN_Pos          4            /**< \brief (AC_INTFLAG) Window x */
-#define AC_INTFLAG_WIN_Msk          (_U_(0x1) << AC_INTFLAG_WIN_Pos)
-#define AC_INTFLAG_WIN(value)       (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
-#define AC_INTFLAG_MASK             _U_(0x13)    /**< \brief (AC_INTFLAG) MASK Register */
-
-/* -------- AC_STATUSA : (AC Offset: 0x07) (R/   8) Status A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
-    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_STATUSA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_STATUSA_OFFSET           0x07         /**< \brief (AC_STATUSA offset) Status A */
-#define AC_STATUSA_RESETVALUE       _U_(0x00)    /**< \brief (AC_STATUSA reset_value) Status A */
-
-#define AC_STATUSA_STATE0_Pos       0            /**< \brief (AC_STATUSA) Comparator 0 Current State */
-#define AC_STATUSA_STATE0           (_U_(1) << AC_STATUSA_STATE0_Pos)
-#define AC_STATUSA_STATE1_Pos       1            /**< \brief (AC_STATUSA) Comparator 1 Current State */
-#define AC_STATUSA_STATE1           (_U_(1) << AC_STATUSA_STATE1_Pos)
-#define AC_STATUSA_STATE_Pos        0            /**< \brief (AC_STATUSA) Comparator x Current State */
-#define AC_STATUSA_STATE_Msk        (_U_(0x3) << AC_STATUSA_STATE_Pos)
-#define AC_STATUSA_STATE(value)     (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
-#define AC_STATUSA_WSTATE0_Pos      4            /**< \brief (AC_STATUSA) Window 0 Current State */
-#define AC_STATUSA_WSTATE0_Msk      (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0(value)   (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
-#define   AC_STATUSA_WSTATE0_ABOVE_Val    _U_(0x0)   /**< \brief (AC_STATUSA) Signal is above window */
-#define   AC_STATUSA_WSTATE0_INSIDE_Val   _U_(0x1)   /**< \brief (AC_STATUSA) Signal is inside window */
-#define   AC_STATUSA_WSTATE0_BELOW_Val    _U_(0x2)   /**< \brief (AC_STATUSA) Signal is below window */
-#define AC_STATUSA_WSTATE0_ABOVE    (AC_STATUSA_WSTATE0_ABOVE_Val  << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0_INSIDE   (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_WSTATE0_BELOW    (AC_STATUSA_WSTATE0_BELOW_Val  << AC_STATUSA_WSTATE0_Pos)
-#define AC_STATUSA_MASK             _U_(0x33)    /**< \brief (AC_STATUSA) MASK Register */
-
-/* -------- AC_STATUSB : (AC Offset: 0x08) (R/   8) Status B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  READY0:1;         /*!< bit:      0  Comparator 0 Ready                 */
-    uint8_t  READY1:1;         /*!< bit:      1  Comparator 1 Ready                 */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  READY:2;          /*!< bit:  0.. 1  Comparator x Ready                 */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_STATUSB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_STATUSB_OFFSET           0x08         /**< \brief (AC_STATUSB offset) Status B */
-#define AC_STATUSB_RESETVALUE       _U_(0x00)    /**< \brief (AC_STATUSB reset_value) Status B */
-
-#define AC_STATUSB_READY0_Pos       0            /**< \brief (AC_STATUSB) Comparator 0 Ready */
-#define AC_STATUSB_READY0           (_U_(1) << AC_STATUSB_READY0_Pos)
-#define AC_STATUSB_READY1_Pos       1            /**< \brief (AC_STATUSB) Comparator 1 Ready */
-#define AC_STATUSB_READY1           (_U_(1) << AC_STATUSB_READY1_Pos)
-#define AC_STATUSB_READY_Pos        0            /**< \brief (AC_STATUSB) Comparator x Ready */
-#define AC_STATUSB_READY_Msk        (_U_(0x3) << AC_STATUSB_READY_Pos)
-#define AC_STATUSB_READY(value)     (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
-#define AC_STATUSB_MASK             _U_(0x03)    /**< \brief (AC_STATUSB) MASK Register */
-
-/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_DBGCTRL_OFFSET           0x09         /**< \brief (AC_DBGCTRL offset) Debug Control */
-#define AC_DBGCTRL_RESETVALUE       _U_(0x00)    /**< \brief (AC_DBGCTRL reset_value) Debug Control */
-
-#define AC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (AC_DBGCTRL) Debug Run */
-#define AC_DBGCTRL_DBGRUN           (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
-#define AC_DBGCTRL_MASK             _U_(0x01)    /**< \brief (AC_DBGCTRL) MASK Register */
-
-/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W  8) Window Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  WEN0:1;           /*!< bit:      0  Window 0 Mode Enable               */
-    uint8_t  WINTSEL0:2;       /*!< bit:  1.. 2  Window 0 Interrupt Selection       */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_WINCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_WINCTRL_OFFSET           0x0A         /**< \brief (AC_WINCTRL offset) Window Control */
-#define AC_WINCTRL_RESETVALUE       _U_(0x00)    /**< \brief (AC_WINCTRL reset_value) Window Control */
-
-#define AC_WINCTRL_WEN0_Pos         0            /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
-#define AC_WINCTRL_WEN0             (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
-#define AC_WINCTRL_WINTSEL0_Pos     1            /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
-#define AC_WINCTRL_WINTSEL0_Msk     (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0(value)  (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
-#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   _U_(0x0)   /**< \brief (AC_WINCTRL) Interrupt on signal above window */
-#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  _U_(0x1)   /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
-#define   AC_WINCTRL_WINTSEL0_BELOW_Val   _U_(0x2)   /**< \brief (AC_WINCTRL) Interrupt on signal below window */
-#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3)   /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
-#define AC_WINCTRL_WINTSEL0_ABOVE   (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_INSIDE  (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_BELOW   (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
-#define AC_WINCTRL_MASK             _U_(0x07)    /**< \brief (AC_WINCTRL) MASK Register */
-
-/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W  8) Scaler n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  VALUE:6;          /*!< bit:  0.. 5  Scaler Value                       */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AC_SCALER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_SCALER_OFFSET            0x0C         /**< \brief (AC_SCALER offset) Scaler n */
-#define AC_SCALER_RESETVALUE        _U_(0x00)    /**< \brief (AC_SCALER reset_value) Scaler n */
-
-#define AC_SCALER_VALUE_Pos         0            /**< \brief (AC_SCALER) Scaler Value */
-#define AC_SCALER_VALUE_Msk         (_U_(0x3F) << AC_SCALER_VALUE_Pos)
-#define AC_SCALER_VALUE(value)      (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
-#define AC_SCALER_MASK              _U_(0x3F)    /**< \brief (AC_SCALER) MASK Register */
-
-/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t SINGLE:1;         /*!< bit:      2  Single-Shot Mode                   */
-    uint32_t INTSEL:2;         /*!< bit:  3.. 4  Interrupt Selection                */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t MUXNEG:3;         /*!< bit:  8..10  Negative Input Mux Selection       */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t MUXPOS:3;         /*!< bit: 12..14  Positive Input Mux Selection       */
-    uint32_t SWAP:1;           /*!< bit:     15  Swap Inputs and Invert             */
-    uint32_t SPEED:2;          /*!< bit: 16..17  Speed Selection                    */
-    uint32_t :1;               /*!< bit:     18  Reserved                           */
-    uint32_t HYSTEN:1;         /*!< bit:     19  Hysteresis Enable                  */
-    uint32_t HYST:2;           /*!< bit: 20..21  Hysteresis Level                   */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t FLEN:3;           /*!< bit: 24..26  Filter Length                      */
-    uint32_t :1;               /*!< bit:     27  Reserved                           */
-    uint32_t OUT:2;            /*!< bit: 28..29  Output                             */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} AC_COMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_COMPCTRL_OFFSET          0x10         /**< \brief (AC_COMPCTRL offset) Comparator Control n */
-#define AC_COMPCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
-
-#define AC_COMPCTRL_ENABLE_Pos      1            /**< \brief (AC_COMPCTRL) Enable */
-#define AC_COMPCTRL_ENABLE          (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
-#define AC_COMPCTRL_SINGLE_Pos      2            /**< \brief (AC_COMPCTRL) Single-Shot Mode */
-#define AC_COMPCTRL_SINGLE          (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
-#define AC_COMPCTRL_INTSEL_Pos      3            /**< \brief (AC_COMPCTRL) Interrupt Selection */
-#define AC_COMPCTRL_INTSEL_Msk      (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL(value)   (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
-#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   _U_(0x0)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
-#define   AC_COMPCTRL_INTSEL_RISING_Val   _U_(0x1)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
-#define   AC_COMPCTRL_INTSEL_FALLING_Val  _U_(0x2)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
-#define   AC_COMPCTRL_INTSEL_EOC_Val      _U_(0x3)   /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
-#define AC_COMPCTRL_INTSEL_TOGGLE   (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_RISING   (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_FALLING  (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_INTSEL_EOC      (AC_COMPCTRL_INTSEL_EOC_Val    << AC_COMPCTRL_INTSEL_Pos)
-#define AC_COMPCTRL_RUNSTDBY_Pos    6            /**< \brief (AC_COMPCTRL) Run in Standby */
-#define AC_COMPCTRL_RUNSTDBY        (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
-#define AC_COMPCTRL_MUXNEG_Pos      8            /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
-#define AC_COMPCTRL_MUXNEG_Msk      (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG(value)   (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
-#define   AC_COMPCTRL_MUXNEG_PIN0_Val     _U_(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define   AC_COMPCTRL_MUXNEG_PIN1_Val     _U_(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define   AC_COMPCTRL_MUXNEG_PIN2_Val     _U_(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define   AC_COMPCTRL_MUXNEG_PIN3_Val     _U_(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
-#define   AC_COMPCTRL_MUXNEG_GND_Val      _U_(0x4)   /**< \brief (AC_COMPCTRL) Ground */
-#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   _U_(0x5)   /**< \brief (AC_COMPCTRL) VDD scaler */
-#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  _U_(0x6)   /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
-#define   AC_COMPCTRL_MUXNEG_DAC_Val      _U_(0x7)   /**< \brief (AC_COMPCTRL) DAC output */
-#define AC_COMPCTRL_MUXNEG_PIN0     (AC_COMPCTRL_MUXNEG_PIN0_Val   << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN1     (AC_COMPCTRL_MUXNEG_PIN1_Val   << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN2     (AC_COMPCTRL_MUXNEG_PIN2_Val   << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_PIN3     (AC_COMPCTRL_MUXNEG_PIN3_Val   << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_GND      (AC_COMPCTRL_MUXNEG_GND_Val    << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_VSCALE   (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_BANDGAP  (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXNEG_DAC      (AC_COMPCTRL_MUXNEG_DAC_Val    << AC_COMPCTRL_MUXNEG_Pos)
-#define AC_COMPCTRL_MUXPOS_Pos      12           /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
-#define AC_COMPCTRL_MUXPOS_Msk      (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS(value)   (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
-#define   AC_COMPCTRL_MUXPOS_PIN0_Val     _U_(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
-#define   AC_COMPCTRL_MUXPOS_PIN1_Val     _U_(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
-#define   AC_COMPCTRL_MUXPOS_PIN2_Val     _U_(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
-#define   AC_COMPCTRL_MUXPOS_PIN3_Val     _U_(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
-#define   AC_COMPCTRL_MUXPOS_VSCALE_Val   _U_(0x4)   /**< \brief (AC_COMPCTRL) VDD Scaler */
-#define AC_COMPCTRL_MUXPOS_PIN0     (AC_COMPCTRL_MUXPOS_PIN0_Val   << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN1     (AC_COMPCTRL_MUXPOS_PIN1_Val   << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN2     (AC_COMPCTRL_MUXPOS_PIN2_Val   << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_PIN3     (AC_COMPCTRL_MUXPOS_PIN3_Val   << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_MUXPOS_VSCALE   (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
-#define AC_COMPCTRL_SWAP_Pos        15           /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
-#define AC_COMPCTRL_SWAP            (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
-#define AC_COMPCTRL_SPEED_Pos       16           /**< \brief (AC_COMPCTRL) Speed Selection */
-#define AC_COMPCTRL_SPEED_Msk       (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
-#define AC_COMPCTRL_SPEED(value)    (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
-#define   AC_COMPCTRL_SPEED_HIGH_Val      _U_(0x3)   /**< \brief (AC_COMPCTRL) High speed */
-#define AC_COMPCTRL_SPEED_HIGH      (AC_COMPCTRL_SPEED_HIGH_Val    << AC_COMPCTRL_SPEED_Pos)
-#define AC_COMPCTRL_HYSTEN_Pos      19           /**< \brief (AC_COMPCTRL) Hysteresis Enable */
-#define AC_COMPCTRL_HYSTEN          (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
-#define AC_COMPCTRL_HYST_Pos        20           /**< \brief (AC_COMPCTRL) Hysteresis Level */
-#define AC_COMPCTRL_HYST_Msk        (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_HYST(value)     (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
-#define   AC_COMPCTRL_HYST_HYST50_Val     _U_(0x0)   /**< \brief (AC_COMPCTRL) 50mV */
-#define   AC_COMPCTRL_HYST_HYST100_Val    _U_(0x1)   /**< \brief (AC_COMPCTRL) 100mV */
-#define   AC_COMPCTRL_HYST_HYST150_Val    _U_(0x2)   /**< \brief (AC_COMPCTRL) 150mV */
-#define AC_COMPCTRL_HYST_HYST50     (AC_COMPCTRL_HYST_HYST50_Val   << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_HYST_HYST100    (AC_COMPCTRL_HYST_HYST100_Val  << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_HYST_HYST150    (AC_COMPCTRL_HYST_HYST150_Val  << AC_COMPCTRL_HYST_Pos)
-#define AC_COMPCTRL_FLEN_Pos        24           /**< \brief (AC_COMPCTRL) Filter Length */
-#define AC_COMPCTRL_FLEN_Msk        (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN(value)     (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
-#define   AC_COMPCTRL_FLEN_OFF_Val        _U_(0x0)   /**< \brief (AC_COMPCTRL) No filtering */
-#define   AC_COMPCTRL_FLEN_MAJ3_Val       _U_(0x1)   /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
-#define   AC_COMPCTRL_FLEN_MAJ5_Val       _U_(0x2)   /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
-#define AC_COMPCTRL_FLEN_OFF        (AC_COMPCTRL_FLEN_OFF_Val      << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN_MAJ3       (AC_COMPCTRL_FLEN_MAJ3_Val     << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_FLEN_MAJ5       (AC_COMPCTRL_FLEN_MAJ5_Val     << AC_COMPCTRL_FLEN_Pos)
-#define AC_COMPCTRL_OUT_Pos         28           /**< \brief (AC_COMPCTRL) Output */
-#define AC_COMPCTRL_OUT_Msk         (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT(value)      (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
-#define   AC_COMPCTRL_OUT_OFF_Val         _U_(0x0)   /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
-#define   AC_COMPCTRL_OUT_ASYNC_Val       _U_(0x1)   /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
-#define   AC_COMPCTRL_OUT_SYNC_Val        _U_(0x2)   /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
-#define AC_COMPCTRL_OUT_OFF         (AC_COMPCTRL_OUT_OFF_Val       << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT_ASYNC       (AC_COMPCTRL_OUT_ASYNC_Val     << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_OUT_SYNC        (AC_COMPCTRL_OUT_SYNC_Val      << AC_COMPCTRL_OUT_Pos)
-#define AC_COMPCTRL_MASK            _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
-
-/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
-    uint32_t WINCTRL:1;        /*!< bit:      2  WINCTRL Synchronization Busy       */
-    uint32_t COMPCTRL0:1;      /*!< bit:      3  COMPCTRL 0 Synchronization Busy    */
-    uint32_t COMPCTRL1:1;      /*!< bit:      4  COMPCTRL 1 Synchronization Busy    */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :3;               /*!< bit:  0.. 2  Reserved                           */
-    uint32_t COMPCTRL:2;       /*!< bit:  3.. 4  COMPCTRL x Synchronization Busy    */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} AC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_SYNCBUSY_OFFSET          0x20         /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
-#define AC_SYNCBUSY_RESETVALUE      _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define AC_SYNCBUSY_SWRST_Pos       0            /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
-#define AC_SYNCBUSY_SWRST           (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
-#define AC_SYNCBUSY_ENABLE_Pos      1            /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
-#define AC_SYNCBUSY_ENABLE          (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
-#define AC_SYNCBUSY_WINCTRL_Pos     2            /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
-#define AC_SYNCBUSY_WINCTRL         (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
-#define AC_SYNCBUSY_COMPCTRL0_Pos   3            /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
-#define AC_SYNCBUSY_COMPCTRL0       (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
-#define AC_SYNCBUSY_COMPCTRL1_Pos   4            /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
-#define AC_SYNCBUSY_COMPCTRL1       (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
-#define AC_SYNCBUSY_COMPCTRL_Pos    3            /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
-#define AC_SYNCBUSY_COMPCTRL_Msk    (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
-#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
-#define AC_SYNCBUSY_MASK            _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
-
-/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BIAS0:2;          /*!< bit:  0.. 1  COMP0/1 Bias Scaling               */
-    uint16_t :14;              /*!< bit:  2..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} AC_CALIB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AC_CALIB_OFFSET             0x24         /**< \brief (AC_CALIB offset) Calibration */
-#define AC_CALIB_RESETVALUE         _U_(0x0101)  /**< \brief (AC_CALIB reset_value) Calibration */
-
-#define AC_CALIB_BIAS0_Pos          0            /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */
-#define AC_CALIB_BIAS0_Msk          (_U_(0x3) << AC_CALIB_BIAS0_Pos)
-#define AC_CALIB_BIAS0(value)       (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
-#define AC_CALIB_MASK               _U_(0x0003)  /**< \brief (AC_CALIB) MASK Register */
-
-/** \brief AC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO AC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
-  __O  AC_CTRLB_Type             CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B */
-  __IO AC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x02 (R/W 16) Event Control */
-  __IO AC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
-  __IO AC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
-  __IO AC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
-  __I  AC_STATUSA_Type           STATUSA;     /**< \brief Offset: 0x07 (R/   8) Status A */
-  __I  AC_STATUSB_Type           STATUSB;     /**< \brief Offset: 0x08 (R/   8) Status B */
-  __IO AC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x09 (R/W  8) Debug Control */
-  __IO AC_WINCTRL_Type           WINCTRL;     /**< \brief Offset: 0x0A (R/W  8) Window Control */
-       RoReg8                    Reserved1[0x1];
-  __IO AC_SCALER_Type            SCALER[2];   /**< \brief Offset: 0x0C (R/W  8) Scaler n */
-       RoReg8                    Reserved2[0x2];
-  __IO AC_COMPCTRL_Type          COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
-       RoReg8                    Reserved3[0x8];
-  __I  AC_SYNCBUSY_Type          SYNCBUSY;    /**< \brief Offset: 0x20 (R/  32) Synchronization Busy */
-  __IO AC_CALIB_Type             CALIB;       /**< \brief Offset: 0x24 (R/W 16) Calibration */
-} Ac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_AC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h
deleted file mode 100644
index 33c38ae3f8..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/adc.h
+++ /dev/null
@@ -1,871 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for ADC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_ADC_COMPONENT_
-#define _SAMD51_ADC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR ADC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_ADC Analog Digital Converter */
-/*@{*/
-
-#define ADC_U2500
-#define REV_ADC                     0x100
-
-/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint16_t :1;               /*!< bit:      2  Reserved                           */
-    uint16_t DUALSEL:2;        /*!< bit:  3.. 4  Dual Mode Trigger Selection        */
-    uint16_t SLAVEEN:1;        /*!< bit:      5  Slave Enable                       */
-    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-    uint16_t PRESCALER:3;      /*!< bit:  8..10  Prescaler Configuration            */
-    uint16_t :4;               /*!< bit: 11..14  Reserved                           */
-    uint16_t R2R:1;            /*!< bit:     15  Rail to Rail Operation Enable      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CTRLA_OFFSET            0x00         /**< \brief (ADC_CTRLA offset) Control A */
-#define ADC_CTRLA_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_CTRLA reset_value) Control A */
-
-#define ADC_CTRLA_SWRST_Pos         0            /**< \brief (ADC_CTRLA) Software Reset */
-#define ADC_CTRLA_SWRST             (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
-#define ADC_CTRLA_ENABLE_Pos        1            /**< \brief (ADC_CTRLA) Enable */
-#define ADC_CTRLA_ENABLE            (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
-#define ADC_CTRLA_DUALSEL_Pos       3            /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */
-#define ADC_CTRLA_DUALSEL_Msk       (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)
-#define ADC_CTRLA_DUALSEL(value)    (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
-#define   ADC_CTRLA_DUALSEL_BOTH_Val      _U_(0x0)   /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
-#define   ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1)   /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
-#define ADC_CTRLA_DUALSEL_BOTH      (ADC_CTRLA_DUALSEL_BOTH_Val    << ADC_CTRLA_DUALSEL_Pos)
-#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)
-#define ADC_CTRLA_SLAVEEN_Pos       5            /**< \brief (ADC_CTRLA) Slave Enable */
-#define ADC_CTRLA_SLAVEEN           (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
-#define ADC_CTRLA_RUNSTDBY_Pos      6            /**< \brief (ADC_CTRLA) Run in Standby */
-#define ADC_CTRLA_RUNSTDBY          (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
-#define ADC_CTRLA_ONDEMAND_Pos      7            /**< \brief (ADC_CTRLA) On Demand Control */
-#define ADC_CTRLA_ONDEMAND          (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
-#define ADC_CTRLA_PRESCALER_Pos     8            /**< \brief (ADC_CTRLA) Prescaler Configuration */
-#define ADC_CTRLA_PRESCALER_Msk     (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER(value)  (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
-#define   ADC_CTRLA_PRESCALER_DIV2_Val    _U_(0x0)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */
-#define   ADC_CTRLA_PRESCALER_DIV4_Val    _U_(0x1)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */
-#define   ADC_CTRLA_PRESCALER_DIV8_Val    _U_(0x2)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */
-#define   ADC_CTRLA_PRESCALER_DIV16_Val   _U_(0x3)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */
-#define   ADC_CTRLA_PRESCALER_DIV32_Val   _U_(0x4)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */
-#define   ADC_CTRLA_PRESCALER_DIV64_Val   _U_(0x5)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */
-#define   ADC_CTRLA_PRESCALER_DIV128_Val  _U_(0x6)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */
-#define   ADC_CTRLA_PRESCALER_DIV256_Val  _U_(0x7)   /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */
-#define ADC_CTRLA_PRESCALER_DIV2    (ADC_CTRLA_PRESCALER_DIV2_Val  << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV4    (ADC_CTRLA_PRESCALER_DIV4_Val  << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV8    (ADC_CTRLA_PRESCALER_DIV8_Val  << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV16   (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV32   (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV64   (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV128  (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_PRESCALER_DIV256  (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)
-#define ADC_CTRLA_R2R_Pos           15           /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */
-#define ADC_CTRLA_R2R               (_U_(0x1) << ADC_CTRLA_R2R_Pos)
-#define ADC_CTRLA_MASK              _U_(0x87FB)  /**< \brief (ADC_CTRLA) MASK Register */
-
-/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W  8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FLUSHEI:1;        /*!< bit:      0  Flush Event Input Enable           */
-    uint8_t  STARTEI:1;        /*!< bit:      1  Start Conversion Event Input Enable */
-    uint8_t  FLUSHINV:1;       /*!< bit:      2  Flush Event Invert Enable          */
-    uint8_t  STARTINV:1;       /*!< bit:      3  Start Conversion Event Invert Enable */
-    uint8_t  RESRDYEO:1;       /*!< bit:      4  Result Ready Event Out             */
-    uint8_t  WINMONEO:1;       /*!< bit:      5  Window Monitor Event Out           */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_EVCTRL_OFFSET           0x02         /**< \brief (ADC_EVCTRL offset) Event Control */
-#define ADC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (ADC_EVCTRL reset_value) Event Control */
-
-#define ADC_EVCTRL_FLUSHEI_Pos      0            /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
-#define ADC_EVCTRL_FLUSHEI          (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
-#define ADC_EVCTRL_STARTEI_Pos      1            /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
-#define ADC_EVCTRL_STARTEI          (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
-#define ADC_EVCTRL_FLUSHINV_Pos     2            /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
-#define ADC_EVCTRL_FLUSHINV         (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
-#define ADC_EVCTRL_STARTINV_Pos     3            /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */
-#define ADC_EVCTRL_STARTINV         (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
-#define ADC_EVCTRL_RESRDYEO_Pos     4            /**< \brief (ADC_EVCTRL) Result Ready Event Out */
-#define ADC_EVCTRL_RESRDYEO         (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
-#define ADC_EVCTRL_WINMONEO_Pos     5            /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
-#define ADC_EVCTRL_WINMONEO         (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
-#define ADC_EVCTRL_MASK             _U_(0x3F)    /**< \brief (ADC_EVCTRL) MASK Register */
-
-/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DBGCTRL_OFFSET          0x03         /**< \brief (ADC_DBGCTRL offset) Debug Control */
-#define ADC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
-
-#define ADC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (ADC_DBGCTRL) Debug Run */
-#define ADC_DBGCTRL_DBGRUN          (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
-#define ADC_DBGCTRL_MASK            _U_(0x01)    /**< \brief (ADC_DBGCTRL) MASK Register */
-
-/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t MUXPOS:5;         /*!< bit:  0.. 4  Positive Mux Input Selection       */
-    uint16_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint16_t DIFFMODE:1;       /*!< bit:      7  Differential Mode                  */
-    uint16_t MUXNEG:5;         /*!< bit:  8..12  Negative Mux Input Selection       */
-    uint16_t :2;               /*!< bit: 13..14  Reserved                           */
-    uint16_t DSEQSTOP:1;       /*!< bit:     15  Stop DMA Sequencing                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_INPUTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INPUTCTRL_OFFSET        0x04         /**< \brief (ADC_INPUTCTRL offset) Input Control */
-#define ADC_INPUTCTRL_RESETVALUE    _U_(0x0000)  /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
-
-#define ADC_INPUTCTRL_MUXPOS_Pos    0            /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
-#define ADC_INPUTCTRL_MUXPOS_Msk    (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
-#define   ADC_INPUTCTRL_MUXPOS_AIN0_Val   _U_(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN1_Val   _U_(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN2_Val   _U_(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN3_Val   _U_(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN4_Val   _U_(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN5_Val   _U_(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN6_Val   _U_(0x6)   /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN7_Val   _U_(0x7)   /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN8_Val   _U_(0x8)   /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN9_Val   _U_(0x9)   /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN10_Val  _U_(0xA)   /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN11_Val  _U_(0xB)   /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN12_Val  _U_(0xC)   /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN13_Val  _U_(0xD)   /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN14_Val  _U_(0xE)   /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN15_Val  _U_(0xF)   /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN16_Val  _U_(0x10)   /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN17_Val  _U_(0x11)   /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN18_Val  _U_(0x12)   /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN19_Val  _U_(0x13)   /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN20_Val  _U_(0x14)   /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN21_Val  _U_(0x15)   /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN22_Val  _U_(0x16)   /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_AIN23_Val  _U_(0x17)   /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */
-#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18)   /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
-#define   ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19)   /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
-#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A)   /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
-#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B)   /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
-#define   ADC_INPUTCTRL_MUXPOS_PTAT_Val   _U_(0x1C)   /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
-#define   ADC_INPUTCTRL_MUXPOS_CTAT_Val   _U_(0x1D)   /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
-#define   ADC_INPUTCTRL_MUXPOS_DAC_Val    _U_(0x1E)   /**< \brief (ADC_INPUTCTRL) DAC Output */
-#define   ADC_INPUTCTRL_MUXPOS_PTC_Val    _U_(0x1F)   /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */
-#define ADC_INPUTCTRL_MUXPOS_AIN0   (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN1   (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN2   (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN3   (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN4   (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN5   (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN6   (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN7   (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN8   (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN9   (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN10  (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN11  (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN12  (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN13  (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN14  (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN15  (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN16  (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN17  (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN18  (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN19  (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN20  (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN21  (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN22  (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_AIN23  (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PTAT   (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_CTAT   (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_DAC    (ADC_INPUTCTRL_MUXPOS_DAC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_MUXPOS_PTC    (ADC_INPUTCTRL_MUXPOS_PTC_Val  << ADC_INPUTCTRL_MUXPOS_Pos)
-#define ADC_INPUTCTRL_DIFFMODE_Pos  7            /**< \brief (ADC_INPUTCTRL) Differential Mode */
-#define ADC_INPUTCTRL_DIFFMODE      (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)
-#define ADC_INPUTCTRL_MUXNEG_Pos    8            /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
-#define ADC_INPUTCTRL_MUXNEG_Msk    (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
-#define   ADC_INPUTCTRL_MUXNEG_AIN0_Val   _U_(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_AIN1_Val   _U_(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_AIN2_Val   _U_(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_AIN3_Val   _U_(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_AIN4_Val   _U_(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_AIN5_Val   _U_(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_AIN6_Val   _U_(0x6)   /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_AIN7_Val   _U_(0x7)   /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
-#define   ADC_INPUTCTRL_MUXNEG_GND_Val    _U_(0x18)   /**< \brief (ADC_INPUTCTRL) Internal Ground */
-#define ADC_INPUTCTRL_MUXNEG_AIN0   (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN1   (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN2   (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN3   (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN4   (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN5   (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN6   (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_AIN7   (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
-#define ADC_INPUTCTRL_DSEQSTOP_Pos  15           /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */
-#define ADC_INPUTCTRL_DSEQSTOP      (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)
-#define ADC_INPUTCTRL_MASK          _U_(0x9F9F)  /**< \brief (ADC_INPUTCTRL) MASK Register */
-
-/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t LEFTADJ:1;        /*!< bit:      0  Left-Adjusted Result               */
-    uint16_t FREERUN:1;        /*!< bit:      1  Free Running Mode                  */
-    uint16_t CORREN:1;         /*!< bit:      2  Digital Correction Logic Enable    */
-    uint16_t RESSEL:2;         /*!< bit:  3.. 4  Conversion Result Resolution       */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t WINMODE:3;        /*!< bit:  8..10  Window Monitor Mode                */
-    uint16_t WINSS:1;          /*!< bit:     11  Window Single Sample               */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CTRLB_OFFSET            0x06         /**< \brief (ADC_CTRLB offset) Control B */
-#define ADC_CTRLB_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_CTRLB reset_value) Control B */
-
-#define ADC_CTRLB_LEFTADJ_Pos       0            /**< \brief (ADC_CTRLB) Left-Adjusted Result */
-#define ADC_CTRLB_LEFTADJ           (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)
-#define ADC_CTRLB_FREERUN_Pos       1            /**< \brief (ADC_CTRLB) Free Running Mode */
-#define ADC_CTRLB_FREERUN           (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)
-#define ADC_CTRLB_CORREN_Pos        2            /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */
-#define ADC_CTRLB_CORREN            (_U_(0x1) << ADC_CTRLB_CORREN_Pos)
-#define ADC_CTRLB_RESSEL_Pos        3            /**< \brief (ADC_CTRLB) Conversion Result Resolution */
-#define ADC_CTRLB_RESSEL_Msk        (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL(value)     (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
-#define   ADC_CTRLB_RESSEL_12BIT_Val      _U_(0x0)   /**< \brief (ADC_CTRLB) 12-bit result */
-#define   ADC_CTRLB_RESSEL_16BIT_Val      _U_(0x1)   /**< \brief (ADC_CTRLB) For averaging mode output */
-#define   ADC_CTRLB_RESSEL_10BIT_Val      _U_(0x2)   /**< \brief (ADC_CTRLB) 10-bit result */
-#define   ADC_CTRLB_RESSEL_8BIT_Val       _U_(0x3)   /**< \brief (ADC_CTRLB) 8-bit result */
-#define ADC_CTRLB_RESSEL_12BIT      (ADC_CTRLB_RESSEL_12BIT_Val    << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_16BIT      (ADC_CTRLB_RESSEL_16BIT_Val    << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_10BIT      (ADC_CTRLB_RESSEL_10BIT_Val    << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_RESSEL_8BIT       (ADC_CTRLB_RESSEL_8BIT_Val     << ADC_CTRLB_RESSEL_Pos)
-#define ADC_CTRLB_WINMODE_Pos       8            /**< \brief (ADC_CTRLB) Window Monitor Mode */
-#define ADC_CTRLB_WINMODE_Msk       (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE(value)    (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
-#define   ADC_CTRLB_WINMODE_DISABLE_Val   _U_(0x0)   /**< \brief (ADC_CTRLB) No window mode (default) */
-#define   ADC_CTRLB_WINMODE_MODE1_Val     _U_(0x1)   /**< \brief (ADC_CTRLB) RESULT > WINLT */
-#define   ADC_CTRLB_WINMODE_MODE2_Val     _U_(0x2)   /**< \brief (ADC_CTRLB) RESULT < WINUT */
-#define   ADC_CTRLB_WINMODE_MODE3_Val     _U_(0x3)   /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */
-#define   ADC_CTRLB_WINMODE_MODE4_Val     _U_(0x4)   /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
-#define ADC_CTRLB_WINMODE_DISABLE   (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE1     (ADC_CTRLB_WINMODE_MODE1_Val   << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE2     (ADC_CTRLB_WINMODE_MODE2_Val   << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE3     (ADC_CTRLB_WINMODE_MODE3_Val   << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINMODE_MODE4     (ADC_CTRLB_WINMODE_MODE4_Val   << ADC_CTRLB_WINMODE_Pos)
-#define ADC_CTRLB_WINSS_Pos         11           /**< \brief (ADC_CTRLB) Window Single Sample */
-#define ADC_CTRLB_WINSS             (_U_(0x1) << ADC_CTRLB_WINSS_Pos)
-#define ADC_CTRLB_MASK              _U_(0x0F1F)  /**< \brief (ADC_CTRLB) MASK Register */
-
-/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W  8) Reference Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  REFSEL:4;         /*!< bit:  0.. 3  Reference Selection                */
-    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint8_t  REFCOMP:1;        /*!< bit:      7  Reference Buffer Offset Compensation Enable */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_REFCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_REFCTRL_OFFSET          0x08         /**< \brief (ADC_REFCTRL offset) Reference Control */
-#define ADC_REFCTRL_RESETVALUE      _U_(0x00)    /**< \brief (ADC_REFCTRL reset_value) Reference Control */
-
-#define ADC_REFCTRL_REFSEL_Pos      0            /**< \brief (ADC_REFCTRL) Reference Selection */
-#define ADC_REFCTRL_REFSEL_Msk      (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL(value)   (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
-#define   ADC_REFCTRL_REFSEL_INTREF_Val   _U_(0x0)   /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
-#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  _U_(0x2)   /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
-#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  _U_(0x3)   /**< \brief (ADC_REFCTRL) VDDANA */
-#define   ADC_REFCTRL_REFSEL_AREFA_Val    _U_(0x4)   /**< \brief (ADC_REFCTRL) External Reference */
-#define   ADC_REFCTRL_REFSEL_AREFB_Val    _U_(0x5)   /**< \brief (ADC_REFCTRL) External Reference */
-#define   ADC_REFCTRL_REFSEL_AREFC_Val    _U_(0x6)   /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */
-#define ADC_REFCTRL_REFSEL_INTREF   (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFSEL_AREFC    (ADC_REFCTRL_REFSEL_AREFC_Val  << ADC_REFCTRL_REFSEL_Pos)
-#define ADC_REFCTRL_REFCOMP_Pos     7            /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
-#define ADC_REFCTRL_REFCOMP         (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
-#define ADC_REFCTRL_MASK            _U_(0x8F)    /**< \brief (ADC_REFCTRL) MASK Register */
-
-/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W  8) Average Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SAMPLENUM:4;      /*!< bit:  0.. 3  Number of Samples to be Collected  */
-    uint8_t  ADJRES:3;         /*!< bit:  4.. 6  Adjusting Result / Division Coefficient */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_AVGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_AVGCTRL_OFFSET          0x0A         /**< \brief (ADC_AVGCTRL offset) Average Control */
-#define ADC_AVGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (ADC_AVGCTRL reset_value) Average Control */
-
-#define ADC_AVGCTRL_SAMPLENUM_Pos   0            /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
-#define ADC_AVGCTRL_SAMPLENUM_Msk   (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
-#define   ADC_AVGCTRL_SAMPLENUM_1_Val     _U_(0x0)   /**< \brief (ADC_AVGCTRL) 1 sample */
-#define   ADC_AVGCTRL_SAMPLENUM_2_Val     _U_(0x1)   /**< \brief (ADC_AVGCTRL) 2 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_4_Val     _U_(0x2)   /**< \brief (ADC_AVGCTRL) 4 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_8_Val     _U_(0x3)   /**< \brief (ADC_AVGCTRL) 8 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_16_Val    _U_(0x4)   /**< \brief (ADC_AVGCTRL) 16 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_32_Val    _U_(0x5)   /**< \brief (ADC_AVGCTRL) 32 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_64_Val    _U_(0x6)   /**< \brief (ADC_AVGCTRL) 64 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_128_Val   _U_(0x7)   /**< \brief (ADC_AVGCTRL) 128 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_256_Val   _U_(0x8)   /**< \brief (ADC_AVGCTRL) 256 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_512_Val   _U_(0x9)   /**< \brief (ADC_AVGCTRL) 512 samples */
-#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  _U_(0xA)   /**< \brief (ADC_AVGCTRL) 1024 samples */
-#define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_8     (ADC_AVGCTRL_SAMPLENUM_8_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_16    (ADC_AVGCTRL_SAMPLENUM_16_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_32    (ADC_AVGCTRL_SAMPLENUM_32_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_64    (ADC_AVGCTRL_SAMPLENUM_64_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_128   (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_256   (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
-#define ADC_AVGCTRL_ADJRES_Pos      4            /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
-#define ADC_AVGCTRL_ADJRES_Msk      (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
-#define ADC_AVGCTRL_ADJRES(value)   (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
-#define ADC_AVGCTRL_MASK            _U_(0x7F)    /**< \brief (ADC_AVGCTRL) MASK Register */
-
-/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W  8) Sample Time Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SAMPLEN:6;        /*!< bit:  0.. 5  Sampling Time Length               */
-    uint8_t  :1;               /*!< bit:      6  Reserved                           */
-    uint8_t  OFFCOMP:1;        /*!< bit:      7  Comparator Offset Compensation Enable */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_SAMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SAMPCTRL_OFFSET         0x0B         /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
-#define ADC_SAMPCTRL_RESETVALUE     _U_(0x00)    /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
-
-#define ADC_SAMPCTRL_SAMPLEN_Pos    0            /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
-#define ADC_SAMPCTRL_SAMPLEN_Msk    (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
-#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
-#define ADC_SAMPCTRL_OFFCOMP_Pos    7            /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
-#define ADC_SAMPCTRL_OFFCOMP        (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
-#define ADC_SAMPCTRL_MASK           _U_(0xBF)    /**< \brief (ADC_SAMPCTRL) MASK Register */
-
-/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t WINLT:16;         /*!< bit:  0..15  Window Lower Threshold             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_WINLT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_WINLT_OFFSET            0x0C         /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
-#define ADC_WINLT_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
-
-#define ADC_WINLT_WINLT_Pos         0            /**< \brief (ADC_WINLT) Window Lower Threshold */
-#define ADC_WINLT_WINLT_Msk         (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
-#define ADC_WINLT_WINLT(value)      (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
-#define ADC_WINLT_MASK              _U_(0xFFFF)  /**< \brief (ADC_WINLT) MASK Register */
-
-/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t WINUT:16;         /*!< bit:  0..15  Window Upper Threshold             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_WINUT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_WINUT_OFFSET            0x0E         /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
-#define ADC_WINUT_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
-
-#define ADC_WINUT_WINUT_Pos         0            /**< \brief (ADC_WINUT) Window Upper Threshold */
-#define ADC_WINUT_WINUT_Msk         (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
-#define ADC_WINUT_WINUT(value)      (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
-#define ADC_WINUT_MASK              _U_(0xFFFF)  /**< \brief (ADC_WINUT) MASK Register */
-
-/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t GAINCORR:12;      /*!< bit:  0..11  Gain Correction Value              */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_GAINCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_GAINCORR_OFFSET         0x10         /**< \brief (ADC_GAINCORR offset) Gain Correction */
-#define ADC_GAINCORR_RESETVALUE     _U_(0x0000)  /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
-
-#define ADC_GAINCORR_GAINCORR_Pos   0            /**< \brief (ADC_GAINCORR) Gain Correction Value */
-#define ADC_GAINCORR_GAINCORR_Msk   (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
-#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
-#define ADC_GAINCORR_MASK           _U_(0x0FFF)  /**< \brief (ADC_GAINCORR) MASK Register */
-
-/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t OFFSETCORR:12;    /*!< bit:  0..11  Offset Correction Value            */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_OFFSETCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_OFFSETCORR_OFFSET       0x12         /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
-#define ADC_OFFSETCORR_RESETVALUE   _U_(0x0000)  /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
-
-#define ADC_OFFSETCORR_OFFSETCORR_Pos 0            /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
-#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
-#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
-#define ADC_OFFSETCORR_MASK         _U_(0x0FFF)  /**< \brief (ADC_OFFSETCORR) MASK Register */
-
-/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W  8) Software Trigger -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FLUSH:1;          /*!< bit:      0  ADC Conversion Flush               */
-    uint8_t  START:1;          /*!< bit:      1  Start ADC Conversion               */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_SWTRIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SWTRIG_OFFSET           0x14         /**< \brief (ADC_SWTRIG offset) Software Trigger */
-#define ADC_SWTRIG_RESETVALUE       _U_(0x00)    /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
-
-#define ADC_SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
-#define ADC_SWTRIG_FLUSH            (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
-#define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) Start ADC Conversion */
-#define ADC_SWTRIG_START            (_U_(0x1) << ADC_SWTRIG_START_Pos)
-#define ADC_SWTRIG_MASK             _U_(0x03)    /**< \brief (ADC_SWTRIG) MASK Register */
-
-/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Disable     */
-    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Disable          */
-    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Disable   */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTENCLR_OFFSET         0x2C         /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
-#define ADC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define ADC_INTENCLR_RESRDY_Pos     0            /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
-#define ADC_INTENCLR_RESRDY         (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
-#define ADC_INTENCLR_OVERRUN_Pos    1            /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
-#define ADC_INTENCLR_OVERRUN        (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
-#define ADC_INTENCLR_WINMON_Pos     2            /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
-#define ADC_INTENCLR_WINMON         (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
-#define ADC_INTENCLR_MASK           _U_(0x07)    /**< \brief (ADC_INTENCLR) MASK Register */
-
-/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
-    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
-    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTENSET_OFFSET         0x2D         /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
-#define ADC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
-
-#define ADC_INTENSET_RESRDY_Pos     0            /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
-#define ADC_INTENSET_RESRDY         (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
-#define ADC_INTENSET_OVERRUN_Pos    1            /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
-#define ADC_INTENSET_OVERRUN        (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
-#define ADC_INTENSET_WINMON_Pos     2            /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
-#define ADC_INTENSET_WINMON         (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
-#define ADC_INTENSET_MASK           _U_(0x07)    /**< \brief (ADC_INTENSET) MASK Register */
-
-/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Flag        */
-    __I uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Flag             */
-    __I uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Flag      */
-    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_INTFLAG_OFFSET          0x2E         /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define ADC_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define ADC_INTFLAG_RESRDY_Pos      0            /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
-#define ADC_INTFLAG_RESRDY          (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
-#define ADC_INTFLAG_OVERRUN_Pos     1            /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
-#define ADC_INTFLAG_OVERRUN         (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
-#define ADC_INTFLAG_WINMON_Pos      2            /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
-#define ADC_INTFLAG_WINMON          (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
-#define ADC_INTFLAG_MASK            _U_(0x07)    /**< \brief (ADC_INTFLAG) MASK Register */
-
-/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/   8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ADCBUSY:1;        /*!< bit:      0  ADC Busy Status                    */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  WCC:6;            /*!< bit:  2.. 7  Window Comparator Counter          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} ADC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_STATUS_OFFSET           0x2F         /**< \brief (ADC_STATUS offset) Status */
-#define ADC_STATUS_RESETVALUE       _U_(0x00)    /**< \brief (ADC_STATUS reset_value) Status */
-
-#define ADC_STATUS_ADCBUSY_Pos      0            /**< \brief (ADC_STATUS) ADC Busy Status */
-#define ADC_STATUS_ADCBUSY          (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)
-#define ADC_STATUS_WCC_Pos          2            /**< \brief (ADC_STATUS) Window Comparator Counter */
-#define ADC_STATUS_WCC_Msk          (_U_(0x3F) << ADC_STATUS_WCC_Pos)
-#define ADC_STATUS_WCC(value)       (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
-#define ADC_STATUS_MASK             _U_(0xFD)    /**< \brief (ADC_STATUS) MASK Register */
-
-/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  SWRST Synchronization Busy         */
-    uint32_t ENABLE:1;         /*!< bit:      1  ENABLE Synchronization Busy        */
-    uint32_t INPUTCTRL:1;      /*!< bit:      2  Input Control Synchronization Busy */
-    uint32_t CTRLB:1;          /*!< bit:      3  Control B Synchronization Busy     */
-    uint32_t REFCTRL:1;        /*!< bit:      4  Reference Control Synchronization Busy */
-    uint32_t AVGCTRL:1;        /*!< bit:      5  Average Control Synchronization Busy */
-    uint32_t SAMPCTRL:1;       /*!< bit:      6  Sampling Time Control Synchronization Busy */
-    uint32_t WINLT:1;          /*!< bit:      7  Window Monitor Lower Threshold Synchronization Busy */
-    uint32_t WINUT:1;          /*!< bit:      8  Window Monitor Upper Threshold Synchronization Busy */
-    uint32_t GAINCORR:1;       /*!< bit:      9  Gain Correction Synchronization Busy */
-    uint32_t OFFSETCORR:1;     /*!< bit:     10  Offset Correction Synchronization Busy */
-    uint32_t SWTRIG:1;         /*!< bit:     11  Software Trigger Synchronization Busy */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ADC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_SYNCBUSY_OFFSET         0x30         /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
-#define ADC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define ADC_SYNCBUSY_SWRST_Pos      0            /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
-#define ADC_SYNCBUSY_SWRST          (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
-#define ADC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
-#define ADC_SYNCBUSY_ENABLE         (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
-#define ADC_SYNCBUSY_INPUTCTRL_Pos  2            /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */
-#define ADC_SYNCBUSY_INPUTCTRL      (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
-#define ADC_SYNCBUSY_CTRLB_Pos      3            /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */
-#define ADC_SYNCBUSY_CTRLB          (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)
-#define ADC_SYNCBUSY_REFCTRL_Pos    4            /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */
-#define ADC_SYNCBUSY_REFCTRL        (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)
-#define ADC_SYNCBUSY_AVGCTRL_Pos    5            /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */
-#define ADC_SYNCBUSY_AVGCTRL        (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
-#define ADC_SYNCBUSY_SAMPCTRL_Pos   6            /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */
-#define ADC_SYNCBUSY_SAMPCTRL       (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
-#define ADC_SYNCBUSY_WINLT_Pos      7            /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */
-#define ADC_SYNCBUSY_WINLT          (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
-#define ADC_SYNCBUSY_WINUT_Pos      8            /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */
-#define ADC_SYNCBUSY_WINUT          (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
-#define ADC_SYNCBUSY_GAINCORR_Pos   9            /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */
-#define ADC_SYNCBUSY_GAINCORR       (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
-#define ADC_SYNCBUSY_OFFSETCORR_Pos 10           /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */
-#define ADC_SYNCBUSY_OFFSETCORR     (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
-#define ADC_SYNCBUSY_SWTRIG_Pos     11           /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */
-#define ADC_SYNCBUSY_SWTRIG         (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
-#define ADC_SYNCBUSY_MASK           _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */
-
-/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  DMA Sequential Data                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ADC_DSEQDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DSEQDATA_OFFSET         0x34         /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */
-#define ADC_DSEQDATA_RESETVALUE     _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */
-
-#define ADC_DSEQDATA_DATA_Pos       0            /**< \brief (ADC_DSEQDATA) DMA Sequential Data */
-#define ADC_DSEQDATA_DATA_Msk       (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)
-#define ADC_DSEQDATA_DATA(value)    (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
-#define ADC_DSEQDATA_MASK           _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */
-
-/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t INPUTCTRL:1;      /*!< bit:      0  Input Control                      */
-    uint32_t CTRLB:1;          /*!< bit:      1  Control B                          */
-    uint32_t REFCTRL:1;        /*!< bit:      2  Reference Control                  */
-    uint32_t AVGCTRL:1;        /*!< bit:      3  Average Control                    */
-    uint32_t SAMPCTRL:1;       /*!< bit:      4  Sampling Time Control              */
-    uint32_t WINLT:1;          /*!< bit:      5  Window Monitor Lower Threshold     */
-    uint32_t WINUT:1;          /*!< bit:      6  Window Monitor Upper Threshold     */
-    uint32_t GAINCORR:1;       /*!< bit:      7  Gain Correction                    */
-    uint32_t OFFSETCORR:1;     /*!< bit:      8  Offset Correction                  */
-    uint32_t :22;              /*!< bit:  9..30  Reserved                           */
-    uint32_t AUTOSTART:1;      /*!< bit:     31  ADC Auto-Start Conversion          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ADC_DSEQCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DSEQCTRL_OFFSET         0x38         /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */
-#define ADC_DSEQCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */
-
-#define ADC_DSEQCTRL_INPUTCTRL_Pos  0            /**< \brief (ADC_DSEQCTRL) Input Control */
-#define ADC_DSEQCTRL_INPUTCTRL      (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)
-#define ADC_DSEQCTRL_CTRLB_Pos      1            /**< \brief (ADC_DSEQCTRL) Control B */
-#define ADC_DSEQCTRL_CTRLB          (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)
-#define ADC_DSEQCTRL_REFCTRL_Pos    2            /**< \brief (ADC_DSEQCTRL) Reference Control */
-#define ADC_DSEQCTRL_REFCTRL        (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)
-#define ADC_DSEQCTRL_AVGCTRL_Pos    3            /**< \brief (ADC_DSEQCTRL) Average Control */
-#define ADC_DSEQCTRL_AVGCTRL        (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)
-#define ADC_DSEQCTRL_SAMPCTRL_Pos   4            /**< \brief (ADC_DSEQCTRL) Sampling Time Control */
-#define ADC_DSEQCTRL_SAMPCTRL       (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)
-#define ADC_DSEQCTRL_WINLT_Pos      5            /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */
-#define ADC_DSEQCTRL_WINLT          (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)
-#define ADC_DSEQCTRL_WINUT_Pos      6            /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */
-#define ADC_DSEQCTRL_WINUT          (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)
-#define ADC_DSEQCTRL_GAINCORR_Pos   7            /**< \brief (ADC_DSEQCTRL) Gain Correction */
-#define ADC_DSEQCTRL_GAINCORR       (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)
-#define ADC_DSEQCTRL_OFFSETCORR_Pos 8            /**< \brief (ADC_DSEQCTRL) Offset Correction */
-#define ADC_DSEQCTRL_OFFSETCORR     (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)
-#define ADC_DSEQCTRL_AUTOSTART_Pos  31           /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */
-#define ADC_DSEQCTRL_AUTOSTART      (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)
-#define ADC_DSEQCTRL_MASK           _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */
-
-/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/  32) DMA Sequencial Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t INPUTCTRL:1;      /*!< bit:      0  Input Control                      */
-    uint32_t CTRLB:1;          /*!< bit:      1  Control B                          */
-    uint32_t REFCTRL:1;        /*!< bit:      2  Reference Control                  */
-    uint32_t AVGCTRL:1;        /*!< bit:      3  Average Control                    */
-    uint32_t SAMPCTRL:1;       /*!< bit:      4  Sampling Time Control              */
-    uint32_t WINLT:1;          /*!< bit:      5  Window Monitor Lower Threshold     */
-    uint32_t WINUT:1;          /*!< bit:      6  Window Monitor Upper Threshold     */
-    uint32_t GAINCORR:1;       /*!< bit:      7  Gain Correction                    */
-    uint32_t OFFSETCORR:1;     /*!< bit:      8  Offset Correction                  */
-    uint32_t :22;              /*!< bit:  9..30  Reserved                           */
-    uint32_t BUSY:1;           /*!< bit:     31  DMA Sequencing Busy                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ADC_DSEQSTAT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_DSEQSTAT_OFFSET         0x3C         /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */
-#define ADC_DSEQSTAT_RESETVALUE     _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */
-
-#define ADC_DSEQSTAT_INPUTCTRL_Pos  0            /**< \brief (ADC_DSEQSTAT) Input Control */
-#define ADC_DSEQSTAT_INPUTCTRL      (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)
-#define ADC_DSEQSTAT_CTRLB_Pos      1            /**< \brief (ADC_DSEQSTAT) Control B */
-#define ADC_DSEQSTAT_CTRLB          (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)
-#define ADC_DSEQSTAT_REFCTRL_Pos    2            /**< \brief (ADC_DSEQSTAT) Reference Control */
-#define ADC_DSEQSTAT_REFCTRL        (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)
-#define ADC_DSEQSTAT_AVGCTRL_Pos    3            /**< \brief (ADC_DSEQSTAT) Average Control */
-#define ADC_DSEQSTAT_AVGCTRL        (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)
-#define ADC_DSEQSTAT_SAMPCTRL_Pos   4            /**< \brief (ADC_DSEQSTAT) Sampling Time Control */
-#define ADC_DSEQSTAT_SAMPCTRL       (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)
-#define ADC_DSEQSTAT_WINLT_Pos      5            /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */
-#define ADC_DSEQSTAT_WINLT          (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)
-#define ADC_DSEQSTAT_WINUT_Pos      6            /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */
-#define ADC_DSEQSTAT_WINUT          (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)
-#define ADC_DSEQSTAT_GAINCORR_Pos   7            /**< \brief (ADC_DSEQSTAT) Gain Correction */
-#define ADC_DSEQSTAT_GAINCORR       (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)
-#define ADC_DSEQSTAT_OFFSETCORR_Pos 8            /**< \brief (ADC_DSEQSTAT) Offset Correction */
-#define ADC_DSEQSTAT_OFFSETCORR     (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)
-#define ADC_DSEQSTAT_BUSY_Pos       31           /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */
-#define ADC_DSEQSTAT_BUSY           (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)
-#define ADC_DSEQSTAT_MASK           _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */
-
-/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/  16) Result Conversion Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t RESULT:16;        /*!< bit:  0..15  Result Conversion Value            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_RESULT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_RESULT_OFFSET           0x40         /**< \brief (ADC_RESULT offset) Result Conversion Value */
-#define ADC_RESULT_RESETVALUE       _U_(0x0000)  /**< \brief (ADC_RESULT reset_value) Result Conversion Value */
-
-#define ADC_RESULT_RESULT_Pos       0            /**< \brief (ADC_RESULT) Result Conversion Value */
-#define ADC_RESULT_RESULT_Msk       (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
-#define ADC_RESULT_RESULT(value)    (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
-#define ADC_RESULT_MASK             _U_(0xFFFF)  /**< \brief (ADC_RESULT) MASK Register */
-
-/* -------- ADC_RESS : (ADC Offset: 0x44) (R/  16) Last Sample Result -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t RESS:16;          /*!< bit:  0..15  Last ADC conversion result         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_RESS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_RESS_OFFSET             0x44         /**< \brief (ADC_RESS offset) Last Sample Result */
-#define ADC_RESS_RESETVALUE         _U_(0x0000)  /**< \brief (ADC_RESS reset_value) Last Sample Result */
-
-#define ADC_RESS_RESS_Pos           0            /**< \brief (ADC_RESS) Last ADC conversion result */
-#define ADC_RESS_RESS_Msk           (_U_(0xFFFF) << ADC_RESS_RESS_Pos)
-#define ADC_RESS_RESS(value)        (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
-#define ADC_RESS_MASK               _U_(0xFFFF)  /**< \brief (ADC_RESS) MASK Register */
-
-/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BIASCOMP:3;       /*!< bit:  0.. 2  Bias Comparator Scaling            */
-    uint16_t :1;               /*!< bit:      3  Reserved                           */
-    uint16_t BIASR2R:3;        /*!< bit:  4.. 6  Bias R2R Ampli scaling             */
-    uint16_t :1;               /*!< bit:      7  Reserved                           */
-    uint16_t BIASREFBUF:3;     /*!< bit:  8..10  Bias  Reference Buffer Scaling     */
-    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} ADC_CALIB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ADC_CALIB_OFFSET            0x48         /**< \brief (ADC_CALIB offset) Calibration */
-#define ADC_CALIB_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_CALIB reset_value) Calibration */
-
-#define ADC_CALIB_BIASCOMP_Pos      0            /**< \brief (ADC_CALIB) Bias Comparator Scaling */
-#define ADC_CALIB_BIASCOMP_Msk      (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
-#define ADC_CALIB_BIASCOMP(value)   (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
-#define ADC_CALIB_BIASR2R_Pos       4            /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */
-#define ADC_CALIB_BIASR2R_Msk       (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)
-#define ADC_CALIB_BIASR2R(value)    (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
-#define ADC_CALIB_BIASREFBUF_Pos    8            /**< \brief (ADC_CALIB) Bias  Reference Buffer Scaling */
-#define ADC_CALIB_BIASREFBUF_Msk    (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
-#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
-#define ADC_CALIB_MASK              _U_(0x0777)  /**< \brief (ADC_CALIB) MASK Register */
-
-/** \brief ADC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO ADC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
-  __IO ADC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x02 (R/W  8) Event Control */
-  __IO ADC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x03 (R/W  8) Debug Control */
-  __IO ADC_INPUTCTRL_Type        INPUTCTRL;   /**< \brief Offset: 0x04 (R/W 16) Input Control */
-  __IO ADC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x06 (R/W 16) Control B */
-  __IO ADC_REFCTRL_Type          REFCTRL;     /**< \brief Offset: 0x08 (R/W  8) Reference Control */
-       RoReg8                    Reserved1[0x1];
-  __IO ADC_AVGCTRL_Type          AVGCTRL;     /**< \brief Offset: 0x0A (R/W  8) Average Control */
-  __IO ADC_SAMPCTRL_Type         SAMPCTRL;    /**< \brief Offset: 0x0B (R/W  8) Sample Time Control */
-  __IO ADC_WINLT_Type            WINLT;       /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
-  __IO ADC_WINUT_Type            WINUT;       /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
-  __IO ADC_GAINCORR_Type         GAINCORR;    /**< \brief Offset: 0x10 (R/W 16) Gain Correction */
-  __IO ADC_OFFSETCORR_Type       OFFSETCORR;  /**< \brief Offset: 0x12 (R/W 16) Offset Correction */
-  __IO ADC_SWTRIG_Type           SWTRIG;      /**< \brief Offset: 0x14 (R/W  8) Software Trigger */
-       RoReg8                    Reserved2[0x17];
-  __IO ADC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x2C (R/W  8) Interrupt Enable Clear */
-  __IO ADC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x2D (R/W  8) Interrupt Enable Set */
-  __IO ADC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2E (R/W  8) Interrupt Flag Status and Clear */
-  __I  ADC_STATUS_Type           STATUS;      /**< \brief Offset: 0x2F (R/   8) Status */
-  __I  ADC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x30 (R/  32) Synchronization Busy */
-  __O  ADC_DSEQDATA_Type         DSEQDATA;    /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */
-  __IO ADC_DSEQCTRL_Type         DSEQCTRL;    /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */
-  __I  ADC_DSEQSTAT_Type         DSEQSTAT;    /**< \brief Offset: 0x3C (R/  32) DMA Sequencial Status */
-  __I  ADC_RESULT_Type           RESULT;      /**< \brief Offset: 0x40 (R/  16) Result Conversion Value */
-       RoReg8                    Reserved3[0x2];
-  __I  ADC_RESS_Type             RESS;        /**< \brief Offset: 0x44 (R/  16) Last Sample Result */
-       RoReg8                    Reserved4[0x2];
-  __IO ADC_CALIB_Type            CALIB;       /**< \brief Offset: 0x48 (R/W 16) Calibration */
-} Adc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_ADC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h
deleted file mode 100644
index 5a74eac28b..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/aes.h
+++ /dev/null
@@ -1,375 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for AES
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_AES_COMPONENT_
-#define _SAMD51_AES_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR AES */
-/* ========================================================================== */
-/** \addtogroup SAMD51_AES Advanced Encryption Standard */
-/*@{*/
-
-#define AES_U2238
-#define REV_AES                     0x220
-
-/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t AESMODE:3;        /*!< bit:  2.. 4  AES Modes of operation             */
-    uint32_t CFBS:3;           /*!< bit:  5.. 7  Cipher Feedback Block Size         */
-    uint32_t KEYSIZE:2;        /*!< bit:  8.. 9  Encryption Key Size                */
-    uint32_t CIPHER:1;         /*!< bit:     10  Cipher Mode                        */
-    uint32_t STARTMODE:1;      /*!< bit:     11  Start Mode Select                  */
-    uint32_t LOD:1;            /*!< bit:     12  Last Output Data Mode              */
-    uint32_t KEYGEN:1;         /*!< bit:     13  Last Key Generation                */
-    uint32_t XORKEY:1;         /*!< bit:     14  XOR Key Operation                  */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t CTYPE:4;          /*!< bit: 16..19  Counter Measure Type               */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} AES_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_CTRLA_OFFSET            0x00         /**< \brief (AES_CTRLA offset) Control A */
-#define AES_CTRLA_RESETVALUE        _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
-
-#define AES_CTRLA_SWRST_Pos         0            /**< \brief (AES_CTRLA) Software Reset */
-#define AES_CTRLA_SWRST             (_U_(0x1) << AES_CTRLA_SWRST_Pos)
-#define AES_CTRLA_ENABLE_Pos        1            /**< \brief (AES_CTRLA) Enable */
-#define AES_CTRLA_ENABLE            (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
-#define AES_CTRLA_AESMODE_Pos       2            /**< \brief (AES_CTRLA) AES Modes of operation */
-#define AES_CTRLA_AESMODE_Msk       (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE(value)    (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
-#define   AES_CTRLA_AESMODE_ECB_Val       _U_(0x0)   /**< \brief (AES_CTRLA) Electronic code book mode */
-#define   AES_CTRLA_AESMODE_CBC_Val       _U_(0x1)   /**< \brief (AES_CTRLA) Cipher block chaining mode */
-#define   AES_CTRLA_AESMODE_OFB_Val       _U_(0x2)   /**< \brief (AES_CTRLA) Output feedback mode */
-#define   AES_CTRLA_AESMODE_CFB_Val       _U_(0x3)   /**< \brief (AES_CTRLA) Cipher feedback mode */
-#define   AES_CTRLA_AESMODE_COUNTER_Val   _U_(0x4)   /**< \brief (AES_CTRLA) Counter mode */
-#define   AES_CTRLA_AESMODE_CCM_Val       _U_(0x5)   /**< \brief (AES_CTRLA) CCM mode */
-#define   AES_CTRLA_AESMODE_GCM_Val       _U_(0x6)   /**< \brief (AES_CTRLA) Galois counter mode */
-#define AES_CTRLA_AESMODE_ECB       (AES_CTRLA_AESMODE_ECB_Val     << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_CBC       (AES_CTRLA_AESMODE_CBC_Val     << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_OFB       (AES_CTRLA_AESMODE_OFB_Val     << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_CFB       (AES_CTRLA_AESMODE_CFB_Val     << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_COUNTER   (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_CCM       (AES_CTRLA_AESMODE_CCM_Val     << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_AESMODE_GCM       (AES_CTRLA_AESMODE_GCM_Val     << AES_CTRLA_AESMODE_Pos)
-#define AES_CTRLA_CFBS_Pos          5            /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
-#define AES_CTRLA_CFBS_Msk          (_U_(0x7) << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS(value)       (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
-#define   AES_CTRLA_CFBS_128BIT_Val       _U_(0x0)   /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define   AES_CTRLA_CFBS_64BIT_Val        _U_(0x1)   /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define   AES_CTRLA_CFBS_32BIT_Val        _U_(0x2)   /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define   AES_CTRLA_CFBS_16BIT_Val        _U_(0x3)   /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define   AES_CTRLA_CFBS_8BIT_Val         _U_(0x4)   /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
-#define AES_CTRLA_CFBS_128BIT       (AES_CTRLA_CFBS_128BIT_Val     << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_64BIT        (AES_CTRLA_CFBS_64BIT_Val      << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_32BIT        (AES_CTRLA_CFBS_32BIT_Val      << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_16BIT        (AES_CTRLA_CFBS_16BIT_Val      << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_CFBS_8BIT         (AES_CTRLA_CFBS_8BIT_Val       << AES_CTRLA_CFBS_Pos)
-#define AES_CTRLA_KEYSIZE_Pos       8            /**< \brief (AES_CTRLA) Encryption Key Size */
-#define AES_CTRLA_KEYSIZE_Msk       (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_KEYSIZE(value)    (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
-#define   AES_CTRLA_KEYSIZE_128BIT_Val    _U_(0x0)   /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
-#define   AES_CTRLA_KEYSIZE_192BIT_Val    _U_(0x1)   /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
-#define   AES_CTRLA_KEYSIZE_256BIT_Val    _U_(0x2)   /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
-#define AES_CTRLA_KEYSIZE_128BIT    (AES_CTRLA_KEYSIZE_128BIT_Val  << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_KEYSIZE_192BIT    (AES_CTRLA_KEYSIZE_192BIT_Val  << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_KEYSIZE_256BIT    (AES_CTRLA_KEYSIZE_256BIT_Val  << AES_CTRLA_KEYSIZE_Pos)
-#define AES_CTRLA_CIPHER_Pos        10           /**< \brief (AES_CTRLA) Cipher Mode */
-#define AES_CTRLA_CIPHER            (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
-#define   AES_CTRLA_CIPHER_DEC_Val        _U_(0x0)   /**< \brief (AES_CTRLA) Decryption */
-#define   AES_CTRLA_CIPHER_ENC_Val        _U_(0x1)   /**< \brief (AES_CTRLA) Encryption */
-#define AES_CTRLA_CIPHER_DEC        (AES_CTRLA_CIPHER_DEC_Val      << AES_CTRLA_CIPHER_Pos)
-#define AES_CTRLA_CIPHER_ENC        (AES_CTRLA_CIPHER_ENC_Val      << AES_CTRLA_CIPHER_Pos)
-#define AES_CTRLA_STARTMODE_Pos     11           /**< \brief (AES_CTRLA) Start Mode Select */
-#define AES_CTRLA_STARTMODE         (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
-#define   AES_CTRLA_STARTMODE_MANUAL_Val  _U_(0x0)   /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
-#define   AES_CTRLA_STARTMODE_AUTO_Val    _U_(0x1)   /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
-#define AES_CTRLA_STARTMODE_MANUAL  (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
-#define AES_CTRLA_STARTMODE_AUTO    (AES_CTRLA_STARTMODE_AUTO_Val  << AES_CTRLA_STARTMODE_Pos)
-#define AES_CTRLA_LOD_Pos           12           /**< \brief (AES_CTRLA) Last Output Data Mode */
-#define AES_CTRLA_LOD               (_U_(0x1) << AES_CTRLA_LOD_Pos)
-#define   AES_CTRLA_LOD_NONE_Val          _U_(0x0)   /**< \brief (AES_CTRLA) No effect */
-#define   AES_CTRLA_LOD_LAST_Val          _U_(0x1)   /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
-#define AES_CTRLA_LOD_NONE          (AES_CTRLA_LOD_NONE_Val        << AES_CTRLA_LOD_Pos)
-#define AES_CTRLA_LOD_LAST          (AES_CTRLA_LOD_LAST_Val        << AES_CTRLA_LOD_Pos)
-#define AES_CTRLA_KEYGEN_Pos        13           /**< \brief (AES_CTRLA) Last Key Generation */
-#define AES_CTRLA_KEYGEN            (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
-#define   AES_CTRLA_KEYGEN_NONE_Val       _U_(0x0)   /**< \brief (AES_CTRLA) No effect */
-#define   AES_CTRLA_KEYGEN_LAST_Val       _U_(0x1)   /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
-#define AES_CTRLA_KEYGEN_NONE       (AES_CTRLA_KEYGEN_NONE_Val     << AES_CTRLA_KEYGEN_Pos)
-#define AES_CTRLA_KEYGEN_LAST       (AES_CTRLA_KEYGEN_LAST_Val     << AES_CTRLA_KEYGEN_Pos)
-#define AES_CTRLA_XORKEY_Pos        14           /**< \brief (AES_CTRLA) XOR Key Operation */
-#define AES_CTRLA_XORKEY            (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
-#define   AES_CTRLA_XORKEY_NONE_Val       _U_(0x0)   /**< \brief (AES_CTRLA) No effect */
-#define   AES_CTRLA_XORKEY_XOR_Val        _U_(0x1)   /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
-#define AES_CTRLA_XORKEY_NONE       (AES_CTRLA_XORKEY_NONE_Val     << AES_CTRLA_XORKEY_Pos)
-#define AES_CTRLA_XORKEY_XOR        (AES_CTRLA_XORKEY_XOR_Val      << AES_CTRLA_XORKEY_Pos)
-#define AES_CTRLA_CTYPE_Pos         16           /**< \brief (AES_CTRLA) Counter Measure Type */
-#define AES_CTRLA_CTYPE_Msk         (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
-#define AES_CTRLA_CTYPE(value)      (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
-#define AES_CTRLA_MASK              _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
-
-/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W  8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  START:1;          /*!< bit:      0  Start Encryption/Decryption        */
-    uint8_t  NEWMSG:1;         /*!< bit:      1  New message                        */
-    uint8_t  EOM:1;            /*!< bit:      2  End of message                     */
-    uint8_t  GFMUL:1;          /*!< bit:      3  GF Multiplication                  */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AES_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_CTRLB_OFFSET            0x04         /**< \brief (AES_CTRLB offset) Control B */
-#define AES_CTRLB_RESETVALUE        _U_(0x00)    /**< \brief (AES_CTRLB reset_value) Control B */
-
-#define AES_CTRLB_START_Pos         0            /**< \brief (AES_CTRLB) Start Encryption/Decryption */
-#define AES_CTRLB_START             (_U_(0x1) << AES_CTRLB_START_Pos)
-#define AES_CTRLB_NEWMSG_Pos        1            /**< \brief (AES_CTRLB) New message */
-#define AES_CTRLB_NEWMSG            (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
-#define AES_CTRLB_EOM_Pos           2            /**< \brief (AES_CTRLB) End of message */
-#define AES_CTRLB_EOM               (_U_(0x1) << AES_CTRLB_EOM_Pos)
-#define AES_CTRLB_GFMUL_Pos         3            /**< \brief (AES_CTRLB) GF Multiplication */
-#define AES_CTRLB_GFMUL             (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
-#define AES_CTRLB_MASK              _U_(0x0F)    /**< \brief (AES_CTRLB) MASK Register */
-
-/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete Interrupt Enable */
-    uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete Interrupt Enable */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AES_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTENCLR_OFFSET         0x05         /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
-#define AES_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define AES_INTENCLR_ENCCMP_Pos     0            /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
-#define AES_INTENCLR_ENCCMP         (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
-#define AES_INTENCLR_GFMCMP_Pos     1            /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
-#define AES_INTENCLR_GFMCMP         (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
-#define AES_INTENCLR_MASK           _U_(0x03)    /**< \brief (AES_INTENCLR) MASK Register */
-
-/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete Interrupt Enable */
-    uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete Interrupt Enable */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AES_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTENSET_OFFSET         0x06         /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
-#define AES_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
-
-#define AES_INTENSET_ENCCMP_Pos     0            /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
-#define AES_INTENSET_ENCCMP         (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
-#define AES_INTENSET_GFMCMP_Pos     1            /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
-#define AES_INTENSET_GFMCMP         (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
-#define AES_INTENSET_MASK           _U_(0x03)    /**< \brief (AES_INTENSET) MASK Register */
-
-/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W  8) Interrupt Flag Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete                */
-    __I uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete         */
-    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AES_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTFLAG_OFFSET          0x07         /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
-#define AES_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
-
-#define AES_INTFLAG_ENCCMP_Pos      0            /**< \brief (AES_INTFLAG) Encryption Complete */
-#define AES_INTFLAG_ENCCMP          (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
-#define AES_INTFLAG_GFMCMP_Pos      1            /**< \brief (AES_INTFLAG) GF Multiplication Complete */
-#define AES_INTFLAG_GFMCMP          (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
-#define AES_INTFLAG_MASK            _U_(0x03)    /**< \brief (AES_INTFLAG) MASK Register */
-
-/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W  8) Data buffer pointer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  INDATAPTR:2;      /*!< bit:  0.. 1  Input Data Pointer                 */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AES_DATABUFPTR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_DATABUFPTR_OFFSET       0x08         /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
-#define AES_DATABUFPTR_RESETVALUE   _U_(0x00)    /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
-
-#define AES_DATABUFPTR_INDATAPTR_Pos 0            /**< \brief (AES_DATABUFPTR) Input Data Pointer */
-#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
-#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
-#define AES_DATABUFPTR_MASK         _U_(0x03)    /**< \brief (AES_DATABUFPTR) MASK Register */
-
-/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W  8) Debug control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} AES_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_DBGCTRL_OFFSET          0x09         /**< \brief (AES_DBGCTRL offset) Debug control */
-#define AES_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (AES_DBGCTRL reset_value) Debug control */
-
-#define AES_DBGCTRL_DBGRUN_Pos      0            /**< \brief (AES_DBGCTRL) Debug Run */
-#define AES_DBGCTRL_DBGRUN          (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
-#define AES_DBGCTRL_MASK            _U_(0x01)    /**< \brief (AES_DBGCTRL) MASK Register */
-
-/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} AES_KEYWORD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_KEYWORD_OFFSET          0x0C         /**< \brief (AES_KEYWORD offset) Keyword n */
-#define AES_KEYWORD_RESETVALUE      _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
-#define AES_KEYWORD_MASK            _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
-
-/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} AES_INDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INDATA_OFFSET           0x38         /**< \brief (AES_INDATA offset) Indata */
-#define AES_INDATA_RESETVALUE       _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
-#define AES_INDATA_MASK             _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
-
-/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} AES_INTVECTV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_INTVECTV_OFFSET         0x3C         /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
-#define AES_INTVECTV_RESETVALUE     _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
-#define AES_INTVECTV_MASK           _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
-
-/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} AES_HASHKEY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_HASHKEY_OFFSET          0x5C         /**< \brief (AES_HASHKEY offset) Hash key n */
-#define AES_HASHKEY_RESETVALUE      _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
-#define AES_HASHKEY_MASK            _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
-
-/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} AES_GHASH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_GHASH_OFFSET            0x6C         /**< \brief (AES_GHASH offset) Galois Hash n */
-#define AES_GHASH_RESETVALUE        _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
-#define AES_GHASH_MASK              _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
-
-/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} AES_CIPLEN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_CIPLEN_OFFSET           0x80         /**< \brief (AES_CIPLEN offset) Cipher Length */
-#define AES_CIPLEN_RESETVALUE       _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
-#define AES_CIPLEN_MASK             _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
-
-/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} AES_RANDSEED_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define AES_RANDSEED_OFFSET         0x84         /**< \brief (AES_RANDSEED offset) Random Seed */
-#define AES_RANDSEED_RESETVALUE     _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
-#define AES_RANDSEED_MASK           _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
-
-/** \brief AES hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO AES_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO AES_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x04 (R/W  8) Control B */
-  __IO AES_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Clear */
-  __IO AES_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x06 (R/W  8) Interrupt Enable Set */
-  __IO AES_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x07 (R/W  8) Interrupt Flag Status */
-  __IO AES_DATABUFPTR_Type       DATABUFPTR;  /**< \brief Offset: 0x08 (R/W  8) Data buffer pointer */
-  __IO AES_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x09 (R/W  8) Debug control */
-       RoReg8                    Reserved1[0x2];
-  __O  AES_KEYWORD_Type          KEYWORD[8];  /**< \brief Offset: 0x0C ( /W 32) Keyword n */
-       RoReg8                    Reserved2[0xC];
-  __IO AES_INDATA_Type           INDATA;      /**< \brief Offset: 0x38 (R/W 32) Indata */
-  __O  AES_INTVECTV_Type         INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
-       RoReg8                    Reserved3[0x10];
-  __IO AES_HASHKEY_Type          HASHKEY[4];  /**< \brief Offset: 0x5C (R/W 32) Hash key n */
-  __IO AES_GHASH_Type            GHASH[4];    /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
-       RoReg8                    Reserved4[0x4];
-  __IO AES_CIPLEN_Type           CIPLEN;      /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
-  __IO AES_RANDSEED_Type         RANDSEED;    /**< \brief Offset: 0x84 (R/W 32) Random Seed */
-} Aes;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_AES_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h
deleted file mode 100644
index 9d6754998c..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/can.h
+++ /dev/null
@@ -1,3207 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for CAN
- *
- * Copyright (c) 2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- *    Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CAN_COMPONENT_
-#define _SAMD51_CAN_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR CAN */
-/* ========================================================================== */
-/** \addtogroup SAMD51_CAN Control Area Network */
-/*@{*/
-
-#define CAN_U2003
-#define REV_CAN                     0x321
-
-/* -------- CAN_CREL : (CAN Offset: 0x00) (R/  32) Core Release -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :20;              /*!< bit:  0..19  Reserved                           */
-    uint32_t SUBSTEP:4;        /*!< bit: 20..23  Sub-step of Core Release           */
-    uint32_t STEP:4;           /*!< bit: 24..27  Step of Core Release               */
-    uint32_t REL:4;            /*!< bit: 28..31  Core Release                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_CREL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_CREL_OFFSET             0x00         /**< \brief (CAN_CREL offset) Core Release */
-#define CAN_CREL_RESETVALUE         0x32100000u  /**< \brief (CAN_CREL reset_value) Core Release */
-
-#define CAN_CREL_SUBSTEP_Pos        20           /**< \brief (CAN_CREL) Sub-step of Core Release */
-#define CAN_CREL_SUBSTEP_Msk        (0xFu << CAN_CREL_SUBSTEP_Pos)
-#define CAN_CREL_SUBSTEP(value)     (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos))
-#define CAN_CREL_STEP_Pos           24           /**< \brief (CAN_CREL) Step of Core Release */
-#define CAN_CREL_STEP_Msk           (0xFu << CAN_CREL_STEP_Pos)
-#define CAN_CREL_STEP(value)        (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos))
-#define CAN_CREL_REL_Pos            28           /**< \brief (CAN_CREL) Core Release */
-#define CAN_CREL_REL_Msk            (0xFu << CAN_CREL_REL_Pos)
-#define CAN_CREL_REL(value)         (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos))
-#define CAN_CREL_MASK               0xFFF00000u  /**< \brief (CAN_CREL) MASK Register */
-
-/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/  32) Endian -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ETV:32;           /*!< bit:  0..31  Endianness Test Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_ENDN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ENDN_OFFSET             0x04         /**< \brief (CAN_ENDN offset) Endian */
-#define CAN_ENDN_RESETVALUE         0x87654321u  /**< \brief (CAN_ENDN reset_value) Endian */
-
-#define CAN_ENDN_ETV_Pos            0            /**< \brief (CAN_ENDN) Endianness Test Value */
-#define CAN_ENDN_ETV_Msk            (0xFFFFFFFFu << CAN_ENDN_ETV_Pos)
-#define CAN_ENDN_ETV(value)         (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos))
-#define CAN_ENDN_MASK               0xFFFFFFFFu  /**< \brief (CAN_ENDN) MASK Register */
-
-/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t QOS:2;            /*!< bit:  0.. 1  Quality of Service                 */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_MRCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_MRCFG_OFFSET            0x08         /**< \brief (CAN_MRCFG offset) Message RAM Configuration */
-#define CAN_MRCFG_RESETVALUE        0x00000002u  /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */
-
-#define CAN_MRCFG_QOS_Pos           0            /**< \brief (CAN_MRCFG) Quality of Service */
-#define CAN_MRCFG_QOS_Msk           (0x3u << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS(value)        (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos))
-#define   CAN_MRCFG_QOS_DISABLE_Val       0x0u   /**< \brief (CAN_MRCFG) Background (no sensitive operation) */
-#define   CAN_MRCFG_QOS_LOW_Val           0x1u   /**< \brief (CAN_MRCFG) Sensitive Bandwidth */
-#define   CAN_MRCFG_QOS_MEDIUM_Val        0x2u   /**< \brief (CAN_MRCFG) Sensitive Latency */
-#define   CAN_MRCFG_QOS_HIGH_Val          0x3u   /**< \brief (CAN_MRCFG) Critical Latency */
-#define CAN_MRCFG_QOS_DISABLE       (CAN_MRCFG_QOS_DISABLE_Val     << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS_LOW           (CAN_MRCFG_QOS_LOW_Val         << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS_MEDIUM        (CAN_MRCFG_QOS_MEDIUM_Val      << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_QOS_HIGH          (CAN_MRCFG_QOS_HIGH_Val        << CAN_MRCFG_QOS_Pos)
-#define CAN_MRCFG_MASK              0x00000003u  /**< \brief (CAN_MRCFG) MASK Register */
-
-/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DSJW:4;           /*!< bit:  0.. 3  Data (Re)Synchronization Jump Width */
-    uint32_t DTSEG2:4;         /*!< bit:  4.. 7  Data time segment after sample point */
-    uint32_t DTSEG1:5;         /*!< bit:  8..12  Data time segment before sample point */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t DBRP:5;           /*!< bit: 16..20  Data Baud Rate Prescaler           */
-    uint32_t :2;               /*!< bit: 21..22  Reserved                           */
-    uint32_t TDC:1;            /*!< bit:     23  Tranceiver Delay Compensation      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_DBTP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_DBTP_OFFSET             0x0C         /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */
-#define CAN_DBTP_RESETVALUE         0x00000A33u  /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */
-
-#define CAN_DBTP_DSJW_Pos           0            /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */
-#define CAN_DBTP_DSJW_Msk           (0xFu << CAN_DBTP_DSJW_Pos)
-#define CAN_DBTP_DSJW(value)        (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos))
-#define CAN_DBTP_DTSEG2_Pos         4            /**< \brief (CAN_DBTP) Data time segment after sample point */
-#define CAN_DBTP_DTSEG2_Msk         (0xFu << CAN_DBTP_DTSEG2_Pos)
-#define CAN_DBTP_DTSEG2(value)      (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos))
-#define CAN_DBTP_DTSEG1_Pos         8            /**< \brief (CAN_DBTP) Data time segment before sample point */
-#define CAN_DBTP_DTSEG1_Msk         (0x1Fu << CAN_DBTP_DTSEG1_Pos)
-#define CAN_DBTP_DTSEG1(value)      (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos))
-#define CAN_DBTP_DBRP_Pos           16           /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */
-#define CAN_DBTP_DBRP_Msk           (0x1Fu << CAN_DBTP_DBRP_Pos)
-#define CAN_DBTP_DBRP(value)        (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos))
-#define CAN_DBTP_TDC_Pos            23           /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */
-#define CAN_DBTP_TDC                (0x1u << CAN_DBTP_TDC_Pos)
-#define CAN_DBTP_MASK               0x009F1FFFu  /**< \brief (CAN_DBTP) MASK Register */
-
-/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint32_t LBCK:1;           /*!< bit:      4  Loop Back Mode                     */
-    uint32_t TX:2;             /*!< bit:  5.. 6  Control of Transmit Pin            */
-    uint32_t RX:1;             /*!< bit:      7  Receive Pin                        */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TEST_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TEST_OFFSET             0x10         /**< \brief (CAN_TEST offset) Test */
-#define CAN_TEST_RESETVALUE         0x00000000u  /**< \brief (CAN_TEST reset_value) Test */
-
-#define CAN_TEST_LBCK_Pos           4            /**< \brief (CAN_TEST) Loop Back Mode */
-#define CAN_TEST_LBCK               (0x1u << CAN_TEST_LBCK_Pos)
-#define CAN_TEST_TX_Pos             5            /**< \brief (CAN_TEST) Control of Transmit Pin */
-#define CAN_TEST_TX_Msk             (0x3u << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX(value)          (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos))
-#define   CAN_TEST_TX_CORE_Val            0x0u   /**< \brief (CAN_TEST) TX controlled by CAN core */
-#define   CAN_TEST_TX_SAMPLE_Val          0x1u   /**< \brief (CAN_TEST) TX monitoring sample point */
-#define   CAN_TEST_TX_DOMINANT_Val        0x2u   /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */
-#define   CAN_TEST_TX_RECESSIVE_Val       0x3u   /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */
-#define CAN_TEST_TX_CORE            (CAN_TEST_TX_CORE_Val          << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX_SAMPLE          (CAN_TEST_TX_SAMPLE_Val        << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX_DOMINANT        (CAN_TEST_TX_DOMINANT_Val      << CAN_TEST_TX_Pos)
-#define CAN_TEST_TX_RECESSIVE       (CAN_TEST_TX_RECESSIVE_Val     << CAN_TEST_TX_Pos)
-#define CAN_TEST_RX_Pos             7            /**< \brief (CAN_TEST) Receive Pin */
-#define CAN_TEST_RX                 (0x1u << CAN_TEST_RX_Pos)
-#define CAN_TEST_MASK               0x000000F0u  /**< \brief (CAN_TEST) MASK Register */
-
-/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WDC:8;            /*!< bit:  0.. 7  Watchdog Configuration             */
-    uint32_t WDV:8;            /*!< bit:  8..15  Watchdog Value                     */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RWD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RWD_OFFSET              0x14         /**< \brief (CAN_RWD offset) RAM Watchdog */
-#define CAN_RWD_RESETVALUE          0x00000000u  /**< \brief (CAN_RWD reset_value) RAM Watchdog */
-
-#define CAN_RWD_WDC_Pos             0            /**< \brief (CAN_RWD) Watchdog Configuration */
-#define CAN_RWD_WDC_Msk             (0xFFu << CAN_RWD_WDC_Pos)
-#define CAN_RWD_WDC(value)          (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos))
-#define CAN_RWD_WDV_Pos             8            /**< \brief (CAN_RWD) Watchdog Value */
-#define CAN_RWD_WDV_Msk             (0xFFu << CAN_RWD_WDV_Pos)
-#define CAN_RWD_WDV(value)          (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos))
-#define CAN_RWD_MASK                0x0000FFFFu  /**< \brief (CAN_RWD) MASK Register */
-
-/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t INIT:1;           /*!< bit:      0  Initialization                     */
-    uint32_t CCE:1;            /*!< bit:      1  Configuration Change Enable        */
-    uint32_t ASM:1;            /*!< bit:      2  ASM Restricted Operation Mode      */
-    uint32_t CSA:1;            /*!< bit:      3  Clock Stop Acknowledge             */
-    uint32_t CSR:1;            /*!< bit:      4  Clock Stop Request                 */
-    uint32_t MON:1;            /*!< bit:      5  Bus Monitoring Mode                */
-    uint32_t DAR:1;            /*!< bit:      6  Disable Automatic Retransmission   */
-    uint32_t TEST:1;           /*!< bit:      7  Test Mode Enable                   */
-    uint32_t FDOE:1;           /*!< bit:      8  FD Operation Enable                */
-    uint32_t BRSE:1;           /*!< bit:      9  Bit Rate Switch Enable             */
-    uint32_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint32_t PXHD:1;           /*!< bit:     12  Protocol Exception Handling Disable */
-    uint32_t EFBI:1;           /*!< bit:     13  Edge Filtering during Bus Integration */
-    uint32_t TXP:1;            /*!< bit:     14  Transmit Pause                     */
-    uint32_t NISO:1;           /*!< bit:     15  Non ISO Operation                  */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_CCCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_CCCR_OFFSET             0x18         /**< \brief (CAN_CCCR offset) CC Control */
-#define CAN_CCCR_RESETVALUE         0x00000001u  /**< \brief (CAN_CCCR reset_value) CC Control */
-
-#define CAN_CCCR_INIT_Pos           0            /**< \brief (CAN_CCCR) Initialization */
-#define CAN_CCCR_INIT               (0x1u << CAN_CCCR_INIT_Pos)
-#define CAN_CCCR_CCE_Pos            1            /**< \brief (CAN_CCCR) Configuration Change Enable */
-#define CAN_CCCR_CCE                (0x1u << CAN_CCCR_CCE_Pos)
-#define CAN_CCCR_ASM_Pos            2            /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */
-#define CAN_CCCR_ASM                (0x1u << CAN_CCCR_ASM_Pos)
-#define CAN_CCCR_CSA_Pos            3            /**< \brief (CAN_CCCR) Clock Stop Acknowledge */
-#define CAN_CCCR_CSA                (0x1u << CAN_CCCR_CSA_Pos)
-#define CAN_CCCR_CSR_Pos            4            /**< \brief (CAN_CCCR) Clock Stop Request */
-#define CAN_CCCR_CSR                (0x1u << CAN_CCCR_CSR_Pos)
-#define CAN_CCCR_MON_Pos            5            /**< \brief (CAN_CCCR) Bus Monitoring Mode */
-#define CAN_CCCR_MON                (0x1u << CAN_CCCR_MON_Pos)
-#define CAN_CCCR_DAR_Pos            6            /**< \brief (CAN_CCCR) Disable Automatic Retransmission */
-#define CAN_CCCR_DAR                (0x1u << CAN_CCCR_DAR_Pos)
-#define CAN_CCCR_TEST_Pos           7            /**< \brief (CAN_CCCR) Test Mode Enable */
-#define CAN_CCCR_TEST               (0x1u << CAN_CCCR_TEST_Pos)
-#define CAN_CCCR_FDOE_Pos           8            /**< \brief (CAN_CCCR) FD Operation Enable */
-#define CAN_CCCR_FDOE               (0x1u << CAN_CCCR_FDOE_Pos)
-#define CAN_CCCR_BRSE_Pos           9            /**< \brief (CAN_CCCR) Bit Rate Switch Enable */
-#define CAN_CCCR_BRSE               (0x1u << CAN_CCCR_BRSE_Pos)
-#define CAN_CCCR_PXHD_Pos           12           /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */
-#define CAN_CCCR_PXHD               (0x1u << CAN_CCCR_PXHD_Pos)
-#define CAN_CCCR_EFBI_Pos           13           /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */
-#define CAN_CCCR_EFBI               (0x1u << CAN_CCCR_EFBI_Pos)
-#define CAN_CCCR_TXP_Pos            14           /**< \brief (CAN_CCCR) Transmit Pause */
-#define CAN_CCCR_TXP                (0x1u << CAN_CCCR_TXP_Pos)
-#define CAN_CCCR_NISO_Pos           15           /**< \brief (CAN_CCCR) Non ISO Operation */
-#define CAN_CCCR_NISO               (0x1u << CAN_CCCR_NISO_Pos)
-#define CAN_CCCR_MASK               0x0000F3FFu  /**< \brief (CAN_CCCR) MASK Register */
-
-/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t NTSEG2:7;         /*!< bit:  0.. 6  Nominal Time segment after sample point */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t NTSEG1:8;         /*!< bit:  8..15  Nominal Time segment before sample point */
-    uint32_t NBRP:9;           /*!< bit: 16..24  Nominal Baud Rate Prescaler        */
-    uint32_t NSJW:7;           /*!< bit: 25..31  Nominal (Re)Synchronization Jump Width */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_NBTP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_NBTP_OFFSET             0x1C         /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */
-#define CAN_NBTP_RESETVALUE         0x06000A03u  /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */
-
-#define CAN_NBTP_NTSEG2_Pos         0            /**< \brief (CAN_NBTP) Nominal Time segment after sample point */
-#define CAN_NBTP_NTSEG2_Msk         (0x7Fu << CAN_NBTP_NTSEG2_Pos)
-#define CAN_NBTP_NTSEG2(value)      (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos))
-#define CAN_NBTP_NTSEG1_Pos         8            /**< \brief (CAN_NBTP) Nominal Time segment before sample point */
-#define CAN_NBTP_NTSEG1_Msk         (0xFFu << CAN_NBTP_NTSEG1_Pos)
-#define CAN_NBTP_NTSEG1(value)      (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos))
-#define CAN_NBTP_NBRP_Pos           16           /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */
-#define CAN_NBTP_NBRP_Msk           (0x1FFu << CAN_NBTP_NBRP_Pos)
-#define CAN_NBTP_NBRP(value)        (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos))
-#define CAN_NBTP_NSJW_Pos           25           /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */
-#define CAN_NBTP_NSJW_Msk           (0x7Fu << CAN_NBTP_NSJW_Pos)
-#define CAN_NBTP_NSJW(value)        (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos))
-#define CAN_NBTP_MASK               0xFFFFFF7Fu  /**< \brief (CAN_NBTP) MASK Register */
-
-/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TSS:2;            /*!< bit:  0.. 1  Timestamp Select                   */
-    uint32_t :14;              /*!< bit:  2..15  Reserved                           */
-    uint32_t TCP:4;            /*!< bit: 16..19  Timestamp Counter Prescaler        */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TSCC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TSCC_OFFSET             0x20         /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */
-#define CAN_TSCC_RESETVALUE         0x00000000u  /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */
-
-#define CAN_TSCC_TSS_Pos            0            /**< \brief (CAN_TSCC) Timestamp Select */
-#define CAN_TSCC_TSS_Msk            (0x3u << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TSS(value)         (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos))
-#define   CAN_TSCC_TSS_ZERO_Val           0x0u   /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */
-#define   CAN_TSCC_TSS_INC_Val            0x1u   /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */
-#define   CAN_TSCC_TSS_EXT_Val            0x2u   /**< \brief (CAN_TSCC) External timestamp counter value used */
-#define CAN_TSCC_TSS_ZERO           (CAN_TSCC_TSS_ZERO_Val         << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TSS_INC            (CAN_TSCC_TSS_INC_Val          << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TSS_EXT            (CAN_TSCC_TSS_EXT_Val          << CAN_TSCC_TSS_Pos)
-#define CAN_TSCC_TCP_Pos            16           /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */
-#define CAN_TSCC_TCP_Msk            (0xFu << CAN_TSCC_TCP_Pos)
-#define CAN_TSCC_TCP(value)         (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos))
-#define CAN_TSCC_MASK               0x000F0003u  /**< \brief (CAN_TSCC) MASK Register */
-
-/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/  32) Timestamp Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TSC:16;           /*!< bit:  0..15  Timestamp Counter                  */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TSCV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TSCV_OFFSET             0x24         /**< \brief (CAN_TSCV offset) Timestamp Counter Value */
-#define CAN_TSCV_RESETVALUE         0x00000000u  /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */
-
-#define CAN_TSCV_TSC_Pos            0            /**< \brief (CAN_TSCV) Timestamp Counter */
-#define CAN_TSCV_TSC_Msk            (0xFFFFu << CAN_TSCV_TSC_Pos)
-#define CAN_TSCV_TSC(value)         (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos))
-#define CAN_TSCV_MASK               0x0000FFFFu  /**< \brief (CAN_TSCV) MASK Register */
-
-/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ETOC:1;           /*!< bit:      0  Enable Timeout Counter             */
-    uint32_t TOS:2;            /*!< bit:  1.. 2  Timeout Select                     */
-    uint32_t :13;              /*!< bit:  3..15  Reserved                           */
-    uint32_t TOP:16;           /*!< bit: 16..31  Timeout Period                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TOCC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TOCC_OFFSET             0x28         /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */
-#define CAN_TOCC_RESETVALUE         0xFFFF0000u  /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */
-
-#define CAN_TOCC_ETOC_Pos           0            /**< \brief (CAN_TOCC) Enable Timeout Counter */
-#define CAN_TOCC_ETOC               (0x1u << CAN_TOCC_ETOC_Pos)
-#define CAN_TOCC_TOS_Pos            1            /**< \brief (CAN_TOCC) Timeout Select */
-#define CAN_TOCC_TOS_Msk            (0x3u << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS(value)         (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos))
-#define   CAN_TOCC_TOS_CONT_Val           0x0u   /**< \brief (CAN_TOCC) Continuout operation */
-#define   CAN_TOCC_TOS_TXEF_Val           0x1u   /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */
-#define   CAN_TOCC_TOS_RXF0_Val           0x2u   /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */
-#define   CAN_TOCC_TOS_RXF1_Val           0x3u   /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */
-#define CAN_TOCC_TOS_CONT           (CAN_TOCC_TOS_CONT_Val         << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS_TXEF           (CAN_TOCC_TOS_TXEF_Val         << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS_RXF0           (CAN_TOCC_TOS_RXF0_Val         << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOS_RXF1           (CAN_TOCC_TOS_RXF1_Val         << CAN_TOCC_TOS_Pos)
-#define CAN_TOCC_TOP_Pos            16           /**< \brief (CAN_TOCC) Timeout Period */
-#define CAN_TOCC_TOP_Msk            (0xFFFFu << CAN_TOCC_TOP_Pos)
-#define CAN_TOCC_TOP(value)         (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos))
-#define CAN_TOCC_MASK               0xFFFF0007u  /**< \brief (CAN_TOCC) MASK Register */
-
-/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TOC:16;           /*!< bit:  0..15  Timeout Counter                    */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TOCV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TOCV_OFFSET             0x2C         /**< \brief (CAN_TOCV offset) Timeout Counter Value */
-#define CAN_TOCV_RESETVALUE         0x0000FFFFu  /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */
-
-#define CAN_TOCV_TOC_Pos            0            /**< \brief (CAN_TOCV) Timeout Counter */
-#define CAN_TOCV_TOC_Msk            (0xFFFFu << CAN_TOCV_TOC_Pos)
-#define CAN_TOCV_TOC(value)         (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos))
-#define CAN_TOCV_MASK               0x0000FFFFu  /**< \brief (CAN_TOCV) MASK Register */
-
-/* -------- CAN_ECR : (CAN Offset: 0x40) (R/  32) Error Counter -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TEC:8;            /*!< bit:  0.. 7  Transmit Error Counter             */
-    uint32_t REC:7;            /*!< bit:  8..14  Receive Error Counter              */
-    uint32_t RP:1;             /*!< bit:     15  Receive Error Passive              */
-    uint32_t CEL:8;            /*!< bit: 16..23  CAN Error Logging                  */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_ECR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ECR_OFFSET              0x40         /**< \brief (CAN_ECR offset) Error Counter */
-#define CAN_ECR_RESETVALUE          0x00000000u  /**< \brief (CAN_ECR reset_value) Error Counter */
-
-#define CAN_ECR_TEC_Pos             0            /**< \brief (CAN_ECR) Transmit Error Counter */
-#define CAN_ECR_TEC_Msk             (0xFFu << CAN_ECR_TEC_Pos)
-#define CAN_ECR_TEC(value)          (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos))
-#define CAN_ECR_REC_Pos             8            /**< \brief (CAN_ECR) Receive Error Counter */
-#define CAN_ECR_REC_Msk             (0x7Fu << CAN_ECR_REC_Pos)
-#define CAN_ECR_REC(value)          (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos))
-#define CAN_ECR_RP_Pos              15           /**< \brief (CAN_ECR) Receive Error Passive */
-#define CAN_ECR_RP                  (0x1u << CAN_ECR_RP_Pos)
-#define CAN_ECR_CEL_Pos             16           /**< \brief (CAN_ECR) CAN Error Logging */
-#define CAN_ECR_CEL_Msk             (0xFFu << CAN_ECR_CEL_Pos)
-#define CAN_ECR_CEL(value)          (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos))
-#define CAN_ECR_MASK                0x00FFFFFFu  /**< \brief (CAN_ECR) MASK Register */
-
-/* -------- CAN_PSR : (CAN Offset: 0x44) (R/  32) Protocol Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LEC:3;            /*!< bit:  0.. 2  Last Error Code                    */
-    uint32_t ACT:2;            /*!< bit:  3.. 4  Activity                           */
-    uint32_t EP:1;             /*!< bit:      5  Error Passive                      */
-    uint32_t EW:1;             /*!< bit:      6  Warning Status                     */
-    uint32_t BO:1;             /*!< bit:      7  Bus_Off Status                     */
-    uint32_t DLEC:3;           /*!< bit:  8..10  Data Phase Last Error Code         */
-    uint32_t RESI:1;           /*!< bit:     11  ESI flag of last received CAN FD Message */
-    uint32_t RBRS:1;           /*!< bit:     12  BRS flag of last received CAN FD Message */
-    uint32_t RFDF:1;           /*!< bit:     13  Received a CAN FD Message          */
-    uint32_t PXE:1;            /*!< bit:     14  Protocol Exception Event           */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t TDCV:7;           /*!< bit: 16..22  Transmitter Delay Compensation Value */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_PSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_PSR_OFFSET              0x44         /**< \brief (CAN_PSR offset) Protocol Status */
-#define CAN_PSR_RESETVALUE          0x00000707u  /**< \brief (CAN_PSR reset_value) Protocol Status */
-
-#define CAN_PSR_LEC_Pos             0            /**< \brief (CAN_PSR) Last Error Code */
-#define CAN_PSR_LEC_Msk             (0x7u << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC(value)          (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos))
-#define   CAN_PSR_LEC_NONE_Val            0x0u   /**< \brief (CAN_PSR) No Error */
-#define   CAN_PSR_LEC_STUFF_Val           0x1u   /**< \brief (CAN_PSR) Stuff Error */
-#define   CAN_PSR_LEC_FORM_Val            0x2u   /**< \brief (CAN_PSR) Form Error */
-#define   CAN_PSR_LEC_ACK_Val             0x3u   /**< \brief (CAN_PSR) Ack Error */
-#define   CAN_PSR_LEC_BIT1_Val            0x4u   /**< \brief (CAN_PSR) Bit1 Error */
-#define   CAN_PSR_LEC_BIT0_Val            0x5u   /**< \brief (CAN_PSR) Bit0 Error */
-#define   CAN_PSR_LEC_CRC_Val             0x6u   /**< \brief (CAN_PSR) CRC Error */
-#define   CAN_PSR_LEC_NC_Val              0x7u   /**< \brief (CAN_PSR) No Change */
-#define CAN_PSR_LEC_NONE            (CAN_PSR_LEC_NONE_Val          << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_STUFF           (CAN_PSR_LEC_STUFF_Val         << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_FORM            (CAN_PSR_LEC_FORM_Val          << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_ACK             (CAN_PSR_LEC_ACK_Val           << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_BIT1            (CAN_PSR_LEC_BIT1_Val          << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_BIT0            (CAN_PSR_LEC_BIT0_Val          << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_CRC             (CAN_PSR_LEC_CRC_Val           << CAN_PSR_LEC_Pos)
-#define CAN_PSR_LEC_NC              (CAN_PSR_LEC_NC_Val            << CAN_PSR_LEC_Pos)
-#define CAN_PSR_ACT_Pos             3            /**< \brief (CAN_PSR) Activity */
-#define CAN_PSR_ACT_Msk             (0x3u << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT(value)          (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos))
-#define   CAN_PSR_ACT_SYNC_Val            0x0u   /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */
-#define   CAN_PSR_ACT_IDLE_Val            0x1u   /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */
-#define   CAN_PSR_ACT_RX_Val              0x2u   /**< \brief (CAN_PSR) Node is operating as receiver */
-#define   CAN_PSR_ACT_TX_Val              0x3u   /**< \brief (CAN_PSR) Node is operating as transmitter */
-#define CAN_PSR_ACT_SYNC            (CAN_PSR_ACT_SYNC_Val          << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT_IDLE            (CAN_PSR_ACT_IDLE_Val          << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT_RX              (CAN_PSR_ACT_RX_Val            << CAN_PSR_ACT_Pos)
-#define CAN_PSR_ACT_TX              (CAN_PSR_ACT_TX_Val            << CAN_PSR_ACT_Pos)
-#define CAN_PSR_EP_Pos              5            /**< \brief (CAN_PSR) Error Passive */
-#define CAN_PSR_EP                  (0x1u << CAN_PSR_EP_Pos)
-#define CAN_PSR_EW_Pos              6            /**< \brief (CAN_PSR) Warning Status */
-#define CAN_PSR_EW                  (0x1u << CAN_PSR_EW_Pos)
-#define CAN_PSR_BO_Pos              7            /**< \brief (CAN_PSR) Bus_Off Status */
-#define CAN_PSR_BO                  (0x1u << CAN_PSR_BO_Pos)
-#define CAN_PSR_DLEC_Pos            8            /**< \brief (CAN_PSR) Data Phase Last Error Code */
-#define CAN_PSR_DLEC_Msk            (0x7u << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC(value)         (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos))
-#define   CAN_PSR_DLEC_NONE_Val           0x0u   /**< \brief (CAN_PSR) No Error */
-#define   CAN_PSR_DLEC_STUFF_Val          0x1u   /**< \brief (CAN_PSR) Stuff Error */
-#define   CAN_PSR_DLEC_FORM_Val           0x2u   /**< \brief (CAN_PSR) Form Error */
-#define   CAN_PSR_DLEC_ACK_Val            0x3u   /**< \brief (CAN_PSR) Ack Error */
-#define   CAN_PSR_DLEC_BIT1_Val           0x4u   /**< \brief (CAN_PSR) Bit1 Error */
-#define   CAN_PSR_DLEC_BIT0_Val           0x5u   /**< \brief (CAN_PSR) Bit0 Error */
-#define   CAN_PSR_DLEC_CRC_Val            0x6u   /**< \brief (CAN_PSR) CRC Error */
-#define   CAN_PSR_DLEC_NC_Val             0x7u   /**< \brief (CAN_PSR) No Change */
-#define CAN_PSR_DLEC_NONE           (CAN_PSR_DLEC_NONE_Val         << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_STUFF          (CAN_PSR_DLEC_STUFF_Val        << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_FORM           (CAN_PSR_DLEC_FORM_Val         << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_ACK            (CAN_PSR_DLEC_ACK_Val          << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_BIT1           (CAN_PSR_DLEC_BIT1_Val         << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_BIT0           (CAN_PSR_DLEC_BIT0_Val         << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_CRC            (CAN_PSR_DLEC_CRC_Val          << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_DLEC_NC             (CAN_PSR_DLEC_NC_Val           << CAN_PSR_DLEC_Pos)
-#define CAN_PSR_RESI_Pos            11           /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */
-#define CAN_PSR_RESI                (0x1u << CAN_PSR_RESI_Pos)
-#define CAN_PSR_RBRS_Pos            12           /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */
-#define CAN_PSR_RBRS                (0x1u << CAN_PSR_RBRS_Pos)
-#define CAN_PSR_RFDF_Pos            13           /**< \brief (CAN_PSR) Received a CAN FD Message */
-#define CAN_PSR_RFDF                (0x1u << CAN_PSR_RFDF_Pos)
-#define CAN_PSR_PXE_Pos             14           /**< \brief (CAN_PSR) Protocol Exception Event */
-#define CAN_PSR_PXE                 (0x1u << CAN_PSR_PXE_Pos)
-#define CAN_PSR_TDCV_Pos            16           /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */
-#define CAN_PSR_TDCV_Msk            (0x7Fu << CAN_PSR_TDCV_Pos)
-#define CAN_PSR_TDCV(value)         (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos))
-#define CAN_PSR_MASK                0x007F7FFFu  /**< \brief (CAN_PSR) MASK Register */
-
-/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TDCF:7;           /*!< bit:  0.. 6  Transmitter Delay Compensation Filter Length */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t TDCO:7;           /*!< bit:  8..14  Transmitter Delay Compensation Offset */
-    uint32_t :17;              /*!< bit: 15..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TDCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TDCR_OFFSET             0x48         /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */
-#define CAN_TDCR_RESETVALUE         0x00000000u  /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */
-
-#define CAN_TDCR_TDCF_Pos           0            /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */
-#define CAN_TDCR_TDCF_Msk           (0x7Fu << CAN_TDCR_TDCF_Pos)
-#define CAN_TDCR_TDCF(value)        (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos))
-#define CAN_TDCR_TDCO_Pos           8            /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */
-#define CAN_TDCR_TDCO_Msk           (0x7Fu << CAN_TDCR_TDCO_Pos)
-#define CAN_TDCR_TDCO(value)        (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos))
-#define CAN_TDCR_MASK               0x00007F7Fu  /**< \brief (CAN_TDCR) MASK Register */
-
-/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RF0N:1;           /*!< bit:      0  Rx FIFO 0 New Message              */
-    uint32_t RF0W:1;           /*!< bit:      1  Rx FIFO 0 Watermark Reached        */
-    uint32_t RF0F:1;           /*!< bit:      2  Rx FIFO 0 Full                     */
-    uint32_t RF0L:1;           /*!< bit:      3  Rx FIFO 0 Message Lost             */
-    uint32_t RF1N:1;           /*!< bit:      4  Rx FIFO 1 New Message              */
-    uint32_t RF1W:1;           /*!< bit:      5  Rx FIFO 1 Watermark Reached        */
-    uint32_t RF1F:1;           /*!< bit:      6  Rx FIFO 1 FIFO Full                */
-    uint32_t RF1L:1;           /*!< bit:      7  Rx FIFO 1 Message Lost             */
-    uint32_t HPM:1;            /*!< bit:      8  High Priority Message              */
-    uint32_t TC:1;             /*!< bit:      9  Timestamp Completed                */
-    uint32_t TCF:1;            /*!< bit:     10  Transmission Cancellation Finished */
-    uint32_t TFE:1;            /*!< bit:     11  Tx FIFO Empty                      */
-    uint32_t TEFN:1;           /*!< bit:     12  Tx Event FIFO New Entry            */
-    uint32_t TEFW:1;           /*!< bit:     13  Tx Event FIFO Watermark Reached    */
-    uint32_t TEFF:1;           /*!< bit:     14  Tx Event FIFO Full                 */
-    uint32_t TEFL:1;           /*!< bit:     15  Tx Event FIFO Element Lost         */
-    uint32_t TSW:1;            /*!< bit:     16  Timestamp Wraparound               */
-    uint32_t MRAF:1;           /*!< bit:     17  Message RAM Access Failure         */
-    uint32_t TOO:1;            /*!< bit:     18  Timeout Occurred                   */
-    uint32_t DRX:1;            /*!< bit:     19  Message stored to Dedicated Rx Buffer */
-    uint32_t BEC:1;            /*!< bit:     20  Bit Error Corrected                */
-    uint32_t BEU:1;            /*!< bit:     21  Bit Error Uncorrected              */
-    uint32_t ELO:1;            /*!< bit:     22  Error Logging Overflow             */
-    uint32_t EP:1;             /*!< bit:     23  Error Passive                      */
-    uint32_t EW:1;             /*!< bit:     24  Warning Status                     */
-    uint32_t BO:1;             /*!< bit:     25  Bus_Off Status                     */
-    uint32_t WDI:1;            /*!< bit:     26  Watchdog Interrupt                 */
-    uint32_t PEA:1;            /*!< bit:     27  Protocol Error in Arbitration Phase */
-    uint32_t PED:1;            /*!< bit:     28  Protocol Error in Data Phase       */
-    uint32_t ARA:1;            /*!< bit:     29  Access to Reserved Address         */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_IR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_IR_OFFSET               0x50         /**< \brief (CAN_IR offset) Interrupt */
-#define CAN_IR_RESETVALUE           0x00000000u  /**< \brief (CAN_IR reset_value) Interrupt */
-
-#define CAN_IR_RF0N_Pos             0            /**< \brief (CAN_IR) Rx FIFO 0 New Message */
-#define CAN_IR_RF0N                 (0x1u << CAN_IR_RF0N_Pos)
-#define CAN_IR_RF0W_Pos             1            /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */
-#define CAN_IR_RF0W                 (0x1u << CAN_IR_RF0W_Pos)
-#define CAN_IR_RF0F_Pos             2            /**< \brief (CAN_IR) Rx FIFO 0 Full */
-#define CAN_IR_RF0F                 (0x1u << CAN_IR_RF0F_Pos)
-#define CAN_IR_RF0L_Pos             3            /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */
-#define CAN_IR_RF0L                 (0x1u << CAN_IR_RF0L_Pos)
-#define CAN_IR_RF1N_Pos             4            /**< \brief (CAN_IR) Rx FIFO 1 New Message */
-#define CAN_IR_RF1N                 (0x1u << CAN_IR_RF1N_Pos)
-#define CAN_IR_RF1W_Pos             5            /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */
-#define CAN_IR_RF1W                 (0x1u << CAN_IR_RF1W_Pos)
-#define CAN_IR_RF1F_Pos             6            /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */
-#define CAN_IR_RF1F                 (0x1u << CAN_IR_RF1F_Pos)
-#define CAN_IR_RF1L_Pos             7            /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */
-#define CAN_IR_RF1L                 (0x1u << CAN_IR_RF1L_Pos)
-#define CAN_IR_HPM_Pos              8            /**< \brief (CAN_IR) High Priority Message */
-#define CAN_IR_HPM                  (0x1u << CAN_IR_HPM_Pos)
-#define CAN_IR_TC_Pos               9            /**< \brief (CAN_IR) Timestamp Completed */
-#define CAN_IR_TC                   (0x1u << CAN_IR_TC_Pos)
-#define CAN_IR_TCF_Pos              10           /**< \brief (CAN_IR) Transmission Cancellation Finished */
-#define CAN_IR_TCF                  (0x1u << CAN_IR_TCF_Pos)
-#define CAN_IR_TFE_Pos              11           /**< \brief (CAN_IR) Tx FIFO Empty */
-#define CAN_IR_TFE                  (0x1u << CAN_IR_TFE_Pos)
-#define CAN_IR_TEFN_Pos             12           /**< \brief (CAN_IR) Tx Event FIFO New Entry */
-#define CAN_IR_TEFN                 (0x1u << CAN_IR_TEFN_Pos)
-#define CAN_IR_TEFW_Pos             13           /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */
-#define CAN_IR_TEFW                 (0x1u << CAN_IR_TEFW_Pos)
-#define CAN_IR_TEFF_Pos             14           /**< \brief (CAN_IR) Tx Event FIFO Full */
-#define CAN_IR_TEFF                 (0x1u << CAN_IR_TEFF_Pos)
-#define CAN_IR_TEFL_Pos             15           /**< \brief (CAN_IR) Tx Event FIFO Element Lost */
-#define CAN_IR_TEFL                 (0x1u << CAN_IR_TEFL_Pos)
-#define CAN_IR_TSW_Pos              16           /**< \brief (CAN_IR) Timestamp Wraparound */
-#define CAN_IR_TSW                  (0x1u << CAN_IR_TSW_Pos)
-#define CAN_IR_MRAF_Pos             17           /**< \brief (CAN_IR) Message RAM Access Failure */
-#define CAN_IR_MRAF                 (0x1u << CAN_IR_MRAF_Pos)
-#define CAN_IR_TOO_Pos              18           /**< \brief (CAN_IR) Timeout Occurred */
-#define CAN_IR_TOO                  (0x1u << CAN_IR_TOO_Pos)
-#define CAN_IR_DRX_Pos              19           /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */
-#define CAN_IR_DRX                  (0x1u << CAN_IR_DRX_Pos)
-#define CAN_IR_BEC_Pos              20           /**< \brief (CAN_IR) Bit Error Corrected */
-#define CAN_IR_BEC                  (0x1u << CAN_IR_BEC_Pos)
-#define CAN_IR_BEU_Pos              21           /**< \brief (CAN_IR) Bit Error Uncorrected */
-#define CAN_IR_BEU                  (0x1u << CAN_IR_BEU_Pos)
-#define CAN_IR_ELO_Pos              22           /**< \brief (CAN_IR) Error Logging Overflow */
-#define CAN_IR_ELO                  (0x1u << CAN_IR_ELO_Pos)
-#define CAN_IR_EP_Pos               23           /**< \brief (CAN_IR) Error Passive */
-#define CAN_IR_EP                   (0x1u << CAN_IR_EP_Pos)
-#define CAN_IR_EW_Pos               24           /**< \brief (CAN_IR) Warning Status */
-#define CAN_IR_EW                   (0x1u << CAN_IR_EW_Pos)
-#define CAN_IR_BO_Pos               25           /**< \brief (CAN_IR) Bus_Off Status */
-#define CAN_IR_BO                   (0x1u << CAN_IR_BO_Pos)
-#define CAN_IR_WDI_Pos              26           /**< \brief (CAN_IR) Watchdog Interrupt */
-#define CAN_IR_WDI                  (0x1u << CAN_IR_WDI_Pos)
-#define CAN_IR_PEA_Pos              27           /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */
-#define CAN_IR_PEA                  (0x1u << CAN_IR_PEA_Pos)
-#define CAN_IR_PED_Pos              28           /**< \brief (CAN_IR) Protocol Error in Data Phase */
-#define CAN_IR_PED                  (0x1u << CAN_IR_PED_Pos)
-#define CAN_IR_ARA_Pos              29           /**< \brief (CAN_IR) Access to Reserved Address */
-#define CAN_IR_ARA                  (0x1u << CAN_IR_ARA_Pos)
-#define CAN_IR_MASK                 0x3FFFFFFFu  /**< \brief (CAN_IR) MASK Register */
-
-/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RF0NE:1;          /*!< bit:      0  Rx FIFO 0 New Message Interrupt Enable */
-    uint32_t RF0WE:1;          /*!< bit:      1  Rx FIFO 0 Watermark Reached Interrupt Enable */
-    uint32_t RF0FE:1;          /*!< bit:      2  Rx FIFO 0 Full Interrupt Enable    */
-    uint32_t RF0LE:1;          /*!< bit:      3  Rx FIFO 0 Message Lost Interrupt Enable */
-    uint32_t RF1NE:1;          /*!< bit:      4  Rx FIFO 1 New Message Interrupt Enable */
-    uint32_t RF1WE:1;          /*!< bit:      5  Rx FIFO 1 Watermark Reached Interrupt Enable */
-    uint32_t RF1FE:1;          /*!< bit:      6  Rx FIFO 1 FIFO Full Interrupt Enable */
-    uint32_t RF1LE:1;          /*!< bit:      7  Rx FIFO 1 Message Lost Interrupt Enable */
-    uint32_t HPME:1;           /*!< bit:      8  High Priority Message Interrupt Enable */
-    uint32_t TCE:1;            /*!< bit:      9  Timestamp Completed Interrupt Enable */
-    uint32_t TCFE:1;           /*!< bit:     10  Transmission Cancellation Finished Interrupt Enable */
-    uint32_t TFEE:1;           /*!< bit:     11  Tx FIFO Empty Interrupt Enable     */
-    uint32_t TEFNE:1;          /*!< bit:     12  Tx Event FIFO New Entry Interrupt Enable */
-    uint32_t TEFWE:1;          /*!< bit:     13  Tx Event FIFO Watermark Reached Interrupt Enable */
-    uint32_t TEFFE:1;          /*!< bit:     14  Tx Event FIFO Full Interrupt Enable */
-    uint32_t TEFLE:1;          /*!< bit:     15  Tx Event FIFO Element Lost Interrupt Enable */
-    uint32_t TSWE:1;           /*!< bit:     16  Timestamp Wraparound Interrupt Enable */
-    uint32_t MRAFE:1;          /*!< bit:     17  Message RAM Access Failure Interrupt Enable */
-    uint32_t TOOE:1;           /*!< bit:     18  Timeout Occurred Interrupt Enable  */
-    uint32_t DRXE:1;           /*!< bit:     19  Message stored to Dedicated Rx Buffer Interrupt Enable */
-    uint32_t BECE:1;           /*!< bit:     20  Bit Error Corrected Interrupt Enable */
-    uint32_t BEUE:1;           /*!< bit:     21  Bit Error Uncorrected Interrupt Enable */
-    uint32_t ELOE:1;           /*!< bit:     22  Error Logging Overflow Interrupt Enable */
-    uint32_t EPE:1;            /*!< bit:     23  Error Passive Interrupt Enable     */
-    uint32_t EWE:1;            /*!< bit:     24  Warning Status Interrupt Enable    */
-    uint32_t BOE:1;            /*!< bit:     25  Bus_Off Status Interrupt Enable    */
-    uint32_t WDIE:1;           /*!< bit:     26  Watchdog Interrupt Interrupt Enable */
-    uint32_t PEAE:1;           /*!< bit:     27  Protocol Error in Arbitration Phase Enable */
-    uint32_t PEDE:1;           /*!< bit:     28  Protocol Error in Data Phase Enable */
-    uint32_t ARAE:1;           /*!< bit:     29  Access to Reserved Address Enable  */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_IE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_IE_OFFSET               0x54         /**< \brief (CAN_IE offset) Interrupt Enable */
-#define CAN_IE_RESETVALUE           0x00000000u  /**< \brief (CAN_IE reset_value) Interrupt Enable */
-
-#define CAN_IE_RF0NE_Pos            0            /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */
-#define CAN_IE_RF0NE                (0x1u << CAN_IE_RF0NE_Pos)
-#define CAN_IE_RF0WE_Pos            1            /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */
-#define CAN_IE_RF0WE                (0x1u << CAN_IE_RF0WE_Pos)
-#define CAN_IE_RF0FE_Pos            2            /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */
-#define CAN_IE_RF0FE                (0x1u << CAN_IE_RF0FE_Pos)
-#define CAN_IE_RF0LE_Pos            3            /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */
-#define CAN_IE_RF0LE                (0x1u << CAN_IE_RF0LE_Pos)
-#define CAN_IE_RF1NE_Pos            4            /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */
-#define CAN_IE_RF1NE                (0x1u << CAN_IE_RF1NE_Pos)
-#define CAN_IE_RF1WE_Pos            5            /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */
-#define CAN_IE_RF1WE                (0x1u << CAN_IE_RF1WE_Pos)
-#define CAN_IE_RF1FE_Pos            6            /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */
-#define CAN_IE_RF1FE                (0x1u << CAN_IE_RF1FE_Pos)
-#define CAN_IE_RF1LE_Pos            7            /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */
-#define CAN_IE_RF1LE                (0x1u << CAN_IE_RF1LE_Pos)
-#define CAN_IE_HPME_Pos             8            /**< \brief (CAN_IE) High Priority Message Interrupt Enable */
-#define CAN_IE_HPME                 (0x1u << CAN_IE_HPME_Pos)
-#define CAN_IE_TCE_Pos              9            /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */
-#define CAN_IE_TCE                  (0x1u << CAN_IE_TCE_Pos)
-#define CAN_IE_TCFE_Pos             10           /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */
-#define CAN_IE_TCFE                 (0x1u << CAN_IE_TCFE_Pos)
-#define CAN_IE_TFEE_Pos             11           /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */
-#define CAN_IE_TFEE                 (0x1u << CAN_IE_TFEE_Pos)
-#define CAN_IE_TEFNE_Pos            12           /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */
-#define CAN_IE_TEFNE                (0x1u << CAN_IE_TEFNE_Pos)
-#define CAN_IE_TEFWE_Pos            13           /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */
-#define CAN_IE_TEFWE                (0x1u << CAN_IE_TEFWE_Pos)
-#define CAN_IE_TEFFE_Pos            14           /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */
-#define CAN_IE_TEFFE                (0x1u << CAN_IE_TEFFE_Pos)
-#define CAN_IE_TEFLE_Pos            15           /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */
-#define CAN_IE_TEFLE                (0x1u << CAN_IE_TEFLE_Pos)
-#define CAN_IE_TSWE_Pos             16           /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */
-#define CAN_IE_TSWE                 (0x1u << CAN_IE_TSWE_Pos)
-#define CAN_IE_MRAFE_Pos            17           /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */
-#define CAN_IE_MRAFE                (0x1u << CAN_IE_MRAFE_Pos)
-#define CAN_IE_TOOE_Pos             18           /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */
-#define CAN_IE_TOOE                 (0x1u << CAN_IE_TOOE_Pos)
-#define CAN_IE_DRXE_Pos             19           /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */
-#define CAN_IE_DRXE                 (0x1u << CAN_IE_DRXE_Pos)
-#define CAN_IE_BECE_Pos             20           /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */
-#define CAN_IE_BECE                 (0x1u << CAN_IE_BECE_Pos)
-#define CAN_IE_BEUE_Pos             21           /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */
-#define CAN_IE_BEUE                 (0x1u << CAN_IE_BEUE_Pos)
-#define CAN_IE_ELOE_Pos             22           /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */
-#define CAN_IE_ELOE                 (0x1u << CAN_IE_ELOE_Pos)
-#define CAN_IE_EPE_Pos              23           /**< \brief (CAN_IE) Error Passive Interrupt Enable */
-#define CAN_IE_EPE                  (0x1u << CAN_IE_EPE_Pos)
-#define CAN_IE_EWE_Pos              24           /**< \brief (CAN_IE) Warning Status Interrupt Enable */
-#define CAN_IE_EWE                  (0x1u << CAN_IE_EWE_Pos)
-#define CAN_IE_BOE_Pos              25           /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */
-#define CAN_IE_BOE                  (0x1u << CAN_IE_BOE_Pos)
-#define CAN_IE_WDIE_Pos             26           /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */
-#define CAN_IE_WDIE                 (0x1u << CAN_IE_WDIE_Pos)
-#define CAN_IE_PEAE_Pos             27           /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */
-#define CAN_IE_PEAE                 (0x1u << CAN_IE_PEAE_Pos)
-#define CAN_IE_PEDE_Pos             28           /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */
-#define CAN_IE_PEDE                 (0x1u << CAN_IE_PEDE_Pos)
-#define CAN_IE_ARAE_Pos             29           /**< \brief (CAN_IE) Access to Reserved Address Enable */
-#define CAN_IE_ARAE                 (0x1u << CAN_IE_ARAE_Pos)
-#define CAN_IE_MASK                 0x3FFFFFFFu  /**< \brief (CAN_IE) MASK Register */
-
-/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RF0NL:1;          /*!< bit:      0  Rx FIFO 0 New Message Interrupt Line */
-    uint32_t RF0WL:1;          /*!< bit:      1  Rx FIFO 0 Watermark Reached Interrupt Line */
-    uint32_t RF0FL:1;          /*!< bit:      2  Rx FIFO 0 Full Interrupt Line      */
-    uint32_t RF0LL:1;          /*!< bit:      3  Rx FIFO 0 Message Lost Interrupt Line */
-    uint32_t RF1NL:1;          /*!< bit:      4  Rx FIFO 1 New Message Interrupt Line */
-    uint32_t RF1WL:1;          /*!< bit:      5  Rx FIFO 1 Watermark Reached Interrupt Line */
-    uint32_t RF1FL:1;          /*!< bit:      6  Rx FIFO 1 FIFO Full Interrupt Line */
-    uint32_t RF1LL:1;          /*!< bit:      7  Rx FIFO 1 Message Lost Interrupt Line */
-    uint32_t HPML:1;           /*!< bit:      8  High Priority Message Interrupt Line */
-    uint32_t TCL:1;            /*!< bit:      9  Timestamp Completed Interrupt Line */
-    uint32_t TCFL:1;           /*!< bit:     10  Transmission Cancellation Finished Interrupt Line */
-    uint32_t TFEL:1;           /*!< bit:     11  Tx FIFO Empty Interrupt Line       */
-    uint32_t TEFNL:1;          /*!< bit:     12  Tx Event FIFO New Entry Interrupt Line */
-    uint32_t TEFWL:1;          /*!< bit:     13  Tx Event FIFO Watermark Reached Interrupt Line */
-    uint32_t TEFFL:1;          /*!< bit:     14  Tx Event FIFO Full Interrupt Line  */
-    uint32_t TEFLL:1;          /*!< bit:     15  Tx Event FIFO Element Lost Interrupt Line */
-    uint32_t TSWL:1;           /*!< bit:     16  Timestamp Wraparound Interrupt Line */
-    uint32_t MRAFL:1;          /*!< bit:     17  Message RAM Access Failure Interrupt Line */
-    uint32_t TOOL:1;           /*!< bit:     18  Timeout Occurred Interrupt Line    */
-    uint32_t DRXL:1;           /*!< bit:     19  Message stored to Dedicated Rx Buffer Interrupt Line */
-    uint32_t BECL:1;           /*!< bit:     20  Bit Error Corrected Interrupt Line */
-    uint32_t BEUL:1;           /*!< bit:     21  Bit Error Uncorrected Interrupt Line */
-    uint32_t ELOL:1;           /*!< bit:     22  Error Logging Overflow Interrupt Line */
-    uint32_t EPL:1;            /*!< bit:     23  Error Passive Interrupt Line       */
-    uint32_t EWL:1;            /*!< bit:     24  Warning Status Interrupt Line      */
-    uint32_t BOL:1;            /*!< bit:     25  Bus_Off Status Interrupt Line      */
-    uint32_t WDIL:1;           /*!< bit:     26  Watchdog Interrupt Interrupt Line  */
-    uint32_t PEAL:1;           /*!< bit:     27  Protocol Error in Arbitration Phase Line */
-    uint32_t PEDL:1;           /*!< bit:     28  Protocol Error in Data Phase Line  */
-    uint32_t ARAL:1;           /*!< bit:     29  Access to Reserved Address Line    */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_ILS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ILS_OFFSET              0x58         /**< \brief (CAN_ILS offset) Interrupt Line Select */
-#define CAN_ILS_RESETVALUE          0x00000000u  /**< \brief (CAN_ILS reset_value) Interrupt Line Select */
-
-#define CAN_ILS_RF0NL_Pos           0            /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */
-#define CAN_ILS_RF0NL               (0x1u << CAN_ILS_RF0NL_Pos)
-#define CAN_ILS_RF0WL_Pos           1            /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */
-#define CAN_ILS_RF0WL               (0x1u << CAN_ILS_RF0WL_Pos)
-#define CAN_ILS_RF0FL_Pos           2            /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */
-#define CAN_ILS_RF0FL               (0x1u << CAN_ILS_RF0FL_Pos)
-#define CAN_ILS_RF0LL_Pos           3            /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */
-#define CAN_ILS_RF0LL               (0x1u << CAN_ILS_RF0LL_Pos)
-#define CAN_ILS_RF1NL_Pos           4            /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */
-#define CAN_ILS_RF1NL               (0x1u << CAN_ILS_RF1NL_Pos)
-#define CAN_ILS_RF1WL_Pos           5            /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */
-#define CAN_ILS_RF1WL               (0x1u << CAN_ILS_RF1WL_Pos)
-#define CAN_ILS_RF1FL_Pos           6            /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */
-#define CAN_ILS_RF1FL               (0x1u << CAN_ILS_RF1FL_Pos)
-#define CAN_ILS_RF1LL_Pos           7            /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */
-#define CAN_ILS_RF1LL               (0x1u << CAN_ILS_RF1LL_Pos)
-#define CAN_ILS_HPML_Pos            8            /**< \brief (CAN_ILS) High Priority Message Interrupt Line */
-#define CAN_ILS_HPML                (0x1u << CAN_ILS_HPML_Pos)
-#define CAN_ILS_TCL_Pos             9            /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */
-#define CAN_ILS_TCL                 (0x1u << CAN_ILS_TCL_Pos)
-#define CAN_ILS_TCFL_Pos            10           /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */
-#define CAN_ILS_TCFL                (0x1u << CAN_ILS_TCFL_Pos)
-#define CAN_ILS_TFEL_Pos            11           /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */
-#define CAN_ILS_TFEL                (0x1u << CAN_ILS_TFEL_Pos)
-#define CAN_ILS_TEFNL_Pos           12           /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */
-#define CAN_ILS_TEFNL               (0x1u << CAN_ILS_TEFNL_Pos)
-#define CAN_ILS_TEFWL_Pos           13           /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */
-#define CAN_ILS_TEFWL               (0x1u << CAN_ILS_TEFWL_Pos)
-#define CAN_ILS_TEFFL_Pos           14           /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */
-#define CAN_ILS_TEFFL               (0x1u << CAN_ILS_TEFFL_Pos)
-#define CAN_ILS_TEFLL_Pos           15           /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */
-#define CAN_ILS_TEFLL               (0x1u << CAN_ILS_TEFLL_Pos)
-#define CAN_ILS_TSWL_Pos            16           /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */
-#define CAN_ILS_TSWL                (0x1u << CAN_ILS_TSWL_Pos)
-#define CAN_ILS_MRAFL_Pos           17           /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */
-#define CAN_ILS_MRAFL               (0x1u << CAN_ILS_MRAFL_Pos)
-#define CAN_ILS_TOOL_Pos            18           /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */
-#define CAN_ILS_TOOL                (0x1u << CAN_ILS_TOOL_Pos)
-#define CAN_ILS_DRXL_Pos            19           /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */
-#define CAN_ILS_DRXL                (0x1u << CAN_ILS_DRXL_Pos)
-#define CAN_ILS_BECL_Pos            20           /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */
-#define CAN_ILS_BECL                (0x1u << CAN_ILS_BECL_Pos)
-#define CAN_ILS_BEUL_Pos            21           /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */
-#define CAN_ILS_BEUL                (0x1u << CAN_ILS_BEUL_Pos)
-#define CAN_ILS_ELOL_Pos            22           /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */
-#define CAN_ILS_ELOL                (0x1u << CAN_ILS_ELOL_Pos)
-#define CAN_ILS_EPL_Pos             23           /**< \brief (CAN_ILS) Error Passive Interrupt Line */
-#define CAN_ILS_EPL                 (0x1u << CAN_ILS_EPL_Pos)
-#define CAN_ILS_EWL_Pos             24           /**< \brief (CAN_ILS) Warning Status Interrupt Line */
-#define CAN_ILS_EWL                 (0x1u << CAN_ILS_EWL_Pos)
-#define CAN_ILS_BOL_Pos             25           /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */
-#define CAN_ILS_BOL                 (0x1u << CAN_ILS_BOL_Pos)
-#define CAN_ILS_WDIL_Pos            26           /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */
-#define CAN_ILS_WDIL                (0x1u << CAN_ILS_WDIL_Pos)
-#define CAN_ILS_PEAL_Pos            27           /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */
-#define CAN_ILS_PEAL                (0x1u << CAN_ILS_PEAL_Pos)
-#define CAN_ILS_PEDL_Pos            28           /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */
-#define CAN_ILS_PEDL                (0x1u << CAN_ILS_PEDL_Pos)
-#define CAN_ILS_ARAL_Pos            29           /**< \brief (CAN_ILS) Access to Reserved Address Line */
-#define CAN_ILS_ARAL                (0x1u << CAN_ILS_ARAL_Pos)
-#define CAN_ILS_MASK                0x3FFFFFFFu  /**< \brief (CAN_ILS) MASK Register */
-
-/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EINT0:1;          /*!< bit:      0  Enable Interrupt Line 0            */
-    uint32_t EINT1:1;          /*!< bit:      1  Enable Interrupt Line 1            */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_ILE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_ILE_OFFSET              0x5C         /**< \brief (CAN_ILE offset) Interrupt Line Enable */
-#define CAN_ILE_RESETVALUE          0x00000000u  /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */
-
-#define CAN_ILE_EINT0_Pos           0            /**< \brief (CAN_ILE) Enable Interrupt Line 0 */
-#define CAN_ILE_EINT0               (0x1u << CAN_ILE_EINT0_Pos)
-#define CAN_ILE_EINT1_Pos           1            /**< \brief (CAN_ILE) Enable Interrupt Line 1 */
-#define CAN_ILE_EINT1               (0x1u << CAN_ILE_EINT1_Pos)
-#define CAN_ILE_MASK                0x00000003u  /**< \brief (CAN_ILE) MASK Register */
-
-/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RRFE:1;           /*!< bit:      0  Reject Remote Frames Extended      */
-    uint32_t RRFS:1;           /*!< bit:      1  Reject Remote Frames Standard      */
-    uint32_t ANFE:2;           /*!< bit:  2.. 3  Accept Non-matching Frames Extended */
-    uint32_t ANFS:2;           /*!< bit:  4.. 5  Accept Non-matching Frames Standard */
-    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_GFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_GFC_OFFSET              0x80         /**< \brief (CAN_GFC offset) Global Filter Configuration */
-#define CAN_GFC_RESETVALUE          0x00000000u  /**< \brief (CAN_GFC reset_value) Global Filter Configuration */
-
-#define CAN_GFC_RRFE_Pos            0            /**< \brief (CAN_GFC) Reject Remote Frames Extended */
-#define CAN_GFC_RRFE                (0x1u << CAN_GFC_RRFE_Pos)
-#define CAN_GFC_RRFS_Pos            1            /**< \brief (CAN_GFC) Reject Remote Frames Standard */
-#define CAN_GFC_RRFS                (0x1u << CAN_GFC_RRFS_Pos)
-#define CAN_GFC_ANFE_Pos            2            /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */
-#define CAN_GFC_ANFE_Msk            (0x3u << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFE(value)         (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos))
-#define   CAN_GFC_ANFE_RXF0_Val           0x0u   /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
-#define   CAN_GFC_ANFE_RXF1_Val           0x1u   /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
-#define   CAN_GFC_ANFE_REJECT_Val         0x2u   /**< \brief (CAN_GFC) Reject */
-#define CAN_GFC_ANFE_RXF0           (CAN_GFC_ANFE_RXF0_Val         << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFE_RXF1           (CAN_GFC_ANFE_RXF1_Val         << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFE_REJECT         (CAN_GFC_ANFE_REJECT_Val       << CAN_GFC_ANFE_Pos)
-#define CAN_GFC_ANFS_Pos            4            /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */
-#define CAN_GFC_ANFS_Msk            (0x3u << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_ANFS(value)         (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos))
-#define   CAN_GFC_ANFS_RXF0_Val           0x0u   /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
-#define   CAN_GFC_ANFS_RXF1_Val           0x1u   /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
-#define   CAN_GFC_ANFS_REJECT_Val         0x2u   /**< \brief (CAN_GFC) Reject */
-#define CAN_GFC_ANFS_RXF0           (CAN_GFC_ANFS_RXF0_Val         << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_ANFS_RXF1           (CAN_GFC_ANFS_RXF1_Val         << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_ANFS_REJECT         (CAN_GFC_ANFS_REJECT_Val       << CAN_GFC_ANFS_Pos)
-#define CAN_GFC_MASK                0x0000003Fu  /**< \brief (CAN_GFC) MASK Register */
-
-/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t FLSSA:16;         /*!< bit:  0..15  Filter List Standard Start Address */
-    uint32_t LSS:8;            /*!< bit: 16..23  List Size Standard                 */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_SIDFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_SIDFC_OFFSET            0x84         /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */
-#define CAN_SIDFC_RESETVALUE        0x00000000u  /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */
-
-#define CAN_SIDFC_FLSSA_Pos         0            /**< \brief (CAN_SIDFC) Filter List Standard Start Address */
-#define CAN_SIDFC_FLSSA_Msk         (0xFFFFu << CAN_SIDFC_FLSSA_Pos)
-#define CAN_SIDFC_FLSSA(value)      (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos))
-#define CAN_SIDFC_LSS_Pos           16           /**< \brief (CAN_SIDFC) List Size Standard */
-#define CAN_SIDFC_LSS_Msk           (0xFFu << CAN_SIDFC_LSS_Pos)
-#define CAN_SIDFC_LSS(value)        (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos))
-#define CAN_SIDFC_MASK              0x00FFFFFFu  /**< \brief (CAN_SIDFC) MASK Register */
-
-/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t FLESA:16;         /*!< bit:  0..15  Filter List Extended Start Address */
-    uint32_t LSE:7;            /*!< bit: 16..22  List Size Extended                 */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_XIDFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDFC_OFFSET            0x88         /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */
-#define CAN_XIDFC_RESETVALUE        0x00000000u  /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */
-
-#define CAN_XIDFC_FLESA_Pos         0            /**< \brief (CAN_XIDFC) Filter List Extended Start Address */
-#define CAN_XIDFC_FLESA_Msk         (0xFFFFu << CAN_XIDFC_FLESA_Pos)
-#define CAN_XIDFC_FLESA(value)      (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos))
-#define CAN_XIDFC_LSE_Pos           16           /**< \brief (CAN_XIDFC) List Size Extended */
-#define CAN_XIDFC_LSE_Msk           (0x7Fu << CAN_XIDFC_LSE_Pos)
-#define CAN_XIDFC_LSE(value)        (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos))
-#define CAN_XIDFC_MASK              0x007FFFFFu  /**< \brief (CAN_XIDFC) MASK Register */
-
-/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EIDM:29;          /*!< bit:  0..28  Extended ID Mask                   */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_XIDAM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDAM_OFFSET            0x90         /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */
-#define CAN_XIDAM_RESETVALUE        0x1FFFFFFFu  /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */
-
-#define CAN_XIDAM_EIDM_Pos          0            /**< \brief (CAN_XIDAM) Extended ID Mask */
-#define CAN_XIDAM_EIDM_Msk          (0x1FFFFFFFu << CAN_XIDAM_EIDM_Pos)
-#define CAN_XIDAM_EIDM(value)       (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos))
-#define CAN_XIDAM_MASK              0x1FFFFFFFu  /**< \brief (CAN_XIDAM) MASK Register */
-
-/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/  32) High Priority Message Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BIDX:6;           /*!< bit:  0.. 5  Buffer Index                       */
-    uint32_t MSI:2;            /*!< bit:  6.. 7  Message Storage Indicator          */
-    uint32_t FIDX:7;           /*!< bit:  8..14  Filter Index                       */
-    uint32_t FLST:1;           /*!< bit:     15  Filter List                        */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_HPMS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_HPMS_OFFSET             0x94         /**< \brief (CAN_HPMS offset) High Priority Message Status */
-#define CAN_HPMS_RESETVALUE         0x00000000u  /**< \brief (CAN_HPMS reset_value) High Priority Message Status */
-
-#define CAN_HPMS_BIDX_Pos           0            /**< \brief (CAN_HPMS) Buffer Index */
-#define CAN_HPMS_BIDX_Msk           (0x3Fu << CAN_HPMS_BIDX_Pos)
-#define CAN_HPMS_BIDX(value)        (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos))
-#define CAN_HPMS_MSI_Pos            6            /**< \brief (CAN_HPMS) Message Storage Indicator */
-#define CAN_HPMS_MSI_Msk            (0x3u << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI(value)         (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos))
-#define   CAN_HPMS_MSI_NONE_Val           0x0u   /**< \brief (CAN_HPMS) No FIFO selected */
-#define   CAN_HPMS_MSI_LOST_Val           0x1u   /**< \brief (CAN_HPMS) FIFO message lost */
-#define   CAN_HPMS_MSI_FIFO0_Val          0x2u   /**< \brief (CAN_HPMS) Message stored in FIFO 0 */
-#define   CAN_HPMS_MSI_FIFO1_Val          0x3u   /**< \brief (CAN_HPMS) Message stored in FIFO 1 */
-#define CAN_HPMS_MSI_NONE           (CAN_HPMS_MSI_NONE_Val         << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI_LOST           (CAN_HPMS_MSI_LOST_Val         << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI_FIFO0          (CAN_HPMS_MSI_FIFO0_Val        << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_MSI_FIFO1          (CAN_HPMS_MSI_FIFO1_Val        << CAN_HPMS_MSI_Pos)
-#define CAN_HPMS_FIDX_Pos           8            /**< \brief (CAN_HPMS) Filter Index */
-#define CAN_HPMS_FIDX_Msk           (0x7Fu << CAN_HPMS_FIDX_Pos)
-#define CAN_HPMS_FIDX(value)        (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos))
-#define CAN_HPMS_FLST_Pos           15           /**< \brief (CAN_HPMS) Filter List */
-#define CAN_HPMS_FLST               (0x1u << CAN_HPMS_FLST_Pos)
-#define CAN_HPMS_MASK               0x0000FFFFu  /**< \brief (CAN_HPMS) MASK Register */
-
-/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ND0:1;            /*!< bit:      0  New Data 0                         */
-    uint32_t ND1:1;            /*!< bit:      1  New Data 1                         */
-    uint32_t ND2:1;            /*!< bit:      2  New Data 2                         */
-    uint32_t ND3:1;            /*!< bit:      3  New Data 3                         */
-    uint32_t ND4:1;            /*!< bit:      4  New Data 4                         */
-    uint32_t ND5:1;            /*!< bit:      5  New Data 5                         */
-    uint32_t ND6:1;            /*!< bit:      6  New Data 6                         */
-    uint32_t ND7:1;            /*!< bit:      7  New Data 7                         */
-    uint32_t ND8:1;            /*!< bit:      8  New Data 8                         */
-    uint32_t ND9:1;            /*!< bit:      9  New Data 9                         */
-    uint32_t ND10:1;           /*!< bit:     10  New Data 10                        */
-    uint32_t ND11:1;           /*!< bit:     11  New Data 11                        */
-    uint32_t ND12:1;           /*!< bit:     12  New Data 12                        */
-    uint32_t ND13:1;           /*!< bit:     13  New Data 13                        */
-    uint32_t ND14:1;           /*!< bit:     14  New Data 14                        */
-    uint32_t ND15:1;           /*!< bit:     15  New Data 15                        */
-    uint32_t ND16:1;           /*!< bit:     16  New Data 16                        */
-    uint32_t ND17:1;           /*!< bit:     17  New Data 17                        */
-    uint32_t ND18:1;           /*!< bit:     18  New Data 18                        */
-    uint32_t ND19:1;           /*!< bit:     19  New Data 19                        */
-    uint32_t ND20:1;           /*!< bit:     20  New Data 20                        */
-    uint32_t ND21:1;           /*!< bit:     21  New Data 21                        */
-    uint32_t ND22:1;           /*!< bit:     22  New Data 22                        */
-    uint32_t ND23:1;           /*!< bit:     23  New Data 23                        */
-    uint32_t ND24:1;           /*!< bit:     24  New Data 24                        */
-    uint32_t ND25:1;           /*!< bit:     25  New Data 25                        */
-    uint32_t ND26:1;           /*!< bit:     26  New Data 26                        */
-    uint32_t ND27:1;           /*!< bit:     27  New Data 27                        */
-    uint32_t ND28:1;           /*!< bit:     28  New Data 28                        */
-    uint32_t ND29:1;           /*!< bit:     29  New Data 29                        */
-    uint32_t ND30:1;           /*!< bit:     30  New Data 30                        */
-    uint32_t ND31:1;           /*!< bit:     31  New Data 31                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_NDAT1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_NDAT1_OFFSET            0x98         /**< \brief (CAN_NDAT1 offset) New Data 1 */
-#define CAN_NDAT1_RESETVALUE        0x00000000u  /**< \brief (CAN_NDAT1 reset_value) New Data 1 */
-
-#define CAN_NDAT1_ND0_Pos           0            /**< \brief (CAN_NDAT1) New Data 0 */
-#define CAN_NDAT1_ND0               (0x1u << CAN_NDAT1_ND0_Pos)
-#define CAN_NDAT1_ND1_Pos           1            /**< \brief (CAN_NDAT1) New Data 1 */
-#define CAN_NDAT1_ND1               (0x1u << CAN_NDAT1_ND1_Pos)
-#define CAN_NDAT1_ND2_Pos           2            /**< \brief (CAN_NDAT1) New Data 2 */
-#define CAN_NDAT1_ND2               (0x1u << CAN_NDAT1_ND2_Pos)
-#define CAN_NDAT1_ND3_Pos           3            /**< \brief (CAN_NDAT1) New Data 3 */
-#define CAN_NDAT1_ND3               (0x1u << CAN_NDAT1_ND3_Pos)
-#define CAN_NDAT1_ND4_Pos           4            /**< \brief (CAN_NDAT1) New Data 4 */
-#define CAN_NDAT1_ND4               (0x1u << CAN_NDAT1_ND4_Pos)
-#define CAN_NDAT1_ND5_Pos           5            /**< \brief (CAN_NDAT1) New Data 5 */
-#define CAN_NDAT1_ND5               (0x1u << CAN_NDAT1_ND5_Pos)
-#define CAN_NDAT1_ND6_Pos           6            /**< \brief (CAN_NDAT1) New Data 6 */
-#define CAN_NDAT1_ND6               (0x1u << CAN_NDAT1_ND6_Pos)
-#define CAN_NDAT1_ND7_Pos           7            /**< \brief (CAN_NDAT1) New Data 7 */
-#define CAN_NDAT1_ND7               (0x1u << CAN_NDAT1_ND7_Pos)
-#define CAN_NDAT1_ND8_Pos           8            /**< \brief (CAN_NDAT1) New Data 8 */
-#define CAN_NDAT1_ND8               (0x1u << CAN_NDAT1_ND8_Pos)
-#define CAN_NDAT1_ND9_Pos           9            /**< \brief (CAN_NDAT1) New Data 9 */
-#define CAN_NDAT1_ND9               (0x1u << CAN_NDAT1_ND9_Pos)
-#define CAN_NDAT1_ND10_Pos          10           /**< \brief (CAN_NDAT1) New Data 10 */
-#define CAN_NDAT1_ND10              (0x1u << CAN_NDAT1_ND10_Pos)
-#define CAN_NDAT1_ND11_Pos          11           /**< \brief (CAN_NDAT1) New Data 11 */
-#define CAN_NDAT1_ND11              (0x1u << CAN_NDAT1_ND11_Pos)
-#define CAN_NDAT1_ND12_Pos          12           /**< \brief (CAN_NDAT1) New Data 12 */
-#define CAN_NDAT1_ND12              (0x1u << CAN_NDAT1_ND12_Pos)
-#define CAN_NDAT1_ND13_Pos          13           /**< \brief (CAN_NDAT1) New Data 13 */
-#define CAN_NDAT1_ND13              (0x1u << CAN_NDAT1_ND13_Pos)
-#define CAN_NDAT1_ND14_Pos          14           /**< \brief (CAN_NDAT1) New Data 14 */
-#define CAN_NDAT1_ND14              (0x1u << CAN_NDAT1_ND14_Pos)
-#define CAN_NDAT1_ND15_Pos          15           /**< \brief (CAN_NDAT1) New Data 15 */
-#define CAN_NDAT1_ND15              (0x1u << CAN_NDAT1_ND15_Pos)
-#define CAN_NDAT1_ND16_Pos          16           /**< \brief (CAN_NDAT1) New Data 16 */
-#define CAN_NDAT1_ND16              (0x1u << CAN_NDAT1_ND16_Pos)
-#define CAN_NDAT1_ND17_Pos          17           /**< \brief (CAN_NDAT1) New Data 17 */
-#define CAN_NDAT1_ND17              (0x1u << CAN_NDAT1_ND17_Pos)
-#define CAN_NDAT1_ND18_Pos          18           /**< \brief (CAN_NDAT1) New Data 18 */
-#define CAN_NDAT1_ND18              (0x1u << CAN_NDAT1_ND18_Pos)
-#define CAN_NDAT1_ND19_Pos          19           /**< \brief (CAN_NDAT1) New Data 19 */
-#define CAN_NDAT1_ND19              (0x1u << CAN_NDAT1_ND19_Pos)
-#define CAN_NDAT1_ND20_Pos          20           /**< \brief (CAN_NDAT1) New Data 20 */
-#define CAN_NDAT1_ND20              (0x1u << CAN_NDAT1_ND20_Pos)
-#define CAN_NDAT1_ND21_Pos          21           /**< \brief (CAN_NDAT1) New Data 21 */
-#define CAN_NDAT1_ND21              (0x1u << CAN_NDAT1_ND21_Pos)
-#define CAN_NDAT1_ND22_Pos          22           /**< \brief (CAN_NDAT1) New Data 22 */
-#define CAN_NDAT1_ND22              (0x1u << CAN_NDAT1_ND22_Pos)
-#define CAN_NDAT1_ND23_Pos          23           /**< \brief (CAN_NDAT1) New Data 23 */
-#define CAN_NDAT1_ND23              (0x1u << CAN_NDAT1_ND23_Pos)
-#define CAN_NDAT1_ND24_Pos          24           /**< \brief (CAN_NDAT1) New Data 24 */
-#define CAN_NDAT1_ND24              (0x1u << CAN_NDAT1_ND24_Pos)
-#define CAN_NDAT1_ND25_Pos          25           /**< \brief (CAN_NDAT1) New Data 25 */
-#define CAN_NDAT1_ND25              (0x1u << CAN_NDAT1_ND25_Pos)
-#define CAN_NDAT1_ND26_Pos          26           /**< \brief (CAN_NDAT1) New Data 26 */
-#define CAN_NDAT1_ND26              (0x1u << CAN_NDAT1_ND26_Pos)
-#define CAN_NDAT1_ND27_Pos          27           /**< \brief (CAN_NDAT1) New Data 27 */
-#define CAN_NDAT1_ND27              (0x1u << CAN_NDAT1_ND27_Pos)
-#define CAN_NDAT1_ND28_Pos          28           /**< \brief (CAN_NDAT1) New Data 28 */
-#define CAN_NDAT1_ND28              (0x1u << CAN_NDAT1_ND28_Pos)
-#define CAN_NDAT1_ND29_Pos          29           /**< \brief (CAN_NDAT1) New Data 29 */
-#define CAN_NDAT1_ND29              (0x1u << CAN_NDAT1_ND29_Pos)
-#define CAN_NDAT1_ND30_Pos          30           /**< \brief (CAN_NDAT1) New Data 30 */
-#define CAN_NDAT1_ND30              (0x1u << CAN_NDAT1_ND30_Pos)
-#define CAN_NDAT1_ND31_Pos          31           /**< \brief (CAN_NDAT1) New Data 31 */
-#define CAN_NDAT1_ND31              (0x1u << CAN_NDAT1_ND31_Pos)
-#define CAN_NDAT1_MASK              0xFFFFFFFFu  /**< \brief (CAN_NDAT1) MASK Register */
-
-/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ND32:1;           /*!< bit:      0  New Data 32                        */
-    uint32_t ND33:1;           /*!< bit:      1  New Data 33                        */
-    uint32_t ND34:1;           /*!< bit:      2  New Data 34                        */
-    uint32_t ND35:1;           /*!< bit:      3  New Data 35                        */
-    uint32_t ND36:1;           /*!< bit:      4  New Data 36                        */
-    uint32_t ND37:1;           /*!< bit:      5  New Data 37                        */
-    uint32_t ND38:1;           /*!< bit:      6  New Data 38                        */
-    uint32_t ND39:1;           /*!< bit:      7  New Data 39                        */
-    uint32_t ND40:1;           /*!< bit:      8  New Data 40                        */
-    uint32_t ND41:1;           /*!< bit:      9  New Data 41                        */
-    uint32_t ND42:1;           /*!< bit:     10  New Data 42                        */
-    uint32_t ND43:1;           /*!< bit:     11  New Data 43                        */
-    uint32_t ND44:1;           /*!< bit:     12  New Data 44                        */
-    uint32_t ND45:1;           /*!< bit:     13  New Data 45                        */
-    uint32_t ND46:1;           /*!< bit:     14  New Data 46                        */
-    uint32_t ND47:1;           /*!< bit:     15  New Data 47                        */
-    uint32_t ND48:1;           /*!< bit:     16  New Data 48                        */
-    uint32_t ND49:1;           /*!< bit:     17  New Data 49                        */
-    uint32_t ND50:1;           /*!< bit:     18  New Data 50                        */
-    uint32_t ND51:1;           /*!< bit:     19  New Data 51                        */
-    uint32_t ND52:1;           /*!< bit:     20  New Data 52                        */
-    uint32_t ND53:1;           /*!< bit:     21  New Data 53                        */
-    uint32_t ND54:1;           /*!< bit:     22  New Data 54                        */
-    uint32_t ND55:1;           /*!< bit:     23  New Data 55                        */
-    uint32_t ND56:1;           /*!< bit:     24  New Data 56                        */
-    uint32_t ND57:1;           /*!< bit:     25  New Data 57                        */
-    uint32_t ND58:1;           /*!< bit:     26  New Data 58                        */
-    uint32_t ND59:1;           /*!< bit:     27  New Data 59                        */
-    uint32_t ND60:1;           /*!< bit:     28  New Data 60                        */
-    uint32_t ND61:1;           /*!< bit:     29  New Data 61                        */
-    uint32_t ND62:1;           /*!< bit:     30  New Data 62                        */
-    uint32_t ND63:1;           /*!< bit:     31  New Data 63                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_NDAT2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_NDAT2_OFFSET            0x9C         /**< \brief (CAN_NDAT2 offset) New Data 2 */
-#define CAN_NDAT2_RESETVALUE        0x00000000u  /**< \brief (CAN_NDAT2 reset_value) New Data 2 */
-
-#define CAN_NDAT2_ND32_Pos          0            /**< \brief (CAN_NDAT2) New Data 32 */
-#define CAN_NDAT2_ND32              (0x1u << CAN_NDAT2_ND32_Pos)
-#define CAN_NDAT2_ND33_Pos          1            /**< \brief (CAN_NDAT2) New Data 33 */
-#define CAN_NDAT2_ND33              (0x1u << CAN_NDAT2_ND33_Pos)
-#define CAN_NDAT2_ND34_Pos          2            /**< \brief (CAN_NDAT2) New Data 34 */
-#define CAN_NDAT2_ND34              (0x1u << CAN_NDAT2_ND34_Pos)
-#define CAN_NDAT2_ND35_Pos          3            /**< \brief (CAN_NDAT2) New Data 35 */
-#define CAN_NDAT2_ND35              (0x1u << CAN_NDAT2_ND35_Pos)
-#define CAN_NDAT2_ND36_Pos          4            /**< \brief (CAN_NDAT2) New Data 36 */
-#define CAN_NDAT2_ND36              (0x1u << CAN_NDAT2_ND36_Pos)
-#define CAN_NDAT2_ND37_Pos          5            /**< \brief (CAN_NDAT2) New Data 37 */
-#define CAN_NDAT2_ND37              (0x1u << CAN_NDAT2_ND37_Pos)
-#define CAN_NDAT2_ND38_Pos          6            /**< \brief (CAN_NDAT2) New Data 38 */
-#define CAN_NDAT2_ND38              (0x1u << CAN_NDAT2_ND38_Pos)
-#define CAN_NDAT2_ND39_Pos          7            /**< \brief (CAN_NDAT2) New Data 39 */
-#define CAN_NDAT2_ND39              (0x1u << CAN_NDAT2_ND39_Pos)
-#define CAN_NDAT2_ND40_Pos          8            /**< \brief (CAN_NDAT2) New Data 40 */
-#define CAN_NDAT2_ND40              (0x1u << CAN_NDAT2_ND40_Pos)
-#define CAN_NDAT2_ND41_Pos          9            /**< \brief (CAN_NDAT2) New Data 41 */
-#define CAN_NDAT2_ND41              (0x1u << CAN_NDAT2_ND41_Pos)
-#define CAN_NDAT2_ND42_Pos          10           /**< \brief (CAN_NDAT2) New Data 42 */
-#define CAN_NDAT2_ND42              (0x1u << CAN_NDAT2_ND42_Pos)
-#define CAN_NDAT2_ND43_Pos          11           /**< \brief (CAN_NDAT2) New Data 43 */
-#define CAN_NDAT2_ND43              (0x1u << CAN_NDAT2_ND43_Pos)
-#define CAN_NDAT2_ND44_Pos          12           /**< \brief (CAN_NDAT2) New Data 44 */
-#define CAN_NDAT2_ND44              (0x1u << CAN_NDAT2_ND44_Pos)
-#define CAN_NDAT2_ND45_Pos          13           /**< \brief (CAN_NDAT2) New Data 45 */
-#define CAN_NDAT2_ND45              (0x1u << CAN_NDAT2_ND45_Pos)
-#define CAN_NDAT2_ND46_Pos          14           /**< \brief (CAN_NDAT2) New Data 46 */
-#define CAN_NDAT2_ND46              (0x1u << CAN_NDAT2_ND46_Pos)
-#define CAN_NDAT2_ND47_Pos          15           /**< \brief (CAN_NDAT2) New Data 47 */
-#define CAN_NDAT2_ND47              (0x1u << CAN_NDAT2_ND47_Pos)
-#define CAN_NDAT2_ND48_Pos          16           /**< \brief (CAN_NDAT2) New Data 48 */
-#define CAN_NDAT2_ND48              (0x1u << CAN_NDAT2_ND48_Pos)
-#define CAN_NDAT2_ND49_Pos          17           /**< \brief (CAN_NDAT2) New Data 49 */
-#define CAN_NDAT2_ND49              (0x1u << CAN_NDAT2_ND49_Pos)
-#define CAN_NDAT2_ND50_Pos          18           /**< \brief (CAN_NDAT2) New Data 50 */
-#define CAN_NDAT2_ND50              (0x1u << CAN_NDAT2_ND50_Pos)
-#define CAN_NDAT2_ND51_Pos          19           /**< \brief (CAN_NDAT2) New Data 51 */
-#define CAN_NDAT2_ND51              (0x1u << CAN_NDAT2_ND51_Pos)
-#define CAN_NDAT2_ND52_Pos          20           /**< \brief (CAN_NDAT2) New Data 52 */
-#define CAN_NDAT2_ND52              (0x1u << CAN_NDAT2_ND52_Pos)
-#define CAN_NDAT2_ND53_Pos          21           /**< \brief (CAN_NDAT2) New Data 53 */
-#define CAN_NDAT2_ND53              (0x1u << CAN_NDAT2_ND53_Pos)
-#define CAN_NDAT2_ND54_Pos          22           /**< \brief (CAN_NDAT2) New Data 54 */
-#define CAN_NDAT2_ND54              (0x1u << CAN_NDAT2_ND54_Pos)
-#define CAN_NDAT2_ND55_Pos          23           /**< \brief (CAN_NDAT2) New Data 55 */
-#define CAN_NDAT2_ND55              (0x1u << CAN_NDAT2_ND55_Pos)
-#define CAN_NDAT2_ND56_Pos          24           /**< \brief (CAN_NDAT2) New Data 56 */
-#define CAN_NDAT2_ND56              (0x1u << CAN_NDAT2_ND56_Pos)
-#define CAN_NDAT2_ND57_Pos          25           /**< \brief (CAN_NDAT2) New Data 57 */
-#define CAN_NDAT2_ND57              (0x1u << CAN_NDAT2_ND57_Pos)
-#define CAN_NDAT2_ND58_Pos          26           /**< \brief (CAN_NDAT2) New Data 58 */
-#define CAN_NDAT2_ND58              (0x1u << CAN_NDAT2_ND58_Pos)
-#define CAN_NDAT2_ND59_Pos          27           /**< \brief (CAN_NDAT2) New Data 59 */
-#define CAN_NDAT2_ND59              (0x1u << CAN_NDAT2_ND59_Pos)
-#define CAN_NDAT2_ND60_Pos          28           /**< \brief (CAN_NDAT2) New Data 60 */
-#define CAN_NDAT2_ND60              (0x1u << CAN_NDAT2_ND60_Pos)
-#define CAN_NDAT2_ND61_Pos          29           /**< \brief (CAN_NDAT2) New Data 61 */
-#define CAN_NDAT2_ND61              (0x1u << CAN_NDAT2_ND61_Pos)
-#define CAN_NDAT2_ND62_Pos          30           /**< \brief (CAN_NDAT2) New Data 62 */
-#define CAN_NDAT2_ND62              (0x1u << CAN_NDAT2_ND62_Pos)
-#define CAN_NDAT2_ND63_Pos          31           /**< \brief (CAN_NDAT2) New Data 63 */
-#define CAN_NDAT2_ND63              (0x1u << CAN_NDAT2_ND63_Pos)
-#define CAN_NDAT2_MASK              0xFFFFFFFFu  /**< \brief (CAN_NDAT2) MASK Register */
-
-/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t F0SA:16;          /*!< bit:  0..15  Rx FIFO 0 Start Address            */
-    uint32_t F0S:7;            /*!< bit: 16..22  Rx FIFO 0 Size                     */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t F0WM:7;           /*!< bit: 24..30  Rx FIFO 0 Watermark                */
-    uint32_t F0OM:1;           /*!< bit:     31  FIFO 0 Operation Mode              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF0C_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0C_OFFSET            0xA0         /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */
-#define CAN_RXF0C_RESETVALUE        0x00000000u  /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */
-
-#define CAN_RXF0C_F0SA_Pos          0            /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */
-#define CAN_RXF0C_F0SA_Msk          (0xFFFFu << CAN_RXF0C_F0SA_Pos)
-#define CAN_RXF0C_F0SA(value)       (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos))
-#define CAN_RXF0C_F0S_Pos           16           /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */
-#define CAN_RXF0C_F0S_Msk           (0x7Fu << CAN_RXF0C_F0S_Pos)
-#define CAN_RXF0C_F0S(value)        (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos))
-#define CAN_RXF0C_F0WM_Pos          24           /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */
-#define CAN_RXF0C_F0WM_Msk          (0x7Fu << CAN_RXF0C_F0WM_Pos)
-#define CAN_RXF0C_F0WM(value)       (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos))
-#define CAN_RXF0C_F0OM_Pos          31           /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */
-#define CAN_RXF0C_F0OM              (0x1u << CAN_RXF0C_F0OM_Pos)
-#define CAN_RXF0C_MASK              0xFF7FFFFFu  /**< \brief (CAN_RXF0C) MASK Register */
-
-/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/  32) Rx FIFO 0 Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t F0FL:7;           /*!< bit:  0.. 6  Rx FIFO 0 Fill Level               */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t F0GI:6;           /*!< bit:  8..13  Rx FIFO 0 Get Index                */
-    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
-    uint32_t F0PI:6;           /*!< bit: 16..21  Rx FIFO 0 Put Index                */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t F0F:1;            /*!< bit:     24  Rx FIFO 0 Full                     */
-    uint32_t RF0L:1;           /*!< bit:     25  Rx FIFO 0 Message Lost             */
-    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF0S_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0S_OFFSET            0xA4         /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */
-#define CAN_RXF0S_RESETVALUE        0x00000000u  /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */
-
-#define CAN_RXF0S_F0FL_Pos          0            /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */
-#define CAN_RXF0S_F0FL_Msk          (0x7Fu << CAN_RXF0S_F0FL_Pos)
-#define CAN_RXF0S_F0FL(value)       (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos))
-#define CAN_RXF0S_F0GI_Pos          8            /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */
-#define CAN_RXF0S_F0GI_Msk          (0x3Fu << CAN_RXF0S_F0GI_Pos)
-#define CAN_RXF0S_F0GI(value)       (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos))
-#define CAN_RXF0S_F0PI_Pos          16           /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */
-#define CAN_RXF0S_F0PI_Msk          (0x3Fu << CAN_RXF0S_F0PI_Pos)
-#define CAN_RXF0S_F0PI(value)       (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos))
-#define CAN_RXF0S_F0F_Pos           24           /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */
-#define CAN_RXF0S_F0F               (0x1u << CAN_RXF0S_F0F_Pos)
-#define CAN_RXF0S_RF0L_Pos          25           /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */
-#define CAN_RXF0S_RF0L              (0x1u << CAN_RXF0S_RF0L_Pos)
-#define CAN_RXF0S_MASK              0x033F3F7Fu  /**< \brief (CAN_RXF0S) MASK Register */
-
-/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t F0AI:6;           /*!< bit:  0.. 5  Rx FIFO 0 Acknowledge Index        */
-    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF0A_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0A_OFFSET            0xA8         /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */
-#define CAN_RXF0A_RESETVALUE        0x00000000u  /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */
-
-#define CAN_RXF0A_F0AI_Pos          0            /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */
-#define CAN_RXF0A_F0AI_Msk          (0x3Fu << CAN_RXF0A_F0AI_Pos)
-#define CAN_RXF0A_F0AI(value)       (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos))
-#define CAN_RXF0A_MASK              0x0000003Fu  /**< \brief (CAN_RXF0A) MASK Register */
-
-/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RBSA:16;          /*!< bit:  0..15  Rx Buffer Start Address            */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXBC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBC_OFFSET             0xAC         /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */
-#define CAN_RXBC_RESETVALUE         0x00000000u  /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */
-
-#define CAN_RXBC_RBSA_Pos           0            /**< \brief (CAN_RXBC) Rx Buffer Start Address */
-#define CAN_RXBC_RBSA_Msk           (0xFFFFu << CAN_RXBC_RBSA_Pos)
-#define CAN_RXBC_RBSA(value)        (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos))
-#define CAN_RXBC_MASK               0x0000FFFFu  /**< \brief (CAN_RXBC) MASK Register */
-
-/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t F1SA:16;          /*!< bit:  0..15  Rx FIFO 1 Start Address            */
-    uint32_t F1S:7;            /*!< bit: 16..22  Rx FIFO 1 Size                     */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t F1WM:7;           /*!< bit: 24..30  Rx FIFO 1 Watermark                */
-    uint32_t F1OM:1;           /*!< bit:     31  FIFO 1 Operation Mode              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF1C_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1C_OFFSET            0xB0         /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */
-#define CAN_RXF1C_RESETVALUE        0x00000000u  /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */
-
-#define CAN_RXF1C_F1SA_Pos          0            /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */
-#define CAN_RXF1C_F1SA_Msk          (0xFFFFu << CAN_RXF1C_F1SA_Pos)
-#define CAN_RXF1C_F1SA(value)       (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos))
-#define CAN_RXF1C_F1S_Pos           16           /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */
-#define CAN_RXF1C_F1S_Msk           (0x7Fu << CAN_RXF1C_F1S_Pos)
-#define CAN_RXF1C_F1S(value)        (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos))
-#define CAN_RXF1C_F1WM_Pos          24           /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */
-#define CAN_RXF1C_F1WM_Msk          (0x7Fu << CAN_RXF1C_F1WM_Pos)
-#define CAN_RXF1C_F1WM(value)       (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos))
-#define CAN_RXF1C_F1OM_Pos          31           /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */
-#define CAN_RXF1C_F1OM              (0x1u << CAN_RXF1C_F1OM_Pos)
-#define CAN_RXF1C_MASK              0xFF7FFFFFu  /**< \brief (CAN_RXF1C) MASK Register */
-
-/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/  32) Rx FIFO 1 Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t F1FL:7;           /*!< bit:  0.. 6  Rx FIFO 1 Fill Level               */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t F1GI:6;           /*!< bit:  8..13  Rx FIFO 1 Get Index                */
-    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
-    uint32_t F1PI:6;           /*!< bit: 16..21  Rx FIFO 1 Put Index                */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t F1F:1;            /*!< bit:     24  Rx FIFO 1 Full                     */
-    uint32_t RF1L:1;           /*!< bit:     25  Rx FIFO 1 Message Lost             */
-    uint32_t :4;               /*!< bit: 26..29  Reserved                           */
-    uint32_t DMS:2;            /*!< bit: 30..31  Debug Message Status               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF1S_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1S_OFFSET            0xB4         /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */
-#define CAN_RXF1S_RESETVALUE        0x00000000u  /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */
-
-#define CAN_RXF1S_F1FL_Pos          0            /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */
-#define CAN_RXF1S_F1FL_Msk          (0x7Fu << CAN_RXF1S_F1FL_Pos)
-#define CAN_RXF1S_F1FL(value)       (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos))
-#define CAN_RXF1S_F1GI_Pos          8            /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */
-#define CAN_RXF1S_F1GI_Msk          (0x3Fu << CAN_RXF1S_F1GI_Pos)
-#define CAN_RXF1S_F1GI(value)       (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos))
-#define CAN_RXF1S_F1PI_Pos          16           /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */
-#define CAN_RXF1S_F1PI_Msk          (0x3Fu << CAN_RXF1S_F1PI_Pos)
-#define CAN_RXF1S_F1PI(value)       (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos))
-#define CAN_RXF1S_F1F_Pos           24           /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */
-#define CAN_RXF1S_F1F               (0x1u << CAN_RXF1S_F1F_Pos)
-#define CAN_RXF1S_RF1L_Pos          25           /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */
-#define CAN_RXF1S_RF1L              (0x1u << CAN_RXF1S_RF1L_Pos)
-#define CAN_RXF1S_DMS_Pos           30           /**< \brief (CAN_RXF1S) Debug Message Status */
-#define CAN_RXF1S_DMS_Msk           (0x3u << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS(value)        (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos))
-#define   CAN_RXF1S_DMS_IDLE_Val          0x0u   /**< \brief (CAN_RXF1S) Idle state */
-#define   CAN_RXF1S_DMS_DBGA_Val          0x1u   /**< \brief (CAN_RXF1S) Debug message A received */
-#define   CAN_RXF1S_DMS_DBGB_Val          0x2u   /**< \brief (CAN_RXF1S) Debug message A/B received */
-#define   CAN_RXF1S_DMS_DBGC_Val          0x3u   /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */
-#define CAN_RXF1S_DMS_IDLE          (CAN_RXF1S_DMS_IDLE_Val        << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS_DBGA          (CAN_RXF1S_DMS_DBGA_Val        << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS_DBGB          (CAN_RXF1S_DMS_DBGB_Val        << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_DMS_DBGC          (CAN_RXF1S_DMS_DBGC_Val        << CAN_RXF1S_DMS_Pos)
-#define CAN_RXF1S_MASK              0xC33F3F7Fu  /**< \brief (CAN_RXF1S) MASK Register */
-
-/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t F1AI:6;           /*!< bit:  0.. 5  Rx FIFO 1 Acknowledge Index        */
-    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF1A_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1A_OFFSET            0xB8         /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */
-#define CAN_RXF1A_RESETVALUE        0x00000000u  /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */
-
-#define CAN_RXF1A_F1AI_Pos          0            /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */
-#define CAN_RXF1A_F1AI_Msk          (0x3Fu << CAN_RXF1A_F1AI_Pos)
-#define CAN_RXF1A_F1AI(value)       (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos))
-#define CAN_RXF1A_MASK              0x0000003Fu  /**< \brief (CAN_RXF1A) MASK Register */
-
-/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t F0DS:3;           /*!< bit:  0.. 2  Rx FIFO 0 Data Field Size          */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t F1DS:3;           /*!< bit:  4.. 6  Rx FIFO 1 Data Field Size          */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t RBDS:3;           /*!< bit:  8..10  Rx Buffer Data Field Size          */
-    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXESC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXESC_OFFSET            0xBC         /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */
-#define CAN_RXESC_RESETVALUE        0x00000000u  /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */
-
-#define CAN_RXESC_F0DS_Pos          0            /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */
-#define CAN_RXESC_F0DS_Msk          (0x7u << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS(value)       (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos))
-#define   CAN_RXESC_F0DS_DATA8_Val        0x0u   /**< \brief (CAN_RXESC) 8 byte data field */
-#define   CAN_RXESC_F0DS_DATA12_Val       0x1u   /**< \brief (CAN_RXESC) 12 byte data field */
-#define   CAN_RXESC_F0DS_DATA16_Val       0x2u   /**< \brief (CAN_RXESC) 16 byte data field */
-#define   CAN_RXESC_F0DS_DATA20_Val       0x3u   /**< \brief (CAN_RXESC) 20 byte data field */
-#define   CAN_RXESC_F0DS_DATA24_Val       0x4u   /**< \brief (CAN_RXESC) 24 byte data field */
-#define   CAN_RXESC_F0DS_DATA32_Val       0x5u   /**< \brief (CAN_RXESC) 32 byte data field */
-#define   CAN_RXESC_F0DS_DATA48_Val       0x6u   /**< \brief (CAN_RXESC) 48 byte data field */
-#define   CAN_RXESC_F0DS_DATA64_Val       0x7u   /**< \brief (CAN_RXESC) 64 byte data field */
-#define CAN_RXESC_F0DS_DATA8        (CAN_RXESC_F0DS_DATA8_Val      << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA12       (CAN_RXESC_F0DS_DATA12_Val     << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA16       (CAN_RXESC_F0DS_DATA16_Val     << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA20       (CAN_RXESC_F0DS_DATA20_Val     << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA24       (CAN_RXESC_F0DS_DATA24_Val     << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA32       (CAN_RXESC_F0DS_DATA32_Val     << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA48       (CAN_RXESC_F0DS_DATA48_Val     << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F0DS_DATA64       (CAN_RXESC_F0DS_DATA64_Val     << CAN_RXESC_F0DS_Pos)
-#define CAN_RXESC_F1DS_Pos          4            /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */
-#define CAN_RXESC_F1DS_Msk          (0x7u << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS(value)       (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos))
-#define   CAN_RXESC_F1DS_DATA8_Val        0x0u   /**< \brief (CAN_RXESC) 8 byte data field */
-#define   CAN_RXESC_F1DS_DATA12_Val       0x1u   /**< \brief (CAN_RXESC) 12 byte data field */
-#define   CAN_RXESC_F1DS_DATA16_Val       0x2u   /**< \brief (CAN_RXESC) 16 byte data field */
-#define   CAN_RXESC_F1DS_DATA20_Val       0x3u   /**< \brief (CAN_RXESC) 20 byte data field */
-#define   CAN_RXESC_F1DS_DATA24_Val       0x4u   /**< \brief (CAN_RXESC) 24 byte data field */
-#define   CAN_RXESC_F1DS_DATA32_Val       0x5u   /**< \brief (CAN_RXESC) 32 byte data field */
-#define   CAN_RXESC_F1DS_DATA48_Val       0x6u   /**< \brief (CAN_RXESC) 48 byte data field */
-#define   CAN_RXESC_F1DS_DATA64_Val       0x7u   /**< \brief (CAN_RXESC) 64 byte data field */
-#define CAN_RXESC_F1DS_DATA8        (CAN_RXESC_F1DS_DATA8_Val      << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA12       (CAN_RXESC_F1DS_DATA12_Val     << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA16       (CAN_RXESC_F1DS_DATA16_Val     << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA20       (CAN_RXESC_F1DS_DATA20_Val     << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA24       (CAN_RXESC_F1DS_DATA24_Val     << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA32       (CAN_RXESC_F1DS_DATA32_Val     << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA48       (CAN_RXESC_F1DS_DATA48_Val     << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_F1DS_DATA64       (CAN_RXESC_F1DS_DATA64_Val     << CAN_RXESC_F1DS_Pos)
-#define CAN_RXESC_RBDS_Pos          8            /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */
-#define CAN_RXESC_RBDS_Msk          (0x7u << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS(value)       (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos))
-#define   CAN_RXESC_RBDS_DATA8_Val        0x0u   /**< \brief (CAN_RXESC) 8 byte data field */
-#define   CAN_RXESC_RBDS_DATA12_Val       0x1u   /**< \brief (CAN_RXESC) 12 byte data field */
-#define   CAN_RXESC_RBDS_DATA16_Val       0x2u   /**< \brief (CAN_RXESC) 16 byte data field */
-#define   CAN_RXESC_RBDS_DATA20_Val       0x3u   /**< \brief (CAN_RXESC) 20 byte data field */
-#define   CAN_RXESC_RBDS_DATA24_Val       0x4u   /**< \brief (CAN_RXESC) 24 byte data field */
-#define   CAN_RXESC_RBDS_DATA32_Val       0x5u   /**< \brief (CAN_RXESC) 32 byte data field */
-#define   CAN_RXESC_RBDS_DATA48_Val       0x6u   /**< \brief (CAN_RXESC) 48 byte data field */
-#define   CAN_RXESC_RBDS_DATA64_Val       0x7u   /**< \brief (CAN_RXESC) 64 byte data field */
-#define CAN_RXESC_RBDS_DATA8        (CAN_RXESC_RBDS_DATA8_Val      << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA12       (CAN_RXESC_RBDS_DATA12_Val     << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA16       (CAN_RXESC_RBDS_DATA16_Val     << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA20       (CAN_RXESC_RBDS_DATA20_Val     << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA24       (CAN_RXESC_RBDS_DATA24_Val     << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA32       (CAN_RXESC_RBDS_DATA32_Val     << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA48       (CAN_RXESC_RBDS_DATA48_Val     << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_RBDS_DATA64       (CAN_RXESC_RBDS_DATA64_Val     << CAN_RXESC_RBDS_Pos)
-#define CAN_RXESC_MASK              0x00000777u  /**< \brief (CAN_RXESC) MASK Register */
-
-/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TBSA:16;          /*!< bit:  0..15  Tx Buffers Start Address           */
-    uint32_t NDTB:6;           /*!< bit: 16..21  Number of Dedicated Transmit Buffers */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t TFQS:6;           /*!< bit: 24..29  Transmit FIFO/Queue Size           */
-    uint32_t TFQM:1;           /*!< bit:     30  Tx FIFO/Queue Mode                 */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBC_OFFSET             0xC0         /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */
-#define CAN_TXBC_RESETVALUE         0x00000000u  /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */
-
-#define CAN_TXBC_TBSA_Pos           0            /**< \brief (CAN_TXBC) Tx Buffers Start Address */
-#define CAN_TXBC_TBSA_Msk           (0xFFFFu << CAN_TXBC_TBSA_Pos)
-#define CAN_TXBC_TBSA(value)        (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos))
-#define CAN_TXBC_NDTB_Pos           16           /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */
-#define CAN_TXBC_NDTB_Msk           (0x3Fu << CAN_TXBC_NDTB_Pos)
-#define CAN_TXBC_NDTB(value)        (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos))
-#define CAN_TXBC_TFQS_Pos           24           /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */
-#define CAN_TXBC_TFQS_Msk           (0x3Fu << CAN_TXBC_TFQS_Pos)
-#define CAN_TXBC_TFQS(value)        (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos))
-#define CAN_TXBC_TFQM_Pos           30           /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */
-#define CAN_TXBC_TFQM               (0x1u << CAN_TXBC_TFQM_Pos)
-#define CAN_TXBC_MASK               0x7F3FFFFFu  /**< \brief (CAN_TXBC) MASK Register */
-
-/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/  32) Tx FIFO / Queue Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TFFL:6;           /*!< bit:  0.. 5  Tx FIFO Free Level                 */
-    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint32_t TFGI:5;           /*!< bit:  8..12  Tx FIFO Get Index                  */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t TFQPI:5;          /*!< bit: 16..20  Tx FIFO/Queue Put Index            */
-    uint32_t TFQF:1;           /*!< bit:     21  Tx FIFO/Queue Full                 */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXFQS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXFQS_OFFSET            0xC4         /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */
-#define CAN_TXFQS_RESETVALUE        0x00000000u  /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */
-
-#define CAN_TXFQS_TFFL_Pos          0            /**< \brief (CAN_TXFQS) Tx FIFO Free Level */
-#define CAN_TXFQS_TFFL_Msk          (0x3Fu << CAN_TXFQS_TFFL_Pos)
-#define CAN_TXFQS_TFFL(value)       (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos))
-#define CAN_TXFQS_TFGI_Pos          8            /**< \brief (CAN_TXFQS) Tx FIFO Get Index */
-#define CAN_TXFQS_TFGI_Msk          (0x1Fu << CAN_TXFQS_TFGI_Pos)
-#define CAN_TXFQS_TFGI(value)       (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos))
-#define CAN_TXFQS_TFQPI_Pos         16           /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */
-#define CAN_TXFQS_TFQPI_Msk         (0x1Fu << CAN_TXFQS_TFQPI_Pos)
-#define CAN_TXFQS_TFQPI(value)      (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos))
-#define CAN_TXFQS_TFQF_Pos          21           /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */
-#define CAN_TXFQS_TFQF              (0x1u << CAN_TXFQS_TFQF_Pos)
-#define CAN_TXFQS_MASK              0x003F1F3Fu  /**< \brief (CAN_TXFQS) MASK Register */
-
-/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TBDS:3;           /*!< bit:  0.. 2  Tx Buffer Data Field Size          */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXESC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXESC_OFFSET            0xC8         /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */
-#define CAN_TXESC_RESETVALUE        0x00000000u  /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */
-
-#define CAN_TXESC_TBDS_Pos          0            /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */
-#define CAN_TXESC_TBDS_Msk          (0x7u << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS(value)       (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos))
-#define   CAN_TXESC_TBDS_DATA8_Val        0x0u   /**< \brief (CAN_TXESC) 8 byte data field */
-#define   CAN_TXESC_TBDS_DATA12_Val       0x1u   /**< \brief (CAN_TXESC) 12 byte data field */
-#define   CAN_TXESC_TBDS_DATA16_Val       0x2u   /**< \brief (CAN_TXESC) 16 byte data field */
-#define   CAN_TXESC_TBDS_DATA20_Val       0x3u   /**< \brief (CAN_TXESC) 20 byte data field */
-#define   CAN_TXESC_TBDS_DATA24_Val       0x4u   /**< \brief (CAN_TXESC) 24 byte data field */
-#define   CAN_TXESC_TBDS_DATA32_Val       0x5u   /**< \brief (CAN_TXESC) 32 byte data field */
-#define   CAN_TXESC_TBDS_DATA48_Val       0x6u   /**< \brief (CAN_TXESC) 48 byte data field */
-#define   CAN_TXESC_TBDS_DATA64_Val       0x7u   /**< \brief (CAN_TXESC) 64 byte data field */
-#define CAN_TXESC_TBDS_DATA8        (CAN_TXESC_TBDS_DATA8_Val      << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA12       (CAN_TXESC_TBDS_DATA12_Val     << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA16       (CAN_TXESC_TBDS_DATA16_Val     << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA20       (CAN_TXESC_TBDS_DATA20_Val     << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA24       (CAN_TXESC_TBDS_DATA24_Val     << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA32       (CAN_TXESC_TBDS_DATA32_Val     << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA48       (CAN_TXESC_TBDS_DATA48_Val     << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_TBDS_DATA64       (CAN_TXESC_TBDS_DATA64_Val     << CAN_TXESC_TBDS_Pos)
-#define CAN_TXESC_MASK              0x00000007u  /**< \brief (CAN_TXESC) MASK Register */
-
-/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/  32) Tx Buffer Request Pending -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TRP0:1;           /*!< bit:      0  Transmission Request Pending 0     */
-    uint32_t TRP1:1;           /*!< bit:      1  Transmission Request Pending 1     */
-    uint32_t TRP2:1;           /*!< bit:      2  Transmission Request Pending 2     */
-    uint32_t TRP3:1;           /*!< bit:      3  Transmission Request Pending 3     */
-    uint32_t TRP4:1;           /*!< bit:      4  Transmission Request Pending 4     */
-    uint32_t TRP5:1;           /*!< bit:      5  Transmission Request Pending 5     */
-    uint32_t TRP6:1;           /*!< bit:      6  Transmission Request Pending 6     */
-    uint32_t TRP7:1;           /*!< bit:      7  Transmission Request Pending 7     */
-    uint32_t TRP8:1;           /*!< bit:      8  Transmission Request Pending 8     */
-    uint32_t TRP9:1;           /*!< bit:      9  Transmission Request Pending 9     */
-    uint32_t TRP10:1;          /*!< bit:     10  Transmission Request Pending 10    */
-    uint32_t TRP11:1;          /*!< bit:     11  Transmission Request Pending 11    */
-    uint32_t TRP12:1;          /*!< bit:     12  Transmission Request Pending 12    */
-    uint32_t TRP13:1;          /*!< bit:     13  Transmission Request Pending 13    */
-    uint32_t TRP14:1;          /*!< bit:     14  Transmission Request Pending 14    */
-    uint32_t TRP15:1;          /*!< bit:     15  Transmission Request Pending 15    */
-    uint32_t TRP16:1;          /*!< bit:     16  Transmission Request Pending 16    */
-    uint32_t TRP17:1;          /*!< bit:     17  Transmission Request Pending 17    */
-    uint32_t TRP18:1;          /*!< bit:     18  Transmission Request Pending 18    */
-    uint32_t TRP19:1;          /*!< bit:     19  Transmission Request Pending 19    */
-    uint32_t TRP20:1;          /*!< bit:     20  Transmission Request Pending 20    */
-    uint32_t TRP21:1;          /*!< bit:     21  Transmission Request Pending 21    */
-    uint32_t TRP22:1;          /*!< bit:     22  Transmission Request Pending 22    */
-    uint32_t TRP23:1;          /*!< bit:     23  Transmission Request Pending 23    */
-    uint32_t TRP24:1;          /*!< bit:     24  Transmission Request Pending 24    */
-    uint32_t TRP25:1;          /*!< bit:     25  Transmission Request Pending 25    */
-    uint32_t TRP26:1;          /*!< bit:     26  Transmission Request Pending 26    */
-    uint32_t TRP27:1;          /*!< bit:     27  Transmission Request Pending 27    */
-    uint32_t TRP28:1;          /*!< bit:     28  Transmission Request Pending 28    */
-    uint32_t TRP29:1;          /*!< bit:     29  Transmission Request Pending 29    */
-    uint32_t TRP30:1;          /*!< bit:     30  Transmission Request Pending 30    */
-    uint32_t TRP31:1;          /*!< bit:     31  Transmission Request Pending 31    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBRP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBRP_OFFSET            0xCC         /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */
-#define CAN_TXBRP_RESETVALUE        0x00000000u  /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */
-
-#define CAN_TXBRP_TRP0_Pos          0            /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */
-#define CAN_TXBRP_TRP0              (0x1u << CAN_TXBRP_TRP0_Pos)
-#define CAN_TXBRP_TRP1_Pos          1            /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */
-#define CAN_TXBRP_TRP1              (0x1u << CAN_TXBRP_TRP1_Pos)
-#define CAN_TXBRP_TRP2_Pos          2            /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */
-#define CAN_TXBRP_TRP2              (0x1u << CAN_TXBRP_TRP2_Pos)
-#define CAN_TXBRP_TRP3_Pos          3            /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */
-#define CAN_TXBRP_TRP3              (0x1u << CAN_TXBRP_TRP3_Pos)
-#define CAN_TXBRP_TRP4_Pos          4            /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */
-#define CAN_TXBRP_TRP4              (0x1u << CAN_TXBRP_TRP4_Pos)
-#define CAN_TXBRP_TRP5_Pos          5            /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */
-#define CAN_TXBRP_TRP5              (0x1u << CAN_TXBRP_TRP5_Pos)
-#define CAN_TXBRP_TRP6_Pos          6            /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */
-#define CAN_TXBRP_TRP6              (0x1u << CAN_TXBRP_TRP6_Pos)
-#define CAN_TXBRP_TRP7_Pos          7            /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */
-#define CAN_TXBRP_TRP7              (0x1u << CAN_TXBRP_TRP7_Pos)
-#define CAN_TXBRP_TRP8_Pos          8            /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */
-#define CAN_TXBRP_TRP8              (0x1u << CAN_TXBRP_TRP8_Pos)
-#define CAN_TXBRP_TRP9_Pos          9            /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */
-#define CAN_TXBRP_TRP9              (0x1u << CAN_TXBRP_TRP9_Pos)
-#define CAN_TXBRP_TRP10_Pos         10           /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */
-#define CAN_TXBRP_TRP10             (0x1u << CAN_TXBRP_TRP10_Pos)
-#define CAN_TXBRP_TRP11_Pos         11           /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */
-#define CAN_TXBRP_TRP11             (0x1u << CAN_TXBRP_TRP11_Pos)
-#define CAN_TXBRP_TRP12_Pos         12           /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */
-#define CAN_TXBRP_TRP12             (0x1u << CAN_TXBRP_TRP12_Pos)
-#define CAN_TXBRP_TRP13_Pos         13           /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */
-#define CAN_TXBRP_TRP13             (0x1u << CAN_TXBRP_TRP13_Pos)
-#define CAN_TXBRP_TRP14_Pos         14           /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */
-#define CAN_TXBRP_TRP14             (0x1u << CAN_TXBRP_TRP14_Pos)
-#define CAN_TXBRP_TRP15_Pos         15           /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */
-#define CAN_TXBRP_TRP15             (0x1u << CAN_TXBRP_TRP15_Pos)
-#define CAN_TXBRP_TRP16_Pos         16           /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */
-#define CAN_TXBRP_TRP16             (0x1u << CAN_TXBRP_TRP16_Pos)
-#define CAN_TXBRP_TRP17_Pos         17           /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */
-#define CAN_TXBRP_TRP17             (0x1u << CAN_TXBRP_TRP17_Pos)
-#define CAN_TXBRP_TRP18_Pos         18           /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */
-#define CAN_TXBRP_TRP18             (0x1u << CAN_TXBRP_TRP18_Pos)
-#define CAN_TXBRP_TRP19_Pos         19           /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */
-#define CAN_TXBRP_TRP19             (0x1u << CAN_TXBRP_TRP19_Pos)
-#define CAN_TXBRP_TRP20_Pos         20           /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */
-#define CAN_TXBRP_TRP20             (0x1u << CAN_TXBRP_TRP20_Pos)
-#define CAN_TXBRP_TRP21_Pos         21           /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */
-#define CAN_TXBRP_TRP21             (0x1u << CAN_TXBRP_TRP21_Pos)
-#define CAN_TXBRP_TRP22_Pos         22           /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */
-#define CAN_TXBRP_TRP22             (0x1u << CAN_TXBRP_TRP22_Pos)
-#define CAN_TXBRP_TRP23_Pos         23           /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */
-#define CAN_TXBRP_TRP23             (0x1u << CAN_TXBRP_TRP23_Pos)
-#define CAN_TXBRP_TRP24_Pos         24           /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */
-#define CAN_TXBRP_TRP24             (0x1u << CAN_TXBRP_TRP24_Pos)
-#define CAN_TXBRP_TRP25_Pos         25           /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */
-#define CAN_TXBRP_TRP25             (0x1u << CAN_TXBRP_TRP25_Pos)
-#define CAN_TXBRP_TRP26_Pos         26           /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */
-#define CAN_TXBRP_TRP26             (0x1u << CAN_TXBRP_TRP26_Pos)
-#define CAN_TXBRP_TRP27_Pos         27           /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */
-#define CAN_TXBRP_TRP27             (0x1u << CAN_TXBRP_TRP27_Pos)
-#define CAN_TXBRP_TRP28_Pos         28           /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */
-#define CAN_TXBRP_TRP28             (0x1u << CAN_TXBRP_TRP28_Pos)
-#define CAN_TXBRP_TRP29_Pos         29           /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */
-#define CAN_TXBRP_TRP29             (0x1u << CAN_TXBRP_TRP29_Pos)
-#define CAN_TXBRP_TRP30_Pos         30           /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */
-#define CAN_TXBRP_TRP30             (0x1u << CAN_TXBRP_TRP30_Pos)
-#define CAN_TXBRP_TRP31_Pos         31           /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */
-#define CAN_TXBRP_TRP31             (0x1u << CAN_TXBRP_TRP31_Pos)
-#define CAN_TXBRP_MASK              0xFFFFFFFFu  /**< \brief (CAN_TXBRP) MASK Register */
-
-/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t AR0:1;            /*!< bit:      0  Add Request 0                      */
-    uint32_t AR1:1;            /*!< bit:      1  Add Request 1                      */
-    uint32_t AR2:1;            /*!< bit:      2  Add Request 2                      */
-    uint32_t AR3:1;            /*!< bit:      3  Add Request 3                      */
-    uint32_t AR4:1;            /*!< bit:      4  Add Request 4                      */
-    uint32_t AR5:1;            /*!< bit:      5  Add Request 5                      */
-    uint32_t AR6:1;            /*!< bit:      6  Add Request 6                      */
-    uint32_t AR7:1;            /*!< bit:      7  Add Request 7                      */
-    uint32_t AR8:1;            /*!< bit:      8  Add Request 8                      */
-    uint32_t AR9:1;            /*!< bit:      9  Add Request 9                      */
-    uint32_t AR10:1;           /*!< bit:     10  Add Request 10                     */
-    uint32_t AR11:1;           /*!< bit:     11  Add Request 11                     */
-    uint32_t AR12:1;           /*!< bit:     12  Add Request 12                     */
-    uint32_t AR13:1;           /*!< bit:     13  Add Request 13                     */
-    uint32_t AR14:1;           /*!< bit:     14  Add Request 14                     */
-    uint32_t AR15:1;           /*!< bit:     15  Add Request 15                     */
-    uint32_t AR16:1;           /*!< bit:     16  Add Request 16                     */
-    uint32_t AR17:1;           /*!< bit:     17  Add Request 17                     */
-    uint32_t AR18:1;           /*!< bit:     18  Add Request 18                     */
-    uint32_t AR19:1;           /*!< bit:     19  Add Request 19                     */
-    uint32_t AR20:1;           /*!< bit:     20  Add Request 20                     */
-    uint32_t AR21:1;           /*!< bit:     21  Add Request 21                     */
-    uint32_t AR22:1;           /*!< bit:     22  Add Request 22                     */
-    uint32_t AR23:1;           /*!< bit:     23  Add Request 23                     */
-    uint32_t AR24:1;           /*!< bit:     24  Add Request 24                     */
-    uint32_t AR25:1;           /*!< bit:     25  Add Request 25                     */
-    uint32_t AR26:1;           /*!< bit:     26  Add Request 26                     */
-    uint32_t AR27:1;           /*!< bit:     27  Add Request 27                     */
-    uint32_t AR28:1;           /*!< bit:     28  Add Request 28                     */
-    uint32_t AR29:1;           /*!< bit:     29  Add Request 29                     */
-    uint32_t AR30:1;           /*!< bit:     30  Add Request 30                     */
-    uint32_t AR31:1;           /*!< bit:     31  Add Request 31                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBAR_OFFSET            0xD0         /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */
-#define CAN_TXBAR_RESETVALUE        0x00000000u  /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */
-
-#define CAN_TXBAR_AR0_Pos           0            /**< \brief (CAN_TXBAR) Add Request 0 */
-#define CAN_TXBAR_AR0               (0x1u << CAN_TXBAR_AR0_Pos)
-#define CAN_TXBAR_AR1_Pos           1            /**< \brief (CAN_TXBAR) Add Request 1 */
-#define CAN_TXBAR_AR1               (0x1u << CAN_TXBAR_AR1_Pos)
-#define CAN_TXBAR_AR2_Pos           2            /**< \brief (CAN_TXBAR) Add Request 2 */
-#define CAN_TXBAR_AR2               (0x1u << CAN_TXBAR_AR2_Pos)
-#define CAN_TXBAR_AR3_Pos           3            /**< \brief (CAN_TXBAR) Add Request 3 */
-#define CAN_TXBAR_AR3               (0x1u << CAN_TXBAR_AR3_Pos)
-#define CAN_TXBAR_AR4_Pos           4            /**< \brief (CAN_TXBAR) Add Request 4 */
-#define CAN_TXBAR_AR4               (0x1u << CAN_TXBAR_AR4_Pos)
-#define CAN_TXBAR_AR5_Pos           5            /**< \brief (CAN_TXBAR) Add Request 5 */
-#define CAN_TXBAR_AR5               (0x1u << CAN_TXBAR_AR5_Pos)
-#define CAN_TXBAR_AR6_Pos           6            /**< \brief (CAN_TXBAR) Add Request 6 */
-#define CAN_TXBAR_AR6               (0x1u << CAN_TXBAR_AR6_Pos)
-#define CAN_TXBAR_AR7_Pos           7            /**< \brief (CAN_TXBAR) Add Request 7 */
-#define CAN_TXBAR_AR7               (0x1u << CAN_TXBAR_AR7_Pos)
-#define CAN_TXBAR_AR8_Pos           8            /**< \brief (CAN_TXBAR) Add Request 8 */
-#define CAN_TXBAR_AR8               (0x1u << CAN_TXBAR_AR8_Pos)
-#define CAN_TXBAR_AR9_Pos           9            /**< \brief (CAN_TXBAR) Add Request 9 */
-#define CAN_TXBAR_AR9               (0x1u << CAN_TXBAR_AR9_Pos)
-#define CAN_TXBAR_AR10_Pos          10           /**< \brief (CAN_TXBAR) Add Request 10 */
-#define CAN_TXBAR_AR10              (0x1u << CAN_TXBAR_AR10_Pos)
-#define CAN_TXBAR_AR11_Pos          11           /**< \brief (CAN_TXBAR) Add Request 11 */
-#define CAN_TXBAR_AR11              (0x1u << CAN_TXBAR_AR11_Pos)
-#define CAN_TXBAR_AR12_Pos          12           /**< \brief (CAN_TXBAR) Add Request 12 */
-#define CAN_TXBAR_AR12              (0x1u << CAN_TXBAR_AR12_Pos)
-#define CAN_TXBAR_AR13_Pos          13           /**< \brief (CAN_TXBAR) Add Request 13 */
-#define CAN_TXBAR_AR13              (0x1u << CAN_TXBAR_AR13_Pos)
-#define CAN_TXBAR_AR14_Pos          14           /**< \brief (CAN_TXBAR) Add Request 14 */
-#define CAN_TXBAR_AR14              (0x1u << CAN_TXBAR_AR14_Pos)
-#define CAN_TXBAR_AR15_Pos          15           /**< \brief (CAN_TXBAR) Add Request 15 */
-#define CAN_TXBAR_AR15              (0x1u << CAN_TXBAR_AR15_Pos)
-#define CAN_TXBAR_AR16_Pos          16           /**< \brief (CAN_TXBAR) Add Request 16 */
-#define CAN_TXBAR_AR16              (0x1u << CAN_TXBAR_AR16_Pos)
-#define CAN_TXBAR_AR17_Pos          17           /**< \brief (CAN_TXBAR) Add Request 17 */
-#define CAN_TXBAR_AR17              (0x1u << CAN_TXBAR_AR17_Pos)
-#define CAN_TXBAR_AR18_Pos          18           /**< \brief (CAN_TXBAR) Add Request 18 */
-#define CAN_TXBAR_AR18              (0x1u << CAN_TXBAR_AR18_Pos)
-#define CAN_TXBAR_AR19_Pos          19           /**< \brief (CAN_TXBAR) Add Request 19 */
-#define CAN_TXBAR_AR19              (0x1u << CAN_TXBAR_AR19_Pos)
-#define CAN_TXBAR_AR20_Pos          20           /**< \brief (CAN_TXBAR) Add Request 20 */
-#define CAN_TXBAR_AR20              (0x1u << CAN_TXBAR_AR20_Pos)
-#define CAN_TXBAR_AR21_Pos          21           /**< \brief (CAN_TXBAR) Add Request 21 */
-#define CAN_TXBAR_AR21              (0x1u << CAN_TXBAR_AR21_Pos)
-#define CAN_TXBAR_AR22_Pos          22           /**< \brief (CAN_TXBAR) Add Request 22 */
-#define CAN_TXBAR_AR22              (0x1u << CAN_TXBAR_AR22_Pos)
-#define CAN_TXBAR_AR23_Pos          23           /**< \brief (CAN_TXBAR) Add Request 23 */
-#define CAN_TXBAR_AR23              (0x1u << CAN_TXBAR_AR23_Pos)
-#define CAN_TXBAR_AR24_Pos          24           /**< \brief (CAN_TXBAR) Add Request 24 */
-#define CAN_TXBAR_AR24              (0x1u << CAN_TXBAR_AR24_Pos)
-#define CAN_TXBAR_AR25_Pos          25           /**< \brief (CAN_TXBAR) Add Request 25 */
-#define CAN_TXBAR_AR25              (0x1u << CAN_TXBAR_AR25_Pos)
-#define CAN_TXBAR_AR26_Pos          26           /**< \brief (CAN_TXBAR) Add Request 26 */
-#define CAN_TXBAR_AR26              (0x1u << CAN_TXBAR_AR26_Pos)
-#define CAN_TXBAR_AR27_Pos          27           /**< \brief (CAN_TXBAR) Add Request 27 */
-#define CAN_TXBAR_AR27              (0x1u << CAN_TXBAR_AR27_Pos)
-#define CAN_TXBAR_AR28_Pos          28           /**< \brief (CAN_TXBAR) Add Request 28 */
-#define CAN_TXBAR_AR28              (0x1u << CAN_TXBAR_AR28_Pos)
-#define CAN_TXBAR_AR29_Pos          29           /**< \brief (CAN_TXBAR) Add Request 29 */
-#define CAN_TXBAR_AR29              (0x1u << CAN_TXBAR_AR29_Pos)
-#define CAN_TXBAR_AR30_Pos          30           /**< \brief (CAN_TXBAR) Add Request 30 */
-#define CAN_TXBAR_AR30              (0x1u << CAN_TXBAR_AR30_Pos)
-#define CAN_TXBAR_AR31_Pos          31           /**< \brief (CAN_TXBAR) Add Request 31 */
-#define CAN_TXBAR_AR31              (0x1u << CAN_TXBAR_AR31_Pos)
-#define CAN_TXBAR_MASK              0xFFFFFFFFu  /**< \brief (CAN_TXBAR) MASK Register */
-
-/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CR0:1;            /*!< bit:      0  Cancellation Request 0             */
-    uint32_t CR1:1;            /*!< bit:      1  Cancellation Request 1             */
-    uint32_t CR2:1;            /*!< bit:      2  Cancellation Request 2             */
-    uint32_t CR3:1;            /*!< bit:      3  Cancellation Request 3             */
-    uint32_t CR4:1;            /*!< bit:      4  Cancellation Request 4             */
-    uint32_t CR5:1;            /*!< bit:      5  Cancellation Request 5             */
-    uint32_t CR6:1;            /*!< bit:      6  Cancellation Request 6             */
-    uint32_t CR7:1;            /*!< bit:      7  Cancellation Request 7             */
-    uint32_t CR8:1;            /*!< bit:      8  Cancellation Request 8             */
-    uint32_t CR9:1;            /*!< bit:      9  Cancellation Request 9             */
-    uint32_t CR10:1;           /*!< bit:     10  Cancellation Request 10            */
-    uint32_t CR11:1;           /*!< bit:     11  Cancellation Request 11            */
-    uint32_t CR12:1;           /*!< bit:     12  Cancellation Request 12            */
-    uint32_t CR13:1;           /*!< bit:     13  Cancellation Request 13            */
-    uint32_t CR14:1;           /*!< bit:     14  Cancellation Request 14            */
-    uint32_t CR15:1;           /*!< bit:     15  Cancellation Request 15            */
-    uint32_t CR16:1;           /*!< bit:     16  Cancellation Request 16            */
-    uint32_t CR17:1;           /*!< bit:     17  Cancellation Request 17            */
-    uint32_t CR18:1;           /*!< bit:     18  Cancellation Request 18            */
-    uint32_t CR19:1;           /*!< bit:     19  Cancellation Request 19            */
-    uint32_t CR20:1;           /*!< bit:     20  Cancellation Request 20            */
-    uint32_t CR21:1;           /*!< bit:     21  Cancellation Request 21            */
-    uint32_t CR22:1;           /*!< bit:     22  Cancellation Request 22            */
-    uint32_t CR23:1;           /*!< bit:     23  Cancellation Request 23            */
-    uint32_t CR24:1;           /*!< bit:     24  Cancellation Request 24            */
-    uint32_t CR25:1;           /*!< bit:     25  Cancellation Request 25            */
-    uint32_t CR26:1;           /*!< bit:     26  Cancellation Request 26            */
-    uint32_t CR27:1;           /*!< bit:     27  Cancellation Request 27            */
-    uint32_t CR28:1;           /*!< bit:     28  Cancellation Request 28            */
-    uint32_t CR29:1;           /*!< bit:     29  Cancellation Request 29            */
-    uint32_t CR30:1;           /*!< bit:     30  Cancellation Request 30            */
-    uint32_t CR31:1;           /*!< bit:     31  Cancellation Request 31            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBCR_OFFSET            0xD4         /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */
-#define CAN_TXBCR_RESETVALUE        0x00000000u  /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */
-
-#define CAN_TXBCR_CR0_Pos           0            /**< \brief (CAN_TXBCR) Cancellation Request 0 */
-#define CAN_TXBCR_CR0               (0x1u << CAN_TXBCR_CR0_Pos)
-#define CAN_TXBCR_CR1_Pos           1            /**< \brief (CAN_TXBCR) Cancellation Request 1 */
-#define CAN_TXBCR_CR1               (0x1u << CAN_TXBCR_CR1_Pos)
-#define CAN_TXBCR_CR2_Pos           2            /**< \brief (CAN_TXBCR) Cancellation Request 2 */
-#define CAN_TXBCR_CR2               (0x1u << CAN_TXBCR_CR2_Pos)
-#define CAN_TXBCR_CR3_Pos           3            /**< \brief (CAN_TXBCR) Cancellation Request 3 */
-#define CAN_TXBCR_CR3               (0x1u << CAN_TXBCR_CR3_Pos)
-#define CAN_TXBCR_CR4_Pos           4            /**< \brief (CAN_TXBCR) Cancellation Request 4 */
-#define CAN_TXBCR_CR4               (0x1u << CAN_TXBCR_CR4_Pos)
-#define CAN_TXBCR_CR5_Pos           5            /**< \brief (CAN_TXBCR) Cancellation Request 5 */
-#define CAN_TXBCR_CR5               (0x1u << CAN_TXBCR_CR5_Pos)
-#define CAN_TXBCR_CR6_Pos           6            /**< \brief (CAN_TXBCR) Cancellation Request 6 */
-#define CAN_TXBCR_CR6               (0x1u << CAN_TXBCR_CR6_Pos)
-#define CAN_TXBCR_CR7_Pos           7            /**< \brief (CAN_TXBCR) Cancellation Request 7 */
-#define CAN_TXBCR_CR7               (0x1u << CAN_TXBCR_CR7_Pos)
-#define CAN_TXBCR_CR8_Pos           8            /**< \brief (CAN_TXBCR) Cancellation Request 8 */
-#define CAN_TXBCR_CR8               (0x1u << CAN_TXBCR_CR8_Pos)
-#define CAN_TXBCR_CR9_Pos           9            /**< \brief (CAN_TXBCR) Cancellation Request 9 */
-#define CAN_TXBCR_CR9               (0x1u << CAN_TXBCR_CR9_Pos)
-#define CAN_TXBCR_CR10_Pos          10           /**< \brief (CAN_TXBCR) Cancellation Request 10 */
-#define CAN_TXBCR_CR10              (0x1u << CAN_TXBCR_CR10_Pos)
-#define CAN_TXBCR_CR11_Pos          11           /**< \brief (CAN_TXBCR) Cancellation Request 11 */
-#define CAN_TXBCR_CR11              (0x1u << CAN_TXBCR_CR11_Pos)
-#define CAN_TXBCR_CR12_Pos          12           /**< \brief (CAN_TXBCR) Cancellation Request 12 */
-#define CAN_TXBCR_CR12              (0x1u << CAN_TXBCR_CR12_Pos)
-#define CAN_TXBCR_CR13_Pos          13           /**< \brief (CAN_TXBCR) Cancellation Request 13 */
-#define CAN_TXBCR_CR13              (0x1u << CAN_TXBCR_CR13_Pos)
-#define CAN_TXBCR_CR14_Pos          14           /**< \brief (CAN_TXBCR) Cancellation Request 14 */
-#define CAN_TXBCR_CR14              (0x1u << CAN_TXBCR_CR14_Pos)
-#define CAN_TXBCR_CR15_Pos          15           /**< \brief (CAN_TXBCR) Cancellation Request 15 */
-#define CAN_TXBCR_CR15              (0x1u << CAN_TXBCR_CR15_Pos)
-#define CAN_TXBCR_CR16_Pos          16           /**< \brief (CAN_TXBCR) Cancellation Request 16 */
-#define CAN_TXBCR_CR16              (0x1u << CAN_TXBCR_CR16_Pos)
-#define CAN_TXBCR_CR17_Pos          17           /**< \brief (CAN_TXBCR) Cancellation Request 17 */
-#define CAN_TXBCR_CR17              (0x1u << CAN_TXBCR_CR17_Pos)
-#define CAN_TXBCR_CR18_Pos          18           /**< \brief (CAN_TXBCR) Cancellation Request 18 */
-#define CAN_TXBCR_CR18              (0x1u << CAN_TXBCR_CR18_Pos)
-#define CAN_TXBCR_CR19_Pos          19           /**< \brief (CAN_TXBCR) Cancellation Request 19 */
-#define CAN_TXBCR_CR19              (0x1u << CAN_TXBCR_CR19_Pos)
-#define CAN_TXBCR_CR20_Pos          20           /**< \brief (CAN_TXBCR) Cancellation Request 20 */
-#define CAN_TXBCR_CR20              (0x1u << CAN_TXBCR_CR20_Pos)
-#define CAN_TXBCR_CR21_Pos          21           /**< \brief (CAN_TXBCR) Cancellation Request 21 */
-#define CAN_TXBCR_CR21              (0x1u << CAN_TXBCR_CR21_Pos)
-#define CAN_TXBCR_CR22_Pos          22           /**< \brief (CAN_TXBCR) Cancellation Request 22 */
-#define CAN_TXBCR_CR22              (0x1u << CAN_TXBCR_CR22_Pos)
-#define CAN_TXBCR_CR23_Pos          23           /**< \brief (CAN_TXBCR) Cancellation Request 23 */
-#define CAN_TXBCR_CR23              (0x1u << CAN_TXBCR_CR23_Pos)
-#define CAN_TXBCR_CR24_Pos          24           /**< \brief (CAN_TXBCR) Cancellation Request 24 */
-#define CAN_TXBCR_CR24              (0x1u << CAN_TXBCR_CR24_Pos)
-#define CAN_TXBCR_CR25_Pos          25           /**< \brief (CAN_TXBCR) Cancellation Request 25 */
-#define CAN_TXBCR_CR25              (0x1u << CAN_TXBCR_CR25_Pos)
-#define CAN_TXBCR_CR26_Pos          26           /**< \brief (CAN_TXBCR) Cancellation Request 26 */
-#define CAN_TXBCR_CR26              (0x1u << CAN_TXBCR_CR26_Pos)
-#define CAN_TXBCR_CR27_Pos          27           /**< \brief (CAN_TXBCR) Cancellation Request 27 */
-#define CAN_TXBCR_CR27              (0x1u << CAN_TXBCR_CR27_Pos)
-#define CAN_TXBCR_CR28_Pos          28           /**< \brief (CAN_TXBCR) Cancellation Request 28 */
-#define CAN_TXBCR_CR28              (0x1u << CAN_TXBCR_CR28_Pos)
-#define CAN_TXBCR_CR29_Pos          29           /**< \brief (CAN_TXBCR) Cancellation Request 29 */
-#define CAN_TXBCR_CR29              (0x1u << CAN_TXBCR_CR29_Pos)
-#define CAN_TXBCR_CR30_Pos          30           /**< \brief (CAN_TXBCR) Cancellation Request 30 */
-#define CAN_TXBCR_CR30              (0x1u << CAN_TXBCR_CR30_Pos)
-#define CAN_TXBCR_CR31_Pos          31           /**< \brief (CAN_TXBCR) Cancellation Request 31 */
-#define CAN_TXBCR_CR31              (0x1u << CAN_TXBCR_CR31_Pos)
-#define CAN_TXBCR_MASK              0xFFFFFFFFu  /**< \brief (CAN_TXBCR) MASK Register */
-
-/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/  32) Tx Buffer Transmission Occurred -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TO0:1;            /*!< bit:      0  Transmission Occurred 0            */
-    uint32_t TO1:1;            /*!< bit:      1  Transmission Occurred 1            */
-    uint32_t TO2:1;            /*!< bit:      2  Transmission Occurred 2            */
-    uint32_t TO3:1;            /*!< bit:      3  Transmission Occurred 3            */
-    uint32_t TO4:1;            /*!< bit:      4  Transmission Occurred 4            */
-    uint32_t TO5:1;            /*!< bit:      5  Transmission Occurred 5            */
-    uint32_t TO6:1;            /*!< bit:      6  Transmission Occurred 6            */
-    uint32_t TO7:1;            /*!< bit:      7  Transmission Occurred 7            */
-    uint32_t TO8:1;            /*!< bit:      8  Transmission Occurred 8            */
-    uint32_t TO9:1;            /*!< bit:      9  Transmission Occurred 9            */
-    uint32_t TO10:1;           /*!< bit:     10  Transmission Occurred 10           */
-    uint32_t TO11:1;           /*!< bit:     11  Transmission Occurred 11           */
-    uint32_t TO12:1;           /*!< bit:     12  Transmission Occurred 12           */
-    uint32_t TO13:1;           /*!< bit:     13  Transmission Occurred 13           */
-    uint32_t TO14:1;           /*!< bit:     14  Transmission Occurred 14           */
-    uint32_t TO15:1;           /*!< bit:     15  Transmission Occurred 15           */
-    uint32_t TO16:1;           /*!< bit:     16  Transmission Occurred 16           */
-    uint32_t TO17:1;           /*!< bit:     17  Transmission Occurred 17           */
-    uint32_t TO18:1;           /*!< bit:     18  Transmission Occurred 18           */
-    uint32_t TO19:1;           /*!< bit:     19  Transmission Occurred 19           */
-    uint32_t TO20:1;           /*!< bit:     20  Transmission Occurred 20           */
-    uint32_t TO21:1;           /*!< bit:     21  Transmission Occurred 21           */
-    uint32_t TO22:1;           /*!< bit:     22  Transmission Occurred 22           */
-    uint32_t TO23:1;           /*!< bit:     23  Transmission Occurred 23           */
-    uint32_t TO24:1;           /*!< bit:     24  Transmission Occurred 24           */
-    uint32_t TO25:1;           /*!< bit:     25  Transmission Occurred 25           */
-    uint32_t TO26:1;           /*!< bit:     26  Transmission Occurred 26           */
-    uint32_t TO27:1;           /*!< bit:     27  Transmission Occurred 27           */
-    uint32_t TO28:1;           /*!< bit:     28  Transmission Occurred 28           */
-    uint32_t TO29:1;           /*!< bit:     29  Transmission Occurred 29           */
-    uint32_t TO30:1;           /*!< bit:     30  Transmission Occurred 30           */
-    uint32_t TO31:1;           /*!< bit:     31  Transmission Occurred 31           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBTO_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBTO_OFFSET            0xD8         /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */
-#define CAN_TXBTO_RESETVALUE        0x00000000u  /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */
-
-#define CAN_TXBTO_TO0_Pos           0            /**< \brief (CAN_TXBTO) Transmission Occurred 0 */
-#define CAN_TXBTO_TO0               (0x1u << CAN_TXBTO_TO0_Pos)
-#define CAN_TXBTO_TO1_Pos           1            /**< \brief (CAN_TXBTO) Transmission Occurred 1 */
-#define CAN_TXBTO_TO1               (0x1u << CAN_TXBTO_TO1_Pos)
-#define CAN_TXBTO_TO2_Pos           2            /**< \brief (CAN_TXBTO) Transmission Occurred 2 */
-#define CAN_TXBTO_TO2               (0x1u << CAN_TXBTO_TO2_Pos)
-#define CAN_TXBTO_TO3_Pos           3            /**< \brief (CAN_TXBTO) Transmission Occurred 3 */
-#define CAN_TXBTO_TO3               (0x1u << CAN_TXBTO_TO3_Pos)
-#define CAN_TXBTO_TO4_Pos           4            /**< \brief (CAN_TXBTO) Transmission Occurred 4 */
-#define CAN_TXBTO_TO4               (0x1u << CAN_TXBTO_TO4_Pos)
-#define CAN_TXBTO_TO5_Pos           5            /**< \brief (CAN_TXBTO) Transmission Occurred 5 */
-#define CAN_TXBTO_TO5               (0x1u << CAN_TXBTO_TO5_Pos)
-#define CAN_TXBTO_TO6_Pos           6            /**< \brief (CAN_TXBTO) Transmission Occurred 6 */
-#define CAN_TXBTO_TO6               (0x1u << CAN_TXBTO_TO6_Pos)
-#define CAN_TXBTO_TO7_Pos           7            /**< \brief (CAN_TXBTO) Transmission Occurred 7 */
-#define CAN_TXBTO_TO7               (0x1u << CAN_TXBTO_TO7_Pos)
-#define CAN_TXBTO_TO8_Pos           8            /**< \brief (CAN_TXBTO) Transmission Occurred 8 */
-#define CAN_TXBTO_TO8               (0x1u << CAN_TXBTO_TO8_Pos)
-#define CAN_TXBTO_TO9_Pos           9            /**< \brief (CAN_TXBTO) Transmission Occurred 9 */
-#define CAN_TXBTO_TO9               (0x1u << CAN_TXBTO_TO9_Pos)
-#define CAN_TXBTO_TO10_Pos          10           /**< \brief (CAN_TXBTO) Transmission Occurred 10 */
-#define CAN_TXBTO_TO10              (0x1u << CAN_TXBTO_TO10_Pos)
-#define CAN_TXBTO_TO11_Pos          11           /**< \brief (CAN_TXBTO) Transmission Occurred 11 */
-#define CAN_TXBTO_TO11              (0x1u << CAN_TXBTO_TO11_Pos)
-#define CAN_TXBTO_TO12_Pos          12           /**< \brief (CAN_TXBTO) Transmission Occurred 12 */
-#define CAN_TXBTO_TO12              (0x1u << CAN_TXBTO_TO12_Pos)
-#define CAN_TXBTO_TO13_Pos          13           /**< \brief (CAN_TXBTO) Transmission Occurred 13 */
-#define CAN_TXBTO_TO13              (0x1u << CAN_TXBTO_TO13_Pos)
-#define CAN_TXBTO_TO14_Pos          14           /**< \brief (CAN_TXBTO) Transmission Occurred 14 */
-#define CAN_TXBTO_TO14              (0x1u << CAN_TXBTO_TO14_Pos)
-#define CAN_TXBTO_TO15_Pos          15           /**< \brief (CAN_TXBTO) Transmission Occurred 15 */
-#define CAN_TXBTO_TO15              (0x1u << CAN_TXBTO_TO15_Pos)
-#define CAN_TXBTO_TO16_Pos          16           /**< \brief (CAN_TXBTO) Transmission Occurred 16 */
-#define CAN_TXBTO_TO16              (0x1u << CAN_TXBTO_TO16_Pos)
-#define CAN_TXBTO_TO17_Pos          17           /**< \brief (CAN_TXBTO) Transmission Occurred 17 */
-#define CAN_TXBTO_TO17              (0x1u << CAN_TXBTO_TO17_Pos)
-#define CAN_TXBTO_TO18_Pos          18           /**< \brief (CAN_TXBTO) Transmission Occurred 18 */
-#define CAN_TXBTO_TO18              (0x1u << CAN_TXBTO_TO18_Pos)
-#define CAN_TXBTO_TO19_Pos          19           /**< \brief (CAN_TXBTO) Transmission Occurred 19 */
-#define CAN_TXBTO_TO19              (0x1u << CAN_TXBTO_TO19_Pos)
-#define CAN_TXBTO_TO20_Pos          20           /**< \brief (CAN_TXBTO) Transmission Occurred 20 */
-#define CAN_TXBTO_TO20              (0x1u << CAN_TXBTO_TO20_Pos)
-#define CAN_TXBTO_TO21_Pos          21           /**< \brief (CAN_TXBTO) Transmission Occurred 21 */
-#define CAN_TXBTO_TO21              (0x1u << CAN_TXBTO_TO21_Pos)
-#define CAN_TXBTO_TO22_Pos          22           /**< \brief (CAN_TXBTO) Transmission Occurred 22 */
-#define CAN_TXBTO_TO22              (0x1u << CAN_TXBTO_TO22_Pos)
-#define CAN_TXBTO_TO23_Pos          23           /**< \brief (CAN_TXBTO) Transmission Occurred 23 */
-#define CAN_TXBTO_TO23              (0x1u << CAN_TXBTO_TO23_Pos)
-#define CAN_TXBTO_TO24_Pos          24           /**< \brief (CAN_TXBTO) Transmission Occurred 24 */
-#define CAN_TXBTO_TO24              (0x1u << CAN_TXBTO_TO24_Pos)
-#define CAN_TXBTO_TO25_Pos          25           /**< \brief (CAN_TXBTO) Transmission Occurred 25 */
-#define CAN_TXBTO_TO25              (0x1u << CAN_TXBTO_TO25_Pos)
-#define CAN_TXBTO_TO26_Pos          26           /**< \brief (CAN_TXBTO) Transmission Occurred 26 */
-#define CAN_TXBTO_TO26              (0x1u << CAN_TXBTO_TO26_Pos)
-#define CAN_TXBTO_TO27_Pos          27           /**< \brief (CAN_TXBTO) Transmission Occurred 27 */
-#define CAN_TXBTO_TO27              (0x1u << CAN_TXBTO_TO27_Pos)
-#define CAN_TXBTO_TO28_Pos          28           /**< \brief (CAN_TXBTO) Transmission Occurred 28 */
-#define CAN_TXBTO_TO28              (0x1u << CAN_TXBTO_TO28_Pos)
-#define CAN_TXBTO_TO29_Pos          29           /**< \brief (CAN_TXBTO) Transmission Occurred 29 */
-#define CAN_TXBTO_TO29              (0x1u << CAN_TXBTO_TO29_Pos)
-#define CAN_TXBTO_TO30_Pos          30           /**< \brief (CAN_TXBTO) Transmission Occurred 30 */
-#define CAN_TXBTO_TO30              (0x1u << CAN_TXBTO_TO30_Pos)
-#define CAN_TXBTO_TO31_Pos          31           /**< \brief (CAN_TXBTO) Transmission Occurred 31 */
-#define CAN_TXBTO_TO31              (0x1u << CAN_TXBTO_TO31_Pos)
-#define CAN_TXBTO_MASK              0xFFFFFFFFu  /**< \brief (CAN_TXBTO) MASK Register */
-
-/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/  32) Tx Buffer Cancellation Finished -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CF0:1;            /*!< bit:      0  Tx Buffer Cancellation Finished 0  */
-    uint32_t CF1:1;            /*!< bit:      1  Tx Buffer Cancellation Finished 1  */
-    uint32_t CF2:1;            /*!< bit:      2  Tx Buffer Cancellation Finished 2  */
-    uint32_t CF3:1;            /*!< bit:      3  Tx Buffer Cancellation Finished 3  */
-    uint32_t CF4:1;            /*!< bit:      4  Tx Buffer Cancellation Finished 4  */
-    uint32_t CF5:1;            /*!< bit:      5  Tx Buffer Cancellation Finished 5  */
-    uint32_t CF6:1;            /*!< bit:      6  Tx Buffer Cancellation Finished 6  */
-    uint32_t CF7:1;            /*!< bit:      7  Tx Buffer Cancellation Finished 7  */
-    uint32_t CF8:1;            /*!< bit:      8  Tx Buffer Cancellation Finished 8  */
-    uint32_t CF9:1;            /*!< bit:      9  Tx Buffer Cancellation Finished 9  */
-    uint32_t CF10:1;           /*!< bit:     10  Tx Buffer Cancellation Finished 10 */
-    uint32_t CF11:1;           /*!< bit:     11  Tx Buffer Cancellation Finished 11 */
-    uint32_t CF12:1;           /*!< bit:     12  Tx Buffer Cancellation Finished 12 */
-    uint32_t CF13:1;           /*!< bit:     13  Tx Buffer Cancellation Finished 13 */
-    uint32_t CF14:1;           /*!< bit:     14  Tx Buffer Cancellation Finished 14 */
-    uint32_t CF15:1;           /*!< bit:     15  Tx Buffer Cancellation Finished 15 */
-    uint32_t CF16:1;           /*!< bit:     16  Tx Buffer Cancellation Finished 16 */
-    uint32_t CF17:1;           /*!< bit:     17  Tx Buffer Cancellation Finished 17 */
-    uint32_t CF18:1;           /*!< bit:     18  Tx Buffer Cancellation Finished 18 */
-    uint32_t CF19:1;           /*!< bit:     19  Tx Buffer Cancellation Finished 19 */
-    uint32_t CF20:1;           /*!< bit:     20  Tx Buffer Cancellation Finished 20 */
-    uint32_t CF21:1;           /*!< bit:     21  Tx Buffer Cancellation Finished 21 */
-    uint32_t CF22:1;           /*!< bit:     22  Tx Buffer Cancellation Finished 22 */
-    uint32_t CF23:1;           /*!< bit:     23  Tx Buffer Cancellation Finished 23 */
-    uint32_t CF24:1;           /*!< bit:     24  Tx Buffer Cancellation Finished 24 */
-    uint32_t CF25:1;           /*!< bit:     25  Tx Buffer Cancellation Finished 25 */
-    uint32_t CF26:1;           /*!< bit:     26  Tx Buffer Cancellation Finished 26 */
-    uint32_t CF27:1;           /*!< bit:     27  Tx Buffer Cancellation Finished 27 */
-    uint32_t CF28:1;           /*!< bit:     28  Tx Buffer Cancellation Finished 28 */
-    uint32_t CF29:1;           /*!< bit:     29  Tx Buffer Cancellation Finished 29 */
-    uint32_t CF30:1;           /*!< bit:     30  Tx Buffer Cancellation Finished 30 */
-    uint32_t CF31:1;           /*!< bit:     31  Tx Buffer Cancellation Finished 31 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBCF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBCF_OFFSET            0xDC         /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */
-#define CAN_TXBCF_RESETVALUE        0x00000000u  /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */
-
-#define CAN_TXBCF_CF0_Pos           0            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */
-#define CAN_TXBCF_CF0               (0x1u << CAN_TXBCF_CF0_Pos)
-#define CAN_TXBCF_CF1_Pos           1            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */
-#define CAN_TXBCF_CF1               (0x1u << CAN_TXBCF_CF1_Pos)
-#define CAN_TXBCF_CF2_Pos           2            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */
-#define CAN_TXBCF_CF2               (0x1u << CAN_TXBCF_CF2_Pos)
-#define CAN_TXBCF_CF3_Pos           3            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */
-#define CAN_TXBCF_CF3               (0x1u << CAN_TXBCF_CF3_Pos)
-#define CAN_TXBCF_CF4_Pos           4            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */
-#define CAN_TXBCF_CF4               (0x1u << CAN_TXBCF_CF4_Pos)
-#define CAN_TXBCF_CF5_Pos           5            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */
-#define CAN_TXBCF_CF5               (0x1u << CAN_TXBCF_CF5_Pos)
-#define CAN_TXBCF_CF6_Pos           6            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */
-#define CAN_TXBCF_CF6               (0x1u << CAN_TXBCF_CF6_Pos)
-#define CAN_TXBCF_CF7_Pos           7            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */
-#define CAN_TXBCF_CF7               (0x1u << CAN_TXBCF_CF7_Pos)
-#define CAN_TXBCF_CF8_Pos           8            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */
-#define CAN_TXBCF_CF8               (0x1u << CAN_TXBCF_CF8_Pos)
-#define CAN_TXBCF_CF9_Pos           9            /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */
-#define CAN_TXBCF_CF9               (0x1u << CAN_TXBCF_CF9_Pos)
-#define CAN_TXBCF_CF10_Pos          10           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */
-#define CAN_TXBCF_CF10              (0x1u << CAN_TXBCF_CF10_Pos)
-#define CAN_TXBCF_CF11_Pos          11           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */
-#define CAN_TXBCF_CF11              (0x1u << CAN_TXBCF_CF11_Pos)
-#define CAN_TXBCF_CF12_Pos          12           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */
-#define CAN_TXBCF_CF12              (0x1u << CAN_TXBCF_CF12_Pos)
-#define CAN_TXBCF_CF13_Pos          13           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */
-#define CAN_TXBCF_CF13              (0x1u << CAN_TXBCF_CF13_Pos)
-#define CAN_TXBCF_CF14_Pos          14           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */
-#define CAN_TXBCF_CF14              (0x1u << CAN_TXBCF_CF14_Pos)
-#define CAN_TXBCF_CF15_Pos          15           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */
-#define CAN_TXBCF_CF15              (0x1u << CAN_TXBCF_CF15_Pos)
-#define CAN_TXBCF_CF16_Pos          16           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */
-#define CAN_TXBCF_CF16              (0x1u << CAN_TXBCF_CF16_Pos)
-#define CAN_TXBCF_CF17_Pos          17           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */
-#define CAN_TXBCF_CF17              (0x1u << CAN_TXBCF_CF17_Pos)
-#define CAN_TXBCF_CF18_Pos          18           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */
-#define CAN_TXBCF_CF18              (0x1u << CAN_TXBCF_CF18_Pos)
-#define CAN_TXBCF_CF19_Pos          19           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */
-#define CAN_TXBCF_CF19              (0x1u << CAN_TXBCF_CF19_Pos)
-#define CAN_TXBCF_CF20_Pos          20           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */
-#define CAN_TXBCF_CF20              (0x1u << CAN_TXBCF_CF20_Pos)
-#define CAN_TXBCF_CF21_Pos          21           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */
-#define CAN_TXBCF_CF21              (0x1u << CAN_TXBCF_CF21_Pos)
-#define CAN_TXBCF_CF22_Pos          22           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */
-#define CAN_TXBCF_CF22              (0x1u << CAN_TXBCF_CF22_Pos)
-#define CAN_TXBCF_CF23_Pos          23           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */
-#define CAN_TXBCF_CF23              (0x1u << CAN_TXBCF_CF23_Pos)
-#define CAN_TXBCF_CF24_Pos          24           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */
-#define CAN_TXBCF_CF24              (0x1u << CAN_TXBCF_CF24_Pos)
-#define CAN_TXBCF_CF25_Pos          25           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */
-#define CAN_TXBCF_CF25              (0x1u << CAN_TXBCF_CF25_Pos)
-#define CAN_TXBCF_CF26_Pos          26           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */
-#define CAN_TXBCF_CF26              (0x1u << CAN_TXBCF_CF26_Pos)
-#define CAN_TXBCF_CF27_Pos          27           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */
-#define CAN_TXBCF_CF27              (0x1u << CAN_TXBCF_CF27_Pos)
-#define CAN_TXBCF_CF28_Pos          28           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */
-#define CAN_TXBCF_CF28              (0x1u << CAN_TXBCF_CF28_Pos)
-#define CAN_TXBCF_CF29_Pos          29           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */
-#define CAN_TXBCF_CF29              (0x1u << CAN_TXBCF_CF29_Pos)
-#define CAN_TXBCF_CF30_Pos          30           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */
-#define CAN_TXBCF_CF30              (0x1u << CAN_TXBCF_CF30_Pos)
-#define CAN_TXBCF_CF31_Pos          31           /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */
-#define CAN_TXBCF_CF31              (0x1u << CAN_TXBCF_CF31_Pos)
-#define CAN_TXBCF_MASK              0xFFFFFFFFu  /**< \brief (CAN_TXBCF) MASK Register */
-
-/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TIE0:1;           /*!< bit:      0  Transmission Interrupt Enable 0    */
-    uint32_t TIE1:1;           /*!< bit:      1  Transmission Interrupt Enable 1    */
-    uint32_t TIE2:1;           /*!< bit:      2  Transmission Interrupt Enable 2    */
-    uint32_t TIE3:1;           /*!< bit:      3  Transmission Interrupt Enable 3    */
-    uint32_t TIE4:1;           /*!< bit:      4  Transmission Interrupt Enable 4    */
-    uint32_t TIE5:1;           /*!< bit:      5  Transmission Interrupt Enable 5    */
-    uint32_t TIE6:1;           /*!< bit:      6  Transmission Interrupt Enable 6    */
-    uint32_t TIE7:1;           /*!< bit:      7  Transmission Interrupt Enable 7    */
-    uint32_t TIE8:1;           /*!< bit:      8  Transmission Interrupt Enable 8    */
-    uint32_t TIE9:1;           /*!< bit:      9  Transmission Interrupt Enable 9    */
-    uint32_t TIE10:1;          /*!< bit:     10  Transmission Interrupt Enable 10   */
-    uint32_t TIE11:1;          /*!< bit:     11  Transmission Interrupt Enable 11   */
-    uint32_t TIE12:1;          /*!< bit:     12  Transmission Interrupt Enable 12   */
-    uint32_t TIE13:1;          /*!< bit:     13  Transmission Interrupt Enable 13   */
-    uint32_t TIE14:1;          /*!< bit:     14  Transmission Interrupt Enable 14   */
-    uint32_t TIE15:1;          /*!< bit:     15  Transmission Interrupt Enable 15   */
-    uint32_t TIE16:1;          /*!< bit:     16  Transmission Interrupt Enable 16   */
-    uint32_t TIE17:1;          /*!< bit:     17  Transmission Interrupt Enable 17   */
-    uint32_t TIE18:1;          /*!< bit:     18  Transmission Interrupt Enable 18   */
-    uint32_t TIE19:1;          /*!< bit:     19  Transmission Interrupt Enable 19   */
-    uint32_t TIE20:1;          /*!< bit:     20  Transmission Interrupt Enable 20   */
-    uint32_t TIE21:1;          /*!< bit:     21  Transmission Interrupt Enable 21   */
-    uint32_t TIE22:1;          /*!< bit:     22  Transmission Interrupt Enable 22   */
-    uint32_t TIE23:1;          /*!< bit:     23  Transmission Interrupt Enable 23   */
-    uint32_t TIE24:1;          /*!< bit:     24  Transmission Interrupt Enable 24   */
-    uint32_t TIE25:1;          /*!< bit:     25  Transmission Interrupt Enable 25   */
-    uint32_t TIE26:1;          /*!< bit:     26  Transmission Interrupt Enable 26   */
-    uint32_t TIE27:1;          /*!< bit:     27  Transmission Interrupt Enable 27   */
-    uint32_t TIE28:1;          /*!< bit:     28  Transmission Interrupt Enable 28   */
-    uint32_t TIE29:1;          /*!< bit:     29  Transmission Interrupt Enable 29   */
-    uint32_t TIE30:1;          /*!< bit:     30  Transmission Interrupt Enable 30   */
-    uint32_t TIE31:1;          /*!< bit:     31  Transmission Interrupt Enable 31   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBTIE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBTIE_OFFSET           0xE0         /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */
-#define CAN_TXBTIE_RESETVALUE       0x00000000u  /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */
-
-#define CAN_TXBTIE_TIE0_Pos         0            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */
-#define CAN_TXBTIE_TIE0             (0x1u << CAN_TXBTIE_TIE0_Pos)
-#define CAN_TXBTIE_TIE1_Pos         1            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */
-#define CAN_TXBTIE_TIE1             (0x1u << CAN_TXBTIE_TIE1_Pos)
-#define CAN_TXBTIE_TIE2_Pos         2            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */
-#define CAN_TXBTIE_TIE2             (0x1u << CAN_TXBTIE_TIE2_Pos)
-#define CAN_TXBTIE_TIE3_Pos         3            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */
-#define CAN_TXBTIE_TIE3             (0x1u << CAN_TXBTIE_TIE3_Pos)
-#define CAN_TXBTIE_TIE4_Pos         4            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */
-#define CAN_TXBTIE_TIE4             (0x1u << CAN_TXBTIE_TIE4_Pos)
-#define CAN_TXBTIE_TIE5_Pos         5            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */
-#define CAN_TXBTIE_TIE5             (0x1u << CAN_TXBTIE_TIE5_Pos)
-#define CAN_TXBTIE_TIE6_Pos         6            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */
-#define CAN_TXBTIE_TIE6             (0x1u << CAN_TXBTIE_TIE6_Pos)
-#define CAN_TXBTIE_TIE7_Pos         7            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */
-#define CAN_TXBTIE_TIE7             (0x1u << CAN_TXBTIE_TIE7_Pos)
-#define CAN_TXBTIE_TIE8_Pos         8            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */
-#define CAN_TXBTIE_TIE8             (0x1u << CAN_TXBTIE_TIE8_Pos)
-#define CAN_TXBTIE_TIE9_Pos         9            /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */
-#define CAN_TXBTIE_TIE9             (0x1u << CAN_TXBTIE_TIE9_Pos)
-#define CAN_TXBTIE_TIE10_Pos        10           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */
-#define CAN_TXBTIE_TIE10            (0x1u << CAN_TXBTIE_TIE10_Pos)
-#define CAN_TXBTIE_TIE11_Pos        11           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */
-#define CAN_TXBTIE_TIE11            (0x1u << CAN_TXBTIE_TIE11_Pos)
-#define CAN_TXBTIE_TIE12_Pos        12           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */
-#define CAN_TXBTIE_TIE12            (0x1u << CAN_TXBTIE_TIE12_Pos)
-#define CAN_TXBTIE_TIE13_Pos        13           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */
-#define CAN_TXBTIE_TIE13            (0x1u << CAN_TXBTIE_TIE13_Pos)
-#define CAN_TXBTIE_TIE14_Pos        14           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */
-#define CAN_TXBTIE_TIE14            (0x1u << CAN_TXBTIE_TIE14_Pos)
-#define CAN_TXBTIE_TIE15_Pos        15           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */
-#define CAN_TXBTIE_TIE15            (0x1u << CAN_TXBTIE_TIE15_Pos)
-#define CAN_TXBTIE_TIE16_Pos        16           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */
-#define CAN_TXBTIE_TIE16            (0x1u << CAN_TXBTIE_TIE16_Pos)
-#define CAN_TXBTIE_TIE17_Pos        17           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */
-#define CAN_TXBTIE_TIE17            (0x1u << CAN_TXBTIE_TIE17_Pos)
-#define CAN_TXBTIE_TIE18_Pos        18           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */
-#define CAN_TXBTIE_TIE18            (0x1u << CAN_TXBTIE_TIE18_Pos)
-#define CAN_TXBTIE_TIE19_Pos        19           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */
-#define CAN_TXBTIE_TIE19            (0x1u << CAN_TXBTIE_TIE19_Pos)
-#define CAN_TXBTIE_TIE20_Pos        20           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */
-#define CAN_TXBTIE_TIE20            (0x1u << CAN_TXBTIE_TIE20_Pos)
-#define CAN_TXBTIE_TIE21_Pos        21           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */
-#define CAN_TXBTIE_TIE21            (0x1u << CAN_TXBTIE_TIE21_Pos)
-#define CAN_TXBTIE_TIE22_Pos        22           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */
-#define CAN_TXBTIE_TIE22            (0x1u << CAN_TXBTIE_TIE22_Pos)
-#define CAN_TXBTIE_TIE23_Pos        23           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */
-#define CAN_TXBTIE_TIE23            (0x1u << CAN_TXBTIE_TIE23_Pos)
-#define CAN_TXBTIE_TIE24_Pos        24           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */
-#define CAN_TXBTIE_TIE24            (0x1u << CAN_TXBTIE_TIE24_Pos)
-#define CAN_TXBTIE_TIE25_Pos        25           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */
-#define CAN_TXBTIE_TIE25            (0x1u << CAN_TXBTIE_TIE25_Pos)
-#define CAN_TXBTIE_TIE26_Pos        26           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */
-#define CAN_TXBTIE_TIE26            (0x1u << CAN_TXBTIE_TIE26_Pos)
-#define CAN_TXBTIE_TIE27_Pos        27           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */
-#define CAN_TXBTIE_TIE27            (0x1u << CAN_TXBTIE_TIE27_Pos)
-#define CAN_TXBTIE_TIE28_Pos        28           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */
-#define CAN_TXBTIE_TIE28            (0x1u << CAN_TXBTIE_TIE28_Pos)
-#define CAN_TXBTIE_TIE29_Pos        29           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */
-#define CAN_TXBTIE_TIE29            (0x1u << CAN_TXBTIE_TIE29_Pos)
-#define CAN_TXBTIE_TIE30_Pos        30           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */
-#define CAN_TXBTIE_TIE30            (0x1u << CAN_TXBTIE_TIE30_Pos)
-#define CAN_TXBTIE_TIE31_Pos        31           /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */
-#define CAN_TXBTIE_TIE31            (0x1u << CAN_TXBTIE_TIE31_Pos)
-#define CAN_TXBTIE_MASK             0xFFFFFFFFu  /**< \brief (CAN_TXBTIE) MASK Register */
-
-/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CFIE0:1;          /*!< bit:      0  Cancellation Finished Interrupt Enable 0 */
-    uint32_t CFIE1:1;          /*!< bit:      1  Cancellation Finished Interrupt Enable 1 */
-    uint32_t CFIE2:1;          /*!< bit:      2  Cancellation Finished Interrupt Enable 2 */
-    uint32_t CFIE3:1;          /*!< bit:      3  Cancellation Finished Interrupt Enable 3 */
-    uint32_t CFIE4:1;          /*!< bit:      4  Cancellation Finished Interrupt Enable 4 */
-    uint32_t CFIE5:1;          /*!< bit:      5  Cancellation Finished Interrupt Enable 5 */
-    uint32_t CFIE6:1;          /*!< bit:      6  Cancellation Finished Interrupt Enable 6 */
-    uint32_t CFIE7:1;          /*!< bit:      7  Cancellation Finished Interrupt Enable 7 */
-    uint32_t CFIE8:1;          /*!< bit:      8  Cancellation Finished Interrupt Enable 8 */
-    uint32_t CFIE9:1;          /*!< bit:      9  Cancellation Finished Interrupt Enable 9 */
-    uint32_t CFIE10:1;         /*!< bit:     10  Cancellation Finished Interrupt Enable 10 */
-    uint32_t CFIE11:1;         /*!< bit:     11  Cancellation Finished Interrupt Enable 11 */
-    uint32_t CFIE12:1;         /*!< bit:     12  Cancellation Finished Interrupt Enable 12 */
-    uint32_t CFIE13:1;         /*!< bit:     13  Cancellation Finished Interrupt Enable 13 */
-    uint32_t CFIE14:1;         /*!< bit:     14  Cancellation Finished Interrupt Enable 14 */
-    uint32_t CFIE15:1;         /*!< bit:     15  Cancellation Finished Interrupt Enable 15 */
-    uint32_t CFIE16:1;         /*!< bit:     16  Cancellation Finished Interrupt Enable 16 */
-    uint32_t CFIE17:1;         /*!< bit:     17  Cancellation Finished Interrupt Enable 17 */
-    uint32_t CFIE18:1;         /*!< bit:     18  Cancellation Finished Interrupt Enable 18 */
-    uint32_t CFIE19:1;         /*!< bit:     19  Cancellation Finished Interrupt Enable 19 */
-    uint32_t CFIE20:1;         /*!< bit:     20  Cancellation Finished Interrupt Enable 20 */
-    uint32_t CFIE21:1;         /*!< bit:     21  Cancellation Finished Interrupt Enable 21 */
-    uint32_t CFIE22:1;         /*!< bit:     22  Cancellation Finished Interrupt Enable 22 */
-    uint32_t CFIE23:1;         /*!< bit:     23  Cancellation Finished Interrupt Enable 23 */
-    uint32_t CFIE24:1;         /*!< bit:     24  Cancellation Finished Interrupt Enable 24 */
-    uint32_t CFIE25:1;         /*!< bit:     25  Cancellation Finished Interrupt Enable 25 */
-    uint32_t CFIE26:1;         /*!< bit:     26  Cancellation Finished Interrupt Enable 26 */
-    uint32_t CFIE27:1;         /*!< bit:     27  Cancellation Finished Interrupt Enable 27 */
-    uint32_t CFIE28:1;         /*!< bit:     28  Cancellation Finished Interrupt Enable 28 */
-    uint32_t CFIE29:1;         /*!< bit:     29  Cancellation Finished Interrupt Enable 29 */
-    uint32_t CFIE30:1;         /*!< bit:     30  Cancellation Finished Interrupt Enable 30 */
-    uint32_t CFIE31:1;         /*!< bit:     31  Cancellation Finished Interrupt Enable 31 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBCIE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBCIE_OFFSET           0xE4         /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */
-#define CAN_TXBCIE_RESETVALUE       0x00000000u  /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */
-
-#define CAN_TXBCIE_CFIE0_Pos        0            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */
-#define CAN_TXBCIE_CFIE0            (0x1u << CAN_TXBCIE_CFIE0_Pos)
-#define CAN_TXBCIE_CFIE1_Pos        1            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */
-#define CAN_TXBCIE_CFIE1            (0x1u << CAN_TXBCIE_CFIE1_Pos)
-#define CAN_TXBCIE_CFIE2_Pos        2            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */
-#define CAN_TXBCIE_CFIE2            (0x1u << CAN_TXBCIE_CFIE2_Pos)
-#define CAN_TXBCIE_CFIE3_Pos        3            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */
-#define CAN_TXBCIE_CFIE3            (0x1u << CAN_TXBCIE_CFIE3_Pos)
-#define CAN_TXBCIE_CFIE4_Pos        4            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */
-#define CAN_TXBCIE_CFIE4            (0x1u << CAN_TXBCIE_CFIE4_Pos)
-#define CAN_TXBCIE_CFIE5_Pos        5            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */
-#define CAN_TXBCIE_CFIE5            (0x1u << CAN_TXBCIE_CFIE5_Pos)
-#define CAN_TXBCIE_CFIE6_Pos        6            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */
-#define CAN_TXBCIE_CFIE6            (0x1u << CAN_TXBCIE_CFIE6_Pos)
-#define CAN_TXBCIE_CFIE7_Pos        7            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */
-#define CAN_TXBCIE_CFIE7            (0x1u << CAN_TXBCIE_CFIE7_Pos)
-#define CAN_TXBCIE_CFIE8_Pos        8            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */
-#define CAN_TXBCIE_CFIE8            (0x1u << CAN_TXBCIE_CFIE8_Pos)
-#define CAN_TXBCIE_CFIE9_Pos        9            /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */
-#define CAN_TXBCIE_CFIE9            (0x1u << CAN_TXBCIE_CFIE9_Pos)
-#define CAN_TXBCIE_CFIE10_Pos       10           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */
-#define CAN_TXBCIE_CFIE10           (0x1u << CAN_TXBCIE_CFIE10_Pos)
-#define CAN_TXBCIE_CFIE11_Pos       11           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */
-#define CAN_TXBCIE_CFIE11           (0x1u << CAN_TXBCIE_CFIE11_Pos)
-#define CAN_TXBCIE_CFIE12_Pos       12           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */
-#define CAN_TXBCIE_CFIE12           (0x1u << CAN_TXBCIE_CFIE12_Pos)
-#define CAN_TXBCIE_CFIE13_Pos       13           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */
-#define CAN_TXBCIE_CFIE13           (0x1u << CAN_TXBCIE_CFIE13_Pos)
-#define CAN_TXBCIE_CFIE14_Pos       14           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */
-#define CAN_TXBCIE_CFIE14           (0x1u << CAN_TXBCIE_CFIE14_Pos)
-#define CAN_TXBCIE_CFIE15_Pos       15           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */
-#define CAN_TXBCIE_CFIE15           (0x1u << CAN_TXBCIE_CFIE15_Pos)
-#define CAN_TXBCIE_CFIE16_Pos       16           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */
-#define CAN_TXBCIE_CFIE16           (0x1u << CAN_TXBCIE_CFIE16_Pos)
-#define CAN_TXBCIE_CFIE17_Pos       17           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */
-#define CAN_TXBCIE_CFIE17           (0x1u << CAN_TXBCIE_CFIE17_Pos)
-#define CAN_TXBCIE_CFIE18_Pos       18           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */
-#define CAN_TXBCIE_CFIE18           (0x1u << CAN_TXBCIE_CFIE18_Pos)
-#define CAN_TXBCIE_CFIE19_Pos       19           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */
-#define CAN_TXBCIE_CFIE19           (0x1u << CAN_TXBCIE_CFIE19_Pos)
-#define CAN_TXBCIE_CFIE20_Pos       20           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */
-#define CAN_TXBCIE_CFIE20           (0x1u << CAN_TXBCIE_CFIE20_Pos)
-#define CAN_TXBCIE_CFIE21_Pos       21           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */
-#define CAN_TXBCIE_CFIE21           (0x1u << CAN_TXBCIE_CFIE21_Pos)
-#define CAN_TXBCIE_CFIE22_Pos       22           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */
-#define CAN_TXBCIE_CFIE22           (0x1u << CAN_TXBCIE_CFIE22_Pos)
-#define CAN_TXBCIE_CFIE23_Pos       23           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */
-#define CAN_TXBCIE_CFIE23           (0x1u << CAN_TXBCIE_CFIE23_Pos)
-#define CAN_TXBCIE_CFIE24_Pos       24           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */
-#define CAN_TXBCIE_CFIE24           (0x1u << CAN_TXBCIE_CFIE24_Pos)
-#define CAN_TXBCIE_CFIE25_Pos       25           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */
-#define CAN_TXBCIE_CFIE25           (0x1u << CAN_TXBCIE_CFIE25_Pos)
-#define CAN_TXBCIE_CFIE26_Pos       26           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */
-#define CAN_TXBCIE_CFIE26           (0x1u << CAN_TXBCIE_CFIE26_Pos)
-#define CAN_TXBCIE_CFIE27_Pos       27           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */
-#define CAN_TXBCIE_CFIE27           (0x1u << CAN_TXBCIE_CFIE27_Pos)
-#define CAN_TXBCIE_CFIE28_Pos       28           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */
-#define CAN_TXBCIE_CFIE28           (0x1u << CAN_TXBCIE_CFIE28_Pos)
-#define CAN_TXBCIE_CFIE29_Pos       29           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */
-#define CAN_TXBCIE_CFIE29           (0x1u << CAN_TXBCIE_CFIE29_Pos)
-#define CAN_TXBCIE_CFIE30_Pos       30           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */
-#define CAN_TXBCIE_CFIE30           (0x1u << CAN_TXBCIE_CFIE30_Pos)
-#define CAN_TXBCIE_CFIE31_Pos       31           /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */
-#define CAN_TXBCIE_CFIE31           (0x1u << CAN_TXBCIE_CFIE31_Pos)
-#define CAN_TXBCIE_MASK             0xFFFFFFFFu  /**< \brief (CAN_TXBCIE) MASK Register */
-
-/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EFSA:16;          /*!< bit:  0..15  Event FIFO Start Address           */
-    uint32_t EFS:6;            /*!< bit: 16..21  Event FIFO Size                    */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t EFWM:6;           /*!< bit: 24..29  Event FIFO Watermark               */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXEFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFC_OFFSET            0xF0         /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */
-#define CAN_TXEFC_RESETVALUE        0x00000000u  /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */
-
-#define CAN_TXEFC_EFSA_Pos          0            /**< \brief (CAN_TXEFC) Event FIFO Start Address */
-#define CAN_TXEFC_EFSA_Msk          (0xFFFFu << CAN_TXEFC_EFSA_Pos)
-#define CAN_TXEFC_EFSA(value)       (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos))
-#define CAN_TXEFC_EFS_Pos           16           /**< \brief (CAN_TXEFC) Event FIFO Size */
-#define CAN_TXEFC_EFS_Msk           (0x3Fu << CAN_TXEFC_EFS_Pos)
-#define CAN_TXEFC_EFS(value)        (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos))
-#define CAN_TXEFC_EFWM_Pos          24           /**< \brief (CAN_TXEFC) Event FIFO Watermark */
-#define CAN_TXEFC_EFWM_Msk          (0x3Fu << CAN_TXEFC_EFWM_Pos)
-#define CAN_TXEFC_EFWM(value)       (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos))
-#define CAN_TXEFC_MASK              0x3F3FFFFFu  /**< \brief (CAN_TXEFC) MASK Register */
-
-/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/  32) Tx Event FIFO Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EFFL:6;           /*!< bit:  0.. 5  Event FIFO Fill Level              */
-    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint32_t EFGI:5;           /*!< bit:  8..12  Event FIFO Get Index               */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t EFPI:5;           /*!< bit: 16..20  Event FIFO Put Index               */
-    uint32_t :3;               /*!< bit: 21..23  Reserved                           */
-    uint32_t EFF:1;            /*!< bit:     24  Event FIFO Full                    */
-    uint32_t TEFL:1;           /*!< bit:     25  Tx Event FIFO Element Lost         */
-    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXEFS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFS_OFFSET            0xF4         /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */
-#define CAN_TXEFS_RESETVALUE        0x00000000u  /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */
-
-#define CAN_TXEFS_EFFL_Pos          0            /**< \brief (CAN_TXEFS) Event FIFO Fill Level */
-#define CAN_TXEFS_EFFL_Msk          (0x3Fu << CAN_TXEFS_EFFL_Pos)
-#define CAN_TXEFS_EFFL(value)       (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos))
-#define CAN_TXEFS_EFGI_Pos          8            /**< \brief (CAN_TXEFS) Event FIFO Get Index */
-#define CAN_TXEFS_EFGI_Msk          (0x1Fu << CAN_TXEFS_EFGI_Pos)
-#define CAN_TXEFS_EFGI(value)       (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos))
-#define CAN_TXEFS_EFPI_Pos          16           /**< \brief (CAN_TXEFS) Event FIFO Put Index */
-#define CAN_TXEFS_EFPI_Msk          (0x1Fu << CAN_TXEFS_EFPI_Pos)
-#define CAN_TXEFS_EFPI(value)       (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos))
-#define CAN_TXEFS_EFF_Pos           24           /**< \brief (CAN_TXEFS) Event FIFO Full */
-#define CAN_TXEFS_EFF               (0x1u << CAN_TXEFS_EFF_Pos)
-#define CAN_TXEFS_TEFL_Pos          25           /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */
-#define CAN_TXEFS_TEFL              (0x1u << CAN_TXEFS_TEFL_Pos)
-#define CAN_TXEFS_MASK              0x031F1F3Fu  /**< \brief (CAN_TXEFS) MASK Register */
-
-/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EFAI:5;           /*!< bit:  0.. 4  Event FIFO Acknowledge Index       */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXEFA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFA_OFFSET            0xF8         /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */
-#define CAN_TXEFA_RESETVALUE        0x00000000u  /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */
-
-#define CAN_TXEFA_EFAI_Pos          0            /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */
-#define CAN_TXEFA_EFAI_Msk          (0x1Fu << CAN_TXEFA_EFAI_Pos)
-#define CAN_TXEFA_EFAI(value)       (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos))
-#define CAN_TXEFA_MASK              0x0000001Fu  /**< \brief (CAN_TXEFA) MASK Register */
-
-/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ID:29;            /*!< bit:  0..28  Identifier                         */
-    uint32_t RTR:1;            /*!< bit:     29  Remote Transmission Request        */
-    uint32_t XTD:1;            /*!< bit:     30  Extended Identifier                */
-    uint32_t ESI:1;            /*!< bit:     31  Error State Indicator              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXBE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBE_0_OFFSET           0x00         /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */
-#define CAN_RXBE_0_RESETVALUE       0x00000000u  /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */
-
-#define CAN_RXBE_0_ID_Pos           0            /**< \brief (CAN_RXBE_0) Identifier */
-#define CAN_RXBE_0_ID_Msk           (0x1FFFFFFFu << CAN_RXBE_0_ID_Pos)
-#define CAN_RXBE_0_ID(value)        (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos))
-#define CAN_RXBE_0_RTR_Pos          29           /**< \brief (CAN_RXBE_0) Remote Transmission Request */
-#define CAN_RXBE_0_RTR              (0x1u << CAN_RXBE_0_RTR_Pos)
-#define CAN_RXBE_0_XTD_Pos          30           /**< \brief (CAN_RXBE_0) Extended Identifier */
-#define CAN_RXBE_0_XTD              (0x1u << CAN_RXBE_0_XTD_Pos)
-#define CAN_RXBE_0_ESI_Pos          31           /**< \brief (CAN_RXBE_0) Error State Indicator */
-#define CAN_RXBE_0_ESI              (0x1u << CAN_RXBE_0_ESI_Pos)
-#define CAN_RXBE_0_MASK             0xFFFFFFFFu  /**< \brief (CAN_RXBE_0) MASK Register */
-
-/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RXTS:16;          /*!< bit:  0..15  Rx Timestamp                       */
-    uint32_t DLC:4;            /*!< bit: 16..19  Data Length Code                   */
-    uint32_t BRS:1;            /*!< bit:     20  Bit Rate Search                    */
-    uint32_t FDF:1;            /*!< bit:     21  FD Format                          */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t FIDX:7;           /*!< bit: 24..30  Filter Index                       */
-    uint32_t ANMF:1;           /*!< bit:     31  Accepted Non-matching Frame        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXBE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBE_1_OFFSET           0x04         /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */
-#define CAN_RXBE_1_RESETVALUE       0x00000000u  /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */
-
-#define CAN_RXBE_1_RXTS_Pos         0            /**< \brief (CAN_RXBE_1) Rx Timestamp */
-#define CAN_RXBE_1_RXTS_Msk         (0xFFFFu << CAN_RXBE_1_RXTS_Pos)
-#define CAN_RXBE_1_RXTS(value)      (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos))
-#define CAN_RXBE_1_DLC_Pos          16           /**< \brief (CAN_RXBE_1) Data Length Code */
-#define CAN_RXBE_1_DLC_Msk          (0xFu << CAN_RXBE_1_DLC_Pos)
-#define CAN_RXBE_1_DLC(value)       (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos))
-#define CAN_RXBE_1_BRS_Pos          20           /**< \brief (CAN_RXBE_1) Bit Rate Search */
-#define CAN_RXBE_1_BRS              (0x1u << CAN_RXBE_1_BRS_Pos)
-#define CAN_RXBE_1_FDF_Pos          21           /**< \brief (CAN_RXBE_1) FD Format */
-#define CAN_RXBE_1_FDF              (0x1u << CAN_RXBE_1_FDF_Pos)
-#define CAN_RXBE_1_FIDX_Pos         24           /**< \brief (CAN_RXBE_1) Filter Index */
-#define CAN_RXBE_1_FIDX_Msk         (0x7Fu << CAN_RXBE_1_FIDX_Pos)
-#define CAN_RXBE_1_FIDX(value)      (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos))
-#define CAN_RXBE_1_ANMF_Pos         31           /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */
-#define CAN_RXBE_1_ANMF             (0x1u << CAN_RXBE_1_ANMF_Pos)
-#define CAN_RXBE_1_MASK             0xFF3FFFFFu  /**< \brief (CAN_RXBE_1) MASK Register */
-
-/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DB0:8;            /*!< bit:  0.. 7  Data Byte 0                        */
-    uint32_t DB1:8;            /*!< bit:  8..15  Data Byte 1                        */
-    uint32_t DB2:8;            /*!< bit: 16..23  Data Byte 2                        */
-    uint32_t DB3:8;            /*!< bit: 24..31  Data Byte 3                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXBE_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXBE_DATA_OFFSET        0x08         /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */
-#define CAN_RXBE_DATA_RESETVALUE    0x00000000u  /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */
-
-#define CAN_RXBE_DATA_DB0_Pos       0            /**< \brief (CAN_RXBE_DATA) Data Byte 0 */
-#define CAN_RXBE_DATA_DB0_Msk       (0xFFu << CAN_RXBE_DATA_DB0_Pos)
-#define CAN_RXBE_DATA_DB0(value)    (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos))
-#define CAN_RXBE_DATA_DB1_Pos       8            /**< \brief (CAN_RXBE_DATA) Data Byte 1 */
-#define CAN_RXBE_DATA_DB1_Msk       (0xFFu << CAN_RXBE_DATA_DB1_Pos)
-#define CAN_RXBE_DATA_DB1(value)    (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos))
-#define CAN_RXBE_DATA_DB2_Pos       16           /**< \brief (CAN_RXBE_DATA) Data Byte 2 */
-#define CAN_RXBE_DATA_DB2_Msk       (0xFFu << CAN_RXBE_DATA_DB2_Pos)
-#define CAN_RXBE_DATA_DB2(value)    (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos))
-#define CAN_RXBE_DATA_DB3_Pos       24           /**< \brief (CAN_RXBE_DATA) Data Byte 3 */
-#define CAN_RXBE_DATA_DB3_Msk       (0xFFu << CAN_RXBE_DATA_DB3_Pos)
-#define CAN_RXBE_DATA_DB3(value)    (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos))
-#define CAN_RXBE_DATA_MASK          0xFFFFFFFFu  /**< \brief (CAN_RXBE_DATA) MASK Register */
-
-/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ID:29;            /*!< bit:  0..28  Identifier                         */
-    uint32_t RTR:1;            /*!< bit:     29  Remote Transmission Request        */
-    uint32_t XTD:1;            /*!< bit:     30  Extended Identifier                */
-    uint32_t ESI:1;            /*!< bit:     31  Error State Indicator              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF0E_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0E_0_OFFSET          0x00         /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */
-#define CAN_RXF0E_0_RESETVALUE      0x00000000u  /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */
-
-#define CAN_RXF0E_0_ID_Pos          0            /**< \brief (CAN_RXF0E_0) Identifier */
-#define CAN_RXF0E_0_ID_Msk          (0x1FFFFFFFu << CAN_RXF0E_0_ID_Pos)
-#define CAN_RXF0E_0_ID(value)       (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos))
-#define CAN_RXF0E_0_RTR_Pos         29           /**< \brief (CAN_RXF0E_0) Remote Transmission Request */
-#define CAN_RXF0E_0_RTR             (0x1u << CAN_RXF0E_0_RTR_Pos)
-#define CAN_RXF0E_0_XTD_Pos         30           /**< \brief (CAN_RXF0E_0) Extended Identifier */
-#define CAN_RXF0E_0_XTD             (0x1u << CAN_RXF0E_0_XTD_Pos)
-#define CAN_RXF0E_0_ESI_Pos         31           /**< \brief (CAN_RXF0E_0) Error State Indicator */
-#define CAN_RXF0E_0_ESI             (0x1u << CAN_RXF0E_0_ESI_Pos)
-#define CAN_RXF0E_0_MASK            0xFFFFFFFFu  /**< \brief (CAN_RXF0E_0) MASK Register */
-
-/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RXTS:16;          /*!< bit:  0..15  Rx Timestamp                       */
-    uint32_t DLC:4;            /*!< bit: 16..19  Data Length Code                   */
-    uint32_t BRS:1;            /*!< bit:     20  Bit Rate Search                    */
-    uint32_t FDF:1;            /*!< bit:     21  FD Format                          */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t FIDX:7;           /*!< bit: 24..30  Filter Index                       */
-    uint32_t ANMF:1;           /*!< bit:     31  Accepted Non-matching Frame        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF0E_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0E_1_OFFSET          0x04         /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */
-#define CAN_RXF0E_1_RESETVALUE      0x00000000u  /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */
-
-#define CAN_RXF0E_1_RXTS_Pos        0            /**< \brief (CAN_RXF0E_1) Rx Timestamp */
-#define CAN_RXF0E_1_RXTS_Msk        (0xFFFFu << CAN_RXF0E_1_RXTS_Pos)
-#define CAN_RXF0E_1_RXTS(value)     (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos))
-#define CAN_RXF0E_1_DLC_Pos         16           /**< \brief (CAN_RXF0E_1) Data Length Code */
-#define CAN_RXF0E_1_DLC_Msk         (0xFu << CAN_RXF0E_1_DLC_Pos)
-#define CAN_RXF0E_1_DLC(value)      (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos))
-#define CAN_RXF0E_1_BRS_Pos         20           /**< \brief (CAN_RXF0E_1) Bit Rate Search */
-#define CAN_RXF0E_1_BRS             (0x1u << CAN_RXF0E_1_BRS_Pos)
-#define CAN_RXF0E_1_FDF_Pos         21           /**< \brief (CAN_RXF0E_1) FD Format */
-#define CAN_RXF0E_1_FDF             (0x1u << CAN_RXF0E_1_FDF_Pos)
-#define CAN_RXF0E_1_FIDX_Pos        24           /**< \brief (CAN_RXF0E_1) Filter Index */
-#define CAN_RXF0E_1_FIDX_Msk        (0x7Fu << CAN_RXF0E_1_FIDX_Pos)
-#define CAN_RXF0E_1_FIDX(value)     (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos))
-#define CAN_RXF0E_1_ANMF_Pos        31           /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */
-#define CAN_RXF0E_1_ANMF            (0x1u << CAN_RXF0E_1_ANMF_Pos)
-#define CAN_RXF0E_1_MASK            0xFF3FFFFFu  /**< \brief (CAN_RXF0E_1) MASK Register */
-
-/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DB0:8;            /*!< bit:  0.. 7  Data Byte 0                        */
-    uint32_t DB1:8;            /*!< bit:  8..15  Data Byte 1                        */
-    uint32_t DB2:8;            /*!< bit: 16..23  Data Byte 2                        */
-    uint32_t DB3:8;            /*!< bit: 24..31  Data Byte 3                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF0E_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF0E_DATA_OFFSET       0x08         /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */
-#define CAN_RXF0E_DATA_RESETVALUE   0x00000000u  /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */
-
-#define CAN_RXF0E_DATA_DB0_Pos      0            /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */
-#define CAN_RXF0E_DATA_DB0_Msk      (0xFFu << CAN_RXF0E_DATA_DB0_Pos)
-#define CAN_RXF0E_DATA_DB0(value)   (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos))
-#define CAN_RXF0E_DATA_DB1_Pos      8            /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */
-#define CAN_RXF0E_DATA_DB1_Msk      (0xFFu << CAN_RXF0E_DATA_DB1_Pos)
-#define CAN_RXF0E_DATA_DB1(value)   (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos))
-#define CAN_RXF0E_DATA_DB2_Pos      16           /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */
-#define CAN_RXF0E_DATA_DB2_Msk      (0xFFu << CAN_RXF0E_DATA_DB2_Pos)
-#define CAN_RXF0E_DATA_DB2(value)   (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos))
-#define CAN_RXF0E_DATA_DB3_Pos      24           /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */
-#define CAN_RXF0E_DATA_DB3_Msk      (0xFFu << CAN_RXF0E_DATA_DB3_Pos)
-#define CAN_RXF0E_DATA_DB3(value)   (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos))
-#define CAN_RXF0E_DATA_MASK         0xFFFFFFFFu  /**< \brief (CAN_RXF0E_DATA) MASK Register */
-
-/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ID:29;            /*!< bit:  0..28  Identifier                         */
-    uint32_t RTR:1;            /*!< bit:     29  Remote Transmission Request        */
-    uint32_t XTD:1;            /*!< bit:     30  Extended Identifier                */
-    uint32_t ESI:1;            /*!< bit:     31  Error State Indicator              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF1E_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1E_0_OFFSET          0x00         /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */
-#define CAN_RXF1E_0_RESETVALUE      0x00000000u  /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */
-
-#define CAN_RXF1E_0_ID_Pos          0            /**< \brief (CAN_RXF1E_0) Identifier */
-#define CAN_RXF1E_0_ID_Msk          (0x1FFFFFFFu << CAN_RXF1E_0_ID_Pos)
-#define CAN_RXF1E_0_ID(value)       (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos))
-#define CAN_RXF1E_0_RTR_Pos         29           /**< \brief (CAN_RXF1E_0) Remote Transmission Request */
-#define CAN_RXF1E_0_RTR             (0x1u << CAN_RXF1E_0_RTR_Pos)
-#define CAN_RXF1E_0_XTD_Pos         30           /**< \brief (CAN_RXF1E_0) Extended Identifier */
-#define CAN_RXF1E_0_XTD             (0x1u << CAN_RXF1E_0_XTD_Pos)
-#define CAN_RXF1E_0_ESI_Pos         31           /**< \brief (CAN_RXF1E_0) Error State Indicator */
-#define CAN_RXF1E_0_ESI             (0x1u << CAN_RXF1E_0_ESI_Pos)
-#define CAN_RXF1E_0_MASK            0xFFFFFFFFu  /**< \brief (CAN_RXF1E_0) MASK Register */
-
-/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RXTS:16;          /*!< bit:  0..15  Rx Timestamp                       */
-    uint32_t DLC:4;            /*!< bit: 16..19  Data Length Code                   */
-    uint32_t BRS:1;            /*!< bit:     20  Bit Rate Search                    */
-    uint32_t FDF:1;            /*!< bit:     21  FD Format                          */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t FIDX:7;           /*!< bit: 24..30  Filter Index                       */
-    uint32_t ANMF:1;           /*!< bit:     31  Accepted Non-matching Frame        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF1E_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1E_1_OFFSET          0x04         /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */
-#define CAN_RXF1E_1_RESETVALUE      0x00000000u  /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */
-
-#define CAN_RXF1E_1_RXTS_Pos        0            /**< \brief (CAN_RXF1E_1) Rx Timestamp */
-#define CAN_RXF1E_1_RXTS_Msk        (0xFFFFu << CAN_RXF1E_1_RXTS_Pos)
-#define CAN_RXF1E_1_RXTS(value)     (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos))
-#define CAN_RXF1E_1_DLC_Pos         16           /**< \brief (CAN_RXF1E_1) Data Length Code */
-#define CAN_RXF1E_1_DLC_Msk         (0xFu << CAN_RXF1E_1_DLC_Pos)
-#define CAN_RXF1E_1_DLC(value)      (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos))
-#define CAN_RXF1E_1_BRS_Pos         20           /**< \brief (CAN_RXF1E_1) Bit Rate Search */
-#define CAN_RXF1E_1_BRS             (0x1u << CAN_RXF1E_1_BRS_Pos)
-#define CAN_RXF1E_1_FDF_Pos         21           /**< \brief (CAN_RXF1E_1) FD Format */
-#define CAN_RXF1E_1_FDF             (0x1u << CAN_RXF1E_1_FDF_Pos)
-#define CAN_RXF1E_1_FIDX_Pos        24           /**< \brief (CAN_RXF1E_1) Filter Index */
-#define CAN_RXF1E_1_FIDX_Msk        (0x7Fu << CAN_RXF1E_1_FIDX_Pos)
-#define CAN_RXF1E_1_FIDX(value)     (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos))
-#define CAN_RXF1E_1_ANMF_Pos        31           /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */
-#define CAN_RXF1E_1_ANMF            (0x1u << CAN_RXF1E_1_ANMF_Pos)
-#define CAN_RXF1E_1_MASK            0xFF3FFFFFu  /**< \brief (CAN_RXF1E_1) MASK Register */
-
-/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DB0:8;            /*!< bit:  0.. 7  Data Byte 0                        */
-    uint32_t DB1:8;            /*!< bit:  8..15  Data Byte 1                        */
-    uint32_t DB2:8;            /*!< bit: 16..23  Data Byte 2                        */
-    uint32_t DB3:8;            /*!< bit: 24..31  Data Byte 3                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_RXF1E_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_RXF1E_DATA_OFFSET       0x08         /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */
-#define CAN_RXF1E_DATA_RESETVALUE   0x00000000u  /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */
-
-#define CAN_RXF1E_DATA_DB0_Pos      0            /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */
-#define CAN_RXF1E_DATA_DB0_Msk      (0xFFu << CAN_RXF1E_DATA_DB0_Pos)
-#define CAN_RXF1E_DATA_DB0(value)   (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos))
-#define CAN_RXF1E_DATA_DB1_Pos      8            /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */
-#define CAN_RXF1E_DATA_DB1_Msk      (0xFFu << CAN_RXF1E_DATA_DB1_Pos)
-#define CAN_RXF1E_DATA_DB1(value)   (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos))
-#define CAN_RXF1E_DATA_DB2_Pos      16           /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */
-#define CAN_RXF1E_DATA_DB2_Msk      (0xFFu << CAN_RXF1E_DATA_DB2_Pos)
-#define CAN_RXF1E_DATA_DB2(value)   (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos))
-#define CAN_RXF1E_DATA_DB3_Pos      24           /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */
-#define CAN_RXF1E_DATA_DB3_Msk      (0xFFu << CAN_RXF1E_DATA_DB3_Pos)
-#define CAN_RXF1E_DATA_DB3(value)   (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos))
-#define CAN_RXF1E_DATA_MASK         0xFFFFFFFFu  /**< \brief (CAN_RXF1E_DATA) MASK Register */
-
-/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SFID2:11;         /*!< bit:  0..10  Standard Filter ID 2               */
-    uint32_t :5;               /*!< bit: 11..15  Reserved                           */
-    uint32_t SFID1:11;         /*!< bit: 16..26  Standard Filter ID 1               */
-    uint32_t SFEC:3;           /*!< bit: 27..29  Standard Filter Element Configuration */
-    uint32_t SFT:2;            /*!< bit: 30..31  Standard Filter Type               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_SIDFE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_SIDFE_0_OFFSET          0x00         /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */
-#define CAN_SIDFE_0_RESETVALUE      0x00000000u  /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */
-
-#define CAN_SIDFE_0_SFID2_Pos       0            /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */
-#define CAN_SIDFE_0_SFID2_Msk       (0x7FFu << CAN_SIDFE_0_SFID2_Pos)
-#define CAN_SIDFE_0_SFID2(value)    (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos))
-#define CAN_SIDFE_0_SFID1_Pos       16           /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */
-#define CAN_SIDFE_0_SFID1_Msk       (0x7FFu << CAN_SIDFE_0_SFID1_Pos)
-#define CAN_SIDFE_0_SFID1(value)    (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos))
-#define CAN_SIDFE_0_SFEC_Pos        27           /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */
-#define CAN_SIDFE_0_SFEC_Msk        (0x7u << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC(value)     (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos))
-#define   CAN_SIDFE_0_SFEC_DISABLE_Val    0x0u   /**< \brief (CAN_SIDFE_0) Disable filter element */
-#define   CAN_SIDFE_0_SFEC_STF0M_Val      0x1u   /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */
-#define   CAN_SIDFE_0_SFEC_STF1M_Val      0x2u   /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */
-#define   CAN_SIDFE_0_SFEC_REJECT_Val     0x3u   /**< \brief (CAN_SIDFE_0) Reject ID if filter match */
-#define   CAN_SIDFE_0_SFEC_PRIORITY_Val   0x4u   /**< \brief (CAN_SIDFE_0) Set priority if filter match */
-#define   CAN_SIDFE_0_SFEC_PRIF0M_Val     0x5u   /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */
-#define   CAN_SIDFE_0_SFEC_PRIF1M_Val     0x6u   /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */
-#define   CAN_SIDFE_0_SFEC_STRXBUF_Val    0x7u   /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */
-#define CAN_SIDFE_0_SFEC_DISABLE    (CAN_SIDFE_0_SFEC_DISABLE_Val  << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_STF0M      (CAN_SIDFE_0_SFEC_STF0M_Val    << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_STF1M      (CAN_SIDFE_0_SFEC_STF1M_Val    << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_REJECT     (CAN_SIDFE_0_SFEC_REJECT_Val   << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_PRIORITY   (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_PRIF0M     (CAN_SIDFE_0_SFEC_PRIF0M_Val   << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_PRIF1M     (CAN_SIDFE_0_SFEC_PRIF1M_Val   << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFEC_STRXBUF    (CAN_SIDFE_0_SFEC_STRXBUF_Val  << CAN_SIDFE_0_SFEC_Pos)
-#define CAN_SIDFE_0_SFT_Pos         30           /**< \brief (CAN_SIDFE_0) Standard Filter Type */
-#define CAN_SIDFE_0_SFT_Msk         (0x3u << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_SFT(value)      (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos))
-#define   CAN_SIDFE_0_SFT_RANGE_Val       0x0u   /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */
-#define   CAN_SIDFE_0_SFT_DUAL_Val        0x1u   /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */
-#define   CAN_SIDFE_0_SFT_CLASSIC_Val     0x2u   /**< \brief (CAN_SIDFE_0) Classic filter */
-#define CAN_SIDFE_0_SFT_RANGE       (CAN_SIDFE_0_SFT_RANGE_Val     << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_SFT_DUAL        (CAN_SIDFE_0_SFT_DUAL_Val      << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_SFT_CLASSIC     (CAN_SIDFE_0_SFT_CLASSIC_Val   << CAN_SIDFE_0_SFT_Pos)
-#define CAN_SIDFE_0_MASK            0xFFFF07FFu  /**< \brief (CAN_SIDFE_0) MASK Register */
-
-/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ID:29;            /*!< bit:  0..28  Identifier                         */
-    uint32_t RTR:1;            /*!< bit:     29  Remote Transmission Request        */
-    uint32_t XTD:1;            /*!< bit:     30  Extended Identifier                */
-    uint32_t ESI:1;            /*!< bit:     31  Error State Indicator              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBE_0_OFFSET           0x00         /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */
-#define CAN_TXBE_0_RESETVALUE       0x00000000u  /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */
-
-#define CAN_TXBE_0_ID_Pos           0            /**< \brief (CAN_TXBE_0) Identifier */
-#define CAN_TXBE_0_ID_Msk           (0x1FFFFFFFu << CAN_TXBE_0_ID_Pos)
-#define CAN_TXBE_0_ID(value)        (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos))
-#define CAN_TXBE_0_RTR_Pos          29           /**< \brief (CAN_TXBE_0) Remote Transmission Request */
-#define CAN_TXBE_0_RTR              (0x1u << CAN_TXBE_0_RTR_Pos)
-#define CAN_TXBE_0_XTD_Pos          30           /**< \brief (CAN_TXBE_0) Extended Identifier */
-#define CAN_TXBE_0_XTD              (0x1u << CAN_TXBE_0_XTD_Pos)
-#define CAN_TXBE_0_ESI_Pos          31           /**< \brief (CAN_TXBE_0) Error State Indicator */
-#define CAN_TXBE_0_ESI              (0x1u << CAN_TXBE_0_ESI_Pos)
-#define CAN_TXBE_0_MASK             0xFFFFFFFFu  /**< \brief (CAN_TXBE_0) MASK Register */
-
-/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t DLC:4;            /*!< bit: 16..19  Identifier                         */
-    uint32_t BRS:1;            /*!< bit:     20  Bit Rate Search                    */
-    uint32_t FDF:1;            /*!< bit:     21  FD Format                          */
-    uint32_t :1;               /*!< bit:     22  Reserved                           */
-    uint32_t EFC:1;            /*!< bit:     23  Event FIFO Control                 */
-    uint32_t MM:8;             /*!< bit: 24..31  Message Marker                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBE_1_OFFSET           0x04         /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */
-#define CAN_TXBE_1_RESETVALUE       0x00000000u  /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */
-
-#define CAN_TXBE_1_DLC_Pos          16           /**< \brief (CAN_TXBE_1) Identifier */
-#define CAN_TXBE_1_DLC_Msk          (0xFu << CAN_TXBE_1_DLC_Pos)
-#define CAN_TXBE_1_DLC(value)       (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos))
-#define CAN_TXBE_1_BRS_Pos          20           /**< \brief (CAN_TXBE_1) Bit Rate Search */
-#define CAN_TXBE_1_BRS              (0x1u << CAN_TXBE_1_BRS_Pos)
-#define CAN_TXBE_1_FDF_Pos          21           /**< \brief (CAN_TXBE_1) FD Format */
-#define CAN_TXBE_1_FDF              (0x1u << CAN_TXBE_1_FDF_Pos)
-#define CAN_TXBE_1_EFC_Pos          23           /**< \brief (CAN_TXBE_1) Event FIFO Control */
-#define CAN_TXBE_1_EFC              (0x1u << CAN_TXBE_1_EFC_Pos)
-#define CAN_TXBE_1_MM_Pos           24           /**< \brief (CAN_TXBE_1) Message Marker */
-#define CAN_TXBE_1_MM_Msk           (0xFFu << CAN_TXBE_1_MM_Pos)
-#define CAN_TXBE_1_MM(value)        (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos))
-#define CAN_TXBE_1_MASK             0xFFBF0000u  /**< \brief (CAN_TXBE_1) MASK Register */
-
-/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DB0:8;            /*!< bit:  0.. 7  Data Byte 0                        */
-    uint32_t DB1:8;            /*!< bit:  8..15  Data Byte 1                        */
-    uint32_t DB2:8;            /*!< bit: 16..23  Data Byte 2                        */
-    uint32_t DB3:8;            /*!< bit: 24..31  Data Byte 3                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXBE_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXBE_DATA_OFFSET        0x08         /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */
-#define CAN_TXBE_DATA_RESETVALUE    0x00000000u  /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */
-
-#define CAN_TXBE_DATA_DB0_Pos       0            /**< \brief (CAN_TXBE_DATA) Data Byte 0 */
-#define CAN_TXBE_DATA_DB0_Msk       (0xFFu << CAN_TXBE_DATA_DB0_Pos)
-#define CAN_TXBE_DATA_DB0(value)    (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos))
-#define CAN_TXBE_DATA_DB1_Pos       8            /**< \brief (CAN_TXBE_DATA) Data Byte 1 */
-#define CAN_TXBE_DATA_DB1_Msk       (0xFFu << CAN_TXBE_DATA_DB1_Pos)
-#define CAN_TXBE_DATA_DB1(value)    (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos))
-#define CAN_TXBE_DATA_DB2_Pos       16           /**< \brief (CAN_TXBE_DATA) Data Byte 2 */
-#define CAN_TXBE_DATA_DB2_Msk       (0xFFu << CAN_TXBE_DATA_DB2_Pos)
-#define CAN_TXBE_DATA_DB2(value)    (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos))
-#define CAN_TXBE_DATA_DB3_Pos       24           /**< \brief (CAN_TXBE_DATA) Data Byte 3 */
-#define CAN_TXBE_DATA_DB3_Msk       (0xFFu << CAN_TXBE_DATA_DB3_Pos)
-#define CAN_TXBE_DATA_DB3(value)    (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos))
-#define CAN_TXBE_DATA_MASK          0xFFFFFFFFu  /**< \brief (CAN_TXBE_DATA) MASK Register */
-
-/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ID:29;            /*!< bit:  0..28  Identifier                         */
-    uint32_t RTR:1;            /*!< bit:     29  Remote Transmission Request        */
-    uint32_t XTD:1;            /*!< bit:     30  Extended Indentifier               */
-    uint32_t ESI:1;            /*!< bit:     31  Error State Indicator              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXEFE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFE_0_OFFSET          0x00         /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */
-#define CAN_TXEFE_0_RESETVALUE      0x00000000u  /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */
-
-#define CAN_TXEFE_0_ID_Pos          0            /**< \brief (CAN_TXEFE_0) Identifier */
-#define CAN_TXEFE_0_ID_Msk          (0x1FFFFFFFu << CAN_TXEFE_0_ID_Pos)
-#define CAN_TXEFE_0_ID(value)       (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos))
-#define CAN_TXEFE_0_RTR_Pos         29           /**< \brief (CAN_TXEFE_0) Remote Transmission Request */
-#define CAN_TXEFE_0_RTR             (0x1u << CAN_TXEFE_0_RTR_Pos)
-#define CAN_TXEFE_0_XTD_Pos         30           /**< \brief (CAN_TXEFE_0) Extended Indentifier */
-#define CAN_TXEFE_0_XTD             (0x1u << CAN_TXEFE_0_XTD_Pos)
-#define CAN_TXEFE_0_ESI_Pos         31           /**< \brief (CAN_TXEFE_0) Error State Indicator */
-#define CAN_TXEFE_0_ESI             (0x1u << CAN_TXEFE_0_ESI_Pos)
-#define CAN_TXEFE_0_MASK            0xFFFFFFFFu  /**< \brief (CAN_TXEFE_0) MASK Register */
-
-/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TXTS:16;          /*!< bit:  0..15  Tx Timestamp                       */
-    uint32_t DLC:4;            /*!< bit: 16..19  Data Length Code                   */
-    uint32_t BRS:1;            /*!< bit:     20  Bit Rate Search                    */
-    uint32_t FDF:1;            /*!< bit:     21  FD Format                          */
-    uint32_t ET:2;             /*!< bit: 22..23  Event Type                         */
-    uint32_t MM:8;             /*!< bit: 24..31  Message Marker                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_TXEFE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_TXEFE_1_OFFSET          0x04         /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */
-#define CAN_TXEFE_1_RESETVALUE      0x00000000u  /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */
-
-#define CAN_TXEFE_1_TXTS_Pos        0            /**< \brief (CAN_TXEFE_1) Tx Timestamp */
-#define CAN_TXEFE_1_TXTS_Msk        (0xFFFFu << CAN_TXEFE_1_TXTS_Pos)
-#define CAN_TXEFE_1_TXTS(value)     (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos))
-#define CAN_TXEFE_1_DLC_Pos         16           /**< \brief (CAN_TXEFE_1) Data Length Code */
-#define CAN_TXEFE_1_DLC_Msk         (0xFu << CAN_TXEFE_1_DLC_Pos)
-#define CAN_TXEFE_1_DLC(value)      (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos))
-#define CAN_TXEFE_1_BRS_Pos         20           /**< \brief (CAN_TXEFE_1) Bit Rate Search */
-#define CAN_TXEFE_1_BRS             (0x1u << CAN_TXEFE_1_BRS_Pos)
-#define CAN_TXEFE_1_FDF_Pos         21           /**< \brief (CAN_TXEFE_1) FD Format */
-#define CAN_TXEFE_1_FDF             (0x1u << CAN_TXEFE_1_FDF_Pos)
-#define CAN_TXEFE_1_ET_Pos          22           /**< \brief (CAN_TXEFE_1) Event Type */
-#define CAN_TXEFE_1_ET_Msk          (0x3u << CAN_TXEFE_1_ET_Pos)
-#define CAN_TXEFE_1_ET(value)       (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos))
-#define   CAN_TXEFE_1_ET_TXE_Val          0x1u   /**< \brief (CAN_TXEFE_1) Tx event */
-#define   CAN_TXEFE_1_ET_TXC_Val          0x2u   /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */
-#define CAN_TXEFE_1_ET_TXE          (CAN_TXEFE_1_ET_TXE_Val        << CAN_TXEFE_1_ET_Pos)
-#define CAN_TXEFE_1_ET_TXC          (CAN_TXEFE_1_ET_TXC_Val        << CAN_TXEFE_1_ET_Pos)
-#define CAN_TXEFE_1_MM_Pos          24           /**< \brief (CAN_TXEFE_1) Message Marker */
-#define CAN_TXEFE_1_MM_Msk          (0xFFu << CAN_TXEFE_1_MM_Pos)
-#define CAN_TXEFE_1_MM(value)       (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos))
-#define CAN_TXEFE_1_MASK            0xFFFFFFFFu  /**< \brief (CAN_TXEFE_1) MASK Register */
-
-/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EFID1:29;         /*!< bit:  0..28  Extended Filter ID 1               */
-    uint32_t EFEC:3;           /*!< bit: 29..31  Extended Filter Element Configuration */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_XIDFE_0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDFE_0_OFFSET          0x00         /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */
-#define CAN_XIDFE_0_RESETVALUE      0x00000000u  /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */
-
-#define CAN_XIDFE_0_EFID1_Pos       0            /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */
-#define CAN_XIDFE_0_EFID1_Msk       (0x1FFFFFFFu << CAN_XIDFE_0_EFID1_Pos)
-#define CAN_XIDFE_0_EFID1(value)    (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos))
-#define CAN_XIDFE_0_EFEC_Pos        29           /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */
-#define CAN_XIDFE_0_EFEC_Msk        (0x7u << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC(value)     (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos))
-#define   CAN_XIDFE_0_EFEC_DISABLE_Val    0x0u   /**< \brief (CAN_XIDFE_0) Disable filter element */
-#define   CAN_XIDFE_0_EFEC_STF0M_Val      0x1u   /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */
-#define   CAN_XIDFE_0_EFEC_STF1M_Val      0x2u   /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */
-#define   CAN_XIDFE_0_EFEC_REJECT_Val     0x3u   /**< \brief (CAN_XIDFE_0) Reject ID if filter match */
-#define   CAN_XIDFE_0_EFEC_PRIORITY_Val   0x4u   /**< \brief (CAN_XIDFE_0) Set priority if filter match */
-#define   CAN_XIDFE_0_EFEC_PRIF0M_Val     0x5u   /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */
-#define   CAN_XIDFE_0_EFEC_PRIF1M_Val     0x6u   /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */
-#define   CAN_XIDFE_0_EFEC_STRXBUF_Val    0x7u   /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */
-#define CAN_XIDFE_0_EFEC_DISABLE    (CAN_XIDFE_0_EFEC_DISABLE_Val  << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_STF0M      (CAN_XIDFE_0_EFEC_STF0M_Val    << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_STF1M      (CAN_XIDFE_0_EFEC_STF1M_Val    << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_REJECT     (CAN_XIDFE_0_EFEC_REJECT_Val   << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_PRIORITY   (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_PRIF0M     (CAN_XIDFE_0_EFEC_PRIF0M_Val   << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_PRIF1M     (CAN_XIDFE_0_EFEC_PRIF1M_Val   << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_EFEC_STRXBUF    (CAN_XIDFE_0_EFEC_STRXBUF_Val  << CAN_XIDFE_0_EFEC_Pos)
-#define CAN_XIDFE_0_MASK            0xFFFFFFFFu  /**< \brief (CAN_XIDFE_0) MASK Register */
-
-/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EFID2:29;         /*!< bit:  0..28  Extended Filter ID 2               */
-    uint32_t :1;               /*!< bit:     29  Reserved                           */
-    uint32_t EFT:2;            /*!< bit: 30..31  Extended Filter Type               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CAN_XIDFE_1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CAN_XIDFE_1_OFFSET          0x04         /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */
-#define CAN_XIDFE_1_RESETVALUE      0x00000000u  /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */
-
-#define CAN_XIDFE_1_EFID2_Pos       0            /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */
-#define CAN_XIDFE_1_EFID2_Msk       (0x1FFFFFFFu << CAN_XIDFE_1_EFID2_Pos)
-#define CAN_XIDFE_1_EFID2(value)    (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos))
-#define CAN_XIDFE_1_EFT_Pos         30           /**< \brief (CAN_XIDFE_1) Extended Filter Type */
-#define CAN_XIDFE_1_EFT_Msk         (0x3u << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT(value)      (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos))
-#define   CAN_XIDFE_1_EFT_RANGEM_Val      0x0u   /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */
-#define   CAN_XIDFE_1_EFT_DUAL_Val        0x1u   /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */
-#define   CAN_XIDFE_1_EFT_CLASSIC_Val     0x2u   /**< \brief (CAN_XIDFE_1) Classic filter */
-#define   CAN_XIDFE_1_EFT_RANGE_Val       0x3u   /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */
-#define CAN_XIDFE_1_EFT_RANGEM      (CAN_XIDFE_1_EFT_RANGEM_Val    << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT_DUAL        (CAN_XIDFE_1_EFT_DUAL_Val      << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT_CLASSIC     (CAN_XIDFE_1_EFT_CLASSIC_Val   << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_EFT_RANGE       (CAN_XIDFE_1_EFT_RANGE_Val     << CAN_XIDFE_1_EFT_Pos)
-#define CAN_XIDFE_1_MASK            0xDFFFFFFFu  /**< \brief (CAN_XIDFE_1) MASK Register */
-
-/** \brief CAN APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __I  CAN_CREL_Type             CREL;        /**< \brief Offset: 0x00 (R/  32) Core Release */
-  __I  CAN_ENDN_Type             ENDN;        /**< \brief Offset: 0x04 (R/  32) Endian */
-  __IO CAN_MRCFG_Type            MRCFG;       /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */
-  __IO CAN_DBTP_Type             DBTP;        /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */
-  __IO CAN_TEST_Type             TEST;        /**< \brief Offset: 0x10 (R/W 32) Test */
-  __IO CAN_RWD_Type              RWD;         /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */
-  __IO CAN_CCCR_Type             CCCR;        /**< \brief Offset: 0x18 (R/W 32) CC Control */
-  __IO CAN_NBTP_Type             NBTP;        /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */
-  __IO CAN_TSCC_Type             TSCC;        /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */
-  __I  CAN_TSCV_Type             TSCV;        /**< \brief Offset: 0x24 (R/  32) Timestamp Counter Value */
-  __IO CAN_TOCC_Type             TOCC;        /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */
-  __IO CAN_TOCV_Type             TOCV;        /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */
-       RoReg8                    Reserved1[0x10];
-  __I  CAN_ECR_Type              ECR;         /**< \brief Offset: 0x40 (R/  32) Error Counter */
-  __I  CAN_PSR_Type              PSR;         /**< \brief Offset: 0x44 (R/  32) Protocol Status */
-  __IO CAN_TDCR_Type             TDCR;        /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */
-       RoReg8                    Reserved2[0x4];
-  __IO CAN_IR_Type               IR;          /**< \brief Offset: 0x50 (R/W 32) Interrupt */
-  __IO CAN_IE_Type               IE;          /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */
-  __IO CAN_ILS_Type              ILS;         /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */
-  __IO CAN_ILE_Type              ILE;         /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */
-       RoReg8                    Reserved3[0x20];
-  __IO CAN_GFC_Type              GFC;         /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */
-  __IO CAN_SIDFC_Type            SIDFC;       /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */
-  __IO CAN_XIDFC_Type            XIDFC;       /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */
-       RoReg8                    Reserved4[0x4];
-  __IO CAN_XIDAM_Type            XIDAM;       /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */
-  __I  CAN_HPMS_Type             HPMS;        /**< \brief Offset: 0x94 (R/  32) High Priority Message Status */
-  __IO CAN_NDAT1_Type            NDAT1;       /**< \brief Offset: 0x98 (R/W 32) New Data 1 */
-  __IO CAN_NDAT2_Type            NDAT2;       /**< \brief Offset: 0x9C (R/W 32) New Data 2 */
-  __IO CAN_RXF0C_Type            RXF0C;       /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */
-  __I  CAN_RXF0S_Type            RXF0S;       /**< \brief Offset: 0xA4 (R/  32) Rx FIFO 0 Status */
-  __IO CAN_RXF0A_Type            RXF0A;       /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */
-  __IO CAN_RXBC_Type             RXBC;        /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */
-  __IO CAN_RXF1C_Type            RXF1C;       /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */
-  __I  CAN_RXF1S_Type            RXF1S;       /**< \brief Offset: 0xB4 (R/  32) Rx FIFO 1 Status */
-  __IO CAN_RXF1A_Type            RXF1A;       /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */
-  __IO CAN_RXESC_Type            RXESC;       /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */
-  __IO CAN_TXBC_Type             TXBC;        /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */
-  __I  CAN_TXFQS_Type            TXFQS;       /**< \brief Offset: 0xC4 (R/  32) Tx FIFO / Queue Status */
-  __IO CAN_TXESC_Type            TXESC;       /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */
-  __I  CAN_TXBRP_Type            TXBRP;       /**< \brief Offset: 0xCC (R/  32) Tx Buffer Request Pending */
-  __IO CAN_TXBAR_Type            TXBAR;       /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */
-  __IO CAN_TXBCR_Type            TXBCR;       /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */
-  __I  CAN_TXBTO_Type            TXBTO;       /**< \brief Offset: 0xD8 (R/  32) Tx Buffer Transmission Occurred */
-  __I  CAN_TXBCF_Type            TXBCF;       /**< \brief Offset: 0xDC (R/  32) Tx Buffer Cancellation Finished */
-  __IO CAN_TXBTIE_Type           TXBTIE;      /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */
-  __IO CAN_TXBCIE_Type           TXBCIE;      /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */
-       RoReg8                    Reserved5[0x8];
-  __IO CAN_TXEFC_Type            TXEFC;       /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */
-  __I  CAN_TXEFS_Type            TXEFS;       /**< \brief Offset: 0xF4 (R/  32) Tx Event FIFO Status */
-  __IO CAN_TXEFA_Type            TXEFA;       /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */
-} Can;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_rxbe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO CAN_RXBE_0_Type           RXBE_0;      /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */
-  __IO CAN_RXBE_1_Type           RXBE_1;      /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */
-  __IO CAN_RXBE_DATA_Type        RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */
-} CanMramRxbe
-#ifdef __GNUC__
-  __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_rxf0e hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO CAN_RXF0E_0_Type          RXF0E_0;     /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */
-  __IO CAN_RXF0E_1_Type          RXF0E_1;     /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */
-  __IO CAN_RXF0E_DATA_Type       RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */
-} CanMramRxf0e
-#ifdef __GNUC__
-  __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_rxf1e hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO CAN_RXF1E_0_Type          RXF1E_0;     /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */
-  __IO CAN_RXF1E_1_Type          RXF1E_1;     /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */
-  __IO CAN_RXF1E_DATA_Type       RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */
-} CanMramRxf1e
-#ifdef __GNUC__
-  __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_sidfe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO CAN_SIDFE_0_Type          SIDFE_0;     /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */
-} CanMramSidfe
-#ifdef __GNUC__
-  __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_txbe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO CAN_TXBE_0_Type           TXBE_0;      /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */
-  __IO CAN_TXBE_1_Type           TXBE_1;      /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */
-  __IO CAN_TXBE_DATA_Type        TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */
-} CanMramTxbe
-#ifdef __GNUC__
-  __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_txefe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO CAN_TXEFE_0_Type          TXEFE_0;     /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */
-  __IO CAN_TXEFE_1_Type          TXEFE_1;     /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */
-} CanMramTxefe
-#ifdef __GNUC__
-  __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief CAN Mram_xifde hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO CAN_XIDFE_0_Type          XIDFE_0;     /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */
-  __IO CAN_XIDFE_1_Type          XIDFE_1;     /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */
-} CanMramXifde
-#ifdef __GNUC__
-  __attribute__ ((aligned (4)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_CAN_MRAM_RXBE
-
-#define SECTION_CAN_MRAM_RXF0E
-
-#define SECTION_CAN_MRAM_RXF1E
-
-#define SECTION_CAN_MRAM_SIDFE
-
-#define SECTION_CAN_MRAM_TXBE
-
-#define SECTION_CAN_MRAM_TXEFE
-
-#define SECTION_CAN_MRAM_XIFDE
-
-/*@}*/
-
-#endif /* _SAMD51_CAN_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h
deleted file mode 100644
index 890e81edf6..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ccl.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for CCL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CCL_COMPONENT_
-#define _SAMD51_CCL_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR CCL */
-/* ========================================================================== */
-/** \addtogroup SAMD51_CCL Configurable Custom Logic */
-/*@{*/
-
-#define CCL_U2225
-#define REV_CCL                     0x110
-
-/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} CCL_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CCL_CTRL_OFFSET             0x0          /**< \brief (CCL_CTRL offset) Control */
-#define CCL_CTRL_RESETVALUE         _U_(0x00)    /**< \brief (CCL_CTRL reset_value) Control */
-
-#define CCL_CTRL_SWRST_Pos          0            /**< \brief (CCL_CTRL) Software Reset */
-#define CCL_CTRL_SWRST              (_U_(0x1) << CCL_CTRL_SWRST_Pos)
-#define CCL_CTRL_ENABLE_Pos         1            /**< \brief (CCL_CTRL) Enable */
-#define CCL_CTRL_ENABLE             (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
-#define CCL_CTRL_RUNSTDBY_Pos       6            /**< \brief (CCL_CTRL) Run in Standby */
-#define CCL_CTRL_RUNSTDBY           (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
-#define CCL_CTRL_MASK               _U_(0x43)    /**< \brief (CCL_CTRL) MASK Register */
-
-/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W  8) SEQ Control x -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SEQSEL:4;         /*!< bit:  0.. 3  Sequential Selection               */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} CCL_SEQCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CCL_SEQCTRL_OFFSET          0x4          /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
-#define CCL_SEQCTRL_RESETVALUE      _U_(0x00)    /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
-
-#define CCL_SEQCTRL_SEQSEL_Pos      0            /**< \brief (CCL_SEQCTRL) Sequential Selection */
-#define CCL_SEQCTRL_SEQSEL_Msk      (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL(value)   (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
-#define   CCL_SEQCTRL_SEQSEL_DISABLE_Val  _U_(0x0)   /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
-#define   CCL_SEQCTRL_SEQSEL_DFF_Val      _U_(0x1)   /**< \brief (CCL_SEQCTRL) D flip flop */
-#define   CCL_SEQCTRL_SEQSEL_JK_Val       _U_(0x2)   /**< \brief (CCL_SEQCTRL) JK flip flop */
-#define   CCL_SEQCTRL_SEQSEL_LATCH_Val    _U_(0x3)   /**< \brief (CCL_SEQCTRL) D latch */
-#define   CCL_SEQCTRL_SEQSEL_RS_Val       _U_(0x4)   /**< \brief (CCL_SEQCTRL) RS latch */
-#define CCL_SEQCTRL_SEQSEL_DISABLE  (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_DFF      (CCL_SEQCTRL_SEQSEL_DFF_Val    << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_JK       (CCL_SEQCTRL_SEQSEL_JK_Val     << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_LATCH    (CCL_SEQCTRL_SEQSEL_LATCH_Val  << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_SEQSEL_RS       (CCL_SEQCTRL_SEQSEL_RS_Val     << CCL_SEQCTRL_SEQSEL_Pos)
-#define CCL_SEQCTRL_MASK            _U_(0x0F)    /**< \brief (CCL_SEQCTRL) MASK Register */
-
-/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  LUT Enable                         */
-    uint32_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint32_t FILTSEL:2;        /*!< bit:  4.. 5  Filter Selection                   */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t EDGESEL:1;        /*!< bit:      7  Edge Selection                     */
-    uint32_t INSEL0:4;         /*!< bit:  8..11  Input Selection 0                  */
-    uint32_t INSEL1:4;         /*!< bit: 12..15  Input Selection 1                  */
-    uint32_t INSEL2:4;         /*!< bit: 16..19  Input Selection 2                  */
-    uint32_t INVEI:1;          /*!< bit:     20  Inverted Event Input Enable        */
-    uint32_t LUTEI:1;          /*!< bit:     21  LUT Event Input Enable             */
-    uint32_t LUTEO:1;          /*!< bit:     22  LUT Event Output Enable            */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t TRUTH:8;          /*!< bit: 24..31  Truth Value                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CCL_LUTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CCL_LUTCTRL_OFFSET          0x8          /**< \brief (CCL_LUTCTRL offset) LUT Control x */
-#define CCL_LUTCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
-
-#define CCL_LUTCTRL_ENABLE_Pos      1            /**< \brief (CCL_LUTCTRL) LUT Enable */
-#define CCL_LUTCTRL_ENABLE          (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
-#define CCL_LUTCTRL_FILTSEL_Pos     4            /**< \brief (CCL_LUTCTRL) Filter Selection */
-#define CCL_LUTCTRL_FILTSEL_Msk     (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_FILTSEL(value)  (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
-#define   CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0)   /**< \brief (CCL_LUTCTRL) Filter disabled */
-#define   CCL_LUTCTRL_FILTSEL_SYNCH_Val   _U_(0x1)   /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
-#define   CCL_LUTCTRL_FILTSEL_FILTER_Val  _U_(0x2)   /**< \brief (CCL_LUTCTRL) Filter enabled */
-#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_FILTSEL_SYNCH   (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_FILTSEL_FILTER  (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
-#define CCL_LUTCTRL_EDGESEL_Pos     7            /**< \brief (CCL_LUTCTRL) Edge Selection */
-#define CCL_LUTCTRL_EDGESEL         (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
-#define CCL_LUTCTRL_INSEL0_Pos      8            /**< \brief (CCL_LUTCTRL) Input Selection 0 */
-#define CCL_LUTCTRL_INSEL0_Msk      (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0(value)   (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
-#define   CCL_LUTCTRL_INSEL0_MASK_Val     _U_(0x0)   /**< \brief (CCL_LUTCTRL) Masked input */
-#define   CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1)   /**< \brief (CCL_LUTCTRL) Feedback input source */
-#define   CCL_LUTCTRL_INSEL0_LINK_Val     _U_(0x2)   /**< \brief (CCL_LUTCTRL) Linked LUT input source */
-#define   CCL_LUTCTRL_INSEL0_EVENT_Val    _U_(0x3)   /**< \brief (CCL_LUTCTRL) Event input source */
-#define   CCL_LUTCTRL_INSEL0_IO_Val       _U_(0x4)   /**< \brief (CCL_LUTCTRL) I/O pin input source */
-#define   CCL_LUTCTRL_INSEL0_AC_Val       _U_(0x5)   /**< \brief (CCL_LUTCTRL) AC input source */
-#define   CCL_LUTCTRL_INSEL0_TC_Val       _U_(0x6)   /**< \brief (CCL_LUTCTRL) TC input source */
-#define   CCL_LUTCTRL_INSEL0_ALTTC_Val    _U_(0x7)   /**< \brief (CCL_LUTCTRL) Alternate TC input source */
-#define   CCL_LUTCTRL_INSEL0_TCC_Val      _U_(0x8)   /**< \brief (CCL_LUTCTRL) TCC input source */
-#define   CCL_LUTCTRL_INSEL0_SERCOM_Val   _U_(0x9)   /**< \brief (CCL_LUTCTRL) SERCOM input source */
-#define CCL_LUTCTRL_INSEL0_MASK     (CCL_LUTCTRL_INSEL0_MASK_Val   << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_LINK     (CCL_LUTCTRL_INSEL0_LINK_Val   << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_EVENT    (CCL_LUTCTRL_INSEL0_EVENT_Val  << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_IO       (CCL_LUTCTRL_INSEL0_IO_Val     << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_AC       (CCL_LUTCTRL_INSEL0_AC_Val     << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_TC       (CCL_LUTCTRL_INSEL0_TC_Val     << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_ALTTC    (CCL_LUTCTRL_INSEL0_ALTTC_Val  << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_TCC      (CCL_LUTCTRL_INSEL0_TCC_Val    << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL0_SERCOM   (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
-#define CCL_LUTCTRL_INSEL1_Pos      12           /**< \brief (CCL_LUTCTRL) Input Selection 1 */
-#define CCL_LUTCTRL_INSEL1_Msk      (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1(value)   (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
-#define   CCL_LUTCTRL_INSEL1_MASK_Val     _U_(0x0)   /**< \brief (CCL_LUTCTRL) Masked input */
-#define   CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1)   /**< \brief (CCL_LUTCTRL) Feedback input source */
-#define   CCL_LUTCTRL_INSEL1_LINK_Val     _U_(0x2)   /**< \brief (CCL_LUTCTRL) Linked LUT input source */
-#define   CCL_LUTCTRL_INSEL1_EVENT_Val    _U_(0x3)   /**< \brief (CCL_LUTCTRL) Event input source */
-#define   CCL_LUTCTRL_INSEL1_IO_Val       _U_(0x4)   /**< \brief (CCL_LUTCTRL) I/O pin input source */
-#define   CCL_LUTCTRL_INSEL1_AC_Val       _U_(0x5)   /**< \brief (CCL_LUTCTRL) AC input source */
-#define   CCL_LUTCTRL_INSEL1_TC_Val       _U_(0x6)   /**< \brief (CCL_LUTCTRL) TC input source */
-#define   CCL_LUTCTRL_INSEL1_ALTTC_Val    _U_(0x7)   /**< \brief (CCL_LUTCTRL) Alternate TC input source */
-#define   CCL_LUTCTRL_INSEL1_TCC_Val      _U_(0x8)   /**< \brief (CCL_LUTCTRL) TCC input source */
-#define   CCL_LUTCTRL_INSEL1_SERCOM_Val   _U_(0x9)   /**< \brief (CCL_LUTCTRL) SERCOM input source */
-#define CCL_LUTCTRL_INSEL1_MASK     (CCL_LUTCTRL_INSEL1_MASK_Val   << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_LINK     (CCL_LUTCTRL_INSEL1_LINK_Val   << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_EVENT    (CCL_LUTCTRL_INSEL1_EVENT_Val  << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_IO       (CCL_LUTCTRL_INSEL1_IO_Val     << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_AC       (CCL_LUTCTRL_INSEL1_AC_Val     << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_TC       (CCL_LUTCTRL_INSEL1_TC_Val     << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_ALTTC    (CCL_LUTCTRL_INSEL1_ALTTC_Val  << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_TCC      (CCL_LUTCTRL_INSEL1_TCC_Val    << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL1_SERCOM   (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos)
-#define CCL_LUTCTRL_INSEL2_Pos      16           /**< \brief (CCL_LUTCTRL) Input Selection 2 */
-#define CCL_LUTCTRL_INSEL2_Msk      (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2(value)   (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
-#define   CCL_LUTCTRL_INSEL2_MASK_Val     _U_(0x0)   /**< \brief (CCL_LUTCTRL) Masked input */
-#define   CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1)   /**< \brief (CCL_LUTCTRL) Feedback input source */
-#define   CCL_LUTCTRL_INSEL2_LINK_Val     _U_(0x2)   /**< \brief (CCL_LUTCTRL) Linked LUT input source */
-#define   CCL_LUTCTRL_INSEL2_EVENT_Val    _U_(0x3)   /**< \brief (CCL_LUTCTRL) Event input source */
-#define   CCL_LUTCTRL_INSEL2_IO_Val       _U_(0x4)   /**< \brief (CCL_LUTCTRL) I/O pin input source */
-#define   CCL_LUTCTRL_INSEL2_AC_Val       _U_(0x5)   /**< \brief (CCL_LUTCTRL) AC input source */
-#define   CCL_LUTCTRL_INSEL2_TC_Val       _U_(0x6)   /**< \brief (CCL_LUTCTRL) TC input source */
-#define   CCL_LUTCTRL_INSEL2_ALTTC_Val    _U_(0x7)   /**< \brief (CCL_LUTCTRL) Alternate TC input source */
-#define   CCL_LUTCTRL_INSEL2_TCC_Val      _U_(0x8)   /**< \brief (CCL_LUTCTRL) TCC input source */
-#define   CCL_LUTCTRL_INSEL2_SERCOM_Val   _U_(0x9)   /**< \brief (CCL_LUTCTRL) SERCOM input source */
-#define CCL_LUTCTRL_INSEL2_MASK     (CCL_LUTCTRL_INSEL2_MASK_Val   << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_LINK     (CCL_LUTCTRL_INSEL2_LINK_Val   << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_EVENT    (CCL_LUTCTRL_INSEL2_EVENT_Val  << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_IO       (CCL_LUTCTRL_INSEL2_IO_Val     << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_AC       (CCL_LUTCTRL_INSEL2_AC_Val     << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_TC       (CCL_LUTCTRL_INSEL2_TC_Val     << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_ALTTC    (CCL_LUTCTRL_INSEL2_ALTTC_Val  << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_TCC      (CCL_LUTCTRL_INSEL2_TCC_Val    << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INSEL2_SERCOM   (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos)
-#define CCL_LUTCTRL_INVEI_Pos       20           /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */
-#define CCL_LUTCTRL_INVEI           (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
-#define CCL_LUTCTRL_LUTEI_Pos       21           /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */
-#define CCL_LUTCTRL_LUTEI           (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
-#define CCL_LUTCTRL_LUTEO_Pos       22           /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */
-#define CCL_LUTCTRL_LUTEO           (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
-#define CCL_LUTCTRL_TRUTH_Pos       24           /**< \brief (CCL_LUTCTRL) Truth Value */
-#define CCL_LUTCTRL_TRUTH_Msk       (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
-#define CCL_LUTCTRL_TRUTH(value)    (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
-#define CCL_LUTCTRL_MASK            _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
-
-/** \brief CCL hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO CCL_CTRL_Type             CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
-       RoReg8                    Reserved1[0x3];
-  __IO CCL_SEQCTRL_Type          SEQCTRL[2];  /**< \brief Offset: 0x4 (R/W  8) SEQ Control x */
-       RoReg8                    Reserved2[0x2];
-  __IO CCL_LUTCTRL_Type          LUTCTRL[4];  /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
-} Ccl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_CCL_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h
deleted file mode 100644
index 92fa6813ef..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/cmcc.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for CMCC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CMCC_COMPONENT_
-#define _SAMD51_CMCC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR CMCC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */
-/*@{*/
-
-#define CMCC_U2015
-#define REV_CMCC                    0x600
-
-/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/  32) Cache Type Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t GCLK:1;           /*!< bit:      1  dynamic Clock Gating supported     */
-    uint32_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint32_t RRP:1;            /*!< bit:      4  Round Robin Policy supported       */
-    uint32_t WAYNUM:2;         /*!< bit:  5.. 6  Number of Way                      */
-    uint32_t LCKDOWN:1;        /*!< bit:      7  Lock Down supported                */
-    uint32_t CSIZE:3;          /*!< bit:  8..10  Cache Size                         */
-    uint32_t CLSIZE:3;         /*!< bit: 11..13  Cache Line Size                    */
-    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_TYPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_TYPE_OFFSET            0x00         /**< \brief (CMCC_TYPE offset) Cache Type Register */
-#define CMCC_TYPE_RESETVALUE        _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */
-
-#define CMCC_TYPE_GCLK_Pos          1            /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */
-#define CMCC_TYPE_GCLK              (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
-#define CMCC_TYPE_RRP_Pos           4            /**< \brief (CMCC_TYPE) Round Robin Policy supported */
-#define CMCC_TYPE_RRP               (_U_(0x1) << CMCC_TYPE_RRP_Pos)
-#define CMCC_TYPE_WAYNUM_Pos        5            /**< \brief (CMCC_TYPE) Number of Way */
-#define CMCC_TYPE_WAYNUM_Msk        (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_WAYNUM(value)     (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
-#define   CMCC_TYPE_WAYNUM_DMAPPED_Val    _U_(0x0)   /**< \brief (CMCC_TYPE) Direct Mapped Cache */
-#define   CMCC_TYPE_WAYNUM_ARCH2WAY_Val   _U_(0x1)   /**< \brief (CMCC_TYPE) 2-WAY set associative */
-#define   CMCC_TYPE_WAYNUM_ARCH4WAY_Val   _U_(0x2)   /**< \brief (CMCC_TYPE) 4-WAY set associative */
-#define CMCC_TYPE_WAYNUM_DMAPPED    (CMCC_TYPE_WAYNUM_DMAPPED_Val  << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_WAYNUM_ARCH2WAY   (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_WAYNUM_ARCH4WAY   (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
-#define CMCC_TYPE_LCKDOWN_Pos       7            /**< \brief (CMCC_TYPE) Lock Down supported */
-#define CMCC_TYPE_LCKDOWN           (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
-#define CMCC_TYPE_CSIZE_Pos         8            /**< \brief (CMCC_TYPE) Cache Size */
-#define CMCC_TYPE_CSIZE_Msk         (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE(value)      (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
-#define   CMCC_TYPE_CSIZE_CSIZE_1KB_Val   _U_(0x0)   /**< \brief (CMCC_TYPE) Cache Size is 1 KB */
-#define   CMCC_TYPE_CSIZE_CSIZE_2KB_Val   _U_(0x1)   /**< \brief (CMCC_TYPE) Cache Size is 2 KB */
-#define   CMCC_TYPE_CSIZE_CSIZE_4KB_Val   _U_(0x2)   /**< \brief (CMCC_TYPE) Cache Size is 4 KB */
-#define   CMCC_TYPE_CSIZE_CSIZE_8KB_Val   _U_(0x3)   /**< \brief (CMCC_TYPE) Cache Size is 8 KB */
-#define   CMCC_TYPE_CSIZE_CSIZE_16KB_Val  _U_(0x4)   /**< \brief (CMCC_TYPE) Cache Size is 16 KB */
-#define   CMCC_TYPE_CSIZE_CSIZE_32KB_Val  _U_(0x5)   /**< \brief (CMCC_TYPE) Cache Size is 32 KB */
-#define   CMCC_TYPE_CSIZE_CSIZE_64KB_Val  _U_(0x6)   /**< \brief (CMCC_TYPE) Cache Size is 64 KB */
-#define CMCC_TYPE_CSIZE_CSIZE_1KB   (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_2KB   (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_4KB   (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_8KB   (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_16KB  (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_32KB  (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CSIZE_CSIZE_64KB  (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_Pos        11           /**< \brief (CMCC_TYPE) Cache Line Size */
-#define CMCC_TYPE_CLSIZE_Msk        (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE(value)     (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
-#define   CMCC_TYPE_CLSIZE_CLSIZE_4B_Val  _U_(0x0)   /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */
-#define   CMCC_TYPE_CLSIZE_CLSIZE_8B_Val  _U_(0x1)   /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */
-#define   CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2)   /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */
-#define   CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3)   /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */
-#define   CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4)   /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */
-#define   CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5)   /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */
-#define CMCC_TYPE_CLSIZE_CLSIZE_4B  (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_8B  (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
-#define CMCC_TYPE_MASK              _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */
-
-/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ICDIS:1;          /*!< bit:      1  Instruction Cache Disable          */
-    uint32_t DCDIS:1;          /*!< bit:      2  Data Cache Disable                 */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t CSIZESW:3;        /*!< bit:  4.. 6  Cache size configured by software  */
-    uint32_t :25;              /*!< bit:  7..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_CFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_CFG_OFFSET             0x04         /**< \brief (CMCC_CFG offset) Cache Configuration Register */
-#define CMCC_CFG_RESETVALUE         _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */
-
-#define CMCC_CFG_ICDIS_Pos          1            /**< \brief (CMCC_CFG) Instruction Cache Disable */
-#define CMCC_CFG_ICDIS              (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
-#define CMCC_CFG_DCDIS_Pos          2            /**< \brief (CMCC_CFG) Data Cache Disable */
-#define CMCC_CFG_DCDIS              (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
-#define CMCC_CFG_CSIZESW_Pos        4            /**< \brief (CMCC_CFG) Cache size configured by software */
-#define CMCC_CFG_CSIZESW_Msk        (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW(value)     (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
-#define   CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0)   /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */
-#define   CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1)   /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */
-#define   CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2)   /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */
-#define   CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3)   /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */
-#define   CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4)   /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */
-#define   CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5)   /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */
-#define   CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6)   /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
-#define CMCC_CFG_MASK               _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */
-
-/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CEN:1;            /*!< bit:      0  Cache Controller Enable            */
-    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_CTRL_OFFSET            0x08         /**< \brief (CMCC_CTRL offset) Cache Control Register */
-#define CMCC_CTRL_RESETVALUE        _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */
-
-#define CMCC_CTRL_CEN_Pos           0            /**< \brief (CMCC_CTRL) Cache Controller Enable */
-#define CMCC_CTRL_CEN               (_U_(0x1) << CMCC_CTRL_CEN_Pos)
-#define CMCC_CTRL_MASK              _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */
-
-/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/  32) Cache Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CSTS:1;           /*!< bit:      0  Cache Controller Status            */
-    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_SR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_SR_OFFSET              0x0C         /**< \brief (CMCC_SR offset) Cache Status Register */
-#define CMCC_SR_RESETVALUE          _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */
-
-#define CMCC_SR_CSTS_Pos            0            /**< \brief (CMCC_SR) Cache Controller Status */
-#define CMCC_SR_CSTS                (_U_(0x1) << CMCC_SR_CSTS_Pos)
-#define CMCC_SR_MASK                _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */
-
-/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LCKWAY:4;         /*!< bit:  0.. 3  Lockdown way Register              */
-    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_LCKWAY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_LCKWAY_OFFSET          0x10         /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */
-#define CMCC_LCKWAY_RESETVALUE      _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */
-
-#define CMCC_LCKWAY_LCKWAY_Pos      0            /**< \brief (CMCC_LCKWAY) Lockdown way Register */
-#define CMCC_LCKWAY_LCKWAY_Msk      (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
-#define CMCC_LCKWAY_LCKWAY(value)   (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
-#define CMCC_LCKWAY_MASK            _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */
-
-/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t INVALL:1;         /*!< bit:      0  Cache Controller invalidate All    */
-    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_MAINT0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MAINT0_OFFSET          0x20         /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */
-#define CMCC_MAINT0_RESETVALUE      _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */
-
-#define CMCC_MAINT0_INVALL_Pos      0            /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */
-#define CMCC_MAINT0_INVALL          (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
-#define CMCC_MAINT0_MASK            _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */
-
-/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint32_t INDEX:8;          /*!< bit:  4..11  Invalidate Index                   */
-    uint32_t :16;              /*!< bit: 12..27  Reserved                           */
-    uint32_t WAY:4;            /*!< bit: 28..31  Invalidate Way                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_MAINT1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MAINT1_OFFSET          0x24         /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */
-#define CMCC_MAINT1_RESETVALUE      _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */
-
-#define CMCC_MAINT1_INDEX_Pos       4            /**< \brief (CMCC_MAINT1) Invalidate Index */
-#define CMCC_MAINT1_INDEX_Msk       (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
-#define CMCC_MAINT1_INDEX(value)    (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
-#define CMCC_MAINT1_WAY_Pos         28           /**< \brief (CMCC_MAINT1) Invalidate Way */
-#define CMCC_MAINT1_WAY_Msk         (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY(value)      (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
-#define   CMCC_MAINT1_WAY_WAY0_Val        _U_(0x0)   /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
-#define   CMCC_MAINT1_WAY_WAY1_Val        _U_(0x1)   /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
-#define   CMCC_MAINT1_WAY_WAY2_Val        _U_(0x2)   /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
-#define   CMCC_MAINT1_WAY_WAY3_Val        _U_(0x3)   /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
-#define CMCC_MAINT1_WAY_WAY0        (CMCC_MAINT1_WAY_WAY0_Val      << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY_WAY1        (CMCC_MAINT1_WAY_WAY1_Val      << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY_WAY2        (CMCC_MAINT1_WAY_WAY2_Val      << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_WAY_WAY3        (CMCC_MAINT1_WAY_WAY3_Val      << CMCC_MAINT1_WAY_Pos)
-#define CMCC_MAINT1_MASK            _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */
-
-/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t MODE:2;           /*!< bit:  0.. 1  Cache Controller Monitor Counter Mode */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_MCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MCFG_OFFSET            0x28         /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */
-#define CMCC_MCFG_RESETVALUE        _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */
-
-#define CMCC_MCFG_MODE_Pos          0            /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
-#define CMCC_MCFG_MODE_Msk          (_U_(0x3) << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MODE(value)       (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
-#define   CMCC_MCFG_MODE_CYCLE_COUNT_Val  _U_(0x0)   /**< \brief (CMCC_MCFG) cycle counter */
-#define   CMCC_MCFG_MODE_IHIT_COUNT_Val   _U_(0x1)   /**< \brief (CMCC_MCFG) instruction hit counter */
-#define   CMCC_MCFG_MODE_DHIT_COUNT_Val   _U_(0x2)   /**< \brief (CMCC_MCFG) data hit counter */
-#define CMCC_MCFG_MODE_CYCLE_COUNT  (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MODE_IHIT_COUNT   (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MODE_DHIT_COUNT   (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
-#define CMCC_MCFG_MASK              _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */
-
-/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t MENABLE:1;        /*!< bit:      0  Cache Controller Monitor Enable    */
-    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_MEN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MEN_OFFSET             0x2C         /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */
-#define CMCC_MEN_RESETVALUE         _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */
-
-#define CMCC_MEN_MENABLE_Pos        0            /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
-#define CMCC_MEN_MENABLE            (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
-#define CMCC_MEN_MASK               _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */
-
-/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Cache Controller Software Reset    */
-    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_MCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MCTRL_OFFSET           0x30         /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */
-#define CMCC_MCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */
-
-#define CMCC_MCTRL_SWRST_Pos        0            /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */
-#define CMCC_MCTRL_SWRST            (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
-#define CMCC_MCTRL_MASK             _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */
-
-/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/  32) Cache Monitor Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EVENT_CNT:32;     /*!< bit:  0..31  Monitor Event Counter              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} CMCC_MSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define CMCC_MSR_OFFSET             0x34         /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */
-#define CMCC_MSR_RESETVALUE         _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */
-
-#define CMCC_MSR_EVENT_CNT_Pos      0            /**< \brief (CMCC_MSR) Monitor Event Counter */
-#define CMCC_MSR_EVENT_CNT_Msk      (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
-#define CMCC_MSR_EVENT_CNT(value)   (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
-#define CMCC_MSR_MASK               _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */
-
-/** \brief CMCC APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __I  CMCC_TYPE_Type            TYPE;        /**< \brief Offset: 0x00 (R/  32) Cache Type Register */
-  __IO CMCC_CFG_Type             CFG;         /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */
-  __O  CMCC_CTRL_Type            CTRL;        /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */
-  __I  CMCC_SR_Type              SR;          /**< \brief Offset: 0x0C (R/  32) Cache Status Register */
-  __IO CMCC_LCKWAY_Type          LCKWAY;      /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */
-       RoReg8                    Reserved1[0xC];
-  __O  CMCC_MAINT0_Type          MAINT0;      /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
-  __O  CMCC_MAINT1_Type          MAINT1;      /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
-  __IO CMCC_MCFG_Type            MCFG;        /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
-  __IO CMCC_MEN_Type             MEN;         /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
-  __O  CMCC_MCTRL_Type           MCTRL;       /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */
-  __I  CMCC_MSR_Type             MSR;         /**< \brief Offset: 0x34 (R/  32) Cache Monitor Status Register */
-} Cmcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_CMCC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h
deleted file mode 100644
index c67efda303..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dac.h
+++ /dev/null
@@ -1,544 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for DAC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_DAC_COMPONENT_
-#define _SAMD51_DAC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR DAC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_DAC Digital-to-Analog Converter */
-/*@{*/
-
-#define DAC_U2502
-#define REV_DAC                     0x100
-
-/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable DAC Controller              */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_CTRLA_OFFSET            0x00         /**< \brief (DAC_CTRLA offset) Control A */
-#define DAC_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (DAC_CTRLA reset_value) Control A */
-
-#define DAC_CTRLA_SWRST_Pos         0            /**< \brief (DAC_CTRLA) Software Reset */
-#define DAC_CTRLA_SWRST             (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
-#define DAC_CTRLA_ENABLE_Pos        1            /**< \brief (DAC_CTRLA) Enable DAC Controller */
-#define DAC_CTRLA_ENABLE            (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
-#define DAC_CTRLA_MASK              _U_(0x03)    /**< \brief (DAC_CTRLA) MASK Register */
-
-/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W  8) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIFF:1;           /*!< bit:      0  Differential mode enable           */
-    uint8_t  REFSEL:2;         /*!< bit:  1.. 2  Reference Selection for DAC0/1     */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_CTRLB_OFFSET            0x01         /**< \brief (DAC_CTRLB offset) Control B */
-#define DAC_CTRLB_RESETVALUE        _U_(0x02)    /**< \brief (DAC_CTRLB reset_value) Control B */
-
-#define DAC_CTRLB_DIFF_Pos          0            /**< \brief (DAC_CTRLB) Differential mode enable */
-#define DAC_CTRLB_DIFF              (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
-#define DAC_CTRLB_REFSEL_Pos        1            /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */
-#define DAC_CTRLB_REFSEL_Msk        (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL(value)     (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
-#define   DAC_CTRLB_REFSEL_VREFPU_Val     _U_(0x0)   /**< \brief (DAC_CTRLB) External reference unbuffered */
-#define   DAC_CTRLB_REFSEL_VDDANA_Val     _U_(0x1)   /**< \brief (DAC_CTRLB) Analog supply */
-#define   DAC_CTRLB_REFSEL_VREFPB_Val     _U_(0x2)   /**< \brief (DAC_CTRLB) External reference buffered */
-#define   DAC_CTRLB_REFSEL_INTREF_Val     _U_(0x3)   /**< \brief (DAC_CTRLB) Internal bandgap reference */
-#define DAC_CTRLB_REFSEL_VREFPU     (DAC_CTRLB_REFSEL_VREFPU_Val   << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_VDDANA     (DAC_CTRLB_REFSEL_VDDANA_Val   << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_VREFPB     (DAC_CTRLB_REFSEL_VREFPB_Val   << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_REFSEL_INTREF     (DAC_CTRLB_REFSEL_INTREF_Val   << DAC_CTRLB_REFSEL_Pos)
-#define DAC_CTRLB_MASK              _U_(0x07)    /**< \brief (DAC_CTRLB) MASK Register */
-
-/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W  8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  STARTEI0:1;       /*!< bit:      0  Start Conversion Event Input DAC 0 */
-    uint8_t  STARTEI1:1;       /*!< bit:      1  Start Conversion Event Input DAC 1 */
-    uint8_t  EMPTYEO0:1;       /*!< bit:      2  Data Buffer Empty Event Output DAC 0 */
-    uint8_t  EMPTYEO1:1;       /*!< bit:      3  Data Buffer Empty Event Output DAC 1 */
-    uint8_t  INVEI0:1;         /*!< bit:      4  Enable Invertion of DAC 0 input event */
-    uint8_t  INVEI1:1;         /*!< bit:      5  Enable Invertion of DAC 1 input event */
-    uint8_t  RESRDYEO0:1;      /*!< bit:      6  Result Ready Event Output 0        */
-    uint8_t  RESRDYEO1:1;      /*!< bit:      7  Result Ready Event Output 1        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  STARTEI:2;        /*!< bit:  0.. 1  Start Conversion Event Input DAC x */
-    uint8_t  EMPTYEO:2;        /*!< bit:  2.. 3  Data Buffer Empty Event Output DAC x */
-    uint8_t  INVEI:2;          /*!< bit:  4.. 5  Enable Invertion of DAC x input event */
-    uint8_t  RESRDYEO:2;       /*!< bit:  6.. 7  Result Ready Event Output x        */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_EVCTRL_OFFSET           0x02         /**< \brief (DAC_EVCTRL offset) Event Control */
-#define DAC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (DAC_EVCTRL reset_value) Event Control */
-
-#define DAC_EVCTRL_STARTEI0_Pos     0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */
-#define DAC_EVCTRL_STARTEI0         (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
-#define DAC_EVCTRL_STARTEI1_Pos     1            /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */
-#define DAC_EVCTRL_STARTEI1         (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
-#define DAC_EVCTRL_STARTEI_Pos      0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */
-#define DAC_EVCTRL_STARTEI_Msk      (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
-#define DAC_EVCTRL_STARTEI(value)   (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
-#define DAC_EVCTRL_EMPTYEO0_Pos     2            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */
-#define DAC_EVCTRL_EMPTYEO0         (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
-#define DAC_EVCTRL_EMPTYEO1_Pos     3            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */
-#define DAC_EVCTRL_EMPTYEO1         (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
-#define DAC_EVCTRL_EMPTYEO_Pos      2            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */
-#define DAC_EVCTRL_EMPTYEO_Msk      (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
-#define DAC_EVCTRL_EMPTYEO(value)   (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
-#define DAC_EVCTRL_INVEI0_Pos       4            /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */
-#define DAC_EVCTRL_INVEI0           (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
-#define DAC_EVCTRL_INVEI1_Pos       5            /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */
-#define DAC_EVCTRL_INVEI1           (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
-#define DAC_EVCTRL_INVEI_Pos        4            /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */
-#define DAC_EVCTRL_INVEI_Msk        (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
-#define DAC_EVCTRL_INVEI(value)     (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
-#define DAC_EVCTRL_RESRDYEO0_Pos    6            /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */
-#define DAC_EVCTRL_RESRDYEO0        (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)
-#define DAC_EVCTRL_RESRDYEO1_Pos    7            /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */
-#define DAC_EVCTRL_RESRDYEO1        (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)
-#define DAC_EVCTRL_RESRDYEO_Pos     6            /**< \brief (DAC_EVCTRL) Result Ready Event Output x */
-#define DAC_EVCTRL_RESRDYEO_Msk     (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)
-#define DAC_EVCTRL_RESRDYEO(value)  (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
-#define DAC_EVCTRL_MASK             _U_(0xFF)    /**< \brief (DAC_EVCTRL) MASK Register */
-
-/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  UNDERRUN0:1;      /*!< bit:      0  Underrun 0 Interrupt Enable        */
-    uint8_t  UNDERRUN1:1;      /*!< bit:      1  Underrun 1 Interrupt Enable        */
-    uint8_t  EMPTY0:1;         /*!< bit:      2  Data Buffer 0 Empty Interrupt Enable */
-    uint8_t  EMPTY1:1;         /*!< bit:      3  Data Buffer 1 Empty Interrupt Enable */
-    uint8_t  RESRDY0:1;        /*!< bit:      4  Result 0 Ready Interrupt Enable    */
-    uint8_t  RESRDY1:1;        /*!< bit:      5  Result 1 Ready Interrupt Enable    */
-    uint8_t  OVERRUN0:1;       /*!< bit:      6  Overrun 0 Interrupt Enable         */
-    uint8_t  OVERRUN1:1;       /*!< bit:      7  Overrun 1 Interrupt Enable         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  UNDERRUN:2;       /*!< bit:  0.. 1  Underrun x Interrupt Enable        */
-    uint8_t  EMPTY:2;          /*!< bit:  2.. 3  Data Buffer x Empty Interrupt Enable */
-    uint8_t  RESRDY:2;         /*!< bit:  4.. 5  Result x Ready Interrupt Enable    */
-    uint8_t  OVERRUN:2;        /*!< bit:  6.. 7  Overrun x Interrupt Enable         */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTENCLR_OFFSET         0x04         /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
-#define DAC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define DAC_INTENCLR_UNDERRUN0_Pos  0            /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN0      (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
-#define DAC_INTENCLR_UNDERRUN1_Pos  1            /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN1      (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
-#define DAC_INTENCLR_UNDERRUN_Pos   0            /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */
-#define DAC_INTENCLR_UNDERRUN_Msk   (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
-#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
-#define DAC_INTENCLR_EMPTY0_Pos     2            /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY0         (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
-#define DAC_INTENCLR_EMPTY1_Pos     3            /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY1         (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
-#define DAC_INTENCLR_EMPTY_Pos      2            /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */
-#define DAC_INTENCLR_EMPTY_Msk      (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
-#define DAC_INTENCLR_EMPTY(value)   (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
-#define DAC_INTENCLR_RESRDY0_Pos    4            /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */
-#define DAC_INTENCLR_RESRDY0        (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)
-#define DAC_INTENCLR_RESRDY1_Pos    5            /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */
-#define DAC_INTENCLR_RESRDY1        (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)
-#define DAC_INTENCLR_RESRDY_Pos     4            /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */
-#define DAC_INTENCLR_RESRDY_Msk     (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)
-#define DAC_INTENCLR_RESRDY(value)  (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
-#define DAC_INTENCLR_OVERRUN0_Pos   6            /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */
-#define DAC_INTENCLR_OVERRUN0       (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)
-#define DAC_INTENCLR_OVERRUN1_Pos   7            /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */
-#define DAC_INTENCLR_OVERRUN1       (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)
-#define DAC_INTENCLR_OVERRUN_Pos    6            /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */
-#define DAC_INTENCLR_OVERRUN_Msk    (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)
-#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
-#define DAC_INTENCLR_MASK           _U_(0xFF)    /**< \brief (DAC_INTENCLR) MASK Register */
-
-/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  UNDERRUN0:1;      /*!< bit:      0  Underrun 0 Interrupt Enable        */
-    uint8_t  UNDERRUN1:1;      /*!< bit:      1  Underrun 1 Interrupt Enable        */
-    uint8_t  EMPTY0:1;         /*!< bit:      2  Data Buffer 0 Empty Interrupt Enable */
-    uint8_t  EMPTY1:1;         /*!< bit:      3  Data Buffer 1 Empty Interrupt Enable */
-    uint8_t  RESRDY0:1;        /*!< bit:      4  Result 0 Ready Interrupt Enable    */
-    uint8_t  RESRDY1:1;        /*!< bit:      5  Result 1 Ready Interrupt Enable    */
-    uint8_t  OVERRUN0:1;       /*!< bit:      6  Overrun 0 Interrupt Enable         */
-    uint8_t  OVERRUN1:1;       /*!< bit:      7  Overrun 1 Interrupt Enable         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  UNDERRUN:2;       /*!< bit:  0.. 1  Underrun x Interrupt Enable        */
-    uint8_t  EMPTY:2;          /*!< bit:  2.. 3  Data Buffer x Empty Interrupt Enable */
-    uint8_t  RESRDY:2;         /*!< bit:  4.. 5  Result x Ready Interrupt Enable    */
-    uint8_t  OVERRUN:2;        /*!< bit:  6.. 7  Overrun x Interrupt Enable         */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTENSET_OFFSET         0x05         /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
-#define DAC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
-
-#define DAC_INTENSET_UNDERRUN0_Pos  0            /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN0      (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
-#define DAC_INTENSET_UNDERRUN1_Pos  1            /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN1      (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
-#define DAC_INTENSET_UNDERRUN_Pos   0            /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */
-#define DAC_INTENSET_UNDERRUN_Msk   (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
-#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
-#define DAC_INTENSET_EMPTY0_Pos     2            /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY0         (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
-#define DAC_INTENSET_EMPTY1_Pos     3            /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY1         (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
-#define DAC_INTENSET_EMPTY_Pos      2            /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */
-#define DAC_INTENSET_EMPTY_Msk      (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
-#define DAC_INTENSET_EMPTY(value)   (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
-#define DAC_INTENSET_RESRDY0_Pos    4            /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */
-#define DAC_INTENSET_RESRDY0        (_U_(1) << DAC_INTENSET_RESRDY0_Pos)
-#define DAC_INTENSET_RESRDY1_Pos    5            /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */
-#define DAC_INTENSET_RESRDY1        (_U_(1) << DAC_INTENSET_RESRDY1_Pos)
-#define DAC_INTENSET_RESRDY_Pos     4            /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */
-#define DAC_INTENSET_RESRDY_Msk     (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)
-#define DAC_INTENSET_RESRDY(value)  (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
-#define DAC_INTENSET_OVERRUN0_Pos   6            /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */
-#define DAC_INTENSET_OVERRUN0       (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)
-#define DAC_INTENSET_OVERRUN1_Pos   7            /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */
-#define DAC_INTENSET_OVERRUN1       (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)
-#define DAC_INTENSET_OVERRUN_Pos    6            /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */
-#define DAC_INTENSET_OVERRUN_Msk    (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)
-#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
-#define DAC_INTENSET_MASK           _U_(0xFF)    /**< \brief (DAC_INTENSET) MASK Register */
-
-/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  UNDERRUN0:1;      /*!< bit:      0  Result 0 Underrun                  */
-    __I uint8_t  UNDERRUN1:1;      /*!< bit:      1  Result 1 Underrun                  */
-    __I uint8_t  EMPTY0:1;         /*!< bit:      2  Data Buffer 0 Empty                */
-    __I uint8_t  EMPTY1:1;         /*!< bit:      3  Data Buffer 1 Empty                */
-    __I uint8_t  RESRDY0:1;        /*!< bit:      4  Result 0 Ready                     */
-    __I uint8_t  RESRDY1:1;        /*!< bit:      5  Result 1 Ready                     */
-    __I uint8_t  OVERRUN0:1;       /*!< bit:      6  Result 0 Overrun                   */
-    __I uint8_t  OVERRUN1:1;       /*!< bit:      7  Result 1 Overrun                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  UNDERRUN:2;       /*!< bit:  0.. 1  Result x Underrun                  */
-    __I uint8_t  EMPTY:2;          /*!< bit:  2.. 3  Data Buffer x Empty                */
-    __I uint8_t  RESRDY:2;         /*!< bit:  4.. 5  Result x Ready                     */
-    __I uint8_t  OVERRUN:2;        /*!< bit:  6.. 7  Result x Overrun                   */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_INTFLAG_OFFSET          0x06         /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define DAC_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define DAC_INTFLAG_UNDERRUN0_Pos   0            /**< \brief (DAC_INTFLAG) Result 0 Underrun */
-#define DAC_INTFLAG_UNDERRUN0       (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
-#define DAC_INTFLAG_UNDERRUN1_Pos   1            /**< \brief (DAC_INTFLAG) Result 1 Underrun */
-#define DAC_INTFLAG_UNDERRUN1       (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
-#define DAC_INTFLAG_UNDERRUN_Pos    0            /**< \brief (DAC_INTFLAG) Result x Underrun */
-#define DAC_INTFLAG_UNDERRUN_Msk    (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
-#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
-#define DAC_INTFLAG_EMPTY0_Pos      2            /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */
-#define DAC_INTFLAG_EMPTY0          (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
-#define DAC_INTFLAG_EMPTY1_Pos      3            /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */
-#define DAC_INTFLAG_EMPTY1          (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
-#define DAC_INTFLAG_EMPTY_Pos       2            /**< \brief (DAC_INTFLAG) Data Buffer x Empty */
-#define DAC_INTFLAG_EMPTY_Msk       (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
-#define DAC_INTFLAG_EMPTY(value)    (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
-#define DAC_INTFLAG_RESRDY0_Pos     4            /**< \brief (DAC_INTFLAG) Result 0 Ready */
-#define DAC_INTFLAG_RESRDY0         (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)
-#define DAC_INTFLAG_RESRDY1_Pos     5            /**< \brief (DAC_INTFLAG) Result 1 Ready */
-#define DAC_INTFLAG_RESRDY1         (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)
-#define DAC_INTFLAG_RESRDY_Pos      4            /**< \brief (DAC_INTFLAG) Result x Ready */
-#define DAC_INTFLAG_RESRDY_Msk      (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)
-#define DAC_INTFLAG_RESRDY(value)   (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
-#define DAC_INTFLAG_OVERRUN0_Pos    6            /**< \brief (DAC_INTFLAG) Result 0 Overrun */
-#define DAC_INTFLAG_OVERRUN0        (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)
-#define DAC_INTFLAG_OVERRUN1_Pos    7            /**< \brief (DAC_INTFLAG) Result 1 Overrun */
-#define DAC_INTFLAG_OVERRUN1        (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)
-#define DAC_INTFLAG_OVERRUN_Pos     6            /**< \brief (DAC_INTFLAG) Result x Overrun */
-#define DAC_INTFLAG_OVERRUN_Msk     (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)
-#define DAC_INTFLAG_OVERRUN(value)  (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
-#define DAC_INTFLAG_MASK            _U_(0xFF)    /**< \brief (DAC_INTFLAG) MASK Register */
-
-/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/   8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  READY0:1;         /*!< bit:      0  DAC 0 Startup Ready                */
-    uint8_t  READY1:1;         /*!< bit:      1  DAC 1 Startup Ready                */
-    uint8_t  EOC0:1;           /*!< bit:      2  DAC 0 End of Conversion            */
-    uint8_t  EOC1:1;           /*!< bit:      3  DAC 1 End of Conversion            */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  READY:2;          /*!< bit:  0.. 1  DAC x Startup Ready                */
-    uint8_t  EOC:2;            /*!< bit:  2.. 3  DAC x End of Conversion            */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_STATUS_OFFSET           0x07         /**< \brief (DAC_STATUS offset) Status */
-#define DAC_STATUS_RESETVALUE       _U_(0x00)    /**< \brief (DAC_STATUS reset_value) Status */
-
-#define DAC_STATUS_READY0_Pos       0            /**< \brief (DAC_STATUS) DAC 0 Startup Ready */
-#define DAC_STATUS_READY0           (_U_(1) << DAC_STATUS_READY0_Pos)
-#define DAC_STATUS_READY1_Pos       1            /**< \brief (DAC_STATUS) DAC 1 Startup Ready */
-#define DAC_STATUS_READY1           (_U_(1) << DAC_STATUS_READY1_Pos)
-#define DAC_STATUS_READY_Pos        0            /**< \brief (DAC_STATUS) DAC x Startup Ready */
-#define DAC_STATUS_READY_Msk        (_U_(0x3) << DAC_STATUS_READY_Pos)
-#define DAC_STATUS_READY(value)     (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
-#define DAC_STATUS_EOC0_Pos         2            /**< \brief (DAC_STATUS) DAC 0 End of Conversion */
-#define DAC_STATUS_EOC0             (_U_(1) << DAC_STATUS_EOC0_Pos)
-#define DAC_STATUS_EOC1_Pos         3            /**< \brief (DAC_STATUS) DAC 1 End of Conversion */
-#define DAC_STATUS_EOC1             (_U_(1) << DAC_STATUS_EOC1_Pos)
-#define DAC_STATUS_EOC_Pos          2            /**< \brief (DAC_STATUS) DAC x End of Conversion */
-#define DAC_STATUS_EOC_Msk          (_U_(0x3) << DAC_STATUS_EOC_Pos)
-#define DAC_STATUS_EOC(value)       (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
-#define DAC_STATUS_MASK             _U_(0x0F)    /**< \brief (DAC_STATUS) MASK Register */
-
-/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  DAC Enable Status                  */
-    uint32_t DATA0:1;          /*!< bit:      2  Data DAC 0                         */
-    uint32_t DATA1:1;          /*!< bit:      3  Data DAC 1                         */
-    uint32_t DATABUF0:1;       /*!< bit:      4  Data Buffer DAC 0                  */
-    uint32_t DATABUF1:1;       /*!< bit:      5  Data Buffer DAC 1                  */
-    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint32_t DATA:2;           /*!< bit:  2.. 3  Data DAC x                         */
-    uint32_t DATABUF:2;        /*!< bit:  4.. 5  Data Buffer DAC x                  */
-    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DAC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_SYNCBUSY_OFFSET         0x08         /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */
-#define DAC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define DAC_SYNCBUSY_SWRST_Pos      0            /**< \brief (DAC_SYNCBUSY) Software Reset */
-#define DAC_SYNCBUSY_SWRST          (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
-#define DAC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (DAC_SYNCBUSY) DAC Enable Status */
-#define DAC_SYNCBUSY_ENABLE         (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
-#define DAC_SYNCBUSY_DATA0_Pos      2            /**< \brief (DAC_SYNCBUSY) Data DAC 0 */
-#define DAC_SYNCBUSY_DATA0          (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
-#define DAC_SYNCBUSY_DATA1_Pos      3            /**< \brief (DAC_SYNCBUSY) Data DAC 1 */
-#define DAC_SYNCBUSY_DATA1          (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
-#define DAC_SYNCBUSY_DATA_Pos       2            /**< \brief (DAC_SYNCBUSY) Data DAC x */
-#define DAC_SYNCBUSY_DATA_Msk       (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
-#define DAC_SYNCBUSY_DATA(value)    (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
-#define DAC_SYNCBUSY_DATABUF0_Pos   4            /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */
-#define DAC_SYNCBUSY_DATABUF0       (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
-#define DAC_SYNCBUSY_DATABUF1_Pos   5            /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */
-#define DAC_SYNCBUSY_DATABUF1       (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
-#define DAC_SYNCBUSY_DATABUF_Pos    4            /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */
-#define DAC_SYNCBUSY_DATABUF_Msk    (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
-#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
-#define DAC_SYNCBUSY_MASK           _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */
-
-/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t LEFTADJ:1;        /*!< bit:      0  Left Adjusted Data                 */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable DAC0                        */
-    uint16_t CCTRL:2;          /*!< bit:  2.. 3  Current Control                    */
-    uint16_t :1;               /*!< bit:      4  Reserved                           */
-    uint16_t FEXT:1;           /*!< bit:      5  Standalone Filter                  */
-    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint16_t DITHER:1;         /*!< bit:      7  Dithering Mode                     */
-    uint16_t REFRESH:4;        /*!< bit:  8..11  Refresh period                     */
-    uint16_t :1;               /*!< bit:     12  Reserved                           */
-    uint16_t OSR:3;            /*!< bit: 13..15  Sampling Rate                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DAC_DACCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DACCTRL_OFFSET          0x0C         /**< \brief (DAC_DACCTRL offset) DAC n Control */
-#define DAC_DACCTRL_RESETVALUE      _U_(0x0000)  /**< \brief (DAC_DACCTRL reset_value) DAC n Control */
-
-#define DAC_DACCTRL_LEFTADJ_Pos     0            /**< \brief (DAC_DACCTRL) Left Adjusted Data */
-#define DAC_DACCTRL_LEFTADJ         (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
-#define DAC_DACCTRL_ENABLE_Pos      1            /**< \brief (DAC_DACCTRL) Enable DAC0 */
-#define DAC_DACCTRL_ENABLE          (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
-#define DAC_DACCTRL_CCTRL_Pos       2            /**< \brief (DAC_DACCTRL) Current Control */
-#define DAC_DACCTRL_CCTRL_Msk       (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_CCTRL(value)    (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
-#define   DAC_DACCTRL_CCTRL_CC100K_Val    _U_(0x0)   /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */
-#define   DAC_DACCTRL_CCTRL_CC1M_Val      _U_(0x1)   /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC  ≤ 6MHz (500kSPS) */
-#define   DAC_DACCTRL_CCTRL_CC12M_Val     _U_(0x2)   /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */
-#define DAC_DACCTRL_CCTRL_CC100K    (DAC_DACCTRL_CCTRL_CC100K_Val  << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_CCTRL_CC1M      (DAC_DACCTRL_CCTRL_CC1M_Val    << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_CCTRL_CC12M     (DAC_DACCTRL_CCTRL_CC12M_Val   << DAC_DACCTRL_CCTRL_Pos)
-#define DAC_DACCTRL_FEXT_Pos        5            /**< \brief (DAC_DACCTRL) Standalone Filter */
-#define DAC_DACCTRL_FEXT            (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)
-#define DAC_DACCTRL_RUNSTDBY_Pos    6            /**< \brief (DAC_DACCTRL) Run in Standby */
-#define DAC_DACCTRL_RUNSTDBY        (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
-#define DAC_DACCTRL_DITHER_Pos      7            /**< \brief (DAC_DACCTRL) Dithering Mode */
-#define DAC_DACCTRL_DITHER          (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
-#define DAC_DACCTRL_REFRESH_Pos     8            /**< \brief (DAC_DACCTRL) Refresh period */
-#define DAC_DACCTRL_REFRESH_Msk     (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
-#define DAC_DACCTRL_REFRESH(value)  (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
-#define DAC_DACCTRL_OSR_Pos         13           /**< \brief (DAC_DACCTRL) Sampling Rate */
-#define DAC_DACCTRL_OSR_Msk         (_U_(0x7) << DAC_DACCTRL_OSR_Pos)
-#define DAC_DACCTRL_OSR(value)      (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
-#define DAC_DACCTRL_MASK            _U_(0xEFEF)  /**< \brief (DAC_DACCTRL) MASK Register */
-
-/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DATA:16;          /*!< bit:  0..15  DAC0 Data                          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DAC_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DATA_OFFSET             0x10         /**< \brief (DAC_DATA offset) DAC n Data */
-#define DAC_DATA_RESETVALUE         _U_(0x0000)  /**< \brief (DAC_DATA reset_value) DAC n Data */
-
-#define DAC_DATA_DATA_Pos           0            /**< \brief (DAC_DATA) DAC0 Data */
-#define DAC_DATA_DATA_Msk           (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
-#define DAC_DATA_DATA(value)        (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
-#define DAC_DATA_MASK               _U_(0xFFFF)  /**< \brief (DAC_DATA) MASK Register */
-
-/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DATABUF:16;       /*!< bit:  0..15  DAC0 Data Buffer                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DAC_DATABUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DATABUF_OFFSET          0x14         /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */
-#define DAC_DATABUF_RESETVALUE      _U_(0x0000)  /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */
-
-#define DAC_DATABUF_DATABUF_Pos     0            /**< \brief (DAC_DATABUF) DAC0 Data Buffer */
-#define DAC_DATABUF_DATABUF_Msk     (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
-#define DAC_DATABUF_DATABUF(value)  (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
-#define DAC_DATABUF_MASK            _U_(0xFFFF)  /**< \brief (DAC_DATABUF) MASK Register */
-
-/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DAC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_DBGCTRL_OFFSET          0x18         /**< \brief (DAC_DBGCTRL offset) Debug Control */
-#define DAC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (DAC_DBGCTRL reset_value) Debug Control */
-
-#define DAC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (DAC_DBGCTRL) Debug Run */
-#define DAC_DBGCTRL_DBGRUN          (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
-#define DAC_DBGCTRL_MASK            _U_(0x01)    /**< \brief (DAC_DBGCTRL) MASK Register */
-
-/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/  16) Filter Result -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t RESULT:16;        /*!< bit:  0..15  Filter Result                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DAC_RESULT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DAC_RESULT_OFFSET           0x1C         /**< \brief (DAC_RESULT offset) Filter Result */
-#define DAC_RESULT_RESETVALUE       _U_(0x0000)  /**< \brief (DAC_RESULT reset_value) Filter Result */
-
-#define DAC_RESULT_RESULT_Pos       0            /**< \brief (DAC_RESULT) Filter Result */
-#define DAC_RESULT_RESULT_Msk       (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)
-#define DAC_RESULT_RESULT(value)    (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
-#define DAC_RESULT_MASK             _U_(0xFFFF)  /**< \brief (DAC_RESULT) MASK Register */
-
-/** \brief DAC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO DAC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
-  __IO DAC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x01 (R/W  8) Control B */
-  __IO DAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x02 (R/W  8) Event Control */
-       RoReg8                    Reserved1[0x1];
-  __IO DAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
-  __IO DAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
-  __IO DAC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
-  __I  DAC_STATUS_Type           STATUS;      /**< \brief Offset: 0x07 (R/   8) Status */
-  __I  DAC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
-  __IO DAC_DACCTRL_Type          DACCTRL[2];  /**< \brief Offset: 0x0C (R/W 16) DAC n Control */
-  __O  DAC_DATA_Type             DATA[2];     /**< \brief Offset: 0x10 ( /W 16) DAC n Data */
-  __O  DAC_DATABUF_Type          DATABUF[2];  /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
-  __IO DAC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x18 (R/W  8) Debug Control */
-       RoReg8                    Reserved2[0x3];
-  __I  DAC_RESULT_Type           RESULT[2];   /**< \brief Offset: 0x1C (R/  16) Filter Result */
-} Dac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_DAC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h
deleted file mode 100644
index 295b31fe48..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dmac.h
+++ /dev/null
@@ -1,1416 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for DMAC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_DMAC_COMPONENT_
-#define _SAMD51_DMAC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR DMAC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_DMAC Direct Memory Access Controller */
-/*@{*/
-
-#define DMAC_U2503
-#define REV_DMAC                    0x100
-
-/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t DMAENABLE:1;      /*!< bit:      1  DMA Enable                         */
-    uint16_t :6;               /*!< bit:  2.. 7  Reserved                           */
-    uint16_t LVLEN0:1;         /*!< bit:      8  Priority Level 0 Enable            */
-    uint16_t LVLEN1:1;         /*!< bit:      9  Priority Level 1 Enable            */
-    uint16_t LVLEN2:1;         /*!< bit:     10  Priority Level 2 Enable            */
-    uint16_t LVLEN3:1;         /*!< bit:     11  Priority Level 3 Enable            */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint16_t LVLEN:4;          /*!< bit:  8..11  Priority Level x Enable            */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CTRL_OFFSET            0x00         /**< \brief (DMAC_CTRL offset) Control */
-#define DMAC_CTRL_RESETVALUE        _U_(0x0000)  /**< \brief (DMAC_CTRL reset_value) Control */
-
-#define DMAC_CTRL_SWRST_Pos         0            /**< \brief (DMAC_CTRL) Software Reset */
-#define DMAC_CTRL_SWRST             (_U_(0x1) << DMAC_CTRL_SWRST_Pos)
-#define DMAC_CTRL_DMAENABLE_Pos     1            /**< \brief (DMAC_CTRL) DMA Enable */
-#define DMAC_CTRL_DMAENABLE         (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)
-#define DMAC_CTRL_LVLEN0_Pos        8            /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
-#define DMAC_CTRL_LVLEN0            (_U_(1) << DMAC_CTRL_LVLEN0_Pos)
-#define DMAC_CTRL_LVLEN1_Pos        9            /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
-#define DMAC_CTRL_LVLEN1            (_U_(1) << DMAC_CTRL_LVLEN1_Pos)
-#define DMAC_CTRL_LVLEN2_Pos        10           /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
-#define DMAC_CTRL_LVLEN2            (_U_(1) << DMAC_CTRL_LVLEN2_Pos)
-#define DMAC_CTRL_LVLEN3_Pos        11           /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
-#define DMAC_CTRL_LVLEN3            (_U_(1) << DMAC_CTRL_LVLEN3_Pos)
-#define DMAC_CTRL_LVLEN_Pos         8            /**< \brief (DMAC_CTRL) Priority Level x Enable */
-#define DMAC_CTRL_LVLEN_Msk         (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)
-#define DMAC_CTRL_LVLEN(value)      (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
-#define DMAC_CTRL_MASK              _U_(0x0F03)  /**< \brief (DMAC_CTRL) MASK Register */
-
-/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CRCBEATSIZE:2;    /*!< bit:  0.. 1  CRC Beat Size                      */
-    uint16_t CRCPOLY:2;        /*!< bit:  2.. 3  CRC Polynomial Type                */
-    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint16_t CRCSRC:6;         /*!< bit:  8..13  CRC Input Source                   */
-    uint16_t CRCMODE:2;        /*!< bit: 14..15  CRC Operating Mode                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_CRCCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCCTRL_OFFSET         0x02         /**< \brief (DMAC_CRCCTRL offset) CRC Control */
-#define DMAC_CRCCTRL_RESETVALUE     _U_(0x0000)  /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
-
-#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0            /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
-#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
-#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0)   /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
-#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1)   /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
-#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2)   /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
-#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
-#define DMAC_CRCCTRL_CRCPOLY_Pos    2            /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
-#define DMAC_CRCCTRL_CRCPOLY_Msk    (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
-#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val  _U_(0x0)   /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
-#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val  _U_(0x1)   /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
-#define DMAC_CRCCTRL_CRCPOLY_CRC16  (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCPOLY_CRC32  (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
-#define DMAC_CRCCTRL_CRCSRC_Pos     8            /**< \brief (DMAC_CRCCTRL) CRC Input Source */
-#define DMAC_CRCCTRL_CRCSRC_Msk     (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCSRC(value)  (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
-#define   DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0)   /**< \brief (DMAC_CRCCTRL) CRC Disabled */
-#define   DMAC_CRCCTRL_CRCSRC_IO_Val      _U_(0x1)   /**< \brief (DMAC_CRCCTRL) I/O interface */
-#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCSRC_IO      (DMAC_CRCCTRL_CRCSRC_IO_Val    << DMAC_CRCCTRL_CRCSRC_Pos)
-#define DMAC_CRCCTRL_CRCMODE_Pos    14           /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */
-#define DMAC_CRCCTRL_CRCMODE_Msk    (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos))
-#define   DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0)   /**< \brief (DMAC_CRCCTRL) Default operating mode */
-#define   DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2)   /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */
-#define   DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3)   /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */
-#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos)
-#define DMAC_CRCCTRL_MASK           _U_(0xFF0F)  /**< \brief (DMAC_CRCCTRL) MASK Register */
-
-/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CRCDATAIN:32;     /*!< bit:  0..31  CRC Data Input                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_CRCDATAIN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCDATAIN_OFFSET       0x04         /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
-#define DMAC_CRCDATAIN_RESETVALUE   _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
-
-#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0            /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
-#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
-#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
-#define DMAC_CRCDATAIN_MASK         _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */
-
-/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CRCCHKSUM:32;     /*!< bit:  0..31  CRC Checksum                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_CRCCHKSUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCCHKSUM_OFFSET       0x08         /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
-#define DMAC_CRCCHKSUM_RESETVALUE   _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
-
-#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0            /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
-#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
-#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
-#define DMAC_CRCCHKSUM_MASK         _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */
-
-/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W  8) CRC Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CRCBUSY:1;        /*!< bit:      0  CRC Module Busy                    */
-    uint8_t  CRCZERO:1;        /*!< bit:      1  CRC Zero                           */
-    uint8_t  CRCERR:1;         /*!< bit:      2  CRC Error                          */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CRCSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CRCSTATUS_OFFSET       0x0C         /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
-#define DMAC_CRCSTATUS_RESETVALUE   _U_(0x00)    /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
-
-#define DMAC_CRCSTATUS_CRCBUSY_Pos  0            /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
-#define DMAC_CRCSTATUS_CRCBUSY      (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
-#define DMAC_CRCSTATUS_CRCZERO_Pos  1            /**< \brief (DMAC_CRCSTATUS) CRC Zero */
-#define DMAC_CRCSTATUS_CRCZERO      (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
-#define DMAC_CRCSTATUS_CRCERR_Pos   2            /**< \brief (DMAC_CRCSTATUS) CRC Error */
-#define DMAC_CRCSTATUS_CRCERR       (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos)
-#define DMAC_CRCSTATUS_MASK         _U_(0x07)    /**< \brief (DMAC_CRCSTATUS) MASK Register */
-
-/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DBGCTRL_OFFSET         0x0D         /**< \brief (DMAC_DBGCTRL offset) Debug Control */
-#define DMAC_DBGCTRL_RESETVALUE     _U_(0x00)    /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
-
-#define DMAC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (DMAC_DBGCTRL) Debug Run */
-#define DMAC_DBGCTRL_DBGRUN         (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
-#define DMAC_DBGCTRL_MASK           _U_(0x01)    /**< \brief (DMAC_DBGCTRL) MASK Register */
-
-/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWTRIG0:1;        /*!< bit:      0  Channel 0 Software Trigger         */
-    uint32_t SWTRIG1:1;        /*!< bit:      1  Channel 1 Software Trigger         */
-    uint32_t SWTRIG2:1;        /*!< bit:      2  Channel 2 Software Trigger         */
-    uint32_t SWTRIG3:1;        /*!< bit:      3  Channel 3 Software Trigger         */
-    uint32_t SWTRIG4:1;        /*!< bit:      4  Channel 4 Software Trigger         */
-    uint32_t SWTRIG5:1;        /*!< bit:      5  Channel 5 Software Trigger         */
-    uint32_t SWTRIG6:1;        /*!< bit:      6  Channel 6 Software Trigger         */
-    uint32_t SWTRIG7:1;        /*!< bit:      7  Channel 7 Software Trigger         */
-    uint32_t SWTRIG8:1;        /*!< bit:      8  Channel 8 Software Trigger         */
-    uint32_t SWTRIG9:1;        /*!< bit:      9  Channel 9 Software Trigger         */
-    uint32_t SWTRIG10:1;       /*!< bit:     10  Channel 10 Software Trigger        */
-    uint32_t SWTRIG11:1;       /*!< bit:     11  Channel 11 Software Trigger        */
-    uint32_t SWTRIG12:1;       /*!< bit:     12  Channel 12 Software Trigger        */
-    uint32_t SWTRIG13:1;       /*!< bit:     13  Channel 13 Software Trigger        */
-    uint32_t SWTRIG14:1;       /*!< bit:     14  Channel 14 Software Trigger        */
-    uint32_t SWTRIG15:1;       /*!< bit:     15  Channel 15 Software Trigger        */
-    uint32_t SWTRIG16:1;       /*!< bit:     16  Channel 16 Software Trigger        */
-    uint32_t SWTRIG17:1;       /*!< bit:     17  Channel 17 Software Trigger        */
-    uint32_t SWTRIG18:1;       /*!< bit:     18  Channel 18 Software Trigger        */
-    uint32_t SWTRIG19:1;       /*!< bit:     19  Channel 19 Software Trigger        */
-    uint32_t SWTRIG20:1;       /*!< bit:     20  Channel 20 Software Trigger        */
-    uint32_t SWTRIG21:1;       /*!< bit:     21  Channel 21 Software Trigger        */
-    uint32_t SWTRIG22:1;       /*!< bit:     22  Channel 22 Software Trigger        */
-    uint32_t SWTRIG23:1;       /*!< bit:     23  Channel 23 Software Trigger        */
-    uint32_t SWTRIG24:1;       /*!< bit:     24  Channel 24 Software Trigger        */
-    uint32_t SWTRIG25:1;       /*!< bit:     25  Channel 25 Software Trigger        */
-    uint32_t SWTRIG26:1;       /*!< bit:     26  Channel 26 Software Trigger        */
-    uint32_t SWTRIG27:1;       /*!< bit:     27  Channel 27 Software Trigger        */
-    uint32_t SWTRIG28:1;       /*!< bit:     28  Channel 28 Software Trigger        */
-    uint32_t SWTRIG29:1;       /*!< bit:     29  Channel 29 Software Trigger        */
-    uint32_t SWTRIG30:1;       /*!< bit:     30  Channel 30 Software Trigger        */
-    uint32_t SWTRIG31:1;       /*!< bit:     31  Channel 31 Software Trigger        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t SWTRIG:32;        /*!< bit:  0..31  Channel x Software Trigger         */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_SWTRIGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_SWTRIGCTRL_OFFSET      0x10         /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
-#define DMAC_SWTRIGCTRL_RESETVALUE  _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
-
-#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0            /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG0     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1            /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG1     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2            /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG2     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3            /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG3     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4            /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG4     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5            /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG5     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6            /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG6     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7            /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG7     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8            /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG8     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9            /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG9     (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10           /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG10    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11           /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG11    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12           /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG12    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13           /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG13    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14           /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG14    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15           /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG15    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16           /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG16    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17           /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG17    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18           /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG18    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19           /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG19    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20           /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG20    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21           /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG21    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22           /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG22    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23           /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG23    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24           /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG24    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25           /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG25    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26           /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG26    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27           /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG27    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28           /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG28    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29           /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG29    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30           /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG30    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31           /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG31    (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG_Pos  0            /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
-#define DMAC_SWTRIGCTRL_SWTRIG_Msk  (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
-#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
-#define DMAC_SWTRIGCTRL_MASK        _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
-
-/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LVLPRI0:5;        /*!< bit:  0.. 4  Level 0 Channel Priority Number    */
-    uint32_t QOS0:2;           /*!< bit:  5.. 6  Level 0 Quality of Service         */
-    uint32_t RRLVLEN0:1;       /*!< bit:      7  Level 0 Round-Robin Scheduling Enable */
-    uint32_t LVLPRI1:5;        /*!< bit:  8..12  Level 1 Channel Priority Number    */
-    uint32_t QOS1:2;           /*!< bit: 13..14  Level 1 Quality of Service         */
-    uint32_t RRLVLEN1:1;       /*!< bit:     15  Level 1 Round-Robin Scheduling Enable */
-    uint32_t LVLPRI2:5;        /*!< bit: 16..20  Level 2 Channel Priority Number    */
-    uint32_t QOS2:2;           /*!< bit: 21..22  Level 2 Quality of Service         */
-    uint32_t RRLVLEN2:1;       /*!< bit:     23  Level 2 Round-Robin Scheduling Enable */
-    uint32_t LVLPRI3:5;        /*!< bit: 24..28  Level 3 Channel Priority Number    */
-    uint32_t QOS3:2;           /*!< bit: 29..30  Level 3 Quality of Service         */
-    uint32_t RRLVLEN3:1;       /*!< bit:     31  Level 3 Round-Robin Scheduling Enable */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_PRICTRL0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_PRICTRL0_OFFSET        0x14         /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
-#define DMAC_PRICTRL0_RESETVALUE    _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
-
-#define DMAC_PRICTRL0_LVLPRI0_Pos   0            /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI0_Msk   (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos)
-#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
-#define DMAC_PRICTRL0_QOS0_Pos      5            /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */
-#define DMAC_PRICTRL0_QOS0_Msk      (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0(value)   (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos))
-#define   DMAC_PRICTRL0_QOS0_REGULAR_Val  _U_(0x0)   /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define   DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1)   /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define   DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2)   /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define   DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3)   /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS0_REGULAR  (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos)
-#define DMAC_PRICTRL0_RRLVLEN0_Pos  7            /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN0      (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
-#define DMAC_PRICTRL0_LVLPRI1_Pos   8            /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI1_Msk   (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos)
-#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
-#define DMAC_PRICTRL0_QOS1_Pos      13           /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */
-#define DMAC_PRICTRL0_QOS1_Msk      (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1(value)   (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos))
-#define   DMAC_PRICTRL0_QOS1_REGULAR_Val  _U_(0x0)   /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define   DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1)   /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define   DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2)   /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define   DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3)   /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS1_REGULAR  (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos)
-#define DMAC_PRICTRL0_RRLVLEN1_Pos  15           /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN1      (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
-#define DMAC_PRICTRL0_LVLPRI2_Pos   16           /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI2_Msk   (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos)
-#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
-#define DMAC_PRICTRL0_QOS2_Pos      21           /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */
-#define DMAC_PRICTRL0_QOS2_Msk      (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2(value)   (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos))
-#define   DMAC_PRICTRL0_QOS2_REGULAR_Val  _U_(0x0)   /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define   DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1)   /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define   DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2)   /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define   DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3)   /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS2_REGULAR  (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos)
-#define DMAC_PRICTRL0_RRLVLEN2_Pos  23           /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN2      (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
-#define DMAC_PRICTRL0_LVLPRI3_Pos   24           /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
-#define DMAC_PRICTRL0_LVLPRI3_Msk   (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos)
-#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
-#define DMAC_PRICTRL0_QOS3_Pos      29           /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */
-#define DMAC_PRICTRL0_QOS3_Msk      (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3(value)   (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos))
-#define   DMAC_PRICTRL0_QOS3_REGULAR_Val  _U_(0x0)   /**< \brief (DMAC_PRICTRL0) Regular delivery */
-#define   DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1)   /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */
-#define   DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2)   /**< \brief (DMAC_PRICTRL0) Latency sensitive */
-#define   DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3)   /**< \brief (DMAC_PRICTRL0) Latency critical */
-#define DMAC_PRICTRL0_QOS3_REGULAR  (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos)
-#define DMAC_PRICTRL0_RRLVLEN3_Pos  31           /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
-#define DMAC_PRICTRL0_RRLVLEN3      (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
-#define DMAC_PRICTRL0_MASK          _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */
-
-/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t ID:5;             /*!< bit:  0.. 4  Channel ID                         */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t TERR:1;           /*!< bit:      8  Transfer Error                     */
-    uint16_t TCMPL:1;          /*!< bit:      9  Transfer Complete                  */
-    uint16_t SUSP:1;           /*!< bit:     10  Channel Suspend                    */
-    uint16_t :1;               /*!< bit:     11  Reserved                           */
-    uint16_t CRCERR:1;         /*!< bit:     12  CRC Error                          */
-    uint16_t FERR:1;           /*!< bit:     13  Fetch Error                        */
-    uint16_t BUSY:1;           /*!< bit:     14  Busy                               */
-    uint16_t PEND:1;           /*!< bit:     15  Pending                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_INTPEND_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_INTPEND_OFFSET         0x20         /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
-#define DMAC_INTPEND_RESETVALUE     _U_(0x0000)  /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
-
-#define DMAC_INTPEND_ID_Pos         0            /**< \brief (DMAC_INTPEND) Channel ID */
-#define DMAC_INTPEND_ID_Msk         (_U_(0x1F) << DMAC_INTPEND_ID_Pos)
-#define DMAC_INTPEND_ID(value)      (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
-#define DMAC_INTPEND_TERR_Pos       8            /**< \brief (DMAC_INTPEND) Transfer Error */
-#define DMAC_INTPEND_TERR           (_U_(0x1) << DMAC_INTPEND_TERR_Pos)
-#define DMAC_INTPEND_TCMPL_Pos      9            /**< \brief (DMAC_INTPEND) Transfer Complete */
-#define DMAC_INTPEND_TCMPL          (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos)
-#define DMAC_INTPEND_SUSP_Pos       10           /**< \brief (DMAC_INTPEND) Channel Suspend */
-#define DMAC_INTPEND_SUSP           (_U_(0x1) << DMAC_INTPEND_SUSP_Pos)
-#define DMAC_INTPEND_CRCERR_Pos     12           /**< \brief (DMAC_INTPEND) CRC Error */
-#define DMAC_INTPEND_CRCERR         (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos)
-#define DMAC_INTPEND_FERR_Pos       13           /**< \brief (DMAC_INTPEND) Fetch Error */
-#define DMAC_INTPEND_FERR           (_U_(0x1) << DMAC_INTPEND_FERR_Pos)
-#define DMAC_INTPEND_BUSY_Pos       14           /**< \brief (DMAC_INTPEND) Busy */
-#define DMAC_INTPEND_BUSY           (_U_(0x1) << DMAC_INTPEND_BUSY_Pos)
-#define DMAC_INTPEND_PEND_Pos       15           /**< \brief (DMAC_INTPEND) Pending */
-#define DMAC_INTPEND_PEND           (_U_(0x1) << DMAC_INTPEND_PEND_Pos)
-#define DMAC_INTPEND_MASK           _U_(0xF71F)  /**< \brief (DMAC_INTPEND) MASK Register */
-
-/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/  32) Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHINT0:1;         /*!< bit:      0  Channel 0 Pending Interrupt        */
-    uint32_t CHINT1:1;         /*!< bit:      1  Channel 1 Pending Interrupt        */
-    uint32_t CHINT2:1;         /*!< bit:      2  Channel 2 Pending Interrupt        */
-    uint32_t CHINT3:1;         /*!< bit:      3  Channel 3 Pending Interrupt        */
-    uint32_t CHINT4:1;         /*!< bit:      4  Channel 4 Pending Interrupt        */
-    uint32_t CHINT5:1;         /*!< bit:      5  Channel 5 Pending Interrupt        */
-    uint32_t CHINT6:1;         /*!< bit:      6  Channel 6 Pending Interrupt        */
-    uint32_t CHINT7:1;         /*!< bit:      7  Channel 7 Pending Interrupt        */
-    uint32_t CHINT8:1;         /*!< bit:      8  Channel 8 Pending Interrupt        */
-    uint32_t CHINT9:1;         /*!< bit:      9  Channel 9 Pending Interrupt        */
-    uint32_t CHINT10:1;        /*!< bit:     10  Channel 10 Pending Interrupt       */
-    uint32_t CHINT11:1;        /*!< bit:     11  Channel 11 Pending Interrupt       */
-    uint32_t CHINT12:1;        /*!< bit:     12  Channel 12 Pending Interrupt       */
-    uint32_t CHINT13:1;        /*!< bit:     13  Channel 13 Pending Interrupt       */
-    uint32_t CHINT14:1;        /*!< bit:     14  Channel 14 Pending Interrupt       */
-    uint32_t CHINT15:1;        /*!< bit:     15  Channel 15 Pending Interrupt       */
-    uint32_t CHINT16:1;        /*!< bit:     16  Channel 16 Pending Interrupt       */
-    uint32_t CHINT17:1;        /*!< bit:     17  Channel 17 Pending Interrupt       */
-    uint32_t CHINT18:1;        /*!< bit:     18  Channel 18 Pending Interrupt       */
-    uint32_t CHINT19:1;        /*!< bit:     19  Channel 19 Pending Interrupt       */
-    uint32_t CHINT20:1;        /*!< bit:     20  Channel 20 Pending Interrupt       */
-    uint32_t CHINT21:1;        /*!< bit:     21  Channel 21 Pending Interrupt       */
-    uint32_t CHINT22:1;        /*!< bit:     22  Channel 22 Pending Interrupt       */
-    uint32_t CHINT23:1;        /*!< bit:     23  Channel 23 Pending Interrupt       */
-    uint32_t CHINT24:1;        /*!< bit:     24  Channel 24 Pending Interrupt       */
-    uint32_t CHINT25:1;        /*!< bit:     25  Channel 25 Pending Interrupt       */
-    uint32_t CHINT26:1;        /*!< bit:     26  Channel 26 Pending Interrupt       */
-    uint32_t CHINT27:1;        /*!< bit:     27  Channel 27 Pending Interrupt       */
-    uint32_t CHINT28:1;        /*!< bit:     28  Channel 28 Pending Interrupt       */
-    uint32_t CHINT29:1;        /*!< bit:     29  Channel 29 Pending Interrupt       */
-    uint32_t CHINT30:1;        /*!< bit:     30  Channel 30 Pending Interrupt       */
-    uint32_t CHINT31:1;        /*!< bit:     31  Channel 31 Pending Interrupt       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t CHINT:32;         /*!< bit:  0..31  Channel x Pending Interrupt        */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_INTSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_INTSTATUS_OFFSET       0x24         /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
-#define DMAC_INTSTATUS_RESETVALUE   _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
-
-#define DMAC_INTSTATUS_CHINT0_Pos   0            /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT0       (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos)
-#define DMAC_INTSTATUS_CHINT1_Pos   1            /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT1       (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos)
-#define DMAC_INTSTATUS_CHINT2_Pos   2            /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT2       (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos)
-#define DMAC_INTSTATUS_CHINT3_Pos   3            /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT3       (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos)
-#define DMAC_INTSTATUS_CHINT4_Pos   4            /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT4       (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos)
-#define DMAC_INTSTATUS_CHINT5_Pos   5            /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT5       (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos)
-#define DMAC_INTSTATUS_CHINT6_Pos   6            /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT6       (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos)
-#define DMAC_INTSTATUS_CHINT7_Pos   7            /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT7       (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos)
-#define DMAC_INTSTATUS_CHINT8_Pos   8            /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT8       (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos)
-#define DMAC_INTSTATUS_CHINT9_Pos   9            /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT9       (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos)
-#define DMAC_INTSTATUS_CHINT10_Pos  10           /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT10      (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos)
-#define DMAC_INTSTATUS_CHINT11_Pos  11           /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT11      (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos)
-#define DMAC_INTSTATUS_CHINT12_Pos  12           /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT12      (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos)
-#define DMAC_INTSTATUS_CHINT13_Pos  13           /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT13      (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos)
-#define DMAC_INTSTATUS_CHINT14_Pos  14           /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT14      (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos)
-#define DMAC_INTSTATUS_CHINT15_Pos  15           /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT15      (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos)
-#define DMAC_INTSTATUS_CHINT16_Pos  16           /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT16      (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos)
-#define DMAC_INTSTATUS_CHINT17_Pos  17           /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT17      (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos)
-#define DMAC_INTSTATUS_CHINT18_Pos  18           /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT18      (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos)
-#define DMAC_INTSTATUS_CHINT19_Pos  19           /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT19      (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos)
-#define DMAC_INTSTATUS_CHINT20_Pos  20           /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT20      (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos)
-#define DMAC_INTSTATUS_CHINT21_Pos  21           /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT21      (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos)
-#define DMAC_INTSTATUS_CHINT22_Pos  22           /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT22      (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos)
-#define DMAC_INTSTATUS_CHINT23_Pos  23           /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT23      (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos)
-#define DMAC_INTSTATUS_CHINT24_Pos  24           /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT24      (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos)
-#define DMAC_INTSTATUS_CHINT25_Pos  25           /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT25      (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos)
-#define DMAC_INTSTATUS_CHINT26_Pos  26           /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT26      (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos)
-#define DMAC_INTSTATUS_CHINT27_Pos  27           /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT27      (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos)
-#define DMAC_INTSTATUS_CHINT28_Pos  28           /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT28      (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos)
-#define DMAC_INTSTATUS_CHINT29_Pos  29           /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT29      (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos)
-#define DMAC_INTSTATUS_CHINT30_Pos  30           /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT30      (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos)
-#define DMAC_INTSTATUS_CHINT31_Pos  31           /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT31      (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos)
-#define DMAC_INTSTATUS_CHINT_Pos    0            /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
-#define DMAC_INTSTATUS_CHINT_Msk    (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos)
-#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
-#define DMAC_INTSTATUS_MASK         _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */
-
-/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/  32) Busy Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BUSYCH0:1;        /*!< bit:      0  Busy Channel 0                     */
-    uint32_t BUSYCH1:1;        /*!< bit:      1  Busy Channel 1                     */
-    uint32_t BUSYCH2:1;        /*!< bit:      2  Busy Channel 2                     */
-    uint32_t BUSYCH3:1;        /*!< bit:      3  Busy Channel 3                     */
-    uint32_t BUSYCH4:1;        /*!< bit:      4  Busy Channel 4                     */
-    uint32_t BUSYCH5:1;        /*!< bit:      5  Busy Channel 5                     */
-    uint32_t BUSYCH6:1;        /*!< bit:      6  Busy Channel 6                     */
-    uint32_t BUSYCH7:1;        /*!< bit:      7  Busy Channel 7                     */
-    uint32_t BUSYCH8:1;        /*!< bit:      8  Busy Channel 8                     */
-    uint32_t BUSYCH9:1;        /*!< bit:      9  Busy Channel 9                     */
-    uint32_t BUSYCH10:1;       /*!< bit:     10  Busy Channel 10                    */
-    uint32_t BUSYCH11:1;       /*!< bit:     11  Busy Channel 11                    */
-    uint32_t BUSYCH12:1;       /*!< bit:     12  Busy Channel 12                    */
-    uint32_t BUSYCH13:1;       /*!< bit:     13  Busy Channel 13                    */
-    uint32_t BUSYCH14:1;       /*!< bit:     14  Busy Channel 14                    */
-    uint32_t BUSYCH15:1;       /*!< bit:     15  Busy Channel 15                    */
-    uint32_t BUSYCH16:1;       /*!< bit:     16  Busy Channel 16                    */
-    uint32_t BUSYCH17:1;       /*!< bit:     17  Busy Channel 17                    */
-    uint32_t BUSYCH18:1;       /*!< bit:     18  Busy Channel 18                    */
-    uint32_t BUSYCH19:1;       /*!< bit:     19  Busy Channel 19                    */
-    uint32_t BUSYCH20:1;       /*!< bit:     20  Busy Channel 20                    */
-    uint32_t BUSYCH21:1;       /*!< bit:     21  Busy Channel 21                    */
-    uint32_t BUSYCH22:1;       /*!< bit:     22  Busy Channel 22                    */
-    uint32_t BUSYCH23:1;       /*!< bit:     23  Busy Channel 23                    */
-    uint32_t BUSYCH24:1;       /*!< bit:     24  Busy Channel 24                    */
-    uint32_t BUSYCH25:1;       /*!< bit:     25  Busy Channel 25                    */
-    uint32_t BUSYCH26:1;       /*!< bit:     26  Busy Channel 26                    */
-    uint32_t BUSYCH27:1;       /*!< bit:     27  Busy Channel 27                    */
-    uint32_t BUSYCH28:1;       /*!< bit:     28  Busy Channel 28                    */
-    uint32_t BUSYCH29:1;       /*!< bit:     29  Busy Channel 29                    */
-    uint32_t BUSYCH30:1;       /*!< bit:     30  Busy Channel 30                    */
-    uint32_t BUSYCH31:1;       /*!< bit:     31  Busy Channel 31                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t BUSYCH:32;        /*!< bit:  0..31  Busy Channel x                     */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_BUSYCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BUSYCH_OFFSET          0x28         /**< \brief (DMAC_BUSYCH offset) Busy Channels */
-#define DMAC_BUSYCH_RESETVALUE      _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
-
-#define DMAC_BUSYCH_BUSYCH0_Pos     0            /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
-#define DMAC_BUSYCH_BUSYCH0         (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos)
-#define DMAC_BUSYCH_BUSYCH1_Pos     1            /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
-#define DMAC_BUSYCH_BUSYCH1         (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos)
-#define DMAC_BUSYCH_BUSYCH2_Pos     2            /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
-#define DMAC_BUSYCH_BUSYCH2         (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos)
-#define DMAC_BUSYCH_BUSYCH3_Pos     3            /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
-#define DMAC_BUSYCH_BUSYCH3         (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos)
-#define DMAC_BUSYCH_BUSYCH4_Pos     4            /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
-#define DMAC_BUSYCH_BUSYCH4         (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos)
-#define DMAC_BUSYCH_BUSYCH5_Pos     5            /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
-#define DMAC_BUSYCH_BUSYCH5         (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos)
-#define DMAC_BUSYCH_BUSYCH6_Pos     6            /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
-#define DMAC_BUSYCH_BUSYCH6         (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos)
-#define DMAC_BUSYCH_BUSYCH7_Pos     7            /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
-#define DMAC_BUSYCH_BUSYCH7         (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos)
-#define DMAC_BUSYCH_BUSYCH8_Pos     8            /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
-#define DMAC_BUSYCH_BUSYCH8         (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos)
-#define DMAC_BUSYCH_BUSYCH9_Pos     9            /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
-#define DMAC_BUSYCH_BUSYCH9         (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos)
-#define DMAC_BUSYCH_BUSYCH10_Pos    10           /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
-#define DMAC_BUSYCH_BUSYCH10        (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos)
-#define DMAC_BUSYCH_BUSYCH11_Pos    11           /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
-#define DMAC_BUSYCH_BUSYCH11        (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos)
-#define DMAC_BUSYCH_BUSYCH12_Pos    12           /**< \brief (DMAC_BUSYCH) Busy Channel 12 */
-#define DMAC_BUSYCH_BUSYCH12        (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos)
-#define DMAC_BUSYCH_BUSYCH13_Pos    13           /**< \brief (DMAC_BUSYCH) Busy Channel 13 */
-#define DMAC_BUSYCH_BUSYCH13        (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos)
-#define DMAC_BUSYCH_BUSYCH14_Pos    14           /**< \brief (DMAC_BUSYCH) Busy Channel 14 */
-#define DMAC_BUSYCH_BUSYCH14        (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos)
-#define DMAC_BUSYCH_BUSYCH15_Pos    15           /**< \brief (DMAC_BUSYCH) Busy Channel 15 */
-#define DMAC_BUSYCH_BUSYCH15        (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos)
-#define DMAC_BUSYCH_BUSYCH16_Pos    16           /**< \brief (DMAC_BUSYCH) Busy Channel 16 */
-#define DMAC_BUSYCH_BUSYCH16        (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos)
-#define DMAC_BUSYCH_BUSYCH17_Pos    17           /**< \brief (DMAC_BUSYCH) Busy Channel 17 */
-#define DMAC_BUSYCH_BUSYCH17        (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos)
-#define DMAC_BUSYCH_BUSYCH18_Pos    18           /**< \brief (DMAC_BUSYCH) Busy Channel 18 */
-#define DMAC_BUSYCH_BUSYCH18        (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos)
-#define DMAC_BUSYCH_BUSYCH19_Pos    19           /**< \brief (DMAC_BUSYCH) Busy Channel 19 */
-#define DMAC_BUSYCH_BUSYCH19        (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos)
-#define DMAC_BUSYCH_BUSYCH20_Pos    20           /**< \brief (DMAC_BUSYCH) Busy Channel 20 */
-#define DMAC_BUSYCH_BUSYCH20        (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos)
-#define DMAC_BUSYCH_BUSYCH21_Pos    21           /**< \brief (DMAC_BUSYCH) Busy Channel 21 */
-#define DMAC_BUSYCH_BUSYCH21        (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos)
-#define DMAC_BUSYCH_BUSYCH22_Pos    22           /**< \brief (DMAC_BUSYCH) Busy Channel 22 */
-#define DMAC_BUSYCH_BUSYCH22        (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos)
-#define DMAC_BUSYCH_BUSYCH23_Pos    23           /**< \brief (DMAC_BUSYCH) Busy Channel 23 */
-#define DMAC_BUSYCH_BUSYCH23        (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos)
-#define DMAC_BUSYCH_BUSYCH24_Pos    24           /**< \brief (DMAC_BUSYCH) Busy Channel 24 */
-#define DMAC_BUSYCH_BUSYCH24        (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos)
-#define DMAC_BUSYCH_BUSYCH25_Pos    25           /**< \brief (DMAC_BUSYCH) Busy Channel 25 */
-#define DMAC_BUSYCH_BUSYCH25        (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos)
-#define DMAC_BUSYCH_BUSYCH26_Pos    26           /**< \brief (DMAC_BUSYCH) Busy Channel 26 */
-#define DMAC_BUSYCH_BUSYCH26        (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos)
-#define DMAC_BUSYCH_BUSYCH27_Pos    27           /**< \brief (DMAC_BUSYCH) Busy Channel 27 */
-#define DMAC_BUSYCH_BUSYCH27        (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos)
-#define DMAC_BUSYCH_BUSYCH28_Pos    28           /**< \brief (DMAC_BUSYCH) Busy Channel 28 */
-#define DMAC_BUSYCH_BUSYCH28        (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos)
-#define DMAC_BUSYCH_BUSYCH29_Pos    29           /**< \brief (DMAC_BUSYCH) Busy Channel 29 */
-#define DMAC_BUSYCH_BUSYCH29        (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos)
-#define DMAC_BUSYCH_BUSYCH30_Pos    30           /**< \brief (DMAC_BUSYCH) Busy Channel 30 */
-#define DMAC_BUSYCH_BUSYCH30        (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos)
-#define DMAC_BUSYCH_BUSYCH31_Pos    31           /**< \brief (DMAC_BUSYCH) Busy Channel 31 */
-#define DMAC_BUSYCH_BUSYCH31        (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos)
-#define DMAC_BUSYCH_BUSYCH_Pos      0            /**< \brief (DMAC_BUSYCH) Busy Channel x */
-#define DMAC_BUSYCH_BUSYCH_Msk      (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos)
-#define DMAC_BUSYCH_BUSYCH(value)   (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
-#define DMAC_BUSYCH_MASK            _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */
-
-/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/  32) Pending Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PENDCH0:1;        /*!< bit:      0  Pending Channel 0                  */
-    uint32_t PENDCH1:1;        /*!< bit:      1  Pending Channel 1                  */
-    uint32_t PENDCH2:1;        /*!< bit:      2  Pending Channel 2                  */
-    uint32_t PENDCH3:1;        /*!< bit:      3  Pending Channel 3                  */
-    uint32_t PENDCH4:1;        /*!< bit:      4  Pending Channel 4                  */
-    uint32_t PENDCH5:1;        /*!< bit:      5  Pending Channel 5                  */
-    uint32_t PENDCH6:1;        /*!< bit:      6  Pending Channel 6                  */
-    uint32_t PENDCH7:1;        /*!< bit:      7  Pending Channel 7                  */
-    uint32_t PENDCH8:1;        /*!< bit:      8  Pending Channel 8                  */
-    uint32_t PENDCH9:1;        /*!< bit:      9  Pending Channel 9                  */
-    uint32_t PENDCH10:1;       /*!< bit:     10  Pending Channel 10                 */
-    uint32_t PENDCH11:1;       /*!< bit:     11  Pending Channel 11                 */
-    uint32_t PENDCH12:1;       /*!< bit:     12  Pending Channel 12                 */
-    uint32_t PENDCH13:1;       /*!< bit:     13  Pending Channel 13                 */
-    uint32_t PENDCH14:1;       /*!< bit:     14  Pending Channel 14                 */
-    uint32_t PENDCH15:1;       /*!< bit:     15  Pending Channel 15                 */
-    uint32_t PENDCH16:1;       /*!< bit:     16  Pending Channel 16                 */
-    uint32_t PENDCH17:1;       /*!< bit:     17  Pending Channel 17                 */
-    uint32_t PENDCH18:1;       /*!< bit:     18  Pending Channel 18                 */
-    uint32_t PENDCH19:1;       /*!< bit:     19  Pending Channel 19                 */
-    uint32_t PENDCH20:1;       /*!< bit:     20  Pending Channel 20                 */
-    uint32_t PENDCH21:1;       /*!< bit:     21  Pending Channel 21                 */
-    uint32_t PENDCH22:1;       /*!< bit:     22  Pending Channel 22                 */
-    uint32_t PENDCH23:1;       /*!< bit:     23  Pending Channel 23                 */
-    uint32_t PENDCH24:1;       /*!< bit:     24  Pending Channel 24                 */
-    uint32_t PENDCH25:1;       /*!< bit:     25  Pending Channel 25                 */
-    uint32_t PENDCH26:1;       /*!< bit:     26  Pending Channel 26                 */
-    uint32_t PENDCH27:1;       /*!< bit:     27  Pending Channel 27                 */
-    uint32_t PENDCH28:1;       /*!< bit:     28  Pending Channel 28                 */
-    uint32_t PENDCH29:1;       /*!< bit:     29  Pending Channel 29                 */
-    uint32_t PENDCH30:1;       /*!< bit:     30  Pending Channel 30                 */
-    uint32_t PENDCH31:1;       /*!< bit:     31  Pending Channel 31                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t PENDCH:32;        /*!< bit:  0..31  Pending Channel x                  */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_PENDCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_PENDCH_OFFSET          0x2C         /**< \brief (DMAC_PENDCH offset) Pending Channels */
-#define DMAC_PENDCH_RESETVALUE      _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
-
-#define DMAC_PENDCH_PENDCH0_Pos     0            /**< \brief (DMAC_PENDCH) Pending Channel 0 */
-#define DMAC_PENDCH_PENDCH0         (_U_(1) << DMAC_PENDCH_PENDCH0_Pos)
-#define DMAC_PENDCH_PENDCH1_Pos     1            /**< \brief (DMAC_PENDCH) Pending Channel 1 */
-#define DMAC_PENDCH_PENDCH1         (_U_(1) << DMAC_PENDCH_PENDCH1_Pos)
-#define DMAC_PENDCH_PENDCH2_Pos     2            /**< \brief (DMAC_PENDCH) Pending Channel 2 */
-#define DMAC_PENDCH_PENDCH2         (_U_(1) << DMAC_PENDCH_PENDCH2_Pos)
-#define DMAC_PENDCH_PENDCH3_Pos     3            /**< \brief (DMAC_PENDCH) Pending Channel 3 */
-#define DMAC_PENDCH_PENDCH3         (_U_(1) << DMAC_PENDCH_PENDCH3_Pos)
-#define DMAC_PENDCH_PENDCH4_Pos     4            /**< \brief (DMAC_PENDCH) Pending Channel 4 */
-#define DMAC_PENDCH_PENDCH4         (_U_(1) << DMAC_PENDCH_PENDCH4_Pos)
-#define DMAC_PENDCH_PENDCH5_Pos     5            /**< \brief (DMAC_PENDCH) Pending Channel 5 */
-#define DMAC_PENDCH_PENDCH5         (_U_(1) << DMAC_PENDCH_PENDCH5_Pos)
-#define DMAC_PENDCH_PENDCH6_Pos     6            /**< \brief (DMAC_PENDCH) Pending Channel 6 */
-#define DMAC_PENDCH_PENDCH6         (_U_(1) << DMAC_PENDCH_PENDCH6_Pos)
-#define DMAC_PENDCH_PENDCH7_Pos     7            /**< \brief (DMAC_PENDCH) Pending Channel 7 */
-#define DMAC_PENDCH_PENDCH7         (_U_(1) << DMAC_PENDCH_PENDCH7_Pos)
-#define DMAC_PENDCH_PENDCH8_Pos     8            /**< \brief (DMAC_PENDCH) Pending Channel 8 */
-#define DMAC_PENDCH_PENDCH8         (_U_(1) << DMAC_PENDCH_PENDCH8_Pos)
-#define DMAC_PENDCH_PENDCH9_Pos     9            /**< \brief (DMAC_PENDCH) Pending Channel 9 */
-#define DMAC_PENDCH_PENDCH9         (_U_(1) << DMAC_PENDCH_PENDCH9_Pos)
-#define DMAC_PENDCH_PENDCH10_Pos    10           /**< \brief (DMAC_PENDCH) Pending Channel 10 */
-#define DMAC_PENDCH_PENDCH10        (_U_(1) << DMAC_PENDCH_PENDCH10_Pos)
-#define DMAC_PENDCH_PENDCH11_Pos    11           /**< \brief (DMAC_PENDCH) Pending Channel 11 */
-#define DMAC_PENDCH_PENDCH11        (_U_(1) << DMAC_PENDCH_PENDCH11_Pos)
-#define DMAC_PENDCH_PENDCH12_Pos    12           /**< \brief (DMAC_PENDCH) Pending Channel 12 */
-#define DMAC_PENDCH_PENDCH12        (_U_(1) << DMAC_PENDCH_PENDCH12_Pos)
-#define DMAC_PENDCH_PENDCH13_Pos    13           /**< \brief (DMAC_PENDCH) Pending Channel 13 */
-#define DMAC_PENDCH_PENDCH13        (_U_(1) << DMAC_PENDCH_PENDCH13_Pos)
-#define DMAC_PENDCH_PENDCH14_Pos    14           /**< \brief (DMAC_PENDCH) Pending Channel 14 */
-#define DMAC_PENDCH_PENDCH14        (_U_(1) << DMAC_PENDCH_PENDCH14_Pos)
-#define DMAC_PENDCH_PENDCH15_Pos    15           /**< \brief (DMAC_PENDCH) Pending Channel 15 */
-#define DMAC_PENDCH_PENDCH15        (_U_(1) << DMAC_PENDCH_PENDCH15_Pos)
-#define DMAC_PENDCH_PENDCH16_Pos    16           /**< \brief (DMAC_PENDCH) Pending Channel 16 */
-#define DMAC_PENDCH_PENDCH16        (_U_(1) << DMAC_PENDCH_PENDCH16_Pos)
-#define DMAC_PENDCH_PENDCH17_Pos    17           /**< \brief (DMAC_PENDCH) Pending Channel 17 */
-#define DMAC_PENDCH_PENDCH17        (_U_(1) << DMAC_PENDCH_PENDCH17_Pos)
-#define DMAC_PENDCH_PENDCH18_Pos    18           /**< \brief (DMAC_PENDCH) Pending Channel 18 */
-#define DMAC_PENDCH_PENDCH18        (_U_(1) << DMAC_PENDCH_PENDCH18_Pos)
-#define DMAC_PENDCH_PENDCH19_Pos    19           /**< \brief (DMAC_PENDCH) Pending Channel 19 */
-#define DMAC_PENDCH_PENDCH19        (_U_(1) << DMAC_PENDCH_PENDCH19_Pos)
-#define DMAC_PENDCH_PENDCH20_Pos    20           /**< \brief (DMAC_PENDCH) Pending Channel 20 */
-#define DMAC_PENDCH_PENDCH20        (_U_(1) << DMAC_PENDCH_PENDCH20_Pos)
-#define DMAC_PENDCH_PENDCH21_Pos    21           /**< \brief (DMAC_PENDCH) Pending Channel 21 */
-#define DMAC_PENDCH_PENDCH21        (_U_(1) << DMAC_PENDCH_PENDCH21_Pos)
-#define DMAC_PENDCH_PENDCH22_Pos    22           /**< \brief (DMAC_PENDCH) Pending Channel 22 */
-#define DMAC_PENDCH_PENDCH22        (_U_(1) << DMAC_PENDCH_PENDCH22_Pos)
-#define DMAC_PENDCH_PENDCH23_Pos    23           /**< \brief (DMAC_PENDCH) Pending Channel 23 */
-#define DMAC_PENDCH_PENDCH23        (_U_(1) << DMAC_PENDCH_PENDCH23_Pos)
-#define DMAC_PENDCH_PENDCH24_Pos    24           /**< \brief (DMAC_PENDCH) Pending Channel 24 */
-#define DMAC_PENDCH_PENDCH24        (_U_(1) << DMAC_PENDCH_PENDCH24_Pos)
-#define DMAC_PENDCH_PENDCH25_Pos    25           /**< \brief (DMAC_PENDCH) Pending Channel 25 */
-#define DMAC_PENDCH_PENDCH25        (_U_(1) << DMAC_PENDCH_PENDCH25_Pos)
-#define DMAC_PENDCH_PENDCH26_Pos    26           /**< \brief (DMAC_PENDCH) Pending Channel 26 */
-#define DMAC_PENDCH_PENDCH26        (_U_(1) << DMAC_PENDCH_PENDCH26_Pos)
-#define DMAC_PENDCH_PENDCH27_Pos    27           /**< \brief (DMAC_PENDCH) Pending Channel 27 */
-#define DMAC_PENDCH_PENDCH27        (_U_(1) << DMAC_PENDCH_PENDCH27_Pos)
-#define DMAC_PENDCH_PENDCH28_Pos    28           /**< \brief (DMAC_PENDCH) Pending Channel 28 */
-#define DMAC_PENDCH_PENDCH28        (_U_(1) << DMAC_PENDCH_PENDCH28_Pos)
-#define DMAC_PENDCH_PENDCH29_Pos    29           /**< \brief (DMAC_PENDCH) Pending Channel 29 */
-#define DMAC_PENDCH_PENDCH29        (_U_(1) << DMAC_PENDCH_PENDCH29_Pos)
-#define DMAC_PENDCH_PENDCH30_Pos    30           /**< \brief (DMAC_PENDCH) Pending Channel 30 */
-#define DMAC_PENDCH_PENDCH30        (_U_(1) << DMAC_PENDCH_PENDCH30_Pos)
-#define DMAC_PENDCH_PENDCH31_Pos    31           /**< \brief (DMAC_PENDCH) Pending Channel 31 */
-#define DMAC_PENDCH_PENDCH31        (_U_(1) << DMAC_PENDCH_PENDCH31_Pos)
-#define DMAC_PENDCH_PENDCH_Pos      0            /**< \brief (DMAC_PENDCH) Pending Channel x */
-#define DMAC_PENDCH_PENDCH_Msk      (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos)
-#define DMAC_PENDCH_PENDCH(value)   (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
-#define DMAC_PENDCH_MASK            _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */
-
-/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/  32) Active Channel and Levels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LVLEX0:1;         /*!< bit:      0  Level 0 Channel Trigger Request Executing */
-    uint32_t LVLEX1:1;         /*!< bit:      1  Level 1 Channel Trigger Request Executing */
-    uint32_t LVLEX2:1;         /*!< bit:      2  Level 2 Channel Trigger Request Executing */
-    uint32_t LVLEX3:1;         /*!< bit:      3  Level 3 Channel Trigger Request Executing */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t ID:5;             /*!< bit:  8..12  Active Channel ID                  */
-    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
-    uint32_t ABUSY:1;          /*!< bit:     15  Active Channel Busy                */
-    uint32_t BTCNT:16;         /*!< bit: 16..31  Active Channel Block Transfer Count */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t LVLEX:4;          /*!< bit:  0.. 3  Level x Channel Trigger Request Executing */
-    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_ACTIVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_ACTIVE_OFFSET          0x30         /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
-#define DMAC_ACTIVE_RESETVALUE      _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
-
-#define DMAC_ACTIVE_LVLEX0_Pos      0            /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX0          (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos)
-#define DMAC_ACTIVE_LVLEX1_Pos      1            /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX1          (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos)
-#define DMAC_ACTIVE_LVLEX2_Pos      2            /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX2          (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos)
-#define DMAC_ACTIVE_LVLEX3_Pos      3            /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX3          (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos)
-#define DMAC_ACTIVE_LVLEX_Pos       0            /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
-#define DMAC_ACTIVE_LVLEX_Msk       (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos)
-#define DMAC_ACTIVE_LVLEX(value)    (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
-#define DMAC_ACTIVE_ID_Pos          8            /**< \brief (DMAC_ACTIVE) Active Channel ID */
-#define DMAC_ACTIVE_ID_Msk          (_U_(0x1F) << DMAC_ACTIVE_ID_Pos)
-#define DMAC_ACTIVE_ID(value)       (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
-#define DMAC_ACTIVE_ABUSY_Pos       15           /**< \brief (DMAC_ACTIVE) Active Channel Busy */
-#define DMAC_ACTIVE_ABUSY           (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos)
-#define DMAC_ACTIVE_BTCNT_Pos       16           /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
-#define DMAC_ACTIVE_BTCNT_Msk       (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
-#define DMAC_ACTIVE_BTCNT(value)    (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
-#define DMAC_ACTIVE_MASK            _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */
-
-/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BASEADDR:32;      /*!< bit:  0..31  Descriptor Memory Base Address     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_BASEADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BASEADDR_OFFSET        0x34         /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
-#define DMAC_BASEADDR_RESETVALUE    _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
-
-#define DMAC_BASEADDR_BASEADDR_Pos  0            /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
-#define DMAC_BASEADDR_BASEADDR_Msk  (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
-#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
-#define DMAC_BASEADDR_MASK          _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */
-
-/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WRBADDR:32;       /*!< bit:  0..31  Write-Back Memory Base Address     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_WRBADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_WRBADDR_OFFSET         0x38         /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
-#define DMAC_WRBADDR_RESETVALUE     _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
-
-#define DMAC_WRBADDR_WRBADDR_Pos    0            /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
-#define DMAC_WRBADDR_WRBADDR_Msk    (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
-#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
-#define DMAC_WRBADDR_MASK           _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */
-
-/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Channel Software Reset             */
-    uint32_t ENABLE:1;         /*!< bit:      1  Channel Enable                     */
-    uint32_t :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Channel Run in Standby             */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t TRIGSRC:7;        /*!< bit:  8..14  Trigger Source                     */
-    uint32_t :5;               /*!< bit: 15..19  Reserved                           */
-    uint32_t TRIGACT:2;        /*!< bit: 20..21  Trigger Action                     */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t BURSTLEN:4;       /*!< bit: 24..27  Burst Length                       */
-    uint32_t THRESHOLD:2;      /*!< bit: 28..29  FIFO Threshold                     */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_CHCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHCTRLA_OFFSET         0x40         /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */
-#define DMAC_CHCTRLA_RESETVALUE     _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */
-
-#define DMAC_CHCTRLA_SWRST_Pos      0            /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
-#define DMAC_CHCTRLA_SWRST          (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos)
-#define DMAC_CHCTRLA_ENABLE_Pos     1            /**< \brief (DMAC_CHCTRLA) Channel Enable */
-#define DMAC_CHCTRLA_ENABLE         (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
-#define DMAC_CHCTRLA_RUNSTDBY_Pos   6            /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */
-#define DMAC_CHCTRLA_RUNSTDBY       (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)
-#define DMAC_CHCTRLA_TRIGSRC_Pos    8            /**< \brief (DMAC_CHCTRLA) Trigger Source */
-#define DMAC_CHCTRLA_TRIGSRC_Msk    (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos)
-#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos))
-#define   DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0)   /**< \brief (DMAC_CHCTRLA) Only software/event triggers */
-#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos)
-#define DMAC_CHCTRLA_TRIGACT_Pos    20           /**< \brief (DMAC_CHCTRLA) Trigger Action */
-#define DMAC_CHCTRLA_TRIGACT_Msk    (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos))
-#define   DMAC_CHCTRLA_TRIGACT_BLOCK_Val  _U_(0x0)   /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */
-#define   DMAC_CHCTRLA_TRIGACT_BURST_Val  _U_(0x2)   /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */
-#define   DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3)   /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */
-#define DMAC_CHCTRLA_TRIGACT_BLOCK  (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_TRIGACT_BURST  (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_Pos   24           /**< \brief (DMAC_CHCTRLA) Burst Length */
-#define DMAC_CHCTRLA_BURSTLEN_Msk   (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos))
-#define   DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0)   /**< \brief (DMAC_CHCTRLA) Single-beat burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1)   /**< \brief (DMAC_CHCTRLA) 2-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2)   /**< \brief (DMAC_CHCTRLA) 3-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3)   /**< \brief (DMAC_CHCTRLA) 4-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4)   /**< \brief (DMAC_CHCTRLA) 5-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5)   /**< \brief (DMAC_CHCTRLA) 6-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6)   /**< \brief (DMAC_CHCTRLA) 7-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7)   /**< \brief (DMAC_CHCTRLA) 8-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8)   /**< \brief (DMAC_CHCTRLA) 9-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9)   /**< \brief (DMAC_CHCTRLA) 10-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA)   /**< \brief (DMAC_CHCTRLA) 11-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB)   /**< \brief (DMAC_CHCTRLA) 12-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC)   /**< \brief (DMAC_CHCTRLA) 13-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD)   /**< \brief (DMAC_CHCTRLA) 14-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE)   /**< \brief (DMAC_CHCTRLA) 15-beats burst length */
-#define   DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF)   /**< \brief (DMAC_CHCTRLA) 16-beats burst length */
-#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_Pos  28           /**< \brief (DMAC_CHCTRLA) FIFO Threshold */
-#define DMAC_CHCTRLA_THRESHOLD_Msk  (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos))
-#define   DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0)   /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */
-#define   DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1)   /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */
-#define   DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2)   /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */
-#define   DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3)   /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */
-#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
-#define DMAC_CHCTRLA_MASK           _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */
-
-/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W  8) CHANNEL Channel n Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CMD:2;            /*!< bit:  0.. 1  Software Command                   */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHCTRLB_OFFSET         0x44         /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */
-#define DMAC_CHCTRLB_RESETVALUE     _U_(0x00)    /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */
-
-#define DMAC_CHCTRLB_CMD_Pos        0            /**< \brief (DMAC_CHCTRLB) Software Command */
-#define DMAC_CHCTRLB_CMD_Msk        (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD(value)     (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
-#define   DMAC_CHCTRLB_CMD_NOACT_Val      _U_(0x0)   /**< \brief (DMAC_CHCTRLB) No action */
-#define   DMAC_CHCTRLB_CMD_SUSPEND_Val    _U_(0x1)   /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
-#define   DMAC_CHCTRLB_CMD_RESUME_Val     _U_(0x2)   /**< \brief (DMAC_CHCTRLB) Channel resume operation */
-#define DMAC_CHCTRLB_CMD_NOACT      (DMAC_CHCTRLB_CMD_NOACT_Val    << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD_SUSPEND    (DMAC_CHCTRLB_CMD_SUSPEND_Val  << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_CMD_RESUME     (DMAC_CHCTRLB_CMD_RESUME_Val   << DMAC_CHCTRLB_CMD_Pos)
-#define DMAC_CHCTRLB_MASK           _U_(0x03)    /**< \brief (DMAC_CHCTRLB) MASK Register */
-
-/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W  8) CHANNEL Channel n Priority Level -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PRILVL:2;         /*!< bit:  0.. 1  Channel Priority Level             */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHPRILVL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHPRILVL_OFFSET        0x45         /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */
-#define DMAC_CHPRILVL_RESETVALUE    _U_(0x00)    /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */
-
-#define DMAC_CHPRILVL_PRILVL_Pos    0            /**< \brief (DMAC_CHPRILVL) Channel Priority Level */
-#define DMAC_CHPRILVL_PRILVL_Msk    (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos))
-#define   DMAC_CHPRILVL_PRILVL_LVL0_Val   _U_(0x0)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */
-#define   DMAC_CHPRILVL_PRILVL_LVL1_Val   _U_(0x1)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */
-#define   DMAC_CHPRILVL_PRILVL_LVL2_Val   _U_(0x2)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */
-#define   DMAC_CHPRILVL_PRILVL_LVL3_Val   _U_(0x3)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */
-#define   DMAC_CHPRILVL_PRILVL_LVL4_Val   _U_(0x4)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */
-#define   DMAC_CHPRILVL_PRILVL_LVL5_Val   _U_(0x5)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */
-#define   DMAC_CHPRILVL_PRILVL_LVL6_Val   _U_(0x6)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */
-#define   DMAC_CHPRILVL_PRILVL_LVL7_Val   _U_(0x7)   /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */
-#define DMAC_CHPRILVL_PRILVL_LVL0   (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL1   (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL2   (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL3   (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL4   (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL5   (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL6   (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_PRILVL_LVL7   (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos)
-#define DMAC_CHPRILVL_MASK          _U_(0x03)    /**< \brief (DMAC_CHPRILVL) MASK Register */
-
-/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W  8) CHANNEL Channel n Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EVACT:3;          /*!< bit:  0.. 2  Channel Event Input Action         */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  EVOMODE:2;        /*!< bit:  4.. 5  Channel Event Output Mode          */
-    uint8_t  EVIE:1;           /*!< bit:      6  Channel Event Input Enable         */
-    uint8_t  EVOE:1;           /*!< bit:      7  Channel Event Output Enable        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHEVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHEVCTRL_OFFSET        0x46         /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */
-#define DMAC_CHEVCTRL_RESETVALUE    _U_(0x00)    /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */
-
-#define DMAC_CHEVCTRL_EVACT_Pos     0            /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */
-#define DMAC_CHEVCTRL_EVACT_Msk     (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT(value)  (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos))
-#define   DMAC_CHEVCTRL_EVACT_NOACT_Val   _U_(0x0)   /**< \brief (DMAC_CHEVCTRL) No action */
-#define   DMAC_CHEVCTRL_EVACT_TRIG_Val    _U_(0x1)   /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */
-#define   DMAC_CHEVCTRL_EVACT_CTRIG_Val   _U_(0x2)   /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */
-#define   DMAC_CHEVCTRL_EVACT_CBLOCK_Val  _U_(0x3)   /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */
-#define   DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4)   /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */
-#define   DMAC_CHEVCTRL_EVACT_RESUME_Val  _U_(0x5)   /**< \brief (DMAC_CHEVCTRL) Channel resume operation */
-#define   DMAC_CHEVCTRL_EVACT_SSKIP_Val   _U_(0x6)   /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */
-#define   DMAC_CHEVCTRL_EVACT_INCPRI_Val  _U_(0x7)   /**< \brief (DMAC_CHEVCTRL) Increase priority */
-#define DMAC_CHEVCTRL_EVACT_NOACT   (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_TRIG    (DMAC_CHEVCTRL_EVACT_TRIG_Val  << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_CTRIG   (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_CBLOCK  (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_RESUME  (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_SSKIP   (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVACT_INCPRI  (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos)
-#define DMAC_CHEVCTRL_EVOMODE_Pos   4            /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */
-#define DMAC_CHEVCTRL_EVOMODE_Msk   (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos)
-#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos))
-#define   DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0)   /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */
-#define   DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1)   /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */
-#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
-#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
-#define DMAC_CHEVCTRL_EVIE_Pos      6            /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */
-#define DMAC_CHEVCTRL_EVIE          (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos)
-#define DMAC_CHEVCTRL_EVOE_Pos      7            /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */
-#define DMAC_CHEVCTRL_EVOE          (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos)
-#define DMAC_CHEVCTRL_MASK          _U_(0xF7)    /**< \brief (DMAC_CHEVCTRL) MASK Register */
-
-/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W  8) CHANNEL Channel n Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TERR:1;           /*!< bit:      0  Channel Transfer Error Interrupt Enable */
-    uint8_t  TCMPL:1;          /*!< bit:      1  Channel Transfer Complete Interrupt Enable */
-    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTENCLR_OFFSET      0x4C         /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */
-#define DMAC_CHINTENCLR_RESETVALUE  _U_(0x00)    /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
-
-#define DMAC_CHINTENCLR_TERR_Pos    0            /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
-#define DMAC_CHINTENCLR_TERR        (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos)
-#define DMAC_CHINTENCLR_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENCLR_TCMPL       (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
-#define DMAC_CHINTENCLR_SUSP_Pos    2            /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENCLR_SUSP        (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
-#define DMAC_CHINTENCLR_MASK        _U_(0x07)    /**< \brief (DMAC_CHINTENCLR) MASK Register */
-
-/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W  8) CHANNEL Channel n Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TERR:1;           /*!< bit:      0  Channel Transfer Error Interrupt Enable */
-    uint8_t  TCMPL:1;          /*!< bit:      1  Channel Transfer Complete Interrupt Enable */
-    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTENSET_OFFSET      0x4D         /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */
-#define DMAC_CHINTENSET_RESETVALUE  _U_(0x00)    /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */
-
-#define DMAC_CHINTENSET_TERR_Pos    0            /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
-#define DMAC_CHINTENSET_TERR        (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos)
-#define DMAC_CHINTENSET_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
-#define DMAC_CHINTENSET_TCMPL       (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
-#define DMAC_CHINTENSET_SUSP_Pos    2            /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
-#define DMAC_CHINTENSET_SUSP        (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos)
-#define DMAC_CHINTENSET_MASK        _U_(0x07)    /**< \brief (DMAC_CHINTENSET) MASK Register */
-
-/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W  8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  TERR:1;           /*!< bit:      0  Channel Transfer Error             */
-    __I uint8_t  TCMPL:1;          /*!< bit:      1  Channel Transfer Complete          */
-    __I uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend                    */
-    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHINTFLAG_OFFSET       0x4E         /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
-#define DMAC_CHINTFLAG_RESETVALUE   _U_(0x00)    /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
-
-#define DMAC_CHINTFLAG_TERR_Pos     0            /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
-#define DMAC_CHINTFLAG_TERR         (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos)
-#define DMAC_CHINTFLAG_TCMPL_Pos    1            /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
-#define DMAC_CHINTFLAG_TCMPL        (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
-#define DMAC_CHINTFLAG_SUSP_Pos     2            /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
-#define DMAC_CHINTFLAG_SUSP         (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
-#define DMAC_CHINTFLAG_MASK         _U_(0x07)    /**< \brief (DMAC_CHINTFLAG) MASK Register */
-
-/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W  8) CHANNEL Channel n Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PEND:1;           /*!< bit:      0  Channel Pending                    */
-    uint8_t  BUSY:1;           /*!< bit:      1  Channel Busy                       */
-    uint8_t  FERR:1;           /*!< bit:      2  Channel Fetch Error                */
-    uint8_t  CRCERR:1;         /*!< bit:      3  Channel CRC Error                  */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DMAC_CHSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_CHSTATUS_OFFSET        0x4F         /**< \brief (DMAC_CHSTATUS offset) Channel n Status */
-#define DMAC_CHSTATUS_RESETVALUE    _U_(0x00)    /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */
-
-#define DMAC_CHSTATUS_PEND_Pos      0            /**< \brief (DMAC_CHSTATUS) Channel Pending */
-#define DMAC_CHSTATUS_PEND          (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos)
-#define DMAC_CHSTATUS_BUSY_Pos      1            /**< \brief (DMAC_CHSTATUS) Channel Busy */
-#define DMAC_CHSTATUS_BUSY          (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos)
-#define DMAC_CHSTATUS_FERR_Pos      2            /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
-#define DMAC_CHSTATUS_FERR          (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos)
-#define DMAC_CHSTATUS_CRCERR_Pos    3            /**< \brief (DMAC_CHSTATUS) Channel CRC Error */
-#define DMAC_CHSTATUS_CRCERR        (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos)
-#define DMAC_CHSTATUS_MASK          _U_(0x0F)    /**< \brief (DMAC_CHSTATUS) MASK Register */
-
-/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t VALID:1;          /*!< bit:      0  Descriptor Valid                   */
-    uint16_t EVOSEL:2;         /*!< bit:  1.. 2  Block Event Output Selection       */
-    uint16_t BLOCKACT:2;       /*!< bit:  3.. 4  Block Action                       */
-    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint16_t BEATSIZE:2;       /*!< bit:  8.. 9  Beat Size                          */
-    uint16_t SRCINC:1;         /*!< bit:     10  Source Address Increment Enable    */
-    uint16_t DSTINC:1;         /*!< bit:     11  Destination Address Increment Enable */
-    uint16_t STEPSEL:1;        /*!< bit:     12  Step Selection                     */
-    uint16_t STEPSIZE:3;       /*!< bit: 13..15  Address Increment Step Size        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_BTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BTCTRL_OFFSET          0x00         /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
-#define DMAC_BTCTRL_RESETVALUE      _U_(0x0000)  /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
-
-#define DMAC_BTCTRL_VALID_Pos       0            /**< \brief (DMAC_BTCTRL) Descriptor Valid */
-#define DMAC_BTCTRL_VALID           (_U_(0x1) << DMAC_BTCTRL_VALID_Pos)
-#define DMAC_BTCTRL_EVOSEL_Pos      1            /**< \brief (DMAC_BTCTRL) Block Event Output Selection */
-#define DMAC_BTCTRL_EVOSEL_Msk      (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL(value)   (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
-#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val  _U_(0x0)   /**< \brief (DMAC_BTCTRL) Event generation disabled */
-#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val    _U_(0x1)   /**< \brief (DMAC_BTCTRL) Block event strobe */
-#define   DMAC_BTCTRL_EVOSEL_BURST_Val    _U_(0x3)   /**< \brief (DMAC_BTCTRL) Burst event strobe */
-#define DMAC_BTCTRL_EVOSEL_DISABLE  (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL_BLOCK    (DMAC_BTCTRL_EVOSEL_BLOCK_Val  << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_EVOSEL_BURST    (DMAC_BTCTRL_EVOSEL_BURST_Val  << DMAC_BTCTRL_EVOSEL_Pos)
-#define DMAC_BTCTRL_BLOCKACT_Pos    3            /**< \brief (DMAC_BTCTRL) Block Action */
-#define DMAC_BTCTRL_BLOCKACT_Msk    (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
-#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val  _U_(0x0)   /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
-#define   DMAC_BTCTRL_BLOCKACT_INT_Val    _U_(0x1)   /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
-#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2)   /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
-#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val   _U_(0x3)   /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
-#define DMAC_BTCTRL_BLOCKACT_NOACT  (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_INT    (DMAC_BTCTRL_BLOCKACT_INT_Val  << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BLOCKACT_BOTH   (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
-#define DMAC_BTCTRL_BEATSIZE_Pos    8            /**< \brief (DMAC_BTCTRL) Beat Size */
-#define DMAC_BTCTRL_BEATSIZE_Msk    (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
-#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val   _U_(0x0)   /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
-#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val  _U_(0x1)   /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
-#define   DMAC_BTCTRL_BEATSIZE_WORD_Val   _U_(0x2)   /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
-#define DMAC_BTCTRL_BEATSIZE_BYTE   (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE_HWORD  (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_BEATSIZE_WORD   (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
-#define DMAC_BTCTRL_SRCINC_Pos      10           /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
-#define DMAC_BTCTRL_SRCINC          (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos)
-#define DMAC_BTCTRL_DSTINC_Pos      11           /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
-#define DMAC_BTCTRL_DSTINC          (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos)
-#define DMAC_BTCTRL_STEPSEL_Pos     12           /**< \brief (DMAC_BTCTRL) Step Selection */
-#define DMAC_BTCTRL_STEPSEL         (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
-#define   DMAC_BTCTRL_STEPSEL_DST_Val     _U_(0x0)   /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
-#define   DMAC_BTCTRL_STEPSEL_SRC_Val     _U_(0x1)   /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
-#define DMAC_BTCTRL_STEPSEL_DST     (DMAC_BTCTRL_STEPSEL_DST_Val   << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSEL_SRC     (DMAC_BTCTRL_STEPSEL_SRC_Val   << DMAC_BTCTRL_STEPSEL_Pos)
-#define DMAC_BTCTRL_STEPSIZE_Pos    13           /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
-#define DMAC_BTCTRL_STEPSIZE_Msk    (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
-#define   DMAC_BTCTRL_STEPSIZE_X1_Val     _U_(0x0)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1 */
-#define   DMAC_BTCTRL_STEPSIZE_X2_Val     _U_(0x1)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2 */
-#define   DMAC_BTCTRL_STEPSIZE_X4_Val     _U_(0x2)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4 */
-#define   DMAC_BTCTRL_STEPSIZE_X8_Val     _U_(0x3)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8 */
-#define   DMAC_BTCTRL_STEPSIZE_X16_Val    _U_(0x4)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16 */
-#define   DMAC_BTCTRL_STEPSIZE_X32_Val    _U_(0x5)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32 */
-#define   DMAC_BTCTRL_STEPSIZE_X64_Val    _U_(0x6)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64 */
-#define   DMAC_BTCTRL_STEPSIZE_X128_Val   _U_(0x7)   /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128 */
-#define DMAC_BTCTRL_STEPSIZE_X1     (DMAC_BTCTRL_STEPSIZE_X1_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X2     (DMAC_BTCTRL_STEPSIZE_X2_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X4     (DMAC_BTCTRL_STEPSIZE_X4_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X8     (DMAC_BTCTRL_STEPSIZE_X8_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X16    (DMAC_BTCTRL_STEPSIZE_X16_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X32    (DMAC_BTCTRL_STEPSIZE_X32_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X64    (DMAC_BTCTRL_STEPSIZE_X64_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_STEPSIZE_X128   (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
-#define DMAC_BTCTRL_MASK            _U_(0xFF1F)  /**< \brief (DMAC_BTCTRL) MASK Register */
-
-/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BTCNT:16;         /*!< bit:  0..15  Block Transfer Count               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} DMAC_BTCNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_BTCNT_OFFSET           0x02         /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
-#define DMAC_BTCNT_RESETVALUE       _U_(0x0000)  /**< \brief (DMAC_BTCNT reset_value) Block Transfer Count */
-
-#define DMAC_BTCNT_BTCNT_Pos        0            /**< \brief (DMAC_BTCNT) Block Transfer Count */
-#define DMAC_BTCNT_BTCNT_Msk        (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
-#define DMAC_BTCNT_BTCNT(value)     (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
-#define DMAC_BTCNT_MASK             _U_(0xFFFF)  /**< \brief (DMAC_BTCNT) MASK Register */
-
-/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRCADDR:32;       /*!< bit:  0..31  Transfer Source Address            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_SRCADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_SRCADDR_OFFSET         0x04         /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
-#define DMAC_SRCADDR_RESETVALUE     _U_(0x00000000) /**< \brief (DMAC_SRCADDR reset_value) Block Transfer Source Address */
-
-#define DMAC_SRCADDR_SRCADDR_Pos    0            /**< \brief (DMAC_SRCADDR) Transfer Source Address */
-#define DMAC_SRCADDR_SRCADDR_Msk    (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
-#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
-#define DMAC_SRCADDR_MASK           _U_(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */
-
-/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // CRC mode
-    uint32_t CHKINIT:32;       /*!< bit:  0..31  CRC Checksum Initial Value         */
-  } CRC;                       /*!< Structure used for CRC                          */
-  struct {
-    uint32_t DSTADDR:32;       /*!< bit:  0..31  Transfer Destination Address       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_DSTADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DSTADDR_OFFSET         0x08         /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
-
-// CRC mode
-#define DMAC_DSTADDR_CRC_CHKINIT_Pos 0            /**< \brief (DMAC_DSTADDR_CRC) CRC Checksum Initial Value */
-#define DMAC_DSTADDR_CRC_CHKINIT_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_CRC_CHKINIT_Pos)
-#define DMAC_DSTADDR_CRC_CHKINIT(value) (DMAC_DSTADDR_CRC_CHKINIT_Msk & ((value) << DMAC_DSTADDR_CRC_CHKINIT_Pos))
-#define DMAC_DSTADDR_CRC_MASK       _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR_CRC) MASK Register */
-
-#define DMAC_DSTADDR_DSTADDR_Pos    0            /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
-#define DMAC_DSTADDR_DSTADDR_Msk    (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
-#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
-#define DMAC_DSTADDR_MASK           _U_(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */
-
-/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DESCADDR:32;      /*!< bit:  0..31  Next Descriptor Address            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DMAC_DESCADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DMAC_DESCADDR_OFFSET        0x0C         /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
-
-#define DMAC_DESCADDR_DESCADDR_Pos  0            /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
-#define DMAC_DESCADDR_DESCADDR_Msk  (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
-#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
-#define DMAC_DESCADDR_MASK          _U_(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */
-
-/** \brief DmacChannel hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO DMAC_CHCTRLA_Type         CHCTRLA;     /**< \brief Offset: 0x00 (R/W 32) Channel n Control A */
-  __IO DMAC_CHCTRLB_Type         CHCTRLB;     /**< \brief Offset: 0x04 (R/W  8) Channel n Control B */
-  __IO DMAC_CHPRILVL_Type        CHPRILVL;    /**< \brief Offset: 0x05 (R/W  8) Channel n Priority Level */
-  __IO DMAC_CHEVCTRL_Type        CHEVCTRL;    /**< \brief Offset: 0x06 (R/W  8) Channel n Event Control */
-       RoReg8                    Reserved1[0x5];
-  __IO DMAC_CHINTENCLR_Type      CHINTENCLR;  /**< \brief Offset: 0x0C (R/W  8) Channel n Interrupt Enable Clear */
-  __IO DMAC_CHINTENSET_Type      CHINTENSET;  /**< \brief Offset: 0x0D (R/W  8) Channel n Interrupt Enable Set */
-  __IO DMAC_CHINTFLAG_Type       CHINTFLAG;   /**< \brief Offset: 0x0E (R/W  8) Channel n Interrupt Flag Status and Clear */
-  __IO DMAC_CHSTATUS_Type        CHSTATUS;    /**< \brief Offset: 0x0F (R/W  8) Channel n Status */
-} DmacChannel;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief DMAC APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO DMAC_CTRL_Type            CTRL;        /**< \brief Offset: 0x00 (R/W 16) Control */
-  __IO DMAC_CRCCTRL_Type         CRCCTRL;     /**< \brief Offset: 0x02 (R/W 16) CRC Control */
-  __IO DMAC_CRCDATAIN_Type       CRCDATAIN;   /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
-  __IO DMAC_CRCCHKSUM_Type       CRCCHKSUM;   /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
-  __IO DMAC_CRCSTATUS_Type       CRCSTATUS;   /**< \brief Offset: 0x0C (R/W  8) CRC Status */
-  __IO DMAC_DBGCTRL_Type         DBGCTRL;     /**< \brief Offset: 0x0D (R/W  8) Debug Control */
-       RoReg8                    Reserved1[0x2];
-  __IO DMAC_SWTRIGCTRL_Type      SWTRIGCTRL;  /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
-  __IO DMAC_PRICTRL0_Type        PRICTRL0;    /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
-       RoReg8                    Reserved2[0x8];
-  __IO DMAC_INTPEND_Type         INTPEND;     /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
-       RoReg8                    Reserved3[0x2];
-  __I  DMAC_INTSTATUS_Type       INTSTATUS;   /**< \brief Offset: 0x24 (R/  32) Interrupt Status */
-  __I  DMAC_BUSYCH_Type          BUSYCH;      /**< \brief Offset: 0x28 (R/  32) Busy Channels */
-  __I  DMAC_PENDCH_Type          PENDCH;      /**< \brief Offset: 0x2C (R/  32) Pending Channels */
-  __I  DMAC_ACTIVE_Type          ACTIVE;      /**< \brief Offset: 0x30 (R/  32) Active Channel and Levels */
-  __IO DMAC_BASEADDR_Type        BASEADDR;    /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
-  __IO DMAC_WRBADDR_Type         WRBADDR;     /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
-       RoReg8                    Reserved4[0x4];
-       DmacChannel               Channel[32]; /**< \brief Offset: 0x40 DmacChannel groups [CH_NUM] */
-} Dmac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief DMAC Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO DMAC_BTCTRL_Type          BTCTRL;      /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
-  __IO DMAC_BTCNT_Type           BTCNT;       /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
-  __IO DMAC_SRCADDR_Type         SRCADDR;     /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
-  __IO DMAC_DSTADDR_Type         DSTADDR;     /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
-  __IO DMAC_DESCADDR_Type        DESCADDR;    /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
-} DmacDescriptor
-#ifdef __GNUC__
-  __attribute__ ((aligned (8)))
-#endif
-;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#ifdef __GNUC__
- #define SECTION_DMAC_DESCRIPTOR      __attribute__ ((section(".hsram")))
-#elif defined(__ICCARM__)
- #define SECTION_DMAC_DESCRIPTOR      @".hsram"
-#endif
-
-/*@}*/
-
-#endif /* _SAMD51_DMAC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dsu.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dsu.h
deleted file mode 100644
index 43ae26d208..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dsu.h
+++ /dev/null
@@ -1,1244 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for DSU
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_DSU_COMPONENT_
-#define _SAMD51_DSU_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR DSU */
-/* ========================================================================== */
-/** \addtogroup SAMD51_DSU Device Service Unit */
-/*@{*/
-
-#define DSU_U2410
-#define REV_DSU                     0x100
-
-/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  CRC:1;            /*!< bit:      2  32-bit Cyclic Redundancy Code      */
-    uint8_t  MBIST:1;          /*!< bit:      3  Memory built-in self-test          */
-    uint8_t  CE:1;             /*!< bit:      4  Chip-Erase                         */
-    uint8_t  :1;               /*!< bit:      5  Reserved                           */
-    uint8_t  ARR:1;            /*!< bit:      6  Auxiliary Row Read                 */
-    uint8_t  SMSA:1;           /*!< bit:      7  Start Memory Stream Access         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DSU_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CTRL_OFFSET             0x0000       /**< \brief (DSU_CTRL offset) Control */
-#define DSU_CTRL_RESETVALUE         _U_(0x00)    /**< \brief (DSU_CTRL reset_value) Control */
-
-#define DSU_CTRL_SWRST_Pos          0            /**< \brief (DSU_CTRL) Software Reset */
-#define DSU_CTRL_SWRST              (_U_(0x1) << DSU_CTRL_SWRST_Pos)
-#define DSU_CTRL_CRC_Pos            2            /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */
-#define DSU_CTRL_CRC                (_U_(0x1) << DSU_CTRL_CRC_Pos)
-#define DSU_CTRL_MBIST_Pos          3            /**< \brief (DSU_CTRL) Memory built-in self-test */
-#define DSU_CTRL_MBIST              (_U_(0x1) << DSU_CTRL_MBIST_Pos)
-#define DSU_CTRL_CE_Pos             4            /**< \brief (DSU_CTRL) Chip-Erase */
-#define DSU_CTRL_CE                 (_U_(0x1) << DSU_CTRL_CE_Pos)
-#define DSU_CTRL_ARR_Pos            6            /**< \brief (DSU_CTRL) Auxiliary Row Read */
-#define DSU_CTRL_ARR                (_U_(0x1) << DSU_CTRL_ARR_Pos)
-#define DSU_CTRL_SMSA_Pos           7            /**< \brief (DSU_CTRL) Start Memory Stream Access */
-#define DSU_CTRL_SMSA               (_U_(0x1) << DSU_CTRL_SMSA_Pos)
-#define DSU_CTRL_MASK               _U_(0xDD)    /**< \brief (DSU_CTRL) MASK Register */
-
-/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W  8) Status A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DONE:1;           /*!< bit:      0  Done                               */
-    uint8_t  CRSTEXT:1;        /*!< bit:      1  CPU Reset Phase Extension          */
-    uint8_t  BERR:1;           /*!< bit:      2  Bus Error                          */
-    uint8_t  FAIL:1;           /*!< bit:      3  Failure                            */
-    uint8_t  PERR:1;           /*!< bit:      4  Protection Error                   */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DSU_STATUSA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_STATUSA_OFFSET          0x0001       /**< \brief (DSU_STATUSA offset) Status A */
-#define DSU_STATUSA_RESETVALUE      _U_(0x00)    /**< \brief (DSU_STATUSA reset_value) Status A */
-
-#define DSU_STATUSA_DONE_Pos        0            /**< \brief (DSU_STATUSA) Done */
-#define DSU_STATUSA_DONE            (_U_(0x1) << DSU_STATUSA_DONE_Pos)
-#define DSU_STATUSA_CRSTEXT_Pos     1            /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
-#define DSU_STATUSA_CRSTEXT         (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos)
-#define DSU_STATUSA_BERR_Pos        2            /**< \brief (DSU_STATUSA) Bus Error */
-#define DSU_STATUSA_BERR            (_U_(0x1) << DSU_STATUSA_BERR_Pos)
-#define DSU_STATUSA_FAIL_Pos        3            /**< \brief (DSU_STATUSA) Failure */
-#define DSU_STATUSA_FAIL            (_U_(0x1) << DSU_STATUSA_FAIL_Pos)
-#define DSU_STATUSA_PERR_Pos        4            /**< \brief (DSU_STATUSA) Protection Error */
-#define DSU_STATUSA_PERR            (_U_(0x1) << DSU_STATUSA_PERR_Pos)
-#define DSU_STATUSA_MASK            _U_(0x1F)    /**< \brief (DSU_STATUSA) MASK Register */
-
-/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/   8) Status B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PROT:1;           /*!< bit:      0  Protected                          */
-    uint8_t  DBGPRES:1;        /*!< bit:      1  Debugger Present                   */
-    uint8_t  DCCD0:1;          /*!< bit:      2  Debug Communication Channel 0 Dirty */
-    uint8_t  DCCD1:1;          /*!< bit:      3  Debug Communication Channel 1 Dirty */
-    uint8_t  HPE:1;            /*!< bit:      4  Hot-Plugging Enable                */
-    uint8_t  CELCK:1;          /*!< bit:      5  Chip Erase Locked                  */
-    uint8_t  TDCCD0:1;         /*!< bit:      6  Test Debug Communication Channel 0 Dirty */
-    uint8_t  TDCCD1:1;         /*!< bit:      7  Test Debug Communication Channel 1 Dirty */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint8_t  DCCD:2;           /*!< bit:  2.. 3  Debug Communication Channel x Dirty */
-    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint8_t  TDCCD:2;          /*!< bit:  6.. 7  Test Debug Communication Channel x Dirty */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} DSU_STATUSB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_STATUSB_OFFSET          0x0002       /**< \brief (DSU_STATUSB offset) Status B */
-#define DSU_STATUSB_RESETVALUE      _U_(0x00)    /**< \brief (DSU_STATUSB reset_value) Status B */
-
-#define DSU_STATUSB_PROT_Pos        0            /**< \brief (DSU_STATUSB) Protected */
-#define DSU_STATUSB_PROT            (_U_(0x1) << DSU_STATUSB_PROT_Pos)
-#define DSU_STATUSB_DBGPRES_Pos     1            /**< \brief (DSU_STATUSB) Debugger Present */
-#define DSU_STATUSB_DBGPRES         (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos)
-#define DSU_STATUSB_DCCD0_Pos       2            /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
-#define DSU_STATUSB_DCCD0           (_U_(1) << DSU_STATUSB_DCCD0_Pos)
-#define DSU_STATUSB_DCCD1_Pos       3            /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
-#define DSU_STATUSB_DCCD1           (_U_(1) << DSU_STATUSB_DCCD1_Pos)
-#define DSU_STATUSB_DCCD_Pos        2            /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
-#define DSU_STATUSB_DCCD_Msk        (_U_(0x3) << DSU_STATUSB_DCCD_Pos)
-#define DSU_STATUSB_DCCD(value)     (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
-#define DSU_STATUSB_HPE_Pos         4            /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
-#define DSU_STATUSB_HPE             (_U_(0x1) << DSU_STATUSB_HPE_Pos)
-#define DSU_STATUSB_CELCK_Pos       5            /**< \brief (DSU_STATUSB) Chip Erase Locked */
-#define DSU_STATUSB_CELCK           (_U_(0x1) << DSU_STATUSB_CELCK_Pos)
-#define DSU_STATUSB_TDCCD0_Pos      6            /**< \brief (DSU_STATUSB) Test Debug Communication Channel 0 Dirty */
-#define DSU_STATUSB_TDCCD0          (_U_(1) << DSU_STATUSB_TDCCD0_Pos)
-#define DSU_STATUSB_TDCCD1_Pos      7            /**< \brief (DSU_STATUSB) Test Debug Communication Channel 1 Dirty */
-#define DSU_STATUSB_TDCCD1          (_U_(1) << DSU_STATUSB_TDCCD1_Pos)
-#define DSU_STATUSB_TDCCD_Pos       6            /**< \brief (DSU_STATUSB) Test Debug Communication Channel x Dirty */
-#define DSU_STATUSB_TDCCD_Msk       (_U_(0x3) << DSU_STATUSB_TDCCD_Pos)
-#define DSU_STATUSB_TDCCD(value)    (DSU_STATUSB_TDCCD_Msk & ((value) << DSU_STATUSB_TDCCD_Pos))
-#define DSU_STATUSB_MASK            _U_(0xFF)    /**< \brief (DSU_STATUSB) MASK Register */
-
-/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t AMOD:2;           /*!< bit:  0.. 1  Access Mode                        */
-    uint32_t ADDR:30;          /*!< bit:  2..31  Address                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_ADDR_OFFSET             0x0004       /**< \brief (DSU_ADDR offset) Address */
-#define DSU_ADDR_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */
-
-#define DSU_ADDR_AMOD_Pos           0            /**< \brief (DSU_ADDR) Access Mode */
-#define DSU_ADDR_AMOD_Msk           (_U_(0x3) << DSU_ADDR_AMOD_Pos)
-#define DSU_ADDR_AMOD(value)        (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))
-#define DSU_ADDR_ADDR_Pos           2            /**< \brief (DSU_ADDR) Address */
-#define DSU_ADDR_ADDR_Msk           (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)
-#define DSU_ADDR_ADDR(value)        (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
-#define DSU_ADDR_MASK               _U_(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */
-
-/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint32_t LENGTH:30;        /*!< bit:  2..31  Length                             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_LENGTH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_LENGTH_OFFSET           0x0008       /**< \brief (DSU_LENGTH offset) Length */
-#define DSU_LENGTH_RESETVALUE       _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */
-
-#define DSU_LENGTH_LENGTH_Pos       2            /**< \brief (DSU_LENGTH) Length */
-#define DSU_LENGTH_LENGTH_Msk       (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)
-#define DSU_LENGTH_LENGTH(value)    (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
-#define DSU_LENGTH_MASK             _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */
-
-/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_DATA_OFFSET             0x000C       /**< \brief (DSU_DATA offset) Data */
-#define DSU_DATA_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */
-
-#define DSU_DATA_DATA_Pos           0            /**< \brief (DSU_DATA) Data */
-#define DSU_DATA_DATA_Msk           (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos)
-#define DSU_DATA_DATA(value)        (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
-#define DSU_DATA_MASK               _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */
-
-/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_DCC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_DCC_OFFSET              0x0010       /**< \brief (DSU_DCC offset) Debug Communication Channel n */
-#define DSU_DCC_RESETVALUE          _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
-
-#define DSU_DCC_DATA_Pos            0            /**< \brief (DSU_DCC) Data */
-#define DSU_DCC_DATA_Msk            (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)
-#define DSU_DCC_DATA(value)         (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
-#define DSU_DCC_MASK                _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */
-
-/* -------- DSU_DID : (DSU Offset: 0x0018) (R/  32) Device Identification -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DEVSEL:8;         /*!< bit:  0.. 7  Device Select                      */
-    uint32_t REVISION:4;       /*!< bit:  8..11  Revision Number                    */
-    uint32_t DIE:4;            /*!< bit: 12..15  Die Number                         */
-    uint32_t SERIES:6;         /*!< bit: 16..21  Series                             */
-    uint32_t :1;               /*!< bit:     22  Reserved                           */
-    uint32_t FAMILY:5;         /*!< bit: 23..27  Family                             */
-    uint32_t PROCESSOR:4;      /*!< bit: 28..31  Processor                          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_DID_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_DID_OFFSET              0x0018       /**< \brief (DSU_DID offset) Device Identification */
-
-#define DSU_DID_DEVSEL_Pos          0            /**< \brief (DSU_DID) Device Select */
-#define DSU_DID_DEVSEL_Msk          (_U_(0xFF) << DSU_DID_DEVSEL_Pos)
-#define DSU_DID_DEVSEL(value)       (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
-#define DSU_DID_REVISION_Pos        8            /**< \brief (DSU_DID) Revision Number */
-#define DSU_DID_REVISION_Msk        (_U_(0xF) << DSU_DID_REVISION_Pos)
-#define DSU_DID_REVISION(value)     (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
-#define DSU_DID_DIE_Pos             12           /**< \brief (DSU_DID) Die Number */
-#define DSU_DID_DIE_Msk             (_U_(0xF) << DSU_DID_DIE_Pos)
-#define DSU_DID_DIE(value)          (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
-#define DSU_DID_SERIES_Pos          16           /**< \brief (DSU_DID) Series */
-#define DSU_DID_SERIES_Msk          (_U_(0x3F) << DSU_DID_SERIES_Pos)
-#define DSU_DID_SERIES(value)       (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
-#define   DSU_DID_SERIES_0_Val            _U_(0x0)   /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */
-#define   DSU_DID_SERIES_1_Val            _U_(0x1)   /**< \brief (DSU_DID) Cortex-M0+ processor, USB */
-#define DSU_DID_SERIES_0            (DSU_DID_SERIES_0_Val          << DSU_DID_SERIES_Pos)
-#define DSU_DID_SERIES_1            (DSU_DID_SERIES_1_Val          << DSU_DID_SERIES_Pos)
-#define DSU_DID_FAMILY_Pos          23           /**< \brief (DSU_DID) Family */
-#define DSU_DID_FAMILY_Msk          (_U_(0x1F) << DSU_DID_FAMILY_Pos)
-#define DSU_DID_FAMILY(value)       (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
-#define   DSU_DID_FAMILY_0_Val            _U_(0x0)   /**< \brief (DSU_DID) General purpose microcontroller */
-#define   DSU_DID_FAMILY_1_Val            _U_(0x1)   /**< \brief (DSU_DID) PicoPower */
-#define DSU_DID_FAMILY_0            (DSU_DID_FAMILY_0_Val          << DSU_DID_FAMILY_Pos)
-#define DSU_DID_FAMILY_1            (DSU_DID_FAMILY_1_Val          << DSU_DID_FAMILY_Pos)
-#define DSU_DID_PROCESSOR_Pos       28           /**< \brief (DSU_DID) Processor */
-#define DSU_DID_PROCESSOR_Msk       (_U_(0xF) << DSU_DID_PROCESSOR_Pos)
-#define DSU_DID_PROCESSOR(value)    (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
-#define   DSU_DID_PROCESSOR_CM0P_Val      _U_(0x1)   /**< \brief (DSU_DID) Cortex-M0+ */
-#define   DSU_DID_PROCESSOR_CM23_Val      _U_(0x2)   /**< \brief (DSU_DID) Cortex-M23 */
-#define   DSU_DID_PROCESSOR_CM3_Val       _U_(0x3)   /**< \brief (DSU_DID) Cortex-M3 */
-#define   DSU_DID_PROCESSOR_CM4_Val       _U_(0x5)   /**< \brief (DSU_DID) Cortex-M4 */
-#define   DSU_DID_PROCESSOR_CM4F_Val      _U_(0x6)   /**< \brief (DSU_DID) Cortex-M4 with FPU */
-#define   DSU_DID_PROCESSOR_CM33_Val      _U_(0x7)   /**< \brief (DSU_DID) Cortex-M33 */
-#define DSU_DID_PROCESSOR_CM0P      (DSU_DID_PROCESSOR_CM0P_Val    << DSU_DID_PROCESSOR_Pos)
-#define DSU_DID_PROCESSOR_CM23      (DSU_DID_PROCESSOR_CM23_Val    << DSU_DID_PROCESSOR_Pos)
-#define DSU_DID_PROCESSOR_CM3       (DSU_DID_PROCESSOR_CM3_Val     << DSU_DID_PROCESSOR_Pos)
-#define DSU_DID_PROCESSOR_CM4       (DSU_DID_PROCESSOR_CM4_Val     << DSU_DID_PROCESSOR_Pos)
-#define DSU_DID_PROCESSOR_CM4F      (DSU_DID_PROCESSOR_CM4F_Val    << DSU_DID_PROCESSOR_Pos)
-#define DSU_DID_PROCESSOR_CM33      (DSU_DID_PROCESSOR_CM33_Val    << DSU_DID_PROCESSOR_Pos)
-#define DSU_DID_MASK                _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */
-
-/* -------- DSU_CFG : (DSU Offset: 0x001C) (R/W 32) Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LQOS:2;           /*!< bit:  0.. 1  Latency Quality Of Service         */
-    uint32_t DCCDMALEVEL:2;    /*!< bit:  2.. 3  DMA Trigger Level                  */
-    uint32_t ETBRAMEN:1;       /*!< bit:      4  Trace Control                      */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_CFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CFG_OFFSET              0x001C       /**< \brief (DSU_CFG offset) Configuration */
-#define DSU_CFG_RESETVALUE          _U_(0x00000002) /**< \brief (DSU_CFG reset_value) Configuration */
-
-#define DSU_CFG_LQOS_Pos            0            /**< \brief (DSU_CFG) Latency Quality Of Service */
-#define DSU_CFG_LQOS_Msk            (_U_(0x3) << DSU_CFG_LQOS_Pos)
-#define DSU_CFG_LQOS(value)         (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos))
-#define DSU_CFG_DCCDMALEVEL_Pos     2            /**< \brief (DSU_CFG) DMA Trigger Level */
-#define DSU_CFG_DCCDMALEVEL_Msk     (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos)
-#define DSU_CFG_DCCDMALEVEL(value)  (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos))
-#define   DSU_CFG_DCCDMALEVEL_EMPTY_Val   _U_(0x0)   /**< \brief (DSU_CFG) Trigger rises when DCC is empty */
-#define   DSU_CFG_DCCDMALEVEL_FULL_Val    _U_(0x1)   /**< \brief (DSU_CFG) Trigger rises when DCC is full */
-#define DSU_CFG_DCCDMALEVEL_EMPTY   (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos)
-#define DSU_CFG_DCCDMALEVEL_FULL    (DSU_CFG_DCCDMALEVEL_FULL_Val  << DSU_CFG_DCCDMALEVEL_Pos)
-#define DSU_CFG_ETBRAMEN_Pos        4            /**< \brief (DSU_CFG) Trace Control */
-#define DSU_CFG_ETBRAMEN            (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos)
-#define DSU_CFG_MASK                _U_(0x0000001F) /**< \brief (DSU_CFG) MASK Register */
-
-/* -------- DSU_MBCTRL : (DSU Offset: 0x0040) (R/W 32) MBIST Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  MBIST Software Reset               */
-    uint32_t ENABLE:1;         /*!< bit:      1  MBIST Enable                       */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBCTRL_OFFSET           0x0040       /**< \brief (DSU_MBCTRL offset) MBIST Control */
-#define DSU_MBCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (DSU_MBCTRL reset_value) MBIST Control */
-
-#define DSU_MBCTRL_SWRST_Pos        0            /**< \brief (DSU_MBCTRL) MBIST Software Reset */
-#define DSU_MBCTRL_SWRST            (_U_(0x1) << DSU_MBCTRL_SWRST_Pos)
-#define DSU_MBCTRL_ENABLE_Pos       1            /**< \brief (DSU_MBCTRL) MBIST Enable */
-#define DSU_MBCTRL_ENABLE           (_U_(0x1) << DSU_MBCTRL_ENABLE_Pos)
-#define DSU_MBCTRL_MASK             _U_(0x00000003) /**< \brief (DSU_MBCTRL) MASK Register */
-
-/* -------- DSU_MBCONFIG : (DSU Offset: 0x0044) (R/W 32) MBIST Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ALGO:5;           /*!< bit:  0.. 4  MBIST Algorithm                    */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t DEFRDMARGIN:1;    /*!< bit:      6  Force Default Read Margin          */
-    uint32_t DBG:1;            /*!< bit:      7  Enable Debug Mode                  */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBCONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBCONFIG_OFFSET         0x0044       /**< \brief (DSU_MBCONFIG offset) MBIST Configuration */
-#define DSU_MBCONFIG_RESETVALUE     _U_(0x00000000) /**< \brief (DSU_MBCONFIG reset_value) MBIST Configuration */
-
-#define DSU_MBCONFIG_ALGO_Pos       0            /**< \brief (DSU_MBCONFIG) MBIST Algorithm */
-#define DSU_MBCONFIG_ALGO_Msk       (_U_(0x1F) << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_ALGO(value)    (DSU_MBCONFIG_ALGO_Msk & ((value) << DSU_MBCONFIG_ALGO_Pos))
-#define   DSU_MBCONFIG_ALGO_MEMCLEAR_Val  _U_(0x0)   /**< \brief (DSU_MBCONFIG) Memory Clear (1n) */
-#define   DSU_MBCONFIG_ALGO_VERIFY_Val    _U_(0x1)   /**< \brief (DSU_MBCONFIG) Memory Verify (1n) */
-#define   DSU_MBCONFIG_ALGO_CLEARVER_Val  _U_(0x2)   /**< \brief (DSU_MBCONFIG) Memory Clear and Verify (2n) */
-#define   DSU_MBCONFIG_ALGO_ADDR_DEC_Val  _U_(0x3)   /**< \brief (DSU_MBCONFIG) Address Decoder (2n) */
-#define   DSU_MBCONFIG_ALGO_MARCH_LR_Val  _U_(0x4)   /**< \brief (DSU_MBCONFIG) March LR (14n) */
-#define   DSU_MBCONFIG_ALGO_MARCH_SR_Val  _U_(0x5)   /**< \brief (DSU_MBCONFIG) March SR (14n) */
-#define   DSU_MBCONFIG_ALGO_MARCH_SS_Val  _U_(0x6)   /**< \brief (DSU_MBCONFIG) March SS (22n) */
-#define   DSU_MBCONFIG_ALGO_CRC_UP_Val    _U_(0x8)   /**< \brief (DSU_MBCONFIG) CRC increasing address (1n) */
-#define   DSU_MBCONFIG_ALGO_CRC_DOWN_Val  _U_(0x9)   /**< \brief (DSU_MBCONFIG) CRC decreasing address (1n) */
-#define DSU_MBCONFIG_ALGO_MEMCLEAR  (DSU_MBCONFIG_ALGO_MEMCLEAR_Val << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_ALGO_VERIFY    (DSU_MBCONFIG_ALGO_VERIFY_Val  << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_ALGO_CLEARVER  (DSU_MBCONFIG_ALGO_CLEARVER_Val << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_ALGO_ADDR_DEC  (DSU_MBCONFIG_ALGO_ADDR_DEC_Val << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_ALGO_MARCH_LR  (DSU_MBCONFIG_ALGO_MARCH_LR_Val << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_ALGO_MARCH_SR  (DSU_MBCONFIG_ALGO_MARCH_SR_Val << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_ALGO_MARCH_SS  (DSU_MBCONFIG_ALGO_MARCH_SS_Val << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_ALGO_CRC_UP    (DSU_MBCONFIG_ALGO_CRC_UP_Val  << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_ALGO_CRC_DOWN  (DSU_MBCONFIG_ALGO_CRC_DOWN_Val << DSU_MBCONFIG_ALGO_Pos)
-#define DSU_MBCONFIG_DEFRDMARGIN_Pos 6            /**< \brief (DSU_MBCONFIG) Force Default Read Margin */
-#define DSU_MBCONFIG_DEFRDMARGIN    (_U_(0x1) << DSU_MBCONFIG_DEFRDMARGIN_Pos)
-#define DSU_MBCONFIG_DBG_Pos        7            /**< \brief (DSU_MBCONFIG) Enable Debug Mode */
-#define DSU_MBCONFIG_DBG            (_U_(0x1) << DSU_MBCONFIG_DBG_Pos)
-#define DSU_MBCONFIG_MASK           _U_(0x000000DF) /**< \brief (DSU_MBCONFIG) MASK Register */
-
-/* -------- DSU_MBWORD : (DSU Offset: 0x0048) (R/W 32) MBIST Background Word -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  MBIST Background Word              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBWORD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBWORD_OFFSET           0x0048       /**< \brief (DSU_MBWORD offset) MBIST Background Word */
-#define DSU_MBWORD_RESETVALUE       _U_(0x00000000) /**< \brief (DSU_MBWORD reset_value) MBIST Background Word */
-
-#define DSU_MBWORD_DATA_Pos         0            /**< \brief (DSU_MBWORD) MBIST Background Word */
-#define DSU_MBWORD_DATA_Msk         (_U_(0xFFFFFFFF) << DSU_MBWORD_DATA_Pos)
-#define DSU_MBWORD_DATA(value)      (DSU_MBWORD_DATA_Msk & ((value) << DSU_MBWORD_DATA_Pos))
-#define DSU_MBWORD_MASK             _U_(0xFFFFFFFF) /**< \brief (DSU_MBWORD) MASK Register */
-
-/* -------- DSU_MBGSTAT : (DSU Offset: 0x004C) (R/W 32) MBIST Global Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ALLDONE:1;        /*!< bit:      0  MBIST Completed                    */
-    uint32_t FAILED:1;         /*!< bit:      1  MBIST Failed                       */
-    uint32_t ERRINFO:1;        /*!< bit:      2  MBIST Error Info Present           */
-    uint32_t CONFIGURED:1;     /*!< bit:      3  MBIST Configuration Sent           */
-    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBGSTAT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBGSTAT_OFFSET          0x004C       /**< \brief (DSU_MBGSTAT offset) MBIST Global Status */
-#define DSU_MBGSTAT_RESETVALUE      _U_(0x00000000) /**< \brief (DSU_MBGSTAT reset_value) MBIST Global Status */
-
-#define DSU_MBGSTAT_ALLDONE_Pos     0            /**< \brief (DSU_MBGSTAT) MBIST Completed */
-#define DSU_MBGSTAT_ALLDONE         (_U_(0x1) << DSU_MBGSTAT_ALLDONE_Pos)
-#define DSU_MBGSTAT_FAILED_Pos      1            /**< \brief (DSU_MBGSTAT) MBIST Failed */
-#define DSU_MBGSTAT_FAILED          (_U_(0x1) << DSU_MBGSTAT_FAILED_Pos)
-#define DSU_MBGSTAT_ERRINFO_Pos     2            /**< \brief (DSU_MBGSTAT) MBIST Error Info Present */
-#define DSU_MBGSTAT_ERRINFO         (_U_(0x1) << DSU_MBGSTAT_ERRINFO_Pos)
-#define DSU_MBGSTAT_CONFIGURED_Pos  3            /**< \brief (DSU_MBGSTAT) MBIST Configuration Sent */
-#define DSU_MBGSTAT_CONFIGURED      (_U_(0x1) << DSU_MBGSTAT_CONFIGURED_Pos)
-#define DSU_MBGSTAT_MASK            _U_(0x0000000F) /**< \brief (DSU_MBGSTAT) MASK Register */
-
-/* -------- DSU_MBDFAIL : (DSU Offset: 0x0050) (R/  32) MBIST Fail Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Error Data Read                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBDFAIL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBDFAIL_OFFSET          0x0050       /**< \brief (DSU_MBDFAIL offset) MBIST Fail Data */
-#define DSU_MBDFAIL_RESETVALUE      _U_(0x00000000) /**< \brief (DSU_MBDFAIL reset_value) MBIST Fail Data */
-
-#define DSU_MBDFAIL_DATA_Pos        0            /**< \brief (DSU_MBDFAIL) Error Data Read */
-#define DSU_MBDFAIL_DATA_Msk        (_U_(0xFFFFFFFF) << DSU_MBDFAIL_DATA_Pos)
-#define DSU_MBDFAIL_DATA(value)     (DSU_MBDFAIL_DATA_Msk & ((value) << DSU_MBDFAIL_DATA_Pos))
-#define DSU_MBDFAIL_MASK            _U_(0xFFFFFFFF) /**< \brief (DSU_MBDFAIL) MASK Register */
-
-/* -------- DSU_MBDEXP : (DSU Offset: 0x0054) (R/  32) MBIST Expected Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Expected Data                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBDEXP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBDEXP_OFFSET           0x0054       /**< \brief (DSU_MBDEXP offset) MBIST Expected Data */
-#define DSU_MBDEXP_RESETVALUE       _U_(0x00000000) /**< \brief (DSU_MBDEXP reset_value) MBIST Expected Data */
-
-#define DSU_MBDEXP_DATA_Pos         0            /**< \brief (DSU_MBDEXP) Expected Data */
-#define DSU_MBDEXP_DATA_Msk         (_U_(0xFFFFFFFF) << DSU_MBDEXP_DATA_Pos)
-#define DSU_MBDEXP_DATA(value)      (DSU_MBDEXP_DATA_Msk & ((value) << DSU_MBDEXP_DATA_Pos))
-#define DSU_MBDEXP_MASK             _U_(0xFFFFFFFF) /**< \brief (DSU_MBDEXP) MASK Register */
-
-/* -------- DSU_MBAFAIL : (DSU Offset: 0x0058) (R/  32) MBIST Fail Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:14;          /*!< bit:  0..13  Error Address                      */
-    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBAFAIL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBAFAIL_OFFSET          0x0058       /**< \brief (DSU_MBAFAIL offset) MBIST Fail Address */
-#define DSU_MBAFAIL_RESETVALUE      _U_(0x00000000) /**< \brief (DSU_MBAFAIL reset_value) MBIST Fail Address */
-
-#define DSU_MBAFAIL_ADDR_Pos        0            /**< \brief (DSU_MBAFAIL) Error Address */
-#define DSU_MBAFAIL_ADDR_Msk        (_U_(0x3FFF) << DSU_MBAFAIL_ADDR_Pos)
-#define DSU_MBAFAIL_ADDR(value)     (DSU_MBAFAIL_ADDR_Msk & ((value) << DSU_MBAFAIL_ADDR_Pos))
-#define DSU_MBAFAIL_MASK            _U_(0x00003FFF) /**< \brief (DSU_MBAFAIL) MASK Register */
-
-/* -------- DSU_MBCONTEXT : (DSU Offset: 0x005C) (R/  32) MBIST Fail Context -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SUBSTEP:5;        /*!< bit:  0.. 4  Algorithm Sub-step                 */
-    uint32_t STEP:5;           /*!< bit:  5.. 9  Algorithm Step                     */
-    uint32_t PORT:1;           /*!< bit:     10  DPRAM Port Index                   */
-    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBCONTEXT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBCONTEXT_OFFSET        0x005C       /**< \brief (DSU_MBCONTEXT offset) MBIST Fail Context */
-#define DSU_MBCONTEXT_RESETVALUE    _U_(0x00000000) /**< \brief (DSU_MBCONTEXT reset_value) MBIST Fail Context */
-
-#define DSU_MBCONTEXT_SUBSTEP_Pos   0            /**< \brief (DSU_MBCONTEXT) Algorithm Sub-step */
-#define DSU_MBCONTEXT_SUBSTEP_Msk   (_U_(0x1F) << DSU_MBCONTEXT_SUBSTEP_Pos)
-#define DSU_MBCONTEXT_SUBSTEP(value) (DSU_MBCONTEXT_SUBSTEP_Msk & ((value) << DSU_MBCONTEXT_SUBSTEP_Pos))
-#define   DSU_MBCONTEXT_SUBSTEP_R0_1_Val  _U_(0x1)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_SUBSTEP_R1_1_Val  _U_(0x3)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_SUBSTEP_R0_2_Val  _U_(0x5)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_SUBSTEP_R1_2_Val  _U_(0x7)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_SUBSTEP_R0_3_Val  _U_(0x9)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_SUBSTEP_R1_3_Val  _U_(0xB)   /**< \brief (DSU_MBCONTEXT)  */
-#define DSU_MBCONTEXT_SUBSTEP_R0_1  (DSU_MBCONTEXT_SUBSTEP_R0_1_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
-#define DSU_MBCONTEXT_SUBSTEP_R1_1  (DSU_MBCONTEXT_SUBSTEP_R1_1_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
-#define DSU_MBCONTEXT_SUBSTEP_R0_2  (DSU_MBCONTEXT_SUBSTEP_R0_2_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
-#define DSU_MBCONTEXT_SUBSTEP_R1_2  (DSU_MBCONTEXT_SUBSTEP_R1_2_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
-#define DSU_MBCONTEXT_SUBSTEP_R0_3  (DSU_MBCONTEXT_SUBSTEP_R0_3_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
-#define DSU_MBCONTEXT_SUBSTEP_R1_3  (DSU_MBCONTEXT_SUBSTEP_R1_3_Val << DSU_MBCONTEXT_SUBSTEP_Pos)
-#define DSU_MBCONTEXT_STEP_Pos      5            /**< \brief (DSU_MBCONTEXT) Algorithm Step */
-#define DSU_MBCONTEXT_STEP_Msk      (_U_(0x1F) << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP(value)   (DSU_MBCONTEXT_STEP_Msk & ((value) << DSU_MBCONTEXT_STEP_Pos))
-#define   DSU_MBCONTEXT_STEP_DOWN_R0W1_Val _U_(0x2)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_UP_R1W0R0W1_Val _U_(0x3)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_UP_R1W0_Val  _U_(0x4)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_UP_R0W1R1W0_Val _U_(0x5)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_UP_R0_Val    _U_(0x6)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_UP_R0R0W0R0W1_Val _U_(0x7)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_UP_R1R1W1R1W0_Val _U_(0x8)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_DOWN_R0R0W0R0W1_Val _U_(0x9)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_DOWN_R1R1W1R1W0_Val _U_(0xA)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_UP_R0R0_Val  _U_(0xC)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_DOWN_R1W0R0W1_Val _U_(0xE)   /**< \brief (DSU_MBCONTEXT)  */
-#define   DSU_MBCONTEXT_STEP_DOWN_R1R1_Val _U_(0xF)   /**< \brief (DSU_MBCONTEXT)  */
-#define DSU_MBCONTEXT_STEP_DOWN_R0W1 (DSU_MBCONTEXT_STEP_DOWN_R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_UP_R1W0R0W1 (DSU_MBCONTEXT_STEP_UP_R1W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_UP_R1W0  (DSU_MBCONTEXT_STEP_UP_R1W0_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_UP_R0W1R1W0 (DSU_MBCONTEXT_STEP_UP_R0W1R1W0_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_UP_R0    (DSU_MBCONTEXT_STEP_UP_R0_Val  << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_UP_R0R0W0R0W1 (DSU_MBCONTEXT_STEP_UP_R0R0W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_UP_R1R1W1R1W0 (DSU_MBCONTEXT_STEP_UP_R1R1W1R1W0_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_DOWN_R0R0W0R0W1 (DSU_MBCONTEXT_STEP_DOWN_R0R0W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_DOWN_R1R1W1R1W0 (DSU_MBCONTEXT_STEP_DOWN_R1R1W1R1W0_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_UP_R0R0  (DSU_MBCONTEXT_STEP_UP_R0R0_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_DOWN_R1W0R0W1 (DSU_MBCONTEXT_STEP_DOWN_R1W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_STEP_DOWN_R1R1 (DSU_MBCONTEXT_STEP_DOWN_R1R1_Val << DSU_MBCONTEXT_STEP_Pos)
-#define DSU_MBCONTEXT_PORT_Pos      10           /**< \brief (DSU_MBCONTEXT) DPRAM Port Index */
-#define DSU_MBCONTEXT_PORT          (_U_(0x1) << DSU_MBCONTEXT_PORT_Pos)
-#define DSU_MBCONTEXT_MASK          _U_(0x000007FF) /**< \brief (DSU_MBCONTEXT) MASK Register */
-
-/* -------- DSU_MBENABLE0 : (DSU Offset: 0x0060) (R/W 32) MBIST Memory Enable 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ENABLE0:1;        /*!< bit:      0  Memory 0 MBIST Enable              */
-    uint32_t ENABLE1:1;        /*!< bit:      1  Memory 1 MBIST Enable              */
-    uint32_t ENABLE2:1;        /*!< bit:      2  Memory 2 MBIST Enable              */
-    uint32_t ENABLE3:1;        /*!< bit:      3  Memory 3 MBIST Enable              */
-    uint32_t ENABLE4:1;        /*!< bit:      4  Memory 4 MBIST Enable              */
-    uint32_t ENABLE5:1;        /*!< bit:      5  Memory 5 MBIST Enable              */
-    uint32_t ENABLE6:1;        /*!< bit:      6  Memory 6 MBIST Enable              */
-    uint32_t ENABLE7:1;        /*!< bit:      7  Memory 7 MBIST Enable              */
-    uint32_t ENABLE8:1;        /*!< bit:      8  Memory 8 MBIST Enable              */
-    uint32_t ENABLE9:1;        /*!< bit:      9  Memory 9 MBIST Enable              */
-    uint32_t ENABLE10:1;       /*!< bit:     10  Memory 10 MBIST Enable             */
-    uint32_t ENABLE11:1;       /*!< bit:     11  Memory 11 MBIST Enable             */
-    uint32_t ENABLE12:1;       /*!< bit:     12  Memory 12 MBIST Enable             */
-    uint32_t ENABLE13:1;       /*!< bit:     13  Memory 13 MBIST Enable             */
-    uint32_t ENABLE14:1;       /*!< bit:     14  Memory 14 MBIST Enable             */
-    uint32_t ENABLE15:1;       /*!< bit:     15  Memory 15 MBIST Enable             */
-    uint32_t ENABLE16:1;       /*!< bit:     16  Memory 16 MBIST Enable             */
-    uint32_t ENABLE17:1;       /*!< bit:     17  Memory 17 MBIST Enable             */
-    uint32_t ENABLE18:1;       /*!< bit:     18  Memory 18 MBIST Enable             */
-    uint32_t ENABLE19:1;       /*!< bit:     19  Memory 19 MBIST Enable             */
-    uint32_t ENABLE20:1;       /*!< bit:     20  Memory 20 MBIST Enable             */
-    uint32_t ENABLE21:1;       /*!< bit:     21  Memory 21 MBIST Enable             */
-    uint32_t ENABLE22:1;       /*!< bit:     22  Memory 22 MBIST Enable             */
-    uint32_t ENABLE23:1;       /*!< bit:     23  Memory 23 MBIST Enable             */
-    uint32_t ENABLE24:1;       /*!< bit:     24  Memory 24 MBIST Enable             */
-    uint32_t ENABLE25:1;       /*!< bit:     25  Memory 25 MBIST Enable             */
-    uint32_t ENABLE26:1;       /*!< bit:     26  Memory 26 MBIST Enable             */
-    uint32_t ENABLE27:1;       /*!< bit:     27  Memory 27 MBIST Enable             */
-    uint32_t ENABLE28:1;       /*!< bit:     28  Memory 28 MBIST Enable             */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t ENABLE:29;        /*!< bit:  0..28  Memory x MBIST Enable              */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBENABLE0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBENABLE0_OFFSET        0x0060       /**< \brief (DSU_MBENABLE0 offset) MBIST Memory Enable 0 */
-#define DSU_MBENABLE0_RESETVALUE    _U_(0x00000000) /**< \brief (DSU_MBENABLE0 reset_value) MBIST Memory Enable 0 */
-
-#define DSU_MBENABLE0_ENABLE0_Pos   0            /**< \brief (DSU_MBENABLE0) Memory 0 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE0       (_U_(1) << DSU_MBENABLE0_ENABLE0_Pos)
-#define DSU_MBENABLE0_ENABLE1_Pos   1            /**< \brief (DSU_MBENABLE0) Memory 1 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE1       (_U_(1) << DSU_MBENABLE0_ENABLE1_Pos)
-#define DSU_MBENABLE0_ENABLE2_Pos   2            /**< \brief (DSU_MBENABLE0) Memory 2 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE2       (_U_(1) << DSU_MBENABLE0_ENABLE2_Pos)
-#define DSU_MBENABLE0_ENABLE3_Pos   3            /**< \brief (DSU_MBENABLE0) Memory 3 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE3       (_U_(1) << DSU_MBENABLE0_ENABLE3_Pos)
-#define DSU_MBENABLE0_ENABLE4_Pos   4            /**< \brief (DSU_MBENABLE0) Memory 4 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE4       (_U_(1) << DSU_MBENABLE0_ENABLE4_Pos)
-#define DSU_MBENABLE0_ENABLE5_Pos   5            /**< \brief (DSU_MBENABLE0) Memory 5 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE5       (_U_(1) << DSU_MBENABLE0_ENABLE5_Pos)
-#define DSU_MBENABLE0_ENABLE6_Pos   6            /**< \brief (DSU_MBENABLE0) Memory 6 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE6       (_U_(1) << DSU_MBENABLE0_ENABLE6_Pos)
-#define DSU_MBENABLE0_ENABLE7_Pos   7            /**< \brief (DSU_MBENABLE0) Memory 7 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE7       (_U_(1) << DSU_MBENABLE0_ENABLE7_Pos)
-#define DSU_MBENABLE0_ENABLE8_Pos   8            /**< \brief (DSU_MBENABLE0) Memory 8 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE8       (_U_(1) << DSU_MBENABLE0_ENABLE8_Pos)
-#define DSU_MBENABLE0_ENABLE9_Pos   9            /**< \brief (DSU_MBENABLE0) Memory 9 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE9       (_U_(1) << DSU_MBENABLE0_ENABLE9_Pos)
-#define DSU_MBENABLE0_ENABLE10_Pos  10           /**< \brief (DSU_MBENABLE0) Memory 10 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE10      (_U_(1) << DSU_MBENABLE0_ENABLE10_Pos)
-#define DSU_MBENABLE0_ENABLE11_Pos  11           /**< \brief (DSU_MBENABLE0) Memory 11 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE11      (_U_(1) << DSU_MBENABLE0_ENABLE11_Pos)
-#define DSU_MBENABLE0_ENABLE12_Pos  12           /**< \brief (DSU_MBENABLE0) Memory 12 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE12      (_U_(1) << DSU_MBENABLE0_ENABLE12_Pos)
-#define DSU_MBENABLE0_ENABLE13_Pos  13           /**< \brief (DSU_MBENABLE0) Memory 13 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE13      (_U_(1) << DSU_MBENABLE0_ENABLE13_Pos)
-#define DSU_MBENABLE0_ENABLE14_Pos  14           /**< \brief (DSU_MBENABLE0) Memory 14 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE14      (_U_(1) << DSU_MBENABLE0_ENABLE14_Pos)
-#define DSU_MBENABLE0_ENABLE15_Pos  15           /**< \brief (DSU_MBENABLE0) Memory 15 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE15      (_U_(1) << DSU_MBENABLE0_ENABLE15_Pos)
-#define DSU_MBENABLE0_ENABLE16_Pos  16           /**< \brief (DSU_MBENABLE0) Memory 16 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE16      (_U_(1) << DSU_MBENABLE0_ENABLE16_Pos)
-#define DSU_MBENABLE0_ENABLE17_Pos  17           /**< \brief (DSU_MBENABLE0) Memory 17 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE17      (_U_(1) << DSU_MBENABLE0_ENABLE17_Pos)
-#define DSU_MBENABLE0_ENABLE18_Pos  18           /**< \brief (DSU_MBENABLE0) Memory 18 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE18      (_U_(1) << DSU_MBENABLE0_ENABLE18_Pos)
-#define DSU_MBENABLE0_ENABLE19_Pos  19           /**< \brief (DSU_MBENABLE0) Memory 19 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE19      (_U_(1) << DSU_MBENABLE0_ENABLE19_Pos)
-#define DSU_MBENABLE0_ENABLE20_Pos  20           /**< \brief (DSU_MBENABLE0) Memory 20 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE20      (_U_(1) << DSU_MBENABLE0_ENABLE20_Pos)
-#define DSU_MBENABLE0_ENABLE21_Pos  21           /**< \brief (DSU_MBENABLE0) Memory 21 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE21      (_U_(1) << DSU_MBENABLE0_ENABLE21_Pos)
-#define DSU_MBENABLE0_ENABLE22_Pos  22           /**< \brief (DSU_MBENABLE0) Memory 22 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE22      (_U_(1) << DSU_MBENABLE0_ENABLE22_Pos)
-#define DSU_MBENABLE0_ENABLE23_Pos  23           /**< \brief (DSU_MBENABLE0) Memory 23 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE23      (_U_(1) << DSU_MBENABLE0_ENABLE23_Pos)
-#define DSU_MBENABLE0_ENABLE24_Pos  24           /**< \brief (DSU_MBENABLE0) Memory 24 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE24      (_U_(1) << DSU_MBENABLE0_ENABLE24_Pos)
-#define DSU_MBENABLE0_ENABLE25_Pos  25           /**< \brief (DSU_MBENABLE0) Memory 25 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE25      (_U_(1) << DSU_MBENABLE0_ENABLE25_Pos)
-#define DSU_MBENABLE0_ENABLE26_Pos  26           /**< \brief (DSU_MBENABLE0) Memory 26 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE26      (_U_(1) << DSU_MBENABLE0_ENABLE26_Pos)
-#define DSU_MBENABLE0_ENABLE27_Pos  27           /**< \brief (DSU_MBENABLE0) Memory 27 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE27      (_U_(1) << DSU_MBENABLE0_ENABLE27_Pos)
-#define DSU_MBENABLE0_ENABLE28_Pos  28           /**< \brief (DSU_MBENABLE0) Memory 28 MBIST Enable */
-#define DSU_MBENABLE0_ENABLE28      (_U_(1) << DSU_MBENABLE0_ENABLE28_Pos)
-#define DSU_MBENABLE0_ENABLE_Pos    0            /**< \brief (DSU_MBENABLE0) Memory x MBIST Enable */
-#define DSU_MBENABLE0_ENABLE_Msk    (_U_(0x1FFFFFFF) << DSU_MBENABLE0_ENABLE_Pos)
-#define DSU_MBENABLE0_ENABLE(value) (DSU_MBENABLE0_ENABLE_Msk & ((value) << DSU_MBENABLE0_ENABLE_Pos))
-#define DSU_MBENABLE0_MASK          _U_(0x1FFFFFFF) /**< \brief (DSU_MBENABLE0) MASK Register */
-
-/* -------- DSU_MBBUSY0 : (DSU Offset: 0x0068) (R/  32) MBIST Memory Busy 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BUSY0:1;          /*!< bit:      0  Memory 0 BIST Busy                 */
-    uint32_t BUSY1:1;          /*!< bit:      1  Memory 1 BIST Busy                 */
-    uint32_t BUSY2:1;          /*!< bit:      2  Memory 2 BIST Busy                 */
-    uint32_t BUSY3:1;          /*!< bit:      3  Memory 3 BIST Busy                 */
-    uint32_t BUSY4:1;          /*!< bit:      4  Memory 4 BIST Busy                 */
-    uint32_t BUSY5:1;          /*!< bit:      5  Memory 5 BIST Busy                 */
-    uint32_t BUSY6:1;          /*!< bit:      6  Memory 6 BIST Busy                 */
-    uint32_t BUSY7:1;          /*!< bit:      7  Memory 7 BIST Busy                 */
-    uint32_t BUSY8:1;          /*!< bit:      8  Memory 8 BIST Busy                 */
-    uint32_t BUSY9:1;          /*!< bit:      9  Memory 9 BIST Busy                 */
-    uint32_t BUSY10:1;         /*!< bit:     10  Memory 10 BIST Busy                */
-    uint32_t BUSY11:1;         /*!< bit:     11  Memory 11 BIST Busy                */
-    uint32_t BUSY12:1;         /*!< bit:     12  Memory 12 BIST Busy                */
-    uint32_t BUSY13:1;         /*!< bit:     13  Memory 13 BIST Busy                */
-    uint32_t BUSY14:1;         /*!< bit:     14  Memory 14 BIST Busy                */
-    uint32_t BUSY15:1;         /*!< bit:     15  Memory 15 BIST Busy                */
-    uint32_t BUSY16:1;         /*!< bit:     16  Memory 16 BIST Busy                */
-    uint32_t BUSY17:1;         /*!< bit:     17  Memory 17 BIST Busy                */
-    uint32_t BUSY18:1;         /*!< bit:     18  Memory 18 BIST Busy                */
-    uint32_t BUSY19:1;         /*!< bit:     19  Memory 19 BIST Busy                */
-    uint32_t BUSY20:1;         /*!< bit:     20  Memory 20 BIST Busy                */
-    uint32_t BUSY21:1;         /*!< bit:     21  Memory 21 BIST Busy                */
-    uint32_t BUSY22:1;         /*!< bit:     22  Memory 22 BIST Busy                */
-    uint32_t BUSY23:1;         /*!< bit:     23  Memory 23 BIST Busy                */
-    uint32_t BUSY24:1;         /*!< bit:     24  Memory 24 BIST Busy                */
-    uint32_t BUSY25:1;         /*!< bit:     25  Memory 25 BIST Busy                */
-    uint32_t BUSY26:1;         /*!< bit:     26  Memory 26 BIST Busy                */
-    uint32_t BUSY27:1;         /*!< bit:     27  Memory 27 BIST Busy                */
-    uint32_t BUSY28:1;         /*!< bit:     28  Memory 28 BIST Busy                */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t BUSY:29;          /*!< bit:  0..28  Memory x BIST Busy                 */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBBUSY0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBBUSY0_OFFSET          0x0068       /**< \brief (DSU_MBBUSY0 offset) MBIST Memory Busy 0 */
-#define DSU_MBBUSY0_RESETVALUE      _U_(0x00000000) /**< \brief (DSU_MBBUSY0 reset_value) MBIST Memory Busy 0 */
-
-#define DSU_MBBUSY0_BUSY0_Pos       0            /**< \brief (DSU_MBBUSY0) Memory 0 BIST Busy */
-#define DSU_MBBUSY0_BUSY0           (_U_(1) << DSU_MBBUSY0_BUSY0_Pos)
-#define DSU_MBBUSY0_BUSY1_Pos       1            /**< \brief (DSU_MBBUSY0) Memory 1 BIST Busy */
-#define DSU_MBBUSY0_BUSY1           (_U_(1) << DSU_MBBUSY0_BUSY1_Pos)
-#define DSU_MBBUSY0_BUSY2_Pos       2            /**< \brief (DSU_MBBUSY0) Memory 2 BIST Busy */
-#define DSU_MBBUSY0_BUSY2           (_U_(1) << DSU_MBBUSY0_BUSY2_Pos)
-#define DSU_MBBUSY0_BUSY3_Pos       3            /**< \brief (DSU_MBBUSY0) Memory 3 BIST Busy */
-#define DSU_MBBUSY0_BUSY3           (_U_(1) << DSU_MBBUSY0_BUSY3_Pos)
-#define DSU_MBBUSY0_BUSY4_Pos       4            /**< \brief (DSU_MBBUSY0) Memory 4 BIST Busy */
-#define DSU_MBBUSY0_BUSY4           (_U_(1) << DSU_MBBUSY0_BUSY4_Pos)
-#define DSU_MBBUSY0_BUSY5_Pos       5            /**< \brief (DSU_MBBUSY0) Memory 5 BIST Busy */
-#define DSU_MBBUSY0_BUSY5           (_U_(1) << DSU_MBBUSY0_BUSY5_Pos)
-#define DSU_MBBUSY0_BUSY6_Pos       6            /**< \brief (DSU_MBBUSY0) Memory 6 BIST Busy */
-#define DSU_MBBUSY0_BUSY6           (_U_(1) << DSU_MBBUSY0_BUSY6_Pos)
-#define DSU_MBBUSY0_BUSY7_Pos       7            /**< \brief (DSU_MBBUSY0) Memory 7 BIST Busy */
-#define DSU_MBBUSY0_BUSY7           (_U_(1) << DSU_MBBUSY0_BUSY7_Pos)
-#define DSU_MBBUSY0_BUSY8_Pos       8            /**< \brief (DSU_MBBUSY0) Memory 8 BIST Busy */
-#define DSU_MBBUSY0_BUSY8           (_U_(1) << DSU_MBBUSY0_BUSY8_Pos)
-#define DSU_MBBUSY0_BUSY9_Pos       9            /**< \brief (DSU_MBBUSY0) Memory 9 BIST Busy */
-#define DSU_MBBUSY0_BUSY9           (_U_(1) << DSU_MBBUSY0_BUSY9_Pos)
-#define DSU_MBBUSY0_BUSY10_Pos      10           /**< \brief (DSU_MBBUSY0) Memory 10 BIST Busy */
-#define DSU_MBBUSY0_BUSY10          (_U_(1) << DSU_MBBUSY0_BUSY10_Pos)
-#define DSU_MBBUSY0_BUSY11_Pos      11           /**< \brief (DSU_MBBUSY0) Memory 11 BIST Busy */
-#define DSU_MBBUSY0_BUSY11          (_U_(1) << DSU_MBBUSY0_BUSY11_Pos)
-#define DSU_MBBUSY0_BUSY12_Pos      12           /**< \brief (DSU_MBBUSY0) Memory 12 BIST Busy */
-#define DSU_MBBUSY0_BUSY12          (_U_(1) << DSU_MBBUSY0_BUSY12_Pos)
-#define DSU_MBBUSY0_BUSY13_Pos      13           /**< \brief (DSU_MBBUSY0) Memory 13 BIST Busy */
-#define DSU_MBBUSY0_BUSY13          (_U_(1) << DSU_MBBUSY0_BUSY13_Pos)
-#define DSU_MBBUSY0_BUSY14_Pos      14           /**< \brief (DSU_MBBUSY0) Memory 14 BIST Busy */
-#define DSU_MBBUSY0_BUSY14          (_U_(1) << DSU_MBBUSY0_BUSY14_Pos)
-#define DSU_MBBUSY0_BUSY15_Pos      15           /**< \brief (DSU_MBBUSY0) Memory 15 BIST Busy */
-#define DSU_MBBUSY0_BUSY15          (_U_(1) << DSU_MBBUSY0_BUSY15_Pos)
-#define DSU_MBBUSY0_BUSY16_Pos      16           /**< \brief (DSU_MBBUSY0) Memory 16 BIST Busy */
-#define DSU_MBBUSY0_BUSY16          (_U_(1) << DSU_MBBUSY0_BUSY16_Pos)
-#define DSU_MBBUSY0_BUSY17_Pos      17           /**< \brief (DSU_MBBUSY0) Memory 17 BIST Busy */
-#define DSU_MBBUSY0_BUSY17          (_U_(1) << DSU_MBBUSY0_BUSY17_Pos)
-#define DSU_MBBUSY0_BUSY18_Pos      18           /**< \brief (DSU_MBBUSY0) Memory 18 BIST Busy */
-#define DSU_MBBUSY0_BUSY18          (_U_(1) << DSU_MBBUSY0_BUSY18_Pos)
-#define DSU_MBBUSY0_BUSY19_Pos      19           /**< \brief (DSU_MBBUSY0) Memory 19 BIST Busy */
-#define DSU_MBBUSY0_BUSY19          (_U_(1) << DSU_MBBUSY0_BUSY19_Pos)
-#define DSU_MBBUSY0_BUSY20_Pos      20           /**< \brief (DSU_MBBUSY0) Memory 20 BIST Busy */
-#define DSU_MBBUSY0_BUSY20          (_U_(1) << DSU_MBBUSY0_BUSY20_Pos)
-#define DSU_MBBUSY0_BUSY21_Pos      21           /**< \brief (DSU_MBBUSY0) Memory 21 BIST Busy */
-#define DSU_MBBUSY0_BUSY21          (_U_(1) << DSU_MBBUSY0_BUSY21_Pos)
-#define DSU_MBBUSY0_BUSY22_Pos      22           /**< \brief (DSU_MBBUSY0) Memory 22 BIST Busy */
-#define DSU_MBBUSY0_BUSY22          (_U_(1) << DSU_MBBUSY0_BUSY22_Pos)
-#define DSU_MBBUSY0_BUSY23_Pos      23           /**< \brief (DSU_MBBUSY0) Memory 23 BIST Busy */
-#define DSU_MBBUSY0_BUSY23          (_U_(1) << DSU_MBBUSY0_BUSY23_Pos)
-#define DSU_MBBUSY0_BUSY24_Pos      24           /**< \brief (DSU_MBBUSY0) Memory 24 BIST Busy */
-#define DSU_MBBUSY0_BUSY24          (_U_(1) << DSU_MBBUSY0_BUSY24_Pos)
-#define DSU_MBBUSY0_BUSY25_Pos      25           /**< \brief (DSU_MBBUSY0) Memory 25 BIST Busy */
-#define DSU_MBBUSY0_BUSY25          (_U_(1) << DSU_MBBUSY0_BUSY25_Pos)
-#define DSU_MBBUSY0_BUSY26_Pos      26           /**< \brief (DSU_MBBUSY0) Memory 26 BIST Busy */
-#define DSU_MBBUSY0_BUSY26          (_U_(1) << DSU_MBBUSY0_BUSY26_Pos)
-#define DSU_MBBUSY0_BUSY27_Pos      27           /**< \brief (DSU_MBBUSY0) Memory 27 BIST Busy */
-#define DSU_MBBUSY0_BUSY27          (_U_(1) << DSU_MBBUSY0_BUSY27_Pos)
-#define DSU_MBBUSY0_BUSY28_Pos      28           /**< \brief (DSU_MBBUSY0) Memory 28 BIST Busy */
-#define DSU_MBBUSY0_BUSY28          (_U_(1) << DSU_MBBUSY0_BUSY28_Pos)
-#define DSU_MBBUSY0_BUSY_Pos        0            /**< \brief (DSU_MBBUSY0) Memory x BIST Busy */
-#define DSU_MBBUSY0_BUSY_Msk        (_U_(0x1FFFFFFF) << DSU_MBBUSY0_BUSY_Pos)
-#define DSU_MBBUSY0_BUSY(value)     (DSU_MBBUSY0_BUSY_Msk & ((value) << DSU_MBBUSY0_BUSY_Pos))
-#define DSU_MBBUSY0_MASK            _U_(0x1FFFFFFF) /**< \brief (DSU_MBBUSY0) MASK Register */
-
-/* -------- DSU_MBSTATUS0 : (DSU Offset: 0x0070) (R/W 32) MBIST Memory Status 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t STATUS0:1;        /*!< bit:      0  Memory 0 MBIST Status              */
-    uint32_t STATUS1:1;        /*!< bit:      1  Memory 1 MBIST Status              */
-    uint32_t STATUS2:1;        /*!< bit:      2  Memory 2 MBIST Status              */
-    uint32_t STATUS3:1;        /*!< bit:      3  Memory 3 MBIST Status              */
-    uint32_t STATUS4:1;        /*!< bit:      4  Memory 4 MBIST Status              */
-    uint32_t STATUS5:1;        /*!< bit:      5  Memory 5 MBIST Status              */
-    uint32_t STATUS6:1;        /*!< bit:      6  Memory 6 MBIST Status              */
-    uint32_t STATUS7:1;        /*!< bit:      7  Memory 7 MBIST Status              */
-    uint32_t STATUS8:1;        /*!< bit:      8  Memory 8 MBIST Status              */
-    uint32_t STATUS9:1;        /*!< bit:      9  Memory 9 MBIST Status              */
-    uint32_t STATUS10:1;       /*!< bit:     10  Memory 10 MBIST Status             */
-    uint32_t STATUS11:1;       /*!< bit:     11  Memory 11 MBIST Status             */
-    uint32_t STATUS12:1;       /*!< bit:     12  Memory 12 MBIST Status             */
-    uint32_t STATUS13:1;       /*!< bit:     13  Memory 13 MBIST Status             */
-    uint32_t STATUS14:1;       /*!< bit:     14  Memory 14 MBIST Status             */
-    uint32_t STATUS15:1;       /*!< bit:     15  Memory 15 MBIST Status             */
-    uint32_t STATUS16:1;       /*!< bit:     16  Memory 16 MBIST Status             */
-    uint32_t STATUS17:1;       /*!< bit:     17  Memory 17 MBIST Status             */
-    uint32_t STATUS18:1;       /*!< bit:     18  Memory 18 MBIST Status             */
-    uint32_t STATUS19:1;       /*!< bit:     19  Memory 19 MBIST Status             */
-    uint32_t STATUS20:1;       /*!< bit:     20  Memory 20 MBIST Status             */
-    uint32_t STATUS21:1;       /*!< bit:     21  Memory 21 MBIST Status             */
-    uint32_t STATUS22:1;       /*!< bit:     22  Memory 22 MBIST Status             */
-    uint32_t STATUS23:1;       /*!< bit:     23  Memory 23 MBIST Status             */
-    uint32_t STATUS24:1;       /*!< bit:     24  Memory 24 MBIST Status             */
-    uint32_t STATUS25:1;       /*!< bit:     25  Memory 25 MBIST Status             */
-    uint32_t STATUS26:1;       /*!< bit:     26  Memory 26 MBIST Status             */
-    uint32_t STATUS27:1;       /*!< bit:     27  Memory 27 MBIST Status             */
-    uint32_t STATUS28:1;       /*!< bit:     28  Memory 28 MBIST Status             */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t STATUS:29;        /*!< bit:  0..28  Memory x MBIST Status              */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MBSTATUS0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MBSTATUS0_OFFSET        0x0070       /**< \brief (DSU_MBSTATUS0 offset) MBIST Memory Status 0 */
-#define DSU_MBSTATUS0_RESETVALUE    _U_(0x00000000) /**< \brief (DSU_MBSTATUS0 reset_value) MBIST Memory Status 0 */
-
-#define DSU_MBSTATUS0_STATUS0_Pos   0            /**< \brief (DSU_MBSTATUS0) Memory 0 MBIST Status */
-#define DSU_MBSTATUS0_STATUS0       (_U_(1) << DSU_MBSTATUS0_STATUS0_Pos)
-#define DSU_MBSTATUS0_STATUS1_Pos   1            /**< \brief (DSU_MBSTATUS0) Memory 1 MBIST Status */
-#define DSU_MBSTATUS0_STATUS1       (_U_(1) << DSU_MBSTATUS0_STATUS1_Pos)
-#define DSU_MBSTATUS0_STATUS2_Pos   2            /**< \brief (DSU_MBSTATUS0) Memory 2 MBIST Status */
-#define DSU_MBSTATUS0_STATUS2       (_U_(1) << DSU_MBSTATUS0_STATUS2_Pos)
-#define DSU_MBSTATUS0_STATUS3_Pos   3            /**< \brief (DSU_MBSTATUS0) Memory 3 MBIST Status */
-#define DSU_MBSTATUS0_STATUS3       (_U_(1) << DSU_MBSTATUS0_STATUS3_Pos)
-#define DSU_MBSTATUS0_STATUS4_Pos   4            /**< \brief (DSU_MBSTATUS0) Memory 4 MBIST Status */
-#define DSU_MBSTATUS0_STATUS4       (_U_(1) << DSU_MBSTATUS0_STATUS4_Pos)
-#define DSU_MBSTATUS0_STATUS5_Pos   5            /**< \brief (DSU_MBSTATUS0) Memory 5 MBIST Status */
-#define DSU_MBSTATUS0_STATUS5       (_U_(1) << DSU_MBSTATUS0_STATUS5_Pos)
-#define DSU_MBSTATUS0_STATUS6_Pos   6            /**< \brief (DSU_MBSTATUS0) Memory 6 MBIST Status */
-#define DSU_MBSTATUS0_STATUS6       (_U_(1) << DSU_MBSTATUS0_STATUS6_Pos)
-#define DSU_MBSTATUS0_STATUS7_Pos   7            /**< \brief (DSU_MBSTATUS0) Memory 7 MBIST Status */
-#define DSU_MBSTATUS0_STATUS7       (_U_(1) << DSU_MBSTATUS0_STATUS7_Pos)
-#define DSU_MBSTATUS0_STATUS8_Pos   8            /**< \brief (DSU_MBSTATUS0) Memory 8 MBIST Status */
-#define DSU_MBSTATUS0_STATUS8       (_U_(1) << DSU_MBSTATUS0_STATUS8_Pos)
-#define DSU_MBSTATUS0_STATUS9_Pos   9            /**< \brief (DSU_MBSTATUS0) Memory 9 MBIST Status */
-#define DSU_MBSTATUS0_STATUS9       (_U_(1) << DSU_MBSTATUS0_STATUS9_Pos)
-#define DSU_MBSTATUS0_STATUS10_Pos  10           /**< \brief (DSU_MBSTATUS0) Memory 10 MBIST Status */
-#define DSU_MBSTATUS0_STATUS10      (_U_(1) << DSU_MBSTATUS0_STATUS10_Pos)
-#define DSU_MBSTATUS0_STATUS11_Pos  11           /**< \brief (DSU_MBSTATUS0) Memory 11 MBIST Status */
-#define DSU_MBSTATUS0_STATUS11      (_U_(1) << DSU_MBSTATUS0_STATUS11_Pos)
-#define DSU_MBSTATUS0_STATUS12_Pos  12           /**< \brief (DSU_MBSTATUS0) Memory 12 MBIST Status */
-#define DSU_MBSTATUS0_STATUS12      (_U_(1) << DSU_MBSTATUS0_STATUS12_Pos)
-#define DSU_MBSTATUS0_STATUS13_Pos  13           /**< \brief (DSU_MBSTATUS0) Memory 13 MBIST Status */
-#define DSU_MBSTATUS0_STATUS13      (_U_(1) << DSU_MBSTATUS0_STATUS13_Pos)
-#define DSU_MBSTATUS0_STATUS14_Pos  14           /**< \brief (DSU_MBSTATUS0) Memory 14 MBIST Status */
-#define DSU_MBSTATUS0_STATUS14      (_U_(1) << DSU_MBSTATUS0_STATUS14_Pos)
-#define DSU_MBSTATUS0_STATUS15_Pos  15           /**< \brief (DSU_MBSTATUS0) Memory 15 MBIST Status */
-#define DSU_MBSTATUS0_STATUS15      (_U_(1) << DSU_MBSTATUS0_STATUS15_Pos)
-#define DSU_MBSTATUS0_STATUS16_Pos  16           /**< \brief (DSU_MBSTATUS0) Memory 16 MBIST Status */
-#define DSU_MBSTATUS0_STATUS16      (_U_(1) << DSU_MBSTATUS0_STATUS16_Pos)
-#define DSU_MBSTATUS0_STATUS17_Pos  17           /**< \brief (DSU_MBSTATUS0) Memory 17 MBIST Status */
-#define DSU_MBSTATUS0_STATUS17      (_U_(1) << DSU_MBSTATUS0_STATUS17_Pos)
-#define DSU_MBSTATUS0_STATUS18_Pos  18           /**< \brief (DSU_MBSTATUS0) Memory 18 MBIST Status */
-#define DSU_MBSTATUS0_STATUS18      (_U_(1) << DSU_MBSTATUS0_STATUS18_Pos)
-#define DSU_MBSTATUS0_STATUS19_Pos  19           /**< \brief (DSU_MBSTATUS0) Memory 19 MBIST Status */
-#define DSU_MBSTATUS0_STATUS19      (_U_(1) << DSU_MBSTATUS0_STATUS19_Pos)
-#define DSU_MBSTATUS0_STATUS20_Pos  20           /**< \brief (DSU_MBSTATUS0) Memory 20 MBIST Status */
-#define DSU_MBSTATUS0_STATUS20      (_U_(1) << DSU_MBSTATUS0_STATUS20_Pos)
-#define DSU_MBSTATUS0_STATUS21_Pos  21           /**< \brief (DSU_MBSTATUS0) Memory 21 MBIST Status */
-#define DSU_MBSTATUS0_STATUS21      (_U_(1) << DSU_MBSTATUS0_STATUS21_Pos)
-#define DSU_MBSTATUS0_STATUS22_Pos  22           /**< \brief (DSU_MBSTATUS0) Memory 22 MBIST Status */
-#define DSU_MBSTATUS0_STATUS22      (_U_(1) << DSU_MBSTATUS0_STATUS22_Pos)
-#define DSU_MBSTATUS0_STATUS23_Pos  23           /**< \brief (DSU_MBSTATUS0) Memory 23 MBIST Status */
-#define DSU_MBSTATUS0_STATUS23      (_U_(1) << DSU_MBSTATUS0_STATUS23_Pos)
-#define DSU_MBSTATUS0_STATUS24_Pos  24           /**< \brief (DSU_MBSTATUS0) Memory 24 MBIST Status */
-#define DSU_MBSTATUS0_STATUS24      (_U_(1) << DSU_MBSTATUS0_STATUS24_Pos)
-#define DSU_MBSTATUS0_STATUS25_Pos  25           /**< \brief (DSU_MBSTATUS0) Memory 25 MBIST Status */
-#define DSU_MBSTATUS0_STATUS25      (_U_(1) << DSU_MBSTATUS0_STATUS25_Pos)
-#define DSU_MBSTATUS0_STATUS26_Pos  26           /**< \brief (DSU_MBSTATUS0) Memory 26 MBIST Status */
-#define DSU_MBSTATUS0_STATUS26      (_U_(1) << DSU_MBSTATUS0_STATUS26_Pos)
-#define DSU_MBSTATUS0_STATUS27_Pos  27           /**< \brief (DSU_MBSTATUS0) Memory 27 MBIST Status */
-#define DSU_MBSTATUS0_STATUS27      (_U_(1) << DSU_MBSTATUS0_STATUS27_Pos)
-#define DSU_MBSTATUS0_STATUS28_Pos  28           /**< \brief (DSU_MBSTATUS0) Memory 28 MBIST Status */
-#define DSU_MBSTATUS0_STATUS28      (_U_(1) << DSU_MBSTATUS0_STATUS28_Pos)
-#define DSU_MBSTATUS0_STATUS_Pos    0            /**< \brief (DSU_MBSTATUS0) Memory x MBIST Status */
-#define DSU_MBSTATUS0_STATUS_Msk    (_U_(0x1FFFFFFF) << DSU_MBSTATUS0_STATUS_Pos)
-#define DSU_MBSTATUS0_STATUS(value) (DSU_MBSTATUS0_STATUS_Msk & ((value) << DSU_MBSTATUS0_STATUS_Pos))
-#define DSU_MBSTATUS0_MASK          _U_(0x1FFFFFFF) /**< \brief (DSU_MBSTATUS0) MASK Register */
-
-/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DCFG:32;          /*!< bit:  0..31  Device Configuration               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_DCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_DCFG_OFFSET             0x00F0       /**< \brief (DSU_DCFG offset) Device Configuration */
-#define DSU_DCFG_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */
-
-#define DSU_DCFG_DCFG_Pos           0            /**< \brief (DSU_DCFG) Device Configuration */
-#define DSU_DCFG_DCFG_Msk           (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos)
-#define DSU_DCFG_DCFG(value)        (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))
-#define DSU_DCFG_MASK               _U_(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */
-
-/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/  32) CoreSight ROM Table Entry 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EPRES:1;          /*!< bit:      0  Entry Present                      */
-    uint32_t FMT:1;            /*!< bit:      1  Format                             */
-    uint32_t :10;              /*!< bit:  2..11  Reserved                           */
-    uint32_t ADDOFF:20;        /*!< bit: 12..31  Address Offset                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_ENTRY0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_ENTRY0_OFFSET           0x1000       /**< \brief (DSU_ENTRY0 offset) CoreSight ROM Table Entry 0 */
-#define DSU_ENTRY0_RESETVALUE       _U_(0x9F0FC002) /**< \brief (DSU_ENTRY0 reset_value) CoreSight ROM Table Entry 0 */
-
-#define DSU_ENTRY0_EPRES_Pos        0            /**< \brief (DSU_ENTRY0) Entry Present */
-#define DSU_ENTRY0_EPRES            (_U_(0x1) << DSU_ENTRY0_EPRES_Pos)
-#define DSU_ENTRY0_FMT_Pos          1            /**< \brief (DSU_ENTRY0) Format */
-#define DSU_ENTRY0_FMT              (_U_(0x1) << DSU_ENTRY0_FMT_Pos)
-#define DSU_ENTRY0_ADDOFF_Pos       12           /**< \brief (DSU_ENTRY0) Address Offset */
-#define DSU_ENTRY0_ADDOFF_Msk       (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)
-#define DSU_ENTRY0_ADDOFF(value)    (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))
-#define DSU_ENTRY0_MASK             _U_(0xFFFFF003) /**< \brief (DSU_ENTRY0) MASK Register */
-
-/* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) (R/  32) CoreSight ROM Table Entry 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_ENTRY1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_ENTRY1_OFFSET           0x1004       /**< \brief (DSU_ENTRY1 offset) CoreSight ROM Table Entry 1 */
-#define DSU_ENTRY1_RESETVALUE       _U_(0x00000000) /**< \brief (DSU_ENTRY1 reset_value) CoreSight ROM Table Entry 1 */
-#define DSU_ENTRY1_MASK             _U_(0xFFFFFFFF) /**< \brief (DSU_ENTRY1) MASK Register */
-
-/* -------- DSU_END : (DSU Offset: 0x1008) (R/  32) CoreSight ROM Table End -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t END:32;           /*!< bit:  0..31  End Marker                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_END_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_END_OFFSET              0x1008       /**< \brief (DSU_END offset) CoreSight ROM Table End */
-#define DSU_END_RESETVALUE          _U_(0x00000000) /**< \brief (DSU_END reset_value) CoreSight ROM Table End */
-
-#define DSU_END_END_Pos             0            /**< \brief (DSU_END) End Marker */
-#define DSU_END_END_Msk             (_U_(0xFFFFFFFF) << DSU_END_END_Pos)
-#define DSU_END_END(value)          (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
-#define DSU_END_MASK                _U_(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */
-
-/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/  32) CoreSight ROM Table Memory Type -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SMEMP:1;          /*!< bit:      0  System Memory Present              */
-    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_MEMTYPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_MEMTYPE_OFFSET          0x1FCC       /**< \brief (DSU_MEMTYPE offset) CoreSight ROM Table Memory Type */
-#define DSU_MEMTYPE_RESETVALUE      _U_(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) CoreSight ROM Table Memory Type */
-
-#define DSU_MEMTYPE_SMEMP_Pos       0            /**< \brief (DSU_MEMTYPE) System Memory Present */
-#define DSU_MEMTYPE_SMEMP           (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos)
-#define DSU_MEMTYPE_MASK            _U_(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */
-
-/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/  32) Peripheral Identification 4 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t JEPCC:4;          /*!< bit:  0.. 3  JEP-106 Continuation Code          */
-    uint32_t FKBC:4;           /*!< bit:  4.. 7  4KB count                          */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID4_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID4_OFFSET             0x1FD0       /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
-#define DSU_PID4_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
-
-#define DSU_PID4_JEPCC_Pos          0            /**< \brief (DSU_PID4) JEP-106 Continuation Code */
-#define DSU_PID4_JEPCC_Msk          (_U_(0xF) << DSU_PID4_JEPCC_Pos)
-#define DSU_PID4_JEPCC(value)       (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
-#define DSU_PID4_FKBC_Pos           4            /**< \brief (DSU_PID4) 4KB count */
-#define DSU_PID4_FKBC_Msk           (_U_(0xF) << DSU_PID4_FKBC_Pos)
-#define DSU_PID4_FKBC(value)        (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
-#define DSU_PID4_MASK               _U_(0x000000FF) /**< \brief (DSU_PID4) MASK Register */
-
-/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/  32) Peripheral Identification 5 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID5_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID5_OFFSET             0x1FD4       /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */
-#define DSU_PID5_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID5 reset_value) Peripheral Identification 5 */
-#define DSU_PID5_MASK               _U_(0x00000000) /**< \brief (DSU_PID5) MASK Register */
-
-/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/  32) Peripheral Identification 6 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID6_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID6_OFFSET             0x1FD8       /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */
-#define DSU_PID6_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID6 reset_value) Peripheral Identification 6 */
-#define DSU_PID6_MASK               _U_(0x00000000) /**< \brief (DSU_PID6) MASK Register */
-
-/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/  32) Peripheral Identification 7 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID7_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID7_OFFSET             0x1FDC       /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */
-#define DSU_PID7_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID7 reset_value) Peripheral Identification 7 */
-#define DSU_PID7_MASK               _U_(0x00000000) /**< \brief (DSU_PID7) MASK Register */
-
-/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/  32) Peripheral Identification 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PARTNBL:8;        /*!< bit:  0.. 7  Part Number Low                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID0_OFFSET             0x1FE0       /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
-#define DSU_PID0_RESETVALUE         _U_(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
-
-#define DSU_PID0_PARTNBL_Pos        0            /**< \brief (DSU_PID0) Part Number Low */
-#define DSU_PID0_PARTNBL_Msk        (_U_(0xFF) << DSU_PID0_PARTNBL_Pos)
-#define DSU_PID0_PARTNBL(value)     (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
-#define DSU_PID0_MASK               _U_(0x000000FF) /**< \brief (DSU_PID0) MASK Register */
-
-/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/  32) Peripheral Identification 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PARTNBH:4;        /*!< bit:  0.. 3  Part Number High                   */
-    uint32_t JEPIDCL:4;        /*!< bit:  4.. 7  Low part of the JEP-106 Identity Code */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID1_OFFSET             0x1FE4       /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
-#define DSU_PID1_RESETVALUE         _U_(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
-
-#define DSU_PID1_PARTNBH_Pos        0            /**< \brief (DSU_PID1) Part Number High */
-#define DSU_PID1_PARTNBH_Msk        (_U_(0xF) << DSU_PID1_PARTNBH_Pos)
-#define DSU_PID1_PARTNBH(value)     (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
-#define DSU_PID1_JEPIDCL_Pos        4            /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
-#define DSU_PID1_JEPIDCL_Msk        (_U_(0xF) << DSU_PID1_JEPIDCL_Pos)
-#define DSU_PID1_JEPIDCL(value)     (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
-#define DSU_PID1_MASK               _U_(0x000000FF) /**< \brief (DSU_PID1) MASK Register */
-
-/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/  32) Peripheral Identification 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t JEPIDCH:3;        /*!< bit:  0.. 2  JEP-106 Identity Code High         */
-    uint32_t JEPU:1;           /*!< bit:      3  JEP-106 Identity Code is used      */
-    uint32_t REVISION:4;       /*!< bit:  4.. 7  Revision Number                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID2_OFFSET             0x1FE8       /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
-#define DSU_PID2_RESETVALUE         _U_(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
-
-#define DSU_PID2_JEPIDCH_Pos        0            /**< \brief (DSU_PID2) JEP-106 Identity Code High */
-#define DSU_PID2_JEPIDCH_Msk        (_U_(0x7) << DSU_PID2_JEPIDCH_Pos)
-#define DSU_PID2_JEPIDCH(value)     (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
-#define DSU_PID2_JEPU_Pos           3            /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
-#define DSU_PID2_JEPU               (_U_(0x1) << DSU_PID2_JEPU_Pos)
-#define DSU_PID2_REVISION_Pos       4            /**< \brief (DSU_PID2) Revision Number */
-#define DSU_PID2_REVISION_Msk       (_U_(0xF) << DSU_PID2_REVISION_Pos)
-#define DSU_PID2_REVISION(value)    (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
-#define DSU_PID2_MASK               _U_(0x000000FF) /**< \brief (DSU_PID2) MASK Register */
-
-/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/  32) Peripheral Identification 3 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CUSMOD:4;         /*!< bit:  0.. 3  ARM CUSMOD                         */
-    uint32_t REVAND:4;         /*!< bit:  4.. 7  Revision Number                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_PID3_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_PID3_OFFSET             0x1FEC       /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
-#define DSU_PID3_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
-
-#define DSU_PID3_CUSMOD_Pos         0            /**< \brief (DSU_PID3) ARM CUSMOD */
-#define DSU_PID3_CUSMOD_Msk         (_U_(0xF) << DSU_PID3_CUSMOD_Pos)
-#define DSU_PID3_CUSMOD(value)      (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
-#define DSU_PID3_REVAND_Pos         4            /**< \brief (DSU_PID3) Revision Number */
-#define DSU_PID3_REVAND_Msk         (_U_(0xF) << DSU_PID3_REVAND_Pos)
-#define DSU_PID3_REVAND(value)      (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
-#define DSU_PID3_MASK               _U_(0x000000FF) /**< \brief (DSU_PID3) MASK Register */
-
-/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/  32) Component Identification 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PREAMBLEB0:8;     /*!< bit:  0.. 7  Preamble Byte 0                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_CID0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CID0_OFFSET             0x1FF0       /**< \brief (DSU_CID0 offset) Component Identification 0 */
-#define DSU_CID0_RESETVALUE         _U_(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
-
-#define DSU_CID0_PREAMBLEB0_Pos     0            /**< \brief (DSU_CID0) Preamble Byte 0 */
-#define DSU_CID0_PREAMBLEB0_Msk     (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos)
-#define DSU_CID0_PREAMBLEB0(value)  (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
-#define DSU_CID0_MASK               _U_(0x000000FF) /**< \brief (DSU_CID0) MASK Register */
-
-/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/  32) Component Identification 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PREAMBLE:4;       /*!< bit:  0.. 3  Preamble                           */
-    uint32_t CCLASS:4;         /*!< bit:  4.. 7  Component Class                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_CID1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CID1_OFFSET             0x1FF4       /**< \brief (DSU_CID1 offset) Component Identification 1 */
-#define DSU_CID1_RESETVALUE         _U_(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
-
-#define DSU_CID1_PREAMBLE_Pos       0            /**< \brief (DSU_CID1) Preamble */
-#define DSU_CID1_PREAMBLE_Msk       (_U_(0xF) << DSU_CID1_PREAMBLE_Pos)
-#define DSU_CID1_PREAMBLE(value)    (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
-#define DSU_CID1_CCLASS_Pos         4            /**< \brief (DSU_CID1) Component Class */
-#define DSU_CID1_CCLASS_Msk         (_U_(0xF) << DSU_CID1_CCLASS_Pos)
-#define DSU_CID1_CCLASS(value)      (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
-#define DSU_CID1_MASK               _U_(0x000000FF) /**< \brief (DSU_CID1) MASK Register */
-
-/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/  32) Component Identification 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PREAMBLEB2:8;     /*!< bit:  0.. 7  Preamble Byte 2                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_CID2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CID2_OFFSET             0x1FF8       /**< \brief (DSU_CID2 offset) Component Identification 2 */
-#define DSU_CID2_RESETVALUE         _U_(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
-
-#define DSU_CID2_PREAMBLEB2_Pos     0            /**< \brief (DSU_CID2) Preamble Byte 2 */
-#define DSU_CID2_PREAMBLEB2_Msk     (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos)
-#define DSU_CID2_PREAMBLEB2(value)  (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
-#define DSU_CID2_MASK               _U_(0x000000FF) /**< \brief (DSU_CID2) MASK Register */
-
-/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/  32) Component Identification 3 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PREAMBLEB3:8;     /*!< bit:  0.. 7  Preamble Byte 3                    */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} DSU_CID3_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define DSU_CID3_OFFSET             0x1FFC       /**< \brief (DSU_CID3 offset) Component Identification 3 */
-#define DSU_CID3_RESETVALUE         _U_(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
-
-#define DSU_CID3_PREAMBLEB3_Pos     0            /**< \brief (DSU_CID3) Preamble Byte 3 */
-#define DSU_CID3_PREAMBLEB3_Msk     (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos)
-#define DSU_CID3_PREAMBLEB3(value)  (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
-#define DSU_CID3_MASK               _U_(0x000000FF) /**< \brief (DSU_CID3) MASK Register */
-
-/** \brief DSU hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __O  DSU_CTRL_Type             CTRL;        /**< \brief Offset: 0x0000 ( /W  8) Control */
-  __IO DSU_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x0001 (R/W  8) Status A */
-  __I  DSU_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x0002 (R/   8) Status B */
-       RoReg8                    Reserved1[0x1];
-  __IO DSU_ADDR_Type             ADDR;        /**< \brief Offset: 0x0004 (R/W 32) Address */
-  __IO DSU_LENGTH_Type           LENGTH;      /**< \brief Offset: 0x0008 (R/W 32) Length */
-  __IO DSU_DATA_Type             DATA;        /**< \brief Offset: 0x000C (R/W 32) Data */
-  __IO DSU_DCC_Type              DCC[2];      /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
-  __I  DSU_DID_Type              DID;         /**< \brief Offset: 0x0018 (R/  32) Device Identification */
-  __IO DSU_CFG_Type              CFG;         /**< \brief Offset: 0x001C (R/W 32) Configuration */
-       RoReg8                    Reserved2[0x20];
-  __IO DSU_MBCTRL_Type           MBCTRL;      /**< \brief Offset: 0x0040 (R/W 32) MBIST Control */
-  __IO DSU_MBCONFIG_Type         MBCONFIG;    /**< \brief Offset: 0x0044 (R/W 32) MBIST Configuration */
-  __IO DSU_MBWORD_Type           MBWORD;      /**< \brief Offset: 0x0048 (R/W 32) MBIST Background Word */
-  __IO DSU_MBGSTAT_Type          MBGSTAT;     /**< \brief Offset: 0x004C (R/W 32) MBIST Global Status */
-  __I  DSU_MBDFAIL_Type          MBDFAIL;     /**< \brief Offset: 0x0050 (R/  32) MBIST Fail Data */
-  __I  DSU_MBDEXP_Type           MBDEXP;      /**< \brief Offset: 0x0054 (R/  32) MBIST Expected Data */
-  __I  DSU_MBAFAIL_Type          MBAFAIL;     /**< \brief Offset: 0x0058 (R/  32) MBIST Fail Address */
-  __I  DSU_MBCONTEXT_Type        MBCONTEXT;   /**< \brief Offset: 0x005C (R/  32) MBIST Fail Context */
-  __IO DSU_MBENABLE0_Type        MBENABLE0;   /**< \brief Offset: 0x0060 (R/W 32) MBIST Memory Enable 0 */
-       RoReg8                    Reserved3[0x4];
-  __I  DSU_MBBUSY0_Type          MBBUSY0;     /**< \brief Offset: 0x0068 (R/  32) MBIST Memory Busy 0 */
-       RoReg8                    Reserved4[0x4];
-  __IO DSU_MBSTATUS0_Type        MBSTATUS0;   /**< \brief Offset: 0x0070 (R/W 32) MBIST Memory Status 0 */
-       RoReg8                    Reserved5[0x7C];
-  __IO DSU_DCFG_Type             DCFG[2];     /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */
-       RoReg8                    Reserved6[0xF08];
-  __I  DSU_ENTRY0_Type           ENTRY0;      /**< \brief Offset: 0x1000 (R/  32) CoreSight ROM Table Entry 0 */
-  __I  DSU_ENTRY1_Type           ENTRY1;      /**< \brief Offset: 0x1004 (R/  32) CoreSight ROM Table Entry 1 */
-  __I  DSU_END_Type              END;         /**< \brief Offset: 0x1008 (R/  32) CoreSight ROM Table End */
-       RoReg8                    Reserved7[0xFC0];
-  __I  DSU_MEMTYPE_Type          MEMTYPE;     /**< \brief Offset: 0x1FCC (R/  32) CoreSight ROM Table Memory Type */
-  __I  DSU_PID4_Type             PID4;        /**< \brief Offset: 0x1FD0 (R/  32) Peripheral Identification 4 */
-  __I  DSU_PID5_Type             PID5;        /**< \brief Offset: 0x1FD4 (R/  32) Peripheral Identification 5 */
-  __I  DSU_PID6_Type             PID6;        /**< \brief Offset: 0x1FD8 (R/  32) Peripheral Identification 6 */
-  __I  DSU_PID7_Type             PID7;        /**< \brief Offset: 0x1FDC (R/  32) Peripheral Identification 7 */
-  __I  DSU_PID0_Type             PID0;        /**< \brief Offset: 0x1FE0 (R/  32) Peripheral Identification 0 */
-  __I  DSU_PID1_Type             PID1;        /**< \brief Offset: 0x1FE4 (R/  32) Peripheral Identification 1 */
-  __I  DSU_PID2_Type             PID2;        /**< \brief Offset: 0x1FE8 (R/  32) Peripheral Identification 2 */
-  __I  DSU_PID3_Type             PID3;        /**< \brief Offset: 0x1FEC (R/  32) Peripheral Identification 3 */
-  __I  DSU_CID0_Type             CID0;        /**< \brief Offset: 0x1FF0 (R/  32) Component Identification 0 */
-  __I  DSU_CID1_Type             CID1;        /**< \brief Offset: 0x1FF4 (R/  32) Component Identification 1 */
-  __I  DSU_CID2_Type             CID2;        /**< \brief Offset: 0x1FF8 (R/  32) Component Identification 2 */
-  __I  DSU_CID3_Type             CID3;        /**< \brief Offset: 0x1FFC (R/  32) Component Identification 3 */
-} Dsu;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_DSU_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/eic.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/eic.h
deleted file mode 100644
index 53d9e1c080..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/eic.h
+++ /dev/null
@@ -1,497 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for EIC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_EIC_COMPONENT_
-#define _SAMD51_EIC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR EIC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_EIC External Interrupt Controller */
-/*@{*/
-
-#define EIC_U2254
-#define REV_EIC                     0x300
-
-/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  CKSEL:1;          /*!< bit:      4  Clock Selection                    */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EIC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_CTRLA_OFFSET            0x00         /**< \brief (EIC_CTRLA offset) Control A */
-#define EIC_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (EIC_CTRLA reset_value) Control A */
-
-#define EIC_CTRLA_SWRST_Pos         0            /**< \brief (EIC_CTRLA) Software Reset */
-#define EIC_CTRLA_SWRST             (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
-#define EIC_CTRLA_ENABLE_Pos        1            /**< \brief (EIC_CTRLA) Enable */
-#define EIC_CTRLA_ENABLE            (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
-#define EIC_CTRLA_CKSEL_Pos         4            /**< \brief (EIC_CTRLA) Clock Selection */
-#define EIC_CTRLA_CKSEL             (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
-#define EIC_CTRLA_MASK              _U_(0x13)    /**< \brief (EIC_CTRLA) MASK Register */
-
-/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W  8) Non-Maskable Interrupt Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  NMISENSE:3;       /*!< bit:  0.. 2  Non-Maskable Interrupt Sense Configuration */
-    uint8_t  NMIFILTEN:1;      /*!< bit:      3  Non-Maskable Interrupt Filter Enable */
-    uint8_t  NMIASYNCH:1;      /*!< bit:      4  Asynchronous Edge Detection Mode   */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EIC_NMICTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_NMICTRL_OFFSET          0x01         /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
-#define EIC_NMICTRL_RESETVALUE      _U_(0x00)    /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
-
-#define EIC_NMICTRL_NMISENSE_Pos    0            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration */
-#define EIC_NMICTRL_NMISENSE_Msk    (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
-#define   EIC_NMICTRL_NMISENSE_NONE_Val   _U_(0x0)   /**< \brief (EIC_NMICTRL) No detection */
-#define   EIC_NMICTRL_NMISENSE_RISE_Val   _U_(0x1)   /**< \brief (EIC_NMICTRL) Rising-edge detection */
-#define   EIC_NMICTRL_NMISENSE_FALL_Val   _U_(0x2)   /**< \brief (EIC_NMICTRL) Falling-edge detection */
-#define   EIC_NMICTRL_NMISENSE_BOTH_Val   _U_(0x3)   /**< \brief (EIC_NMICTRL) Both-edges detection */
-#define   EIC_NMICTRL_NMISENSE_HIGH_Val   _U_(0x4)   /**< \brief (EIC_NMICTRL) High-level detection */
-#define   EIC_NMICTRL_NMISENSE_LOW_Val    _U_(0x5)   /**< \brief (EIC_NMICTRL) Low-level detection */
-#define EIC_NMICTRL_NMISENSE_NONE   (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_RISE   (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_FALL   (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_BOTH   (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_HIGH   (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMISENSE_LOW    (EIC_NMICTRL_NMISENSE_LOW_Val  << EIC_NMICTRL_NMISENSE_Pos)
-#define EIC_NMICTRL_NMIFILTEN_Pos   3            /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
-#define EIC_NMICTRL_NMIFILTEN       (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
-#define EIC_NMICTRL_NMIASYNCH_Pos   4            /**< \brief (EIC_NMICTRL) Asynchronous Edge Detection Mode */
-#define EIC_NMICTRL_NMIASYNCH       (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
-#define EIC_NMICTRL_MASK            _U_(0x1F)    /**< \brief (EIC_NMICTRL) MASK Register */
-
-/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t NMI:1;            /*!< bit:      0  Non-Maskable Interrupt             */
-    uint16_t :15;              /*!< bit:  1..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} EIC_NMIFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_NMIFLAG_OFFSET          0x02         /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
-#define EIC_NMIFLAG_RESETVALUE      _U_(0x0000)  /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
-
-#define EIC_NMIFLAG_NMI_Pos         0            /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
-#define EIC_NMIFLAG_NMI             (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
-#define EIC_NMIFLAG_MASK            _U_(0x0001)  /**< \brief (EIC_NMIFLAG) MASK Register */
-
-/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy Status */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy Status */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_SYNCBUSY_OFFSET         0x04         /**< \brief (EIC_SYNCBUSY offset) Synchronization Busy */
-#define EIC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define EIC_SYNCBUSY_SWRST_Pos      0            /**< \brief (EIC_SYNCBUSY) Software Reset Synchronization Busy Status */
-#define EIC_SYNCBUSY_SWRST          (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
-#define EIC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (EIC_SYNCBUSY) Enable Synchronization Busy Status */
-#define EIC_SYNCBUSY_ENABLE         (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
-#define EIC_SYNCBUSY_MASK           _U_(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */
-
-/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EXTINTEO:16;      /*!< bit:  0..15  External Interrupt Event Output Enable */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_EVCTRL_OFFSET           0x08         /**< \brief (EIC_EVCTRL offset) Event Control */
-#define EIC_EVCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
-
-#define EIC_EVCTRL_EXTINTEO_Pos     0            /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */
-#define EIC_EVCTRL_EXTINTEO_Msk     (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
-#define EIC_EVCTRL_EXTINTEO(value)  (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
-#define EIC_EVCTRL_MASK             _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
-
-/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt Enable          */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_INTENCLR_OFFSET         0x0C         /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
-#define EIC_INTENCLR_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define EIC_INTENCLR_EXTINT_Pos     0            /**< \brief (EIC_INTENCLR) External Interrupt Enable */
-#define EIC_INTENCLR_EXTINT_Msk     (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
-#define EIC_INTENCLR_EXTINT(value)  (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
-#define EIC_INTENCLR_MASK           _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
-
-/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt Enable          */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_INTENSET_OFFSET         0x10         /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
-#define EIC_INTENSET_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
-
-#define EIC_INTENSET_EXTINT_Pos     0            /**< \brief (EIC_INTENSET) External Interrupt Enable */
-#define EIC_INTENSET_EXTINT_Msk     (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
-#define EIC_INTENSET_EXTINT(value)  (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
-#define EIC_INTENSET_MASK           _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
-
-/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt                 */
-    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_INTFLAG_OFFSET          0x14         /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define EIC_INTFLAG_RESETVALUE      _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define EIC_INTFLAG_EXTINT_Pos      0            /**< \brief (EIC_INTFLAG) External Interrupt */
-#define EIC_INTFLAG_EXTINT_Msk      (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
-#define EIC_INTFLAG_EXTINT(value)   (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
-#define EIC_INTFLAG_MASK            _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
-
-/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ASYNCH:16;        /*!< bit:  0..15  Asynchronous Edge Detection Mode   */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_ASYNCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_ASYNCH_OFFSET           0x18         /**< \brief (EIC_ASYNCH offset) External Interrupt Asynchronous Mode */
-#define EIC_ASYNCH_RESETVALUE       _U_(0x00000000) /**< \brief (EIC_ASYNCH reset_value) External Interrupt Asynchronous Mode */
-
-#define EIC_ASYNCH_ASYNCH_Pos       0            /**< \brief (EIC_ASYNCH) Asynchronous Edge Detection Mode */
-#define EIC_ASYNCH_ASYNCH_Msk       (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
-#define EIC_ASYNCH_ASYNCH(value)    (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
-#define EIC_ASYNCH_MASK             _U_(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */
-
-/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SENSE0:3;         /*!< bit:  0.. 2  Input Sense Configuration 0        */
-    uint32_t FILTEN0:1;        /*!< bit:      3  Filter Enable 0                    */
-    uint32_t SENSE1:3;         /*!< bit:  4.. 6  Input Sense Configuration 1        */
-    uint32_t FILTEN1:1;        /*!< bit:      7  Filter Enable 1                    */
-    uint32_t SENSE2:3;         /*!< bit:  8..10  Input Sense Configuration 2        */
-    uint32_t FILTEN2:1;        /*!< bit:     11  Filter Enable 2                    */
-    uint32_t SENSE3:3;         /*!< bit: 12..14  Input Sense Configuration 3        */
-    uint32_t FILTEN3:1;        /*!< bit:     15  Filter Enable 3                    */
-    uint32_t SENSE4:3;         /*!< bit: 16..18  Input Sense Configuration 4        */
-    uint32_t FILTEN4:1;        /*!< bit:     19  Filter Enable 4                    */
-    uint32_t SENSE5:3;         /*!< bit: 20..22  Input Sense Configuration 5        */
-    uint32_t FILTEN5:1;        /*!< bit:     23  Filter Enable 5                    */
-    uint32_t SENSE6:3;         /*!< bit: 24..26  Input Sense Configuration 6        */
-    uint32_t FILTEN6:1;        /*!< bit:     27  Filter Enable 6                    */
-    uint32_t SENSE7:3;         /*!< bit: 28..30  Input Sense Configuration 7        */
-    uint32_t FILTEN7:1;        /*!< bit:     31  Filter Enable 7                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_CONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_CONFIG_OFFSET           0x1C         /**< \brief (EIC_CONFIG offset) External Interrupt Sense Configuration */
-#define EIC_CONFIG_RESETVALUE       _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) External Interrupt Sense Configuration */
-
-#define EIC_CONFIG_SENSE0_Pos       0            /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */
-#define EIC_CONFIG_SENSE0_Msk       (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0(value)    (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
-#define   EIC_CONFIG_SENSE0_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE0_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE0_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE0_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE0_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE0_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE0_NONE      (EIC_CONFIG_SENSE0_NONE_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_RISE      (EIC_CONFIG_SENSE0_RISE_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_FALL      (EIC_CONFIG_SENSE0_FALL_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_BOTH      (EIC_CONFIG_SENSE0_BOTH_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_HIGH      (EIC_CONFIG_SENSE0_HIGH_Val    << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_SENSE0_LOW       (EIC_CONFIG_SENSE0_LOW_Val     << EIC_CONFIG_SENSE0_Pos)
-#define EIC_CONFIG_FILTEN0_Pos      3            /**< \brief (EIC_CONFIG) Filter Enable 0 */
-#define EIC_CONFIG_FILTEN0          (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
-#define EIC_CONFIG_SENSE1_Pos       4            /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */
-#define EIC_CONFIG_SENSE1_Msk       (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1(value)    (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
-#define   EIC_CONFIG_SENSE1_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE1_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE1_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE1_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE1_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE1_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE1_NONE      (EIC_CONFIG_SENSE1_NONE_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_RISE      (EIC_CONFIG_SENSE1_RISE_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_FALL      (EIC_CONFIG_SENSE1_FALL_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_BOTH      (EIC_CONFIG_SENSE1_BOTH_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_HIGH      (EIC_CONFIG_SENSE1_HIGH_Val    << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_SENSE1_LOW       (EIC_CONFIG_SENSE1_LOW_Val     << EIC_CONFIG_SENSE1_Pos)
-#define EIC_CONFIG_FILTEN1_Pos      7            /**< \brief (EIC_CONFIG) Filter Enable 1 */
-#define EIC_CONFIG_FILTEN1          (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
-#define EIC_CONFIG_SENSE2_Pos       8            /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */
-#define EIC_CONFIG_SENSE2_Msk       (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2(value)    (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
-#define   EIC_CONFIG_SENSE2_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE2_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE2_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE2_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE2_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE2_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE2_NONE      (EIC_CONFIG_SENSE2_NONE_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_RISE      (EIC_CONFIG_SENSE2_RISE_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_FALL      (EIC_CONFIG_SENSE2_FALL_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_BOTH      (EIC_CONFIG_SENSE2_BOTH_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_HIGH      (EIC_CONFIG_SENSE2_HIGH_Val    << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_SENSE2_LOW       (EIC_CONFIG_SENSE2_LOW_Val     << EIC_CONFIG_SENSE2_Pos)
-#define EIC_CONFIG_FILTEN2_Pos      11           /**< \brief (EIC_CONFIG) Filter Enable 2 */
-#define EIC_CONFIG_FILTEN2          (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
-#define EIC_CONFIG_SENSE3_Pos       12           /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */
-#define EIC_CONFIG_SENSE3_Msk       (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3(value)    (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
-#define   EIC_CONFIG_SENSE3_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE3_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE3_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE3_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE3_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE3_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE3_NONE      (EIC_CONFIG_SENSE3_NONE_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_RISE      (EIC_CONFIG_SENSE3_RISE_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_FALL      (EIC_CONFIG_SENSE3_FALL_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_BOTH      (EIC_CONFIG_SENSE3_BOTH_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_HIGH      (EIC_CONFIG_SENSE3_HIGH_Val    << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_SENSE3_LOW       (EIC_CONFIG_SENSE3_LOW_Val     << EIC_CONFIG_SENSE3_Pos)
-#define EIC_CONFIG_FILTEN3_Pos      15           /**< \brief (EIC_CONFIG) Filter Enable 3 */
-#define EIC_CONFIG_FILTEN3          (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
-#define EIC_CONFIG_SENSE4_Pos       16           /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */
-#define EIC_CONFIG_SENSE4_Msk       (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4(value)    (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
-#define   EIC_CONFIG_SENSE4_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE4_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE4_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE4_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE4_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE4_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE4_NONE      (EIC_CONFIG_SENSE4_NONE_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_RISE      (EIC_CONFIG_SENSE4_RISE_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_FALL      (EIC_CONFIG_SENSE4_FALL_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_BOTH      (EIC_CONFIG_SENSE4_BOTH_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_HIGH      (EIC_CONFIG_SENSE4_HIGH_Val    << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_SENSE4_LOW       (EIC_CONFIG_SENSE4_LOW_Val     << EIC_CONFIG_SENSE4_Pos)
-#define EIC_CONFIG_FILTEN4_Pos      19           /**< \brief (EIC_CONFIG) Filter Enable 4 */
-#define EIC_CONFIG_FILTEN4          (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
-#define EIC_CONFIG_SENSE5_Pos       20           /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */
-#define EIC_CONFIG_SENSE5_Msk       (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5(value)    (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
-#define   EIC_CONFIG_SENSE5_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE5_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE5_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE5_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE5_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE5_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE5_NONE      (EIC_CONFIG_SENSE5_NONE_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_RISE      (EIC_CONFIG_SENSE5_RISE_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_FALL      (EIC_CONFIG_SENSE5_FALL_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_BOTH      (EIC_CONFIG_SENSE5_BOTH_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_HIGH      (EIC_CONFIG_SENSE5_HIGH_Val    << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_SENSE5_LOW       (EIC_CONFIG_SENSE5_LOW_Val     << EIC_CONFIG_SENSE5_Pos)
-#define EIC_CONFIG_FILTEN5_Pos      23           /**< \brief (EIC_CONFIG) Filter Enable 5 */
-#define EIC_CONFIG_FILTEN5          (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
-#define EIC_CONFIG_SENSE6_Pos       24           /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */
-#define EIC_CONFIG_SENSE6_Msk       (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6(value)    (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
-#define   EIC_CONFIG_SENSE6_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE6_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE6_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE6_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE6_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE6_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE6_NONE      (EIC_CONFIG_SENSE6_NONE_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_RISE      (EIC_CONFIG_SENSE6_RISE_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_FALL      (EIC_CONFIG_SENSE6_FALL_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_BOTH      (EIC_CONFIG_SENSE6_BOTH_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_HIGH      (EIC_CONFIG_SENSE6_HIGH_Val    << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_SENSE6_LOW       (EIC_CONFIG_SENSE6_LOW_Val     << EIC_CONFIG_SENSE6_Pos)
-#define EIC_CONFIG_FILTEN6_Pos      27           /**< \brief (EIC_CONFIG) Filter Enable 6 */
-#define EIC_CONFIG_FILTEN6          (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
-#define EIC_CONFIG_SENSE7_Pos       28           /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */
-#define EIC_CONFIG_SENSE7_Msk       (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7(value)    (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
-#define   EIC_CONFIG_SENSE7_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
-#define   EIC_CONFIG_SENSE7_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
-#define   EIC_CONFIG_SENSE7_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
-#define   EIC_CONFIG_SENSE7_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
-#define   EIC_CONFIG_SENSE7_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
-#define   EIC_CONFIG_SENSE7_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
-#define EIC_CONFIG_SENSE7_NONE      (EIC_CONFIG_SENSE7_NONE_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_RISE      (EIC_CONFIG_SENSE7_RISE_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_FALL      (EIC_CONFIG_SENSE7_FALL_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_BOTH      (EIC_CONFIG_SENSE7_BOTH_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_HIGH      (EIC_CONFIG_SENSE7_HIGH_Val    << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_SENSE7_LOW       (EIC_CONFIG_SENSE7_LOW_Val     << EIC_CONFIG_SENSE7_Pos)
-#define EIC_CONFIG_FILTEN7_Pos      31           /**< \brief (EIC_CONFIG) Filter Enable 7 */
-#define EIC_CONFIG_FILTEN7          (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
-#define EIC_CONFIG_MASK             _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
-
-/* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DEBOUNCEN:16;     /*!< bit:  0..15  Debouncer Enable                   */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_DEBOUNCEN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_DEBOUNCEN_OFFSET        0x30         /**< \brief (EIC_DEBOUNCEN offset) Debouncer Enable */
-#define EIC_DEBOUNCEN_RESETVALUE    _U_(0x00000000) /**< \brief (EIC_DEBOUNCEN reset_value) Debouncer Enable */
-
-#define EIC_DEBOUNCEN_DEBOUNCEN_Pos 0            /**< \brief (EIC_DEBOUNCEN) Debouncer Enable */
-#define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)
-#define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))
-#define EIC_DEBOUNCEN_MASK          _U_(0x0000FFFF) /**< \brief (EIC_DEBOUNCEN) MASK Register */
-
-/* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PRESCALER0:3;     /*!< bit:  0.. 2  Debouncer Prescaler                */
-    uint32_t STATES0:1;        /*!< bit:      3  Debouncer number of states         */
-    uint32_t PRESCALER1:3;     /*!< bit:  4.. 6  Debouncer Prescaler                */
-    uint32_t STATES1:1;        /*!< bit:      7  Debouncer number of states         */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t TICKON:1;         /*!< bit:     16  Pin Sampler frequency selection    */
-    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_DPRESCALER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_DPRESCALER_OFFSET       0x34         /**< \brief (EIC_DPRESCALER offset) Debouncer Prescaler */
-#define EIC_DPRESCALER_RESETVALUE   _U_(0x00000000) /**< \brief (EIC_DPRESCALER reset_value) Debouncer Prescaler */
-
-#define EIC_DPRESCALER_PRESCALER0_Pos 0            /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
-#define EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)
-#define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))
-#define EIC_DPRESCALER_STATES0_Pos  3            /**< \brief (EIC_DPRESCALER) Debouncer number of states */
-#define EIC_DPRESCALER_STATES0      (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos)
-#define EIC_DPRESCALER_PRESCALER1_Pos 4            /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
-#define EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)
-#define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))
-#define EIC_DPRESCALER_STATES1_Pos  7            /**< \brief (EIC_DPRESCALER) Debouncer number of states */
-#define EIC_DPRESCALER_STATES1      (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos)
-#define EIC_DPRESCALER_TICKON_Pos   16           /**< \brief (EIC_DPRESCALER) Pin Sampler frequency selection */
-#define EIC_DPRESCALER_TICKON       (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos)
-#define EIC_DPRESCALER_MASK         _U_(0x000100FF) /**< \brief (EIC_DPRESCALER) MASK Register */
-
-/* -------- EIC_PINSTATE : (EIC Offset: 0x38) (R/  32) Pin State -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PINSTATE:16;      /*!< bit:  0..15  Pin State                          */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EIC_PINSTATE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EIC_PINSTATE_OFFSET         0x38         /**< \brief (EIC_PINSTATE offset) Pin State */
-#define EIC_PINSTATE_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_PINSTATE reset_value) Pin State */
-
-#define EIC_PINSTATE_PINSTATE_Pos   0            /**< \brief (EIC_PINSTATE) Pin State */
-#define EIC_PINSTATE_PINSTATE_Msk   (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)
-#define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))
-#define EIC_PINSTATE_MASK           _U_(0x0000FFFF) /**< \brief (EIC_PINSTATE) MASK Register */
-
-/** \brief EIC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO EIC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
-  __IO EIC_NMICTRL_Type          NMICTRL;     /**< \brief Offset: 0x01 (R/W  8) Non-Maskable Interrupt Control */
-  __IO EIC_NMIFLAG_Type          NMIFLAG;     /**< \brief Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */
-  __I  EIC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x04 (R/  32) Synchronization Busy */
-  __IO EIC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x08 (R/W 32) Event Control */
-  __IO EIC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */
-  __IO EIC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */
-  __IO EIC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
-  __IO EIC_ASYNCH_Type           ASYNCH;      /**< \brief Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */
-  __IO EIC_CONFIG_Type           CONFIG[2];   /**< \brief Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */
-       RoReg8                    Reserved1[0xC];
-  __IO EIC_DEBOUNCEN_Type        DEBOUNCEN;   /**< \brief Offset: 0x30 (R/W 32) Debouncer Enable */
-  __IO EIC_DPRESCALER_Type       DPRESCALER;  /**< \brief Offset: 0x34 (R/W 32) Debouncer Prescaler */
-  __I  EIC_PINSTATE_Type         PINSTATE;    /**< \brief Offset: 0x38 (R/  32) Pin State */
-} Eic;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_EIC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/evsys.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/evsys.h
deleted file mode 100644
index c5fdcf53e3..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/evsys.h
+++ /dev/null
@@ -1,587 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for EVSYS
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_EVSYS_COMPONENT_
-#define _SAMD51_EVSYS_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR EVSYS */
-/* ========================================================================== */
-/** \addtogroup SAMD51_EVSYS Event System Interface */
-/*@{*/
-
-#define EVSYS_U2504
-#define REV_EVSYS                   0x100
-
-/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x000) (R/W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EVSYS_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CTRLA_OFFSET          0x000        /**< \brief (EVSYS_CTRLA offset) Control */
-#define EVSYS_CTRLA_RESETVALUE      _U_(0x00)    /**< \brief (EVSYS_CTRLA reset_value) Control */
-
-#define EVSYS_CTRLA_SWRST_Pos       0            /**< \brief (EVSYS_CTRLA) Software Reset */
-#define EVSYS_CTRLA_SWRST           (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
-#define EVSYS_CTRLA_MASK            _U_(0x01)    /**< \brief (EVSYS_CTRLA) MASK Register */
-
-/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x004) ( /W 32) Software Event -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHANNEL0:1;       /*!< bit:      0  Channel 0 Software Selection       */
-    uint32_t CHANNEL1:1;       /*!< bit:      1  Channel 1 Software Selection       */
-    uint32_t CHANNEL2:1;       /*!< bit:      2  Channel 2 Software Selection       */
-    uint32_t CHANNEL3:1;       /*!< bit:      3  Channel 3 Software Selection       */
-    uint32_t CHANNEL4:1;       /*!< bit:      4  Channel 4 Software Selection       */
-    uint32_t CHANNEL5:1;       /*!< bit:      5  Channel 5 Software Selection       */
-    uint32_t CHANNEL6:1;       /*!< bit:      6  Channel 6 Software Selection       */
-    uint32_t CHANNEL7:1;       /*!< bit:      7  Channel 7 Software Selection       */
-    uint32_t CHANNEL8:1;       /*!< bit:      8  Channel 8 Software Selection       */
-    uint32_t CHANNEL9:1;       /*!< bit:      9  Channel 9 Software Selection       */
-    uint32_t CHANNEL10:1;      /*!< bit:     10  Channel 10 Software Selection      */
-    uint32_t CHANNEL11:1;      /*!< bit:     11  Channel 11 Software Selection      */
-    uint32_t CHANNEL12:1;      /*!< bit:     12  Channel 12 Software Selection      */
-    uint32_t CHANNEL13:1;      /*!< bit:     13  Channel 13 Software Selection      */
-    uint32_t CHANNEL14:1;      /*!< bit:     14  Channel 14 Software Selection      */
-    uint32_t CHANNEL15:1;      /*!< bit:     15  Channel 15 Software Selection      */
-    uint32_t CHANNEL16:1;      /*!< bit:     16  Channel 16 Software Selection      */
-    uint32_t CHANNEL17:1;      /*!< bit:     17  Channel 17 Software Selection      */
-    uint32_t CHANNEL18:1;      /*!< bit:     18  Channel 18 Software Selection      */
-    uint32_t CHANNEL19:1;      /*!< bit:     19  Channel 19 Software Selection      */
-    uint32_t CHANNEL20:1;      /*!< bit:     20  Channel 20 Software Selection      */
-    uint32_t CHANNEL21:1;      /*!< bit:     21  Channel 21 Software Selection      */
-    uint32_t CHANNEL22:1;      /*!< bit:     22  Channel 22 Software Selection      */
-    uint32_t CHANNEL23:1;      /*!< bit:     23  Channel 23 Software Selection      */
-    uint32_t CHANNEL24:1;      /*!< bit:     24  Channel 24 Software Selection      */
-    uint32_t CHANNEL25:1;      /*!< bit:     25  Channel 25 Software Selection      */
-    uint32_t CHANNEL26:1;      /*!< bit:     26  Channel 26 Software Selection      */
-    uint32_t CHANNEL27:1;      /*!< bit:     27  Channel 27 Software Selection      */
-    uint32_t CHANNEL28:1;      /*!< bit:     28  Channel 28 Software Selection      */
-    uint32_t CHANNEL29:1;      /*!< bit:     29  Channel 29 Software Selection      */
-    uint32_t CHANNEL30:1;      /*!< bit:     30  Channel 30 Software Selection      */
-    uint32_t CHANNEL31:1;      /*!< bit:     31  Channel 31 Software Selection      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t CHANNEL:32;       /*!< bit:  0..31  Channel x Software Selection       */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_SWEVT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_SWEVT_OFFSET          0x004        /**< \brief (EVSYS_SWEVT offset) Software Event */
-#define EVSYS_SWEVT_RESETVALUE      _U_(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */
-
-#define EVSYS_SWEVT_CHANNEL0_Pos    0            /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */
-#define EVSYS_SWEVT_CHANNEL0        (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
-#define EVSYS_SWEVT_CHANNEL1_Pos    1            /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */
-#define EVSYS_SWEVT_CHANNEL1        (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
-#define EVSYS_SWEVT_CHANNEL2_Pos    2            /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */
-#define EVSYS_SWEVT_CHANNEL2        (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
-#define EVSYS_SWEVT_CHANNEL3_Pos    3            /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */
-#define EVSYS_SWEVT_CHANNEL3        (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
-#define EVSYS_SWEVT_CHANNEL4_Pos    4            /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */
-#define EVSYS_SWEVT_CHANNEL4        (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
-#define EVSYS_SWEVT_CHANNEL5_Pos    5            /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */
-#define EVSYS_SWEVT_CHANNEL5        (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
-#define EVSYS_SWEVT_CHANNEL6_Pos    6            /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */
-#define EVSYS_SWEVT_CHANNEL6        (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
-#define EVSYS_SWEVT_CHANNEL7_Pos    7            /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */
-#define EVSYS_SWEVT_CHANNEL7        (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
-#define EVSYS_SWEVT_CHANNEL8_Pos    8            /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */
-#define EVSYS_SWEVT_CHANNEL8        (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
-#define EVSYS_SWEVT_CHANNEL9_Pos    9            /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */
-#define EVSYS_SWEVT_CHANNEL9        (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
-#define EVSYS_SWEVT_CHANNEL10_Pos   10           /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */
-#define EVSYS_SWEVT_CHANNEL10       (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
-#define EVSYS_SWEVT_CHANNEL11_Pos   11           /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */
-#define EVSYS_SWEVT_CHANNEL11       (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
-#define EVSYS_SWEVT_CHANNEL12_Pos   12           /**< \brief (EVSYS_SWEVT) Channel 12 Software Selection */
-#define EVSYS_SWEVT_CHANNEL12       (_U_(1) << EVSYS_SWEVT_CHANNEL12_Pos)
-#define EVSYS_SWEVT_CHANNEL13_Pos   13           /**< \brief (EVSYS_SWEVT) Channel 13 Software Selection */
-#define EVSYS_SWEVT_CHANNEL13       (_U_(1) << EVSYS_SWEVT_CHANNEL13_Pos)
-#define EVSYS_SWEVT_CHANNEL14_Pos   14           /**< \brief (EVSYS_SWEVT) Channel 14 Software Selection */
-#define EVSYS_SWEVT_CHANNEL14       (_U_(1) << EVSYS_SWEVT_CHANNEL14_Pos)
-#define EVSYS_SWEVT_CHANNEL15_Pos   15           /**< \brief (EVSYS_SWEVT) Channel 15 Software Selection */
-#define EVSYS_SWEVT_CHANNEL15       (_U_(1) << EVSYS_SWEVT_CHANNEL15_Pos)
-#define EVSYS_SWEVT_CHANNEL16_Pos   16           /**< \brief (EVSYS_SWEVT) Channel 16 Software Selection */
-#define EVSYS_SWEVT_CHANNEL16       (_U_(1) << EVSYS_SWEVT_CHANNEL16_Pos)
-#define EVSYS_SWEVT_CHANNEL17_Pos   17           /**< \brief (EVSYS_SWEVT) Channel 17 Software Selection */
-#define EVSYS_SWEVT_CHANNEL17       (_U_(1) << EVSYS_SWEVT_CHANNEL17_Pos)
-#define EVSYS_SWEVT_CHANNEL18_Pos   18           /**< \brief (EVSYS_SWEVT) Channel 18 Software Selection */
-#define EVSYS_SWEVT_CHANNEL18       (_U_(1) << EVSYS_SWEVT_CHANNEL18_Pos)
-#define EVSYS_SWEVT_CHANNEL19_Pos   19           /**< \brief (EVSYS_SWEVT) Channel 19 Software Selection */
-#define EVSYS_SWEVT_CHANNEL19       (_U_(1) << EVSYS_SWEVT_CHANNEL19_Pos)
-#define EVSYS_SWEVT_CHANNEL20_Pos   20           /**< \brief (EVSYS_SWEVT) Channel 20 Software Selection */
-#define EVSYS_SWEVT_CHANNEL20       (_U_(1) << EVSYS_SWEVT_CHANNEL20_Pos)
-#define EVSYS_SWEVT_CHANNEL21_Pos   21           /**< \brief (EVSYS_SWEVT) Channel 21 Software Selection */
-#define EVSYS_SWEVT_CHANNEL21       (_U_(1) << EVSYS_SWEVT_CHANNEL21_Pos)
-#define EVSYS_SWEVT_CHANNEL22_Pos   22           /**< \brief (EVSYS_SWEVT) Channel 22 Software Selection */
-#define EVSYS_SWEVT_CHANNEL22       (_U_(1) << EVSYS_SWEVT_CHANNEL22_Pos)
-#define EVSYS_SWEVT_CHANNEL23_Pos   23           /**< \brief (EVSYS_SWEVT) Channel 23 Software Selection */
-#define EVSYS_SWEVT_CHANNEL23       (_U_(1) << EVSYS_SWEVT_CHANNEL23_Pos)
-#define EVSYS_SWEVT_CHANNEL24_Pos   24           /**< \brief (EVSYS_SWEVT) Channel 24 Software Selection */
-#define EVSYS_SWEVT_CHANNEL24       (_U_(1) << EVSYS_SWEVT_CHANNEL24_Pos)
-#define EVSYS_SWEVT_CHANNEL25_Pos   25           /**< \brief (EVSYS_SWEVT) Channel 25 Software Selection */
-#define EVSYS_SWEVT_CHANNEL25       (_U_(1) << EVSYS_SWEVT_CHANNEL25_Pos)
-#define EVSYS_SWEVT_CHANNEL26_Pos   26           /**< \brief (EVSYS_SWEVT) Channel 26 Software Selection */
-#define EVSYS_SWEVT_CHANNEL26       (_U_(1) << EVSYS_SWEVT_CHANNEL26_Pos)
-#define EVSYS_SWEVT_CHANNEL27_Pos   27           /**< \brief (EVSYS_SWEVT) Channel 27 Software Selection */
-#define EVSYS_SWEVT_CHANNEL27       (_U_(1) << EVSYS_SWEVT_CHANNEL27_Pos)
-#define EVSYS_SWEVT_CHANNEL28_Pos   28           /**< \brief (EVSYS_SWEVT) Channel 28 Software Selection */
-#define EVSYS_SWEVT_CHANNEL28       (_U_(1) << EVSYS_SWEVT_CHANNEL28_Pos)
-#define EVSYS_SWEVT_CHANNEL29_Pos   29           /**< \brief (EVSYS_SWEVT) Channel 29 Software Selection */
-#define EVSYS_SWEVT_CHANNEL29       (_U_(1) << EVSYS_SWEVT_CHANNEL29_Pos)
-#define EVSYS_SWEVT_CHANNEL30_Pos   30           /**< \brief (EVSYS_SWEVT) Channel 30 Software Selection */
-#define EVSYS_SWEVT_CHANNEL30       (_U_(1) << EVSYS_SWEVT_CHANNEL30_Pos)
-#define EVSYS_SWEVT_CHANNEL31_Pos   31           /**< \brief (EVSYS_SWEVT) Channel 31 Software Selection */
-#define EVSYS_SWEVT_CHANNEL31       (_U_(1) << EVSYS_SWEVT_CHANNEL31_Pos)
-#define EVSYS_SWEVT_CHANNEL_Pos     0            /**< \brief (EVSYS_SWEVT) Channel x Software Selection */
-#define EVSYS_SWEVT_CHANNEL_Msk     (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos)
-#define EVSYS_SWEVT_CHANNEL(value)  (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
-#define EVSYS_SWEVT_MASK            _U_(0xFFFFFFFF) /**< \brief (EVSYS_SWEVT) MASK Register */
-
-/* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x008) (R/W  8) Priority Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PRI:4;            /*!< bit:  0.. 3  Channel Priority Number            */
-    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint8_t  RREN:1;           /*!< bit:      7  Round-Robin Scheduling Enable      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EVSYS_PRICTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_PRICTRL_OFFSET        0x008        /**< \brief (EVSYS_PRICTRL offset) Priority Control */
-#define EVSYS_PRICTRL_RESETVALUE    _U_(0x00)    /**< \brief (EVSYS_PRICTRL reset_value) Priority Control */
-
-#define EVSYS_PRICTRL_PRI_Pos       0            /**< \brief (EVSYS_PRICTRL) Channel Priority Number */
-#define EVSYS_PRICTRL_PRI_Msk       (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos)
-#define EVSYS_PRICTRL_PRI(value)    (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
-#define EVSYS_PRICTRL_RREN_Pos      7            /**< \brief (EVSYS_PRICTRL) Round-Robin Scheduling Enable */
-#define EVSYS_PRICTRL_RREN          (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos)
-#define EVSYS_PRICTRL_MASK          _U_(0x8F)    /**< \brief (EVSYS_PRICTRL) MASK Register */
-
-/* -------- EVSYS_INTPEND : (EVSYS Offset: 0x010) (R/W 16) Channel Pending Interrupt -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t ID:4;             /*!< bit:  0.. 3  Channel ID                         */
-    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint16_t OVR:1;            /*!< bit:      8  Channel Overrun                    */
-    uint16_t EVD:1;            /*!< bit:      9  Channel Event Detected             */
-    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
-    uint16_t READY:1;          /*!< bit:     14  Ready                              */
-    uint16_t BUSY:1;           /*!< bit:     15  Busy                               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} EVSYS_INTPEND_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTPEND_OFFSET        0x010        /**< \brief (EVSYS_INTPEND offset) Channel Pending Interrupt */
-#define EVSYS_INTPEND_RESETVALUE    _U_(0x4000)  /**< \brief (EVSYS_INTPEND reset_value) Channel Pending Interrupt */
-
-#define EVSYS_INTPEND_ID_Pos        0            /**< \brief (EVSYS_INTPEND) Channel ID */
-#define EVSYS_INTPEND_ID_Msk        (_U_(0xF) << EVSYS_INTPEND_ID_Pos)
-#define EVSYS_INTPEND_ID(value)     (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
-#define EVSYS_INTPEND_OVR_Pos       8            /**< \brief (EVSYS_INTPEND) Channel Overrun */
-#define EVSYS_INTPEND_OVR           (_U_(0x1) << EVSYS_INTPEND_OVR_Pos)
-#define EVSYS_INTPEND_EVD_Pos       9            /**< \brief (EVSYS_INTPEND) Channel Event Detected */
-#define EVSYS_INTPEND_EVD           (_U_(0x1) << EVSYS_INTPEND_EVD_Pos)
-#define EVSYS_INTPEND_READY_Pos     14           /**< \brief (EVSYS_INTPEND) Ready */
-#define EVSYS_INTPEND_READY         (_U_(0x1) << EVSYS_INTPEND_READY_Pos)
-#define EVSYS_INTPEND_BUSY_Pos      15           /**< \brief (EVSYS_INTPEND) Busy */
-#define EVSYS_INTPEND_BUSY          (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos)
-#define EVSYS_INTPEND_MASK          _U_(0xC30F)  /**< \brief (EVSYS_INTPEND) MASK Register */
-
-/* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x014) (R/  32) Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHINT0:1;         /*!< bit:      0  Channel 0 Pending Interrupt        */
-    uint32_t CHINT1:1;         /*!< bit:      1  Channel 1 Pending Interrupt        */
-    uint32_t CHINT2:1;         /*!< bit:      2  Channel 2 Pending Interrupt        */
-    uint32_t CHINT3:1;         /*!< bit:      3  Channel 3 Pending Interrupt        */
-    uint32_t CHINT4:1;         /*!< bit:      4  Channel 4 Pending Interrupt        */
-    uint32_t CHINT5:1;         /*!< bit:      5  Channel 5 Pending Interrupt        */
-    uint32_t CHINT6:1;         /*!< bit:      6  Channel 6 Pending Interrupt        */
-    uint32_t CHINT7:1;         /*!< bit:      7  Channel 7 Pending Interrupt        */
-    uint32_t CHINT8:1;         /*!< bit:      8  Channel 8 Pending Interrupt        */
-    uint32_t CHINT9:1;         /*!< bit:      9  Channel 9 Pending Interrupt        */
-    uint32_t CHINT10:1;        /*!< bit:     10  Channel 10 Pending Interrupt       */
-    uint32_t CHINT11:1;        /*!< bit:     11  Channel 11 Pending Interrupt       */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t CHINT:12;         /*!< bit:  0..11  Channel x Pending Interrupt        */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_INTSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_INTSTATUS_OFFSET      0x014        /**< \brief (EVSYS_INTSTATUS offset) Interrupt Status */
-#define EVSYS_INTSTATUS_RESETVALUE  _U_(0x00000000) /**< \brief (EVSYS_INTSTATUS reset_value) Interrupt Status */
-
-#define EVSYS_INTSTATUS_CHINT0_Pos  0            /**< \brief (EVSYS_INTSTATUS) Channel 0 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT0      (_U_(1) << EVSYS_INTSTATUS_CHINT0_Pos)
-#define EVSYS_INTSTATUS_CHINT1_Pos  1            /**< \brief (EVSYS_INTSTATUS) Channel 1 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT1      (_U_(1) << EVSYS_INTSTATUS_CHINT1_Pos)
-#define EVSYS_INTSTATUS_CHINT2_Pos  2            /**< \brief (EVSYS_INTSTATUS) Channel 2 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT2      (_U_(1) << EVSYS_INTSTATUS_CHINT2_Pos)
-#define EVSYS_INTSTATUS_CHINT3_Pos  3            /**< \brief (EVSYS_INTSTATUS) Channel 3 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT3      (_U_(1) << EVSYS_INTSTATUS_CHINT3_Pos)
-#define EVSYS_INTSTATUS_CHINT4_Pos  4            /**< \brief (EVSYS_INTSTATUS) Channel 4 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT4      (_U_(1) << EVSYS_INTSTATUS_CHINT4_Pos)
-#define EVSYS_INTSTATUS_CHINT5_Pos  5            /**< \brief (EVSYS_INTSTATUS) Channel 5 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT5      (_U_(1) << EVSYS_INTSTATUS_CHINT5_Pos)
-#define EVSYS_INTSTATUS_CHINT6_Pos  6            /**< \brief (EVSYS_INTSTATUS) Channel 6 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT6      (_U_(1) << EVSYS_INTSTATUS_CHINT6_Pos)
-#define EVSYS_INTSTATUS_CHINT7_Pos  7            /**< \brief (EVSYS_INTSTATUS) Channel 7 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT7      (_U_(1) << EVSYS_INTSTATUS_CHINT7_Pos)
-#define EVSYS_INTSTATUS_CHINT8_Pos  8            /**< \brief (EVSYS_INTSTATUS) Channel 8 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT8      (_U_(1) << EVSYS_INTSTATUS_CHINT8_Pos)
-#define EVSYS_INTSTATUS_CHINT9_Pos  9            /**< \brief (EVSYS_INTSTATUS) Channel 9 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT9      (_U_(1) << EVSYS_INTSTATUS_CHINT9_Pos)
-#define EVSYS_INTSTATUS_CHINT10_Pos 10           /**< \brief (EVSYS_INTSTATUS) Channel 10 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT10     (_U_(1) << EVSYS_INTSTATUS_CHINT10_Pos)
-#define EVSYS_INTSTATUS_CHINT11_Pos 11           /**< \brief (EVSYS_INTSTATUS) Channel 11 Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT11     (_U_(1) << EVSYS_INTSTATUS_CHINT11_Pos)
-#define EVSYS_INTSTATUS_CHINT_Pos   0            /**< \brief (EVSYS_INTSTATUS) Channel x Pending Interrupt */
-#define EVSYS_INTSTATUS_CHINT_Msk   (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)
-#define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
-#define EVSYS_INTSTATUS_MASK        _U_(0x00000FFF) /**< \brief (EVSYS_INTSTATUS) MASK Register */
-
-/* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x018) (R/  32) Busy Channels -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BUSYCH0:1;        /*!< bit:      0  Busy Channel 0                     */
-    uint32_t BUSYCH1:1;        /*!< bit:      1  Busy Channel 1                     */
-    uint32_t BUSYCH2:1;        /*!< bit:      2  Busy Channel 2                     */
-    uint32_t BUSYCH3:1;        /*!< bit:      3  Busy Channel 3                     */
-    uint32_t BUSYCH4:1;        /*!< bit:      4  Busy Channel 4                     */
-    uint32_t BUSYCH5:1;        /*!< bit:      5  Busy Channel 5                     */
-    uint32_t BUSYCH6:1;        /*!< bit:      6  Busy Channel 6                     */
-    uint32_t BUSYCH7:1;        /*!< bit:      7  Busy Channel 7                     */
-    uint32_t BUSYCH8:1;        /*!< bit:      8  Busy Channel 8                     */
-    uint32_t BUSYCH9:1;        /*!< bit:      9  Busy Channel 9                     */
-    uint32_t BUSYCH10:1;       /*!< bit:     10  Busy Channel 10                    */
-    uint32_t BUSYCH11:1;       /*!< bit:     11  Busy Channel 11                    */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t BUSYCH:12;        /*!< bit:  0..11  Busy Channel x                     */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_BUSYCH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_BUSYCH_OFFSET         0x018        /**< \brief (EVSYS_BUSYCH offset) Busy Channels */
-#define EVSYS_BUSYCH_RESETVALUE     _U_(0x00000000) /**< \brief (EVSYS_BUSYCH reset_value) Busy Channels */
-
-#define EVSYS_BUSYCH_BUSYCH0_Pos    0            /**< \brief (EVSYS_BUSYCH) Busy Channel 0 */
-#define EVSYS_BUSYCH_BUSYCH0        (_U_(1) << EVSYS_BUSYCH_BUSYCH0_Pos)
-#define EVSYS_BUSYCH_BUSYCH1_Pos    1            /**< \brief (EVSYS_BUSYCH) Busy Channel 1 */
-#define EVSYS_BUSYCH_BUSYCH1        (_U_(1) << EVSYS_BUSYCH_BUSYCH1_Pos)
-#define EVSYS_BUSYCH_BUSYCH2_Pos    2            /**< \brief (EVSYS_BUSYCH) Busy Channel 2 */
-#define EVSYS_BUSYCH_BUSYCH2        (_U_(1) << EVSYS_BUSYCH_BUSYCH2_Pos)
-#define EVSYS_BUSYCH_BUSYCH3_Pos    3            /**< \brief (EVSYS_BUSYCH) Busy Channel 3 */
-#define EVSYS_BUSYCH_BUSYCH3        (_U_(1) << EVSYS_BUSYCH_BUSYCH3_Pos)
-#define EVSYS_BUSYCH_BUSYCH4_Pos    4            /**< \brief (EVSYS_BUSYCH) Busy Channel 4 */
-#define EVSYS_BUSYCH_BUSYCH4        (_U_(1) << EVSYS_BUSYCH_BUSYCH4_Pos)
-#define EVSYS_BUSYCH_BUSYCH5_Pos    5            /**< \brief (EVSYS_BUSYCH) Busy Channel 5 */
-#define EVSYS_BUSYCH_BUSYCH5        (_U_(1) << EVSYS_BUSYCH_BUSYCH5_Pos)
-#define EVSYS_BUSYCH_BUSYCH6_Pos    6            /**< \brief (EVSYS_BUSYCH) Busy Channel 6 */
-#define EVSYS_BUSYCH_BUSYCH6        (_U_(1) << EVSYS_BUSYCH_BUSYCH6_Pos)
-#define EVSYS_BUSYCH_BUSYCH7_Pos    7            /**< \brief (EVSYS_BUSYCH) Busy Channel 7 */
-#define EVSYS_BUSYCH_BUSYCH7        (_U_(1) << EVSYS_BUSYCH_BUSYCH7_Pos)
-#define EVSYS_BUSYCH_BUSYCH8_Pos    8            /**< \brief (EVSYS_BUSYCH) Busy Channel 8 */
-#define EVSYS_BUSYCH_BUSYCH8        (_U_(1) << EVSYS_BUSYCH_BUSYCH8_Pos)
-#define EVSYS_BUSYCH_BUSYCH9_Pos    9            /**< \brief (EVSYS_BUSYCH) Busy Channel 9 */
-#define EVSYS_BUSYCH_BUSYCH9        (_U_(1) << EVSYS_BUSYCH_BUSYCH9_Pos)
-#define EVSYS_BUSYCH_BUSYCH10_Pos   10           /**< \brief (EVSYS_BUSYCH) Busy Channel 10 */
-#define EVSYS_BUSYCH_BUSYCH10       (_U_(1) << EVSYS_BUSYCH_BUSYCH10_Pos)
-#define EVSYS_BUSYCH_BUSYCH11_Pos   11           /**< \brief (EVSYS_BUSYCH) Busy Channel 11 */
-#define EVSYS_BUSYCH_BUSYCH11       (_U_(1) << EVSYS_BUSYCH_BUSYCH11_Pos)
-#define EVSYS_BUSYCH_BUSYCH_Pos     0            /**< \brief (EVSYS_BUSYCH) Busy Channel x */
-#define EVSYS_BUSYCH_BUSYCH_Msk     (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)
-#define EVSYS_BUSYCH_BUSYCH(value)  (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
-#define EVSYS_BUSYCH_MASK           _U_(0x00000FFF) /**< \brief (EVSYS_BUSYCH) MASK Register */
-
-/* -------- EVSYS_READYUSR : (EVSYS Offset: 0x01C) (R/  32) Ready Users -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t READYUSR0:1;      /*!< bit:      0  Ready User for Channel 0           */
-    uint32_t READYUSR1:1;      /*!< bit:      1  Ready User for Channel 1           */
-    uint32_t READYUSR2:1;      /*!< bit:      2  Ready User for Channel 2           */
-    uint32_t READYUSR3:1;      /*!< bit:      3  Ready User for Channel 3           */
-    uint32_t READYUSR4:1;      /*!< bit:      4  Ready User for Channel 4           */
-    uint32_t READYUSR5:1;      /*!< bit:      5  Ready User for Channel 5           */
-    uint32_t READYUSR6:1;      /*!< bit:      6  Ready User for Channel 6           */
-    uint32_t READYUSR7:1;      /*!< bit:      7  Ready User for Channel 7           */
-    uint32_t READYUSR8:1;      /*!< bit:      8  Ready User for Channel 8           */
-    uint32_t READYUSR9:1;      /*!< bit:      9  Ready User for Channel 9           */
-    uint32_t READYUSR10:1;     /*!< bit:     10  Ready User for Channel 10          */
-    uint32_t READYUSR11:1;     /*!< bit:     11  Ready User for Channel 11          */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t READYUSR:12;      /*!< bit:  0..11  Ready User for Channel x           */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_READYUSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_READYUSR_OFFSET       0x01C        /**< \brief (EVSYS_READYUSR offset) Ready Users */
-#define EVSYS_READYUSR_RESETVALUE   _U_(0xFFFFFFFF) /**< \brief (EVSYS_READYUSR reset_value) Ready Users */
-
-#define EVSYS_READYUSR_READYUSR0_Pos 0            /**< \brief (EVSYS_READYUSR) Ready User for Channel 0 */
-#define EVSYS_READYUSR_READYUSR0    (_U_(1) << EVSYS_READYUSR_READYUSR0_Pos)
-#define EVSYS_READYUSR_READYUSR1_Pos 1            /**< \brief (EVSYS_READYUSR) Ready User for Channel 1 */
-#define EVSYS_READYUSR_READYUSR1    (_U_(1) << EVSYS_READYUSR_READYUSR1_Pos)
-#define EVSYS_READYUSR_READYUSR2_Pos 2            /**< \brief (EVSYS_READYUSR) Ready User for Channel 2 */
-#define EVSYS_READYUSR_READYUSR2    (_U_(1) << EVSYS_READYUSR_READYUSR2_Pos)
-#define EVSYS_READYUSR_READYUSR3_Pos 3            /**< \brief (EVSYS_READYUSR) Ready User for Channel 3 */
-#define EVSYS_READYUSR_READYUSR3    (_U_(1) << EVSYS_READYUSR_READYUSR3_Pos)
-#define EVSYS_READYUSR_READYUSR4_Pos 4            /**< \brief (EVSYS_READYUSR) Ready User for Channel 4 */
-#define EVSYS_READYUSR_READYUSR4    (_U_(1) << EVSYS_READYUSR_READYUSR4_Pos)
-#define EVSYS_READYUSR_READYUSR5_Pos 5            /**< \brief (EVSYS_READYUSR) Ready User for Channel 5 */
-#define EVSYS_READYUSR_READYUSR5    (_U_(1) << EVSYS_READYUSR_READYUSR5_Pos)
-#define EVSYS_READYUSR_READYUSR6_Pos 6            /**< \brief (EVSYS_READYUSR) Ready User for Channel 6 */
-#define EVSYS_READYUSR_READYUSR6    (_U_(1) << EVSYS_READYUSR_READYUSR6_Pos)
-#define EVSYS_READYUSR_READYUSR7_Pos 7            /**< \brief (EVSYS_READYUSR) Ready User for Channel 7 */
-#define EVSYS_READYUSR_READYUSR7    (_U_(1) << EVSYS_READYUSR_READYUSR7_Pos)
-#define EVSYS_READYUSR_READYUSR8_Pos 8            /**< \brief (EVSYS_READYUSR) Ready User for Channel 8 */
-#define EVSYS_READYUSR_READYUSR8    (_U_(1) << EVSYS_READYUSR_READYUSR8_Pos)
-#define EVSYS_READYUSR_READYUSR9_Pos 9            /**< \brief (EVSYS_READYUSR) Ready User for Channel 9 */
-#define EVSYS_READYUSR_READYUSR9    (_U_(1) << EVSYS_READYUSR_READYUSR9_Pos)
-#define EVSYS_READYUSR_READYUSR10_Pos 10           /**< \brief (EVSYS_READYUSR) Ready User for Channel 10 */
-#define EVSYS_READYUSR_READYUSR10   (_U_(1) << EVSYS_READYUSR_READYUSR10_Pos)
-#define EVSYS_READYUSR_READYUSR11_Pos 11           /**< \brief (EVSYS_READYUSR) Ready User for Channel 11 */
-#define EVSYS_READYUSR_READYUSR11   (_U_(1) << EVSYS_READYUSR_READYUSR11_Pos)
-#define EVSYS_READYUSR_READYUSR_Pos 0            /**< \brief (EVSYS_READYUSR) Ready User for Channel x */
-#define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)
-#define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
-#define EVSYS_READYUSR_MASK         _U_(0x00000FFF) /**< \brief (EVSYS_READYUSR) MASK Register */
-
-/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x020) (R/W 32) CHANNEL Channel n Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EVGEN:7;          /*!< bit:  0.. 6  Event Generator Selection          */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t PATH:2;           /*!< bit:  8.. 9  Path Selection                     */
-    uint32_t EDGSEL:2;         /*!< bit: 10..11  Edge Detection Selection           */
-    uint32_t :2;               /*!< bit: 12..13  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:     14  Run in standby                     */
-    uint32_t ONDEMAND:1;       /*!< bit:     15  Generic Clock On Demand            */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_CHANNEL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHANNEL_OFFSET        0x020        /**< \brief (EVSYS_CHANNEL offset) Channel n Control */
-#define EVSYS_CHANNEL_RESETVALUE    _U_(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n Control */
-
-#define EVSYS_CHANNEL_EVGEN_Pos     0            /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
-#define EVSYS_CHANNEL_EVGEN_Msk     (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
-#define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
-#define EVSYS_CHANNEL_PATH_Pos      8            /**< \brief (EVSYS_CHANNEL) Path Selection */
-#define EVSYS_CHANNEL_PATH_Msk      (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
-#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0)   /**< \brief (EVSYS_CHANNEL) Synchronous path */
-#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1)   /**< \brief (EVSYS_CHANNEL) Resynchronized path */
-#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2)   /**< \brief (EVSYS_CHANNEL) Asynchronous path */
-#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
-#define EVSYS_CHANNEL_EDGSEL_Pos    10           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
-#define EVSYS_CHANNEL_EDGSEL_Msk    (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
-#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0)   /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1)   /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2)   /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
-#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3)   /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
-#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
-#define EVSYS_CHANNEL_RUNSTDBY_Pos  14           /**< \brief (EVSYS_CHANNEL) Run in standby */
-#define EVSYS_CHANNEL_RUNSTDBY      (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
-#define EVSYS_CHANNEL_ONDEMAND_Pos  15           /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */
-#define EVSYS_CHANNEL_ONDEMAND      (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
-#define EVSYS_CHANNEL_MASK          _U_(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */
-
-/* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x024) (R/W  8) CHANNEL Channel n Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  OVR:1;            /*!< bit:      0  Channel Overrun Interrupt Disable  */
-    uint8_t  EVD:1;            /*!< bit:      1  Channel Event Detected Interrupt Disable */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EVSYS_CHINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHINTENCLR_OFFSET     0x024        /**< \brief (EVSYS_CHINTENCLR offset) Channel n Interrupt Enable Clear */
-#define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00)    /**< \brief (EVSYS_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
-
-#define EVSYS_CHINTENCLR_OVR_Pos    0            /**< \brief (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable */
-#define EVSYS_CHINTENCLR_OVR        (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)
-#define EVSYS_CHINTENCLR_EVD_Pos    1            /**< \brief (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable */
-#define EVSYS_CHINTENCLR_EVD        (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)
-#define EVSYS_CHINTENCLR_MASK       _U_(0x03)    /**< \brief (EVSYS_CHINTENCLR) MASK Register */
-
-/* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x025) (R/W  8) CHANNEL Channel n Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  OVR:1;            /*!< bit:      0  Channel Overrun Interrupt Enable   */
-    uint8_t  EVD:1;            /*!< bit:      1  Channel Event Detected Interrupt Enable */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EVSYS_CHINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHINTENSET_OFFSET     0x025        /**< \brief (EVSYS_CHINTENSET offset) Channel n Interrupt Enable Set */
-#define EVSYS_CHINTENSET_RESETVALUE _U_(0x00)    /**< \brief (EVSYS_CHINTENSET reset_value) Channel n Interrupt Enable Set */
-
-#define EVSYS_CHINTENSET_OVR_Pos    0            /**< \brief (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable */
-#define EVSYS_CHINTENSET_OVR        (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos)
-#define EVSYS_CHINTENSET_EVD_Pos    1            /**< \brief (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable */
-#define EVSYS_CHINTENSET_EVD        (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos)
-#define EVSYS_CHINTENSET_MASK       _U_(0x03)    /**< \brief (EVSYS_CHINTENSET) MASK Register */
-
-/* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x026) (R/W  8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  OVR:1;            /*!< bit:      0  Channel Overrun                    */
-    __I uint8_t  EVD:1;            /*!< bit:      1  Channel Event Detected             */
-    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EVSYS_CHINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHINTFLAG_OFFSET      0x026        /**< \brief (EVSYS_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
-#define EVSYS_CHINTFLAG_RESETVALUE  _U_(0x00)    /**< \brief (EVSYS_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
-
-#define EVSYS_CHINTFLAG_OVR_Pos     0            /**< \brief (EVSYS_CHINTFLAG) Channel Overrun */
-#define EVSYS_CHINTFLAG_OVR         (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)
-#define EVSYS_CHINTFLAG_EVD_Pos     1            /**< \brief (EVSYS_CHINTFLAG) Channel Event Detected */
-#define EVSYS_CHINTFLAG_EVD         (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)
-#define EVSYS_CHINTFLAG_MASK        _U_(0x03)    /**< \brief (EVSYS_CHINTFLAG) MASK Register */
-
-/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x027) (R/   8) CHANNEL Channel n Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RDYUSR:1;         /*!< bit:      0  Ready User                         */
-    uint8_t  BUSYCH:1;         /*!< bit:      1  Busy Channel                       */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} EVSYS_CHSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_CHSTATUS_OFFSET       0x027        /**< \brief (EVSYS_CHSTATUS offset) Channel n Status */
-#define EVSYS_CHSTATUS_RESETVALUE   _U_(0x01)    /**< \brief (EVSYS_CHSTATUS reset_value) Channel n Status */
-
-#define EVSYS_CHSTATUS_RDYUSR_Pos   0            /**< \brief (EVSYS_CHSTATUS) Ready User */
-#define EVSYS_CHSTATUS_RDYUSR       (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)
-#define EVSYS_CHSTATUS_BUSYCH_Pos   1            /**< \brief (EVSYS_CHSTATUS) Busy Channel */
-#define EVSYS_CHSTATUS_BUSYCH       (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)
-#define EVSYS_CHSTATUS_MASK         _U_(0x03)    /**< \brief (EVSYS_CHSTATUS) MASK Register */
-
-/* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHANNEL:6;        /*!< bit:  0.. 5  Channel Event Selection            */
-    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} EVSYS_USER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define EVSYS_USER_OFFSET           0x120        /**< \brief (EVSYS_USER offset) User Multiplexer n */
-#define EVSYS_USER_RESETVALUE       _U_(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */
-
-#define EVSYS_USER_CHANNEL_Pos      0            /**< \brief (EVSYS_USER) Channel Event Selection */
-#define EVSYS_USER_CHANNEL_Msk      (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos)
-#define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
-#define EVSYS_USER_MASK             _U_(0x0000003F) /**< \brief (EVSYS_USER) MASK Register */
-
-/** \brief EvsysChannel hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO EVSYS_CHANNEL_Type        CHANNEL;     /**< \brief Offset: 0x000 (R/W 32) Channel n Control */
-  __IO EVSYS_CHINTENCLR_Type     CHINTENCLR;  /**< \brief Offset: 0x004 (R/W  8) Channel n Interrupt Enable Clear */
-  __IO EVSYS_CHINTENSET_Type     CHINTENSET;  /**< \brief Offset: 0x005 (R/W  8) Channel n Interrupt Enable Set */
-  __IO EVSYS_CHINTFLAG_Type      CHINTFLAG;   /**< \brief Offset: 0x006 (R/W  8) Channel n Interrupt Flag Status and Clear */
-  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x007 (R/   8) Channel n Status */
-} EvsysChannel;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief EVSYS hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO EVSYS_CTRLA_Type          CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control */
-       RoReg8                    Reserved1[0x3];
-  __O  EVSYS_SWEVT_Type          SWEVT;       /**< \brief Offset: 0x004 ( /W 32) Software Event */
-  __IO EVSYS_PRICTRL_Type        PRICTRL;     /**< \brief Offset: 0x008 (R/W  8) Priority Control */
-       RoReg8                    Reserved2[0x7];
-  __IO EVSYS_INTPEND_Type        INTPEND;     /**< \brief Offset: 0x010 (R/W 16) Channel Pending Interrupt */
-       RoReg8                    Reserved3[0x2];
-  __I  EVSYS_INTSTATUS_Type      INTSTATUS;   /**< \brief Offset: 0x014 (R/  32) Interrupt Status */
-  __I  EVSYS_BUSYCH_Type         BUSYCH;      /**< \brief Offset: 0x018 (R/  32) Busy Channels */
-  __I  EVSYS_READYUSR_Type       READYUSR;    /**< \brief Offset: 0x01C (R/  32) Ready Users */
-       EvsysChannel              Channel[32]; /**< \brief Offset: 0x020 EvsysChannel groups [CHANNELS] */
-  __IO EVSYS_USER_Type           USER[67];    /**< \brief Offset: 0x120 (R/W 32) User Multiplexer n */
-} Evsys;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_EVSYS_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/freqm.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/freqm.h
deleted file mode 100644
index 3eca2144e0..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/freqm.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for FREQM
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_FREQM_COMPONENT_
-#define _SAMD51_FREQM_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR FREQM */
-/* ========================================================================== */
-/** \addtogroup SAMD51_FREQM Frequency Meter */
-/*@{*/
-
-#define FREQM_U2257
-#define REV_FREQM                   0x110
-
-/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W  8) Control A Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} FREQM_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_CTRLA_OFFSET          0x00         /**< \brief (FREQM_CTRLA offset) Control A Register */
-#define FREQM_CTRLA_RESETVALUE      _U_(0x00)    /**< \brief (FREQM_CTRLA reset_value) Control A Register */
-
-#define FREQM_CTRLA_SWRST_Pos       0            /**< \brief (FREQM_CTRLA) Software Reset */
-#define FREQM_CTRLA_SWRST           (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
-#define FREQM_CTRLA_ENABLE_Pos      1            /**< \brief (FREQM_CTRLA) Enable */
-#define FREQM_CTRLA_ENABLE          (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
-#define FREQM_CTRLA_MASK            _U_(0x03)    /**< \brief (FREQM_CTRLA) MASK Register */
-
-/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W  8) Control B Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  START:1;          /*!< bit:      0  Start Measurement                  */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} FREQM_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_CTRLB_OFFSET          0x01         /**< \brief (FREQM_CTRLB offset) Control B Register */
-#define FREQM_CTRLB_RESETVALUE      _U_(0x00)    /**< \brief (FREQM_CTRLB reset_value) Control B Register */
-
-#define FREQM_CTRLB_START_Pos       0            /**< \brief (FREQM_CTRLB) Start Measurement */
-#define FREQM_CTRLB_START           (_U_(0x1) << FREQM_CTRLB_START_Pos)
-#define FREQM_CTRLB_MASK            _U_(0x01)    /**< \brief (FREQM_CTRLB) MASK Register */
-
-/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t REFNUM:8;         /*!< bit:  0.. 7  Number of Reference Clock Cycles   */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} FREQM_CFGA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_CFGA_OFFSET           0x02         /**< \brief (FREQM_CFGA offset) Config A register */
-#define FREQM_CFGA_RESETVALUE       _U_(0x0000)  /**< \brief (FREQM_CFGA reset_value) Config A register */
-
-#define FREQM_CFGA_REFNUM_Pos       0            /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
-#define FREQM_CFGA_REFNUM_Msk       (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
-#define FREQM_CFGA_REFNUM(value)    (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
-#define FREQM_CFGA_MASK             _U_(0x00FF)  /**< \brief (FREQM_CFGA) MASK Register */
-
-/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W  8) Interrupt Enable Clear Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DONE:1;           /*!< bit:      0  Measurement Done Interrupt Enable  */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} FREQM_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_INTENCLR_OFFSET       0x08         /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
-#define FREQM_INTENCLR_RESETVALUE   _U_(0x00)    /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
-
-#define FREQM_INTENCLR_DONE_Pos     0            /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
-#define FREQM_INTENCLR_DONE         (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
-#define FREQM_INTENCLR_MASK         _U_(0x01)    /**< \brief (FREQM_INTENCLR) MASK Register */
-
-/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W  8) Interrupt Enable Set Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DONE:1;           /*!< bit:      0  Measurement Done Interrupt Enable  */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} FREQM_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_INTENSET_OFFSET       0x09         /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
-#define FREQM_INTENSET_RESETVALUE   _U_(0x00)    /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
-
-#define FREQM_INTENSET_DONE_Pos     0            /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
-#define FREQM_INTENSET_DONE         (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
-#define FREQM_INTENSET_MASK         _U_(0x01)    /**< \brief (FREQM_INTENSET) MASK Register */
-
-/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W  8) Interrupt Flag Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  DONE:1;           /*!< bit:      0  Measurement Done                   */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} FREQM_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_INTFLAG_OFFSET        0x0A         /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
-#define FREQM_INTFLAG_RESETVALUE    _U_(0x00)    /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
-
-#define FREQM_INTFLAG_DONE_Pos      0            /**< \brief (FREQM_INTFLAG) Measurement Done */
-#define FREQM_INTFLAG_DONE          (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
-#define FREQM_INTFLAG_MASK          _U_(0x01)    /**< \brief (FREQM_INTFLAG) MASK Register */
-
-/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W  8) Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  BUSY:1;           /*!< bit:      0  FREQM Status                       */
-    uint8_t  OVF:1;            /*!< bit:      1  Sticky Count Value Overflow        */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} FREQM_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_STATUS_OFFSET         0x0B         /**< \brief (FREQM_STATUS offset) Status Register */
-#define FREQM_STATUS_RESETVALUE     _U_(0x00)    /**< \brief (FREQM_STATUS reset_value) Status Register */
-
-#define FREQM_STATUS_BUSY_Pos       0            /**< \brief (FREQM_STATUS) FREQM Status */
-#define FREQM_STATUS_BUSY           (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
-#define FREQM_STATUS_OVF_Pos        1            /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
-#define FREQM_STATUS_OVF            (_U_(0x1) << FREQM_STATUS_OVF_Pos)
-#define FREQM_STATUS_MASK           _U_(0x03)    /**< \brief (FREQM_STATUS) MASK Register */
-
-/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/  32) Synchronization Busy Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} FREQM_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_SYNCBUSY_OFFSET       0x0C         /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
-#define FREQM_SYNCBUSY_RESETVALUE   _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
-
-#define FREQM_SYNCBUSY_SWRST_Pos    0            /**< \brief (FREQM_SYNCBUSY) Software Reset */
-#define FREQM_SYNCBUSY_SWRST        (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
-#define FREQM_SYNCBUSY_ENABLE_Pos   1            /**< \brief (FREQM_SYNCBUSY) Enable */
-#define FREQM_SYNCBUSY_ENABLE       (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
-#define FREQM_SYNCBUSY_MASK         _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
-
-/* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/  32) Count Value Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t VALUE:24;         /*!< bit:  0..23  Measurement Value                  */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} FREQM_VALUE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define FREQM_VALUE_OFFSET          0x10         /**< \brief (FREQM_VALUE offset) Count Value Register */
-#define FREQM_VALUE_RESETVALUE      _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
-
-#define FREQM_VALUE_VALUE_Pos       0            /**< \brief (FREQM_VALUE) Measurement Value */
-#define FREQM_VALUE_VALUE_Msk       (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
-#define FREQM_VALUE_VALUE(value)    (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
-#define FREQM_VALUE_MASK            _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
-
-/** \brief FREQM hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO FREQM_CTRLA_Type          CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A Register */
-  __O  FREQM_CTRLB_Type          CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B Register */
-  __IO FREQM_CFGA_Type           CFGA;        /**< \brief Offset: 0x02 (R/W 16) Config A register */
-       RoReg8                    Reserved1[0x4];
-  __IO FREQM_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear Register */
-  __IO FREQM_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set Register */
-  __IO FREQM_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Register */
-  __IO FREQM_STATUS_Type         STATUS;      /**< \brief Offset: 0x0B (R/W  8) Status Register */
-  __I  FREQM_SYNCBUSY_Type       SYNCBUSY;    /**< \brief Offset: 0x0C (R/  32) Synchronization Busy Register */
-  __I  FREQM_VALUE_Type          VALUE;       /**< \brief Offset: 0x10 (R/  32) Count Value Register */
-} Freqm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_FREQM_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/gclk.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/gclk.h
deleted file mode 100644
index 6de7d5cdb3..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/gclk.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for GCLK
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_GCLK_COMPONENT_
-#define _SAMD51_GCLK_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR GCLK */
-/* ========================================================================== */
-/** \addtogroup SAMD51_GCLK Generic Clock Generator */
-/*@{*/
-
-#define GCLK_U2122
-#define REV_GCLK                    0x120
-
-/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} GCLK_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_CTRLA_OFFSET           0x00         /**< \brief (GCLK_CTRLA offset) Control */
-#define GCLK_CTRLA_RESETVALUE       _U_(0x00)    /**< \brief (GCLK_CTRLA reset_value) Control */
-
-#define GCLK_CTRLA_SWRST_Pos        0            /**< \brief (GCLK_CTRLA) Software Reset */
-#define GCLK_CTRLA_SWRST            (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
-#define GCLK_CTRLA_MASK             _U_(0x01)    /**< \brief (GCLK_CTRLA) MASK Register */
-
-/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchroniation Busy bit */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t GENCTRL0:1;       /*!< bit:      2  Generic Clock Generator Control 0 Synchronization Busy bits */
-    uint32_t GENCTRL1:1;       /*!< bit:      3  Generic Clock Generator Control 1 Synchronization Busy bits */
-    uint32_t GENCTRL2:1;       /*!< bit:      4  Generic Clock Generator Control 2 Synchronization Busy bits */
-    uint32_t GENCTRL3:1;       /*!< bit:      5  Generic Clock Generator Control 3 Synchronization Busy bits */
-    uint32_t GENCTRL4:1;       /*!< bit:      6  Generic Clock Generator Control 4 Synchronization Busy bits */
-    uint32_t GENCTRL5:1;       /*!< bit:      7  Generic Clock Generator Control 5 Synchronization Busy bits */
-    uint32_t GENCTRL6:1;       /*!< bit:      8  Generic Clock Generator Control 6 Synchronization Busy bits */
-    uint32_t GENCTRL7:1;       /*!< bit:      9  Generic Clock Generator Control 7 Synchronization Busy bits */
-    uint32_t GENCTRL8:1;       /*!< bit:     10  Generic Clock Generator Control 8 Synchronization Busy bits */
-    uint32_t GENCTRL9:1;       /*!< bit:     11  Generic Clock Generator Control 9 Synchronization Busy bits */
-    uint32_t GENCTRL10:1;      /*!< bit:     12  Generic Clock Generator Control 10 Synchronization Busy bits */
-    uint32_t GENCTRL11:1;      /*!< bit:     13  Generic Clock Generator Control 11 Synchronization Busy bits */
-    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint32_t GENCTRL:12;       /*!< bit:  2..13  Generic Clock Generator Control x Synchronization Busy bits */
-    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} GCLK_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_SYNCBUSY_OFFSET        0x04         /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
-#define GCLK_SYNCBUSY_RESETVALUE    _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
-
-#define GCLK_SYNCBUSY_SWRST_Pos     0            /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
-#define GCLK_SYNCBUSY_SWRST         (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
-#define GCLK_SYNCBUSY_GENCTRL0_Pos  2            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL0      (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
-#define GCLK_SYNCBUSY_GENCTRL1_Pos  3            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL1      (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
-#define GCLK_SYNCBUSY_GENCTRL2_Pos  4            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL2      (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
-#define GCLK_SYNCBUSY_GENCTRL3_Pos  5            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL3      (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
-#define GCLK_SYNCBUSY_GENCTRL4_Pos  6            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL4      (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
-#define GCLK_SYNCBUSY_GENCTRL5_Pos  7            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL5      (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
-#define GCLK_SYNCBUSY_GENCTRL6_Pos  8            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL6      (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
-#define GCLK_SYNCBUSY_GENCTRL7_Pos  9            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL7      (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
-#define GCLK_SYNCBUSY_GENCTRL8_Pos  10           /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL8      (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
-#define GCLK_SYNCBUSY_GENCTRL9_Pos  11           /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL9      (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)
-#define GCLK_SYNCBUSY_GENCTRL10_Pos 12           /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL10     (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)
-#define GCLK_SYNCBUSY_GENCTRL11_Pos 13           /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL11     (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_Pos   2            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */
-#define GCLK_SYNCBUSY_GENCTRL_Msk   (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 9 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 10 */
-#define   GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 11 */
-#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
-#define GCLK_SYNCBUSY_MASK          _U_(0x00003FFD) /**< \brief (GCLK_SYNCBUSY) MASK Register */
-
-/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRC:4;            /*!< bit:  0.. 3  Source Select                      */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t GENEN:1;          /*!< bit:      8  Generic Clock Generator Enable     */
-    uint32_t IDC:1;            /*!< bit:      9  Improve Duty Cycle                 */
-    uint32_t OOV:1;            /*!< bit:     10  Output Off Value                   */
-    uint32_t OE:1;             /*!< bit:     11  Output Enable                      */
-    uint32_t DIVSEL:1;         /*!< bit:     12  Divide Selection                   */
-    uint32_t RUNSTDBY:1;       /*!< bit:     13  Run in Standby                     */
-    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
-    uint32_t DIV:16;           /*!< bit: 16..31  Division Factor                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} GCLK_GENCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_GENCTRL_OFFSET         0x20         /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
-#define GCLK_GENCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
-
-#define GCLK_GENCTRL_SRC_Pos        0            /**< \brief (GCLK_GENCTRL) Source Select */
-#define GCLK_GENCTRL_SRC_Msk        (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC(value)     (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
-#define   GCLK_GENCTRL_SRC_XOSC0_Val      _U_(0x0)   /**< \brief (GCLK_GENCTRL) XOSC0 oscillator output */
-#define   GCLK_GENCTRL_SRC_XOSC1_Val      _U_(0x1)   /**< \brief (GCLK_GENCTRL) XOSC1 oscillator output */
-#define   GCLK_GENCTRL_SRC_GCLKIN_Val     _U_(0x2)   /**< \brief (GCLK_GENCTRL) Generator input pad */
-#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   _U_(0x3)   /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
-#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  _U_(0x4)   /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
-#define   GCLK_GENCTRL_SRC_XOSC32K_Val    _U_(0x5)   /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
-#define   GCLK_GENCTRL_SRC_DFLL_Val       _U_(0x6)   /**< \brief (GCLK_GENCTRL) DFLL output */
-#define   GCLK_GENCTRL_SRC_DPLL0_Val      _U_(0x7)   /**< \brief (GCLK_GENCTRL) DPLL0 output */
-#define   GCLK_GENCTRL_SRC_DPLL1_Val      _U_(0x8)   /**< \brief (GCLK_GENCTRL) DPLL1 output */
-#define GCLK_GENCTRL_SRC_XOSC0      (GCLK_GENCTRL_SRC_XOSC0_Val    << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_XOSC1      (GCLK_GENCTRL_SRC_XOSC1_Val    << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_GCLKIN     (GCLK_GENCTRL_SRC_GCLKIN_Val   << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_GCLKGEN1   (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_OSCULP32K  (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_XOSC32K    (GCLK_GENCTRL_SRC_XOSC32K_Val  << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_DFLL       (GCLK_GENCTRL_SRC_DFLL_Val     << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_DPLL0      (GCLK_GENCTRL_SRC_DPLL0_Val    << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_SRC_DPLL1      (GCLK_GENCTRL_SRC_DPLL1_Val    << GCLK_GENCTRL_SRC_Pos)
-#define GCLK_GENCTRL_GENEN_Pos      8            /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
-#define GCLK_GENCTRL_GENEN          (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
-#define GCLK_GENCTRL_IDC_Pos        9            /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
-#define GCLK_GENCTRL_IDC            (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
-#define GCLK_GENCTRL_OOV_Pos        10           /**< \brief (GCLK_GENCTRL) Output Off Value */
-#define GCLK_GENCTRL_OOV            (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
-#define GCLK_GENCTRL_OE_Pos         11           /**< \brief (GCLK_GENCTRL) Output Enable */
-#define GCLK_GENCTRL_OE             (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
-#define GCLK_GENCTRL_DIVSEL_Pos     12           /**< \brief (GCLK_GENCTRL) Divide Selection */
-#define GCLK_GENCTRL_DIVSEL         (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
-#define GCLK_GENCTRL_RUNSTDBY_Pos   13           /**< \brief (GCLK_GENCTRL) Run in Standby */
-#define GCLK_GENCTRL_RUNSTDBY       (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
-#define GCLK_GENCTRL_DIV_Pos        16           /**< \brief (GCLK_GENCTRL) Division Factor */
-#define GCLK_GENCTRL_DIV_Msk        (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
-#define GCLK_GENCTRL_DIV(value)     (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
-#define GCLK_GENCTRL_MASK           _U_(0xFFFF3F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
-
-/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t GEN:4;            /*!< bit:  0.. 3  Generic Clock Generator            */
-    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint32_t CHEN:1;           /*!< bit:      6  Channel Enable                     */
-    uint32_t WRTLOCK:1;        /*!< bit:      7  Write Lock                         */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} GCLK_PCHCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define GCLK_PCHCTRL_OFFSET         0x80         /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
-#define GCLK_PCHCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
-
-#define GCLK_PCHCTRL_GEN_Pos        0            /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
-#define GCLK_PCHCTRL_GEN_Msk        (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN(value)     (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
-#define   GCLK_PCHCTRL_GEN_GCLK0_Val      _U_(0x0)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
-#define   GCLK_PCHCTRL_GEN_GCLK1_Val      _U_(0x1)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
-#define   GCLK_PCHCTRL_GEN_GCLK2_Val      _U_(0x2)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
-#define   GCLK_PCHCTRL_GEN_GCLK3_Val      _U_(0x3)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
-#define   GCLK_PCHCTRL_GEN_GCLK4_Val      _U_(0x4)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
-#define   GCLK_PCHCTRL_GEN_GCLK5_Val      _U_(0x5)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
-#define   GCLK_PCHCTRL_GEN_GCLK6_Val      _U_(0x6)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
-#define   GCLK_PCHCTRL_GEN_GCLK7_Val      _U_(0x7)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
-#define   GCLK_PCHCTRL_GEN_GCLK8_Val      _U_(0x8)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */
-#define   GCLK_PCHCTRL_GEN_GCLK9_Val      _U_(0x9)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 9 */
-#define   GCLK_PCHCTRL_GEN_GCLK10_Val     _U_(0xA)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 10 */
-#define   GCLK_PCHCTRL_GEN_GCLK11_Val     _U_(0xB)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 11 */
-#define GCLK_PCHCTRL_GEN_GCLK0      (GCLK_PCHCTRL_GEN_GCLK0_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK1      (GCLK_PCHCTRL_GEN_GCLK1_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK2      (GCLK_PCHCTRL_GEN_GCLK2_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK3      (GCLK_PCHCTRL_GEN_GCLK3_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK4      (GCLK_PCHCTRL_GEN_GCLK4_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK5      (GCLK_PCHCTRL_GEN_GCLK5_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK6      (GCLK_PCHCTRL_GEN_GCLK6_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK7      (GCLK_PCHCTRL_GEN_GCLK7_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK8      (GCLK_PCHCTRL_GEN_GCLK8_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK9      (GCLK_PCHCTRL_GEN_GCLK9_Val    << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK10     (GCLK_PCHCTRL_GEN_GCLK10_Val   << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_GEN_GCLK11     (GCLK_PCHCTRL_GEN_GCLK11_Val   << GCLK_PCHCTRL_GEN_Pos)
-#define GCLK_PCHCTRL_CHEN_Pos       6            /**< \brief (GCLK_PCHCTRL) Channel Enable */
-#define GCLK_PCHCTRL_CHEN           (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
-#define GCLK_PCHCTRL_WRTLOCK_Pos    7            /**< \brief (GCLK_PCHCTRL) Write Lock */
-#define GCLK_PCHCTRL_WRTLOCK        (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
-#define GCLK_PCHCTRL_MASK           _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */
-
-/** \brief GCLK hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO GCLK_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control */
-       RoReg8                    Reserved1[0x3];
-  __I  GCLK_SYNCBUSY_Type        SYNCBUSY;    /**< \brief Offset: 0x04 (R/  32) Synchronization Busy */
-       RoReg8                    Reserved2[0x18];
-  __IO GCLK_GENCTRL_Type         GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
-       RoReg8                    Reserved3[0x30];
-  __IO GCLK_PCHCTRL_Type         PCHCTRL[48]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
-} Gclk;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_GCLK_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/hmatrixb.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/hmatrixb.h
deleted file mode 100644
index e0526c0d8a..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/hmatrixb.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for HMATRIXB
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_HMATRIXB_COMPONENT_
-#define _SAMD51_HMATRIXB_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR HMATRIXB */
-/* ========================================================================== */
-/** \addtogroup SAMD51_HMATRIXB HSB Matrix */
-/*@{*/
-
-#define HMATRIXB_I7638
-#define REV_HMATRIXB                0x214
-
-/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} HMATRIXB_PRAS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define HMATRIXB_PRAS_OFFSET        0x080        /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
-#define HMATRIXB_PRAS_RESETVALUE    _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
-
-#define HMATRIXB_PRAS_MASK          _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
-
-/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} HMATRIXB_PRBS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define HMATRIXB_PRBS_OFFSET        0x084        /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
-#define HMATRIXB_PRBS_RESETVALUE    _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
-
-#define HMATRIXB_PRBS_MASK          _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
-
-/** \brief HmatrixbPrs hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO HMATRIXB_PRAS_Type        PRAS;        /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
-  __IO HMATRIXB_PRBS_Type        PRBS;        /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
-} HmatrixbPrs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief HMATRIXB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-       RoReg8                    Reserved1[0x80];
-       HmatrixbPrs               Prs[16];     /**< \brief Offset: 0x080 HmatrixbPrs groups */
-} Hmatrixb;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_HMATRIXB_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/i2s.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/i2s.h
deleted file mode 100644
index 5583c69f60..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/i2s.h
+++ /dev/null
@@ -1,747 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for I2S
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_I2S_COMPONENT_
-#define _SAMD51_I2S_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR I2S */
-/* ========================================================================== */
-/** \addtogroup SAMD51_I2S Inter-IC Sound Interface */
-/*@{*/
-
-#define I2S_U2224
-#define REV_I2S                     0x200
-
-/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable                */
-    uint8_t  CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable                */
-    uint8_t  TXEN:1;           /*!< bit:      4  Tx Serializer Enable               */
-    uint8_t  RXEN:1;           /*!< bit:      5  Rx Serializer Enable               */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint8_t  CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable                */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} I2S_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_CTRLA_OFFSET            0x00         /**< \brief (I2S_CTRLA offset) Control A */
-#define I2S_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (I2S_CTRLA reset_value) Control A */
-
-#define I2S_CTRLA_SWRST_Pos         0            /**< \brief (I2S_CTRLA) Software Reset */
-#define I2S_CTRLA_SWRST             (_U_(0x1) << I2S_CTRLA_SWRST_Pos)
-#define I2S_CTRLA_ENABLE_Pos        1            /**< \brief (I2S_CTRLA) Enable */
-#define I2S_CTRLA_ENABLE            (_U_(0x1) << I2S_CTRLA_ENABLE_Pos)
-#define I2S_CTRLA_CKEN0_Pos         2            /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
-#define I2S_CTRLA_CKEN0             (_U_(1) << I2S_CTRLA_CKEN0_Pos)
-#define I2S_CTRLA_CKEN1_Pos         3            /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
-#define I2S_CTRLA_CKEN1             (_U_(1) << I2S_CTRLA_CKEN1_Pos)
-#define I2S_CTRLA_CKEN_Pos          2            /**< \brief (I2S_CTRLA) Clock Unit x Enable */
-#define I2S_CTRLA_CKEN_Msk          (_U_(0x3) << I2S_CTRLA_CKEN_Pos)
-#define I2S_CTRLA_CKEN(value)       (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
-#define I2S_CTRLA_TXEN_Pos          4            /**< \brief (I2S_CTRLA) Tx Serializer Enable */
-#define I2S_CTRLA_TXEN              (_U_(0x1) << I2S_CTRLA_TXEN_Pos)
-#define I2S_CTRLA_RXEN_Pos          5            /**< \brief (I2S_CTRLA) Rx Serializer Enable */
-#define I2S_CTRLA_RXEN              (_U_(0x1) << I2S_CTRLA_RXEN_Pos)
-#define I2S_CTRLA_MASK              _U_(0x3F)    /**< \brief (I2S_CTRLA) MASK Register */
-
-/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SLOTSIZE:2;       /*!< bit:  0.. 1  Slot Size                          */
-    uint32_t NBSLOTS:3;        /*!< bit:  2.. 4  Number of Slots in Frame           */
-    uint32_t FSWIDTH:2;        /*!< bit:  5.. 6  Frame Sync Width                   */
-    uint32_t BITDELAY:1;       /*!< bit:      7  Data Delay from Frame Sync         */
-    uint32_t FSSEL:1;          /*!< bit:      8  Frame Sync Select                  */
-    uint32_t FSINV:1;          /*!< bit:      9  Frame Sync Invert                  */
-    uint32_t FSOUTINV:1;       /*!< bit:     10  Frame Sync Output Invert           */
-    uint32_t SCKSEL:1;         /*!< bit:     11  Serial Clock Select                */
-    uint32_t SCKOUTINV:1;      /*!< bit:     12  Serial Clock Output Invert         */
-    uint32_t MCKSEL:1;         /*!< bit:     13  Master Clock Select                */
-    uint32_t MCKEN:1;          /*!< bit:     14  Master Clock Enable                */
-    uint32_t MCKOUTINV:1;      /*!< bit:     15  Master Clock Output Invert         */
-    uint32_t MCKDIV:6;         /*!< bit: 16..21  Master Clock Division Factor       */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t MCKOUTDIV:6;      /*!< bit: 24..29  Master Clock Output Division Factor */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} I2S_CLKCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_CLKCTRL_OFFSET          0x04         /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
-#define I2S_CLKCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
-
-#define I2S_CLKCTRL_SLOTSIZE_Pos    0            /**< \brief (I2S_CLKCTRL) Slot Size */
-#define I2S_CLKCTRL_SLOTSIZE_Msk    (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
-#define   I2S_CLKCTRL_SLOTSIZE_8_Val      _U_(0x0)   /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
-#define   I2S_CLKCTRL_SLOTSIZE_16_Val     _U_(0x1)   /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
-#define   I2S_CLKCTRL_SLOTSIZE_24_Val     _U_(0x2)   /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
-#define   I2S_CLKCTRL_SLOTSIZE_32_Val     _U_(0x3)   /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
-#define I2S_CLKCTRL_SLOTSIZE_8      (I2S_CLKCTRL_SLOTSIZE_8_Val    << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE_16     (I2S_CLKCTRL_SLOTSIZE_16_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE_24     (I2S_CLKCTRL_SLOTSIZE_24_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_SLOTSIZE_32     (I2S_CLKCTRL_SLOTSIZE_32_Val   << I2S_CLKCTRL_SLOTSIZE_Pos)
-#define I2S_CLKCTRL_NBSLOTS_Pos     2            /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
-#define I2S_CLKCTRL_NBSLOTS_Msk     (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
-#define I2S_CLKCTRL_NBSLOTS(value)  (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
-#define I2S_CLKCTRL_FSWIDTH_Pos     5            /**< \brief (I2S_CLKCTRL) Frame Sync Width */
-#define I2S_CLKCTRL_FSWIDTH_Msk     (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH(value)  (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
-#define   I2S_CLKCTRL_FSWIDTH_SLOT_Val    _U_(0x0)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
-#define   I2S_CLKCTRL_FSWIDTH_HALF_Val    _U_(0x1)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
-#define   I2S_CLKCTRL_FSWIDTH_BIT_Val     _U_(0x2)   /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
-#define   I2S_CLKCTRL_FSWIDTH_BURST_Val   _U_(0x3)   /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
-#define I2S_CLKCTRL_FSWIDTH_SLOT    (I2S_CLKCTRL_FSWIDTH_SLOT_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH_HALF    (I2S_CLKCTRL_FSWIDTH_HALF_Val  << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH_BIT     (I2S_CLKCTRL_FSWIDTH_BIT_Val   << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_FSWIDTH_BURST   (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
-#define I2S_CLKCTRL_BITDELAY_Pos    7            /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
-#define I2S_CLKCTRL_BITDELAY        (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
-#define   I2S_CLKCTRL_BITDELAY_LJ_Val     _U_(0x0)   /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
-#define   I2S_CLKCTRL_BITDELAY_I2S_Val    _U_(0x1)   /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
-#define I2S_CLKCTRL_BITDELAY_LJ     (I2S_CLKCTRL_BITDELAY_LJ_Val   << I2S_CLKCTRL_BITDELAY_Pos)
-#define I2S_CLKCTRL_BITDELAY_I2S    (I2S_CLKCTRL_BITDELAY_I2S_Val  << I2S_CLKCTRL_BITDELAY_Pos)
-#define I2S_CLKCTRL_FSSEL_Pos       8            /**< \brief (I2S_CLKCTRL) Frame Sync Select */
-#define I2S_CLKCTRL_FSSEL           (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos)
-#define   I2S_CLKCTRL_FSSEL_SCKDIV_Val    _U_(0x0)   /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
-#define   I2S_CLKCTRL_FSSEL_FSPIN_Val     _U_(0x1)   /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
-#define I2S_CLKCTRL_FSSEL_SCKDIV    (I2S_CLKCTRL_FSSEL_SCKDIV_Val  << I2S_CLKCTRL_FSSEL_Pos)
-#define I2S_CLKCTRL_FSSEL_FSPIN     (I2S_CLKCTRL_FSSEL_FSPIN_Val   << I2S_CLKCTRL_FSSEL_Pos)
-#define I2S_CLKCTRL_FSINV_Pos       9            /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
-#define I2S_CLKCTRL_FSINV           (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos)
-#define I2S_CLKCTRL_FSOUTINV_Pos    10           /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
-#define I2S_CLKCTRL_FSOUTINV        (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
-#define I2S_CLKCTRL_SCKSEL_Pos      11           /**< \brief (I2S_CLKCTRL) Serial Clock Select */
-#define I2S_CLKCTRL_SCKSEL          (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
-#define   I2S_CLKCTRL_SCKSEL_MCKDIV_Val   _U_(0x0)   /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
-#define   I2S_CLKCTRL_SCKSEL_SCKPIN_Val   _U_(0x1)   /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
-#define I2S_CLKCTRL_SCKSEL_MCKDIV   (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
-#define I2S_CLKCTRL_SCKSEL_SCKPIN   (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
-#define I2S_CLKCTRL_SCKOUTINV_Pos   12           /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
-#define I2S_CLKCTRL_SCKOUTINV       (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
-#define I2S_CLKCTRL_MCKSEL_Pos      13           /**< \brief (I2S_CLKCTRL) Master Clock Select */
-#define I2S_CLKCTRL_MCKSEL          (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
-#define   I2S_CLKCTRL_MCKSEL_GCLK_Val     _U_(0x0)   /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
-#define   I2S_CLKCTRL_MCKSEL_MCKPIN_Val   _U_(0x1)   /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
-#define I2S_CLKCTRL_MCKSEL_GCLK     (I2S_CLKCTRL_MCKSEL_GCLK_Val   << I2S_CLKCTRL_MCKSEL_Pos)
-#define I2S_CLKCTRL_MCKSEL_MCKPIN   (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
-#define I2S_CLKCTRL_MCKEN_Pos       14           /**< \brief (I2S_CLKCTRL) Master Clock Enable */
-#define I2S_CLKCTRL_MCKEN           (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos)
-#define I2S_CLKCTRL_MCKOUTINV_Pos   15           /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
-#define I2S_CLKCTRL_MCKOUTINV       (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
-#define I2S_CLKCTRL_MCKDIV_Pos      16           /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
-#define I2S_CLKCTRL_MCKDIV_Msk      (_U_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos)
-#define I2S_CLKCTRL_MCKDIV(value)   (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
-#define I2S_CLKCTRL_MCKOUTDIV_Pos   24           /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
-#define I2S_CLKCTRL_MCKOUTDIV_Msk   (_U_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
-#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
-#define I2S_CLKCTRL_MASK            _U_(0x3F3FFFFF) /**< \brief (I2S_CLKCTRL) MASK Register */
-
-/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
-    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
-    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
-    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
-    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} I2S_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_INTENCLR_OFFSET         0x0C         /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
-#define I2S_INTENCLR_RESETVALUE     _U_(0x0000)  /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define I2S_INTENCLR_RXRDY0_Pos     0            /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
-#define I2S_INTENCLR_RXRDY0         (_U_(1) << I2S_INTENCLR_RXRDY0_Pos)
-#define I2S_INTENCLR_RXRDY1_Pos     1            /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
-#define I2S_INTENCLR_RXRDY1         (_U_(1) << I2S_INTENCLR_RXRDY1_Pos)
-#define I2S_INTENCLR_RXRDY_Pos      0            /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
-#define I2S_INTENCLR_RXRDY_Msk      (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos)
-#define I2S_INTENCLR_RXRDY(value)   (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
-#define I2S_INTENCLR_RXOR0_Pos      4            /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
-#define I2S_INTENCLR_RXOR0          (_U_(1) << I2S_INTENCLR_RXOR0_Pos)
-#define I2S_INTENCLR_RXOR1_Pos      5            /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
-#define I2S_INTENCLR_RXOR1          (_U_(1) << I2S_INTENCLR_RXOR1_Pos)
-#define I2S_INTENCLR_RXOR_Pos       4            /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
-#define I2S_INTENCLR_RXOR_Msk       (_U_(0x3) << I2S_INTENCLR_RXOR_Pos)
-#define I2S_INTENCLR_RXOR(value)    (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
-#define I2S_INTENCLR_TXRDY0_Pos     8            /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
-#define I2S_INTENCLR_TXRDY0         (_U_(1) << I2S_INTENCLR_TXRDY0_Pos)
-#define I2S_INTENCLR_TXRDY1_Pos     9            /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
-#define I2S_INTENCLR_TXRDY1         (_U_(1) << I2S_INTENCLR_TXRDY1_Pos)
-#define I2S_INTENCLR_TXRDY_Pos      8            /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
-#define I2S_INTENCLR_TXRDY_Msk      (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos)
-#define I2S_INTENCLR_TXRDY(value)   (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
-#define I2S_INTENCLR_TXUR0_Pos      12           /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
-#define I2S_INTENCLR_TXUR0          (_U_(1) << I2S_INTENCLR_TXUR0_Pos)
-#define I2S_INTENCLR_TXUR1_Pos      13           /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
-#define I2S_INTENCLR_TXUR1          (_U_(1) << I2S_INTENCLR_TXUR1_Pos)
-#define I2S_INTENCLR_TXUR_Pos       12           /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
-#define I2S_INTENCLR_TXUR_Msk       (_U_(0x3) << I2S_INTENCLR_TXUR_Pos)
-#define I2S_INTENCLR_TXUR(value)    (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
-#define I2S_INTENCLR_MASK           _U_(0x3333)  /**< \brief (I2S_INTENCLR) MASK Register */
-
-/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0 Interrupt Enable   */
-    uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1 Interrupt Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0 Interrupt Enable */
-    uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1 Interrupt Enable */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0 Interrupt Enable  */
-    uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1 Interrupt Enable  */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0 Interrupt Enable */
-    uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1 Interrupt Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x Interrupt Enable   */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x Interrupt Enable */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x Interrupt Enable  */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x Interrupt Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} I2S_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_INTENSET_OFFSET         0x10         /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
-#define I2S_INTENSET_RESETVALUE     _U_(0x0000)  /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
-
-#define I2S_INTENSET_RXRDY0_Pos     0            /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
-#define I2S_INTENSET_RXRDY0         (_U_(1) << I2S_INTENSET_RXRDY0_Pos)
-#define I2S_INTENSET_RXRDY1_Pos     1            /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
-#define I2S_INTENSET_RXRDY1         (_U_(1) << I2S_INTENSET_RXRDY1_Pos)
-#define I2S_INTENSET_RXRDY_Pos      0            /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
-#define I2S_INTENSET_RXRDY_Msk      (_U_(0x3) << I2S_INTENSET_RXRDY_Pos)
-#define I2S_INTENSET_RXRDY(value)   (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
-#define I2S_INTENSET_RXOR0_Pos      4            /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
-#define I2S_INTENSET_RXOR0          (_U_(1) << I2S_INTENSET_RXOR0_Pos)
-#define I2S_INTENSET_RXOR1_Pos      5            /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
-#define I2S_INTENSET_RXOR1          (_U_(1) << I2S_INTENSET_RXOR1_Pos)
-#define I2S_INTENSET_RXOR_Pos       4            /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
-#define I2S_INTENSET_RXOR_Msk       (_U_(0x3) << I2S_INTENSET_RXOR_Pos)
-#define I2S_INTENSET_RXOR(value)    (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
-#define I2S_INTENSET_TXRDY0_Pos     8            /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
-#define I2S_INTENSET_TXRDY0         (_U_(1) << I2S_INTENSET_TXRDY0_Pos)
-#define I2S_INTENSET_TXRDY1_Pos     9            /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
-#define I2S_INTENSET_TXRDY1         (_U_(1) << I2S_INTENSET_TXRDY1_Pos)
-#define I2S_INTENSET_TXRDY_Pos      8            /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
-#define I2S_INTENSET_TXRDY_Msk      (_U_(0x3) << I2S_INTENSET_TXRDY_Pos)
-#define I2S_INTENSET_TXRDY(value)   (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
-#define I2S_INTENSET_TXUR0_Pos      12           /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
-#define I2S_INTENSET_TXUR0          (_U_(1) << I2S_INTENSET_TXUR0_Pos)
-#define I2S_INTENSET_TXUR1_Pos      13           /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
-#define I2S_INTENSET_TXUR1          (_U_(1) << I2S_INTENSET_TXUR1_Pos)
-#define I2S_INTENSET_TXUR_Pos       12           /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
-#define I2S_INTENSET_TXUR_Msk       (_U_(0x3) << I2S_INTENSET_TXUR_Pos)
-#define I2S_INTENSET_TXUR(value)    (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
-#define I2S_INTENSET_MASK           _U_(0x3333)  /**< \brief (I2S_INTENSET) MASK Register */
-
-/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0                    */
-    __I uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1                    */
-    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    __I uint16_t RXOR0:1;          /*!< bit:      4  Receive Overrun 0                  */
-    __I uint16_t RXOR1:1;          /*!< bit:      5  Receive Overrun 1                  */
-    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    __I uint16_t TXRDY0:1;         /*!< bit:      8  Transmit Ready 0                   */
-    __I uint16_t TXRDY1:1;         /*!< bit:      9  Transmit Ready 1                   */
-    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    __I uint16_t TXUR0:1;          /*!< bit:     12  Transmit Underrun 0                */
-    __I uint16_t TXUR1:1;          /*!< bit:     13  Transmit Underrun 1                */
-    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint16_t RXRDY:2;          /*!< bit:  0.. 1  Receive Ready x                    */
-    __I uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    __I uint16_t RXOR:2;           /*!< bit:  4.. 5  Receive Overrun x                  */
-    __I uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    __I uint16_t TXRDY:2;          /*!< bit:  8.. 9  Transmit Ready x                   */
-    __I uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    __I uint16_t TXUR:2;           /*!< bit: 12..13  Transmit Underrun x                */
-    __I uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} I2S_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_INTFLAG_OFFSET          0x14         /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
-#define I2S_INTFLAG_RESETVALUE      _U_(0x0000)  /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define I2S_INTFLAG_RXRDY0_Pos      0            /**< \brief (I2S_INTFLAG) Receive Ready 0 */
-#define I2S_INTFLAG_RXRDY0          (_U_(1) << I2S_INTFLAG_RXRDY0_Pos)
-#define I2S_INTFLAG_RXRDY1_Pos      1            /**< \brief (I2S_INTFLAG) Receive Ready 1 */
-#define I2S_INTFLAG_RXRDY1          (_U_(1) << I2S_INTFLAG_RXRDY1_Pos)
-#define I2S_INTFLAG_RXRDY_Pos       0            /**< \brief (I2S_INTFLAG) Receive Ready x */
-#define I2S_INTFLAG_RXRDY_Msk       (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos)
-#define I2S_INTFLAG_RXRDY(value)    (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
-#define I2S_INTFLAG_RXOR0_Pos       4            /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
-#define I2S_INTFLAG_RXOR0           (_U_(1) << I2S_INTFLAG_RXOR0_Pos)
-#define I2S_INTFLAG_RXOR1_Pos       5            /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
-#define I2S_INTFLAG_RXOR1           (_U_(1) << I2S_INTFLAG_RXOR1_Pos)
-#define I2S_INTFLAG_RXOR_Pos        4            /**< \brief (I2S_INTFLAG) Receive Overrun x */
-#define I2S_INTFLAG_RXOR_Msk        (_U_(0x3) << I2S_INTFLAG_RXOR_Pos)
-#define I2S_INTFLAG_RXOR(value)     (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
-#define I2S_INTFLAG_TXRDY0_Pos      8            /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
-#define I2S_INTFLAG_TXRDY0          (_U_(1) << I2S_INTFLAG_TXRDY0_Pos)
-#define I2S_INTFLAG_TXRDY1_Pos      9            /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
-#define I2S_INTFLAG_TXRDY1          (_U_(1) << I2S_INTFLAG_TXRDY1_Pos)
-#define I2S_INTFLAG_TXRDY_Pos       8            /**< \brief (I2S_INTFLAG) Transmit Ready x */
-#define I2S_INTFLAG_TXRDY_Msk       (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos)
-#define I2S_INTFLAG_TXRDY(value)    (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
-#define I2S_INTFLAG_TXUR0_Pos       12           /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
-#define I2S_INTFLAG_TXUR0           (_U_(1) << I2S_INTFLAG_TXUR0_Pos)
-#define I2S_INTFLAG_TXUR1_Pos       13           /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
-#define I2S_INTFLAG_TXUR1           (_U_(1) << I2S_INTFLAG_TXUR1_Pos)
-#define I2S_INTFLAG_TXUR_Pos        12           /**< \brief (I2S_INTFLAG) Transmit Underrun x */
-#define I2S_INTFLAG_TXUR_Msk        (_U_(0x3) << I2S_INTFLAG_TXUR_Pos)
-#define I2S_INTFLAG_TXUR(value)     (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
-#define I2S_INTFLAG_MASK            _U_(0x3333)  /**< \brief (I2S_INTFLAG) MASK Register */
-
-/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/  16) Synchronization Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Status */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Status      */
-    uint16_t CKEN0:1;          /*!< bit:      2  Clock Unit 0 Enable Synchronization Status */
-    uint16_t CKEN1:1;          /*!< bit:      3  Clock Unit 1 Enable Synchronization Status */
-    uint16_t TXEN:1;           /*!< bit:      4  Tx Serializer Enable Synchronization Status */
-    uint16_t RXEN:1;           /*!< bit:      5  Rx Serializer Enable Synchronization Status */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t TXDATA:1;         /*!< bit:      8  Tx Data Synchronization Status     */
-    uint16_t RXDATA:1;         /*!< bit:      9  Rx Data Synchronization Status     */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t CKEN:2;           /*!< bit:  2.. 3  Clock Unit x Enable Synchronization Status */
-    uint16_t :12;              /*!< bit:  4..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} I2S_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_SYNCBUSY_OFFSET         0x18         /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
-#define I2S_SYNCBUSY_RESETVALUE     _U_(0x0000)  /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
-
-#define I2S_SYNCBUSY_SWRST_Pos      0            /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
-#define I2S_SYNCBUSY_SWRST          (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos)
-#define I2S_SYNCBUSY_ENABLE_Pos     1            /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
-#define I2S_SYNCBUSY_ENABLE         (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
-#define I2S_SYNCBUSY_CKEN0_Pos      2            /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN0          (_U_(1) << I2S_SYNCBUSY_CKEN0_Pos)
-#define I2S_SYNCBUSY_CKEN1_Pos      3            /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN1          (_U_(1) << I2S_SYNCBUSY_CKEN1_Pos)
-#define I2S_SYNCBUSY_CKEN_Pos       2            /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
-#define I2S_SYNCBUSY_CKEN_Msk       (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos)
-#define I2S_SYNCBUSY_CKEN(value)    (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
-#define I2S_SYNCBUSY_TXEN_Pos       4            /**< \brief (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status */
-#define I2S_SYNCBUSY_TXEN           (_U_(0x1) << I2S_SYNCBUSY_TXEN_Pos)
-#define I2S_SYNCBUSY_RXEN_Pos       5            /**< \brief (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status */
-#define I2S_SYNCBUSY_RXEN           (_U_(0x1) << I2S_SYNCBUSY_RXEN_Pos)
-#define I2S_SYNCBUSY_TXDATA_Pos     8            /**< \brief (I2S_SYNCBUSY) Tx Data Synchronization Status */
-#define I2S_SYNCBUSY_TXDATA         (_U_(0x1) << I2S_SYNCBUSY_TXDATA_Pos)
-#define I2S_SYNCBUSY_RXDATA_Pos     9            /**< \brief (I2S_SYNCBUSY) Rx Data Synchronization Status */
-#define I2S_SYNCBUSY_RXDATA         (_U_(0x1) << I2S_SYNCBUSY_RXDATA_Pos)
-#define I2S_SYNCBUSY_MASK           _U_(0x033F)  /**< \brief (I2S_SYNCBUSY) MASK Register */
-
-/* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint32_t TXDEFAULT:2;      /*!< bit:  2.. 3  Line Default Line when Slot Disabled */
-    uint32_t TXSAME:1;         /*!< bit:      4  Transmit Data when Underrun        */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t SLOTADJ:1;        /*!< bit:      7  Data Slot Formatting Adjust        */
-    uint32_t DATASIZE:3;       /*!< bit:  8..10  Data Word Size                     */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t WORDADJ:1;        /*!< bit:     12  Data Word Formatting Adjust        */
-    uint32_t EXTEND:2;         /*!< bit: 13..14  Data Formatting Bit Extension      */
-    uint32_t BITREV:1;         /*!< bit:     15  Data Formatting Bit Reverse        */
-    uint32_t SLOTDIS0:1;       /*!< bit:     16  Slot 0 Disabled for this Serializer */
-    uint32_t SLOTDIS1:1;       /*!< bit:     17  Slot 1 Disabled for this Serializer */
-    uint32_t SLOTDIS2:1;       /*!< bit:     18  Slot 2 Disabled for this Serializer */
-    uint32_t SLOTDIS3:1;       /*!< bit:     19  Slot 3 Disabled for this Serializer */
-    uint32_t SLOTDIS4:1;       /*!< bit:     20  Slot 4 Disabled for this Serializer */
-    uint32_t SLOTDIS5:1;       /*!< bit:     21  Slot 5 Disabled for this Serializer */
-    uint32_t SLOTDIS6:1;       /*!< bit:     22  Slot 6 Disabled for this Serializer */
-    uint32_t SLOTDIS7:1;       /*!< bit:     23  Slot 7 Disabled for this Serializer */
-    uint32_t MONO:1;           /*!< bit:     24  Mono Mode                          */
-    uint32_t DMA:1;            /*!< bit:     25  Single or Multiple DMA Channels    */
-    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t SLOTDIS:8;        /*!< bit: 16..23  Slot x Disabled for this Serializer */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} I2S_TXCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_TXCTRL_OFFSET           0x20         /**< \brief (I2S_TXCTRL offset) Tx Serializer Control */
-#define I2S_TXCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (I2S_TXCTRL reset_value) Tx Serializer Control */
-
-#define I2S_TXCTRL_TXDEFAULT_Pos    2            /**< \brief (I2S_TXCTRL) Line Default Line when Slot Disabled */
-#define I2S_TXCTRL_TXDEFAULT_Msk    (_U_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos)
-#define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & ((value) << I2S_TXCTRL_TXDEFAULT_Pos))
-#define   I2S_TXCTRL_TXDEFAULT_ZERO_Val   _U_(0x0)   /**< \brief (I2S_TXCTRL) Output Default Value is 0 */
-#define   I2S_TXCTRL_TXDEFAULT_ONE_Val    _U_(0x1)   /**< \brief (I2S_TXCTRL) Output Default Value is 1 */
-#define   I2S_TXCTRL_TXDEFAULT_HIZ_Val    _U_(0x3)   /**< \brief (I2S_TXCTRL) Output Default Value is high impedance */
-#define I2S_TXCTRL_TXDEFAULT_ZERO   (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos)
-#define I2S_TXCTRL_TXDEFAULT_ONE    (I2S_TXCTRL_TXDEFAULT_ONE_Val  << I2S_TXCTRL_TXDEFAULT_Pos)
-#define I2S_TXCTRL_TXDEFAULT_HIZ    (I2S_TXCTRL_TXDEFAULT_HIZ_Val  << I2S_TXCTRL_TXDEFAULT_Pos)
-#define I2S_TXCTRL_TXSAME_Pos       4            /**< \brief (I2S_TXCTRL) Transmit Data when Underrun */
-#define I2S_TXCTRL_TXSAME           (_U_(0x1) << I2S_TXCTRL_TXSAME_Pos)
-#define   I2S_TXCTRL_TXSAME_ZERO_Val      _U_(0x0)   /**< \brief (I2S_TXCTRL) Zero data transmitted in case of underrun */
-#define   I2S_TXCTRL_TXSAME_SAME_Val      _U_(0x1)   /**< \brief (I2S_TXCTRL) Last data transmitted in case of underrun */
-#define I2S_TXCTRL_TXSAME_ZERO      (I2S_TXCTRL_TXSAME_ZERO_Val    << I2S_TXCTRL_TXSAME_Pos)
-#define I2S_TXCTRL_TXSAME_SAME      (I2S_TXCTRL_TXSAME_SAME_Val    << I2S_TXCTRL_TXSAME_Pos)
-#define I2S_TXCTRL_SLOTADJ_Pos      7            /**< \brief (I2S_TXCTRL) Data Slot Formatting Adjust */
-#define I2S_TXCTRL_SLOTADJ          (_U_(0x1) << I2S_TXCTRL_SLOTADJ_Pos)
-#define   I2S_TXCTRL_SLOTADJ_RIGHT_Val    _U_(0x0)   /**< \brief (I2S_TXCTRL) Data is right adjusted in slot */
-#define   I2S_TXCTRL_SLOTADJ_LEFT_Val     _U_(0x1)   /**< \brief (I2S_TXCTRL) Data is left adjusted in slot */
-#define I2S_TXCTRL_SLOTADJ_RIGHT    (I2S_TXCTRL_SLOTADJ_RIGHT_Val  << I2S_TXCTRL_SLOTADJ_Pos)
-#define I2S_TXCTRL_SLOTADJ_LEFT     (I2S_TXCTRL_SLOTADJ_LEFT_Val   << I2S_TXCTRL_SLOTADJ_Pos)
-#define I2S_TXCTRL_DATASIZE_Pos     8            /**< \brief (I2S_TXCTRL) Data Word Size */
-#define I2S_TXCTRL_DATASIZE_Msk     (_U_(0x7) << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE(value)  (I2S_TXCTRL_DATASIZE_Msk & ((value) << I2S_TXCTRL_DATASIZE_Pos))
-#define   I2S_TXCTRL_DATASIZE_32_Val      _U_(0x0)   /**< \brief (I2S_TXCTRL) 32 bits */
-#define   I2S_TXCTRL_DATASIZE_24_Val      _U_(0x1)   /**< \brief (I2S_TXCTRL) 24 bits */
-#define   I2S_TXCTRL_DATASIZE_20_Val      _U_(0x2)   /**< \brief (I2S_TXCTRL) 20 bits */
-#define   I2S_TXCTRL_DATASIZE_18_Val      _U_(0x3)   /**< \brief (I2S_TXCTRL) 18 bits */
-#define   I2S_TXCTRL_DATASIZE_16_Val      _U_(0x4)   /**< \brief (I2S_TXCTRL) 16 bits */
-#define   I2S_TXCTRL_DATASIZE_16C_Val     _U_(0x5)   /**< \brief (I2S_TXCTRL) 16 bits compact stereo */
-#define   I2S_TXCTRL_DATASIZE_8_Val       _U_(0x6)   /**< \brief (I2S_TXCTRL) 8 bits */
-#define   I2S_TXCTRL_DATASIZE_8C_Val      _U_(0x7)   /**< \brief (I2S_TXCTRL) 8 bits compact stereo */
-#define I2S_TXCTRL_DATASIZE_32      (I2S_TXCTRL_DATASIZE_32_Val    << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_24      (I2S_TXCTRL_DATASIZE_24_Val    << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_20      (I2S_TXCTRL_DATASIZE_20_Val    << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_18      (I2S_TXCTRL_DATASIZE_18_Val    << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_16      (I2S_TXCTRL_DATASIZE_16_Val    << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_16C     (I2S_TXCTRL_DATASIZE_16C_Val   << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_8       (I2S_TXCTRL_DATASIZE_8_Val     << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_DATASIZE_8C      (I2S_TXCTRL_DATASIZE_8C_Val    << I2S_TXCTRL_DATASIZE_Pos)
-#define I2S_TXCTRL_WORDADJ_Pos      12           /**< \brief (I2S_TXCTRL) Data Word Formatting Adjust */
-#define I2S_TXCTRL_WORDADJ          (_U_(0x1) << I2S_TXCTRL_WORDADJ_Pos)
-#define   I2S_TXCTRL_WORDADJ_RIGHT_Val    _U_(0x0)   /**< \brief (I2S_TXCTRL) Data is right adjusted in word */
-#define   I2S_TXCTRL_WORDADJ_LEFT_Val     _U_(0x1)   /**< \brief (I2S_TXCTRL) Data is left adjusted in word */
-#define I2S_TXCTRL_WORDADJ_RIGHT    (I2S_TXCTRL_WORDADJ_RIGHT_Val  << I2S_TXCTRL_WORDADJ_Pos)
-#define I2S_TXCTRL_WORDADJ_LEFT     (I2S_TXCTRL_WORDADJ_LEFT_Val   << I2S_TXCTRL_WORDADJ_Pos)
-#define I2S_TXCTRL_EXTEND_Pos       13           /**< \brief (I2S_TXCTRL) Data Formatting Bit Extension */
-#define I2S_TXCTRL_EXTEND_Msk       (_U_(0x3) << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_EXTEND(value)    (I2S_TXCTRL_EXTEND_Msk & ((value) << I2S_TXCTRL_EXTEND_Pos))
-#define   I2S_TXCTRL_EXTEND_ZERO_Val      _U_(0x0)   /**< \brief (I2S_TXCTRL) Extend with zeroes */
-#define   I2S_TXCTRL_EXTEND_ONE_Val       _U_(0x1)   /**< \brief (I2S_TXCTRL) Extend with ones */
-#define   I2S_TXCTRL_EXTEND_MSBIT_Val     _U_(0x2)   /**< \brief (I2S_TXCTRL) Extend with Most Significant Bit */
-#define   I2S_TXCTRL_EXTEND_LSBIT_Val     _U_(0x3)   /**< \brief (I2S_TXCTRL) Extend with Least Significant Bit */
-#define I2S_TXCTRL_EXTEND_ZERO      (I2S_TXCTRL_EXTEND_ZERO_Val    << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_EXTEND_ONE       (I2S_TXCTRL_EXTEND_ONE_Val     << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_EXTEND_MSBIT     (I2S_TXCTRL_EXTEND_MSBIT_Val   << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_EXTEND_LSBIT     (I2S_TXCTRL_EXTEND_LSBIT_Val   << I2S_TXCTRL_EXTEND_Pos)
-#define I2S_TXCTRL_BITREV_Pos       15           /**< \brief (I2S_TXCTRL) Data Formatting Bit Reverse */
-#define I2S_TXCTRL_BITREV           (_U_(0x1) << I2S_TXCTRL_BITREV_Pos)
-#define   I2S_TXCTRL_BITREV_MSBIT_Val     _U_(0x0)   /**< \brief (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
-#define   I2S_TXCTRL_BITREV_LSBIT_Val     _U_(0x1)   /**< \brief (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first */
-#define I2S_TXCTRL_BITREV_MSBIT     (I2S_TXCTRL_BITREV_MSBIT_Val   << I2S_TXCTRL_BITREV_Pos)
-#define I2S_TXCTRL_BITREV_LSBIT     (I2S_TXCTRL_BITREV_LSBIT_Val   << I2S_TXCTRL_BITREV_Pos)
-#define I2S_TXCTRL_SLOTDIS0_Pos     16           /**< \brief (I2S_TXCTRL) Slot 0 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS0         (_U_(1) << I2S_TXCTRL_SLOTDIS0_Pos)
-#define I2S_TXCTRL_SLOTDIS1_Pos     17           /**< \brief (I2S_TXCTRL) Slot 1 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS1         (_U_(1) << I2S_TXCTRL_SLOTDIS1_Pos)
-#define I2S_TXCTRL_SLOTDIS2_Pos     18           /**< \brief (I2S_TXCTRL) Slot 2 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS2         (_U_(1) << I2S_TXCTRL_SLOTDIS2_Pos)
-#define I2S_TXCTRL_SLOTDIS3_Pos     19           /**< \brief (I2S_TXCTRL) Slot 3 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS3         (_U_(1) << I2S_TXCTRL_SLOTDIS3_Pos)
-#define I2S_TXCTRL_SLOTDIS4_Pos     20           /**< \brief (I2S_TXCTRL) Slot 4 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS4         (_U_(1) << I2S_TXCTRL_SLOTDIS4_Pos)
-#define I2S_TXCTRL_SLOTDIS5_Pos     21           /**< \brief (I2S_TXCTRL) Slot 5 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS5         (_U_(1) << I2S_TXCTRL_SLOTDIS5_Pos)
-#define I2S_TXCTRL_SLOTDIS6_Pos     22           /**< \brief (I2S_TXCTRL) Slot 6 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS6         (_U_(1) << I2S_TXCTRL_SLOTDIS6_Pos)
-#define I2S_TXCTRL_SLOTDIS7_Pos     23           /**< \brief (I2S_TXCTRL) Slot 7 Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS7         (_U_(1) << I2S_TXCTRL_SLOTDIS7_Pos)
-#define I2S_TXCTRL_SLOTDIS_Pos      16           /**< \brief (I2S_TXCTRL) Slot x Disabled for this Serializer */
-#define I2S_TXCTRL_SLOTDIS_Msk      (_U_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos)
-#define I2S_TXCTRL_SLOTDIS(value)   (I2S_TXCTRL_SLOTDIS_Msk & ((value) << I2S_TXCTRL_SLOTDIS_Pos))
-#define I2S_TXCTRL_MONO_Pos         24           /**< \brief (I2S_TXCTRL) Mono Mode */
-#define I2S_TXCTRL_MONO             (_U_(0x1) << I2S_TXCTRL_MONO_Pos)
-#define   I2S_TXCTRL_MONO_STEREO_Val      _U_(0x0)   /**< \brief (I2S_TXCTRL) Normal mode */
-#define   I2S_TXCTRL_MONO_MONO_Val        _U_(0x1)   /**< \brief (I2S_TXCTRL) Left channel data is duplicated to right channel */
-#define I2S_TXCTRL_MONO_STEREO      (I2S_TXCTRL_MONO_STEREO_Val    << I2S_TXCTRL_MONO_Pos)
-#define I2S_TXCTRL_MONO_MONO        (I2S_TXCTRL_MONO_MONO_Val      << I2S_TXCTRL_MONO_Pos)
-#define I2S_TXCTRL_DMA_Pos          25           /**< \brief (I2S_TXCTRL) Single or Multiple DMA Channels */
-#define I2S_TXCTRL_DMA              (_U_(0x1) << I2S_TXCTRL_DMA_Pos)
-#define   I2S_TXCTRL_DMA_SINGLE_Val       _U_(0x0)   /**< \brief (I2S_TXCTRL) Single DMA channel */
-#define   I2S_TXCTRL_DMA_MULTIPLE_Val     _U_(0x1)   /**< \brief (I2S_TXCTRL) One DMA channel per data channel */
-#define I2S_TXCTRL_DMA_SINGLE       (I2S_TXCTRL_DMA_SINGLE_Val     << I2S_TXCTRL_DMA_Pos)
-#define I2S_TXCTRL_DMA_MULTIPLE     (I2S_TXCTRL_DMA_MULTIPLE_Val   << I2S_TXCTRL_DMA_Pos)
-#define I2S_TXCTRL_MASK             _U_(0x03FFF79C) /**< \brief (I2S_TXCTRL) MASK Register */
-
-/* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SERMODE:2;        /*!< bit:  0.. 1  Serializer Mode                    */
-    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
-    uint32_t CLKSEL:1;         /*!< bit:      5  Clock Unit Selection               */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t SLOTADJ:1;        /*!< bit:      7  Data Slot Formatting Adjust        */
-    uint32_t DATASIZE:3;       /*!< bit:  8..10  Data Word Size                     */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t WORDADJ:1;        /*!< bit:     12  Data Word Formatting Adjust        */
-    uint32_t EXTEND:2;         /*!< bit: 13..14  Data Formatting Bit Extension      */
-    uint32_t BITREV:1;         /*!< bit:     15  Data Formatting Bit Reverse        */
-    uint32_t SLOTDIS0:1;       /*!< bit:     16  Slot 0 Disabled for this Serializer */
-    uint32_t SLOTDIS1:1;       /*!< bit:     17  Slot 1 Disabled for this Serializer */
-    uint32_t SLOTDIS2:1;       /*!< bit:     18  Slot 2 Disabled for this Serializer */
-    uint32_t SLOTDIS3:1;       /*!< bit:     19  Slot 3 Disabled for this Serializer */
-    uint32_t SLOTDIS4:1;       /*!< bit:     20  Slot 4 Disabled for this Serializer */
-    uint32_t SLOTDIS5:1;       /*!< bit:     21  Slot 5 Disabled for this Serializer */
-    uint32_t SLOTDIS6:1;       /*!< bit:     22  Slot 6 Disabled for this Serializer */
-    uint32_t SLOTDIS7:1;       /*!< bit:     23  Slot 7 Disabled for this Serializer */
-    uint32_t MONO:1;           /*!< bit:     24  Mono Mode                          */
-    uint32_t DMA:1;            /*!< bit:     25  Single or Multiple DMA Channels    */
-    uint32_t RXLOOP:1;         /*!< bit:     26  Loop-back Test Mode                */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t SLOTDIS:8;        /*!< bit: 16..23  Slot x Disabled for this Serializer */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} I2S_RXCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_RXCTRL_OFFSET           0x24         /**< \brief (I2S_RXCTRL offset) Rx Serializer Control */
-#define I2S_RXCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (I2S_RXCTRL reset_value) Rx Serializer Control */
-
-#define I2S_RXCTRL_SERMODE_Pos      0            /**< \brief (I2S_RXCTRL) Serializer Mode */
-#define I2S_RXCTRL_SERMODE_Msk      (_U_(0x3) << I2S_RXCTRL_SERMODE_Pos)
-#define I2S_RXCTRL_SERMODE(value)   (I2S_RXCTRL_SERMODE_Msk & ((value) << I2S_RXCTRL_SERMODE_Pos))
-#define   I2S_RXCTRL_SERMODE_RX_Val       _U_(0x0)   /**< \brief (I2S_RXCTRL) Receive */
-#define   I2S_RXCTRL_SERMODE_PDM2_Val     _U_(0x2)   /**< \brief (I2S_RXCTRL) Receive one PDM data on each serial clock edge */
-#define I2S_RXCTRL_SERMODE_RX       (I2S_RXCTRL_SERMODE_RX_Val     << I2S_RXCTRL_SERMODE_Pos)
-#define I2S_RXCTRL_SERMODE_PDM2     (I2S_RXCTRL_SERMODE_PDM2_Val   << I2S_RXCTRL_SERMODE_Pos)
-#define I2S_RXCTRL_CLKSEL_Pos       5            /**< \brief (I2S_RXCTRL) Clock Unit Selection */
-#define I2S_RXCTRL_CLKSEL           (_U_(0x1) << I2S_RXCTRL_CLKSEL_Pos)
-#define   I2S_RXCTRL_CLKSEL_CLK0_Val      _U_(0x0)   /**< \brief (I2S_RXCTRL) Use Clock Unit 0 */
-#define   I2S_RXCTRL_CLKSEL_CLK1_Val      _U_(0x1)   /**< \brief (I2S_RXCTRL) Use Clock Unit 1 */
-#define I2S_RXCTRL_CLKSEL_CLK0      (I2S_RXCTRL_CLKSEL_CLK0_Val    << I2S_RXCTRL_CLKSEL_Pos)
-#define I2S_RXCTRL_CLKSEL_CLK1      (I2S_RXCTRL_CLKSEL_CLK1_Val    << I2S_RXCTRL_CLKSEL_Pos)
-#define I2S_RXCTRL_SLOTADJ_Pos      7            /**< \brief (I2S_RXCTRL) Data Slot Formatting Adjust */
-#define I2S_RXCTRL_SLOTADJ          (_U_(0x1) << I2S_RXCTRL_SLOTADJ_Pos)
-#define   I2S_RXCTRL_SLOTADJ_RIGHT_Val    _U_(0x0)   /**< \brief (I2S_RXCTRL) Data is right adjusted in slot */
-#define   I2S_RXCTRL_SLOTADJ_LEFT_Val     _U_(0x1)   /**< \brief (I2S_RXCTRL) Data is left adjusted in slot */
-#define I2S_RXCTRL_SLOTADJ_RIGHT    (I2S_RXCTRL_SLOTADJ_RIGHT_Val  << I2S_RXCTRL_SLOTADJ_Pos)
-#define I2S_RXCTRL_SLOTADJ_LEFT     (I2S_RXCTRL_SLOTADJ_LEFT_Val   << I2S_RXCTRL_SLOTADJ_Pos)
-#define I2S_RXCTRL_DATASIZE_Pos     8            /**< \brief (I2S_RXCTRL) Data Word Size */
-#define I2S_RXCTRL_DATASIZE_Msk     (_U_(0x7) << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE(value)  (I2S_RXCTRL_DATASIZE_Msk & ((value) << I2S_RXCTRL_DATASIZE_Pos))
-#define   I2S_RXCTRL_DATASIZE_32_Val      _U_(0x0)   /**< \brief (I2S_RXCTRL) 32 bits */
-#define   I2S_RXCTRL_DATASIZE_24_Val      _U_(0x1)   /**< \brief (I2S_RXCTRL) 24 bits */
-#define   I2S_RXCTRL_DATASIZE_20_Val      _U_(0x2)   /**< \brief (I2S_RXCTRL) 20 bits */
-#define   I2S_RXCTRL_DATASIZE_18_Val      _U_(0x3)   /**< \brief (I2S_RXCTRL) 18 bits */
-#define   I2S_RXCTRL_DATASIZE_16_Val      _U_(0x4)   /**< \brief (I2S_RXCTRL) 16 bits */
-#define   I2S_RXCTRL_DATASIZE_16C_Val     _U_(0x5)   /**< \brief (I2S_RXCTRL) 16 bits compact stereo */
-#define   I2S_RXCTRL_DATASIZE_8_Val       _U_(0x6)   /**< \brief (I2S_RXCTRL) 8 bits */
-#define   I2S_RXCTRL_DATASIZE_8C_Val      _U_(0x7)   /**< \brief (I2S_RXCTRL) 8 bits compact stereo */
-#define I2S_RXCTRL_DATASIZE_32      (I2S_RXCTRL_DATASIZE_32_Val    << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_24      (I2S_RXCTRL_DATASIZE_24_Val    << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_20      (I2S_RXCTRL_DATASIZE_20_Val    << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_18      (I2S_RXCTRL_DATASIZE_18_Val    << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_16      (I2S_RXCTRL_DATASIZE_16_Val    << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_16C     (I2S_RXCTRL_DATASIZE_16C_Val   << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_8       (I2S_RXCTRL_DATASIZE_8_Val     << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_DATASIZE_8C      (I2S_RXCTRL_DATASIZE_8C_Val    << I2S_RXCTRL_DATASIZE_Pos)
-#define I2S_RXCTRL_WORDADJ_Pos      12           /**< \brief (I2S_RXCTRL) Data Word Formatting Adjust */
-#define I2S_RXCTRL_WORDADJ          (_U_(0x1) << I2S_RXCTRL_WORDADJ_Pos)
-#define   I2S_RXCTRL_WORDADJ_RIGHT_Val    _U_(0x0)   /**< \brief (I2S_RXCTRL) Data is right adjusted in word */
-#define   I2S_RXCTRL_WORDADJ_LEFT_Val     _U_(0x1)   /**< \brief (I2S_RXCTRL) Data is left adjusted in word */
-#define I2S_RXCTRL_WORDADJ_RIGHT    (I2S_RXCTRL_WORDADJ_RIGHT_Val  << I2S_RXCTRL_WORDADJ_Pos)
-#define I2S_RXCTRL_WORDADJ_LEFT     (I2S_RXCTRL_WORDADJ_LEFT_Val   << I2S_RXCTRL_WORDADJ_Pos)
-#define I2S_RXCTRL_EXTEND_Pos       13           /**< \brief (I2S_RXCTRL) Data Formatting Bit Extension */
-#define I2S_RXCTRL_EXTEND_Msk       (_U_(0x3) << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_EXTEND(value)    (I2S_RXCTRL_EXTEND_Msk & ((value) << I2S_RXCTRL_EXTEND_Pos))
-#define   I2S_RXCTRL_EXTEND_ZERO_Val      _U_(0x0)   /**< \brief (I2S_RXCTRL) Extend with zeroes */
-#define   I2S_RXCTRL_EXTEND_ONE_Val       _U_(0x1)   /**< \brief (I2S_RXCTRL) Extend with ones */
-#define   I2S_RXCTRL_EXTEND_MSBIT_Val     _U_(0x2)   /**< \brief (I2S_RXCTRL) Extend with Most Significant Bit */
-#define   I2S_RXCTRL_EXTEND_LSBIT_Val     _U_(0x3)   /**< \brief (I2S_RXCTRL) Extend with Least Significant Bit */
-#define I2S_RXCTRL_EXTEND_ZERO      (I2S_RXCTRL_EXTEND_ZERO_Val    << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_EXTEND_ONE       (I2S_RXCTRL_EXTEND_ONE_Val     << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_EXTEND_MSBIT     (I2S_RXCTRL_EXTEND_MSBIT_Val   << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_EXTEND_LSBIT     (I2S_RXCTRL_EXTEND_LSBIT_Val   << I2S_RXCTRL_EXTEND_Pos)
-#define I2S_RXCTRL_BITREV_Pos       15           /**< \brief (I2S_RXCTRL) Data Formatting Bit Reverse */
-#define I2S_RXCTRL_BITREV           (_U_(0x1) << I2S_RXCTRL_BITREV_Pos)
-#define   I2S_RXCTRL_BITREV_MSBIT_Val     _U_(0x0)   /**< \brief (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
-#define   I2S_RXCTRL_BITREV_LSBIT_Val     _U_(0x1)   /**< \brief (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first */
-#define I2S_RXCTRL_BITREV_MSBIT     (I2S_RXCTRL_BITREV_MSBIT_Val   << I2S_RXCTRL_BITREV_Pos)
-#define I2S_RXCTRL_BITREV_LSBIT     (I2S_RXCTRL_BITREV_LSBIT_Val   << I2S_RXCTRL_BITREV_Pos)
-#define I2S_RXCTRL_SLOTDIS0_Pos     16           /**< \brief (I2S_RXCTRL) Slot 0 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS0         (_U_(1) << I2S_RXCTRL_SLOTDIS0_Pos)
-#define I2S_RXCTRL_SLOTDIS1_Pos     17           /**< \brief (I2S_RXCTRL) Slot 1 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS1         (_U_(1) << I2S_RXCTRL_SLOTDIS1_Pos)
-#define I2S_RXCTRL_SLOTDIS2_Pos     18           /**< \brief (I2S_RXCTRL) Slot 2 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS2         (_U_(1) << I2S_RXCTRL_SLOTDIS2_Pos)
-#define I2S_RXCTRL_SLOTDIS3_Pos     19           /**< \brief (I2S_RXCTRL) Slot 3 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS3         (_U_(1) << I2S_RXCTRL_SLOTDIS3_Pos)
-#define I2S_RXCTRL_SLOTDIS4_Pos     20           /**< \brief (I2S_RXCTRL) Slot 4 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS4         (_U_(1) << I2S_RXCTRL_SLOTDIS4_Pos)
-#define I2S_RXCTRL_SLOTDIS5_Pos     21           /**< \brief (I2S_RXCTRL) Slot 5 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS5         (_U_(1) << I2S_RXCTRL_SLOTDIS5_Pos)
-#define I2S_RXCTRL_SLOTDIS6_Pos     22           /**< \brief (I2S_RXCTRL) Slot 6 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS6         (_U_(1) << I2S_RXCTRL_SLOTDIS6_Pos)
-#define I2S_RXCTRL_SLOTDIS7_Pos     23           /**< \brief (I2S_RXCTRL) Slot 7 Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS7         (_U_(1) << I2S_RXCTRL_SLOTDIS7_Pos)
-#define I2S_RXCTRL_SLOTDIS_Pos      16           /**< \brief (I2S_RXCTRL) Slot x Disabled for this Serializer */
-#define I2S_RXCTRL_SLOTDIS_Msk      (_U_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos)
-#define I2S_RXCTRL_SLOTDIS(value)   (I2S_RXCTRL_SLOTDIS_Msk & ((value) << I2S_RXCTRL_SLOTDIS_Pos))
-#define I2S_RXCTRL_MONO_Pos         24           /**< \brief (I2S_RXCTRL) Mono Mode */
-#define I2S_RXCTRL_MONO             (_U_(0x1) << I2S_RXCTRL_MONO_Pos)
-#define   I2S_RXCTRL_MONO_STEREO_Val      _U_(0x0)   /**< \brief (I2S_RXCTRL) Normal mode */
-#define   I2S_RXCTRL_MONO_MONO_Val        _U_(0x1)   /**< \brief (I2S_RXCTRL) Left channel data is duplicated to right channel */
-#define I2S_RXCTRL_MONO_STEREO      (I2S_RXCTRL_MONO_STEREO_Val    << I2S_RXCTRL_MONO_Pos)
-#define I2S_RXCTRL_MONO_MONO        (I2S_RXCTRL_MONO_MONO_Val      << I2S_RXCTRL_MONO_Pos)
-#define I2S_RXCTRL_DMA_Pos          25           /**< \brief (I2S_RXCTRL) Single or Multiple DMA Channels */
-#define I2S_RXCTRL_DMA              (_U_(0x1) << I2S_RXCTRL_DMA_Pos)
-#define   I2S_RXCTRL_DMA_SINGLE_Val       _U_(0x0)   /**< \brief (I2S_RXCTRL) Single DMA channel */
-#define   I2S_RXCTRL_DMA_MULTIPLE_Val     _U_(0x1)   /**< \brief (I2S_RXCTRL) One DMA channel per data channel */
-#define I2S_RXCTRL_DMA_SINGLE       (I2S_RXCTRL_DMA_SINGLE_Val     << I2S_RXCTRL_DMA_Pos)
-#define I2S_RXCTRL_DMA_MULTIPLE     (I2S_RXCTRL_DMA_MULTIPLE_Val   << I2S_RXCTRL_DMA_Pos)
-#define I2S_RXCTRL_RXLOOP_Pos       26           /**< \brief (I2S_RXCTRL) Loop-back Test Mode */
-#define I2S_RXCTRL_RXLOOP           (_U_(0x1) << I2S_RXCTRL_RXLOOP_Pos)
-#define I2S_RXCTRL_MASK             _U_(0x07FFF7A3) /**< \brief (I2S_RXCTRL) MASK Register */
-
-/* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Sample Data                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} I2S_TXDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_TXDATA_OFFSET           0x30         /**< \brief (I2S_TXDATA offset) Tx Data */
-#define I2S_TXDATA_RESETVALUE       _U_(0x00000000) /**< \brief (I2S_TXDATA reset_value) Tx Data */
-
-#define I2S_TXDATA_DATA_Pos         0            /**< \brief (I2S_TXDATA) Sample Data */
-#define I2S_TXDATA_DATA_Msk         (_U_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos)
-#define I2S_TXDATA_DATA(value)      (I2S_TXDATA_DATA_Msk & ((value) << I2S_TXDATA_DATA_Pos))
-#define I2S_TXDATA_MASK             _U_(0xFFFFFFFF) /**< \brief (I2S_TXDATA) MASK Register */
-
-/* -------- I2S_RXDATA : (I2S Offset: 0x34) (R/  32) Rx Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Sample Data                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} I2S_RXDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define I2S_RXDATA_OFFSET           0x34         /**< \brief (I2S_RXDATA offset) Rx Data */
-#define I2S_RXDATA_RESETVALUE       _U_(0x00000000) /**< \brief (I2S_RXDATA reset_value) Rx Data */
-
-#define I2S_RXDATA_DATA_Pos         0            /**< \brief (I2S_RXDATA) Sample Data */
-#define I2S_RXDATA_DATA_Msk         (_U_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos)
-#define I2S_RXDATA_DATA(value)      (I2S_RXDATA_DATA_Msk & ((value) << I2S_RXDATA_DATA_Pos))
-#define I2S_RXDATA_MASK             _U_(0xFFFFFFFF) /**< \brief (I2S_RXDATA) MASK Register */
-
-/** \brief I2S hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO I2S_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
-       RoReg8                    Reserved1[0x3];
-  __IO I2S_CLKCTRL_Type          CLKCTRL[2];  /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
-  __IO I2S_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
-       RoReg8                    Reserved2[0x2];
-  __IO I2S_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
-       RoReg8                    Reserved3[0x2];
-  __IO I2S_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x2];
-  __I  I2S_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x18 (R/  16) Synchronization Status */
-       RoReg8                    Reserved5[0x6];
-  __IO I2S_TXCTRL_Type           TXCTRL;      /**< \brief Offset: 0x20 (R/W 32) Tx Serializer Control */
-  __IO I2S_RXCTRL_Type           RXCTRL;      /**< \brief Offset: 0x24 (R/W 32) Rx Serializer Control */
-       RoReg8                    Reserved6[0x8];
-  __O  I2S_TXDATA_Type           TXDATA;      /**< \brief Offset: 0x30 ( /W 32) Tx Data */
-  __I  I2S_RXDATA_Type           RXDATA;      /**< \brief Offset: 0x34 (R/  32) Rx Data */
-} I2s;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_I2S_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/icm.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/icm.h
deleted file mode 100644
index eb4b28e6ff..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/icm.h
+++ /dev/null
@@ -1,582 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for ICM
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_ICM_COMPONENT_
-#define _SAMD51_ICM_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR ICM */
-/* ========================================================================== */
-/** \addtogroup SAMD51_ICM Integrity Check Monitor */
-/*@{*/
-
-#define ICM_U2010
-#define REV_ICM                     0x120
-
-/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WBDIS:1;          /*!< bit:      0  Write Back Disable                 */
-    uint32_t EOMDIS:1;         /*!< bit:      1  End of Monitoring Disable          */
-    uint32_t SLBDIS:1;         /*!< bit:      2  Secondary List Branching Disable   */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t BBC:4;            /*!< bit:  4.. 7  Bus Burden Control                 */
-    uint32_t ASCD:1;           /*!< bit:      8  Automatic Switch To Compare Digest */
-    uint32_t DUALBUFF:1;       /*!< bit:      9  Dual Input Buffer                  */
-    uint32_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint32_t UIHASH:1;         /*!< bit:     12  User Initial Hash Value            */
-    uint32_t UALGO:3;          /*!< bit: 13..15  User SHA Algorithm                 */
-    uint32_t HAPROT:6;         /*!< bit: 16..21  Region Hash Area Protection        */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t DAPROT:6;         /*!< bit: 24..29  Region Descriptor Area Protection  */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_CFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_CFG_OFFSET              0x00         /**< \brief (ICM_CFG offset) Configuration */
-#define ICM_CFG_RESETVALUE          _U_(0x00000000) /**< \brief (ICM_CFG reset_value) Configuration */
-
-#define ICM_CFG_WBDIS_Pos           0            /**< \brief (ICM_CFG) Write Back Disable */
-#define ICM_CFG_WBDIS               (_U_(0x1) << ICM_CFG_WBDIS_Pos)
-#define ICM_CFG_EOMDIS_Pos          1            /**< \brief (ICM_CFG) End of Monitoring Disable */
-#define ICM_CFG_EOMDIS              (_U_(0x1) << ICM_CFG_EOMDIS_Pos)
-#define ICM_CFG_SLBDIS_Pos          2            /**< \brief (ICM_CFG) Secondary List Branching Disable */
-#define ICM_CFG_SLBDIS              (_U_(0x1) << ICM_CFG_SLBDIS_Pos)
-#define ICM_CFG_BBC_Pos             4            /**< \brief (ICM_CFG) Bus Burden Control */
-#define ICM_CFG_BBC_Msk             (_U_(0xF) << ICM_CFG_BBC_Pos)
-#define ICM_CFG_BBC(value)          (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
-#define ICM_CFG_ASCD_Pos            8            /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
-#define ICM_CFG_ASCD                (_U_(0x1) << ICM_CFG_ASCD_Pos)
-#define ICM_CFG_DUALBUFF_Pos        9            /**< \brief (ICM_CFG) Dual Input Buffer */
-#define ICM_CFG_DUALBUFF            (_U_(0x1) << ICM_CFG_DUALBUFF_Pos)
-#define ICM_CFG_UIHASH_Pos          12           /**< \brief (ICM_CFG) User Initial Hash Value */
-#define ICM_CFG_UIHASH              (_U_(0x1) << ICM_CFG_UIHASH_Pos)
-#define ICM_CFG_UALGO_Pos           13           /**< \brief (ICM_CFG) User SHA Algorithm */
-#define ICM_CFG_UALGO_Msk           (_U_(0x7) << ICM_CFG_UALGO_Pos)
-#define ICM_CFG_UALGO(value)        (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
-#define   ICM_CFG_UALGO_SHA1_Val          _U_(0x0)   /**< \brief (ICM_CFG) SHA1 Algorithm */
-#define   ICM_CFG_UALGO_SHA256_Val        _U_(0x1)   /**< \brief (ICM_CFG) SHA256 Algorithm */
-#define   ICM_CFG_UALGO_SHA224_Val        _U_(0x4)   /**< \brief (ICM_CFG) SHA224 Algorithm */
-#define ICM_CFG_UALGO_SHA1          (ICM_CFG_UALGO_SHA1_Val        << ICM_CFG_UALGO_Pos)
-#define ICM_CFG_UALGO_SHA256        (ICM_CFG_UALGO_SHA256_Val      << ICM_CFG_UALGO_Pos)
-#define ICM_CFG_UALGO_SHA224        (ICM_CFG_UALGO_SHA224_Val      << ICM_CFG_UALGO_Pos)
-#define ICM_CFG_HAPROT_Pos          16           /**< \brief (ICM_CFG) Region Hash Area Protection */
-#define ICM_CFG_HAPROT_Msk          (_U_(0x3F) << ICM_CFG_HAPROT_Pos)
-#define ICM_CFG_HAPROT(value)       (ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))
-#define ICM_CFG_DAPROT_Pos          24           /**< \brief (ICM_CFG) Region Descriptor Area Protection */
-#define ICM_CFG_DAPROT_Msk          (_U_(0x3F) << ICM_CFG_DAPROT_Pos)
-#define ICM_CFG_DAPROT(value)       (ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))
-#define ICM_CFG_MASK                _U_(0x3F3FF3F7) /**< \brief (ICM_CFG) MASK Register */
-
-/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ENABLE:1;         /*!< bit:      0  ICM Enable                         */
-    uint32_t DISABLE:1;        /*!< bit:      1  ICM Disable Register               */
-    uint32_t SWRST:1;          /*!< bit:      2  Software Reset                     */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t REHASH:4;         /*!< bit:  4.. 7  Recompute Internal Hash            */
-    uint32_t RMDIS:4;          /*!< bit:  8..11  Region Monitoring Disable          */
-    uint32_t RMEN:4;           /*!< bit: 12..15  Region Monitoring Enable           */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_CTRL_OFFSET             0x04         /**< \brief (ICM_CTRL offset) Control */
-
-#define ICM_CTRL_ENABLE_Pos         0            /**< \brief (ICM_CTRL) ICM Enable */
-#define ICM_CTRL_ENABLE             (_U_(0x1) << ICM_CTRL_ENABLE_Pos)
-#define ICM_CTRL_DISABLE_Pos        1            /**< \brief (ICM_CTRL) ICM Disable Register */
-#define ICM_CTRL_DISABLE            (_U_(0x1) << ICM_CTRL_DISABLE_Pos)
-#define ICM_CTRL_SWRST_Pos          2            /**< \brief (ICM_CTRL) Software Reset */
-#define ICM_CTRL_SWRST              (_U_(0x1) << ICM_CTRL_SWRST_Pos)
-#define ICM_CTRL_REHASH_Pos         4            /**< \brief (ICM_CTRL) Recompute Internal Hash */
-#define ICM_CTRL_REHASH_Msk         (_U_(0xF) << ICM_CTRL_REHASH_Pos)
-#define ICM_CTRL_REHASH(value)      (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
-#define ICM_CTRL_RMDIS_Pos          8            /**< \brief (ICM_CTRL) Region Monitoring Disable */
-#define ICM_CTRL_RMDIS_Msk          (_U_(0xF) << ICM_CTRL_RMDIS_Pos)
-#define ICM_CTRL_RMDIS(value)       (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
-#define ICM_CTRL_RMEN_Pos           12           /**< \brief (ICM_CTRL) Region Monitoring Enable */
-#define ICM_CTRL_RMEN_Msk           (_U_(0xF) << ICM_CTRL_RMEN_Pos)
-#define ICM_CTRL_RMEN(value)        (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
-#define ICM_CTRL_MASK               _U_(0x0000FFF7) /**< \brief (ICM_CTRL) MASK Register */
-
-/* -------- ICM_SR : (ICM Offset: 0x08) (R/  32) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ENABLE:1;         /*!< bit:      0  ICM Controller Enable Register     */
-    uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
-    uint32_t RAWRMDIS:4;       /*!< bit:  8..11  RAW Region Monitoring Disabled Status */
-    uint32_t RMDIS:4;          /*!< bit: 12..15  Region Monitoring Disabled Status  */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_SR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_SR_OFFSET               0x08         /**< \brief (ICM_SR offset) Status */
-#define ICM_SR_RESETVALUE           _U_(0x00000000) /**< \brief (ICM_SR reset_value) Status */
-
-#define ICM_SR_ENABLE_Pos           0            /**< \brief (ICM_SR) ICM Controller Enable Register */
-#define ICM_SR_ENABLE               (_U_(0x1) << ICM_SR_ENABLE_Pos)
-#define ICM_SR_RAWRMDIS_Pos         8            /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */
-#define ICM_SR_RAWRMDIS_Msk         (_U_(0xF) << ICM_SR_RAWRMDIS_Pos)
-#define ICM_SR_RAWRMDIS(value)      (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
-#define ICM_SR_RMDIS_Pos            12           /**< \brief (ICM_SR) Region Monitoring Disabled Status */
-#define ICM_SR_RMDIS_Msk            (_U_(0xF) << ICM_SR_RMDIS_Pos)
-#define ICM_SR_RMDIS(value)         (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
-#define ICM_SR_MASK                 _U_(0x0000FF01) /**< \brief (ICM_SR) MASK Register */
-
-/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RHC:4;            /*!< bit:  0.. 3  Region Hash Completed Interrupt Enable */
-    uint32_t RDM:4;            /*!< bit:  4.. 7  Region Digest Mismatch Interrupt Enable */
-    uint32_t RBE:4;            /*!< bit:  8..11  Region Bus Error Interrupt Enable  */
-    uint32_t RWC:4;            /*!< bit: 12..15  Region Wrap Condition detected Interrupt Enable */
-    uint32_t REC:4;            /*!< bit: 16..19  Region End bit Condition Detected Interrupt Enable */
-    uint32_t RSU:4;            /*!< bit: 20..23  Region Status Updated Interrupt Disable */
-    uint32_t URAD:1;           /*!< bit:     24  Undefined Register Access Detection Interrupt Enable */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_IER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_IER_OFFSET              0x10         /**< \brief (ICM_IER offset) Interrupt Enable */
-
-#define ICM_IER_RHC_Pos             0            /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
-#define ICM_IER_RHC_Msk             (_U_(0xF) << ICM_IER_RHC_Pos)
-#define ICM_IER_RHC(value)          (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
-#define ICM_IER_RDM_Pos             4            /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
-#define ICM_IER_RDM_Msk             (_U_(0xF) << ICM_IER_RDM_Pos)
-#define ICM_IER_RDM(value)          (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
-#define ICM_IER_RBE_Pos             8            /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
-#define ICM_IER_RBE_Msk             (_U_(0xF) << ICM_IER_RBE_Pos)
-#define ICM_IER_RBE(value)          (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
-#define ICM_IER_RWC_Pos             12           /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
-#define ICM_IER_RWC_Msk             (_U_(0xF) << ICM_IER_RWC_Pos)
-#define ICM_IER_RWC(value)          (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
-#define ICM_IER_REC_Pos             16           /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
-#define ICM_IER_REC_Msk             (_U_(0xF) << ICM_IER_REC_Pos)
-#define ICM_IER_REC(value)          (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
-#define ICM_IER_RSU_Pos             20           /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
-#define ICM_IER_RSU_Msk             (_U_(0xF) << ICM_IER_RSU_Pos)
-#define ICM_IER_RSU(value)          (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
-#define ICM_IER_URAD_Pos            24           /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
-#define ICM_IER_URAD                (_U_(0x1) << ICM_IER_URAD_Pos)
-#define ICM_IER_MASK                _U_(0x01FFFFFF) /**< \brief (ICM_IER) MASK Register */
-
-/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RHC:4;            /*!< bit:  0.. 3  Region Hash Completed Interrupt Disable */
-    uint32_t RDM:4;            /*!< bit:  4.. 7  Region Digest Mismatch Interrupt Disable */
-    uint32_t RBE:4;            /*!< bit:  8..11  Region Bus Error Interrupt Disable */
-    uint32_t RWC:4;            /*!< bit: 12..15  Region Wrap Condition Detected Interrupt Disable */
-    uint32_t REC:4;            /*!< bit: 16..19  Region End bit Condition detected Interrupt Disable */
-    uint32_t RSU:4;            /*!< bit: 20..23  Region Status Updated Interrupt Disable */
-    uint32_t URAD:1;           /*!< bit:     24  Undefined Register Access Detection Interrupt Disable */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_IDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_IDR_OFFSET              0x14         /**< \brief (ICM_IDR offset) Interrupt Disable */
-#define ICM_IDR_RESETVALUE          _U_(0x00000000) /**< \brief (ICM_IDR reset_value) Interrupt Disable */
-
-#define ICM_IDR_RHC_Pos             0            /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
-#define ICM_IDR_RHC_Msk             (_U_(0xF) << ICM_IDR_RHC_Pos)
-#define ICM_IDR_RHC(value)          (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
-#define ICM_IDR_RDM_Pos             4            /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
-#define ICM_IDR_RDM_Msk             (_U_(0xF) << ICM_IDR_RDM_Pos)
-#define ICM_IDR_RDM(value)          (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
-#define ICM_IDR_RBE_Pos             8            /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
-#define ICM_IDR_RBE_Msk             (_U_(0xF) << ICM_IDR_RBE_Pos)
-#define ICM_IDR_RBE(value)          (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
-#define ICM_IDR_RWC_Pos             12           /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
-#define ICM_IDR_RWC_Msk             (_U_(0xF) << ICM_IDR_RWC_Pos)
-#define ICM_IDR_RWC(value)          (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
-#define ICM_IDR_REC_Pos             16           /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
-#define ICM_IDR_REC_Msk             (_U_(0xF) << ICM_IDR_REC_Pos)
-#define ICM_IDR_REC(value)          (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
-#define ICM_IDR_RSU_Pos             20           /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
-#define ICM_IDR_RSU_Msk             (_U_(0xF) << ICM_IDR_RSU_Pos)
-#define ICM_IDR_RSU(value)          (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
-#define ICM_IDR_URAD_Pos            24           /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
-#define ICM_IDR_URAD                (_U_(0x1) << ICM_IDR_URAD_Pos)
-#define ICM_IDR_MASK                _U_(0x01FFFFFF) /**< \brief (ICM_IDR) MASK Register */
-
-/* -------- ICM_IMR : (ICM Offset: 0x18) (R/  32) Interrupt Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RHC:4;            /*!< bit:  0.. 3  Region Hash Completed Interrupt Mask */
-    uint32_t RDM:4;            /*!< bit:  4.. 7  Region Digest Mismatch Interrupt Mask */
-    uint32_t RBE:4;            /*!< bit:  8..11  Region Bus Error Interrupt Mask    */
-    uint32_t RWC:4;            /*!< bit: 12..15  Region Wrap Condition Detected Interrupt Mask */
-    uint32_t REC:4;            /*!< bit: 16..19  Region End bit Condition Detected Interrupt Mask */
-    uint32_t RSU:4;            /*!< bit: 20..23  Region Status Updated Interrupt Mask */
-    uint32_t URAD:1;           /*!< bit:     24  Undefined Register Access Detection Interrupt Mask */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_IMR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_IMR_OFFSET              0x18         /**< \brief (ICM_IMR offset) Interrupt Mask */
-#define ICM_IMR_RESETVALUE          _U_(0x00000000) /**< \brief (ICM_IMR reset_value) Interrupt Mask */
-
-#define ICM_IMR_RHC_Pos             0            /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
-#define ICM_IMR_RHC_Msk             (_U_(0xF) << ICM_IMR_RHC_Pos)
-#define ICM_IMR_RHC(value)          (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
-#define ICM_IMR_RDM_Pos             4            /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
-#define ICM_IMR_RDM_Msk             (_U_(0xF) << ICM_IMR_RDM_Pos)
-#define ICM_IMR_RDM(value)          (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
-#define ICM_IMR_RBE_Pos             8            /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
-#define ICM_IMR_RBE_Msk             (_U_(0xF) << ICM_IMR_RBE_Pos)
-#define ICM_IMR_RBE(value)          (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
-#define ICM_IMR_RWC_Pos             12           /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
-#define ICM_IMR_RWC_Msk             (_U_(0xF) << ICM_IMR_RWC_Pos)
-#define ICM_IMR_RWC(value)          (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
-#define ICM_IMR_REC_Pos             16           /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
-#define ICM_IMR_REC_Msk             (_U_(0xF) << ICM_IMR_REC_Pos)
-#define ICM_IMR_REC(value)          (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
-#define ICM_IMR_RSU_Pos             20           /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
-#define ICM_IMR_RSU_Msk             (_U_(0xF) << ICM_IMR_RSU_Pos)
-#define ICM_IMR_RSU(value)          (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
-#define ICM_IMR_URAD_Pos            24           /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
-#define ICM_IMR_URAD                (_U_(0x1) << ICM_IMR_URAD_Pos)
-#define ICM_IMR_MASK                _U_(0x01FFFFFF) /**< \brief (ICM_IMR) MASK Register */
-
-/* -------- ICM_ISR : (ICM Offset: 0x1C) (R/  32) Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RHC:4;            /*!< bit:  0.. 3  Region Hash Completed              */
-    uint32_t RDM:4;            /*!< bit:  4.. 7  Region Digest Mismatch             */
-    uint32_t RBE:4;            /*!< bit:  8..11  Region Bus Error                   */
-    uint32_t RWC:4;            /*!< bit: 12..15  Region Wrap Condition Detected     */
-    uint32_t REC:4;            /*!< bit: 16..19  Region End bit Condition Detected  */
-    uint32_t RSU:4;            /*!< bit: 20..23  Region Status Updated Detected     */
-    uint32_t URAD:1;           /*!< bit:     24  Undefined Register Access Detection Status */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_ISR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_ISR_OFFSET              0x1C         /**< \brief (ICM_ISR offset) Interrupt Status */
-#define ICM_ISR_RESETVALUE          _U_(0x00000000) /**< \brief (ICM_ISR reset_value) Interrupt Status */
-
-#define ICM_ISR_RHC_Pos             0            /**< \brief (ICM_ISR) Region Hash Completed */
-#define ICM_ISR_RHC_Msk             (_U_(0xF) << ICM_ISR_RHC_Pos)
-#define ICM_ISR_RHC(value)          (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
-#define ICM_ISR_RDM_Pos             4            /**< \brief (ICM_ISR) Region Digest Mismatch */
-#define ICM_ISR_RDM_Msk             (_U_(0xF) << ICM_ISR_RDM_Pos)
-#define ICM_ISR_RDM(value)          (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
-#define ICM_ISR_RBE_Pos             8            /**< \brief (ICM_ISR) Region Bus Error */
-#define ICM_ISR_RBE_Msk             (_U_(0xF) << ICM_ISR_RBE_Pos)
-#define ICM_ISR_RBE(value)          (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
-#define ICM_ISR_RWC_Pos             12           /**< \brief (ICM_ISR) Region Wrap Condition Detected */
-#define ICM_ISR_RWC_Msk             (_U_(0xF) << ICM_ISR_RWC_Pos)
-#define ICM_ISR_RWC(value)          (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
-#define ICM_ISR_REC_Pos             16           /**< \brief (ICM_ISR) Region End bit Condition Detected */
-#define ICM_ISR_REC_Msk             (_U_(0xF) << ICM_ISR_REC_Pos)
-#define ICM_ISR_REC(value)          (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
-#define ICM_ISR_RSU_Pos             20           /**< \brief (ICM_ISR) Region Status Updated Detected */
-#define ICM_ISR_RSU_Msk             (_U_(0xF) << ICM_ISR_RSU_Pos)
-#define ICM_ISR_RSU(value)          (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
-#define ICM_ISR_URAD_Pos            24           /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
-#define ICM_ISR_URAD                (_U_(0x1) << ICM_ISR_URAD_Pos)
-#define ICM_ISR_MASK                _U_(0x01FFFFFF) /**< \brief (ICM_ISR) MASK Register */
-
-/* -------- ICM_UASR : (ICM Offset: 0x20) (R/  32) Undefined Access Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t URAT:3;           /*!< bit:  0.. 2  Undefined Register Access Trace    */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_UASR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_UASR_OFFSET             0x20         /**< \brief (ICM_UASR offset) Undefined Access Status */
-#define ICM_UASR_RESETVALUE         _U_(0x00000000) /**< \brief (ICM_UASR reset_value) Undefined Access Status */
-
-#define ICM_UASR_URAT_Pos           0            /**< \brief (ICM_UASR) Undefined Register Access Trace */
-#define ICM_UASR_URAT_Msk           (_U_(0x7) << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT(value)        (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
-#define   ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0)   /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded */
-#define   ICM_UASR_URAT_CFG_MODIFIED_Val  _U_(0x1)   /**< \brief (ICM_UASR) CFG modified during active monitoring */
-#define   ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2)   /**< \brief (ICM_UASR) DSCR modified during active monitoring */
-#define   ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3)   /**< \brief (ICM_UASR) HASH modified during active monitoring */
-#define   ICM_UASR_URAT_READ_ACCESS_Val   _U_(0x4)   /**< \brief (ICM_UASR) Write-only register read access */
-#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT_CFG_MODIFIED  (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_URAT_READ_ACCESS   (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos)
-#define ICM_UASR_MASK               _U_(0x00000007) /**< \brief (ICM_UASR) MASK Register */
-
-/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
-    uint32_t DASA:26;          /*!< bit:  6..31  Descriptor Area Start Address      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_DSCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_DSCR_OFFSET             0x30         /**< \brief (ICM_DSCR offset) Region Descriptor Area Start Address */
-#define ICM_DSCR_RESETVALUE         _U_(0x00000000) /**< \brief (ICM_DSCR reset_value) Region Descriptor Area Start Address */
-
-#define ICM_DSCR_DASA_Pos           6            /**< \brief (ICM_DSCR) Descriptor Area Start Address */
-#define ICM_DSCR_DASA_Msk           (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos)
-#define ICM_DSCR_DASA(value)        (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
-#define ICM_DSCR_MASK               _U_(0xFFFFFFC0) /**< \brief (ICM_DSCR) MASK Register */
-
-/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :7;               /*!< bit:  0.. 6  Reserved                           */
-    uint32_t HASA:25;          /*!< bit:  7..31  Hash Area Start Address            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_HASH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_HASH_OFFSET             0x34         /**< \brief (ICM_HASH offset) Region Hash Area Start Address */
-#define ICM_HASH_RESETVALUE         _U_(0x00000000) /**< \brief (ICM_HASH reset_value) Region Hash Area Start Address */
-
-#define ICM_HASH_HASA_Pos           7            /**< \brief (ICM_HASH) Hash Area Start Address */
-#define ICM_HASH_HASA_Msk           (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos)
-#define ICM_HASH_HASA(value)        (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
-#define ICM_HASH_MASK               _U_(0xFFFFFF80) /**< \brief (ICM_HASH) MASK Register */
-
-/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t VAL:32;           /*!< bit:  0..31  Initial Hash Value                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_UIHVAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_UIHVAL_OFFSET           0x38         /**< \brief (ICM_UIHVAL offset) User Initial Hash Value n */
-#define ICM_UIHVAL_RESETVALUE       _U_(0x00000000) /**< \brief (ICM_UIHVAL reset_value) User Initial Hash Value n */
-
-#define ICM_UIHVAL_VAL_Pos          0            /**< \brief (ICM_UIHVAL) Initial Hash Value */
-#define ICM_UIHVAL_VAL_Msk          (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos)
-#define ICM_UIHVAL_VAL(value)       (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
-#define ICM_UIHVAL_MASK             _U_(0xFFFFFFFF) /**< \brief (ICM_UIHVAL) MASK Register */
-
-/* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_RADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_RADDR_OFFSET            0x00         /**< \brief (ICM_RADDR offset) Region Start Address */
-#define ICM_RADDR_MASK              _U_(0xFFFFFFFF) /**< \brief (ICM_RADDR) MASK Register */
-
-/* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CDWBN:1;          /*!< bit:      0  Compare Digest Write Back          */
-    uint32_t WRAP:1;           /*!< bit:      1  Region Wrap                        */
-    uint32_t EOM:1;            /*!< bit:      2  End of Monitoring                  */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t RHIEN:1;          /*!< bit:      4  Region Hash Interrupt Enable       */
-    uint32_t DMIEN:1;          /*!< bit:      5  Region Digest Mismatch Interrupt Enable */
-    uint32_t BEIEN:1;          /*!< bit:      6  Region Bus Error Interrupt Enable  */
-    uint32_t WCIEN:1;          /*!< bit:      7  Region Wrap Condition Detected Interrupt Enable */
-    uint32_t ECIEN:1;          /*!< bit:      8  Region End bit Condition detected Interrupt Enable */
-    uint32_t SUIEN:1;          /*!< bit:      9  Region Status Updated Interrupt Enable */
-    uint32_t PROCDLY:1;        /*!< bit:     10  SHA Processing Delay               */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t ALGO:3;           /*!< bit: 12..14  SHA Algorithm                      */
-    uint32_t :9;               /*!< bit: 15..23  Reserved                           */
-    uint32_t MRPROT:6;         /*!< bit: 24..29  Memory Region AHB Protection       */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_RCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_RCFG_OFFSET             0x04         /**< \brief (ICM_RCFG offset) Region Configuration */
-#define ICM_RCFG_RESETVALUE         _U_(0x00000000) /**< \brief (ICM_RCFG reset_value) Region Configuration */
-
-#define ICM_RCFG_CDWBN_Pos          0            /**< \brief (ICM_RCFG) Compare Digest Write Back */
-#define ICM_RCFG_CDWBN              (_U_(0x1) << ICM_RCFG_CDWBN_Pos)
-#define   ICM_RCFG_CDWBN_WRBA_Val         _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_CDWBN_COMP_Val         _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_CDWBN_WRBA         (ICM_RCFG_CDWBN_WRBA_Val       << ICM_RCFG_CDWBN_Pos)
-#define ICM_RCFG_CDWBN_COMP         (ICM_RCFG_CDWBN_COMP_Val       << ICM_RCFG_CDWBN_Pos)
-#define ICM_RCFG_WRAP_Pos           1            /**< \brief (ICM_RCFG) Region Wrap */
-#define ICM_RCFG_WRAP               (_U_(0x1) << ICM_RCFG_WRAP_Pos)
-#define   ICM_RCFG_WRAP_NO_Val            _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_WRAP_YES_Val           _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_WRAP_NO            (ICM_RCFG_WRAP_NO_Val          << ICM_RCFG_WRAP_Pos)
-#define ICM_RCFG_WRAP_YES           (ICM_RCFG_WRAP_YES_Val         << ICM_RCFG_WRAP_Pos)
-#define ICM_RCFG_EOM_Pos            2            /**< \brief (ICM_RCFG) End of Monitoring */
-#define ICM_RCFG_EOM                (_U_(0x1) << ICM_RCFG_EOM_Pos)
-#define   ICM_RCFG_EOM_NO_Val             _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_EOM_YES_Val            _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_EOM_NO             (ICM_RCFG_EOM_NO_Val           << ICM_RCFG_EOM_Pos)
-#define ICM_RCFG_EOM_YES            (ICM_RCFG_EOM_YES_Val          << ICM_RCFG_EOM_Pos)
-#define ICM_RCFG_RHIEN_Pos          4            /**< \brief (ICM_RCFG) Region Hash Interrupt Enable */
-#define ICM_RCFG_RHIEN              (_U_(0x1) << ICM_RCFG_RHIEN_Pos)
-#define   ICM_RCFG_RHIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_RHIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_RHIEN_EN           (ICM_RCFG_RHIEN_EN_Val         << ICM_RCFG_RHIEN_Pos)
-#define ICM_RCFG_RHIEN_DIS          (ICM_RCFG_RHIEN_DIS_Val        << ICM_RCFG_RHIEN_Pos)
-#define ICM_RCFG_DMIEN_Pos          5            /**< \brief (ICM_RCFG) Region Digest Mismatch Interrupt Enable */
-#define ICM_RCFG_DMIEN              (_U_(0x1) << ICM_RCFG_DMIEN_Pos)
-#define   ICM_RCFG_DMIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_DMIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_DMIEN_EN           (ICM_RCFG_DMIEN_EN_Val         << ICM_RCFG_DMIEN_Pos)
-#define ICM_RCFG_DMIEN_DIS          (ICM_RCFG_DMIEN_DIS_Val        << ICM_RCFG_DMIEN_Pos)
-#define ICM_RCFG_BEIEN_Pos          6            /**< \brief (ICM_RCFG) Region Bus Error Interrupt Enable */
-#define ICM_RCFG_BEIEN              (_U_(0x1) << ICM_RCFG_BEIEN_Pos)
-#define   ICM_RCFG_BEIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_BEIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_BEIEN_EN           (ICM_RCFG_BEIEN_EN_Val         << ICM_RCFG_BEIEN_Pos)
-#define ICM_RCFG_BEIEN_DIS          (ICM_RCFG_BEIEN_DIS_Val        << ICM_RCFG_BEIEN_Pos)
-#define ICM_RCFG_WCIEN_Pos          7            /**< \brief (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable */
-#define ICM_RCFG_WCIEN              (_U_(0x1) << ICM_RCFG_WCIEN_Pos)
-#define   ICM_RCFG_WCIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_WCIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_WCIEN_EN           (ICM_RCFG_WCIEN_EN_Val         << ICM_RCFG_WCIEN_Pos)
-#define ICM_RCFG_WCIEN_DIS          (ICM_RCFG_WCIEN_DIS_Val        << ICM_RCFG_WCIEN_Pos)
-#define ICM_RCFG_ECIEN_Pos          8            /**< \brief (ICM_RCFG) Region End bit Condition detected Interrupt Enable */
-#define ICM_RCFG_ECIEN              (_U_(0x1) << ICM_RCFG_ECIEN_Pos)
-#define   ICM_RCFG_ECIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_ECIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_ECIEN_EN           (ICM_RCFG_ECIEN_EN_Val         << ICM_RCFG_ECIEN_Pos)
-#define ICM_RCFG_ECIEN_DIS          (ICM_RCFG_ECIEN_DIS_Val        << ICM_RCFG_ECIEN_Pos)
-#define ICM_RCFG_SUIEN_Pos          9            /**< \brief (ICM_RCFG) Region Status Updated Interrupt Enable */
-#define ICM_RCFG_SUIEN              (_U_(0x1) << ICM_RCFG_SUIEN_Pos)
-#define   ICM_RCFG_SUIEN_EN_Val           _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_SUIEN_DIS_Val          _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_SUIEN_EN           (ICM_RCFG_SUIEN_EN_Val         << ICM_RCFG_SUIEN_Pos)
-#define ICM_RCFG_SUIEN_DIS          (ICM_RCFG_SUIEN_DIS_Val        << ICM_RCFG_SUIEN_Pos)
-#define ICM_RCFG_PROCDLY_Pos        10           /**< \brief (ICM_RCFG) SHA Processing Delay */
-#define ICM_RCFG_PROCDLY            (_U_(0x1) << ICM_RCFG_PROCDLY_Pos)
-#define   ICM_RCFG_PROCDLY_SHORT_Val      _U_(0x0)   /**< \brief (ICM_RCFG)  */
-#define   ICM_RCFG_PROCDLY_LONG_Val       _U_(0x1)   /**< \brief (ICM_RCFG)  */
-#define ICM_RCFG_PROCDLY_SHORT      (ICM_RCFG_PROCDLY_SHORT_Val    << ICM_RCFG_PROCDLY_Pos)
-#define ICM_RCFG_PROCDLY_LONG       (ICM_RCFG_PROCDLY_LONG_Val     << ICM_RCFG_PROCDLY_Pos)
-#define ICM_RCFG_ALGO_Pos           12           /**< \brief (ICM_RCFG) SHA Algorithm */
-#define ICM_RCFG_ALGO_Msk           (_U_(0x7) << ICM_RCFG_ALGO_Pos)
-#define ICM_RCFG_ALGO(value)        (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos))
-#define ICM_RCFG_MRPROT_Pos         24           /**< \brief (ICM_RCFG) Memory Region AHB Protection */
-#define ICM_RCFG_MRPROT_Msk         (_U_(0x3F) << ICM_RCFG_MRPROT_Pos)
-#define ICM_RCFG_MRPROT(value)      (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))
-#define ICM_RCFG_MASK               _U_(0x3F0077F7) /**< \brief (ICM_RCFG) MASK Register */
-
-/* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TRSIZE:16;        /*!< bit:  0..15  Transfer Size                      */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_RCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_RCTRL_OFFSET            0x08         /**< \brief (ICM_RCTRL offset) Region Control */
-
-#define ICM_RCTRL_TRSIZE_Pos        0            /**< \brief (ICM_RCTRL) Transfer Size */
-#define ICM_RCTRL_TRSIZE_Msk        (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos)
-#define ICM_RCTRL_TRSIZE(value)     (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos))
-#define ICM_RCTRL_MASK              _U_(0x0000FFFF) /**< \brief (ICM_RCTRL) MASK Register */
-
-/* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} ICM_RNEXT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define ICM_RNEXT_OFFSET            0x0C         /**< \brief (ICM_RNEXT offset) Region Next Address */
-#define ICM_RNEXT_MASK              _U_(0xFFFFFFFF) /**< \brief (ICM_RNEXT) MASK Register */
-
-/** \brief ICM APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO ICM_CFG_Type              CFG;         /**< \brief Offset: 0x00 (R/W 32) Configuration */
-  __O  ICM_CTRL_Type             CTRL;        /**< \brief Offset: 0x04 ( /W 32) Control */
-  __I  ICM_SR_Type               SR;          /**< \brief Offset: 0x08 (R/  32) Status */
-       RoReg8                    Reserved1[0x4];
-  __O  ICM_IER_Type              IER;         /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable */
-  __O  ICM_IDR_Type              IDR;         /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable */
-  __I  ICM_IMR_Type              IMR;         /**< \brief Offset: 0x18 (R/  32) Interrupt Mask */
-  __I  ICM_ISR_Type              ISR;         /**< \brief Offset: 0x1C (R/  32) Interrupt Status */
-  __I  ICM_UASR_Type             UASR;        /**< \brief Offset: 0x20 (R/  32) Undefined Access Status */
-       RoReg8                    Reserved2[0xC];
-  __IO ICM_DSCR_Type             DSCR;        /**< \brief Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */
-  __IO ICM_HASH_Type             HASH;        /**< \brief Offset: 0x34 (R/W 32) Region Hash Area Start Address */
-  __O  ICM_UIHVAL_Type           UIHVAL[8];   /**< \brief Offset: 0x38 ( /W 32) User Initial Hash Value n */
-} Icm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief ICM Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO ICM_RADDR_Type            RADDR;       /**< \brief Offset: 0x00 (R/W 32) Region Start Address */
-  __IO ICM_RCFG_Type             RCFG;        /**< \brief Offset: 0x04 (R/W 32) Region Configuration */
-  __IO ICM_RCTRL_Type            RCTRL;       /**< \brief Offset: 0x08 (R/W 32) Region Control */
-  __IO ICM_RNEXT_Type            RNEXT;       /**< \brief Offset: 0x0C (R/W 32) Region Next Address */
-} IcmDescriptor;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_ICM_DESCRIPTOR
-
-/*@}*/
-
-#endif /* _SAMD51_ICM_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/mclk.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/mclk.h
deleted file mode 100644
index 23f84a9b18..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/mclk.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for MCLK
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_MCLK_COMPONENT_
-#define _SAMD51_MCLK_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR MCLK */
-/* ========================================================================== */
-/** \addtogroup SAMD51_MCLK Main Clock */
-/*@{*/
-
-#define MCLK_U2408
-#define REV_MCLK                    0x100
-
-/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} MCLK_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_INTENCLR_OFFSET        0x01         /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */
-#define MCLK_INTENCLR_RESETVALUE    _U_(0x00)    /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define MCLK_INTENCLR_CKRDY_Pos     0            /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */
-#define MCLK_INTENCLR_CKRDY         (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
-#define MCLK_INTENCLR_MASK          _U_(0x01)    /**< \brief (MCLK_INTENCLR) MASK Register */
-
-/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} MCLK_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_INTENSET_OFFSET        0x02         /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */
-#define MCLK_INTENSET_RESETVALUE    _U_(0x00)    /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */
-
-#define MCLK_INTENSET_CKRDY_Pos     0            /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */
-#define MCLK_INTENSET_CKRDY         (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
-#define MCLK_INTENSET_MASK          _U_(0x01)    /**< \brief (MCLK_INTENSET) MASK Register */
-
-/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} MCLK_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_INTFLAG_OFFSET         0x03         /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */
-#define MCLK_INTFLAG_RESETVALUE     _U_(0x01)    /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define MCLK_INTFLAG_CKRDY_Pos      0            /**< \brief (MCLK_INTFLAG) Clock Ready */
-#define MCLK_INTFLAG_CKRDY          (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
-#define MCLK_INTFLAG_MASK           _U_(0x01)    /**< \brief (MCLK_INTFLAG) MASK Register */
-
-/* -------- MCLK_HSDIV : (MCLK Offset: 0x04) (R/   8) HS Clock Division -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIV:8;            /*!< bit:  0.. 7  CPU Clock Division Factor          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} MCLK_HSDIV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_HSDIV_OFFSET           0x04         /**< \brief (MCLK_HSDIV offset) HS Clock Division */
-#define MCLK_HSDIV_RESETVALUE       _U_(0x01)    /**< \brief (MCLK_HSDIV reset_value) HS Clock Division */
-
-#define MCLK_HSDIV_DIV_Pos          0            /**< \brief (MCLK_HSDIV) CPU Clock Division Factor */
-#define MCLK_HSDIV_DIV_Msk          (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)
-#define MCLK_HSDIV_DIV(value)       (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
-#define   MCLK_HSDIV_DIV_DIV1_Val         _U_(0x1)   /**< \brief (MCLK_HSDIV) Divide by 1 */
-#define MCLK_HSDIV_DIV_DIV1         (MCLK_HSDIV_DIV_DIV1_Val       << MCLK_HSDIV_DIV_Pos)
-#define MCLK_HSDIV_MASK             _U_(0xFF)    /**< \brief (MCLK_HSDIV) MASK Register */
-
-/* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W  8) CPU Clock Division -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIV:8;            /*!< bit:  0.. 7  Low-Power Clock Division Factor    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} MCLK_CPUDIV_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_CPUDIV_OFFSET          0x05         /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */
-#define MCLK_CPUDIV_RESETVALUE      _U_(0x01)    /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */
-
-#define MCLK_CPUDIV_DIV_Pos         0            /**< \brief (MCLK_CPUDIV) Low-Power Clock Division Factor */
-#define MCLK_CPUDIV_DIV_Msk         (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV(value)      (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
-#define   MCLK_CPUDIV_DIV_DIV1_Val        _U_(0x1)   /**< \brief (MCLK_CPUDIV) Divide by 1 */
-#define   MCLK_CPUDIV_DIV_DIV2_Val        _U_(0x2)   /**< \brief (MCLK_CPUDIV) Divide by 2 */
-#define   MCLK_CPUDIV_DIV_DIV4_Val        _U_(0x4)   /**< \brief (MCLK_CPUDIV) Divide by 4 */
-#define   MCLK_CPUDIV_DIV_DIV8_Val        _U_(0x8)   /**< \brief (MCLK_CPUDIV) Divide by 8 */
-#define   MCLK_CPUDIV_DIV_DIV16_Val       _U_(0x10)   /**< \brief (MCLK_CPUDIV) Divide by 16 */
-#define   MCLK_CPUDIV_DIV_DIV32_Val       _U_(0x20)   /**< \brief (MCLK_CPUDIV) Divide by 32 */
-#define   MCLK_CPUDIV_DIV_DIV64_Val       _U_(0x40)   /**< \brief (MCLK_CPUDIV) Divide by 64 */
-#define   MCLK_CPUDIV_DIV_DIV128_Val      _U_(0x80)   /**< \brief (MCLK_CPUDIV) Divide by 128 */
-#define MCLK_CPUDIV_DIV_DIV1        (MCLK_CPUDIV_DIV_DIV1_Val      << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV2        (MCLK_CPUDIV_DIV_DIV2_Val      << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV4        (MCLK_CPUDIV_DIV_DIV4_Val      << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV8        (MCLK_CPUDIV_DIV_DIV8_Val      << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV16       (MCLK_CPUDIV_DIV_DIV16_Val     << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV32       (MCLK_CPUDIV_DIV_DIV32_Val     << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV64       (MCLK_CPUDIV_DIV_DIV64_Val     << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_DIV_DIV128      (MCLK_CPUDIV_DIV_DIV128_Val    << MCLK_CPUDIV_DIV_Pos)
-#define MCLK_CPUDIV_MASK            _U_(0xFF)    /**< \brief (MCLK_CPUDIV) MASK Register */
-
-/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
-    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
-    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
-    uint32_t HPB3_:1;          /*!< bit:      3  HPB3 AHB Clock Mask                */
-    uint32_t DSU_:1;           /*!< bit:      4  DSU AHB Clock Mask                 */
-    uint32_t HMATRIX_:1;       /*!< bit:      5  HMATRIX AHB Clock Mask             */
-    uint32_t NVMCTRL_:1;       /*!< bit:      6  NVMCTRL AHB Clock Mask             */
-    uint32_t HSRAM_:1;         /*!< bit:      7  HSRAM AHB Clock Mask               */
-    uint32_t CMCC_:1;          /*!< bit:      8  CMCC AHB Clock Mask                */
-    uint32_t DMAC_:1;          /*!< bit:      9  DMAC AHB Clock Mask                */
-    uint32_t USB_:1;           /*!< bit:     10  USB AHB Clock Mask                 */
-    uint32_t BKUPRAM_:1;       /*!< bit:     11  BKUPRAM AHB Clock Mask             */
-    uint32_t PAC_:1;           /*!< bit:     12  PAC AHB Clock Mask                 */
-    uint32_t QSPI_:1;          /*!< bit:     13  QSPI AHB Clock Mask                */
-    uint32_t :1;               /*!< bit:     14  Reserved                           */
-    uint32_t SDHC0_:1;         /*!< bit:     15  SDHC0 AHB Clock Mask               */
-    uint32_t SDHC1_:1;         /*!< bit:     16  SDHC1 AHB Clock Mask               */
-    uint32_t :2;               /*!< bit: 17..18  Reserved                           */
-    uint32_t ICM_:1;           /*!< bit:     19  ICM AHB Clock Mask                 */
-    uint32_t PUKCC_:1;         /*!< bit:     20  PUKCC AHB Clock Mask               */
-    uint32_t QSPI_2X_:1;       /*!< bit:     21  QSPI_2X AHB Clock Mask             */
-    uint32_t NVMCTRL_SMEEPROM_:1; /*!< bit:     22  NVMCTRL_SMEEPROM AHB Clock Mask    */
-    uint32_t NVMCTRL_CACHE_:1; /*!< bit:     23  NVMCTRL_CACHE AHB Clock Mask       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} MCLK_AHBMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_AHBMASK_OFFSET         0x10         /**< \brief (MCLK_AHBMASK offset) AHB Mask */
-#define MCLK_AHBMASK_RESETVALUE     _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */
-
-#define MCLK_AHBMASK_HPB0_Pos       0            /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */
-#define MCLK_AHBMASK_HPB0           (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
-#define MCLK_AHBMASK_HPB1_Pos       1            /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */
-#define MCLK_AHBMASK_HPB1           (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
-#define MCLK_AHBMASK_HPB2_Pos       2            /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */
-#define MCLK_AHBMASK_HPB2           (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
-#define MCLK_AHBMASK_HPB3_Pos       3            /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */
-#define MCLK_AHBMASK_HPB3           (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
-#define MCLK_AHBMASK_DSU_Pos        4            /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */
-#define MCLK_AHBMASK_DSU            (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
-#define MCLK_AHBMASK_HMATRIX_Pos    5            /**< \brief (MCLK_AHBMASK) HMATRIX AHB Clock Mask */
-#define MCLK_AHBMASK_HMATRIX        (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)
-#define MCLK_AHBMASK_NVMCTRL_Pos    6            /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */
-#define MCLK_AHBMASK_NVMCTRL        (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
-#define MCLK_AHBMASK_HSRAM_Pos      7            /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */
-#define MCLK_AHBMASK_HSRAM          (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
-#define MCLK_AHBMASK_CMCC_Pos       8            /**< \brief (MCLK_AHBMASK) CMCC AHB Clock Mask */
-#define MCLK_AHBMASK_CMCC           (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)
-#define MCLK_AHBMASK_DMAC_Pos       9            /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */
-#define MCLK_AHBMASK_DMAC           (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
-#define MCLK_AHBMASK_USB_Pos        10           /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */
-#define MCLK_AHBMASK_USB            (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
-#define MCLK_AHBMASK_BKUPRAM_Pos    11           /**< \brief (MCLK_AHBMASK) BKUPRAM AHB Clock Mask */
-#define MCLK_AHBMASK_BKUPRAM        (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)
-#define MCLK_AHBMASK_PAC_Pos        12           /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */
-#define MCLK_AHBMASK_PAC            (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
-#define MCLK_AHBMASK_QSPI_Pos       13           /**< \brief (MCLK_AHBMASK) QSPI AHB Clock Mask */
-#define MCLK_AHBMASK_QSPI           (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
-#define MCLK_AHBMASK_SDHC0_Pos      15           /**< \brief (MCLK_AHBMASK) SDHC0 AHB Clock Mask */
-#define MCLK_AHBMASK_SDHC0          (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
-#define MCLK_AHBMASK_SDHC1_Pos      16           /**< \brief (MCLK_AHBMASK) SDHC1 AHB Clock Mask */
-#define MCLK_AHBMASK_SDHC1          (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
-#define MCLK_AHBMASK_ICM_Pos        19           /**< \brief (MCLK_AHBMASK) ICM AHB Clock Mask */
-#define MCLK_AHBMASK_ICM            (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
-#define MCLK_AHBMASK_PUKCC_Pos      20           /**< \brief (MCLK_AHBMASK) PUKCC AHB Clock Mask */
-#define MCLK_AHBMASK_PUKCC          (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)
-#define MCLK_AHBMASK_QSPI_2X_Pos    21           /**< \brief (MCLK_AHBMASK) QSPI_2X AHB Clock Mask */
-#define MCLK_AHBMASK_QSPI_2X        (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)
-#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22           /**< \brief (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask */
-#define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
-#define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23           /**< \brief (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask */
-#define MCLK_AHBMASK_NVMCTRL_CACHE  (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
-#define MCLK_AHBMASK_MASK           _U_(0x00F9BFFF) /**< \brief (MCLK_AHBMASK) MASK Register */
-
-/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PAC_:1;           /*!< bit:      0  PAC APB Clock Enable               */
-    uint32_t PM_:1;            /*!< bit:      1  PM APB Clock Enable                */
-    uint32_t MCLK_:1;          /*!< bit:      2  MCLK APB Clock Enable              */
-    uint32_t RSTC_:1;          /*!< bit:      3  RSTC APB Clock Enable              */
-    uint32_t OSCCTRL_:1;       /*!< bit:      4  OSCCTRL APB Clock Enable           */
-    uint32_t OSC32KCTRL_:1;    /*!< bit:      5  OSC32KCTRL APB Clock Enable        */
-    uint32_t SUPC_:1;          /*!< bit:      6  SUPC APB Clock Enable              */
-    uint32_t GCLK_:1;          /*!< bit:      7  GCLK APB Clock Enable              */
-    uint32_t WDT_:1;           /*!< bit:      8  WDT APB Clock Enable               */
-    uint32_t RTC_:1;           /*!< bit:      9  RTC APB Clock Enable               */
-    uint32_t EIC_:1;           /*!< bit:     10  EIC APB Clock Enable               */
-    uint32_t FREQM_:1;         /*!< bit:     11  FREQM APB Clock Enable             */
-    uint32_t SERCOM0_:1;       /*!< bit:     12  SERCOM0 APB Clock Enable           */
-    uint32_t SERCOM1_:1;       /*!< bit:     13  SERCOM1 APB Clock Enable           */
-    uint32_t TC0_:1;           /*!< bit:     14  TC0 APB Clock Enable               */
-    uint32_t TC1_:1;           /*!< bit:     15  TC1 APB Clock Enable               */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} MCLK_APBAMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_APBAMASK_OFFSET        0x14         /**< \brief (MCLK_APBAMASK offset) APBA Mask */
-#define MCLK_APBAMASK_RESETVALUE    _U_(0x000007FF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */
-
-#define MCLK_APBAMASK_PAC_Pos       0            /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */
-#define MCLK_APBAMASK_PAC           (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
-#define MCLK_APBAMASK_PM_Pos        1            /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */
-#define MCLK_APBAMASK_PM            (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
-#define MCLK_APBAMASK_MCLK_Pos      2            /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */
-#define MCLK_APBAMASK_MCLK          (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
-#define MCLK_APBAMASK_RSTC_Pos      3            /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */
-#define MCLK_APBAMASK_RSTC          (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
-#define MCLK_APBAMASK_OSCCTRL_Pos   4            /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */
-#define MCLK_APBAMASK_OSCCTRL       (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
-#define MCLK_APBAMASK_OSC32KCTRL_Pos 5            /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */
-#define MCLK_APBAMASK_OSC32KCTRL    (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
-#define MCLK_APBAMASK_SUPC_Pos      6            /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */
-#define MCLK_APBAMASK_SUPC          (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
-#define MCLK_APBAMASK_GCLK_Pos      7            /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */
-#define MCLK_APBAMASK_GCLK          (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
-#define MCLK_APBAMASK_WDT_Pos       8            /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */
-#define MCLK_APBAMASK_WDT           (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
-#define MCLK_APBAMASK_RTC_Pos       9            /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */
-#define MCLK_APBAMASK_RTC           (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
-#define MCLK_APBAMASK_EIC_Pos       10           /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */
-#define MCLK_APBAMASK_EIC           (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
-#define MCLK_APBAMASK_FREQM_Pos     11           /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */
-#define MCLK_APBAMASK_FREQM         (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
-#define MCLK_APBAMASK_SERCOM0_Pos   12           /**< \brief (MCLK_APBAMASK) SERCOM0 APB Clock Enable */
-#define MCLK_APBAMASK_SERCOM0       (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)
-#define MCLK_APBAMASK_SERCOM1_Pos   13           /**< \brief (MCLK_APBAMASK) SERCOM1 APB Clock Enable */
-#define MCLK_APBAMASK_SERCOM1       (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)
-#define MCLK_APBAMASK_TC0_Pos       14           /**< \brief (MCLK_APBAMASK) TC0 APB Clock Enable */
-#define MCLK_APBAMASK_TC0           (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)
-#define MCLK_APBAMASK_TC1_Pos       15           /**< \brief (MCLK_APBAMASK) TC1 APB Clock Enable */
-#define MCLK_APBAMASK_TC1           (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)
-#define MCLK_APBAMASK_MASK          _U_(0x0000FFFF) /**< \brief (MCLK_APBAMASK) MASK Register */
-
-/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t USB_:1;           /*!< bit:      0  USB APB Clock Enable               */
-    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
-    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t PORT_:1;          /*!< bit:      4  PORT APB Clock Enable              */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Clock Enable           */
-    uint32_t EVSYS_:1;         /*!< bit:      7  EVSYS APB Clock Enable             */
-    uint32_t :1;               /*!< bit:      8  Reserved                           */
-    uint32_t SERCOM2_:1;       /*!< bit:      9  SERCOM2 APB Clock Enable           */
-    uint32_t SERCOM3_:1;       /*!< bit:     10  SERCOM3 APB Clock Enable           */
-    uint32_t TCC0_:1;          /*!< bit:     11  TCC0 APB Clock Enable              */
-    uint32_t TCC1_:1;          /*!< bit:     12  TCC1 APB Clock Enable              */
-    uint32_t TC2_:1;           /*!< bit:     13  TC2 APB Clock Enable               */
-    uint32_t TC3_:1;           /*!< bit:     14  TC3 APB Clock Enable               */
-    uint32_t TAL_:1;           /*!< bit:     15  TAL APB Clock Enable               */
-    uint32_t RAMECC_:1;        /*!< bit:     16  RAMECC APB Clock Enable            */
-    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} MCLK_APBBMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_APBBMASK_OFFSET        0x18         /**< \brief (MCLK_APBBMASK offset) APBB Mask */
-#define MCLK_APBBMASK_RESETVALUE    _U_(0x00018056) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */
-
-#define MCLK_APBBMASK_USB_Pos       0            /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */
-#define MCLK_APBBMASK_USB           (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
-#define MCLK_APBBMASK_DSU_Pos       1            /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */
-#define MCLK_APBBMASK_DSU           (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
-#define MCLK_APBBMASK_NVMCTRL_Pos   2            /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */
-#define MCLK_APBBMASK_NVMCTRL       (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
-#define MCLK_APBBMASK_PORT_Pos      4            /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */
-#define MCLK_APBBMASK_PORT          (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
-#define MCLK_APBBMASK_HMATRIX_Pos   6            /**< \brief (MCLK_APBBMASK) HMATRIX APB Clock Enable */
-#define MCLK_APBBMASK_HMATRIX       (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)
-#define MCLK_APBBMASK_EVSYS_Pos     7            /**< \brief (MCLK_APBBMASK) EVSYS APB Clock Enable */
-#define MCLK_APBBMASK_EVSYS         (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)
-#define MCLK_APBBMASK_SERCOM2_Pos   9            /**< \brief (MCLK_APBBMASK) SERCOM2 APB Clock Enable */
-#define MCLK_APBBMASK_SERCOM2       (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)
-#define MCLK_APBBMASK_SERCOM3_Pos   10           /**< \brief (MCLK_APBBMASK) SERCOM3 APB Clock Enable */
-#define MCLK_APBBMASK_SERCOM3       (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)
-#define MCLK_APBBMASK_TCC0_Pos      11           /**< \brief (MCLK_APBBMASK) TCC0 APB Clock Enable */
-#define MCLK_APBBMASK_TCC0          (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)
-#define MCLK_APBBMASK_TCC1_Pos      12           /**< \brief (MCLK_APBBMASK) TCC1 APB Clock Enable */
-#define MCLK_APBBMASK_TCC1          (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)
-#define MCLK_APBBMASK_TC2_Pos       13           /**< \brief (MCLK_APBBMASK) TC2 APB Clock Enable */
-#define MCLK_APBBMASK_TC2           (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)
-#define MCLK_APBBMASK_TC3_Pos       14           /**< \brief (MCLK_APBBMASK) TC3 APB Clock Enable */
-#define MCLK_APBBMASK_TC3           (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)
-#define MCLK_APBBMASK_TAL_Pos       15           /**< \brief (MCLK_APBBMASK) TAL APB Clock Enable */
-#define MCLK_APBBMASK_TAL           (_U_(0x1) << MCLK_APBBMASK_TAL_Pos)
-#define MCLK_APBBMASK_RAMECC_Pos    16           /**< \brief (MCLK_APBBMASK) RAMECC APB Clock Enable */
-#define MCLK_APBBMASK_RAMECC        (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)
-#define MCLK_APBBMASK_MASK          _U_(0x0001FED7) /**< \brief (MCLK_APBBMASK) MASK Register */
-
-/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :3;               /*!< bit:  0.. 2  Reserved                           */
-    uint32_t TCC2_:1;          /*!< bit:      3  TCC2 APB Clock Enable              */
-    uint32_t TCC3_:1;          /*!< bit:      4  TCC3 APB Clock Enable              */
-    uint32_t TC4_:1;           /*!< bit:      5  TC4 APB Clock Enable               */
-    uint32_t TC5_:1;           /*!< bit:      6  TC5 APB Clock Enable               */
-    uint32_t PDEC_:1;          /*!< bit:      7  PDEC APB Clock Enable              */
-    uint32_t AC_:1;            /*!< bit:      8  AC APB Clock Enable                */
-    uint32_t AES_:1;           /*!< bit:      9  AES APB Clock Enable               */
-    uint32_t TRNG_:1;          /*!< bit:     10  TRNG APB Clock Enable              */
-    uint32_t ICM_:1;           /*!< bit:     11  ICM APB Clock Enable               */
-    uint32_t :1;               /*!< bit:     12  Reserved                           */
-    uint32_t QSPI_:1;          /*!< bit:     13  QSPI APB Clock Enable              */
-    uint32_t CCL_:1;           /*!< bit:     14  CCL APB Clock Enable               */
-    uint32_t :17;              /*!< bit: 15..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} MCLK_APBCMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_APBCMASK_OFFSET        0x1C         /**< \brief (MCLK_APBCMASK offset) APBC Mask */
-#define MCLK_APBCMASK_RESETVALUE    _U_(0x00002000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
-
-#define MCLK_APBCMASK_TCC2_Pos      3            /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
-#define MCLK_APBCMASK_TCC2          (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
-#define MCLK_APBCMASK_TCC3_Pos      4            /**< \brief (MCLK_APBCMASK) TCC3 APB Clock Enable */
-#define MCLK_APBCMASK_TCC3          (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)
-#define MCLK_APBCMASK_TC4_Pos       5            /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */
-#define MCLK_APBCMASK_TC4           (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
-#define MCLK_APBCMASK_TC5_Pos       6            /**< \brief (MCLK_APBCMASK) TC5 APB Clock Enable */
-#define MCLK_APBCMASK_TC5           (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)
-#define MCLK_APBCMASK_PDEC_Pos      7            /**< \brief (MCLK_APBCMASK) PDEC APB Clock Enable */
-#define MCLK_APBCMASK_PDEC          (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)
-#define MCLK_APBCMASK_AC_Pos        8            /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */
-#define MCLK_APBCMASK_AC            (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
-#define MCLK_APBCMASK_AES_Pos       9            /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */
-#define MCLK_APBCMASK_AES           (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
-#define MCLK_APBCMASK_TRNG_Pos      10           /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */
-#define MCLK_APBCMASK_TRNG          (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
-#define MCLK_APBCMASK_ICM_Pos       11           /**< \brief (MCLK_APBCMASK) ICM APB Clock Enable */
-#define MCLK_APBCMASK_ICM           (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)
-#define MCLK_APBCMASK_QSPI_Pos      13           /**< \brief (MCLK_APBCMASK) QSPI APB Clock Enable */
-#define MCLK_APBCMASK_QSPI          (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
-#define MCLK_APBCMASK_CCL_Pos       14           /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */
-#define MCLK_APBCMASK_CCL           (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
-#define MCLK_APBCMASK_MASK          _U_(0x00006FF8) /**< \brief (MCLK_APBCMASK) MASK Register */
-
-/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SERCOM4_:1;       /*!< bit:      0  SERCOM4 APB Clock Enable           */
-    uint32_t SERCOM5_:1;       /*!< bit:      1  SERCOM5 APB Clock Enable           */
-    uint32_t SERCOM6_:1;       /*!< bit:      2  SERCOM6 APB Clock Enable           */
-    uint32_t SERCOM7_:1;       /*!< bit:      3  SERCOM7 APB Clock Enable           */
-    uint32_t TCC4_:1;          /*!< bit:      4  TCC4 APB Clock Enable              */
-    uint32_t TC6_:1;           /*!< bit:      5  TC6 APB Clock Enable               */
-    uint32_t TC7_:1;           /*!< bit:      6  TC7 APB Clock Enable               */
-    uint32_t ADC0_:1;          /*!< bit:      7  ADC0 APB Clock Enable              */
-    uint32_t ADC1_:1;          /*!< bit:      8  ADC1 APB Clock Enable              */
-    uint32_t DAC_:1;           /*!< bit:      9  DAC APB Clock Enable               */
-    uint32_t I2S_:1;           /*!< bit:     10  I2S APB Clock Enable               */
-    uint32_t PCC_:1;           /*!< bit:     11  PCC APB Clock Enable               */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} MCLK_APBDMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define MCLK_APBDMASK_OFFSET        0x20         /**< \brief (MCLK_APBDMASK offset) APBD Mask */
-#define MCLK_APBDMASK_RESETVALUE    _U_(0x00000000) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */
-
-#define MCLK_APBDMASK_SERCOM4_Pos   0            /**< \brief (MCLK_APBDMASK) SERCOM4 APB Clock Enable */
-#define MCLK_APBDMASK_SERCOM4       (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)
-#define MCLK_APBDMASK_SERCOM5_Pos   1            /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */
-#define MCLK_APBDMASK_SERCOM5       (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
-#define MCLK_APBDMASK_SERCOM6_Pos   2            /**< \brief (MCLK_APBDMASK) SERCOM6 APB Clock Enable */
-#define MCLK_APBDMASK_SERCOM6       (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)
-#define MCLK_APBDMASK_SERCOM7_Pos   3            /**< \brief (MCLK_APBDMASK) SERCOM7 APB Clock Enable */
-#define MCLK_APBDMASK_SERCOM7       (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)
-#define MCLK_APBDMASK_TCC4_Pos      4            /**< \brief (MCLK_APBDMASK) TCC4 APB Clock Enable */
-#define MCLK_APBDMASK_TCC4          (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)
-#define MCLK_APBDMASK_TC6_Pos       5            /**< \brief (MCLK_APBDMASK) TC6 APB Clock Enable */
-#define MCLK_APBDMASK_TC6           (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)
-#define MCLK_APBDMASK_TC7_Pos       6            /**< \brief (MCLK_APBDMASK) TC7 APB Clock Enable */
-#define MCLK_APBDMASK_TC7           (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)
-#define MCLK_APBDMASK_ADC0_Pos      7            /**< \brief (MCLK_APBDMASK) ADC0 APB Clock Enable */
-#define MCLK_APBDMASK_ADC0          (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)
-#define MCLK_APBDMASK_ADC1_Pos      8            /**< \brief (MCLK_APBDMASK) ADC1 APB Clock Enable */
-#define MCLK_APBDMASK_ADC1          (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)
-#define MCLK_APBDMASK_DAC_Pos       9            /**< \brief (MCLK_APBDMASK) DAC APB Clock Enable */
-#define MCLK_APBDMASK_DAC           (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)
-#define MCLK_APBDMASK_I2S_Pos       10           /**< \brief (MCLK_APBDMASK) I2S APB Clock Enable */
-#define MCLK_APBDMASK_I2S           (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)
-#define MCLK_APBDMASK_PCC_Pos       11           /**< \brief (MCLK_APBDMASK) PCC APB Clock Enable */
-#define MCLK_APBDMASK_PCC           (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)
-#define MCLK_APBDMASK_MASK          _U_(0x00000FFF) /**< \brief (MCLK_APBDMASK) MASK Register */
-
-/** \brief MCLK hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-       RoReg8                    Reserved1[0x1];
-  __IO MCLK_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x01 (R/W  8) Interrupt Enable Clear */
-  __IO MCLK_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x02 (R/W  8) Interrupt Enable Set */
-  __IO MCLK_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x03 (R/W  8) Interrupt Flag Status and Clear */
-  __I  MCLK_HSDIV_Type           HSDIV;       /**< \brief Offset: 0x04 (R/   8) HS Clock Division */
-  __IO MCLK_CPUDIV_Type          CPUDIV;      /**< \brief Offset: 0x05 (R/W  8) CPU Clock Division */
-       RoReg8                    Reserved2[0xA];
-  __IO MCLK_AHBMASK_Type         AHBMASK;     /**< \brief Offset: 0x10 (R/W 32) AHB Mask */
-  __IO MCLK_APBAMASK_Type        APBAMASK;    /**< \brief Offset: 0x14 (R/W 32) APBA Mask */
-  __IO MCLK_APBBMASK_Type        APBBMASK;    /**< \brief Offset: 0x18 (R/W 32) APBB Mask */
-  __IO MCLK_APBCMASK_Type        APBCMASK;    /**< \brief Offset: 0x1C (R/W 32) APBC Mask */
-  __IO MCLK_APBDMASK_Type        APBDMASK;    /**< \brief Offset: 0x20 (R/W 32) APBD Mask */
-} Mclk;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_MCLK_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/nvmctrl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/nvmctrl.h
deleted file mode 100644
index 50f95f5d04..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/nvmctrl.h
+++ /dev/null
@@ -1,861 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for NVMCTRL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_NVMCTRL_COMPONENT_
-#define _SAMD51_NVMCTRL_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR NVMCTRL */
-/* ========================================================================== */
-/** \addtogroup SAMD51_NVMCTRL Non-Volatile Memory Controller */
-/*@{*/
-
-#define NVMCTRL_U2409
-#define REV_NVMCTRL                 0x100
-
-/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t AUTOWS:1;         /*!< bit:      2  Auto Wait State Enable             */
-    uint16_t SUSPEN:1;         /*!< bit:      3  Suspend Enable                     */
-    uint16_t WMODE:2;          /*!< bit:  4.. 5  Write Mode                         */
-    uint16_t PRM:2;            /*!< bit:  6.. 7  Power Reduction Mode during Sleep  */
-    uint16_t RWS:4;            /*!< bit:  8..11  NVM Read Wait States               */
-    uint16_t AHBNS0:1;         /*!< bit:     12  Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */
-    uint16_t AHBNS1:1;         /*!< bit:     13  Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */
-    uint16_t CACHEDIS0:1;      /*!< bit:     14  AHB0 Cache Disable                 */
-    uint16_t CACHEDIS1:1;      /*!< bit:     15  AHB1 Cache Disable                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
-#define NVMCTRL_CTRLA_RESETVALUE    _U_(0x0004)  /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
-
-#define NVMCTRL_CTRLA_AUTOWS_Pos    2            /**< \brief (NVMCTRL_CTRLA) Auto Wait State Enable */
-#define NVMCTRL_CTRLA_AUTOWS        (_U_(0x1) << NVMCTRL_CTRLA_AUTOWS_Pos)
-#define NVMCTRL_CTRLA_SUSPEN_Pos    3            /**< \brief (NVMCTRL_CTRLA) Suspend Enable */
-#define NVMCTRL_CTRLA_SUSPEN        (_U_(0x1) << NVMCTRL_CTRLA_SUSPEN_Pos)
-#define NVMCTRL_CTRLA_WMODE_Pos     4            /**< \brief (NVMCTRL_CTRLA) Write Mode */
-#define NVMCTRL_CTRLA_WMODE_Msk     (_U_(0x3) << NVMCTRL_CTRLA_WMODE_Pos)
-#define NVMCTRL_CTRLA_WMODE(value)  (NVMCTRL_CTRLA_WMODE_Msk & ((value) << NVMCTRL_CTRLA_WMODE_Pos))
-#define   NVMCTRL_CTRLA_WMODE_MAN_Val     _U_(0x0)   /**< \brief (NVMCTRL_CTRLA) Manual Write */
-#define   NVMCTRL_CTRLA_WMODE_ADW_Val     _U_(0x1)   /**< \brief (NVMCTRL_CTRLA) Automatic Double Word Write */
-#define   NVMCTRL_CTRLA_WMODE_AQW_Val     _U_(0x2)   /**< \brief (NVMCTRL_CTRLA) Automatic Quad Word */
-#define   NVMCTRL_CTRLA_WMODE_AP_Val      _U_(0x3)   /**< \brief (NVMCTRL_CTRLA) Automatic Page Write */
-#define NVMCTRL_CTRLA_WMODE_MAN     (NVMCTRL_CTRLA_WMODE_MAN_Val   << NVMCTRL_CTRLA_WMODE_Pos)
-#define NVMCTRL_CTRLA_WMODE_ADW     (NVMCTRL_CTRLA_WMODE_ADW_Val   << NVMCTRL_CTRLA_WMODE_Pos)
-#define NVMCTRL_CTRLA_WMODE_AQW     (NVMCTRL_CTRLA_WMODE_AQW_Val   << NVMCTRL_CTRLA_WMODE_Pos)
-#define NVMCTRL_CTRLA_WMODE_AP      (NVMCTRL_CTRLA_WMODE_AP_Val    << NVMCTRL_CTRLA_WMODE_Pos)
-#define NVMCTRL_CTRLA_PRM_Pos       6            /**< \brief (NVMCTRL_CTRLA) Power Reduction Mode during Sleep */
-#define NVMCTRL_CTRLA_PRM_Msk       (_U_(0x3) << NVMCTRL_CTRLA_PRM_Pos)
-#define NVMCTRL_CTRLA_PRM(value)    (NVMCTRL_CTRLA_PRM_Msk & ((value) << NVMCTRL_CTRLA_PRM_Pos))
-#define   NVMCTRL_CTRLA_PRM_SEMIAUTO_Val  _U_(0x0)   /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
-#define   NVMCTRL_CTRLA_PRM_FULLAUTO_Val  _U_(0x1)   /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. */
-#define   NVMCTRL_CTRLA_PRM_MANUAL_Val    _U_(0x3)   /**< \brief (NVMCTRL_CTRLA) NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
-#define NVMCTRL_CTRLA_PRM_SEMIAUTO  (NVMCTRL_CTRLA_PRM_SEMIAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
-#define NVMCTRL_CTRLA_PRM_FULLAUTO  (NVMCTRL_CTRLA_PRM_FULLAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
-#define NVMCTRL_CTRLA_PRM_MANUAL    (NVMCTRL_CTRLA_PRM_MANUAL_Val  << NVMCTRL_CTRLA_PRM_Pos)
-#define NVMCTRL_CTRLA_RWS_Pos       8            /**< \brief (NVMCTRL_CTRLA) NVM Read Wait States */
-#define NVMCTRL_CTRLA_RWS_Msk       (_U_(0xF) << NVMCTRL_CTRLA_RWS_Pos)
-#define NVMCTRL_CTRLA_RWS(value)    (NVMCTRL_CTRLA_RWS_Msk & ((value) << NVMCTRL_CTRLA_RWS_Pos))
-#define NVMCTRL_CTRLA_AHBNS0_Pos    12           /**< \brief (NVMCTRL_CTRLA) Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */
-#define NVMCTRL_CTRLA_AHBNS0        (_U_(0x1) << NVMCTRL_CTRLA_AHBNS0_Pos)
-#define NVMCTRL_CTRLA_AHBNS1_Pos    13           /**< \brief (NVMCTRL_CTRLA) Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */
-#define NVMCTRL_CTRLA_AHBNS1        (_U_(0x1) << NVMCTRL_CTRLA_AHBNS1_Pos)
-#define NVMCTRL_CTRLA_CACHEDIS0_Pos 14           /**< \brief (NVMCTRL_CTRLA) AHB0 Cache Disable */
-#define NVMCTRL_CTRLA_CACHEDIS0     (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS0_Pos)
-#define NVMCTRL_CTRLA_CACHEDIS1_Pos 15           /**< \brief (NVMCTRL_CTRLA) AHB1 Cache Disable */
-#define NVMCTRL_CTRLA_CACHEDIS1     (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS1_Pos)
-#define NVMCTRL_CTRLA_MASK          _U_(0xFFFC)  /**< \brief (NVMCTRL_CTRLA) MASK Register */
-
-/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) ( /W 16) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
-    uint16_t :1;               /*!< bit:      7  Reserved                           */
-    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
-#define NVMCTRL_CTRLB_RESETVALUE    _U_(0x0000)  /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
-
-#define NVMCTRL_CTRLB_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLB) Command */
-#define NVMCTRL_CTRLB_CMD_Msk       (_U_(0x7F) << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD(value)    (NVMCTRL_CTRLB_CMD_Msk & ((value) << NVMCTRL_CTRLB_CMD_Pos))
-#define   NVMCTRL_CTRLB_CMD_EP_Val        _U_(0x0)   /**< \brief (NVMCTRL_CTRLB) Erase Page - Only supported in the USER and AUX pages. */
-#define   NVMCTRL_CTRLB_CMD_EB_Val        _U_(0x1)   /**< \brief (NVMCTRL_CTRLB) Erase Block - Erases the block addressed by the ADDR register, not supported in the user page */
-#define   NVMCTRL_CTRLB_CMD_WP_Val        _U_(0x3)   /**< \brief (NVMCTRL_CTRLB) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page */
-#define   NVMCTRL_CTRLB_CMD_WQW_Val       _U_(0x4)   /**< \brief (NVMCTRL_CTRLB) Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. */
-#define   NVMCTRL_CTRLB_CMD_SWRST_Val     _U_(0x10)   /**< \brief (NVMCTRL_CTRLB) Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers */
-#define   NVMCTRL_CTRLB_CMD_LR_Val        _U_(0x11)   /**< \brief (NVMCTRL_CTRLB) Lock Region - Locks the region containing the address location in the ADDR register. */
-#define   NVMCTRL_CTRLB_CMD_UR_Val        _U_(0x12)   /**< \brief (NVMCTRL_CTRLB) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
-#define   NVMCTRL_CTRLB_CMD_SPRM_Val      _U_(0x13)   /**< \brief (NVMCTRL_CTRLB) Sets the power reduction mode. */
-#define   NVMCTRL_CTRLB_CMD_CPRM_Val      _U_(0x14)   /**< \brief (NVMCTRL_CTRLB) Clears the power reduction mode. */
-#define   NVMCTRL_CTRLB_CMD_PBC_Val       _U_(0x15)   /**< \brief (NVMCTRL_CTRLB) Page Buffer Clear - Clears the page buffer. */
-#define   NVMCTRL_CTRLB_CMD_SSB_Val       _U_(0x16)   /**< \brief (NVMCTRL_CTRLB) Set Security Bit */
-#define   NVMCTRL_CTRLB_CMD_BKSWRST_Val   _U_(0x17)   /**< \brief (NVMCTRL_CTRLB) Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK */
-#define   NVMCTRL_CTRLB_CMD_CELCK_Val     _U_(0x18)   /**< \brief (NVMCTRL_CTRLB) Chip Erase Lock - DSU.CE command is not available */
-#define   NVMCTRL_CTRLB_CMD_CEULCK_Val    _U_(0x19)   /**< \brief (NVMCTRL_CTRLB) Chip Erase Unlock - DSU.CE command is available */
-#define   NVMCTRL_CTRLB_CMD_SBPDIS_Val    _U_(0x1A)   /**< \brief (NVMCTRL_CTRLB) Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence */
-#define   NVMCTRL_CTRLB_CMD_CBPDIS_Val    _U_(0x1B)   /**< \brief (NVMCTRL_CTRLB) Clears STATUS.BPDIS, Boot loader protection is not discarded */
-#define   NVMCTRL_CTRLB_CMD_ASEES0_Val    _U_(0x30)   /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 0, deactivate Sector 1 */
-#define   NVMCTRL_CTRLB_CMD_ASEES1_Val    _U_(0x31)   /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 1, deactivate Sector 0 */
-#define   NVMCTRL_CTRLB_CMD_SEERALOC_Val  _U_(0x32)   /**< \brief (NVMCTRL_CTRLB) Starts SmartEEPROM sector reallocation algorithm */
-#define   NVMCTRL_CTRLB_CMD_SEEFLUSH_Val  _U_(0x33)   /**< \brief (NVMCTRL_CTRLB) Flush SMEE data when in buffered mode */
-#define   NVMCTRL_CTRLB_CMD_LSEE_Val      _U_(0x34)   /**< \brief (NVMCTRL_CTRLB) Lock access to SmartEEPROM data from any mean */
-#define   NVMCTRL_CTRLB_CMD_USEE_Val      _U_(0x35)   /**< \brief (NVMCTRL_CTRLB) Unlock access to SmartEEPROM data */
-#define   NVMCTRL_CTRLB_CMD_LSEER_Val     _U_(0x36)   /**< \brief (NVMCTRL_CTRLB) Lock access to the SmartEEPROM Register Address Space (above 64KB) */
-#define   NVMCTRL_CTRLB_CMD_USEER_Val     _U_(0x37)   /**< \brief (NVMCTRL_CTRLB) Unlock access to the SmartEEPROM Register Address Space (above 64KB) */
-#define NVMCTRL_CTRLB_CMD_EP        (NVMCTRL_CTRLB_CMD_EP_Val      << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_EB        (NVMCTRL_CTRLB_CMD_EB_Val      << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_WP        (NVMCTRL_CTRLB_CMD_WP_Val      << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_WQW       (NVMCTRL_CTRLB_CMD_WQW_Val     << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_SWRST     (NVMCTRL_CTRLB_CMD_SWRST_Val   << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_LR        (NVMCTRL_CTRLB_CMD_LR_Val      << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_UR        (NVMCTRL_CTRLB_CMD_UR_Val      << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_SPRM      (NVMCTRL_CTRLB_CMD_SPRM_Val    << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_CPRM      (NVMCTRL_CTRLB_CMD_CPRM_Val    << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_PBC       (NVMCTRL_CTRLB_CMD_PBC_Val     << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_SSB       (NVMCTRL_CTRLB_CMD_SSB_Val     << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_BKSWRST   (NVMCTRL_CTRLB_CMD_BKSWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_CELCK     (NVMCTRL_CTRLB_CMD_CELCK_Val   << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_CEULCK    (NVMCTRL_CTRLB_CMD_CEULCK_Val  << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_SBPDIS    (NVMCTRL_CTRLB_CMD_SBPDIS_Val  << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_CBPDIS    (NVMCTRL_CTRLB_CMD_CBPDIS_Val  << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_ASEES0    (NVMCTRL_CTRLB_CMD_ASEES0_Val  << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_ASEES1    (NVMCTRL_CTRLB_CMD_ASEES1_Val  << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_SEERALOC  (NVMCTRL_CTRLB_CMD_SEERALOC_Val << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_SEEFLUSH  (NVMCTRL_CTRLB_CMD_SEEFLUSH_Val << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_LSEE      (NVMCTRL_CTRLB_CMD_LSEE_Val    << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_USEE      (NVMCTRL_CTRLB_CMD_USEE_Val    << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_LSEER     (NVMCTRL_CTRLB_CMD_LSEER_Val   << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMD_USEER     (NVMCTRL_CTRLB_CMD_USEER_Val   << NVMCTRL_CTRLB_CMD_Pos)
-#define NVMCTRL_CTRLB_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLB) Command Execution */
-#define NVMCTRL_CTRLB_CMDEX_Msk     (_U_(0xFF) << NVMCTRL_CTRLB_CMDEX_Pos)
-#define NVMCTRL_CTRLB_CMDEX(value)  (NVMCTRL_CTRLB_CMDEX_Msk & ((value) << NVMCTRL_CTRLB_CMDEX_Pos))
-#define   NVMCTRL_CTRLB_CMDEX_KEY_Val     _U_(0xA5)   /**< \brief (NVMCTRL_CTRLB) Execution Key */
-#define NVMCTRL_CTRLB_CMDEX_KEY     (NVMCTRL_CTRLB_CMDEX_KEY_Val   << NVMCTRL_CTRLB_CMDEX_Pos)
-#define NVMCTRL_CTRLB_MASK          _U_(0xFF7F)  /**< \brief (NVMCTRL_CTRLB) MASK Register */
-
-/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/  32) NVM Parameter -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
-    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
-    uint32_t :12;              /*!< bit: 19..30  Reserved                           */
-    uint32_t SEE:1;            /*!< bit:     31  SmartEEPROM Supported              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_PARAM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
-#define NVMCTRL_PARAM_RESETVALUE    _U_(0x00060000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
-
-#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
-#define NVMCTRL_PARAM_NVMP_Msk      (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
-#define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
-#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
-#define NVMCTRL_PARAM_PSZ_Msk       (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
-#define   NVMCTRL_PARAM_PSZ_8_Val         _U_(0x0)   /**< \brief (NVMCTRL_PARAM) 8 bytes */
-#define   NVMCTRL_PARAM_PSZ_16_Val        _U_(0x1)   /**< \brief (NVMCTRL_PARAM) 16 bytes */
-#define   NVMCTRL_PARAM_PSZ_32_Val        _U_(0x2)   /**< \brief (NVMCTRL_PARAM) 32 bytes */
-#define   NVMCTRL_PARAM_PSZ_64_Val        _U_(0x3)   /**< \brief (NVMCTRL_PARAM) 64 bytes */
-#define   NVMCTRL_PARAM_PSZ_128_Val       _U_(0x4)   /**< \brief (NVMCTRL_PARAM) 128 bytes */
-#define   NVMCTRL_PARAM_PSZ_256_Val       _U_(0x5)   /**< \brief (NVMCTRL_PARAM) 256 bytes */
-#define   NVMCTRL_PARAM_PSZ_512_Val       _U_(0x6)   /**< \brief (NVMCTRL_PARAM) 512 bytes */
-#define   NVMCTRL_PARAM_PSZ_1024_Val      _U_(0x7)   /**< \brief (NVMCTRL_PARAM) 1024 bytes */
-#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
-#define NVMCTRL_PARAM_SEE_Pos       31           /**< \brief (NVMCTRL_PARAM) SmartEEPROM Supported */
-#define NVMCTRL_PARAM_SEE           (_U_(0x1) << NVMCTRL_PARAM_SEE_Pos)
-#define NVMCTRL_PARAM_MASK          _U_(0x8007FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */
-
-/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DONE:1;           /*!< bit:      0  Command Done Interrupt Clear       */
-    uint16_t ADDRE:1;          /*!< bit:      1  Address Error                      */
-    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Interrupt Clear  */
-    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Interrupt Clear         */
-    uint16_t ECCSE:1;          /*!< bit:      4  ECC Single Error Interrupt Clear   */
-    uint16_t ECCDE:1;          /*!< bit:      5  ECC Dual Error Interrupt Clear     */
-    uint16_t NVME:1;           /*!< bit:      6  NVM Error Interrupt Clear          */
-    uint16_t SUSP:1;           /*!< bit:      7  Suspended Write Or Erase Interrupt Clear */
-    uint16_t SEESFULL:1;       /*!< bit:      8  Active SEES Full Interrupt Clear   */
-    uint16_t SEESOVF:1;        /*!< bit:      9  Active SEES Overflow Interrupt Clear */
-    uint16_t SEEWRC:1;         /*!< bit:     10  SEE Write Completed Interrupt Clear */
-    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
-#define NVMCTRL_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define NVMCTRL_INTENCLR_DONE_Pos   0            /**< \brief (NVMCTRL_INTENCLR) Command Done Interrupt Clear */
-#define NVMCTRL_INTENCLR_DONE       (_U_(0x1) << NVMCTRL_INTENCLR_DONE_Pos)
-#define NVMCTRL_INTENCLR_ADDRE_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Address Error */
-#define NVMCTRL_INTENCLR_ADDRE      (_U_(0x1) << NVMCTRL_INTENCLR_ADDRE_Pos)
-#define NVMCTRL_INTENCLR_PROGE_Pos  2            /**< \brief (NVMCTRL_INTENCLR) Programming Error Interrupt Clear */
-#define NVMCTRL_INTENCLR_PROGE      (_U_(0x1) << NVMCTRL_INTENCLR_PROGE_Pos)
-#define NVMCTRL_INTENCLR_LOCKE_Pos  3            /**< \brief (NVMCTRL_INTENCLR) Lock Error Interrupt Clear */
-#define NVMCTRL_INTENCLR_LOCKE      (_U_(0x1) << NVMCTRL_INTENCLR_LOCKE_Pos)
-#define NVMCTRL_INTENCLR_ECCSE_Pos  4            /**< \brief (NVMCTRL_INTENCLR) ECC Single Error Interrupt Clear */
-#define NVMCTRL_INTENCLR_ECCSE      (_U_(0x1) << NVMCTRL_INTENCLR_ECCSE_Pos)
-#define NVMCTRL_INTENCLR_ECCDE_Pos  5            /**< \brief (NVMCTRL_INTENCLR) ECC Dual Error Interrupt Clear */
-#define NVMCTRL_INTENCLR_ECCDE      (_U_(0x1) << NVMCTRL_INTENCLR_ECCDE_Pos)
-#define NVMCTRL_INTENCLR_NVME_Pos   6            /**< \brief (NVMCTRL_INTENCLR) NVM Error Interrupt Clear */
-#define NVMCTRL_INTENCLR_NVME       (_U_(0x1) << NVMCTRL_INTENCLR_NVME_Pos)
-#define NVMCTRL_INTENCLR_SUSP_Pos   7            /**< \brief (NVMCTRL_INTENCLR) Suspended Write Or Erase Interrupt Clear */
-#define NVMCTRL_INTENCLR_SUSP       (_U_(0x1) << NVMCTRL_INTENCLR_SUSP_Pos)
-#define NVMCTRL_INTENCLR_SEESFULL_Pos 8            /**< \brief (NVMCTRL_INTENCLR) Active SEES Full Interrupt Clear */
-#define NVMCTRL_INTENCLR_SEESFULL   (_U_(0x1) << NVMCTRL_INTENCLR_SEESFULL_Pos)
-#define NVMCTRL_INTENCLR_SEESOVF_Pos 9            /**< \brief (NVMCTRL_INTENCLR) Active SEES Overflow Interrupt Clear */
-#define NVMCTRL_INTENCLR_SEESOVF    (_U_(0x1) << NVMCTRL_INTENCLR_SEESOVF_Pos)
-#define NVMCTRL_INTENCLR_SEEWRC_Pos 10           /**< \brief (NVMCTRL_INTENCLR) SEE Write Completed Interrupt Clear */
-#define NVMCTRL_INTENCLR_SEEWRC     (_U_(0x1) << NVMCTRL_INTENCLR_SEEWRC_Pos)
-#define NVMCTRL_INTENCLR_MASK       _U_(0x07FF)  /**< \brief (NVMCTRL_INTENCLR) MASK Register */
-
-/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x0E) (R/W 16) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DONE:1;           /*!< bit:      0  Command Done Interrupt Enable      */
-    uint16_t ADDRE:1;          /*!< bit:      1  Address Error Interrupt Enable     */
-    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Interrupt Enable */
-    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Interrupt Enable        */
-    uint16_t ECCSE:1;          /*!< bit:      4  ECC Single Error Interrupt Enable  */
-    uint16_t ECCDE:1;          /*!< bit:      5  ECC Dual Error Interrupt Enable    */
-    uint16_t NVME:1;           /*!< bit:      6  NVM Error Interrupt Enable         */
-    uint16_t SUSP:1;           /*!< bit:      7  Suspended Write Or Erase  Interrupt Enable */
-    uint16_t SEESFULL:1;       /*!< bit:      8  Active SEES Full Interrupt Enable  */
-    uint16_t SEESOVF:1;        /*!< bit:      9  Active SEES Overflow Interrupt Enable */
-    uint16_t SEEWRC:1;         /*!< bit:     10  SEE Write Completed Interrupt Enable */
-    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_INTENSET_OFFSET     0x0E         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
-#define NVMCTRL_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
-
-#define NVMCTRL_INTENSET_DONE_Pos   0            /**< \brief (NVMCTRL_INTENSET) Command Done Interrupt Enable */
-#define NVMCTRL_INTENSET_DONE       (_U_(0x1) << NVMCTRL_INTENSET_DONE_Pos)
-#define NVMCTRL_INTENSET_ADDRE_Pos  1            /**< \brief (NVMCTRL_INTENSET) Address Error Interrupt Enable */
-#define NVMCTRL_INTENSET_ADDRE      (_U_(0x1) << NVMCTRL_INTENSET_ADDRE_Pos)
-#define NVMCTRL_INTENSET_PROGE_Pos  2            /**< \brief (NVMCTRL_INTENSET) Programming Error Interrupt Enable */
-#define NVMCTRL_INTENSET_PROGE      (_U_(0x1) << NVMCTRL_INTENSET_PROGE_Pos)
-#define NVMCTRL_INTENSET_LOCKE_Pos  3            /**< \brief (NVMCTRL_INTENSET) Lock Error Interrupt Enable */
-#define NVMCTRL_INTENSET_LOCKE      (_U_(0x1) << NVMCTRL_INTENSET_LOCKE_Pos)
-#define NVMCTRL_INTENSET_ECCSE_Pos  4            /**< \brief (NVMCTRL_INTENSET) ECC Single Error Interrupt Enable */
-#define NVMCTRL_INTENSET_ECCSE      (_U_(0x1) << NVMCTRL_INTENSET_ECCSE_Pos)
-#define NVMCTRL_INTENSET_ECCDE_Pos  5            /**< \brief (NVMCTRL_INTENSET) ECC Dual Error Interrupt Enable */
-#define NVMCTRL_INTENSET_ECCDE      (_U_(0x1) << NVMCTRL_INTENSET_ECCDE_Pos)
-#define NVMCTRL_INTENSET_NVME_Pos   6            /**< \brief (NVMCTRL_INTENSET) NVM Error Interrupt Enable */
-#define NVMCTRL_INTENSET_NVME       (_U_(0x1) << NVMCTRL_INTENSET_NVME_Pos)
-#define NVMCTRL_INTENSET_SUSP_Pos   7            /**< \brief (NVMCTRL_INTENSET) Suspended Write Or Erase  Interrupt Enable */
-#define NVMCTRL_INTENSET_SUSP       (_U_(0x1) << NVMCTRL_INTENSET_SUSP_Pos)
-#define NVMCTRL_INTENSET_SEESFULL_Pos 8            /**< \brief (NVMCTRL_INTENSET) Active SEES Full Interrupt Enable */
-#define NVMCTRL_INTENSET_SEESFULL   (_U_(0x1) << NVMCTRL_INTENSET_SEESFULL_Pos)
-#define NVMCTRL_INTENSET_SEESOVF_Pos 9            /**< \brief (NVMCTRL_INTENSET) Active SEES Overflow Interrupt Enable */
-#define NVMCTRL_INTENSET_SEESOVF    (_U_(0x1) << NVMCTRL_INTENSET_SEESOVF_Pos)
-#define NVMCTRL_INTENSET_SEEWRC_Pos 10           /**< \brief (NVMCTRL_INTENSET) SEE Write Completed Interrupt Enable */
-#define NVMCTRL_INTENSET_SEEWRC     (_U_(0x1) << NVMCTRL_INTENSET_SEEWRC_Pos)
-#define NVMCTRL_INTENSET_MASK       _U_(0x07FF)  /**< \brief (NVMCTRL_INTENSET) MASK Register */
-
-/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x10) (R/W 16) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t DONE:1;           /*!< bit:      0  Command Done                       */
-    __I uint16_t ADDRE:1;          /*!< bit:      1  Address Error                      */
-    __I uint16_t PROGE:1;          /*!< bit:      2  Programming Error                  */
-    __I uint16_t LOCKE:1;          /*!< bit:      3  Lock Error                         */
-    __I uint16_t ECCSE:1;          /*!< bit:      4  ECC Single Error                   */
-    __I uint16_t ECCDE:1;          /*!< bit:      5  ECC Dual Error                     */
-    __I uint16_t NVME:1;           /*!< bit:      6  NVM Error                          */
-    __I uint16_t SUSP:1;           /*!< bit:      7  Suspended Write Or Erase Operation */
-    __I uint16_t SEESFULL:1;       /*!< bit:      8  Active SEES Full                   */
-    __I uint16_t SEESOVF:1;        /*!< bit:      9  Active SEES Overflow               */
-    __I uint16_t SEEWRC:1;         /*!< bit:     10  SEE Write Completed                */
-    __I uint16_t :5;               /*!< bit: 11..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_INTFLAG_OFFSET      0x10         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define NVMCTRL_INTFLAG_RESETVALUE  _U_(0x0000)  /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define NVMCTRL_INTFLAG_DONE_Pos    0            /**< \brief (NVMCTRL_INTFLAG) Command Done */
-#define NVMCTRL_INTFLAG_DONE        (_U_(0x1) << NVMCTRL_INTFLAG_DONE_Pos)
-#define NVMCTRL_INTFLAG_ADDRE_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Address Error */
-#define NVMCTRL_INTFLAG_ADDRE       (_U_(0x1) << NVMCTRL_INTFLAG_ADDRE_Pos)
-#define NVMCTRL_INTFLAG_PROGE_Pos   2            /**< \brief (NVMCTRL_INTFLAG) Programming Error */
-#define NVMCTRL_INTFLAG_PROGE       (_U_(0x1) << NVMCTRL_INTFLAG_PROGE_Pos)
-#define NVMCTRL_INTFLAG_LOCKE_Pos   3            /**< \brief (NVMCTRL_INTFLAG) Lock Error */
-#define NVMCTRL_INTFLAG_LOCKE       (_U_(0x1) << NVMCTRL_INTFLAG_LOCKE_Pos)
-#define NVMCTRL_INTFLAG_ECCSE_Pos   4            /**< \brief (NVMCTRL_INTFLAG) ECC Single Error */
-#define NVMCTRL_INTFLAG_ECCSE       (_U_(0x1) << NVMCTRL_INTFLAG_ECCSE_Pos)
-#define NVMCTRL_INTFLAG_ECCDE_Pos   5            /**< \brief (NVMCTRL_INTFLAG) ECC Dual Error */
-#define NVMCTRL_INTFLAG_ECCDE       (_U_(0x1) << NVMCTRL_INTFLAG_ECCDE_Pos)
-#define NVMCTRL_INTFLAG_NVME_Pos    6            /**< \brief (NVMCTRL_INTFLAG) NVM Error */
-#define NVMCTRL_INTFLAG_NVME        (_U_(0x1) << NVMCTRL_INTFLAG_NVME_Pos)
-#define NVMCTRL_INTFLAG_SUSP_Pos    7            /**< \brief (NVMCTRL_INTFLAG) Suspended Write Or Erase Operation */
-#define NVMCTRL_INTFLAG_SUSP        (_U_(0x1) << NVMCTRL_INTFLAG_SUSP_Pos)
-#define NVMCTRL_INTFLAG_SEESFULL_Pos 8            /**< \brief (NVMCTRL_INTFLAG) Active SEES Full */
-#define NVMCTRL_INTFLAG_SEESFULL    (_U_(0x1) << NVMCTRL_INTFLAG_SEESFULL_Pos)
-#define NVMCTRL_INTFLAG_SEESOVF_Pos 9            /**< \brief (NVMCTRL_INTFLAG) Active SEES Overflow */
-#define NVMCTRL_INTFLAG_SEESOVF     (_U_(0x1) << NVMCTRL_INTFLAG_SEESOVF_Pos)
-#define NVMCTRL_INTFLAG_SEEWRC_Pos  10           /**< \brief (NVMCTRL_INTFLAG) SEE Write Completed */
-#define NVMCTRL_INTFLAG_SEEWRC      (_U_(0x1) << NVMCTRL_INTFLAG_SEEWRC_Pos)
-#define NVMCTRL_INTFLAG_MASK        _U_(0x07FF)  /**< \brief (NVMCTRL_INTFLAG) MASK Register */
-
-/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) (R/  16) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t READY:1;          /*!< bit:      0  Ready to accept a command          */
-    uint16_t PRM:1;            /*!< bit:      1  Power Reduction Mode               */
-    uint16_t LOAD:1;           /*!< bit:      2  NVM Page Buffer Active Loading     */
-    uint16_t SUSP:1;           /*!< bit:      3  NVM Write Or Erase Operation Is Suspended */
-    uint16_t AFIRST:1;         /*!< bit:      4  BANKA First                        */
-    uint16_t BPDIS:1;          /*!< bit:      5  Boot Loader Protection Disable     */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t BOOTPROT:4;       /*!< bit:  8..11  Boot Loader Protection Size        */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_STATUS_OFFSET       0x12         /**< \brief (NVMCTRL_STATUS offset) Status */
-#define NVMCTRL_STATUS_RESETVALUE   _U_(0x0000)  /**< \brief (NVMCTRL_STATUS reset_value) Status */
-
-#define NVMCTRL_STATUS_READY_Pos    0            /**< \brief (NVMCTRL_STATUS) Ready to accept a command */
-#define NVMCTRL_STATUS_READY        (_U_(0x1) << NVMCTRL_STATUS_READY_Pos)
-#define NVMCTRL_STATUS_PRM_Pos      1            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
-#define NVMCTRL_STATUS_PRM          (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos)
-#define NVMCTRL_STATUS_LOAD_Pos     2            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
-#define NVMCTRL_STATUS_LOAD         (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos)
-#define NVMCTRL_STATUS_SUSP_Pos     3            /**< \brief (NVMCTRL_STATUS) NVM Write Or Erase Operation Is Suspended */
-#define NVMCTRL_STATUS_SUSP         (_U_(0x1) << NVMCTRL_STATUS_SUSP_Pos)
-#define NVMCTRL_STATUS_AFIRST_Pos   4            /**< \brief (NVMCTRL_STATUS) BANKA First */
-#define NVMCTRL_STATUS_AFIRST       (_U_(0x1) << NVMCTRL_STATUS_AFIRST_Pos)
-#define NVMCTRL_STATUS_BPDIS_Pos    5            /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Disable */
-#define NVMCTRL_STATUS_BPDIS        (_U_(0x1) << NVMCTRL_STATUS_BPDIS_Pos)
-#define NVMCTRL_STATUS_BOOTPROT_Pos 8            /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Size */
-#define NVMCTRL_STATUS_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_STATUS_BOOTPROT_Pos)
-#define NVMCTRL_STATUS_BOOTPROT(value) (NVMCTRL_STATUS_BOOTPROT_Msk & ((value) << NVMCTRL_STATUS_BOOTPROT_Pos))
-#define NVMCTRL_STATUS_MASK         _U_(0x0F3F)  /**< \brief (NVMCTRL_STATUS) MASK Register */
-
-/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x14) (R/W 32) Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:24;          /*!< bit:  0..23  NVM Address                        */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_ADDR_OFFSET         0x14         /**< \brief (NVMCTRL_ADDR offset) Address */
-#define NVMCTRL_ADDR_RESETVALUE     _U_(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */
-
-#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
-#define NVMCTRL_ADDR_ADDR_Msk       (_U_(0xFFFFFF) << NVMCTRL_ADDR_ADDR_Pos)
-#define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
-#define NVMCTRL_ADDR_MASK           _U_(0x00FFFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */
-
-/* -------- NVMCTRL_RUNLOCK : (NVMCTRL Offset: 0x18) (R/  32) Lock Section -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RUNLOCK:32;       /*!< bit:  0..31  Region Un-Lock Bits                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_RUNLOCK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_RUNLOCK_OFFSET      0x18         /**< \brief (NVMCTRL_RUNLOCK offset) Lock Section */
-#define NVMCTRL_RUNLOCK_RESETVALUE  _U_(0x00000000) /**< \brief (NVMCTRL_RUNLOCK reset_value) Lock Section */
-
-#define NVMCTRL_RUNLOCK_RUNLOCK_Pos 0            /**< \brief (NVMCTRL_RUNLOCK) Region Un-Lock Bits */
-#define NVMCTRL_RUNLOCK_RUNLOCK_Msk (_U_(0xFFFFFFFF) << NVMCTRL_RUNLOCK_RUNLOCK_Pos)
-#define NVMCTRL_RUNLOCK_RUNLOCK(value) (NVMCTRL_RUNLOCK_RUNLOCK_Msk & ((value) << NVMCTRL_RUNLOCK_RUNLOCK_Pos))
-#define NVMCTRL_RUNLOCK_MASK        _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_RUNLOCK) MASK Register */
-
-/* -------- NVMCTRL_PBLDATA : (NVMCTRL Offset: 0x1C) (R/  32) Page Buffer Load Data x -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Page Buffer Data                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_PBLDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_PBLDATA_OFFSET      0x1C         /**< \brief (NVMCTRL_PBLDATA offset) Page Buffer Load Data x */
-#define NVMCTRL_PBLDATA_RESETVALUE  _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA reset_value) Page Buffer Load Data x */
-
-#define NVMCTRL_PBLDATA_DATA_Pos    0            /**< \brief (NVMCTRL_PBLDATA) Page Buffer Data */
-#define NVMCTRL_PBLDATA_DATA_Msk    (_U_(0xFFFFFFFF) << NVMCTRL_PBLDATA_DATA_Pos)
-#define NVMCTRL_PBLDATA_DATA(value) (NVMCTRL_PBLDATA_DATA_Msk & ((value) << NVMCTRL_PBLDATA_DATA_Pos))
-#define NVMCTRL_PBLDATA_MASK        _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA) MASK Register */
-
-/* -------- NVMCTRL_ECCERR : (NVMCTRL Offset: 0x24) (R/  32) ECC Error Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:24;          /*!< bit:  0..23  Error Address                      */
-    uint32_t :4;               /*!< bit: 24..27  Reserved                           */
-    uint32_t TYPEL:2;          /*!< bit: 28..29  Low Double-Word Error Type         */
-    uint32_t TYPEH:2;          /*!< bit: 30..31  High Double-Word Error Type        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_ECCERR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_ECCERR_OFFSET       0x24         /**< \brief (NVMCTRL_ECCERR offset) ECC Error Status Register */
-#define NVMCTRL_ECCERR_RESETVALUE   _U_(0x00000000) /**< \brief (NVMCTRL_ECCERR reset_value) ECC Error Status Register */
-
-#define NVMCTRL_ECCERR_ADDR_Pos     0            /**< \brief (NVMCTRL_ECCERR) Error Address */
-#define NVMCTRL_ECCERR_ADDR_Msk     (_U_(0xFFFFFF) << NVMCTRL_ECCERR_ADDR_Pos)
-#define NVMCTRL_ECCERR_ADDR(value)  (NVMCTRL_ECCERR_ADDR_Msk & ((value) << NVMCTRL_ECCERR_ADDR_Pos))
-#define NVMCTRL_ECCERR_TYPEL_Pos    28           /**< \brief (NVMCTRL_ECCERR) Low Double-Word Error Type */
-#define NVMCTRL_ECCERR_TYPEL_Msk    (_U_(0x3) << NVMCTRL_ECCERR_TYPEL_Pos)
-#define NVMCTRL_ECCERR_TYPEL(value) (NVMCTRL_ECCERR_TYPEL_Msk & ((value) << NVMCTRL_ECCERR_TYPEL_Pos))
-#define   NVMCTRL_ECCERR_TYPEL_NONE_Val   _U_(0x0)   /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */
-#define   NVMCTRL_ECCERR_TYPEL_SINGLE_Val _U_(0x1)   /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
-#define   NVMCTRL_ECCERR_TYPEL_DUAL_Val   _U_(0x2)   /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
-#define NVMCTRL_ECCERR_TYPEL_NONE   (NVMCTRL_ECCERR_TYPEL_NONE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
-#define NVMCTRL_ECCERR_TYPEL_SINGLE (NVMCTRL_ECCERR_TYPEL_SINGLE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
-#define NVMCTRL_ECCERR_TYPEL_DUAL   (NVMCTRL_ECCERR_TYPEL_DUAL_Val << NVMCTRL_ECCERR_TYPEL_Pos)
-#define NVMCTRL_ECCERR_TYPEH_Pos    30           /**< \brief (NVMCTRL_ECCERR) High Double-Word Error Type */
-#define NVMCTRL_ECCERR_TYPEH_Msk    (_U_(0x3) << NVMCTRL_ECCERR_TYPEH_Pos)
-#define NVMCTRL_ECCERR_TYPEH(value) (NVMCTRL_ECCERR_TYPEH_Msk & ((value) << NVMCTRL_ECCERR_TYPEH_Pos))
-#define   NVMCTRL_ECCERR_TYPEH_NONE_Val   _U_(0x0)   /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */
-#define   NVMCTRL_ECCERR_TYPEH_SINGLE_Val _U_(0x1)   /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
-#define   NVMCTRL_ECCERR_TYPEH_DUAL_Val   _U_(0x2)   /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
-#define NVMCTRL_ECCERR_TYPEH_NONE   (NVMCTRL_ECCERR_TYPEH_NONE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
-#define NVMCTRL_ECCERR_TYPEH_SINGLE (NVMCTRL_ECCERR_TYPEH_SINGLE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
-#define NVMCTRL_ECCERR_TYPEH_DUAL   (NVMCTRL_ECCERR_TYPEH_DUAL_Val << NVMCTRL_ECCERR_TYPEH_Pos)
-#define NVMCTRL_ECCERR_MASK         _U_(0xF0FFFFFF) /**< \brief (NVMCTRL_ECCERR) MASK Register */
-
-/* -------- NVMCTRL_DBGCTRL : (NVMCTRL Offset: 0x28) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ECCDIS:1;         /*!< bit:      0  Debugger ECC Read Disable          */
-    uint8_t  ECCELOG:1;        /*!< bit:      1  Debugger ECC Error Tracking Mode   */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} NVMCTRL_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_DBGCTRL_OFFSET      0x28         /**< \brief (NVMCTRL_DBGCTRL offset) Debug Control */
-#define NVMCTRL_DBGCTRL_RESETVALUE  _U_(0x00)    /**< \brief (NVMCTRL_DBGCTRL reset_value) Debug Control */
-
-#define NVMCTRL_DBGCTRL_ECCDIS_Pos  0            /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Read Disable */
-#define NVMCTRL_DBGCTRL_ECCDIS      (_U_(0x1) << NVMCTRL_DBGCTRL_ECCDIS_Pos)
-#define NVMCTRL_DBGCTRL_ECCELOG_Pos 1            /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Error Tracking Mode */
-#define NVMCTRL_DBGCTRL_ECCELOG     (_U_(0x1) << NVMCTRL_DBGCTRL_ECCELOG_Pos)
-#define NVMCTRL_DBGCTRL_MASK        _U_(0x03)    /**< \brief (NVMCTRL_DBGCTRL) MASK Register */
-
-/* -------- NVMCTRL_SEECFG : (NVMCTRL Offset: 0x2A) (R/W  8) SmartEEPROM Configuration Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  WMODE:1;          /*!< bit:      0  Write Mode                         */
-    uint8_t  APRDIS:1;         /*!< bit:      1  Automatic Page Reallocation Disable */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} NVMCTRL_SEECFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_SEECFG_OFFSET       0x2A         /**< \brief (NVMCTRL_SEECFG offset) SmartEEPROM Configuration Register */
-#define NVMCTRL_SEECFG_RESETVALUE   _U_(0x00)    /**< \brief (NVMCTRL_SEECFG reset_value) SmartEEPROM Configuration Register */
-
-#define NVMCTRL_SEECFG_WMODE_Pos    0            /**< \brief (NVMCTRL_SEECFG) Write Mode */
-#define NVMCTRL_SEECFG_WMODE        (_U_(0x1) << NVMCTRL_SEECFG_WMODE_Pos)
-#define   NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val _U_(0x0)   /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued after each write in the pagebuffer */
-#define   NVMCTRL_SEECFG_WMODE_BUFFERED_Val _U_(0x1)   /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued when a write to a new page is requested */
-#define NVMCTRL_SEECFG_WMODE_UNBUFFERED (NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
-#define NVMCTRL_SEECFG_WMODE_BUFFERED (NVMCTRL_SEECFG_WMODE_BUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
-#define NVMCTRL_SEECFG_APRDIS_Pos   1            /**< \brief (NVMCTRL_SEECFG) Automatic Page Reallocation Disable */
-#define NVMCTRL_SEECFG_APRDIS       (_U_(0x1) << NVMCTRL_SEECFG_APRDIS_Pos)
-#define NVMCTRL_SEECFG_MASK         _U_(0x03)    /**< \brief (NVMCTRL_SEECFG) MASK Register */
-
-/* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) (R/  32) SmartEEPROM Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ASEES:1;          /*!< bit:      0  Active SmartEEPROM Sector          */
-    uint32_t LOAD:1;           /*!< bit:      1  Page Buffer Loaded                 */
-    uint32_t BUSY:1;           /*!< bit:      2  Busy                               */
-    uint32_t LOCK:1;           /*!< bit:      3  SmartEEPROM Write Access Is Locked */
-    uint32_t RLOCK:1;          /*!< bit:      4  SmartEEPROM Write Access To Register Address Space Is Locked */
-    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint32_t SBLK:4;           /*!< bit:  8..11  Blocks Number In a Sector          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t PSZ:3;            /*!< bit: 16..18  SmartEEPROM Page Size              */
-    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} NVMCTRL_SEESTAT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define NVMCTRL_SEESTAT_OFFSET      0x2C         /**< \brief (NVMCTRL_SEESTAT offset) SmartEEPROM Status Register */
-#define NVMCTRL_SEESTAT_RESETVALUE  _U_(0x00000000) /**< \brief (NVMCTRL_SEESTAT reset_value) SmartEEPROM Status Register */
-
-#define NVMCTRL_SEESTAT_ASEES_Pos   0            /**< \brief (NVMCTRL_SEESTAT) Active SmartEEPROM Sector */
-#define NVMCTRL_SEESTAT_ASEES       (_U_(0x1) << NVMCTRL_SEESTAT_ASEES_Pos)
-#define NVMCTRL_SEESTAT_LOAD_Pos    1            /**< \brief (NVMCTRL_SEESTAT) Page Buffer Loaded */
-#define NVMCTRL_SEESTAT_LOAD        (_U_(0x1) << NVMCTRL_SEESTAT_LOAD_Pos)
-#define NVMCTRL_SEESTAT_BUSY_Pos    2            /**< \brief (NVMCTRL_SEESTAT) Busy */
-#define NVMCTRL_SEESTAT_BUSY        (_U_(0x1) << NVMCTRL_SEESTAT_BUSY_Pos)
-#define NVMCTRL_SEESTAT_LOCK_Pos    3            /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access Is Locked */
-#define NVMCTRL_SEESTAT_LOCK        (_U_(0x1) << NVMCTRL_SEESTAT_LOCK_Pos)
-#define NVMCTRL_SEESTAT_RLOCK_Pos   4            /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access To Register Address Space Is Locked */
-#define NVMCTRL_SEESTAT_RLOCK       (_U_(0x1) << NVMCTRL_SEESTAT_RLOCK_Pos)
-#define NVMCTRL_SEESTAT_SBLK_Pos    8            /**< \brief (NVMCTRL_SEESTAT) Blocks Number In a Sector */
-#define NVMCTRL_SEESTAT_SBLK_Msk    (_U_(0xF) << NVMCTRL_SEESTAT_SBLK_Pos)
-#define NVMCTRL_SEESTAT_SBLK(value) (NVMCTRL_SEESTAT_SBLK_Msk & ((value) << NVMCTRL_SEESTAT_SBLK_Pos))
-#define NVMCTRL_SEESTAT_PSZ_Pos     16           /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Page Size */
-#define NVMCTRL_SEESTAT_PSZ_Msk     (_U_(0x7) << NVMCTRL_SEESTAT_PSZ_Pos)
-#define NVMCTRL_SEESTAT_PSZ(value)  (NVMCTRL_SEESTAT_PSZ_Msk & ((value) << NVMCTRL_SEESTAT_PSZ_Pos))
-#define NVMCTRL_SEESTAT_MASK        _U_(0x00070F1F) /**< \brief (NVMCTRL_SEESTAT) MASK Register */
-
-/** \brief NVMCTRL APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
-       RoReg8                    Reserved1[0x2];
-  __O  NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 ( /W 16) Control B */
-       RoReg8                    Reserved2[0x2];
-  __I  NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/  32) NVM Parameter */
-  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
-  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x0E (R/W 16) Interrupt Enable Set */
-  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear */
-  __I  NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x12 (R/  16) Status */
-  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x14 (R/W 32) Address */
-  __I  NVMCTRL_RUNLOCK_Type      RUNLOCK;     /**< \brief Offset: 0x18 (R/  32) Lock Section */
-  __I  NVMCTRL_PBLDATA_Type      PBLDATA[2];  /**< \brief Offset: 0x1C (R/  32) Page Buffer Load Data x */
-  __I  NVMCTRL_ECCERR_Type       ECCERR;      /**< \brief Offset: 0x24 (R/  32) ECC Error Status Register */
-  __IO NVMCTRL_DBGCTRL_Type      DBGCTRL;     /**< \brief Offset: 0x28 (R/W  8) Debug Control */
-       RoReg8                    Reserved3[0x1];
-  __IO NVMCTRL_SEECFG_Type       SEECFG;      /**< \brief Offset: 0x2A (R/W  8) SmartEEPROM Configuration Register */
-       RoReg8                    Reserved4[0x1];
-  __I  NVMCTRL_SEESTAT_Type      SEESTAT;     /**< \brief Offset: 0x2C (R/  32) SmartEEPROM Status Register */
-} Nvmctrl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_NVMCTRL_CB
-
-#define SECTION_NVMCTRL_CBW0
-
-#define SECTION_NVMCTRL_CBW1
-
-#define SECTION_NVMCTRL_CBW2
-
-#define SECTION_NVMCTRL_CBW3
-
-#define SECTION_NVMCTRL_CBW4
-
-#define SECTION_NVMCTRL_CBW5
-
-#define SECTION_NVMCTRL_CBW6
-
-#define SECTION_NVMCTRL_CBW7
-
-#define SECTION_NVMCTRL_FS
-
-#define SECTION_NVMCTRL_GB
-
-#define SECTION_NVMCTRL_SW0
-
-#define SECTION_NVMCTRL_SW1
-
-#define SECTION_NVMCTRL_SW2
-
-#define SECTION_NVMCTRL_SW3
-
-#define SECTION_NVMCTRL_SW4
-
-#define SECTION_NVMCTRL_SW5
-
-#define SECTION_NVMCTRL_SW6
-
-#define SECTION_NVMCTRL_SW7
-
-#define SECTION_NVMCTRL_TEMP_LOG
-
-#define SECTION_NVMCTRL_TEMP_LOG_W0
-
-#define SECTION_NVMCTRL_TEMP_LOG_W1
-
-#define SECTION_NVMCTRL_TEMP_LOG_W2
-
-#define SECTION_NVMCTRL_TEMP_LOG_W3
-
-#define SECTION_NVMCTRL_TEMP_LOG_W4
-
-#define SECTION_NVMCTRL_TEMP_LOG_W5
-
-#define SECTION_NVMCTRL_TEMP_LOG_W6
-
-#define SECTION_NVMCTRL_TEMP_LOG_W7
-
-#define SECTION_NVMCTRL_TLATCH
-
-#define SECTION_NVMCTRL_USER
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
-/* ************************************************************************** */
-/** \addtogroup fuses_api Peripheral Software API */
-/*@{*/
-
-
-#define AC_FUSES_BIAS0_ADDR         NVMCTRL_SW0
-#define AC_FUSES_BIAS0_Pos          0            /**< \brief (NVMCTRL_SW0) PAIR0 Bias Calibration */
-#define AC_FUSES_BIAS0_Msk          (_U_(0x3) << AC_FUSES_BIAS0_Pos)
-#define AC_FUSES_BIAS0(value)       (AC_FUSES_BIAS0_Msk & ((value) << AC_FUSES_BIAS0_Pos))
-
-#define ADC0_FUSES_BIASCOMP_ADDR    NVMCTRL_SW0
-#define ADC0_FUSES_BIASCOMP_Pos     2            /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */
-#define ADC0_FUSES_BIASCOMP_Msk     (_U_(0x7) << ADC0_FUSES_BIASCOMP_Pos)
-#define ADC0_FUSES_BIASCOMP(value)  (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos))
-
-#define ADC0_FUSES_BIASR2R_ADDR     NVMCTRL_SW0
-#define ADC0_FUSES_BIASR2R_Pos      8            /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */
-#define ADC0_FUSES_BIASR2R_Msk      (_U_(0x7) << ADC0_FUSES_BIASR2R_Pos)
-#define ADC0_FUSES_BIASR2R(value)   (ADC0_FUSES_BIASR2R_Msk & ((value) << ADC0_FUSES_BIASR2R_Pos))
-
-#define ADC0_FUSES_BIASREFBUF_ADDR  NVMCTRL_SW0
-#define ADC0_FUSES_BIASREFBUF_Pos   5            /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */
-#define ADC0_FUSES_BIASREFBUF_Msk   (_U_(0x7) << ADC0_FUSES_BIASREFBUF_Pos)
-#define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos))
-
-#define ADC1_FUSES_BIASCOMP_ADDR    NVMCTRL_SW0
-#define ADC1_FUSES_BIASCOMP_Pos     16           /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */
-#define ADC1_FUSES_BIASCOMP_Msk     (_U_(0x7) << ADC1_FUSES_BIASCOMP_Pos)
-#define ADC1_FUSES_BIASCOMP(value)  (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos))
-
-#define ADC1_FUSES_BIASR2R_ADDR     NVMCTRL_SW0
-#define ADC1_FUSES_BIASR2R_Pos      22           /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */
-#define ADC1_FUSES_BIASR2R_Msk      (_U_(0x7) << ADC1_FUSES_BIASR2R_Pos)
-#define ADC1_FUSES_BIASR2R(value)   (ADC1_FUSES_BIASR2R_Msk & ((value) << ADC1_FUSES_BIASR2R_Pos))
-
-#define ADC1_FUSES_BIASREFBUF_ADDR  NVMCTRL_SW0
-#define ADC1_FUSES_BIASREFBUF_Pos   19           /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */
-#define ADC1_FUSES_BIASREFBUF_Msk   (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos)
-#define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos))
-
-#define FUSES_BOD12USERLEVEL_ADDR   NVMCTRL_USER
-#define FUSES_BOD12USERLEVEL_Pos    17           /**< \brief (NVMCTRL_USER) BOD12 User Level */
-#define FUSES_BOD12USERLEVEL_Msk    (_U_(0x3F) << FUSES_BOD12USERLEVEL_Pos)
-#define FUSES_BOD12USERLEVEL(value) (FUSES_BOD12USERLEVEL_Msk & ((value) << FUSES_BOD12USERLEVEL_Pos))
-
-#define FUSES_BOD12_ACTION_ADDR     NVMCTRL_USER
-#define FUSES_BOD12_ACTION_Pos      23           /**< \brief (NVMCTRL_USER) BOD12 Action */
-#define FUSES_BOD12_ACTION_Msk      (_U_(0x3) << FUSES_BOD12_ACTION_Pos)
-#define FUSES_BOD12_ACTION(value)   (FUSES_BOD12_ACTION_Msk & ((value) << FUSES_BOD12_ACTION_Pos))
-
-#define FUSES_BOD12_DIS_ADDR        NVMCTRL_USER
-#define FUSES_BOD12_DIS_Pos         16           /**< \brief (NVMCTRL_USER) BOD12 Disable */
-#define FUSES_BOD12_DIS_Msk         (_U_(0x1) << FUSES_BOD12_DIS_Pos)
-
-#define FUSES_BOD12_HYST_ADDR       NVMCTRL_USER
-#define FUSES_BOD12_HYST_Pos        25           /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */
-#define FUSES_BOD12_HYST_Msk        (_U_(0x1) << FUSES_BOD12_HYST_Pos)
-
-#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
-#define FUSES_BOD33USERLEVEL_Pos    1            /**< \brief (NVMCTRL_USER) BOD33 User Level */
-#define FUSES_BOD33USERLEVEL_Msk    (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos)
-#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
-
-#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
-#define FUSES_BOD33_ACTION_Pos      9            /**< \brief (NVMCTRL_USER) BOD33 Action */
-#define FUSES_BOD33_ACTION_Msk      (_U_(0x3) << FUSES_BOD33_ACTION_Pos)
-#define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
-
-#define FUSES_BOD33_DIS_ADDR        NVMCTRL_USER
-#define FUSES_BOD33_DIS_Pos         0            /**< \brief (NVMCTRL_USER) BOD33 Disable */
-#define FUSES_BOD33_DIS_Msk         (_U_(0x1) << FUSES_BOD33_DIS_Pos)
-
-#define FUSES_BOD33_HYST_ADDR       NVMCTRL_USER
-#define FUSES_BOD33_HYST_Pos        11           /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
-#define FUSES_BOD33_HYST_Msk        (_U_(0xF) << FUSES_BOD33_HYST_Pos)
-#define FUSES_BOD33_HYST(value)     (FUSES_BOD33_HYST_Msk & ((value) << FUSES_BOD33_HYST_Pos))
-
-#define FUSES_HOT_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
-#define FUSES_HOT_ADC_VAL_CTAT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature CTAT */
-#define FUSES_HOT_ADC_VAL_CTAT_Msk  (_U_(0xFFF) << FUSES_HOT_ADC_VAL_CTAT_Pos)
-#define FUSES_HOT_ADC_VAL_CTAT(value) (FUSES_HOT_ADC_VAL_CTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_CTAT_Pos))
-
-#define FUSES_HOT_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
-#define FUSES_HOT_ADC_VAL_PTAT_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature PTAT */
-#define FUSES_HOT_ADC_VAL_PTAT_Msk  (_U_(0xFFF) << FUSES_HOT_ADC_VAL_PTAT_Pos)
-#define FUSES_HOT_ADC_VAL_PTAT(value) (FUSES_HOT_ADC_VAL_PTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_PTAT_Pos))
-
-#define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
-#define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
-#define FUSES_HOT_INT1V_VAL_Msk     (_U_(0xFF) << FUSES_HOT_INT1V_VAL_Pos)
-#define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
-
-#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
-#define FUSES_HOT_TEMP_VAL_DEC_Msk  (_U_(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos)
-#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
-
-#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
-#define FUSES_HOT_TEMP_VAL_INT_Msk  (_U_(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos)
-#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
-
-#define FUSES_ROOM_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
-#define FUSES_ROOM_ADC_VAL_CTAT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature CTAT */
-#define FUSES_ROOM_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_CTAT_Pos)
-#define FUSES_ROOM_ADC_VAL_CTAT(value) (FUSES_ROOM_ADC_VAL_CTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_CTAT_Pos))
-
-#define FUSES_ROOM_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
-#define FUSES_ROOM_ADC_VAL_PTAT_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature PTAT */
-#define FUSES_ROOM_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_PTAT_Pos)
-#define FUSES_ROOM_ADC_VAL_PTAT(value) (FUSES_ROOM_ADC_VAL_PTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_PTAT_Pos))
-
-#define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
-#define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
-#define FUSES_ROOM_INT1V_VAL_Msk    (_U_(0xFF) << FUSES_ROOM_INT1V_VAL_Pos)
-#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
-
-#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
-#define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos)
-#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
-
-#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
-#define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
-#define FUSES_ROOM_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos)
-#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
-
-#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
-#define NVMCTRL_FUSES_BOOTPROT_Pos  26           /**< \brief (NVMCTRL_USER) Bootloader Size */
-#define NVMCTRL_FUSES_BOOTPROT_Msk  (_U_(0xF) << NVMCTRL_FUSES_BOOTPROT_Pos)
-#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
-
-#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 8)
-#define NVMCTRL_FUSES_REGION_LOCKS_Pos 0            /**< \brief (NVMCTRL_USER) NVM Region Locks */
-#define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFFFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
-#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
-
-#define NVMCTRL_FUSES_SEEPSZ_ADDR   (NVMCTRL_USER + 4)
-#define NVMCTRL_FUSES_SEEPSZ_Pos    4            /**< \brief (NVMCTRL_USER) Size Of SmartEEPROM Page */
-#define NVMCTRL_FUSES_SEEPSZ_Msk    (_U_(0x7) << NVMCTRL_FUSES_SEEPSZ_Pos)
-#define NVMCTRL_FUSES_SEEPSZ(value) (NVMCTRL_FUSES_SEEPSZ_Msk & ((value) << NVMCTRL_FUSES_SEEPSZ_Pos))
-
-#define NVMCTRL_FUSES_SEESBLK_ADDR  (NVMCTRL_USER + 4)
-#define NVMCTRL_FUSES_SEESBLK_Pos   0            /**< \brief (NVMCTRL_USER) Number Of Physical NVM Blocks Composing a SmartEEPROM Sector */
-#define NVMCTRL_FUSES_SEESBLK_Msk   (_U_(0xF) << NVMCTRL_FUSES_SEESBLK_Pos)
-#define NVMCTRL_FUSES_SEESBLK(value) (NVMCTRL_FUSES_SEESBLK_Msk & ((value) << NVMCTRL_FUSES_SEESBLK_Pos))
-
-#define RAMECC_FUSES_ECCDIS_ADDR    (NVMCTRL_USER + 4)
-#define RAMECC_FUSES_ECCDIS_Pos     7            /**< \brief (NVMCTRL_USER) RAM ECC Disable fuse */
-#define RAMECC_FUSES_ECCDIS_Msk     (_U_(0x1) << RAMECC_FUSES_ECCDIS_Pos)
-
-#define USB_FUSES_TRANSN_ADDR       (NVMCTRL_SW0 + 4)
-#define USB_FUSES_TRANSN_Pos        0            /**< \brief (NVMCTRL_SW0) USB pad Transn calibration */
-#define USB_FUSES_TRANSN_Msk        (_U_(0x1F) << USB_FUSES_TRANSN_Pos)
-#define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
-
-#define USB_FUSES_TRANSP_ADDR       (NVMCTRL_SW0 + 4)
-#define USB_FUSES_TRANSP_Pos        5            /**< \brief (NVMCTRL_SW0) USB pad Transp calibration */
-#define USB_FUSES_TRANSP_Msk        (_U_(0x1F) << USB_FUSES_TRANSP_Pos)
-#define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
-
-#define USB_FUSES_TRIM_ADDR         (NVMCTRL_SW0 + 4)
-#define USB_FUSES_TRIM_Pos          10           /**< \brief (NVMCTRL_SW0) USB pad Trim calibration */
-#define USB_FUSES_TRIM_Msk          (_U_(0x7) << USB_FUSES_TRIM_Pos)
-#define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
-
-#define WDT_FUSES_ALWAYSON_ADDR     (NVMCTRL_USER + 4)
-#define WDT_FUSES_ALWAYSON_Pos      17           /**< \brief (NVMCTRL_USER) WDT Always On */
-#define WDT_FUSES_ALWAYSON_Msk      (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos)
-
-#define WDT_FUSES_ENABLE_ADDR       (NVMCTRL_USER + 4)
-#define WDT_FUSES_ENABLE_Pos        16           /**< \brief (NVMCTRL_USER) WDT Enable */
-#define WDT_FUSES_ENABLE_Msk        (_U_(0x1) << WDT_FUSES_ENABLE_Pos)
-
-#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
-#define WDT_FUSES_EWOFFSET_Pos      26           /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
-#define WDT_FUSES_EWOFFSET_Msk      (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos)
-#define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
-
-#define WDT_FUSES_PER_ADDR          (NVMCTRL_USER + 4)
-#define WDT_FUSES_PER_Pos           18           /**< \brief (NVMCTRL_USER) WDT Period */
-#define WDT_FUSES_PER_Msk           (_U_(0xF) << WDT_FUSES_PER_Pos)
-#define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
-
-#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
-#define WDT_FUSES_WEN_Pos           30           /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
-#define WDT_FUSES_WEN_Msk           (_U_(0x1) << WDT_FUSES_WEN_Pos)
-
-#define WDT_FUSES_WINDOW_ADDR       (NVMCTRL_USER + 4)
-#define WDT_FUSES_WINDOW_Pos        22           /**< \brief (NVMCTRL_USER) WDT Window */
-#define WDT_FUSES_WINDOW_Msk        (_U_(0xF) << WDT_FUSES_WINDOW_Pos)
-#define WDT_FUSES_WINDOW(value)     (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))
-
-/*@}*/
-
-#endif /* _SAMD51_NVMCTRL_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/osc32kctrl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/osc32kctrl.h
deleted file mode 100644
index 8e41c450ed..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/osc32kctrl.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for OSC32KCTRL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_OSC32KCTRL_COMPONENT_
-#define _SAMD51_OSC32KCTRL_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR OSC32KCTRL */
-/* ========================================================================== */
-/** \addtogroup SAMD51_OSC32KCTRL 32kHz Oscillators Control */
-/*@{*/
-
-#define OSC32KCTRL_U2400
-#define REV_OSC32KCTRL              0x100
-
-/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready Interrupt Enable     */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t XOSC32KFAIL:1;    /*!< bit:      2  XOSC32K Clock Failure Detector Interrupt Enable */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSC32KCTRL_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_INTENCLR_OFFSET  0x00         /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */
-#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
-#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
-#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2            /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */
-#define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)
-#define OSC32KCTRL_INTENCLR_MASK    _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */
-
-/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready Interrupt Enable     */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t XOSC32KFAIL:1;    /*!< bit:      2  XOSC32K Clock Failure Detector Interrupt Enable */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSC32KCTRL_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_INTENSET_OFFSET  0x04         /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */
-#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */
-
-#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
-#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
-#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2            /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */
-#define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)
-#define OSC32KCTRL_INTENSET_MASK    _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */
-
-/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready                      */
-    __I uint32_t :1;               /*!< bit:      1  Reserved                           */
-    __I uint32_t XOSC32KFAIL:1;    /*!< bit:      2  XOSC32K Clock Failure Detector     */
-    __I uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSC32KCTRL_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_INTFLAG_OFFSET   0x08         /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */
-#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
-#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2            /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */
-#define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)
-#define OSC32KCTRL_INTFLAG_MASK     _U_(0x00000005) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */
-
-/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready                      */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t XOSC32KFAIL:1;    /*!< bit:      2  XOSC32K Clock Failure Detector     */
-    uint32_t XOSC32KSW:1;      /*!< bit:      3  XOSC32K Clock switch               */
-    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSC32KCTRL_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_STATUS_OFFSET    0x0C         /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */
-#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */
-
-#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */
-#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
-#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2            /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */
-#define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)
-#define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3            /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */
-#define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)
-#define OSC32KCTRL_STATUS_MASK      _U_(0x0000000D) /**< \brief (OSC32KCTRL_STATUS) MASK Register */
-
-/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W  8) RTC Clock Selection -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RTCSEL:3;         /*!< bit:  0.. 2  RTC Clock Selection                */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} OSC32KCTRL_RTCCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_RTCCTRL_OFFSET   0x10         /**< \brief (OSC32KCTRL_RTCCTRL offset) RTC Clock Selection */
-#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00)    /**< \brief (OSC32KCTRL_RTCCTRL reset_value) RTC Clock Selection */
-
-#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0            /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */
-#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
-#define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0)   /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
-#define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1)   /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
-#define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4)   /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
-#define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5)   /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
-#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
-#define OSC32KCTRL_RTCCTRL_MASK     _U_(0x07)    /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */
-
-/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :1;               /*!< bit:      0  Reserved                           */
-    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
-    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
-    uint16_t EN32K:1;          /*!< bit:      3  32kHz Output Enable                */
-    uint16_t EN1K:1;           /*!< bit:      4  1kHz Output Enable                 */
-    uint16_t :1;               /*!< bit:      5  Reserved                           */
-    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-    uint16_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
-    uint16_t :1;               /*!< bit:     11  Reserved                           */
-    uint16_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
-    uint16_t CGM:2;            /*!< bit: 13..14  Control Gain Mode                  */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} OSC32KCTRL_XOSC32K_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_XOSC32K_OFFSET   0x14         /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
-#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080)  /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
-
-#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1            /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */
-#define OSC32KCTRL_XOSC32K_ENABLE   (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
-#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2            /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */
-#define OSC32KCTRL_XOSC32K_XTALEN   (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
-#define OSC32KCTRL_XOSC32K_EN32K_Pos 3            /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */
-#define OSC32KCTRL_XOSC32K_EN32K    (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
-#define OSC32KCTRL_XOSC32K_EN1K_Pos 4            /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */
-#define OSC32KCTRL_XOSC32K_EN1K     (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
-#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6            /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */
-#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
-#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7            /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */
-#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
-#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8            /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */
-#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
-#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
-#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12           /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */
-#define OSC32KCTRL_XOSC32K_WRTLOCK  (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
-#define OSC32KCTRL_XOSC32K_CGM_Pos  13           /**< \brief (OSC32KCTRL_XOSC32K) Control Gain Mode */
-#define OSC32KCTRL_XOSC32K_CGM_Msk  (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)
-#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
-#define   OSC32KCTRL_XOSC32K_CGM_XT_Val   _U_(0x1)   /**< \brief (OSC32KCTRL_XOSC32K) Standard mode */
-#define   OSC32KCTRL_XOSC32K_CGM_HS_Val   _U_(0x2)   /**< \brief (OSC32KCTRL_XOSC32K) High Speed mode */
-#define OSC32KCTRL_XOSC32K_CGM_XT   (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
-#define OSC32KCTRL_XOSC32K_CGM_HS   (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
-#define OSC32KCTRL_XOSC32K_MASK     _U_(0x77DE)  /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */
-
-/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W  8) Clock Failure Detector Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CFDEN:1;          /*!< bit:      0  Clock Failure Detector Enable      */
-    uint8_t  SWBACK:1;         /*!< bit:      1  Clock Switch Back                  */
-    uint8_t  CFDPRESC:1;       /*!< bit:      2  Clock Failure Detector Prescaler   */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} OSC32KCTRL_CFDCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_CFDCTRL_OFFSET   0x16         /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */
-#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00)    /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */
-
-#define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0            /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */
-#define OSC32KCTRL_CFDCTRL_CFDEN    (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
-#define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1            /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */
-#define OSC32KCTRL_CFDCTRL_SWBACK   (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
-#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2            /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */
-#define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
-#define OSC32KCTRL_CFDCTRL_MASK     _U_(0x07)    /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */
-
-/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W  8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CFDEO:1;          /*!< bit:      0  Clock Failure Detector Event Output Enable */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} OSC32KCTRL_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_EVCTRL_OFFSET    0x17         /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */
-#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00)    /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */
-
-#define OSC32KCTRL_EVCTRL_CFDEO_Pos 0            /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */
-#define OSC32KCTRL_EVCTRL_CFDEO     (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
-#define OSC32KCTRL_EVCTRL_MASK      _U_(0x01)    /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */
-
-/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t EN32K:1;          /*!< bit:      1  Enable Out 32k                     */
-    uint32_t EN1K:1;           /*!< bit:      2  Enable Out 1k                      */
-    uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
-    uint32_t CALIB:6;          /*!< bit:  8..13  Oscillator Calibration             */
-    uint32_t :1;               /*!< bit:     14  Reserved                           */
-    uint32_t WRTLOCK:1;        /*!< bit:     15  Write Lock                         */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSC32KCTRL_OSCULP32K_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C         /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-
-#define OSC32KCTRL_OSCULP32K_EN32K_Pos 1            /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 32k */
-#define OSC32KCTRL_OSCULP32K_EN32K  (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)
-#define OSC32KCTRL_OSCULP32K_EN1K_Pos 2            /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 1k */
-#define OSC32KCTRL_OSCULP32K_EN1K   (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)
-#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8            /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */
-#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
-#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
-#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15           /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */
-#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
-#define OSC32KCTRL_OSCULP32K_MASK   _U_(0x0000BF06) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */
-
-/** \brief OSC32KCTRL hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO OSC32KCTRL_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
-  __IO OSC32KCTRL_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
-  __IO OSC32KCTRL_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
-  __I  OSC32KCTRL_STATUS_Type    STATUS;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
-  __IO OSC32KCTRL_RTCCTRL_Type   RTCCTRL;     /**< \brief Offset: 0x10 (R/W  8) RTC Clock Selection */
-       RoReg8                    Reserved1[0x3];
-  __IO OSC32KCTRL_XOSC32K_Type   XOSC32K;     /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
-  __IO OSC32KCTRL_CFDCTRL_Type   CFDCTRL;     /**< \brief Offset: 0x16 (R/W  8) Clock Failure Detector Control */
-  __IO OSC32KCTRL_EVCTRL_Type    EVCTRL;      /**< \brief Offset: 0x17 (R/W  8) Event Control */
-       RoReg8                    Reserved2[0x4];
-  __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K;   /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-} Osc32kctrl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_OSC32KCTRL_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/oscctrl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/oscctrl.h
deleted file mode 100644
index ee9ad2113e..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/oscctrl.h
+++ /dev/null
@@ -1,793 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for OSCCTRL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_OSCCTRL_COMPONENT_
-#define _SAMD51_OSCCTRL_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR OSCCTRL */
-/* ========================================================================== */
-/** \addtogroup SAMD51_OSCCTRL Oscillators Control */
-/*@{*/
-
-#define OSCCTRL_U2401
-#define REV_OSCCTRL                 0x100
-
-/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W  8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CFDEO0:1;         /*!< bit:      0  Clock 0 Failure Detector Event Output Enable */
-    uint8_t  CFDEO1:1;         /*!< bit:      1  Clock 1 Failure Detector Event Output Enable */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  CFDEO:2;          /*!< bit:  0.. 1  Clock x Failure Detector Event Output Enable */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} OSCCTRL_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_EVCTRL_OFFSET       0x00         /**< \brief (OSCCTRL_EVCTRL offset) Event Control */
-#define OSCCTRL_EVCTRL_RESETVALUE   _U_(0x00)    /**< \brief (OSCCTRL_EVCTRL reset_value) Event Control */
-
-#define OSCCTRL_EVCTRL_CFDEO0_Pos   0            /**< \brief (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable */
-#define OSCCTRL_EVCTRL_CFDEO0       (_U_(1) << OSCCTRL_EVCTRL_CFDEO0_Pos)
-#define OSCCTRL_EVCTRL_CFDEO1_Pos   1            /**< \brief (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable */
-#define OSCCTRL_EVCTRL_CFDEO1       (_U_(1) << OSCCTRL_EVCTRL_CFDEO1_Pos)
-#define OSCCTRL_EVCTRL_CFDEO_Pos    0            /**< \brief (OSCCTRL_EVCTRL) Clock x Failure Detector Event Output Enable */
-#define OSCCTRL_EVCTRL_CFDEO_Msk    (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos)
-#define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))
-#define OSCCTRL_EVCTRL_MASK         _U_(0x03)    /**< \brief (OSCCTRL_EVCTRL) MASK Register */
-
-/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t XOSCRDY0:1;       /*!< bit:      0  XOSC 0 Ready Interrupt Enable      */
-    uint32_t XOSCRDY1:1;       /*!< bit:      1  XOSC 1 Ready Interrupt Enable      */
-    uint32_t XOSCFAIL0:1;      /*!< bit:      2  XOSC 0 Clock Failure Detector Interrupt Enable */
-    uint32_t XOSCFAIL1:1;      /*!< bit:      3  XOSC 1 Clock Failure Detector Interrupt Enable */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready Interrupt Enable        */
-    uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds Interrupt Enable */
-    uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine Interrupt Enable    */
-    uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse Interrupt Enable  */
-    uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped Interrupt Enable */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t DPLL0LCKR:1;      /*!< bit:     16  DPLL0 Lock Rise Interrupt Enable   */
-    uint32_t DPLL0LCKF:1;      /*!< bit:     17  DPLL0 Lock Fall Interrupt Enable   */
-    uint32_t DPLL0LTO:1;       /*!< bit:     18  DPLL0 Lock Timeout Interrupt Enable */
-    uint32_t DPLL0LDRTO:1;     /*!< bit:     19  DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t DPLL1LCKR:1;      /*!< bit:     24  DPLL1 Lock Rise Interrupt Enable   */
-    uint32_t DPLL1LCKF:1;      /*!< bit:     25  DPLL1 Lock Fall Interrupt Enable   */
-    uint32_t DPLL1LTO:1;       /*!< bit:     26  DPLL1 Lock Timeout Interrupt Enable */
-    uint32_t DPLL1LDRTO:1;     /*!< bit:     27  DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t XOSCRDY:2;        /*!< bit:  0.. 1  XOSC x Ready Interrupt Enable      */
-    uint32_t XOSCFAIL:2;       /*!< bit:  2.. 3  XOSC x Clock Failure Detector Interrupt Enable */
-    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_INTENCLR_OFFSET     0x04         /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */
-#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define OSCCTRL_INTENCLR_XOSCRDY0_Pos 0            /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCRDY0   (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)
-#define OSCCTRL_INTENCLR_XOSCRDY1_Pos 1            /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCRDY1   (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)
-#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0            /**< \brief (OSCCTRL_INTENCLR) XOSC x Ready Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos)
-#define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))
-#define OSCCTRL_INTENCLR_XOSCFAIL0_Pos 2            /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCFAIL0  (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)
-#define OSCCTRL_INTENCLR_XOSCFAIL1_Pos 3            /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCFAIL1  (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)
-#define OSCCTRL_INTENCLR_XOSCFAIL_Pos 2            /**< \brief (OSCCTRL_INTENCLR) XOSC x Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)
-#define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))
-#define OSCCTRL_INTENCLR_DFLLRDY_Pos 8            /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLRDY    (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)
-#define OSCCTRL_INTENCLR_DFLLOOB_Pos 9            /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLOOB    (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)
-#define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLLCKF   (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)
-#define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLLCKC   (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)
-#define OSCCTRL_INTENCLR_DFLLRCS_Pos 12           /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
-#define OSCCTRL_INTENCLR_DFLLRCS    (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)
-#define OSCCTRL_INTENCLR_DPLL0LCKR_Pos 16           /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL0LCKR  (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)
-#define OSCCTRL_INTENCLR_DPLL0LCKF_Pos 17           /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL0LCKF  (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)
-#define OSCCTRL_INTENCLR_DPLL0LTO_Pos 18           /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL0LTO   (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)
-#define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos 19           /**< \brief (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)
-#define OSCCTRL_INTENCLR_DPLL1LCKR_Pos 24           /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL1LCKR  (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)
-#define OSCCTRL_INTENCLR_DPLL1LCKF_Pos 25           /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL1LCKF  (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)
-#define OSCCTRL_INTENCLR_DPLL1LTO_Pos 26           /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL1LTO   (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)
-#define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos 27           /**< \brief (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
-#define OSCCTRL_INTENCLR_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)
-#define OSCCTRL_INTENCLR_MASK       _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENCLR) MASK Register */
-
-/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t XOSCRDY0:1;       /*!< bit:      0  XOSC 0 Ready Interrupt Enable      */
-    uint32_t XOSCRDY1:1;       /*!< bit:      1  XOSC 1 Ready Interrupt Enable      */
-    uint32_t XOSCFAIL0:1;      /*!< bit:      2  XOSC 0 Clock Failure Detector Interrupt Enable */
-    uint32_t XOSCFAIL1:1;      /*!< bit:      3  XOSC 1 Clock Failure Detector Interrupt Enable */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready Interrupt Enable        */
-    uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds Interrupt Enable */
-    uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine Interrupt Enable    */
-    uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse Interrupt Enable  */
-    uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped Interrupt Enable */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t DPLL0LCKR:1;      /*!< bit:     16  DPLL0 Lock Rise Interrupt Enable   */
-    uint32_t DPLL0LCKF:1;      /*!< bit:     17  DPLL0 Lock Fall Interrupt Enable   */
-    uint32_t DPLL0LTO:1;       /*!< bit:     18  DPLL0 Lock Timeout Interrupt Enable */
-    uint32_t DPLL0LDRTO:1;     /*!< bit:     19  DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t DPLL1LCKR:1;      /*!< bit:     24  DPLL1 Lock Rise Interrupt Enable   */
-    uint32_t DPLL1LCKF:1;      /*!< bit:     25  DPLL1 Lock Fall Interrupt Enable   */
-    uint32_t DPLL1LTO:1;       /*!< bit:     26  DPLL1 Lock Timeout Interrupt Enable */
-    uint32_t DPLL1LDRTO:1;     /*!< bit:     27  DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t XOSCRDY:2;        /*!< bit:  0.. 1  XOSC x Ready Interrupt Enable      */
-    uint32_t XOSCFAIL:2;       /*!< bit:  2.. 3  XOSC x Clock Failure Detector Interrupt Enable */
-    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_INTENSET_OFFSET     0x08         /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */
-#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */
-
-#define OSCCTRL_INTENSET_XOSCRDY0_Pos 0            /**< \brief (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCRDY0   (_U_(1) << OSCCTRL_INTENSET_XOSCRDY0_Pos)
-#define OSCCTRL_INTENSET_XOSCRDY1_Pos 1            /**< \brief (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCRDY1   (_U_(1) << OSCCTRL_INTENSET_XOSCRDY1_Pos)
-#define OSCCTRL_INTENSET_XOSCRDY_Pos 0            /**< \brief (OSCCTRL_INTENSET) XOSC x Ready Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos)
-#define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))
-#define OSCCTRL_INTENSET_XOSCFAIL0_Pos 2            /**< \brief (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCFAIL0  (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)
-#define OSCCTRL_INTENSET_XOSCFAIL1_Pos 3            /**< \brief (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCFAIL1  (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)
-#define OSCCTRL_INTENSET_XOSCFAIL_Pos 2            /**< \brief (OSCCTRL_INTENSET) XOSC x Clock Failure Detector Interrupt Enable */
-#define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos)
-#define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))
-#define OSCCTRL_INTENSET_DFLLRDY_Pos 8            /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLRDY    (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)
-#define OSCCTRL_INTENSET_DFLLOOB_Pos 9            /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLOOB    (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)
-#define OSCCTRL_INTENSET_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLLCKF   (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)
-#define OSCCTRL_INTENSET_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLLCKC   (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)
-#define OSCCTRL_INTENSET_DFLLRCS_Pos 12           /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
-#define OSCCTRL_INTENSET_DFLLRCS    (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)
-#define OSCCTRL_INTENSET_DPLL0LCKR_Pos 16           /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL0LCKR  (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)
-#define OSCCTRL_INTENSET_DPLL0LCKF_Pos 17           /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL0LCKF  (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)
-#define OSCCTRL_INTENSET_DPLL0LTO_Pos 18           /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL0LTO   (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos)
-#define OSCCTRL_INTENSET_DPLL0LDRTO_Pos 19           /**< \brief (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)
-#define OSCCTRL_INTENSET_DPLL1LCKR_Pos 24           /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL1LCKR  (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)
-#define OSCCTRL_INTENSET_DPLL1LCKF_Pos 25           /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL1LCKF  (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)
-#define OSCCTRL_INTENSET_DPLL1LTO_Pos 26           /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL1LTO   (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos)
-#define OSCCTRL_INTENSET_DPLL1LDRTO_Pos 27           /**< \brief (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
-#define OSCCTRL_INTENSET_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)
-#define OSCCTRL_INTENSET_MASK       _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENSET) MASK Register */
-
-/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t XOSCRDY0:1;       /*!< bit:      0  XOSC 0 Ready                       */
-    __I uint32_t XOSCRDY1:1;       /*!< bit:      1  XOSC 1 Ready                       */
-    __I uint32_t XOSCFAIL0:1;      /*!< bit:      2  XOSC 0 Clock Failure Detector      */
-    __I uint32_t XOSCFAIL1:1;      /*!< bit:      3  XOSC 1 Clock Failure Detector      */
-    __I uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    __I uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready                         */
-    __I uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds                 */
-    __I uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine                     */
-    __I uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse                   */
-    __I uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped       */
-    __I uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    __I uint32_t DPLL0LCKR:1;      /*!< bit:     16  DPLL0 Lock Rise                    */
-    __I uint32_t DPLL0LCKF:1;      /*!< bit:     17  DPLL0 Lock Fall                    */
-    __I uint32_t DPLL0LTO:1;       /*!< bit:     18  DPLL0 Lock Timeout                 */
-    __I uint32_t DPLL0LDRTO:1;     /*!< bit:     19  DPLL0 Loop Divider Ratio Update Complete */
-    __I uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    __I uint32_t DPLL1LCKR:1;      /*!< bit:     24  DPLL1 Lock Rise                    */
-    __I uint32_t DPLL1LCKF:1;      /*!< bit:     25  DPLL1 Lock Fall                    */
-    __I uint32_t DPLL1LTO:1;       /*!< bit:     26  DPLL1 Lock Timeout                 */
-    __I uint32_t DPLL1LDRTO:1;     /*!< bit:     27  DPLL1 Loop Divider Ratio Update Complete */
-    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint32_t XOSCRDY:2;        /*!< bit:  0.. 1  XOSC x Ready                       */
-    __I uint32_t XOSCFAIL:2;       /*!< bit:  2.. 3  XOSC x Clock Failure Detector      */
-    __I uint32_t :28;              /*!< bit:  4..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_INTFLAG_OFFSET      0x0C         /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define OSCCTRL_INTFLAG_RESETVALUE  _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define OSCCTRL_INTFLAG_XOSCRDY0_Pos 0            /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Ready */
-#define OSCCTRL_INTFLAG_XOSCRDY0    (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)
-#define OSCCTRL_INTFLAG_XOSCRDY1_Pos 1            /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Ready */
-#define OSCCTRL_INTFLAG_XOSCRDY1    (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)
-#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0            /**< \brief (OSCCTRL_INTFLAG) XOSC x Ready */
-#define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos)
-#define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))
-#define OSCCTRL_INTFLAG_XOSCFAIL0_Pos 2            /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector */
-#define OSCCTRL_INTFLAG_XOSCFAIL0   (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)
-#define OSCCTRL_INTFLAG_XOSCFAIL1_Pos 3            /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector */
-#define OSCCTRL_INTFLAG_XOSCFAIL1   (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)
-#define OSCCTRL_INTFLAG_XOSCFAIL_Pos 2            /**< \brief (OSCCTRL_INTFLAG) XOSC x Clock Failure Detector */
-#define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)
-#define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))
-#define OSCCTRL_INTFLAG_DFLLRDY_Pos 8            /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */
-#define OSCCTRL_INTFLAG_DFLLRDY     (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)
-#define OSCCTRL_INTFLAG_DFLLOOB_Pos 9            /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */
-#define OSCCTRL_INTFLAG_DFLLOOB     (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)
-#define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */
-#define OSCCTRL_INTFLAG_DFLLLCKF    (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)
-#define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */
-#define OSCCTRL_INTFLAG_DFLLLCKC    (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)
-#define OSCCTRL_INTFLAG_DFLLRCS_Pos 12           /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */
-#define OSCCTRL_INTFLAG_DFLLRCS     (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)
-#define OSCCTRL_INTFLAG_DPLL0LCKR_Pos 16           /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Rise */
-#define OSCCTRL_INTFLAG_DPLL0LCKR   (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)
-#define OSCCTRL_INTFLAG_DPLL0LCKF_Pos 17           /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Fall */
-#define OSCCTRL_INTFLAG_DPLL0LCKF   (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)
-#define OSCCTRL_INTFLAG_DPLL0LTO_Pos 18           /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Timeout */
-#define OSCCTRL_INTFLAG_DPLL0LTO    (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)
-#define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos 19           /**< \brief (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete */
-#define OSCCTRL_INTFLAG_DPLL0LDRTO  (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)
-#define OSCCTRL_INTFLAG_DPLL1LCKR_Pos 24           /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Rise */
-#define OSCCTRL_INTFLAG_DPLL1LCKR   (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)
-#define OSCCTRL_INTFLAG_DPLL1LCKF_Pos 25           /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Fall */
-#define OSCCTRL_INTFLAG_DPLL1LCKF   (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)
-#define OSCCTRL_INTFLAG_DPLL1LTO_Pos 26           /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Timeout */
-#define OSCCTRL_INTFLAG_DPLL1LTO    (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)
-#define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos 27           /**< \brief (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete */
-#define OSCCTRL_INTFLAG_DPLL1LDRTO  (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)
-#define OSCCTRL_INTFLAG_MASK        _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTFLAG) MASK Register */
-
-/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) (R/  32) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t XOSCRDY0:1;       /*!< bit:      0  XOSC 0 Ready                       */
-    uint32_t XOSCRDY1:1;       /*!< bit:      1  XOSC 1 Ready                       */
-    uint32_t XOSCFAIL0:1;      /*!< bit:      2  XOSC 0 Clock Failure Detector      */
-    uint32_t XOSCFAIL1:1;      /*!< bit:      3  XOSC 1 Clock Failure Detector      */
-    uint32_t XOSCCKSW0:1;      /*!< bit:      4  XOSC 0 Clock Switch                */
-    uint32_t XOSCCKSW1:1;      /*!< bit:      5  XOSC 1 Clock Switch                */
-    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready                         */
-    uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds                 */
-    uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine                     */
-    uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse                   */
-    uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped       */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t DPLL0LCKR:1;      /*!< bit:     16  DPLL0 Lock Rise                    */
-    uint32_t DPLL0LCKF:1;      /*!< bit:     17  DPLL0 Lock Fall                    */
-    uint32_t DPLL0TO:1;        /*!< bit:     18  DPLL0 Timeout                      */
-    uint32_t DPLL0LDRTO:1;     /*!< bit:     19  DPLL0 Loop Divider Ratio Update Complete */
-    uint32_t :4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t DPLL1LCKR:1;      /*!< bit:     24  DPLL1 Lock Rise                    */
-    uint32_t DPLL1LCKF:1;      /*!< bit:     25  DPLL1 Lock Fall                    */
-    uint32_t DPLL1TO:1;        /*!< bit:     26  DPLL1 Timeout                      */
-    uint32_t DPLL1LDRTO:1;     /*!< bit:     27  DPLL1 Loop Divider Ratio Update Complete */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t XOSCRDY:2;        /*!< bit:  0.. 1  XOSC x Ready                       */
-    uint32_t XOSCFAIL:2;       /*!< bit:  2.. 3  XOSC x Clock Failure Detector      */
-    uint32_t XOSCCKSW:2;       /*!< bit:  4.. 5  XOSC x Clock Switch                */
-    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_STATUS_OFFSET       0x10         /**< \brief (OSCCTRL_STATUS offset) Status */
-#define OSCCTRL_STATUS_RESETVALUE   _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Status */
-
-#define OSCCTRL_STATUS_XOSCRDY0_Pos 0            /**< \brief (OSCCTRL_STATUS) XOSC 0 Ready */
-#define OSCCTRL_STATUS_XOSCRDY0     (_U_(1) << OSCCTRL_STATUS_XOSCRDY0_Pos)
-#define OSCCTRL_STATUS_XOSCRDY1_Pos 1            /**< \brief (OSCCTRL_STATUS) XOSC 1 Ready */
-#define OSCCTRL_STATUS_XOSCRDY1     (_U_(1) << OSCCTRL_STATUS_XOSCRDY1_Pos)
-#define OSCCTRL_STATUS_XOSCRDY_Pos  0            /**< \brief (OSCCTRL_STATUS) XOSC x Ready */
-#define OSCCTRL_STATUS_XOSCRDY_Msk  (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos)
-#define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))
-#define OSCCTRL_STATUS_XOSCFAIL0_Pos 2            /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector */
-#define OSCCTRL_STATUS_XOSCFAIL0    (_U_(1) << OSCCTRL_STATUS_XOSCFAIL0_Pos)
-#define OSCCTRL_STATUS_XOSCFAIL1_Pos 3            /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector */
-#define OSCCTRL_STATUS_XOSCFAIL1    (_U_(1) << OSCCTRL_STATUS_XOSCFAIL1_Pos)
-#define OSCCTRL_STATUS_XOSCFAIL_Pos 2            /**< \brief (OSCCTRL_STATUS) XOSC x Clock Failure Detector */
-#define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos)
-#define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))
-#define OSCCTRL_STATUS_XOSCCKSW0_Pos 4            /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Switch */
-#define OSCCTRL_STATUS_XOSCCKSW0    (_U_(1) << OSCCTRL_STATUS_XOSCCKSW0_Pos)
-#define OSCCTRL_STATUS_XOSCCKSW1_Pos 5            /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Switch */
-#define OSCCTRL_STATUS_XOSCCKSW1    (_U_(1) << OSCCTRL_STATUS_XOSCCKSW1_Pos)
-#define OSCCTRL_STATUS_XOSCCKSW_Pos 4            /**< \brief (OSCCTRL_STATUS) XOSC x Clock Switch */
-#define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos)
-#define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))
-#define OSCCTRL_STATUS_DFLLRDY_Pos  8            /**< \brief (OSCCTRL_STATUS) DFLL Ready */
-#define OSCCTRL_STATUS_DFLLRDY      (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)
-#define OSCCTRL_STATUS_DFLLOOB_Pos  9            /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */
-#define OSCCTRL_STATUS_DFLLOOB      (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)
-#define OSCCTRL_STATUS_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */
-#define OSCCTRL_STATUS_DFLLLCKF     (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)
-#define OSCCTRL_STATUS_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */
-#define OSCCTRL_STATUS_DFLLLCKC     (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)
-#define OSCCTRL_STATUS_DFLLRCS_Pos  12           /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */
-#define OSCCTRL_STATUS_DFLLRCS      (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)
-#define OSCCTRL_STATUS_DPLL0LCKR_Pos 16           /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Rise */
-#define OSCCTRL_STATUS_DPLL0LCKR    (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos)
-#define OSCCTRL_STATUS_DPLL0LCKF_Pos 17           /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Fall */
-#define OSCCTRL_STATUS_DPLL0LCKF    (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos)
-#define OSCCTRL_STATUS_DPLL0TO_Pos  18           /**< \brief (OSCCTRL_STATUS) DPLL0 Timeout */
-#define OSCCTRL_STATUS_DPLL0TO      (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos)
-#define OSCCTRL_STATUS_DPLL0LDRTO_Pos 19           /**< \brief (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete */
-#define OSCCTRL_STATUS_DPLL0LDRTO   (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos)
-#define OSCCTRL_STATUS_DPLL1LCKR_Pos 24           /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Rise */
-#define OSCCTRL_STATUS_DPLL1LCKR    (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos)
-#define OSCCTRL_STATUS_DPLL1LCKF_Pos 25           /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Fall */
-#define OSCCTRL_STATUS_DPLL1LCKF    (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos)
-#define OSCCTRL_STATUS_DPLL1TO_Pos  26           /**< \brief (OSCCTRL_STATUS) DPLL1 Timeout */
-#define OSCCTRL_STATUS_DPLL1TO      (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos)
-#define OSCCTRL_STATUS_DPLL1LDRTO_Pos 27           /**< \brief (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete */
-#define OSCCTRL_STATUS_DPLL1LDRTO   (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos)
-#define OSCCTRL_STATUS_MASK         _U_(0x0F0F1F3F) /**< \brief (OSCCTRL_STATUS) MASK Register */
-
-/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
-    uint32_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
-    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-    uint32_t LOWBUFGAIN:1;     /*!< bit:      8  Low Buffer Gain Enable             */
-    uint32_t IPTAT:2;          /*!< bit:  9..10  Oscillator Current Reference       */
-    uint32_t IMULT:4;          /*!< bit: 11..14  Oscillator Current Multiplier      */
-    uint32_t ENALC:1;          /*!< bit:     15  Automatic Loop Control Enable      */
-    uint32_t CFDEN:1;          /*!< bit:     16  Clock Failure Detector Enable      */
-    uint32_t SWBEN:1;          /*!< bit:     17  Xosc Clock Switch Enable           */
-    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
-    uint32_t STARTUP:4;        /*!< bit: 20..23  Start-Up Time                      */
-    uint32_t CFDPRESC:4;       /*!< bit: 24..27  Clock Failure Detector Prescaler   */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_XOSCCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_XOSCCTRL_OFFSET     0x14         /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator Control */
-#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x00000080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator Control */
-
-#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1            /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */
-#define OSCCTRL_XOSCCTRL_ENABLE     (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)
-#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2            /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */
-#define OSCCTRL_XOSCCTRL_XTALEN     (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)
-#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */
-#define OSCCTRL_XOSCCTRL_RUNSTDBY   (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
-#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */
-#define OSCCTRL_XOSCCTRL_ONDEMAND   (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
-#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos 8            /**< \brief (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable */
-#define OSCCTRL_XOSCCTRL_LOWBUFGAIN (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
-#define OSCCTRL_XOSCCTRL_IPTAT_Pos  9            /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Reference */
-#define OSCCTRL_XOSCCTRL_IPTAT_Msk  (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos)
-#define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
-#define OSCCTRL_XOSCCTRL_IMULT_Pos  11           /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier */
-#define OSCCTRL_XOSCCTRL_IMULT_Msk  (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos)
-#define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
-#define OSCCTRL_XOSCCTRL_ENALC_Pos  15           /**< \brief (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable */
-#define OSCCTRL_XOSCCTRL_ENALC      (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos)
-#define OSCCTRL_XOSCCTRL_CFDEN_Pos  16           /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable */
-#define OSCCTRL_XOSCCTRL_CFDEN      (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)
-#define OSCCTRL_XOSCCTRL_SWBEN_Pos  17           /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable */
-#define OSCCTRL_XOSCCTRL_SWBEN      (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)
-#define OSCCTRL_XOSCCTRL_STARTUP_Pos 20           /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */
-#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)
-#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
-#define OSCCTRL_XOSCCTRL_CFDPRESC_Pos 24           /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler */
-#define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)
-#define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
-#define OSCCTRL_XOSCCTRL_MASK       _U_(0x0FF3FFC6) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */
-
-/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W  8) DFLL48M Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  ENABLE:1;         /*!< bit:      1  DFLL Enable                        */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} OSCCTRL_DFLLCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLCTRLA_OFFSET    0x1C         /**< \brief (OSCCTRL_DFLLCTRLA offset) DFLL48M Control A */
-#define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82)    /**< \brief (OSCCTRL_DFLLCTRLA reset_value) DFLL48M Control A */
-
-#define OSCCTRL_DFLLCTRLA_ENABLE_Pos 1            /**< \brief (OSCCTRL_DFLLCTRLA) DFLL Enable */
-#define OSCCTRL_DFLLCTRLA_ENABLE    (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)
-#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_DFLLCTRLA) Run in Standby */
-#define OSCCTRL_DFLLCTRLA_RUNSTDBY  (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)
-#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_DFLLCTRLA) On Demand Control */
-#define OSCCTRL_DFLLCTRLA_ONDEMAND  (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)
-#define OSCCTRL_DFLLCTRLA_MASK      _U_(0xC2)    /**< \brief (OSCCTRL_DFLLCTRLA) MASK Register */
-
-/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W  8) DFLL48M Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  MODE:1;           /*!< bit:      0  Operating Mode Selection           */
-    uint8_t  STABLE:1;         /*!< bit:      1  Stable DFLL Frequency              */
-    uint8_t  LLAW:1;           /*!< bit:      2  Lose Lock After Wake               */
-    uint8_t  USBCRM:1;         /*!< bit:      3  USB Clock Recovery Mode            */
-    uint8_t  CCDIS:1;          /*!< bit:      4  Chill Cycle Disable                */
-    uint8_t  QLDIS:1;          /*!< bit:      5  Quick Lock Disable                 */
-    uint8_t  BPLCKC:1;         /*!< bit:      6  Bypass Coarse Lock                 */
-    uint8_t  WAITLOCK:1;       /*!< bit:      7  Wait Lock                          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} OSCCTRL_DFLLCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLCTRLB_OFFSET    0x20         /**< \brief (OSCCTRL_DFLLCTRLB offset) DFLL48M Control B */
-#define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00)    /**< \brief (OSCCTRL_DFLLCTRLB reset_value) DFLL48M Control B */
-
-#define OSCCTRL_DFLLCTRLB_MODE_Pos  0            /**< \brief (OSCCTRL_DFLLCTRLB) Operating Mode Selection */
-#define OSCCTRL_DFLLCTRLB_MODE      (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos)
-#define OSCCTRL_DFLLCTRLB_STABLE_Pos 1            /**< \brief (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency */
-#define OSCCTRL_DFLLCTRLB_STABLE    (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)
-#define OSCCTRL_DFLLCTRLB_LLAW_Pos  2            /**< \brief (OSCCTRL_DFLLCTRLB) Lose Lock After Wake */
-#define OSCCTRL_DFLLCTRLB_LLAW      (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)
-#define OSCCTRL_DFLLCTRLB_USBCRM_Pos 3            /**< \brief (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode */
-#define OSCCTRL_DFLLCTRLB_USBCRM    (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)
-#define OSCCTRL_DFLLCTRLB_CCDIS_Pos 4            /**< \brief (OSCCTRL_DFLLCTRLB) Chill Cycle Disable */
-#define OSCCTRL_DFLLCTRLB_CCDIS     (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
-#define OSCCTRL_DFLLCTRLB_QLDIS_Pos 5            /**< \brief (OSCCTRL_DFLLCTRLB) Quick Lock Disable */
-#define OSCCTRL_DFLLCTRLB_QLDIS     (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)
-#define OSCCTRL_DFLLCTRLB_BPLCKC_Pos 6            /**< \brief (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock */
-#define OSCCTRL_DFLLCTRLB_BPLCKC    (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
-#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos 7            /**< \brief (OSCCTRL_DFLLCTRLB) Wait Lock */
-#define OSCCTRL_DFLLCTRLB_WAITLOCK  (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)
-#define OSCCTRL_DFLLCTRLB_MASK      _U_(0xFF)    /**< \brief (OSCCTRL_DFLLCTRLB) MASK Register */
-
-/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t FINE:8;           /*!< bit:  0.. 7  Fine Value                         */
-    uint32_t :2;               /*!< bit:  8.. 9  Reserved                           */
-    uint32_t COARSE:6;         /*!< bit: 10..15  Coarse Value                       */
-    uint32_t DIFF:16;          /*!< bit: 16..31  Multiplication Ratio Difference    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_DFLLVAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLVAL_OFFSET      0x24         /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */
-#define OSCCTRL_DFLLVAL_RESETVALUE  _U_(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */
-
-#define OSCCTRL_DFLLVAL_FINE_Pos    0            /**< \brief (OSCCTRL_DFLLVAL) Fine Value */
-#define OSCCTRL_DFLLVAL_FINE_Msk    (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos)
-#define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
-#define OSCCTRL_DFLLVAL_COARSE_Pos  10           /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */
-#define OSCCTRL_DFLLVAL_COARSE_Msk  (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)
-#define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
-#define OSCCTRL_DFLLVAL_DIFF_Pos    16           /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */
-#define OSCCTRL_DFLLVAL_DIFF_Msk    (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)
-#define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
-#define OSCCTRL_DFLLVAL_MASK        _U_(0xFFFFFCFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */
-
-/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t MUL:16;           /*!< bit:  0..15  DFLL Multiply Factor               */
-    uint32_t FSTEP:8;          /*!< bit: 16..23  Fine Maximum Step                  */
-    uint32_t :2;               /*!< bit: 24..25  Reserved                           */
-    uint32_t CSTEP:6;          /*!< bit: 26..31  Coarse Maximum Step                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_DFLLMUL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLMUL_OFFSET      0x28         /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */
-#define OSCCTRL_DFLLMUL_RESETVALUE  _U_(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
-
-#define OSCCTRL_DFLLMUL_MUL_Pos     0            /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */
-#define OSCCTRL_DFLLMUL_MUL_Msk     (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)
-#define OSCCTRL_DFLLMUL_MUL(value)  (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
-#define OSCCTRL_DFLLMUL_FSTEP_Pos   16           /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */
-#define OSCCTRL_DFLLMUL_FSTEP_Msk   (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos)
-#define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
-#define OSCCTRL_DFLLMUL_CSTEP_Pos   26           /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */
-#define OSCCTRL_DFLLMUL_CSTEP_Msk   (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)
-#define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
-#define OSCCTRL_DFLLMUL_MASK        _U_(0xFCFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */
-
-/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W  8) DFLL48M Synchronization -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  ENABLE:1;         /*!< bit:      1  ENABLE Synchronization Busy        */
-    uint8_t  DFLLCTRLB:1;      /*!< bit:      2  DFLLCTRLB Synchronization Busy     */
-    uint8_t  DFLLVAL:1;        /*!< bit:      3  DFLLVAL Synchronization Busy       */
-    uint8_t  DFLLMUL:1;        /*!< bit:      4  DFLLMUL Synchronization Busy       */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} OSCCTRL_DFLLSYNC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DFLLSYNC_OFFSET     0x2C         /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */
-#define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00)    /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
-
-#define OSCCTRL_DFLLSYNC_ENABLE_Pos 1            /**< \brief (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy */
-#define OSCCTRL_DFLLSYNC_ENABLE     (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos)
-#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos 2            /**< \brief (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy */
-#define OSCCTRL_DFLLSYNC_DFLLCTRLB  (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)
-#define OSCCTRL_DFLLSYNC_DFLLVAL_Pos 3            /**< \brief (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy */
-#define OSCCTRL_DFLLSYNC_DFLLVAL    (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)
-#define OSCCTRL_DFLLSYNC_DFLLMUL_Pos 4            /**< \brief (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy */
-#define OSCCTRL_DFLLSYNC_DFLLMUL    (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)
-#define OSCCTRL_DFLLSYNC_MASK       _U_(0x1E)    /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */
-
-/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x30) (R/W  8) DPLL DPLL Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  ENABLE:1;         /*!< bit:      1  DPLL Enable                        */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} OSCCTRL_DPLLCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLCTRLA_OFFSET    0x30         /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control A */
-#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80)    /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control A */
-
-#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1            /**< \brief (OSCCTRL_DPLLCTRLA) DPLL Enable */
-#define OSCCTRL_DPLLCTRLA_ENABLE    (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)
-#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */
-#define OSCCTRL_DPLLCTRLA_RUNSTDBY  (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
-#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_DPLLCTRLA) On Demand Control */
-#define OSCCTRL_DPLLCTRLA_ONDEMAND  (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
-#define OSCCTRL_DPLLCTRLA_MASK      _U_(0xC2)    /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */
-
-/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x34) (R/W 32) DPLL DPLL Ratio Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LDR:13;           /*!< bit:  0..12  Loop Divider Ratio                 */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t LDRFRAC:5;        /*!< bit: 16..20  Loop Divider Ratio Fractional Part */
-    uint32_t :11;              /*!< bit: 21..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_DPLLRATIO_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLRATIO_OFFSET    0x34         /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */
-#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
-
-#define OSCCTRL_DPLLRATIO_LDR_Pos   0            /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */
-#define OSCCTRL_DPLLRATIO_LDR_Msk   (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos)
-#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
-#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16           /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
-#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)
-#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
-#define OSCCTRL_DPLLRATIO_MASK      _U_(0x001F1FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */
-
-/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x38) (R/W 32) DPLL DPLL Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t FILTER:4;         /*!< bit:  0.. 3  Proportional Integral Filter Selection */
-    uint32_t WUF:1;            /*!< bit:      4  Wake Up Fast                       */
-    uint32_t REFCLK:3;         /*!< bit:  5.. 7  Reference Clock Selection          */
-    uint32_t LTIME:3;          /*!< bit:  8..10  Lock Time                          */
-    uint32_t LBYPASS:1;        /*!< bit:     11  Lock Bypass                        */
-    uint32_t DCOFILTER:3;      /*!< bit: 12..14  Sigma-Delta DCO Filter Selection   */
-    uint32_t DCOEN:1;          /*!< bit:     15  DCO Filter Enable                  */
-    uint32_t DIV:11;           /*!< bit: 16..26  Clock Divider                      */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_DPLLCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLCTRLB_OFFSET    0x38         /**< \brief (OSCCTRL_DPLLCTRLB offset) DPLL Control B */
-#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000020) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) DPLL Control B */
-
-#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0            /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
-#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos)
-#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
-#define OSCCTRL_DPLLCTRLB_WUF_Pos   4            /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */
-#define OSCCTRL_DPLLCTRLB_WUF       (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 5            /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */
-#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
-#define   OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0)   /**< \brief (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */
-#define   OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1)   /**< \brief (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */
-#define   OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2)   /**< \brief (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */
-#define   OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3)   /**< \brief (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */
-#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8            /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */
-#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
-#define   OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0)   /**< \brief (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */
-#define   OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4)   /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */
-#define   OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5)   /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */
-#define   OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6)   /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */
-#define   OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7)   /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */
-#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
-#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 11           /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */
-#define OSCCTRL_DPLLCTRLB_LBYPASS   (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
-#define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos 12           /**< \brief (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection */
-#define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)
-#define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
-#define OSCCTRL_DPLLCTRLB_DCOEN_Pos 15           /**< \brief (OSCCTRL_DPLLCTRLB) DCO Filter Enable */
-#define OSCCTRL_DPLLCTRLB_DCOEN     (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
-#define OSCCTRL_DPLLCTRLB_DIV_Pos   16           /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */
-#define OSCCTRL_DPLLCTRLB_DIV_Msk   (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)
-#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
-#define OSCCTRL_DPLLCTRLB_MASK      _U_(0x07FFFFFF) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */
-
-/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x3C) (R/  32) DPLL DPLL Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  DPLL Enable Synchronization Status */
-    uint32_t DPLLRATIO:1;      /*!< bit:      2  DPLL Loop Divider Ratio Synchronization Status */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_DPLLSYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x3C         /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */
-#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */
-
-#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1            /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */
-#define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)
-#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2            /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status */
-#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)
-#define OSCCTRL_DPLLSYNCBUSY_MASK   _U_(0x00000006) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */
-
-/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x40) (R/  32) DPLL DPLL Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t LOCK:1;           /*!< bit:      0  DPLL Lock Status                   */
-    uint32_t CLKRDY:1;         /*!< bit:      1  DPLL Clock Ready                   */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} OSCCTRL_DPLLSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define OSCCTRL_DPLLSTATUS_OFFSET   0x40         /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */
-#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */
-
-#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0            /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */
-#define OSCCTRL_DPLLSTATUS_LOCK     (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)
-#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1            /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */
-#define OSCCTRL_DPLLSTATUS_CLKRDY   (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)
-#define OSCCTRL_DPLLSTATUS_MASK     _U_(0x00000003) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */
-
-/** \brief OscctrlDpll hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO OSCCTRL_DPLLCTRLA_Type    DPLLCTRLA;   /**< \brief Offset: 0x00 (R/W  8) DPLL Control A */
-       RoReg8                    Reserved1[0x3];
-  __IO OSCCTRL_DPLLRATIO_Type    DPLLRATIO;   /**< \brief Offset: 0x04 (R/W 32) DPLL Ratio Control */
-  __IO OSCCTRL_DPLLCTRLB_Type    DPLLCTRLB;   /**< \brief Offset: 0x08 (R/W 32) DPLL Control B */
-  __I  OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x0C (R/  32) DPLL Synchronization Busy */
-  __I  OSCCTRL_DPLLSTATUS_Type   DPLLSTATUS;  /**< \brief Offset: 0x10 (R/  32) DPLL Status */
-} OscctrlDpll;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief OSCCTRL hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO OSCCTRL_EVCTRL_Type       EVCTRL;      /**< \brief Offset: 0x00 (R/W  8) Event Control */
-       RoReg8                    Reserved1[0x3];
-  __IO OSCCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Clear */
-  __IO OSCCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Set */
-  __IO OSCCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */
-  __I  OSCCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x10 (R/  32) Status */
-  __IO OSCCTRL_XOSCCTRL_Type     XOSCCTRL[2]; /**< \brief Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */
-  __IO OSCCTRL_DFLLCTRLA_Type    DFLLCTRLA;   /**< \brief Offset: 0x1C (R/W  8) DFLL48M Control A */
-       RoReg8                    Reserved2[0x3];
-  __IO OSCCTRL_DFLLCTRLB_Type    DFLLCTRLB;   /**< \brief Offset: 0x20 (R/W  8) DFLL48M Control B */
-       RoReg8                    Reserved3[0x3];
-  __IO OSCCTRL_DFLLVAL_Type      DFLLVAL;     /**< \brief Offset: 0x24 (R/W 32) DFLL48M Value */
-  __IO OSCCTRL_DFLLMUL_Type      DFLLMUL;     /**< \brief Offset: 0x28 (R/W 32) DFLL48M Multiplier */
-  __IO OSCCTRL_DFLLSYNC_Type     DFLLSYNC;    /**< \brief Offset: 0x2C (R/W  8) DFLL48M Synchronization */
-       RoReg8                    Reserved4[0x3];
-       OscctrlDpll               Dpll[2];     /**< \brief Offset: 0x30 OscctrlDpll groups [DPLLS_NUM] */
-} Oscctrl;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_OSCCTRL_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pac.h
deleted file mode 100644
index d8c27d2a41..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pac.h
+++ /dev/null
@@ -1,674 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for PAC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PAC_COMPONENT_
-#define _SAMD51_PAC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR PAC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_PAC Peripheral Access Controller */
-/*@{*/
-
-#define PAC_U2120
-#define REV_PAC                     0x120
-
-/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PERID:16;         /*!< bit:  0..15  Peripheral identifier              */
-    uint32_t KEY:8;            /*!< bit: 16..23  Peripheral access control key      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_WRCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_WRCTRL_OFFSET           0x00         /**< \brief (PAC_WRCTRL offset) Write control */
-#define PAC_WRCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */
-
-#define PAC_WRCTRL_PERID_Pos        0            /**< \brief (PAC_WRCTRL) Peripheral identifier */
-#define PAC_WRCTRL_PERID_Msk        (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
-#define PAC_WRCTRL_PERID(value)     (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
-#define PAC_WRCTRL_KEY_Pos          16           /**< \brief (PAC_WRCTRL) Peripheral access control key */
-#define PAC_WRCTRL_KEY_Msk          (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_KEY(value)       (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
-#define   PAC_WRCTRL_KEY_OFF_Val          _U_(0x0)   /**< \brief (PAC_WRCTRL) No action */
-#define   PAC_WRCTRL_KEY_CLR_Val          _U_(0x1)   /**< \brief (PAC_WRCTRL) Clear protection */
-#define   PAC_WRCTRL_KEY_SET_Val          _U_(0x2)   /**< \brief (PAC_WRCTRL) Set protection */
-#define   PAC_WRCTRL_KEY_SETLCK_Val       _U_(0x3)   /**< \brief (PAC_WRCTRL) Set and lock protection */
-#define PAC_WRCTRL_KEY_OFF          (PAC_WRCTRL_KEY_OFF_Val        << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_KEY_CLR          (PAC_WRCTRL_KEY_CLR_Val        << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_KEY_SET          (PAC_WRCTRL_KEY_SET_Val        << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_KEY_SETLCK       (PAC_WRCTRL_KEY_SETLCK_Val     << PAC_WRCTRL_KEY_Pos)
-#define PAC_WRCTRL_MASK             _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */
-
-/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W  8) Event control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ERREO:1;          /*!< bit:      0  Peripheral acess error event output */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PAC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_EVCTRL_OFFSET           0x04         /**< \brief (PAC_EVCTRL offset) Event control */
-#define PAC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (PAC_EVCTRL reset_value) Event control */
-
-#define PAC_EVCTRL_ERREO_Pos        0            /**< \brief (PAC_EVCTRL) Peripheral acess error event output */
-#define PAC_EVCTRL_ERREO            (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
-#define PAC_EVCTRL_MASK             _U_(0x01)    /**< \brief (PAC_EVCTRL) MASK Register */
-
-/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W  8) Interrupt enable clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ERR:1;            /*!< bit:      0  Peripheral access error interrupt disable */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PAC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTENCLR_OFFSET         0x08         /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */
-#define PAC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */
-
-#define PAC_INTENCLR_ERR_Pos        0            /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */
-#define PAC_INTENCLR_ERR            (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
-#define PAC_INTENCLR_MASK           _U_(0x01)    /**< \brief (PAC_INTENCLR) MASK Register */
-
-/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W  8) Interrupt enable set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ERR:1;            /*!< bit:      0  Peripheral access error interrupt enable */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PAC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTENSET_OFFSET         0x09         /**< \brief (PAC_INTENSET offset) Interrupt enable set */
-#define PAC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */
-
-#define PAC_INTENSET_ERR_Pos        0            /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */
-#define PAC_INTENSET_ERR            (_U_(0x1) << PAC_INTENSET_ERR_Pos)
-#define PAC_INTENSET_MASK           _U_(0x01)    /**< \brief (PAC_INTENSET) MASK Register */
-
-/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t FLASH_:1;         /*!< bit:      0  FLASH                              */
-    __I uint32_t FLASH_ALT_:1;     /*!< bit:      1  FLASH_ALT                          */
-    __I uint32_t SEEPROM_:1;       /*!< bit:      2  SEEPROM                            */
-    __I uint32_t RAMCM4S_:1;       /*!< bit:      3  RAMCM4S                            */
-    __I uint32_t RAMPPPDSU_:1;     /*!< bit:      4  RAMPPPDSU                          */
-    __I uint32_t RAMDMAWR_:1;      /*!< bit:      5  RAMDMAWR                           */
-    __I uint32_t RAMDMACICM_:1;    /*!< bit:      6  RAMDMACICM                         */
-    __I uint32_t HPB0_:1;          /*!< bit:      7  HPB0                               */
-    __I uint32_t HPB1_:1;          /*!< bit:      8  HPB1                               */
-    __I uint32_t HPB2_:1;          /*!< bit:      9  HPB2                               */
-    __I uint32_t HPB3_:1;          /*!< bit:     10  HPB3                               */
-    __I uint32_t PUKCC_:1;         /*!< bit:     11  PUKCC                              */
-    __I uint32_t SDHC0_:1;         /*!< bit:     12  SDHC0                              */
-    __I uint32_t SDHC1_:1;         /*!< bit:     13  SDHC1                              */
-    __I uint32_t QSPI_:1;          /*!< bit:     14  QSPI                               */
-    __I uint32_t BKUPRAM_:1;       /*!< bit:     15  BKUPRAM                            */
-    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_INTFLAGAHB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGAHB_OFFSET       0x10         /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */
-#define PAC_INTFLAGAHB_RESETVALUE   _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */
-
-#define PAC_INTFLAGAHB_FLASH_Pos    0            /**< \brief (PAC_INTFLAGAHB) FLASH */
-#define PAC_INTFLAGAHB_FLASH        (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
-#define PAC_INTFLAGAHB_FLASH_ALT_Pos 1            /**< \brief (PAC_INTFLAGAHB) FLASH_ALT */
-#define PAC_INTFLAGAHB_FLASH_ALT    (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos)
-#define PAC_INTFLAGAHB_SEEPROM_Pos  2            /**< \brief (PAC_INTFLAGAHB) SEEPROM */
-#define PAC_INTFLAGAHB_SEEPROM      (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos)
-#define PAC_INTFLAGAHB_RAMCM4S_Pos  3            /**< \brief (PAC_INTFLAGAHB) RAMCM4S */
-#define PAC_INTFLAGAHB_RAMCM4S      (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos)
-#define PAC_INTFLAGAHB_RAMPPPDSU_Pos 4            /**< \brief (PAC_INTFLAGAHB) RAMPPPDSU */
-#define PAC_INTFLAGAHB_RAMPPPDSU    (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos)
-#define PAC_INTFLAGAHB_RAMDMAWR_Pos 5            /**< \brief (PAC_INTFLAGAHB) RAMDMAWR */
-#define PAC_INTFLAGAHB_RAMDMAWR     (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos)
-#define PAC_INTFLAGAHB_RAMDMACICM_Pos 6            /**< \brief (PAC_INTFLAGAHB) RAMDMACICM */
-#define PAC_INTFLAGAHB_RAMDMACICM   (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos)
-#define PAC_INTFLAGAHB_HPB0_Pos     7            /**< \brief (PAC_INTFLAGAHB) HPB0 */
-#define PAC_INTFLAGAHB_HPB0         (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
-#define PAC_INTFLAGAHB_HPB1_Pos     8            /**< \brief (PAC_INTFLAGAHB) HPB1 */
-#define PAC_INTFLAGAHB_HPB1         (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
-#define PAC_INTFLAGAHB_HPB2_Pos     9            /**< \brief (PAC_INTFLAGAHB) HPB2 */
-#define PAC_INTFLAGAHB_HPB2         (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
-#define PAC_INTFLAGAHB_HPB3_Pos     10           /**< \brief (PAC_INTFLAGAHB) HPB3 */
-#define PAC_INTFLAGAHB_HPB3         (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos)
-#define PAC_INTFLAGAHB_PUKCC_Pos    11           /**< \brief (PAC_INTFLAGAHB) PUKCC */
-#define PAC_INTFLAGAHB_PUKCC        (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos)
-#define PAC_INTFLAGAHB_SDHC0_Pos    12           /**< \brief (PAC_INTFLAGAHB) SDHC0 */
-#define PAC_INTFLAGAHB_SDHC0        (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos)
-#define PAC_INTFLAGAHB_SDHC1_Pos    13           /**< \brief (PAC_INTFLAGAHB) SDHC1 */
-#define PAC_INTFLAGAHB_SDHC1        (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos)
-#define PAC_INTFLAGAHB_QSPI_Pos     14           /**< \brief (PAC_INTFLAGAHB) QSPI */
-#define PAC_INTFLAGAHB_QSPI         (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos)
-#define PAC_INTFLAGAHB_BKUPRAM_Pos  15           /**< \brief (PAC_INTFLAGAHB) BKUPRAM */
-#define PAC_INTFLAGAHB_BKUPRAM      (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos)
-#define PAC_INTFLAGAHB_MASK         _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGAHB) MASK Register */
-
-/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t PAC_:1;           /*!< bit:      0  PAC                                */
-    __I uint32_t PM_:1;            /*!< bit:      1  PM                                 */
-    __I uint32_t MCLK_:1;          /*!< bit:      2  MCLK                               */
-    __I uint32_t RSTC_:1;          /*!< bit:      3  RSTC                               */
-    __I uint32_t OSCCTRL_:1;       /*!< bit:      4  OSCCTRL                            */
-    __I uint32_t OSC32KCTRL_:1;    /*!< bit:      5  OSC32KCTRL                         */
-    __I uint32_t SUPC_:1;          /*!< bit:      6  SUPC                               */
-    __I uint32_t GCLK_:1;          /*!< bit:      7  GCLK                               */
-    __I uint32_t WDT_:1;           /*!< bit:      8  WDT                                */
-    __I uint32_t RTC_:1;           /*!< bit:      9  RTC                                */
-    __I uint32_t EIC_:1;           /*!< bit:     10  EIC                                */
-    __I uint32_t FREQM_:1;         /*!< bit:     11  FREQM                              */
-    __I uint32_t SERCOM0_:1;       /*!< bit:     12  SERCOM0                            */
-    __I uint32_t SERCOM1_:1;       /*!< bit:     13  SERCOM1                            */
-    __I uint32_t TC0_:1;           /*!< bit:     14  TC0                                */
-    __I uint32_t TC1_:1;           /*!< bit:     15  TC1                                */
-    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_INTFLAGA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGA_OFFSET         0x14         /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */
-#define PAC_INTFLAGA_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */
-
-#define PAC_INTFLAGA_PAC_Pos        0            /**< \brief (PAC_INTFLAGA) PAC */
-#define PAC_INTFLAGA_PAC            (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
-#define PAC_INTFLAGA_PM_Pos         1            /**< \brief (PAC_INTFLAGA) PM */
-#define PAC_INTFLAGA_PM             (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
-#define PAC_INTFLAGA_MCLK_Pos       2            /**< \brief (PAC_INTFLAGA) MCLK */
-#define PAC_INTFLAGA_MCLK           (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
-#define PAC_INTFLAGA_RSTC_Pos       3            /**< \brief (PAC_INTFLAGA) RSTC */
-#define PAC_INTFLAGA_RSTC           (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
-#define PAC_INTFLAGA_OSCCTRL_Pos    4            /**< \brief (PAC_INTFLAGA) OSCCTRL */
-#define PAC_INTFLAGA_OSCCTRL        (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
-#define PAC_INTFLAGA_OSC32KCTRL_Pos 5            /**< \brief (PAC_INTFLAGA) OSC32KCTRL */
-#define PAC_INTFLAGA_OSC32KCTRL     (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
-#define PAC_INTFLAGA_SUPC_Pos       6            /**< \brief (PAC_INTFLAGA) SUPC */
-#define PAC_INTFLAGA_SUPC           (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
-#define PAC_INTFLAGA_GCLK_Pos       7            /**< \brief (PAC_INTFLAGA) GCLK */
-#define PAC_INTFLAGA_GCLK           (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
-#define PAC_INTFLAGA_WDT_Pos        8            /**< \brief (PAC_INTFLAGA) WDT */
-#define PAC_INTFLAGA_WDT            (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
-#define PAC_INTFLAGA_RTC_Pos        9            /**< \brief (PAC_INTFLAGA) RTC */
-#define PAC_INTFLAGA_RTC            (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
-#define PAC_INTFLAGA_EIC_Pos        10           /**< \brief (PAC_INTFLAGA) EIC */
-#define PAC_INTFLAGA_EIC            (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
-#define PAC_INTFLAGA_FREQM_Pos      11           /**< \brief (PAC_INTFLAGA) FREQM */
-#define PAC_INTFLAGA_FREQM          (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
-#define PAC_INTFLAGA_SERCOM0_Pos    12           /**< \brief (PAC_INTFLAGA) SERCOM0 */
-#define PAC_INTFLAGA_SERCOM0        (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos)
-#define PAC_INTFLAGA_SERCOM1_Pos    13           /**< \brief (PAC_INTFLAGA) SERCOM1 */
-#define PAC_INTFLAGA_SERCOM1        (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos)
-#define PAC_INTFLAGA_TC0_Pos        14           /**< \brief (PAC_INTFLAGA) TC0 */
-#define PAC_INTFLAGA_TC0            (_U_(0x1) << PAC_INTFLAGA_TC0_Pos)
-#define PAC_INTFLAGA_TC1_Pos        15           /**< \brief (PAC_INTFLAGA) TC1 */
-#define PAC_INTFLAGA_TC1            (_U_(0x1) << PAC_INTFLAGA_TC1_Pos)
-#define PAC_INTFLAGA_MASK           _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGA) MASK Register */
-
-/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t USB_:1;           /*!< bit:      0  USB                                */
-    __I uint32_t DSU_:1;           /*!< bit:      1  DSU                                */
-    __I uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL                            */
-    __I uint32_t CMCC_:1;          /*!< bit:      3  CMCC                               */
-    __I uint32_t PORT_:1;          /*!< bit:      4  PORT                               */
-    __I uint32_t DMAC_:1;          /*!< bit:      5  DMAC                               */
-    __I uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX                            */
-    __I uint32_t EVSYS_:1;         /*!< bit:      7  EVSYS                              */
-    __I uint32_t :1;               /*!< bit:      8  Reserved                           */
-    __I uint32_t SERCOM2_:1;       /*!< bit:      9  SERCOM2                            */
-    __I uint32_t SERCOM3_:1;       /*!< bit:     10  SERCOM3                            */
-    __I uint32_t TCC0_:1;          /*!< bit:     11  TCC0                               */
-    __I uint32_t TCC1_:1;          /*!< bit:     12  TCC1                               */
-    __I uint32_t TC2_:1;           /*!< bit:     13  TC2                                */
-    __I uint32_t TC3_:1;           /*!< bit:     14  TC3                                */
-    __I uint32_t TAL_:1;           /*!< bit:     15  TAL                                */
-    __I uint32_t RAMECC_:1;        /*!< bit:     16  RAMECC                             */
-    __I uint32_t :15;              /*!< bit: 17..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_INTFLAGB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGB_OFFSET         0x18         /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */
-#define PAC_INTFLAGB_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */
-
-#define PAC_INTFLAGB_USB_Pos        0            /**< \brief (PAC_INTFLAGB) USB */
-#define PAC_INTFLAGB_USB            (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
-#define PAC_INTFLAGB_DSU_Pos        1            /**< \brief (PAC_INTFLAGB) DSU */
-#define PAC_INTFLAGB_DSU            (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
-#define PAC_INTFLAGB_NVMCTRL_Pos    2            /**< \brief (PAC_INTFLAGB) NVMCTRL */
-#define PAC_INTFLAGB_NVMCTRL        (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
-#define PAC_INTFLAGB_CMCC_Pos       3            /**< \brief (PAC_INTFLAGB) CMCC */
-#define PAC_INTFLAGB_CMCC           (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos)
-#define PAC_INTFLAGB_PORT_Pos       4            /**< \brief (PAC_INTFLAGB) PORT */
-#define PAC_INTFLAGB_PORT           (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
-#define PAC_INTFLAGB_DMAC_Pos       5            /**< \brief (PAC_INTFLAGB) DMAC */
-#define PAC_INTFLAGB_DMAC           (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
-#define PAC_INTFLAGB_HMATRIX_Pos    6            /**< \brief (PAC_INTFLAGB) HMATRIX */
-#define PAC_INTFLAGB_HMATRIX        (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos)
-#define PAC_INTFLAGB_EVSYS_Pos      7            /**< \brief (PAC_INTFLAGB) EVSYS */
-#define PAC_INTFLAGB_EVSYS          (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos)
-#define PAC_INTFLAGB_SERCOM2_Pos    9            /**< \brief (PAC_INTFLAGB) SERCOM2 */
-#define PAC_INTFLAGB_SERCOM2        (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos)
-#define PAC_INTFLAGB_SERCOM3_Pos    10           /**< \brief (PAC_INTFLAGB) SERCOM3 */
-#define PAC_INTFLAGB_SERCOM3        (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos)
-#define PAC_INTFLAGB_TCC0_Pos       11           /**< \brief (PAC_INTFLAGB) TCC0 */
-#define PAC_INTFLAGB_TCC0           (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos)
-#define PAC_INTFLAGB_TCC1_Pos       12           /**< \brief (PAC_INTFLAGB) TCC1 */
-#define PAC_INTFLAGB_TCC1           (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos)
-#define PAC_INTFLAGB_TC2_Pos        13           /**< \brief (PAC_INTFLAGB) TC2 */
-#define PAC_INTFLAGB_TC2            (_U_(0x1) << PAC_INTFLAGB_TC2_Pos)
-#define PAC_INTFLAGB_TC3_Pos        14           /**< \brief (PAC_INTFLAGB) TC3 */
-#define PAC_INTFLAGB_TC3            (_U_(0x1) << PAC_INTFLAGB_TC3_Pos)
-#define PAC_INTFLAGB_TAL_Pos        15           /**< \brief (PAC_INTFLAGB) TAL */
-#define PAC_INTFLAGB_TAL            (_U_(0x1) << PAC_INTFLAGB_TAL_Pos)
-#define PAC_INTFLAGB_RAMECC_Pos     16           /**< \brief (PAC_INTFLAGB) RAMECC */
-#define PAC_INTFLAGB_RAMECC         (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos)
-#define PAC_INTFLAGB_MASK           _U_(0x0001FEFF) /**< \brief (PAC_INTFLAGB) MASK Register */
-
-/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t :3;               /*!< bit:  0.. 2  Reserved                           */
-    __I uint32_t TCC2_:1;          /*!< bit:      3  TCC2                               */
-    __I uint32_t TCC3_:1;          /*!< bit:      4  TCC3                               */
-    __I uint32_t TC4_:1;           /*!< bit:      5  TC4                                */
-    __I uint32_t TC5_:1;           /*!< bit:      6  TC5                                */
-    __I uint32_t PDEC_:1;          /*!< bit:      7  PDEC                               */
-    __I uint32_t AC_:1;            /*!< bit:      8  AC                                 */
-    __I uint32_t AES_:1;           /*!< bit:      9  AES                                */
-    __I uint32_t TRNG_:1;          /*!< bit:     10  TRNG                               */
-    __I uint32_t ICM_:1;           /*!< bit:     11  ICM                                */
-    __I uint32_t PUKCC_:1;         /*!< bit:     12  PUKCC                              */
-    __I uint32_t QSPI_:1;          /*!< bit:     13  QSPI                               */
-    __I uint32_t CCL_:1;           /*!< bit:     14  CCL                                */
-    __I uint32_t :17;              /*!< bit: 15..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_INTFLAGC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGC_OFFSET         0x1C         /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
-#define PAC_INTFLAGC_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */
-
-#define PAC_INTFLAGC_TCC2_Pos       3            /**< \brief (PAC_INTFLAGC) TCC2 */
-#define PAC_INTFLAGC_TCC2           (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
-#define PAC_INTFLAGC_TCC3_Pos       4            /**< \brief (PAC_INTFLAGC) TCC3 */
-#define PAC_INTFLAGC_TCC3           (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos)
-#define PAC_INTFLAGC_TC4_Pos        5            /**< \brief (PAC_INTFLAGC) TC4 */
-#define PAC_INTFLAGC_TC4            (_U_(0x1) << PAC_INTFLAGC_TC4_Pos)
-#define PAC_INTFLAGC_TC5_Pos        6            /**< \brief (PAC_INTFLAGC) TC5 */
-#define PAC_INTFLAGC_TC5            (_U_(0x1) << PAC_INTFLAGC_TC5_Pos)
-#define PAC_INTFLAGC_PDEC_Pos       7            /**< \brief (PAC_INTFLAGC) PDEC */
-#define PAC_INTFLAGC_PDEC           (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos)
-#define PAC_INTFLAGC_AC_Pos         8            /**< \brief (PAC_INTFLAGC) AC */
-#define PAC_INTFLAGC_AC             (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
-#define PAC_INTFLAGC_AES_Pos        9            /**< \brief (PAC_INTFLAGC) AES */
-#define PAC_INTFLAGC_AES            (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
-#define PAC_INTFLAGC_TRNG_Pos       10           /**< \brief (PAC_INTFLAGC) TRNG */
-#define PAC_INTFLAGC_TRNG           (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
-#define PAC_INTFLAGC_ICM_Pos        11           /**< \brief (PAC_INTFLAGC) ICM */
-#define PAC_INTFLAGC_ICM            (_U_(0x1) << PAC_INTFLAGC_ICM_Pos)
-#define PAC_INTFLAGC_PUKCC_Pos      12           /**< \brief (PAC_INTFLAGC) PUKCC */
-#define PAC_INTFLAGC_PUKCC          (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos)
-#define PAC_INTFLAGC_QSPI_Pos       13           /**< \brief (PAC_INTFLAGC) QSPI */
-#define PAC_INTFLAGC_QSPI           (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos)
-#define PAC_INTFLAGC_CCL_Pos        14           /**< \brief (PAC_INTFLAGC) CCL */
-#define PAC_INTFLAGC_CCL            (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
-#define PAC_INTFLAGC_MASK           _U_(0x00007FF8) /**< \brief (PAC_INTFLAGC) MASK Register */
-
-/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t SERCOM4_:1;       /*!< bit:      0  SERCOM4                            */
-    __I uint32_t SERCOM5_:1;       /*!< bit:      1  SERCOM5                            */
-    __I uint32_t SERCOM6_:1;       /*!< bit:      2  SERCOM6                            */
-    __I uint32_t SERCOM7_:1;       /*!< bit:      3  SERCOM7                            */
-    __I uint32_t TCC4_:1;          /*!< bit:      4  TCC4                               */
-    __I uint32_t TC6_:1;           /*!< bit:      5  TC6                                */
-    __I uint32_t TC7_:1;           /*!< bit:      6  TC7                                */
-    __I uint32_t ADC0_:1;          /*!< bit:      7  ADC0                               */
-    __I uint32_t ADC1_:1;          /*!< bit:      8  ADC1                               */
-    __I uint32_t DAC_:1;           /*!< bit:      9  DAC                                */
-    __I uint32_t I2S_:1;           /*!< bit:     10  I2S                                */
-    __I uint32_t PCC_:1;           /*!< bit:     11  PCC                                */
-    __I uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_INTFLAGD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_INTFLAGD_OFFSET         0x20         /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */
-#define PAC_INTFLAGD_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */
-
-#define PAC_INTFLAGD_SERCOM4_Pos    0            /**< \brief (PAC_INTFLAGD) SERCOM4 */
-#define PAC_INTFLAGD_SERCOM4        (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos)
-#define PAC_INTFLAGD_SERCOM5_Pos    1            /**< \brief (PAC_INTFLAGD) SERCOM5 */
-#define PAC_INTFLAGD_SERCOM5        (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos)
-#define PAC_INTFLAGD_SERCOM6_Pos    2            /**< \brief (PAC_INTFLAGD) SERCOM6 */
-#define PAC_INTFLAGD_SERCOM6        (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos)
-#define PAC_INTFLAGD_SERCOM7_Pos    3            /**< \brief (PAC_INTFLAGD) SERCOM7 */
-#define PAC_INTFLAGD_SERCOM7        (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos)
-#define PAC_INTFLAGD_TCC4_Pos       4            /**< \brief (PAC_INTFLAGD) TCC4 */
-#define PAC_INTFLAGD_TCC4           (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos)
-#define PAC_INTFLAGD_TC6_Pos        5            /**< \brief (PAC_INTFLAGD) TC6 */
-#define PAC_INTFLAGD_TC6            (_U_(0x1) << PAC_INTFLAGD_TC6_Pos)
-#define PAC_INTFLAGD_TC7_Pos        6            /**< \brief (PAC_INTFLAGD) TC7 */
-#define PAC_INTFLAGD_TC7            (_U_(0x1) << PAC_INTFLAGD_TC7_Pos)
-#define PAC_INTFLAGD_ADC0_Pos       7            /**< \brief (PAC_INTFLAGD) ADC0 */
-#define PAC_INTFLAGD_ADC0           (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos)
-#define PAC_INTFLAGD_ADC1_Pos       8            /**< \brief (PAC_INTFLAGD) ADC1 */
-#define PAC_INTFLAGD_ADC1           (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos)
-#define PAC_INTFLAGD_DAC_Pos        9            /**< \brief (PAC_INTFLAGD) DAC */
-#define PAC_INTFLAGD_DAC            (_U_(0x1) << PAC_INTFLAGD_DAC_Pos)
-#define PAC_INTFLAGD_I2S_Pos        10           /**< \brief (PAC_INTFLAGD) I2S */
-#define PAC_INTFLAGD_I2S            (_U_(0x1) << PAC_INTFLAGD_I2S_Pos)
-#define PAC_INTFLAGD_PCC_Pos        11           /**< \brief (PAC_INTFLAGD) PCC */
-#define PAC_INTFLAGD_PCC            (_U_(0x1) << PAC_INTFLAGD_PCC_Pos)
-#define PAC_INTFLAGD_MASK           _U_(0x00000FFF) /**< \brief (PAC_INTFLAGD) MASK Register */
-
-/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/  32) Peripheral write protection status - Bridge A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PAC_:1;           /*!< bit:      0  PAC APB Protect Enable             */
-    uint32_t PM_:1;            /*!< bit:      1  PM APB Protect Enable              */
-    uint32_t MCLK_:1;          /*!< bit:      2  MCLK APB Protect Enable            */
-    uint32_t RSTC_:1;          /*!< bit:      3  RSTC APB Protect Enable            */
-    uint32_t OSCCTRL_:1;       /*!< bit:      4  OSCCTRL APB Protect Enable         */
-    uint32_t OSC32KCTRL_:1;    /*!< bit:      5  OSC32KCTRL APB Protect Enable      */
-    uint32_t SUPC_:1;          /*!< bit:      6  SUPC APB Protect Enable            */
-    uint32_t GCLK_:1;          /*!< bit:      7  GCLK APB Protect Enable            */
-    uint32_t WDT_:1;           /*!< bit:      8  WDT APB Protect Enable             */
-    uint32_t RTC_:1;           /*!< bit:      9  RTC APB Protect Enable             */
-    uint32_t EIC_:1;           /*!< bit:     10  EIC APB Protect Enable             */
-    uint32_t FREQM_:1;         /*!< bit:     11  FREQM APB Protect Enable           */
-    uint32_t SERCOM0_:1;       /*!< bit:     12  SERCOM0 APB Protect Enable         */
-    uint32_t SERCOM1_:1;       /*!< bit:     13  SERCOM1 APB Protect Enable         */
-    uint32_t TC0_:1;           /*!< bit:     14  TC0 APB Protect Enable             */
-    uint32_t TC1_:1;           /*!< bit:     15  TC1 APB Protect Enable             */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_STATUSA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_STATUSA_OFFSET          0x34         /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */
-#define PAC_STATUSA_RESETVALUE      _U_(0x00010000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */
-
-#define PAC_STATUSA_PAC_Pos         0            /**< \brief (PAC_STATUSA) PAC APB Protect Enable */
-#define PAC_STATUSA_PAC             (_U_(0x1) << PAC_STATUSA_PAC_Pos)
-#define PAC_STATUSA_PM_Pos          1            /**< \brief (PAC_STATUSA) PM APB Protect Enable */
-#define PAC_STATUSA_PM              (_U_(0x1) << PAC_STATUSA_PM_Pos)
-#define PAC_STATUSA_MCLK_Pos        2            /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */
-#define PAC_STATUSA_MCLK            (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
-#define PAC_STATUSA_RSTC_Pos        3            /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */
-#define PAC_STATUSA_RSTC            (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
-#define PAC_STATUSA_OSCCTRL_Pos     4            /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */
-#define PAC_STATUSA_OSCCTRL         (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
-#define PAC_STATUSA_OSC32KCTRL_Pos  5            /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */
-#define PAC_STATUSA_OSC32KCTRL      (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
-#define PAC_STATUSA_SUPC_Pos        6            /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */
-#define PAC_STATUSA_SUPC            (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
-#define PAC_STATUSA_GCLK_Pos        7            /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */
-#define PAC_STATUSA_GCLK            (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
-#define PAC_STATUSA_WDT_Pos         8            /**< \brief (PAC_STATUSA) WDT APB Protect Enable */
-#define PAC_STATUSA_WDT             (_U_(0x1) << PAC_STATUSA_WDT_Pos)
-#define PAC_STATUSA_RTC_Pos         9            /**< \brief (PAC_STATUSA) RTC APB Protect Enable */
-#define PAC_STATUSA_RTC             (_U_(0x1) << PAC_STATUSA_RTC_Pos)
-#define PAC_STATUSA_EIC_Pos         10           /**< \brief (PAC_STATUSA) EIC APB Protect Enable */
-#define PAC_STATUSA_EIC             (_U_(0x1) << PAC_STATUSA_EIC_Pos)
-#define PAC_STATUSA_FREQM_Pos       11           /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */
-#define PAC_STATUSA_FREQM           (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
-#define PAC_STATUSA_SERCOM0_Pos     12           /**< \brief (PAC_STATUSA) SERCOM0 APB Protect Enable */
-#define PAC_STATUSA_SERCOM0         (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos)
-#define PAC_STATUSA_SERCOM1_Pos     13           /**< \brief (PAC_STATUSA) SERCOM1 APB Protect Enable */
-#define PAC_STATUSA_SERCOM1         (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos)
-#define PAC_STATUSA_TC0_Pos         14           /**< \brief (PAC_STATUSA) TC0 APB Protect Enable */
-#define PAC_STATUSA_TC0             (_U_(0x1) << PAC_STATUSA_TC0_Pos)
-#define PAC_STATUSA_TC1_Pos         15           /**< \brief (PAC_STATUSA) TC1 APB Protect Enable */
-#define PAC_STATUSA_TC1             (_U_(0x1) << PAC_STATUSA_TC1_Pos)
-#define PAC_STATUSA_MASK            _U_(0x0000FFFF) /**< \brief (PAC_STATUSA) MASK Register */
-
-/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/  32) Peripheral write protection status - Bridge B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t USB_:1;           /*!< bit:      0  USB APB Protect Enable             */
-    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Protect Enable             */
-    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Protect Enable         */
-    uint32_t CMCC_:1;          /*!< bit:      3  CMCC APB Protect Enable            */
-    uint32_t PORT_:1;          /*!< bit:      4  PORT APB Protect Enable            */
-    uint32_t DMAC_:1;          /*!< bit:      5  DMAC APB Protect Enable            */
-    uint32_t HMATRIX_:1;       /*!< bit:      6  HMATRIX APB Protect Enable         */
-    uint32_t EVSYS_:1;         /*!< bit:      7  EVSYS APB Protect Enable           */
-    uint32_t :1;               /*!< bit:      8  Reserved                           */
-    uint32_t SERCOM2_:1;       /*!< bit:      9  SERCOM2 APB Protect Enable         */
-    uint32_t SERCOM3_:1;       /*!< bit:     10  SERCOM3 APB Protect Enable         */
-    uint32_t TCC0_:1;          /*!< bit:     11  TCC0 APB Protect Enable            */
-    uint32_t TCC1_:1;          /*!< bit:     12  TCC1 APB Protect Enable            */
-    uint32_t TC2_:1;           /*!< bit:     13  TC2 APB Protect Enable             */
-    uint32_t TC3_:1;           /*!< bit:     14  TC3 APB Protect Enable             */
-    uint32_t TAL_:1;           /*!< bit:     15  TAL APB Protect Enable             */
-    uint32_t RAMECC_:1;        /*!< bit:     16  RAMECC APB Protect Enable          */
-    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_STATUSB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_STATUSB_OFFSET          0x38         /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */
-#define PAC_STATUSB_RESETVALUE      _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */
-
-#define PAC_STATUSB_USB_Pos         0            /**< \brief (PAC_STATUSB) USB APB Protect Enable */
-#define PAC_STATUSB_USB             (_U_(0x1) << PAC_STATUSB_USB_Pos)
-#define PAC_STATUSB_DSU_Pos         1            /**< \brief (PAC_STATUSB) DSU APB Protect Enable */
-#define PAC_STATUSB_DSU             (_U_(0x1) << PAC_STATUSB_DSU_Pos)
-#define PAC_STATUSB_NVMCTRL_Pos     2            /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */
-#define PAC_STATUSB_NVMCTRL         (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
-#define PAC_STATUSB_CMCC_Pos        3            /**< \brief (PAC_STATUSB) CMCC APB Protect Enable */
-#define PAC_STATUSB_CMCC            (_U_(0x1) << PAC_STATUSB_CMCC_Pos)
-#define PAC_STATUSB_PORT_Pos        4            /**< \brief (PAC_STATUSB) PORT APB Protect Enable */
-#define PAC_STATUSB_PORT            (_U_(0x1) << PAC_STATUSB_PORT_Pos)
-#define PAC_STATUSB_DMAC_Pos        5            /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */
-#define PAC_STATUSB_DMAC            (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
-#define PAC_STATUSB_HMATRIX_Pos     6            /**< \brief (PAC_STATUSB) HMATRIX APB Protect Enable */
-#define PAC_STATUSB_HMATRIX         (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos)
-#define PAC_STATUSB_EVSYS_Pos       7            /**< \brief (PAC_STATUSB) EVSYS APB Protect Enable */
-#define PAC_STATUSB_EVSYS           (_U_(0x1) << PAC_STATUSB_EVSYS_Pos)
-#define PAC_STATUSB_SERCOM2_Pos     9            /**< \brief (PAC_STATUSB) SERCOM2 APB Protect Enable */
-#define PAC_STATUSB_SERCOM2         (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos)
-#define PAC_STATUSB_SERCOM3_Pos     10           /**< \brief (PAC_STATUSB) SERCOM3 APB Protect Enable */
-#define PAC_STATUSB_SERCOM3         (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos)
-#define PAC_STATUSB_TCC0_Pos        11           /**< \brief (PAC_STATUSB) TCC0 APB Protect Enable */
-#define PAC_STATUSB_TCC0            (_U_(0x1) << PAC_STATUSB_TCC0_Pos)
-#define PAC_STATUSB_TCC1_Pos        12           /**< \brief (PAC_STATUSB) TCC1 APB Protect Enable */
-#define PAC_STATUSB_TCC1            (_U_(0x1) << PAC_STATUSB_TCC1_Pos)
-#define PAC_STATUSB_TC2_Pos         13           /**< \brief (PAC_STATUSB) TC2 APB Protect Enable */
-#define PAC_STATUSB_TC2             (_U_(0x1) << PAC_STATUSB_TC2_Pos)
-#define PAC_STATUSB_TC3_Pos         14           /**< \brief (PAC_STATUSB) TC3 APB Protect Enable */
-#define PAC_STATUSB_TC3             (_U_(0x1) << PAC_STATUSB_TC3_Pos)
-#define PAC_STATUSB_TAL_Pos         15           /**< \brief (PAC_STATUSB) TAL APB Protect Enable */
-#define PAC_STATUSB_TAL             (_U_(0x1) << PAC_STATUSB_TAL_Pos)
-#define PAC_STATUSB_RAMECC_Pos      16           /**< \brief (PAC_STATUSB) RAMECC APB Protect Enable */
-#define PAC_STATUSB_RAMECC          (_U_(0x1) << PAC_STATUSB_RAMECC_Pos)
-#define PAC_STATUSB_MASK            _U_(0x0001FEFF) /**< \brief (PAC_STATUSB) MASK Register */
-
-/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/  32) Peripheral write protection status - Bridge C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :3;               /*!< bit:  0.. 2  Reserved                           */
-    uint32_t TCC2_:1;          /*!< bit:      3  TCC2 APB Protect Enable            */
-    uint32_t TCC3_:1;          /*!< bit:      4  TCC3 APB Protect Enable            */
-    uint32_t TC4_:1;           /*!< bit:      5  TC4 APB Protect Enable             */
-    uint32_t TC5_:1;           /*!< bit:      6  TC5 APB Protect Enable             */
-    uint32_t PDEC_:1;          /*!< bit:      7  PDEC APB Protect Enable            */
-    uint32_t AC_:1;            /*!< bit:      8  AC APB Protect Enable              */
-    uint32_t AES_:1;           /*!< bit:      9  AES APB Protect Enable             */
-    uint32_t TRNG_:1;          /*!< bit:     10  TRNG APB Protect Enable            */
-    uint32_t ICM_:1;           /*!< bit:     11  ICM APB Protect Enable             */
-    uint32_t PUKCC_:1;         /*!< bit:     12  PUKCC APB Protect Enable           */
-    uint32_t QSPI_:1;          /*!< bit:     13  QSPI APB Protect Enable            */
-    uint32_t CCL_:1;           /*!< bit:     14  CCL APB Protect Enable             */
-    uint32_t :17;              /*!< bit: 15..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_STATUSC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_STATUSC_OFFSET          0x3C         /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
-#define PAC_STATUSC_RESETVALUE      _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */
-
-#define PAC_STATUSC_TCC2_Pos        3            /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */
-#define PAC_STATUSC_TCC2            (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
-#define PAC_STATUSC_TCC3_Pos        4            /**< \brief (PAC_STATUSC) TCC3 APB Protect Enable */
-#define PAC_STATUSC_TCC3            (_U_(0x1) << PAC_STATUSC_TCC3_Pos)
-#define PAC_STATUSC_TC4_Pos         5            /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */
-#define PAC_STATUSC_TC4             (_U_(0x1) << PAC_STATUSC_TC4_Pos)
-#define PAC_STATUSC_TC5_Pos         6            /**< \brief (PAC_STATUSC) TC5 APB Protect Enable */
-#define PAC_STATUSC_TC5             (_U_(0x1) << PAC_STATUSC_TC5_Pos)
-#define PAC_STATUSC_PDEC_Pos        7            /**< \brief (PAC_STATUSC) PDEC APB Protect Enable */
-#define PAC_STATUSC_PDEC            (_U_(0x1) << PAC_STATUSC_PDEC_Pos)
-#define PAC_STATUSC_AC_Pos          8            /**< \brief (PAC_STATUSC) AC APB Protect Enable */
-#define PAC_STATUSC_AC              (_U_(0x1) << PAC_STATUSC_AC_Pos)
-#define PAC_STATUSC_AES_Pos         9            /**< \brief (PAC_STATUSC) AES APB Protect Enable */
-#define PAC_STATUSC_AES             (_U_(0x1) << PAC_STATUSC_AES_Pos)
-#define PAC_STATUSC_TRNG_Pos        10           /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */
-#define PAC_STATUSC_TRNG            (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
-#define PAC_STATUSC_ICM_Pos         11           /**< \brief (PAC_STATUSC) ICM APB Protect Enable */
-#define PAC_STATUSC_ICM             (_U_(0x1) << PAC_STATUSC_ICM_Pos)
-#define PAC_STATUSC_PUKCC_Pos       12           /**< \brief (PAC_STATUSC) PUKCC APB Protect Enable */
-#define PAC_STATUSC_PUKCC           (_U_(0x1) << PAC_STATUSC_PUKCC_Pos)
-#define PAC_STATUSC_QSPI_Pos        13           /**< \brief (PAC_STATUSC) QSPI APB Protect Enable */
-#define PAC_STATUSC_QSPI            (_U_(0x1) << PAC_STATUSC_QSPI_Pos)
-#define PAC_STATUSC_CCL_Pos         14           /**< \brief (PAC_STATUSC) CCL APB Protect Enable */
-#define PAC_STATUSC_CCL             (_U_(0x1) << PAC_STATUSC_CCL_Pos)
-#define PAC_STATUSC_MASK            _U_(0x00007FF8) /**< \brief (PAC_STATUSC) MASK Register */
-
-/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/  32) Peripheral write protection status - Bridge D -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SERCOM4_:1;       /*!< bit:      0  SERCOM4 APB Protect Enable         */
-    uint32_t SERCOM5_:1;       /*!< bit:      1  SERCOM5 APB Protect Enable         */
-    uint32_t SERCOM6_:1;       /*!< bit:      2  SERCOM6 APB Protect Enable         */
-    uint32_t SERCOM7_:1;       /*!< bit:      3  SERCOM7 APB Protect Enable         */
-    uint32_t TCC4_:1;          /*!< bit:      4  TCC4 APB Protect Enable            */
-    uint32_t TC6_:1;           /*!< bit:      5  TC6 APB Protect Enable             */
-    uint32_t TC7_:1;           /*!< bit:      6  TC7 APB Protect Enable             */
-    uint32_t ADC0_:1;          /*!< bit:      7  ADC0 APB Protect Enable            */
-    uint32_t ADC1_:1;          /*!< bit:      8  ADC1 APB Protect Enable            */
-    uint32_t DAC_:1;           /*!< bit:      9  DAC APB Protect Enable             */
-    uint32_t I2S_:1;           /*!< bit:     10  I2S APB Protect Enable             */
-    uint32_t PCC_:1;           /*!< bit:     11  PCC APB Protect Enable             */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PAC_STATUSD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PAC_STATUSD_OFFSET          0x40         /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */
-#define PAC_STATUSD_RESETVALUE      _U_(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */
-
-#define PAC_STATUSD_SERCOM4_Pos     0            /**< \brief (PAC_STATUSD) SERCOM4 APB Protect Enable */
-#define PAC_STATUSD_SERCOM4         (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos)
-#define PAC_STATUSD_SERCOM5_Pos     1            /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */
-#define PAC_STATUSD_SERCOM5         (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos)
-#define PAC_STATUSD_SERCOM6_Pos     2            /**< \brief (PAC_STATUSD) SERCOM6 APB Protect Enable */
-#define PAC_STATUSD_SERCOM6         (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos)
-#define PAC_STATUSD_SERCOM7_Pos     3            /**< \brief (PAC_STATUSD) SERCOM7 APB Protect Enable */
-#define PAC_STATUSD_SERCOM7         (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos)
-#define PAC_STATUSD_TCC4_Pos        4            /**< \brief (PAC_STATUSD) TCC4 APB Protect Enable */
-#define PAC_STATUSD_TCC4            (_U_(0x1) << PAC_STATUSD_TCC4_Pos)
-#define PAC_STATUSD_TC6_Pos         5            /**< \brief (PAC_STATUSD) TC6 APB Protect Enable */
-#define PAC_STATUSD_TC6             (_U_(0x1) << PAC_STATUSD_TC6_Pos)
-#define PAC_STATUSD_TC7_Pos         6            /**< \brief (PAC_STATUSD) TC7 APB Protect Enable */
-#define PAC_STATUSD_TC7             (_U_(0x1) << PAC_STATUSD_TC7_Pos)
-#define PAC_STATUSD_ADC0_Pos        7            /**< \brief (PAC_STATUSD) ADC0 APB Protect Enable */
-#define PAC_STATUSD_ADC0            (_U_(0x1) << PAC_STATUSD_ADC0_Pos)
-#define PAC_STATUSD_ADC1_Pos        8            /**< \brief (PAC_STATUSD) ADC1 APB Protect Enable */
-#define PAC_STATUSD_ADC1            (_U_(0x1) << PAC_STATUSD_ADC1_Pos)
-#define PAC_STATUSD_DAC_Pos         9            /**< \brief (PAC_STATUSD) DAC APB Protect Enable */
-#define PAC_STATUSD_DAC             (_U_(0x1) << PAC_STATUSD_DAC_Pos)
-#define PAC_STATUSD_I2S_Pos         10           /**< \brief (PAC_STATUSD) I2S APB Protect Enable */
-#define PAC_STATUSD_I2S             (_U_(0x1) << PAC_STATUSD_I2S_Pos)
-#define PAC_STATUSD_PCC_Pos         11           /**< \brief (PAC_STATUSD) PCC APB Protect Enable */
-#define PAC_STATUSD_PCC             (_U_(0x1) << PAC_STATUSD_PCC_Pos)
-#define PAC_STATUSD_MASK            _U_(0x00000FFF) /**< \brief (PAC_STATUSD) MASK Register */
-
-/** \brief PAC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO PAC_WRCTRL_Type           WRCTRL;      /**< \brief Offset: 0x00 (R/W 32) Write control */
-  __IO PAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x04 (R/W  8) Event control */
-       RoReg8                    Reserved1[0x3];
-  __IO PAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt enable clear */
-  __IO PAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt enable set */
-       RoReg8                    Reserved2[0x6];
-  __IO PAC_INTFLAGAHB_Type       INTFLAGAHB;  /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */
-  __IO PAC_INTFLAGA_Type         INTFLAGA;    /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
-  __IO PAC_INTFLAGB_Type         INTFLAGB;    /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
-  __IO PAC_INTFLAGC_Type         INTFLAGC;    /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
-  __IO PAC_INTFLAGD_Type         INTFLAGD;    /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */
-       RoReg8                    Reserved3[0x10];
-  __I  PAC_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x34 (R/  32) Peripheral write protection status - Bridge A */
-  __I  PAC_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x38 (R/  32) Peripheral write protection status - Bridge B */
-  __I  PAC_STATUSC_Type          STATUSC;     /**< \brief Offset: 0x3C (R/  32) Peripheral write protection status - Bridge C */
-  __I  PAC_STATUSD_Type          STATUSD;     /**< \brief Offset: 0x40 (R/  32) Peripheral write protection status - Bridge D */
-} Pac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_PAC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pcc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pcc.h
deleted file mode 100644
index 899c23da03..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pcc.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for PCC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PCC_COMPONENT_
-#define _SAMD51_PCC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR PCC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_PCC Parallel Capture Controller */
-/*@{*/
-
-#define PCC_U2017
-#define REV_PCC                     0x110
-
-/* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PCEN:1;           /*!< bit:      0  Parallel Capture Enable            */
-    uint32_t :3;               /*!< bit:  1.. 3  Reserved                           */
-    uint32_t DSIZE:2;          /*!< bit:  4.. 5  Data size                          */
-    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint32_t SCALE:1;          /*!< bit:      8  Scale data                         */
-    uint32_t ALWYS:1;          /*!< bit:      9  Always Sampling                    */
-    uint32_t HALFS:1;          /*!< bit:     10  Half Sampling                      */
-    uint32_t FRSTS:1;          /*!< bit:     11  First sample                       */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t ISIZE:3;          /*!< bit: 16..18  Input Data Size                    */
-    uint32_t :11;              /*!< bit: 19..29  Reserved                           */
-    uint32_t CID:2;            /*!< bit: 30..31  Clear If Disabled                  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PCC_MR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_MR_OFFSET               0x00         /**< \brief (PCC_MR offset) Mode Register */
-#define PCC_MR_RESETVALUE           _U_(0x00000000) /**< \brief (PCC_MR reset_value) Mode Register */
-
-#define PCC_MR_PCEN_Pos             0            /**< \brief (PCC_MR) Parallel Capture Enable */
-#define PCC_MR_PCEN                 (_U_(0x1) << PCC_MR_PCEN_Pos)
-#define PCC_MR_DSIZE_Pos            4            /**< \brief (PCC_MR) Data size */
-#define PCC_MR_DSIZE_Msk            (_U_(0x3) << PCC_MR_DSIZE_Pos)
-#define PCC_MR_DSIZE(value)         (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
-#define PCC_MR_SCALE_Pos            8            /**< \brief (PCC_MR) Scale data */
-#define PCC_MR_SCALE                (_U_(0x1) << PCC_MR_SCALE_Pos)
-#define PCC_MR_ALWYS_Pos            9            /**< \brief (PCC_MR) Always Sampling */
-#define PCC_MR_ALWYS                (_U_(0x1) << PCC_MR_ALWYS_Pos)
-#define PCC_MR_HALFS_Pos            10           /**< \brief (PCC_MR) Half Sampling */
-#define PCC_MR_HALFS                (_U_(0x1) << PCC_MR_HALFS_Pos)
-#define PCC_MR_FRSTS_Pos            11           /**< \brief (PCC_MR) First sample */
-#define PCC_MR_FRSTS                (_U_(0x1) << PCC_MR_FRSTS_Pos)
-#define PCC_MR_ISIZE_Pos            16           /**< \brief (PCC_MR) Input Data Size */
-#define PCC_MR_ISIZE_Msk            (_U_(0x7) << PCC_MR_ISIZE_Pos)
-#define PCC_MR_ISIZE(value)         (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
-#define PCC_MR_CID_Pos              30           /**< \brief (PCC_MR) Clear If Disabled */
-#define PCC_MR_CID_Msk              (_U_(0x3) << PCC_MR_CID_Pos)
-#define PCC_MR_CID(value)           (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
-#define PCC_MR_MASK                 _U_(0xC0070F31) /**< \brief (PCC_MR) MASK Register */
-
-/* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DRDY:1;           /*!< bit:      0  Data Ready Interrupt Enable        */
-    uint32_t OVRE:1;           /*!< bit:      1  Overrun Error Interrupt Enable     */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PCC_IER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_IER_OFFSET              0x04         /**< \brief (PCC_IER offset) Interrupt Enable Register */
-#define PCC_IER_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_IER reset_value) Interrupt Enable Register */
-
-#define PCC_IER_DRDY_Pos            0            /**< \brief (PCC_IER) Data Ready Interrupt Enable */
-#define PCC_IER_DRDY                (_U_(0x1) << PCC_IER_DRDY_Pos)
-#define PCC_IER_OVRE_Pos            1            /**< \brief (PCC_IER) Overrun Error Interrupt Enable */
-#define PCC_IER_OVRE                (_U_(0x1) << PCC_IER_OVRE_Pos)
-#define PCC_IER_MASK                _U_(0x00000003) /**< \brief (PCC_IER) MASK Register */
-
-/* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DRDY:1;           /*!< bit:      0  Data Ready Interrupt Disable       */
-    uint32_t OVRE:1;           /*!< bit:      1  Overrun Error Interrupt Disable    */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PCC_IDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_IDR_OFFSET              0x08         /**< \brief (PCC_IDR offset) Interrupt Disable Register */
-#define PCC_IDR_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_IDR reset_value) Interrupt Disable Register */
-
-#define PCC_IDR_DRDY_Pos            0            /**< \brief (PCC_IDR) Data Ready Interrupt Disable */
-#define PCC_IDR_DRDY                (_U_(0x1) << PCC_IDR_DRDY_Pos)
-#define PCC_IDR_OVRE_Pos            1            /**< \brief (PCC_IDR) Overrun Error Interrupt Disable */
-#define PCC_IDR_OVRE                (_U_(0x1) << PCC_IDR_OVRE_Pos)
-#define PCC_IDR_MASK                _U_(0x00000003) /**< \brief (PCC_IDR) MASK Register */
-
-/* -------- PCC_IMR : (PCC Offset: 0x0C) (R/  32) Interrupt Mask Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DRDY:1;           /*!< bit:      0  Data Ready Interrupt Mask          */
-    uint32_t OVRE:1;           /*!< bit:      1  Overrun Error Interrupt Mask       */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PCC_IMR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_IMR_OFFSET              0x0C         /**< \brief (PCC_IMR offset) Interrupt Mask Register */
-#define PCC_IMR_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_IMR reset_value) Interrupt Mask Register */
-
-#define PCC_IMR_DRDY_Pos            0            /**< \brief (PCC_IMR) Data Ready Interrupt Mask */
-#define PCC_IMR_DRDY                (_U_(0x1) << PCC_IMR_DRDY_Pos)
-#define PCC_IMR_OVRE_Pos            1            /**< \brief (PCC_IMR) Overrun Error Interrupt Mask */
-#define PCC_IMR_OVRE                (_U_(0x1) << PCC_IMR_OVRE_Pos)
-#define PCC_IMR_MASK                _U_(0x00000003) /**< \brief (PCC_IMR) MASK Register */
-
-/* -------- PCC_ISR : (PCC Offset: 0x10) (R/  32) Interrupt Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DRDY:1;           /*!< bit:      0  Data Ready Interrupt Status        */
-    uint32_t OVRE:1;           /*!< bit:      1  Overrun Error Interrupt Status     */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PCC_ISR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_ISR_OFFSET              0x10         /**< \brief (PCC_ISR offset) Interrupt Status Register */
-#define PCC_ISR_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_ISR reset_value) Interrupt Status Register */
-
-#define PCC_ISR_DRDY_Pos            0            /**< \brief (PCC_ISR) Data Ready Interrupt Status */
-#define PCC_ISR_DRDY                (_U_(0x1) << PCC_ISR_DRDY_Pos)
-#define PCC_ISR_OVRE_Pos            1            /**< \brief (PCC_ISR) Overrun Error Interrupt Status */
-#define PCC_ISR_OVRE                (_U_(0x1) << PCC_ISR_OVRE_Pos)
-#define PCC_ISR_MASK                _U_(0x00000003) /**< \brief (PCC_ISR) MASK Register */
-
-/* -------- PCC_RHR : (PCC Offset: 0x14) (R/  32) Reception Holding Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RDATA:32;         /*!< bit:  0..31  Reception Data                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PCC_RHR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_RHR_OFFSET              0x14         /**< \brief (PCC_RHR offset) Reception Holding Register */
-#define PCC_RHR_RESETVALUE          _U_(0x00000000) /**< \brief (PCC_RHR reset_value) Reception Holding Register */
-
-#define PCC_RHR_RDATA_Pos           0            /**< \brief (PCC_RHR) Reception Data */
-#define PCC_RHR_RDATA_Msk           (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
-#define PCC_RHR_RDATA(value)        (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
-#define PCC_RHR_MASK                _U_(0xFFFFFFFF) /**< \brief (PCC_RHR) MASK Register */
-
-/* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WPEN:1;           /*!< bit:      0  Write Protection Enable            */
-    uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
-    uint32_t WPKEY:24;         /*!< bit:  8..31  Write Protection Key               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PCC_WPMR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_WPMR_OFFSET             0xE0         /**< \brief (PCC_WPMR offset) Write Protection Mode Register */
-#define PCC_WPMR_RESETVALUE         _U_(0x00000000) /**< \brief (PCC_WPMR reset_value) Write Protection Mode Register */
-
-#define PCC_WPMR_WPEN_Pos           0            /**< \brief (PCC_WPMR) Write Protection Enable */
-#define PCC_WPMR_WPEN               (_U_(0x1) << PCC_WPMR_WPEN_Pos)
-#define PCC_WPMR_WPKEY_Pos          8            /**< \brief (PCC_WPMR) Write Protection Key */
-#define PCC_WPMR_WPKEY_Msk          (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
-#define PCC_WPMR_WPKEY(value)       (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
-#define PCC_WPMR_MASK               _U_(0xFFFFFF01) /**< \brief (PCC_WPMR) MASK Register */
-
-/* -------- PCC_WPSR : (PCC Offset: 0xE4) (R/  32) Write Protection Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WPVS:1;           /*!< bit:      0  Write Protection Violation Source  */
-    uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
-    uint32_t WPVSRC:16;        /*!< bit:  8..23  Write Protection Violation Status  */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PCC_WPSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PCC_WPSR_OFFSET             0xE4         /**< \brief (PCC_WPSR offset) Write Protection Status Register */
-#define PCC_WPSR_RESETVALUE         _U_(0x00000000) /**< \brief (PCC_WPSR reset_value) Write Protection Status Register */
-
-#define PCC_WPSR_WPVS_Pos           0            /**< \brief (PCC_WPSR) Write Protection Violation Source */
-#define PCC_WPSR_WPVS               (_U_(0x1) << PCC_WPSR_WPVS_Pos)
-#define PCC_WPSR_WPVSRC_Pos         8            /**< \brief (PCC_WPSR) Write Protection Violation Status */
-#define PCC_WPSR_WPVSRC_Msk         (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
-#define PCC_WPSR_WPVSRC(value)      (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
-#define PCC_WPSR_MASK               _U_(0x00FFFF01) /**< \brief (PCC_WPSR) MASK Register */
-
-/** \brief PCC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO PCC_MR_Type               MR;          /**< \brief Offset: 0x00 (R/W 32) Mode Register */
-  __O  PCC_IER_Type              IER;         /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Register */
-  __O  PCC_IDR_Type              IDR;         /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Register */
-  __I  PCC_IMR_Type              IMR;         /**< \brief Offset: 0x0C (R/  32) Interrupt Mask Register */
-  __I  PCC_ISR_Type              ISR;         /**< \brief Offset: 0x10 (R/  32) Interrupt Status Register */
-  __I  PCC_RHR_Type              RHR;         /**< \brief Offset: 0x14 (R/  32) Reception Holding Register */
-       RoReg8                    Reserved1[0xC8];
-  __IO PCC_WPMR_Type             WPMR;        /**< \brief Offset: 0xE0 (R/W 32) Write Protection Mode Register */
-  __I  PCC_WPSR_Type             WPSR;        /**< \brief Offset: 0xE4 (R/  32) Write Protection Status Register */
-} Pcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_PCC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pdec.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pdec.h
deleted file mode 100644
index 2cb862c05e..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pdec.h
+++ /dev/null
@@ -1,726 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for PDEC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PDEC_COMPONENT_
-#define _SAMD51_PDEC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR PDEC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_PDEC Quadrature Decodeur */
-/*@{*/
-
-#define PDEC_U2263
-#define REV_PDEC                    0x100
-
-/* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:2;           /*!< bit:  2.. 3  Operation Mode                     */
-    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t CONF:3;           /*!< bit:  8..10  PDEC Configuration                 */
-    uint32_t ALOCK:1;          /*!< bit:     11  Auto Lock                          */
-    uint32_t :2;               /*!< bit: 12..13  Reserved                           */
-    uint32_t SWAP:1;           /*!< bit:     14  PDEC Phase A and B Swap            */
-    uint32_t PEREN:1;          /*!< bit:     15  Period Enable                      */
-    uint32_t PINEN0:1;         /*!< bit:     16  PDEC Input From Pin 0 Enable       */
-    uint32_t PINEN1:1;         /*!< bit:     17  PDEC Input From Pin 1 Enable       */
-    uint32_t PINEN2:1;         /*!< bit:     18  PDEC Input From Pin 2 Enable       */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t PINVEN0:1;        /*!< bit:     20  IO Pin 0 Invert Enable             */
-    uint32_t PINVEN1:1;        /*!< bit:     21  IO Pin 1 Invert Enable             */
-    uint32_t PINVEN2:1;        /*!< bit:     22  IO Pin 2 Invert Enable             */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t ANGULAR:3;        /*!< bit: 24..26  Angular Counter Length             */
-    uint32_t :1;               /*!< bit:     27  Reserved                           */
-    uint32_t MAXCMP:4;         /*!< bit: 28..31  Maximum Consecutive Missing Pulses */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t PINEN:3;          /*!< bit: 16..18  PDEC Input From Pin x Enable       */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t PINVEN:3;         /*!< bit: 20..22  IO Pin x Invert Enable             */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PDEC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CTRLA_OFFSET           0x00         /**< \brief (PDEC_CTRLA offset) Control A */
-#define PDEC_CTRLA_RESETVALUE       _U_(0x00000000) /**< \brief (PDEC_CTRLA reset_value) Control A */
-
-#define PDEC_CTRLA_SWRST_Pos        0            /**< \brief (PDEC_CTRLA) Software Reset */
-#define PDEC_CTRLA_SWRST            (_U_(0x1) << PDEC_CTRLA_SWRST_Pos)
-#define PDEC_CTRLA_ENABLE_Pos       1            /**< \brief (PDEC_CTRLA) Enable */
-#define PDEC_CTRLA_ENABLE           (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos)
-#define PDEC_CTRLA_MODE_Pos         2            /**< \brief (PDEC_CTRLA) Operation Mode */
-#define PDEC_CTRLA_MODE_Msk         (_U_(0x3) << PDEC_CTRLA_MODE_Pos)
-#define PDEC_CTRLA_MODE(value)      (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
-#define   PDEC_CTRLA_MODE_QDEC_Val        _U_(0x0)   /**< \brief (PDEC_CTRLA) QDEC operating mode */
-#define   PDEC_CTRLA_MODE_HALL_Val        _U_(0x1)   /**< \brief (PDEC_CTRLA) HALL operating mode */
-#define   PDEC_CTRLA_MODE_COUNTER_Val     _U_(0x2)   /**< \brief (PDEC_CTRLA) COUNTER operating mode */
-#define PDEC_CTRLA_MODE_QDEC        (PDEC_CTRLA_MODE_QDEC_Val      << PDEC_CTRLA_MODE_Pos)
-#define PDEC_CTRLA_MODE_HALL        (PDEC_CTRLA_MODE_HALL_Val      << PDEC_CTRLA_MODE_Pos)
-#define PDEC_CTRLA_MODE_COUNTER     (PDEC_CTRLA_MODE_COUNTER_Val   << PDEC_CTRLA_MODE_Pos)
-#define PDEC_CTRLA_RUNSTDBY_Pos     6            /**< \brief (PDEC_CTRLA) Run in Standby */
-#define PDEC_CTRLA_RUNSTDBY         (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos)
-#define PDEC_CTRLA_CONF_Pos         8            /**< \brief (PDEC_CTRLA) PDEC Configuration */
-#define PDEC_CTRLA_CONF_Msk         (_U_(0x7) << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF(value)      (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
-#define   PDEC_CTRLA_CONF_X4_Val          _U_(0x0)   /**< \brief (PDEC_CTRLA) Quadrature decoder direction */
-#define   PDEC_CTRLA_CONF_X4S_Val         _U_(0x1)   /**< \brief (PDEC_CTRLA) Secure Quadrature decoder direction */
-#define   PDEC_CTRLA_CONF_X2_Val          _U_(0x2)   /**< \brief (PDEC_CTRLA) Decoder direction */
-#define   PDEC_CTRLA_CONF_X2S_Val         _U_(0x3)   /**< \brief (PDEC_CTRLA) Secure decoder direction */
-#define   PDEC_CTRLA_CONF_AUTOC_Val       _U_(0x4)   /**< \brief (PDEC_CTRLA) Auto correction mode */
-#define PDEC_CTRLA_CONF_X4          (PDEC_CTRLA_CONF_X4_Val        << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF_X4S         (PDEC_CTRLA_CONF_X4S_Val       << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF_X2          (PDEC_CTRLA_CONF_X2_Val        << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF_X2S         (PDEC_CTRLA_CONF_X2S_Val       << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_CONF_AUTOC       (PDEC_CTRLA_CONF_AUTOC_Val     << PDEC_CTRLA_CONF_Pos)
-#define PDEC_CTRLA_ALOCK_Pos        11           /**< \brief (PDEC_CTRLA) Auto Lock */
-#define PDEC_CTRLA_ALOCK            (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos)
-#define PDEC_CTRLA_SWAP_Pos         14           /**< \brief (PDEC_CTRLA) PDEC Phase A and B Swap */
-#define PDEC_CTRLA_SWAP             (_U_(0x1) << PDEC_CTRLA_SWAP_Pos)
-#define PDEC_CTRLA_PEREN_Pos        15           /**< \brief (PDEC_CTRLA) Period Enable */
-#define PDEC_CTRLA_PEREN            (_U_(0x1) << PDEC_CTRLA_PEREN_Pos)
-#define PDEC_CTRLA_PINEN0_Pos       16           /**< \brief (PDEC_CTRLA) PDEC Input From Pin 0 Enable */
-#define PDEC_CTRLA_PINEN0           (_U_(1) << PDEC_CTRLA_PINEN0_Pos)
-#define PDEC_CTRLA_PINEN1_Pos       17           /**< \brief (PDEC_CTRLA) PDEC Input From Pin 1 Enable */
-#define PDEC_CTRLA_PINEN1           (_U_(1) << PDEC_CTRLA_PINEN1_Pos)
-#define PDEC_CTRLA_PINEN2_Pos       18           /**< \brief (PDEC_CTRLA) PDEC Input From Pin 2 Enable */
-#define PDEC_CTRLA_PINEN2           (_U_(1) << PDEC_CTRLA_PINEN2_Pos)
-#define PDEC_CTRLA_PINEN_Pos        16           /**< \brief (PDEC_CTRLA) PDEC Input From Pin x Enable */
-#define PDEC_CTRLA_PINEN_Msk        (_U_(0x7) << PDEC_CTRLA_PINEN_Pos)
-#define PDEC_CTRLA_PINEN(value)     (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
-#define PDEC_CTRLA_PINVEN0_Pos      20           /**< \brief (PDEC_CTRLA) IO Pin 0 Invert Enable */
-#define PDEC_CTRLA_PINVEN0          (_U_(1) << PDEC_CTRLA_PINVEN0_Pos)
-#define PDEC_CTRLA_PINVEN1_Pos      21           /**< \brief (PDEC_CTRLA) IO Pin 1 Invert Enable */
-#define PDEC_CTRLA_PINVEN1          (_U_(1) << PDEC_CTRLA_PINVEN1_Pos)
-#define PDEC_CTRLA_PINVEN2_Pos      22           /**< \brief (PDEC_CTRLA) IO Pin 2 Invert Enable */
-#define PDEC_CTRLA_PINVEN2          (_U_(1) << PDEC_CTRLA_PINVEN2_Pos)
-#define PDEC_CTRLA_PINVEN_Pos       20           /**< \brief (PDEC_CTRLA) IO Pin x Invert Enable */
-#define PDEC_CTRLA_PINVEN_Msk       (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos)
-#define PDEC_CTRLA_PINVEN(value)    (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
-#define PDEC_CTRLA_ANGULAR_Pos      24           /**< \brief (PDEC_CTRLA) Angular Counter Length */
-#define PDEC_CTRLA_ANGULAR_Msk      (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos)
-#define PDEC_CTRLA_ANGULAR(value)   (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
-#define PDEC_CTRLA_MAXCMP_Pos       28           /**< \brief (PDEC_CTRLA) Maximum Consecutive Missing Pulses */
-#define PDEC_CTRLA_MAXCMP_Msk       (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos)
-#define PDEC_CTRLA_MAXCMP(value)    (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
-#define PDEC_CTRLA_MASK             _U_(0xF777CF4F) /**< \brief (PDEC_CTRLA) MASK Register */
-
-/* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W  8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  :3;               /*!< bit:  2.. 4  Reserved                           */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  Command                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CTRLBCLR_OFFSET        0x04         /**< \brief (PDEC_CTRLBCLR offset) Control B Clear */
-#define PDEC_CTRLBCLR_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_CTRLBCLR reset_value) Control B Clear */
-
-#define PDEC_CTRLBCLR_LUPD_Pos      1            /**< \brief (PDEC_CTRLBCLR) Lock Update */
-#define PDEC_CTRLBCLR_LUPD          (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos)
-#define PDEC_CTRLBCLR_CMD_Pos       5            /**< \brief (PDEC_CTRLBCLR) Command */
-#define PDEC_CTRLBCLR_CMD_Msk       (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD(value)    (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
-#define   PDEC_CTRLBCLR_CMD_NONE_Val      _U_(0x0)   /**< \brief (PDEC_CTRLBCLR) No action */
-#define   PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1)   /**< \brief (PDEC_CTRLBCLR) Force a counter restart or retrigger */
-#define   PDEC_CTRLBCLR_CMD_UPDATE_Val    _U_(0x2)   /**< \brief (PDEC_CTRLBCLR) Force update of double buffered registers */
-#define   PDEC_CTRLBCLR_CMD_READSYNC_Val  _U_(0x3)   /**< \brief (PDEC_CTRLBCLR) Force a read synchronization of COUNT */
-#define   PDEC_CTRLBCLR_CMD_START_Val     _U_(0x4)   /**< \brief (PDEC_CTRLBCLR) Start QDEC/HALL */
-#define   PDEC_CTRLBCLR_CMD_STOP_Val      _U_(0x5)   /**< \brief (PDEC_CTRLBCLR) Stop QDEC/HALL */
-#define PDEC_CTRLBCLR_CMD_NONE      (PDEC_CTRLBCLR_CMD_NONE_Val    << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_UPDATE    (PDEC_CTRLBCLR_CMD_UPDATE_Val  << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_READSYNC  (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_START     (PDEC_CTRLBCLR_CMD_START_Val   << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_CMD_STOP      (PDEC_CTRLBCLR_CMD_STOP_Val    << PDEC_CTRLBCLR_CMD_Pos)
-#define PDEC_CTRLBCLR_MASK          _U_(0xE2)    /**< \brief (PDEC_CTRLBCLR) MASK Register */
-
-/* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W  8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  :3;               /*!< bit:  2.. 4  Reserved                           */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  Command                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CTRLBSET_OFFSET        0x05         /**< \brief (PDEC_CTRLBSET offset) Control B Set */
-#define PDEC_CTRLBSET_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_CTRLBSET reset_value) Control B Set */
-
-#define PDEC_CTRLBSET_LUPD_Pos      1            /**< \brief (PDEC_CTRLBSET) Lock Update */
-#define PDEC_CTRLBSET_LUPD          (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos)
-#define PDEC_CTRLBSET_CMD_Pos       5            /**< \brief (PDEC_CTRLBSET) Command */
-#define PDEC_CTRLBSET_CMD_Msk       (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD(value)    (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
-#define   PDEC_CTRLBSET_CMD_NONE_Val      _U_(0x0)   /**< \brief (PDEC_CTRLBSET) No action */
-#define   PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1)   /**< \brief (PDEC_CTRLBSET) Force a counter restart or retrigger */
-#define   PDEC_CTRLBSET_CMD_UPDATE_Val    _U_(0x2)   /**< \brief (PDEC_CTRLBSET) Force update of double buffered registers */
-#define   PDEC_CTRLBSET_CMD_READSYNC_Val  _U_(0x3)   /**< \brief (PDEC_CTRLBSET) Force a read synchronization of COUNT */
-#define   PDEC_CTRLBSET_CMD_START_Val     _U_(0x4)   /**< \brief (PDEC_CTRLBSET) Start QDEC/HALL */
-#define   PDEC_CTRLBSET_CMD_STOP_Val      _U_(0x5)   /**< \brief (PDEC_CTRLBSET) Stop QDEC/HALL */
-#define PDEC_CTRLBSET_CMD_NONE      (PDEC_CTRLBSET_CMD_NONE_Val    << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_UPDATE    (PDEC_CTRLBSET_CMD_UPDATE_Val  << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_READSYNC  (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_START     (PDEC_CTRLBSET_CMD_START_Val   << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_CMD_STOP      (PDEC_CTRLBSET_CMD_STOP_Val    << PDEC_CTRLBSET_CMD_Pos)
-#define PDEC_CTRLBSET_MASK          _U_(0xE2)    /**< \brief (PDEC_CTRLBSET) MASK Register */
-
-/* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t EVACT:2;          /*!< bit:  0.. 1  Event Action                       */
-    uint16_t EVINV:3;          /*!< bit:  2.. 4  Inverted Event Input Enable        */
-    uint16_t EVEI:3;           /*!< bit:  5.. 7  Event Input Enable                 */
-    uint16_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
-    uint16_t ERREO:1;          /*!< bit:      9  Error  Output Event Enable         */
-    uint16_t DIREO:1;          /*!< bit:     10  Direction Output Event Enable      */
-    uint16_t VLCEO:1;          /*!< bit:     11  Velocity Output Event Enable       */
-    uint16_t MCEO0:1;          /*!< bit:     12  Match Channel 0 Event Output Enable */
-    uint16_t MCEO1:1;          /*!< bit:     13  Match Channel 1 Event Output Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
-    uint16_t MCEO:2;           /*!< bit: 12..13  Match Channel x Event Output Enable */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} PDEC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_EVCTRL_OFFSET          0x06         /**< \brief (PDEC_EVCTRL offset) Event Control */
-#define PDEC_EVCTRL_RESETVALUE      _U_(0x0000)  /**< \brief (PDEC_EVCTRL reset_value) Event Control */
-
-#define PDEC_EVCTRL_EVACT_Pos       0            /**< \brief (PDEC_EVCTRL) Event Action */
-#define PDEC_EVCTRL_EVACT_Msk       (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos)
-#define PDEC_EVCTRL_EVACT(value)    (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
-#define   PDEC_EVCTRL_EVACT_OFF_Val       _U_(0x0)   /**< \brief (PDEC_EVCTRL) Event action disabled */
-#define   PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1)   /**< \brief (PDEC_EVCTRL) Start, restart or retrigger on event */
-#define   PDEC_EVCTRL_EVACT_COUNT_Val     _U_(0x2)   /**< \brief (PDEC_EVCTRL) Count on event */
-#define PDEC_EVCTRL_EVACT_OFF       (PDEC_EVCTRL_EVACT_OFF_Val     << PDEC_EVCTRL_EVACT_Pos)
-#define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos)
-#define PDEC_EVCTRL_EVACT_COUNT     (PDEC_EVCTRL_EVACT_COUNT_Val   << PDEC_EVCTRL_EVACT_Pos)
-#define PDEC_EVCTRL_EVINV_Pos       2            /**< \brief (PDEC_EVCTRL) Inverted Event Input Enable */
-#define PDEC_EVCTRL_EVINV_Msk       (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos)
-#define PDEC_EVCTRL_EVINV(value)    (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
-#define PDEC_EVCTRL_EVEI_Pos        5            /**< \brief (PDEC_EVCTRL) Event Input Enable */
-#define PDEC_EVCTRL_EVEI_Msk        (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos)
-#define PDEC_EVCTRL_EVEI(value)     (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
-#define PDEC_EVCTRL_OVFEO_Pos       8            /**< \brief (PDEC_EVCTRL) Overflow/Underflow Output Event Enable */
-#define PDEC_EVCTRL_OVFEO           (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos)
-#define PDEC_EVCTRL_ERREO_Pos       9            /**< \brief (PDEC_EVCTRL) Error  Output Event Enable */
-#define PDEC_EVCTRL_ERREO           (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos)
-#define PDEC_EVCTRL_DIREO_Pos       10           /**< \brief (PDEC_EVCTRL) Direction Output Event Enable */
-#define PDEC_EVCTRL_DIREO           (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos)
-#define PDEC_EVCTRL_VLCEO_Pos       11           /**< \brief (PDEC_EVCTRL) Velocity Output Event Enable */
-#define PDEC_EVCTRL_VLCEO           (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos)
-#define PDEC_EVCTRL_MCEO0_Pos       12           /**< \brief (PDEC_EVCTRL) Match Channel 0 Event Output Enable */
-#define PDEC_EVCTRL_MCEO0           (_U_(1) << PDEC_EVCTRL_MCEO0_Pos)
-#define PDEC_EVCTRL_MCEO1_Pos       13           /**< \brief (PDEC_EVCTRL) Match Channel 1 Event Output Enable */
-#define PDEC_EVCTRL_MCEO1           (_U_(1) << PDEC_EVCTRL_MCEO1_Pos)
-#define PDEC_EVCTRL_MCEO_Pos        12           /**< \brief (PDEC_EVCTRL) Match Channel x Event Output Enable */
-#define PDEC_EVCTRL_MCEO_Msk        (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos)
-#define PDEC_EVCTRL_MCEO(value)     (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
-#define PDEC_EVCTRL_MASK            _U_(0x3FFF)  /**< \brief (PDEC_EVCTRL) MASK Register */
-
-/* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  OVF:1;            /*!< bit:      0  Overflow/Underflow Interrupt Disable */
-    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Disable            */
-    uint8_t  DIR:1;            /*!< bit:      2  Direction Interrupt Disable        */
-    uint8_t  VLC:1;            /*!< bit:      3  Velocity Interrupt Disable         */
-    uint8_t  MC0:1;            /*!< bit:      4  Channel 0 Compare Match Disable    */
-    uint8_t  MC1:1;            /*!< bit:      5  Channel 1 Compare Match Disable    */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  MC:2;             /*!< bit:  4.. 5  Channel x Compare Match Disable    */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_INTENCLR_OFFSET        0x08         /**< \brief (PDEC_INTENCLR offset) Interrupt Enable Clear */
-#define PDEC_INTENCLR_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define PDEC_INTENCLR_OVF_Pos       0            /**< \brief (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable */
-#define PDEC_INTENCLR_OVF           (_U_(0x1) << PDEC_INTENCLR_OVF_Pos)
-#define PDEC_INTENCLR_ERR_Pos       1            /**< \brief (PDEC_INTENCLR) Error Interrupt Disable */
-#define PDEC_INTENCLR_ERR           (_U_(0x1) << PDEC_INTENCLR_ERR_Pos)
-#define PDEC_INTENCLR_DIR_Pos       2            /**< \brief (PDEC_INTENCLR) Direction Interrupt Disable */
-#define PDEC_INTENCLR_DIR           (_U_(0x1) << PDEC_INTENCLR_DIR_Pos)
-#define PDEC_INTENCLR_VLC_Pos       3            /**< \brief (PDEC_INTENCLR) Velocity Interrupt Disable */
-#define PDEC_INTENCLR_VLC           (_U_(0x1) << PDEC_INTENCLR_VLC_Pos)
-#define PDEC_INTENCLR_MC0_Pos       4            /**< \brief (PDEC_INTENCLR) Channel 0 Compare Match Disable */
-#define PDEC_INTENCLR_MC0           (_U_(1) << PDEC_INTENCLR_MC0_Pos)
-#define PDEC_INTENCLR_MC1_Pos       5            /**< \brief (PDEC_INTENCLR) Channel 1 Compare Match Disable */
-#define PDEC_INTENCLR_MC1           (_U_(1) << PDEC_INTENCLR_MC1_Pos)
-#define PDEC_INTENCLR_MC_Pos        4            /**< \brief (PDEC_INTENCLR) Channel x Compare Match Disable */
-#define PDEC_INTENCLR_MC_Msk        (_U_(0x3) << PDEC_INTENCLR_MC_Pos)
-#define PDEC_INTENCLR_MC(value)     (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
-#define PDEC_INTENCLR_MASK          _U_(0x3F)    /**< \brief (PDEC_INTENCLR) MASK Register */
-
-/* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  OVF:1;            /*!< bit:      0  Overflow/Underflow Interrupt Enable */
-    uint8_t  ERR:1;            /*!< bit:      1  Error Interrupt Enable             */
-    uint8_t  DIR:1;            /*!< bit:      2  Direction Interrupt Enable         */
-    uint8_t  VLC:1;            /*!< bit:      3  Velocity Interrupt Enable          */
-    uint8_t  MC0:1;            /*!< bit:      4  Channel 0 Compare Match Enable     */
-    uint8_t  MC1:1;            /*!< bit:      5  Channel 1 Compare Match Enable     */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  MC:2;             /*!< bit:  4.. 5  Channel x Compare Match Enable     */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_INTENSET_OFFSET        0x09         /**< \brief (PDEC_INTENSET offset) Interrupt Enable Set */
-#define PDEC_INTENSET_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_INTENSET reset_value) Interrupt Enable Set */
-
-#define PDEC_INTENSET_OVF_Pos       0            /**< \brief (PDEC_INTENSET) Overflow/Underflow Interrupt Enable */
-#define PDEC_INTENSET_OVF           (_U_(0x1) << PDEC_INTENSET_OVF_Pos)
-#define PDEC_INTENSET_ERR_Pos       1            /**< \brief (PDEC_INTENSET) Error Interrupt Enable */
-#define PDEC_INTENSET_ERR           (_U_(0x1) << PDEC_INTENSET_ERR_Pos)
-#define PDEC_INTENSET_DIR_Pos       2            /**< \brief (PDEC_INTENSET) Direction Interrupt Enable */
-#define PDEC_INTENSET_DIR           (_U_(0x1) << PDEC_INTENSET_DIR_Pos)
-#define PDEC_INTENSET_VLC_Pos       3            /**< \brief (PDEC_INTENSET) Velocity Interrupt Enable */
-#define PDEC_INTENSET_VLC           (_U_(0x1) << PDEC_INTENSET_VLC_Pos)
-#define PDEC_INTENSET_MC0_Pos       4            /**< \brief (PDEC_INTENSET) Channel 0 Compare Match Enable */
-#define PDEC_INTENSET_MC0           (_U_(1) << PDEC_INTENSET_MC0_Pos)
-#define PDEC_INTENSET_MC1_Pos       5            /**< \brief (PDEC_INTENSET) Channel 1 Compare Match Enable */
-#define PDEC_INTENSET_MC1           (_U_(1) << PDEC_INTENSET_MC1_Pos)
-#define PDEC_INTENSET_MC_Pos        4            /**< \brief (PDEC_INTENSET) Channel x Compare Match Enable */
-#define PDEC_INTENSET_MC_Msk        (_U_(0x3) << PDEC_INTENSET_MC_Pos)
-#define PDEC_INTENSET_MC(value)     (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
-#define PDEC_INTENSET_MASK          _U_(0x3F)    /**< \brief (PDEC_INTENSET) MASK Register */
-
-/* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  OVF:1;            /*!< bit:      0  Overflow/Underflow                 */
-    __I uint8_t  ERR:1;            /*!< bit:      1  Error                              */
-    __I uint8_t  DIR:1;            /*!< bit:      2  Direction Change                   */
-    __I uint8_t  VLC:1;            /*!< bit:      3  Velocity                           */
-    __I uint8_t  MC0:1;            /*!< bit:      4  Channel 0 Compare Match            */
-    __I uint8_t  MC1:1;            /*!< bit:      5  Channel 1 Compare Match            */
-    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    __I uint8_t  MC:2;             /*!< bit:  4.. 5  Channel x Compare Match            */
-    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_INTFLAG_OFFSET         0x0A         /**< \brief (PDEC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define PDEC_INTFLAG_RESETVALUE     _U_(0x00)    /**< \brief (PDEC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define PDEC_INTFLAG_OVF_Pos        0            /**< \brief (PDEC_INTFLAG) Overflow/Underflow */
-#define PDEC_INTFLAG_OVF            (_U_(0x1) << PDEC_INTFLAG_OVF_Pos)
-#define PDEC_INTFLAG_ERR_Pos        1            /**< \brief (PDEC_INTFLAG) Error */
-#define PDEC_INTFLAG_ERR            (_U_(0x1) << PDEC_INTFLAG_ERR_Pos)
-#define PDEC_INTFLAG_DIR_Pos        2            /**< \brief (PDEC_INTFLAG) Direction Change */
-#define PDEC_INTFLAG_DIR            (_U_(0x1) << PDEC_INTFLAG_DIR_Pos)
-#define PDEC_INTFLAG_VLC_Pos        3            /**< \brief (PDEC_INTFLAG) Velocity */
-#define PDEC_INTFLAG_VLC            (_U_(0x1) << PDEC_INTFLAG_VLC_Pos)
-#define PDEC_INTFLAG_MC0_Pos        4            /**< \brief (PDEC_INTFLAG) Channel 0 Compare Match */
-#define PDEC_INTFLAG_MC0            (_U_(1) << PDEC_INTFLAG_MC0_Pos)
-#define PDEC_INTFLAG_MC1_Pos        5            /**< \brief (PDEC_INTFLAG) Channel 1 Compare Match */
-#define PDEC_INTFLAG_MC1            (_U_(1) << PDEC_INTFLAG_MC1_Pos)
-#define PDEC_INTFLAG_MC_Pos         4            /**< \brief (PDEC_INTFLAG) Channel x Compare Match */
-#define PDEC_INTFLAG_MC_Msk         (_U_(0x3) << PDEC_INTFLAG_MC_Pos)
-#define PDEC_INTFLAG_MC(value)      (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
-#define PDEC_INTFLAG_MASK           _U_(0x3F)    /**< \brief (PDEC_INTFLAG) MASK Register */
-
-/* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t QERR:1;           /*!< bit:      0  Quadrature Error Flag              */
-    uint16_t IDXERR:1;         /*!< bit:      1  Index Error Flag                   */
-    uint16_t MPERR:1;          /*!< bit:      2  Missing Pulse Error flag           */
-    uint16_t :1;               /*!< bit:      3  Reserved                           */
-    uint16_t WINERR:1;         /*!< bit:      4  Window Error Flag                  */
-    uint16_t HERR:1;           /*!< bit:      5  Hall Error Flag                    */
-    uint16_t STOP:1;           /*!< bit:      6  Stop                               */
-    uint16_t DIR:1;            /*!< bit:      7  Direction Status Flag              */
-    uint16_t PRESCBUFV:1;      /*!< bit:      8  Prescaler Buffer Valid             */
-    uint16_t FILTERBUFV:1;     /*!< bit:      9  Filter Buffer Valid                */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t CCBUFV0:1;        /*!< bit:     12  Compare Channel 0 Buffer Valid     */
-    uint16_t CCBUFV1:1;        /*!< bit:     13  Compare Channel 1 Buffer Valid     */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
-    uint16_t CCBUFV:2;         /*!< bit: 12..13  Compare Channel x Buffer Valid     */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} PDEC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_STATUS_OFFSET          0x0C         /**< \brief (PDEC_STATUS offset) Status */
-#define PDEC_STATUS_RESETVALUE      _U_(0x0040)  /**< \brief (PDEC_STATUS reset_value) Status */
-
-#define PDEC_STATUS_QERR_Pos        0            /**< \brief (PDEC_STATUS) Quadrature Error Flag */
-#define PDEC_STATUS_QERR            (_U_(0x1) << PDEC_STATUS_QERR_Pos)
-#define PDEC_STATUS_IDXERR_Pos      1            /**< \brief (PDEC_STATUS) Index Error Flag */
-#define PDEC_STATUS_IDXERR          (_U_(0x1) << PDEC_STATUS_IDXERR_Pos)
-#define PDEC_STATUS_MPERR_Pos       2            /**< \brief (PDEC_STATUS) Missing Pulse Error flag */
-#define PDEC_STATUS_MPERR           (_U_(0x1) << PDEC_STATUS_MPERR_Pos)
-#define PDEC_STATUS_WINERR_Pos      4            /**< \brief (PDEC_STATUS) Window Error Flag */
-#define PDEC_STATUS_WINERR          (_U_(0x1) << PDEC_STATUS_WINERR_Pos)
-#define PDEC_STATUS_HERR_Pos        5            /**< \brief (PDEC_STATUS) Hall Error Flag */
-#define PDEC_STATUS_HERR            (_U_(0x1) << PDEC_STATUS_HERR_Pos)
-#define PDEC_STATUS_STOP_Pos        6            /**< \brief (PDEC_STATUS) Stop */
-#define PDEC_STATUS_STOP            (_U_(0x1) << PDEC_STATUS_STOP_Pos)
-#define PDEC_STATUS_DIR_Pos         7            /**< \brief (PDEC_STATUS) Direction Status Flag */
-#define PDEC_STATUS_DIR             (_U_(0x1) << PDEC_STATUS_DIR_Pos)
-#define PDEC_STATUS_PRESCBUFV_Pos   8            /**< \brief (PDEC_STATUS) Prescaler Buffer Valid */
-#define PDEC_STATUS_PRESCBUFV       (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos)
-#define PDEC_STATUS_FILTERBUFV_Pos  9            /**< \brief (PDEC_STATUS) Filter Buffer Valid */
-#define PDEC_STATUS_FILTERBUFV      (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos)
-#define PDEC_STATUS_CCBUFV0_Pos     12           /**< \brief (PDEC_STATUS) Compare Channel 0 Buffer Valid */
-#define PDEC_STATUS_CCBUFV0         (_U_(1) << PDEC_STATUS_CCBUFV0_Pos)
-#define PDEC_STATUS_CCBUFV1_Pos     13           /**< \brief (PDEC_STATUS) Compare Channel 1 Buffer Valid */
-#define PDEC_STATUS_CCBUFV1         (_U_(1) << PDEC_STATUS_CCBUFV1_Pos)
-#define PDEC_STATUS_CCBUFV_Pos      12           /**< \brief (PDEC_STATUS) Compare Channel x Buffer Valid */
-#define PDEC_STATUS_CCBUFV_Msk      (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos)
-#define PDEC_STATUS_CCBUFV(value)   (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
-#define PDEC_STATUS_MASK            _U_(0x33F7)  /**< \brief (PDEC_STATUS) MASK Register */
-
-/* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run Mode                     */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_DBGCTRL_OFFSET         0x0F         /**< \brief (PDEC_DBGCTRL offset) Debug Control */
-#define PDEC_DBGCTRL_RESETVALUE     _U_(0x00)    /**< \brief (PDEC_DBGCTRL reset_value) Debug Control */
-
-#define PDEC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (PDEC_DBGCTRL) Debug Run Mode */
-#define PDEC_DBGCTRL_DBGRUN         (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos)
-#define PDEC_DBGCTRL_MASK           _U_(0x01)    /**< \brief (PDEC_DBGCTRL) MASK Register */
-
-/* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) (R/  32) Synchronization Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
-    uint32_t CTRLB:1;          /*!< bit:      2  Control B Synchronization Busy     */
-    uint32_t STATUS:1;         /*!< bit:      3  Status Synchronization Busy        */
-    uint32_t PRESC:1;          /*!< bit:      4  Prescaler Synchronization Busy     */
-    uint32_t FILTER:1;         /*!< bit:      5  Filter Synchronization Busy        */
-    uint32_t COUNT:1;          /*!< bit:      6  Count Synchronization Busy         */
-    uint32_t CC0:1;            /*!< bit:      7  Compare Channel 0 Synchronization Busy */
-    uint32_t CC1:1;            /*!< bit:      8  Compare Channel 1 Synchronization Busy */
-    uint32_t :23;              /*!< bit:  9..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :7;               /*!< bit:  0.. 6  Reserved                           */
-    uint32_t CC:2;             /*!< bit:  7.. 8  Compare Channel x Synchronization Busy */
-    uint32_t :23;              /*!< bit:  9..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PDEC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_SYNCBUSY_OFFSET        0x10         /**< \brief (PDEC_SYNCBUSY offset) Synchronization Status */
-#define PDEC_SYNCBUSY_RESETVALUE    _U_(0x00000000) /**< \brief (PDEC_SYNCBUSY reset_value) Synchronization Status */
-
-#define PDEC_SYNCBUSY_SWRST_Pos     0            /**< \brief (PDEC_SYNCBUSY) Software Reset Synchronization Busy */
-#define PDEC_SYNCBUSY_SWRST         (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos)
-#define PDEC_SYNCBUSY_ENABLE_Pos    1            /**< \brief (PDEC_SYNCBUSY) Enable Synchronization Busy */
-#define PDEC_SYNCBUSY_ENABLE        (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos)
-#define PDEC_SYNCBUSY_CTRLB_Pos     2            /**< \brief (PDEC_SYNCBUSY) Control B Synchronization Busy */
-#define PDEC_SYNCBUSY_CTRLB         (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos)
-#define PDEC_SYNCBUSY_STATUS_Pos    3            /**< \brief (PDEC_SYNCBUSY) Status Synchronization Busy */
-#define PDEC_SYNCBUSY_STATUS        (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos)
-#define PDEC_SYNCBUSY_PRESC_Pos     4            /**< \brief (PDEC_SYNCBUSY) Prescaler Synchronization Busy */
-#define PDEC_SYNCBUSY_PRESC         (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos)
-#define PDEC_SYNCBUSY_FILTER_Pos    5            /**< \brief (PDEC_SYNCBUSY) Filter Synchronization Busy */
-#define PDEC_SYNCBUSY_FILTER        (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos)
-#define PDEC_SYNCBUSY_COUNT_Pos     6            /**< \brief (PDEC_SYNCBUSY) Count Synchronization Busy */
-#define PDEC_SYNCBUSY_COUNT         (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos)
-#define PDEC_SYNCBUSY_CC0_Pos       7            /**< \brief (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy */
-#define PDEC_SYNCBUSY_CC0           (_U_(1) << PDEC_SYNCBUSY_CC0_Pos)
-#define PDEC_SYNCBUSY_CC1_Pos       8            /**< \brief (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy */
-#define PDEC_SYNCBUSY_CC1           (_U_(1) << PDEC_SYNCBUSY_CC1_Pos)
-#define PDEC_SYNCBUSY_CC_Pos        7            /**< \brief (PDEC_SYNCBUSY) Compare Channel x Synchronization Busy */
-#define PDEC_SYNCBUSY_CC_Msk        (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos)
-#define PDEC_SYNCBUSY_CC(value)     (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
-#define PDEC_SYNCBUSY_MASK          _U_(0x000001FF) /**< \brief (PDEC_SYNCBUSY) MASK Register */
-
-/* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W  8) Prescaler Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PRESC:4;          /*!< bit:  0.. 3  Prescaler Value                    */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_PRESC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_PRESC_OFFSET           0x14         /**< \brief (PDEC_PRESC offset) Prescaler Value */
-#define PDEC_PRESC_RESETVALUE       _U_(0x00)    /**< \brief (PDEC_PRESC reset_value) Prescaler Value */
-
-#define PDEC_PRESC_PRESC_Pos        0            /**< \brief (PDEC_PRESC) Prescaler Value */
-#define PDEC_PRESC_PRESC_Msk        (_U_(0xF) << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC(value)     (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
-#define   PDEC_PRESC_PRESC_DIV1_Val       _U_(0x0)   /**< \brief (PDEC_PRESC) No division */
-#define   PDEC_PRESC_PRESC_DIV2_Val       _U_(0x1)   /**< \brief (PDEC_PRESC) Divide by 2 */
-#define   PDEC_PRESC_PRESC_DIV4_Val       _U_(0x2)   /**< \brief (PDEC_PRESC) Divide by 4 */
-#define   PDEC_PRESC_PRESC_DIV8_Val       _U_(0x3)   /**< \brief (PDEC_PRESC) Divide by 8 */
-#define   PDEC_PRESC_PRESC_DIV16_Val      _U_(0x4)   /**< \brief (PDEC_PRESC) Divide by 16 */
-#define   PDEC_PRESC_PRESC_DIV32_Val      _U_(0x5)   /**< \brief (PDEC_PRESC) Divide by 32 */
-#define   PDEC_PRESC_PRESC_DIV64_Val      _U_(0x6)   /**< \brief (PDEC_PRESC) Divide by 64 */
-#define   PDEC_PRESC_PRESC_DIV128_Val     _U_(0x7)   /**< \brief (PDEC_PRESC) Divide by 128 */
-#define   PDEC_PRESC_PRESC_DIV256_Val     _U_(0x8)   /**< \brief (PDEC_PRESC) Divide by 256 */
-#define   PDEC_PRESC_PRESC_DIV512_Val     _U_(0x9)   /**< \brief (PDEC_PRESC) Divide by 512 */
-#define   PDEC_PRESC_PRESC_DIV1024_Val    _U_(0xA)   /**< \brief (PDEC_PRESC) Divide by 1024 */
-#define PDEC_PRESC_PRESC_DIV1       (PDEC_PRESC_PRESC_DIV1_Val     << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV2       (PDEC_PRESC_PRESC_DIV2_Val     << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV4       (PDEC_PRESC_PRESC_DIV4_Val     << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV8       (PDEC_PRESC_PRESC_DIV8_Val     << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV16      (PDEC_PRESC_PRESC_DIV16_Val    << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV32      (PDEC_PRESC_PRESC_DIV32_Val    << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV64      (PDEC_PRESC_PRESC_DIV64_Val    << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV128     (PDEC_PRESC_PRESC_DIV128_Val   << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV256     (PDEC_PRESC_PRESC_DIV256_Val   << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV512     (PDEC_PRESC_PRESC_DIV512_Val   << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_PRESC_DIV1024    (PDEC_PRESC_PRESC_DIV1024_Val  << PDEC_PRESC_PRESC_Pos)
-#define PDEC_PRESC_MASK             _U_(0x0F)    /**< \brief (PDEC_PRESC) MASK Register */
-
-/* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W  8) Filter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FILTER:8;         /*!< bit:  0.. 7  Filter Value                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_FILTER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_FILTER_OFFSET          0x15         /**< \brief (PDEC_FILTER offset) Filter Value */
-#define PDEC_FILTER_RESETVALUE      _U_(0x00)    /**< \brief (PDEC_FILTER reset_value) Filter Value */
-
-#define PDEC_FILTER_FILTER_Pos      0            /**< \brief (PDEC_FILTER) Filter Value */
-#define PDEC_FILTER_FILTER_Msk      (_U_(0xFF) << PDEC_FILTER_FILTER_Pos)
-#define PDEC_FILTER_FILTER(value)   (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
-#define PDEC_FILTER_MASK            _U_(0xFF)    /**< \brief (PDEC_FILTER) MASK Register */
-
-/* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W  8) Prescaler Buffer Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PRESCBUF:4;       /*!< bit:  0.. 3  Prescaler Buffer Value             */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_PRESCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_PRESCBUF_OFFSET        0x18         /**< \brief (PDEC_PRESCBUF offset) Prescaler Buffer Value */
-#define PDEC_PRESCBUF_RESETVALUE    _U_(0x00)    /**< \brief (PDEC_PRESCBUF reset_value) Prescaler Buffer Value */
-
-#define PDEC_PRESCBUF_PRESCBUF_Pos  0            /**< \brief (PDEC_PRESCBUF) Prescaler Buffer Value */
-#define PDEC_PRESCBUF_PRESCBUF_Msk  (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
-#define   PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0)   /**< \brief (PDEC_PRESCBUF) No division */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1)   /**< \brief (PDEC_PRESCBUF) Divide by 2 */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2)   /**< \brief (PDEC_PRESCBUF) Divide by 4 */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3)   /**< \brief (PDEC_PRESCBUF) Divide by 8 */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4)   /**< \brief (PDEC_PRESCBUF) Divide by 16 */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5)   /**< \brief (PDEC_PRESCBUF) Divide by 32 */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6)   /**< \brief (PDEC_PRESCBUF) Divide by 64 */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7)   /**< \brief (PDEC_PRESCBUF) Divide by 128 */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8)   /**< \brief (PDEC_PRESCBUF) Divide by 256 */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9)   /**< \brief (PDEC_PRESCBUF) Divide by 512 */
-#define   PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA)   /**< \brief (PDEC_PRESCBUF) Divide by 1024 */
-#define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
-#define PDEC_PRESCBUF_MASK          _U_(0x0F)    /**< \brief (PDEC_PRESCBUF) MASK Register */
-
-/* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W  8) Filter Buffer Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FILTERBUF:8;      /*!< bit:  0.. 7  Filter Buffer Value                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PDEC_FILTERBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_FILTERBUF_OFFSET       0x19         /**< \brief (PDEC_FILTERBUF offset) Filter Buffer Value */
-#define PDEC_FILTERBUF_RESETVALUE   _U_(0x00)    /**< \brief (PDEC_FILTERBUF reset_value) Filter Buffer Value */
-
-#define PDEC_FILTERBUF_FILTERBUF_Pos 0            /**< \brief (PDEC_FILTERBUF) Filter Buffer Value */
-#define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos)
-#define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
-#define PDEC_FILTERBUF_MASK         _U_(0xFF)    /**< \brief (PDEC_FILTERBUF) MASK Register */
-
-/* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PDEC_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_COUNT_OFFSET           0x1C         /**< \brief (PDEC_COUNT offset) Counter Value */
-#define PDEC_COUNT_RESETVALUE       _U_(0x00000000) /**< \brief (PDEC_COUNT reset_value) Counter Value */
-
-#define PDEC_COUNT_COUNT_Pos        0            /**< \brief (PDEC_COUNT) Counter Value */
-#define PDEC_COUNT_COUNT_Msk        (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos)
-#define PDEC_COUNT_COUNT(value)     (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
-#define PDEC_COUNT_MASK             _U_(0x0000FFFF) /**< \brief (PDEC_COUNT) MASK Register */
-
-/* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CC:16;            /*!< bit:  0..15  Channel Compare Value              */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PDEC_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CC_OFFSET              0x20         /**< \brief (PDEC_CC offset) Channel n Compare Value */
-#define PDEC_CC_RESETVALUE          _U_(0x00000000) /**< \brief (PDEC_CC reset_value) Channel n Compare Value */
-
-#define PDEC_CC_CC_Pos              0            /**< \brief (PDEC_CC) Channel Compare Value */
-#define PDEC_CC_CC_Msk              (_U_(0xFFFF) << PDEC_CC_CC_Pos)
-#define PDEC_CC_CC(value)           (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
-#define PDEC_CC_MASK                _U_(0x0000FFFF) /**< \brief (PDEC_CC) MASK Register */
-
-/* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CCBUF:16;         /*!< bit:  0..15  Channel Compare Buffer Value       */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PDEC_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PDEC_CCBUF_OFFSET           0x30         /**< \brief (PDEC_CCBUF offset) Channel Compare Buffer Value */
-#define PDEC_CCBUF_RESETVALUE       _U_(0x00000000) /**< \brief (PDEC_CCBUF reset_value) Channel Compare Buffer Value */
-
-#define PDEC_CCBUF_CCBUF_Pos        0            /**< \brief (PDEC_CCBUF) Channel Compare Buffer Value */
-#define PDEC_CCBUF_CCBUF_Msk        (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos)
-#define PDEC_CCBUF_CCBUF(value)     (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
-#define PDEC_CCBUF_MASK             _U_(0x0000FFFF) /**< \brief (PDEC_CCBUF) MASK Register */
-
-/** \brief PDEC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO PDEC_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO PDEC_CTRLBCLR_Type        CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO PDEC_CTRLBSET_Type        CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-  __IO PDEC_EVCTRL_Type          EVCTRL;      /**< \brief Offset: 0x06 (R/W 16) Event Control */
-  __IO PDEC_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
-  __IO PDEC_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
-  __IO PDEC_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved1[0x1];
-  __IO PDEC_STATUS_Type          STATUS;      /**< \brief Offset: 0x0C (R/W 16) Status */
-       RoReg8                    Reserved2[0x1];
-  __IO PDEC_DBGCTRL_Type         DBGCTRL;     /**< \brief Offset: 0x0F (R/W  8) Debug Control */
-  __I  PDEC_SYNCBUSY_Type        SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) Synchronization Status */
-  __IO PDEC_PRESC_Type           PRESC;       /**< \brief Offset: 0x14 (R/W  8) Prescaler Value */
-  __IO PDEC_FILTER_Type          FILTER;      /**< \brief Offset: 0x15 (R/W  8) Filter Value */
-       RoReg8                    Reserved3[0x2];
-  __IO PDEC_PRESCBUF_Type        PRESCBUF;    /**< \brief Offset: 0x18 (R/W  8) Prescaler Buffer Value */
-  __IO PDEC_FILTERBUF_Type       FILTERBUF;   /**< \brief Offset: 0x19 (R/W  8) Filter Buffer Value */
-       RoReg8                    Reserved4[0x2];
-  __IO PDEC_COUNT_Type           COUNT;       /**< \brief Offset: 0x1C (R/W 32) Counter Value */
-  __IO PDEC_CC_Type              CC[2];       /**< \brief Offset: 0x20 (R/W 32) Channel n Compare Value */
-       RoReg8                    Reserved5[0x8];
-  __IO PDEC_CCBUF_Type           CCBUF[2];    /**< \brief Offset: 0x30 (R/W 32) Channel Compare Buffer Value */
-} Pdec;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_PDEC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pm.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pm.h
deleted file mode 100644
index b6161047b5..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/pm.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for PM
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PM_COMPONENT_
-#define _SAMD51_PM_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR PM */
-/* ========================================================================== */
-/** \addtogroup SAMD51_PM Power Manager */
-/*@{*/
-
-#define PM_U2406
-#define REV_PM                      0x100
-
-/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint8_t  IORET:1;          /*!< bit:      2  I/O Retention                      */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_CTRLA_OFFSET             0x00         /**< \brief (PM_CTRLA offset) Control A */
-#define PM_CTRLA_RESETVALUE         _U_(0x00)    /**< \brief (PM_CTRLA reset_value) Control A */
-
-#define PM_CTRLA_IORET_Pos          2            /**< \brief (PM_CTRLA) I/O Retention */
-#define PM_CTRLA_IORET              (_U_(0x1) << PM_CTRLA_IORET_Pos)
-#define PM_CTRLA_MASK               _U_(0x04)    /**< \brief (PM_CTRLA) MASK Register */
-
-/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W  8) Sleep Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SLEEPMODE:3;      /*!< bit:  0.. 2  Sleep Mode                         */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_SLEEPCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_SLEEPCFG_OFFSET          0x01         /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
-#define PM_SLEEPCFG_RESETVALUE      _U_(0x02)    /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
-
-#define PM_SLEEPCFG_SLEEPMODE_Pos   0            /**< \brief (PM_SLEEPCFG) Sleep Mode */
-#define PM_SLEEPCFG_SLEEPMODE_Msk   (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
-#define   PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0)   /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
-#define   PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1)   /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
-#define   PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2)   /**< \brief (PM_SLEEPCFG) APB clock are OFF */
-#define   PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4)   /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
-#define   PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5)   /**< \brief (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */
-#define   PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6)   /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
-#define   PM_SLEEPCFG_SLEEPMODE_OFF_Val   _U_(0x7)   /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
-#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_SLEEPMODE_OFF   (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
-#define PM_SLEEPCFG_MASK            _U_(0x07)    /**< \brief (PM_SLEEPCFG) MASK Register */
-
-/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SLEEPRDY:1;       /*!< bit:      0  Sleep Mode Entry Ready Enable      */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTENCLR_OFFSET          0x04         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
-#define PM_INTENCLR_RESETVALUE      _U_(0x00)    /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define PM_INTENCLR_SLEEPRDY_Pos    0            /**< \brief (PM_INTENCLR) Sleep Mode Entry Ready Enable */
-#define PM_INTENCLR_SLEEPRDY        (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
-#define PM_INTENCLR_MASK            _U_(0x01)    /**< \brief (PM_INTENCLR) MASK Register */
-
-/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SLEEPRDY:1;       /*!< bit:      0  Sleep Mode Entry Ready Enable      */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTENSET_OFFSET          0x05         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
-#define PM_INTENSET_RESETVALUE      _U_(0x00)    /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
-
-#define PM_INTENSET_SLEEPRDY_Pos    0            /**< \brief (PM_INTENSET) Sleep Mode Entry Ready Enable */
-#define PM_INTENSET_SLEEPRDY        (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
-#define PM_INTENSET_MASK            _U_(0x01)    /**< \brief (PM_INTENSET) MASK Register */
-
-/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  SLEEPRDY:1;       /*!< bit:      0  Sleep Mode Entry Ready             */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_INTFLAG_OFFSET           0x06         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
-#define PM_INTFLAG_RESETVALUE       _U_(0x00)    /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define PM_INTFLAG_SLEEPRDY_Pos     0            /**< \brief (PM_INTFLAG) Sleep Mode Entry Ready */
-#define PM_INTFLAG_SLEEPRDY         (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
-#define PM_INTFLAG_MASK             _U_(0x01)    /**< \brief (PM_INTFLAG) MASK Register */
-
-/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W  8) Standby Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RAMCFG:2;         /*!< bit:  0.. 1  Ram Configuration                  */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  FASTWKUP:2;       /*!< bit:  4.. 5  Fast Wakeup                        */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_STDBYCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_STDBYCFG_OFFSET          0x08         /**< \brief (PM_STDBYCFG offset) Standby Configuration */
-#define PM_STDBYCFG_RESETVALUE      _U_(0x00)    /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
-
-#define PM_STDBYCFG_RAMCFG_Pos      0            /**< \brief (PM_STDBYCFG) Ram Configuration */
-#define PM_STDBYCFG_RAMCFG_Msk      (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
-#define PM_STDBYCFG_RAMCFG(value)   (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
-#define   PM_STDBYCFG_RAMCFG_RET_Val      _U_(0x0)   /**< \brief (PM_STDBYCFG) All the RAMs are retained */
-#define   PM_STDBYCFG_RAMCFG_PARTIAL_Val  _U_(0x1)   /**< \brief (PM_STDBYCFG) Only the first 32K bytes are retained */
-#define   PM_STDBYCFG_RAMCFG_OFF_Val      _U_(0x2)   /**< \brief (PM_STDBYCFG) All the RAMs are OFF */
-#define PM_STDBYCFG_RAMCFG_RET      (PM_STDBYCFG_RAMCFG_RET_Val    << PM_STDBYCFG_RAMCFG_Pos)
-#define PM_STDBYCFG_RAMCFG_PARTIAL  (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
-#define PM_STDBYCFG_RAMCFG_OFF      (PM_STDBYCFG_RAMCFG_OFF_Val    << PM_STDBYCFG_RAMCFG_Pos)
-#define PM_STDBYCFG_FASTWKUP_Pos    4            /**< \brief (PM_STDBYCFG) Fast Wakeup */
-#define PM_STDBYCFG_FASTWKUP_Msk    (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
-#define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
-#define PM_STDBYCFG_MASK            _U_(0x33)    /**< \brief (PM_STDBYCFG) MASK Register */
-
-/* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W  8) Hibernate Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RAMCFG:2;         /*!< bit:  0.. 1  Ram Configuration                  */
-    uint8_t  BRAMCFG:2;        /*!< bit:  2.. 3  Backup Ram Configuration           */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_HIBCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_HIBCFG_OFFSET            0x09         /**< \brief (PM_HIBCFG offset) Hibernate Configuration */
-#define PM_HIBCFG_RESETVALUE        _U_(0x00)    /**< \brief (PM_HIBCFG reset_value) Hibernate Configuration */
-
-#define PM_HIBCFG_RAMCFG_Pos        0            /**< \brief (PM_HIBCFG) Ram Configuration */
-#define PM_HIBCFG_RAMCFG_Msk        (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
-#define PM_HIBCFG_RAMCFG(value)     (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
-#define PM_HIBCFG_BRAMCFG_Pos       2            /**< \brief (PM_HIBCFG) Backup Ram Configuration */
-#define PM_HIBCFG_BRAMCFG_Msk       (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
-#define PM_HIBCFG_BRAMCFG(value)    (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
-#define PM_HIBCFG_MASK              _U_(0x0F)    /**< \brief (PM_HIBCFG) MASK Register */
-
-/* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W  8) Backup Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  BRAMCFG:2;        /*!< bit:  0.. 1  Ram Configuration                  */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_BKUPCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_BKUPCFG_OFFSET           0x0A         /**< \brief (PM_BKUPCFG offset) Backup Configuration */
-#define PM_BKUPCFG_RESETVALUE       _U_(0x00)    /**< \brief (PM_BKUPCFG reset_value) Backup Configuration */
-
-#define PM_BKUPCFG_BRAMCFG_Pos      0            /**< \brief (PM_BKUPCFG) Ram Configuration */
-#define PM_BKUPCFG_BRAMCFG_Msk      (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
-#define PM_BKUPCFG_BRAMCFG(value)   (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
-#define PM_BKUPCFG_MASK             _U_(0x03)    /**< \brief (PM_BKUPCFG) MASK Register */
-
-/* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W  8) Power Switch Acknowledge Delay -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DLYVAL:7;         /*!< bit:  0.. 6  Delay Value                        */
-    uint8_t  IGNACK:1;         /*!< bit:      7  Ignore Acknowledge                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PM_PWSAKDLY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PM_PWSAKDLY_OFFSET          0x12         /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */
-#define PM_PWSAKDLY_RESETVALUE      _U_(0x00)    /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */
-
-#define PM_PWSAKDLY_DLYVAL_Pos      0            /**< \brief (PM_PWSAKDLY) Delay Value */
-#define PM_PWSAKDLY_DLYVAL_Msk      (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
-#define PM_PWSAKDLY_DLYVAL(value)   (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
-#define PM_PWSAKDLY_IGNACK_Pos      7            /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */
-#define PM_PWSAKDLY_IGNACK          (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
-#define PM_PWSAKDLY_MASK            _U_(0xFF)    /**< \brief (PM_PWSAKDLY) MASK Register */
-
-/** \brief PM hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO PM_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
-  __IO PM_SLEEPCFG_Type          SLEEPCFG;    /**< \brief Offset: 0x01 (R/W  8) Sleep Configuration */
-       RoReg8                    Reserved1[0x2];
-  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
-  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
-  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved2[0x1];
-  __IO PM_STDBYCFG_Type          STDBYCFG;    /**< \brief Offset: 0x08 (R/W  8) Standby Configuration */
-  __IO PM_HIBCFG_Type            HIBCFG;      /**< \brief Offset: 0x09 (R/W  8) Hibernate Configuration */
-  __IO PM_BKUPCFG_Type           BKUPCFG;     /**< \brief Offset: 0x0A (R/W  8) Backup Configuration */
-       RoReg8                    Reserved3[0x7];
-  __IO PM_PWSAKDLY_Type          PWSAKDLY;    /**< \brief Offset: 0x12 (R/W  8) Power Switch Acknowledge Delay */
-} Pm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_PM_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/port.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/port.h
deleted file mode 100644
index 9727dcb0ac..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/port.h
+++ /dev/null
@@ -1,414 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for PORT
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PORT_COMPONENT_
-#define _SAMD51_PORT_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR PORT */
-/* ========================================================================== */
-/** \addtogroup SAMD51_PORT Port Module */
-/*@{*/
-
-#define PORT_U2210
-#define REV_PORT                    0x220
-
-/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DIR:32;           /*!< bit:  0..31  Port Data Direction                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_DIR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIR_OFFSET             0x00         /**< \brief (PORT_DIR offset) Data Direction */
-#define PORT_DIR_RESETVALUE         _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
-
-#define PORT_DIR_DIR_Pos            0            /**< \brief (PORT_DIR) Port Data Direction */
-#define PORT_DIR_DIR_Msk            (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
-#define PORT_DIR_DIR(value)         (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
-#define PORT_DIR_MASK               _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
-
-/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DIRCLR:32;        /*!< bit:  0..31  Port Data Direction Clear          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_DIRCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIRCLR_OFFSET          0x04         /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
-#define PORT_DIRCLR_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
-
-#define PORT_DIRCLR_DIRCLR_Pos      0            /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
-#define PORT_DIRCLR_DIRCLR_Msk      (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
-#define PORT_DIRCLR_DIRCLR(value)   (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
-#define PORT_DIRCLR_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
-
-/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DIRSET:32;        /*!< bit:  0..31  Port Data Direction Set            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_DIRSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIRSET_OFFSET          0x08         /**< \brief (PORT_DIRSET offset) Data Direction Set */
-#define PORT_DIRSET_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
-
-#define PORT_DIRSET_DIRSET_Pos      0            /**< \brief (PORT_DIRSET) Port Data Direction Set */
-#define PORT_DIRSET_DIRSET_Msk      (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
-#define PORT_DIRSET_DIRSET(value)   (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
-#define PORT_DIRSET_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
-
-/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DIRTGL:32;        /*!< bit:  0..31  Port Data Direction Toggle         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_DIRTGL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_DIRTGL_OFFSET          0x0C         /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
-#define PORT_DIRTGL_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
-
-#define PORT_DIRTGL_DIRTGL_Pos      0            /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
-#define PORT_DIRTGL_DIRTGL_Msk      (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
-#define PORT_DIRTGL_DIRTGL(value)   (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
-#define PORT_DIRTGL_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
-
-/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OUT:32;           /*!< bit:  0..31  PORT Data Output Value             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_OUT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUT_OFFSET             0x10         /**< \brief (PORT_OUT offset) Data Output Value */
-#define PORT_OUT_RESETVALUE         _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
-
-#define PORT_OUT_OUT_Pos            0            /**< \brief (PORT_OUT) PORT Data Output Value */
-#define PORT_OUT_OUT_Msk            (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
-#define PORT_OUT_OUT(value)         (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
-#define PORT_OUT_MASK               _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
-
-/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OUTCLR:32;        /*!< bit:  0..31  PORT Data Output Value Clear       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_OUTCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUTCLR_OFFSET          0x14         /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
-#define PORT_OUTCLR_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
-
-#define PORT_OUTCLR_OUTCLR_Pos      0            /**< \brief (PORT_OUTCLR) PORT Data Output Value Clear */
-#define PORT_OUTCLR_OUTCLR_Msk      (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
-#define PORT_OUTCLR_OUTCLR(value)   (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
-#define PORT_OUTCLR_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
-
-/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OUTSET:32;        /*!< bit:  0..31  PORT Data Output Value Set         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_OUTSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUTSET_OFFSET          0x18         /**< \brief (PORT_OUTSET offset) Data Output Value Set */
-#define PORT_OUTSET_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
-
-#define PORT_OUTSET_OUTSET_Pos      0            /**< \brief (PORT_OUTSET) PORT Data Output Value Set */
-#define PORT_OUTSET_OUTSET_Msk      (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
-#define PORT_OUTSET_OUTSET(value)   (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
-#define PORT_OUTSET_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
-
-/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OUTTGL:32;        /*!< bit:  0..31  PORT Data Output Value Toggle      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_OUTTGL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_OUTTGL_OFFSET          0x1C         /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
-#define PORT_OUTTGL_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
-
-#define PORT_OUTTGL_OUTTGL_Pos      0            /**< \brief (PORT_OUTTGL) PORT Data Output Value Toggle */
-#define PORT_OUTTGL_OUTTGL_Msk      (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
-#define PORT_OUTTGL_OUTTGL(value)   (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
-#define PORT_OUTTGL_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
-
-/* -------- PORT_IN : (PORT Offset: 0x20) (R/  32) GROUP Data Input Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t IN:32;            /*!< bit:  0..31  PORT Data Input Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_IN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_IN_OFFSET              0x20         /**< \brief (PORT_IN offset) Data Input Value */
-#define PORT_IN_RESETVALUE          _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
-
-#define PORT_IN_IN_Pos              0            /**< \brief (PORT_IN) PORT Data Input Value */
-#define PORT_IN_IN_Msk              (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
-#define PORT_IN_IN(value)           (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
-#define PORT_IN_MASK                _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
-
-/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SAMPLING:32;      /*!< bit:  0..31  Input Sampling Mode                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_CTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_CTRL_OFFSET            0x24         /**< \brief (PORT_CTRL offset) Control */
-#define PORT_CTRL_RESETVALUE        _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
-
-#define PORT_CTRL_SAMPLING_Pos      0            /**< \brief (PORT_CTRL) Input Sampling Mode */
-#define PORT_CTRL_SAMPLING_Msk      (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
-#define PORT_CTRL_SAMPLING(value)   (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
-#define PORT_CTRL_MASK              _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
-
-/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PINMASK:16;       /*!< bit:  0..15  Pin Mask for Multiple Pin Configuration */
-    uint32_t PMUXEN:1;         /*!< bit:     16  Peripheral Multiplexer Enable      */
-    uint32_t INEN:1;           /*!< bit:     17  Input Enable                       */
-    uint32_t PULLEN:1;         /*!< bit:     18  Pull Enable                        */
-    uint32_t :3;               /*!< bit: 19..21  Reserved                           */
-    uint32_t DRVSTR:1;         /*!< bit:     22  Output Driver Strength Selection   */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t PMUX:4;           /*!< bit: 24..27  Peripheral Multiplexing            */
-    uint32_t WRPMUX:1;         /*!< bit:     28  Write PMUX                         */
-    uint32_t :1;               /*!< bit:     29  Reserved                           */
-    uint32_t WRPINCFG:1;       /*!< bit:     30  Write PINCFG                       */
-    uint32_t HWSEL:1;          /*!< bit:     31  Half-Word Select                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_WRCONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_WRCONFIG_OFFSET        0x28         /**< \brief (PORT_WRCONFIG offset) Write Configuration */
-#define PORT_WRCONFIG_RESETVALUE    _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
-
-#define PORT_WRCONFIG_PINMASK_Pos   0            /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
-#define PORT_WRCONFIG_PINMASK_Msk   (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
-#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
-#define PORT_WRCONFIG_PMUXEN_Pos    16           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
-#define PORT_WRCONFIG_PMUXEN        (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
-#define PORT_WRCONFIG_INEN_Pos      17           /**< \brief (PORT_WRCONFIG) Input Enable */
-#define PORT_WRCONFIG_INEN          (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
-#define PORT_WRCONFIG_PULLEN_Pos    18           /**< \brief (PORT_WRCONFIG) Pull Enable */
-#define PORT_WRCONFIG_PULLEN        (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
-#define PORT_WRCONFIG_DRVSTR_Pos    22           /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
-#define PORT_WRCONFIG_DRVSTR        (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
-#define PORT_WRCONFIG_PMUX_Pos      24           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
-#define PORT_WRCONFIG_PMUX_Msk      (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
-#define PORT_WRCONFIG_PMUX(value)   (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
-#define PORT_WRCONFIG_WRPMUX_Pos    28           /**< \brief (PORT_WRCONFIG) Write PMUX */
-#define PORT_WRCONFIG_WRPMUX        (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
-#define PORT_WRCONFIG_WRPINCFG_Pos  30           /**< \brief (PORT_WRCONFIG) Write PINCFG */
-#define PORT_WRCONFIG_WRPINCFG      (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
-#define PORT_WRCONFIG_HWSEL_Pos     31           /**< \brief (PORT_WRCONFIG) Half-Word Select */
-#define PORT_WRCONFIG_HWSEL         (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
-#define PORT_WRCONFIG_MASK          _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
-
-/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PID0:5;           /*!< bit:  0.. 4  PORT Event Pin Identifier 0        */
-    uint32_t EVACT0:2;         /*!< bit:  5.. 6  PORT Event Action 0                */
-    uint32_t PORTEI0:1;        /*!< bit:      7  PORT Event Input Enable 0          */
-    uint32_t PID1:5;           /*!< bit:  8..12  PORT Event Pin Identifier 1        */
-    uint32_t EVACT1:2;         /*!< bit: 13..14  PORT Event Action 1                */
-    uint32_t PORTEI1:1;        /*!< bit:     15  PORT Event Input Enable 1          */
-    uint32_t PID2:5;           /*!< bit: 16..20  PORT Event Pin Identifier 2        */
-    uint32_t EVACT2:2;         /*!< bit: 21..22  PORT Event Action 2                */
-    uint32_t PORTEI2:1;        /*!< bit:     23  PORT Event Input Enable 2          */
-    uint32_t PID3:5;           /*!< bit: 24..28  PORT Event Pin Identifier 3        */
-    uint32_t EVACT3:2;         /*!< bit: 29..30  PORT Event Action 3                */
-    uint32_t PORTEI3:1;        /*!< bit:     31  PORT Event Input Enable 3          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} PORT_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_EVCTRL_OFFSET          0x2C         /**< \brief (PORT_EVCTRL offset) Event Input Control */
-#define PORT_EVCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */
-
-#define PORT_EVCTRL_PID0_Pos        0            /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 0 */
-#define PORT_EVCTRL_PID0_Msk        (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
-#define PORT_EVCTRL_PID0(value)     (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
-#define PORT_EVCTRL_EVACT0_Pos      5            /**< \brief (PORT_EVCTRL) PORT Event Action 0 */
-#define PORT_EVCTRL_EVACT0_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_EVACT0(value)   (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
-#define   PORT_EVCTRL_EVACT0_OUT_Val      _U_(0x0)   /**< \brief (PORT_EVCTRL) Event output to pin */
-#define   PORT_EVCTRL_EVACT0_SET_Val      _U_(0x1)   /**< \brief (PORT_EVCTRL) Set output register of pin on event */
-#define   PORT_EVCTRL_EVACT0_CLR_Val      _U_(0x2)   /**< \brief (PORT_EVCTRL) Clear output register of pin on event */
-#define   PORT_EVCTRL_EVACT0_TGL_Val      _U_(0x3)   /**< \brief (PORT_EVCTRL) Toggle output register of pin on event */
-#define PORT_EVCTRL_EVACT0_OUT      (PORT_EVCTRL_EVACT0_OUT_Val    << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_EVACT0_SET      (PORT_EVCTRL_EVACT0_SET_Val    << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_EVACT0_CLR      (PORT_EVCTRL_EVACT0_CLR_Val    << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_EVACT0_TGL      (PORT_EVCTRL_EVACT0_TGL_Val    << PORT_EVCTRL_EVACT0_Pos)
-#define PORT_EVCTRL_PORTEI0_Pos     7            /**< \brief (PORT_EVCTRL) PORT Event Input Enable 0 */
-#define PORT_EVCTRL_PORTEI0         (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
-#define PORT_EVCTRL_PID1_Pos        8            /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 1 */
-#define PORT_EVCTRL_PID1_Msk        (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
-#define PORT_EVCTRL_PID1(value)     (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
-#define PORT_EVCTRL_EVACT1_Pos      13           /**< \brief (PORT_EVCTRL) PORT Event Action 1 */
-#define PORT_EVCTRL_EVACT1_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
-#define PORT_EVCTRL_EVACT1(value)   (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
-#define PORT_EVCTRL_PORTEI1_Pos     15           /**< \brief (PORT_EVCTRL) PORT Event Input Enable 1 */
-#define PORT_EVCTRL_PORTEI1         (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
-#define PORT_EVCTRL_PID2_Pos        16           /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 2 */
-#define PORT_EVCTRL_PID2_Msk        (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
-#define PORT_EVCTRL_PID2(value)     (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
-#define PORT_EVCTRL_EVACT2_Pos      21           /**< \brief (PORT_EVCTRL) PORT Event Action 2 */
-#define PORT_EVCTRL_EVACT2_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
-#define PORT_EVCTRL_EVACT2(value)   (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
-#define PORT_EVCTRL_PORTEI2_Pos     23           /**< \brief (PORT_EVCTRL) PORT Event Input Enable 2 */
-#define PORT_EVCTRL_PORTEI2         (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
-#define PORT_EVCTRL_PID3_Pos        24           /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 3 */
-#define PORT_EVCTRL_PID3_Msk        (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
-#define PORT_EVCTRL_PID3(value)     (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
-#define PORT_EVCTRL_EVACT3_Pos      29           /**< \brief (PORT_EVCTRL) PORT Event Action 3 */
-#define PORT_EVCTRL_EVACT3_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
-#define PORT_EVCTRL_EVACT3(value)   (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
-#define PORT_EVCTRL_PORTEI3_Pos     31           /**< \brief (PORT_EVCTRL) PORT Event Input Enable 3 */
-#define PORT_EVCTRL_PORTEI3         (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
-#define PORT_EVCTRL_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */
-
-/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W  8) GROUP Peripheral Multiplexing -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PMUXE:4;          /*!< bit:  0.. 3  Peripheral Multiplexing for Even-Numbered Pin */
-    uint8_t  PMUXO:4;          /*!< bit:  4.. 7  Peripheral Multiplexing for Odd-Numbered Pin */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PORT_PMUX_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_PMUX_OFFSET            0x30         /**< \brief (PORT_PMUX offset) Peripheral Multiplexing */
-#define PORT_PMUX_RESETVALUE        _U_(0x00)    /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing */
-
-#define PORT_PMUX_PMUXE_Pos         0            /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */
-#define PORT_PMUX_PMUXE_Msk         (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
-#define PORT_PMUX_PMUXE(value)      (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
-#define PORT_PMUX_PMUXO_Pos         4            /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */
-#define PORT_PMUX_PMUXO_Msk         (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
-#define PORT_PMUX_PMUXO(value)      (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
-#define PORT_PMUX_MASK              _U_(0xFF)    /**< \brief (PORT_PMUX) MASK Register */
-
-/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W  8) GROUP Pin Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PMUXEN:1;         /*!< bit:      0  Peripheral Multiplexer Enable      */
-    uint8_t  INEN:1;           /*!< bit:      1  Input Enable                       */
-    uint8_t  PULLEN:1;         /*!< bit:      2  Pull Enable                        */
-    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint8_t  DRVSTR:1;         /*!< bit:      6  Output Driver Strength Selection   */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} PORT_PINCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define PORT_PINCFG_OFFSET          0x40         /**< \brief (PORT_PINCFG offset) Pin Configuration */
-#define PORT_PINCFG_RESETVALUE      _U_(0x00)    /**< \brief (PORT_PINCFG reset_value) Pin Configuration */
-
-#define PORT_PINCFG_PMUXEN_Pos      0            /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
-#define PORT_PINCFG_PMUXEN          (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
-#define PORT_PINCFG_INEN_Pos        1            /**< \brief (PORT_PINCFG) Input Enable */
-#define PORT_PINCFG_INEN            (_U_(0x1) << PORT_PINCFG_INEN_Pos)
-#define PORT_PINCFG_PULLEN_Pos      2            /**< \brief (PORT_PINCFG) Pull Enable */
-#define PORT_PINCFG_PULLEN          (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
-#define PORT_PINCFG_DRVSTR_Pos      6            /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
-#define PORT_PINCFG_DRVSTR          (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
-#define PORT_PINCFG_MASK            _U_(0x47)    /**< \brief (PORT_PINCFG) MASK Register */
-
-/** \brief PortGroup hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO PORT_DIR_Type             DIR;         /**< \brief Offset: 0x00 (R/W 32) Data Direction */
-  __IO PORT_DIRCLR_Type          DIRCLR;      /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
-  __IO PORT_DIRSET_Type          DIRSET;      /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
-  __IO PORT_DIRTGL_Type          DIRTGL;      /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
-  __IO PORT_OUT_Type             OUT;         /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
-  __IO PORT_OUTCLR_Type          OUTCLR;      /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
-  __IO PORT_OUTSET_Type          OUTSET;      /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
-  __IO PORT_OUTTGL_Type          OUTTGL;      /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
-  __I  PORT_IN_Type              IN;          /**< \brief Offset: 0x20 (R/  32) Data Input Value */
-  __IO PORT_CTRL_Type            CTRL;        /**< \brief Offset: 0x24 (R/W 32) Control */
-  __O  PORT_WRCONFIG_Type        WRCONFIG;    /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
-  __IO PORT_EVCTRL_Type          EVCTRL;      /**< \brief Offset: 0x2C (R/W 32) Event Input Control */
-  __IO PORT_PMUX_Type            PMUX[16];    /**< \brief Offset: 0x30 (R/W  8) Peripheral Multiplexing */
-  __IO PORT_PINCFG_Type          PINCFG[32];  /**< \brief Offset: 0x40 (R/W  8) Pin Configuration */
-       RoReg8                    Reserved1[0x20];
-} PortGroup;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief PORT hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-       PortGroup                 Group[4];    /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
-} Port;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_PORT_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/qspi.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/qspi.h
deleted file mode 100644
index 208a955d62..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/qspi.h
+++ /dev/null
@@ -1,528 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for QSPI
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_QSPI_COMPONENT_
-#define _SAMD51_QSPI_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR QSPI */
-/* ========================================================================== */
-/** \addtogroup SAMD51_QSPI Quad SPI interface */
-/*@{*/
-
-#define QSPI_U2008
-#define REV_QSPI                    0x163
-
-/* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t :22;              /*!< bit:  2..23  Reserved                           */
-    uint32_t LASTXFER:1;       /*!< bit:     24  Last Transfer                      */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_CTRLA_OFFSET           0x00         /**< \brief (QSPI_CTRLA offset) Control A */
-#define QSPI_CTRLA_RESETVALUE       _U_(0x00000000) /**< \brief (QSPI_CTRLA reset_value) Control A */
-
-#define QSPI_CTRLA_SWRST_Pos        0            /**< \brief (QSPI_CTRLA) Software Reset */
-#define QSPI_CTRLA_SWRST            (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
-#define QSPI_CTRLA_ENABLE_Pos       1            /**< \brief (QSPI_CTRLA) Enable */
-#define QSPI_CTRLA_ENABLE           (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
-#define QSPI_CTRLA_LASTXFER_Pos     24           /**< \brief (QSPI_CTRLA) Last Transfer */
-#define QSPI_CTRLA_LASTXFER         (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
-#define QSPI_CTRLA_MASK             _U_(0x01000003) /**< \brief (QSPI_CTRLA) MASK Register */
-
-/* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t MODE:1;           /*!< bit:      0  Serial Memory Mode                 */
-    uint32_t LOOPEN:1;         /*!< bit:      1  Local Loopback Enable              */
-    uint32_t WDRBT:1;          /*!< bit:      2  Wait Data Read Before Transfer     */
-    uint32_t SMEMREG:1;        /*!< bit:      3  Serial Memory reg                  */
-    uint32_t CSMODE:2;         /*!< bit:  4.. 5  Chip Select Mode                   */
-    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint32_t DATALEN:4;        /*!< bit:  8..11  Data Length                        */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t DLYBCT:8;         /*!< bit: 16..23  Delay Between Consecutive Transfers */
-    uint32_t DLYCS:8;          /*!< bit: 24..31  Minimum Inactive CS Delay          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_CTRLB_OFFSET           0x04         /**< \brief (QSPI_CTRLB offset) Control B */
-#define QSPI_CTRLB_RESETVALUE       _U_(0x00000000) /**< \brief (QSPI_CTRLB reset_value) Control B */
-
-#define QSPI_CTRLB_MODE_Pos         0            /**< \brief (QSPI_CTRLB) Serial Memory Mode */
-#define QSPI_CTRLB_MODE             (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
-#define   QSPI_CTRLB_MODE_SPI_Val         _U_(0x0)   /**< \brief (QSPI_CTRLB) SPI operating mode */
-#define   QSPI_CTRLB_MODE_MEMORY_Val      _U_(0x1)   /**< \brief (QSPI_CTRLB) Serial Memory operating mode */
-#define QSPI_CTRLB_MODE_SPI         (QSPI_CTRLB_MODE_SPI_Val       << QSPI_CTRLB_MODE_Pos)
-#define QSPI_CTRLB_MODE_MEMORY      (QSPI_CTRLB_MODE_MEMORY_Val    << QSPI_CTRLB_MODE_Pos)
-#define QSPI_CTRLB_LOOPEN_Pos       1            /**< \brief (QSPI_CTRLB) Local Loopback Enable */
-#define QSPI_CTRLB_LOOPEN           (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
-#define QSPI_CTRLB_WDRBT_Pos        2            /**< \brief (QSPI_CTRLB) Wait Data Read Before Transfer */
-#define QSPI_CTRLB_WDRBT            (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
-#define QSPI_CTRLB_SMEMREG_Pos      3            /**< \brief (QSPI_CTRLB) Serial Memory reg */
-#define QSPI_CTRLB_SMEMREG          (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
-#define QSPI_CTRLB_CSMODE_Pos       4            /**< \brief (QSPI_CTRLB) Chip Select Mode */
-#define QSPI_CTRLB_CSMODE_Msk       (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
-#define QSPI_CTRLB_CSMODE(value)    (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
-#define   QSPI_CTRLB_CSMODE_NORELOAD_Val  _U_(0x0)   /**< \brief (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
-#define   QSPI_CTRLB_CSMODE_LASTXFER_Val  _U_(0x1)   /**< \brief (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
-#define   QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2)   /**< \brief (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. */
-#define QSPI_CTRLB_CSMODE_NORELOAD  (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
-#define QSPI_CTRLB_CSMODE_LASTXFER  (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
-#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
-#define QSPI_CTRLB_DATALEN_Pos      8            /**< \brief (QSPI_CTRLB) Data Length */
-#define QSPI_CTRLB_DATALEN_Msk      (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN(value)   (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
-#define   QSPI_CTRLB_DATALEN_8BITS_Val    _U_(0x0)   /**< \brief (QSPI_CTRLB) 8-bits transfer */
-#define   QSPI_CTRLB_DATALEN_9BITS_Val    _U_(0x1)   /**< \brief (QSPI_CTRLB) 9 bits transfer */
-#define   QSPI_CTRLB_DATALEN_10BITS_Val   _U_(0x2)   /**< \brief (QSPI_CTRLB) 10-bits transfer */
-#define   QSPI_CTRLB_DATALEN_11BITS_Val   _U_(0x3)   /**< \brief (QSPI_CTRLB) 11-bits transfer */
-#define   QSPI_CTRLB_DATALEN_12BITS_Val   _U_(0x4)   /**< \brief (QSPI_CTRLB) 12-bits transfer */
-#define   QSPI_CTRLB_DATALEN_13BITS_Val   _U_(0x5)   /**< \brief (QSPI_CTRLB) 13-bits transfer */
-#define   QSPI_CTRLB_DATALEN_14BITS_Val   _U_(0x6)   /**< \brief (QSPI_CTRLB) 14-bits transfer */
-#define   QSPI_CTRLB_DATALEN_15BITS_Val   _U_(0x7)   /**< \brief (QSPI_CTRLB) 15-bits transfer */
-#define   QSPI_CTRLB_DATALEN_16BITS_Val   _U_(0x8)   /**< \brief (QSPI_CTRLB) 16-bits transfer */
-#define QSPI_CTRLB_DATALEN_8BITS    (QSPI_CTRLB_DATALEN_8BITS_Val  << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_9BITS    (QSPI_CTRLB_DATALEN_9BITS_Val  << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_10BITS   (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_11BITS   (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_12BITS   (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_13BITS   (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_14BITS   (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_15BITS   (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DATALEN_16BITS   (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
-#define QSPI_CTRLB_DLYBCT_Pos       16           /**< \brief (QSPI_CTRLB) Delay Between Consecutive Transfers */
-#define QSPI_CTRLB_DLYBCT_Msk       (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
-#define QSPI_CTRLB_DLYBCT(value)    (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
-#define QSPI_CTRLB_DLYCS_Pos        24           /**< \brief (QSPI_CTRLB) Minimum Inactive CS Delay */
-#define QSPI_CTRLB_DLYCS_Msk        (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
-#define QSPI_CTRLB_DLYCS(value)     (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
-#define QSPI_CTRLB_MASK             _U_(0xFFFF0F3F) /**< \brief (QSPI_CTRLB) MASK Register */
-
-/* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CPOL:1;           /*!< bit:      0  Clock Polarity                     */
-    uint32_t CPHA:1;           /*!< bit:      1  Clock Phase                        */
-    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
-    uint32_t BAUD:8;           /*!< bit:  8..15  Serial Clock Baud Rate             */
-    uint32_t DLYBS:8;          /*!< bit: 16..23  Delay Before SCK                   */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_BAUD_OFFSET            0x08         /**< \brief (QSPI_BAUD offset) Baud Rate */
-#define QSPI_BAUD_RESETVALUE        _U_(0x00000000) /**< \brief (QSPI_BAUD reset_value) Baud Rate */
-
-#define QSPI_BAUD_CPOL_Pos          0            /**< \brief (QSPI_BAUD) Clock Polarity */
-#define QSPI_BAUD_CPOL              (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
-#define QSPI_BAUD_CPHA_Pos          1            /**< \brief (QSPI_BAUD) Clock Phase */
-#define QSPI_BAUD_CPHA              (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
-#define QSPI_BAUD_BAUD_Pos          8            /**< \brief (QSPI_BAUD) Serial Clock Baud Rate */
-#define QSPI_BAUD_BAUD_Msk          (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
-#define QSPI_BAUD_BAUD(value)       (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
-#define QSPI_BAUD_DLYBS_Pos         16           /**< \brief (QSPI_BAUD) Delay Before SCK */
-#define QSPI_BAUD_DLYBS_Msk         (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
-#define QSPI_BAUD_DLYBS(value)      (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
-#define QSPI_BAUD_MASK              _U_(0x00FFFF03) /**< \brief (QSPI_BAUD) MASK Register */
-
-/* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) (R/  32) Receive Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:16;          /*!< bit:  0..15  Receive Data                       */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_RXDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_RXDATA_OFFSET          0x0C         /**< \brief (QSPI_RXDATA offset) Receive Data */
-#define QSPI_RXDATA_RESETVALUE      _U_(0x00000000) /**< \brief (QSPI_RXDATA reset_value) Receive Data */
-
-#define QSPI_RXDATA_DATA_Pos        0            /**< \brief (QSPI_RXDATA) Receive Data */
-#define QSPI_RXDATA_DATA_Msk        (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
-#define QSPI_RXDATA_DATA(value)     (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
-#define QSPI_RXDATA_MASK            _U_(0x0000FFFF) /**< \brief (QSPI_RXDATA) MASK Register */
-
-/* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:16;          /*!< bit:  0..15  Transmit Data                      */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_TXDATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_TXDATA_OFFSET          0x10         /**< \brief (QSPI_TXDATA offset) Transmit Data */
-#define QSPI_TXDATA_RESETVALUE      _U_(0x00000000) /**< \brief (QSPI_TXDATA reset_value) Transmit Data */
-
-#define QSPI_TXDATA_DATA_Pos        0            /**< \brief (QSPI_TXDATA) Transmit Data */
-#define QSPI_TXDATA_DATA_Msk        (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
-#define QSPI_TXDATA_DATA(value)     (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
-#define QSPI_TXDATA_MASK            _U_(0x0000FFFF) /**< \brief (QSPI_TXDATA) MASK Register */
-
-/* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RXC:1;            /*!< bit:      0  Receive Data Register Full Interrupt Disable */
-    uint32_t DRE:1;            /*!< bit:      1  Transmit Data Register Empty Interrupt Disable */
-    uint32_t TXC:1;            /*!< bit:      2  Transmission Complete Interrupt Disable */
-    uint32_t ERROR:1;          /*!< bit:      3  Overrun Error Interrupt Disable    */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t CSRISE:1;         /*!< bit:      8  Chip Select Rise Interrupt Disable */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t INSTREND:1;       /*!< bit:     10  Instruction End Interrupt Disable  */
-    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INTENCLR_OFFSET        0x14         /**< \brief (QSPI_INTENCLR offset) Interrupt Enable Clear */
-#define QSPI_INTENCLR_RESETVALUE    _U_(0x00000000) /**< \brief (QSPI_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define QSPI_INTENCLR_RXC_Pos       0            /**< \brief (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable */
-#define QSPI_INTENCLR_RXC           (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
-#define QSPI_INTENCLR_DRE_Pos       1            /**< \brief (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable */
-#define QSPI_INTENCLR_DRE           (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
-#define QSPI_INTENCLR_TXC_Pos       2            /**< \brief (QSPI_INTENCLR) Transmission Complete Interrupt Disable */
-#define QSPI_INTENCLR_TXC           (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
-#define QSPI_INTENCLR_ERROR_Pos     3            /**< \brief (QSPI_INTENCLR) Overrun Error Interrupt Disable */
-#define QSPI_INTENCLR_ERROR         (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
-#define QSPI_INTENCLR_CSRISE_Pos    8            /**< \brief (QSPI_INTENCLR) Chip Select Rise Interrupt Disable */
-#define QSPI_INTENCLR_CSRISE        (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
-#define QSPI_INTENCLR_INSTREND_Pos  10           /**< \brief (QSPI_INTENCLR) Instruction End Interrupt Disable */
-#define QSPI_INTENCLR_INSTREND      (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
-#define QSPI_INTENCLR_MASK          _U_(0x0000050F) /**< \brief (QSPI_INTENCLR) MASK Register */
-
-/* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RXC:1;            /*!< bit:      0  Receive Data Register Full Interrupt Enable */
-    uint32_t DRE:1;            /*!< bit:      1  Transmit Data Register Empty Interrupt Enable */
-    uint32_t TXC:1;            /*!< bit:      2  Transmission Complete Interrupt Enable */
-    uint32_t ERROR:1;          /*!< bit:      3  Overrun Error Interrupt Enable     */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t CSRISE:1;         /*!< bit:      8  Chip Select Rise Interrupt Enable  */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t INSTREND:1;       /*!< bit:     10  Instruction End Interrupt Enable   */
-    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INTENSET_OFFSET        0x18         /**< \brief (QSPI_INTENSET offset) Interrupt Enable Set */
-#define QSPI_INTENSET_RESETVALUE    _U_(0x00000000) /**< \brief (QSPI_INTENSET reset_value) Interrupt Enable Set */
-
-#define QSPI_INTENSET_RXC_Pos       0            /**< \brief (QSPI_INTENSET) Receive Data Register Full Interrupt Enable */
-#define QSPI_INTENSET_RXC           (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
-#define QSPI_INTENSET_DRE_Pos       1            /**< \brief (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable */
-#define QSPI_INTENSET_DRE           (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
-#define QSPI_INTENSET_TXC_Pos       2            /**< \brief (QSPI_INTENSET) Transmission Complete Interrupt Enable */
-#define QSPI_INTENSET_TXC           (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
-#define QSPI_INTENSET_ERROR_Pos     3            /**< \brief (QSPI_INTENSET) Overrun Error Interrupt Enable */
-#define QSPI_INTENSET_ERROR         (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
-#define QSPI_INTENSET_CSRISE_Pos    8            /**< \brief (QSPI_INTENSET) Chip Select Rise Interrupt Enable */
-#define QSPI_INTENSET_CSRISE        (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
-#define QSPI_INTENSET_INSTREND_Pos  10           /**< \brief (QSPI_INTENSET) Instruction End Interrupt Enable */
-#define QSPI_INTENSET_INSTREND      (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
-#define QSPI_INTENSET_MASK          _U_(0x0000050F) /**< \brief (QSPI_INTENSET) MASK Register */
-
-/* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t RXC:1;            /*!< bit:      0  Receive Data Register Full         */
-    __I uint32_t DRE:1;            /*!< bit:      1  Transmit Data Register Empty       */
-    __I uint32_t TXC:1;            /*!< bit:      2  Transmission Complete              */
-    __I uint32_t ERROR:1;          /*!< bit:      3  Overrun Error                      */
-    __I uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    __I uint32_t CSRISE:1;         /*!< bit:      8  Chip Select Rise                   */
-    __I uint32_t :1;               /*!< bit:      9  Reserved                           */
-    __I uint32_t INSTREND:1;       /*!< bit:     10  Instruction End                    */
-    __I uint32_t :21;              /*!< bit: 11..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INTFLAG_OFFSET         0x1C         /**< \brief (QSPI_INTFLAG offset) Interrupt Flag Status and Clear */
-#define QSPI_INTFLAG_RESETVALUE     _U_(0x00000000) /**< \brief (QSPI_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define QSPI_INTFLAG_RXC_Pos        0            /**< \brief (QSPI_INTFLAG) Receive Data Register Full */
-#define QSPI_INTFLAG_RXC            (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
-#define QSPI_INTFLAG_DRE_Pos        1            /**< \brief (QSPI_INTFLAG) Transmit Data Register Empty */
-#define QSPI_INTFLAG_DRE            (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
-#define QSPI_INTFLAG_TXC_Pos        2            /**< \brief (QSPI_INTFLAG) Transmission Complete */
-#define QSPI_INTFLAG_TXC            (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
-#define QSPI_INTFLAG_ERROR_Pos      3            /**< \brief (QSPI_INTFLAG) Overrun Error */
-#define QSPI_INTFLAG_ERROR          (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
-#define QSPI_INTFLAG_CSRISE_Pos     8            /**< \brief (QSPI_INTFLAG) Chip Select Rise */
-#define QSPI_INTFLAG_CSRISE         (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
-#define QSPI_INTFLAG_INSTREND_Pos   10           /**< \brief (QSPI_INTFLAG) Instruction End */
-#define QSPI_INTFLAG_INSTREND       (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
-#define QSPI_INTFLAG_MASK           _U_(0x0000050F) /**< \brief (QSPI_INTFLAG) MASK Register */
-
-/* -------- QSPI_STATUS : (QSPI Offset: 0x20) (R/  32) Status Register -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t :7;               /*!< bit:  2.. 8  Reserved                           */
-    uint32_t CSSTATUS:1;       /*!< bit:      9  Chip Select                        */
-    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_STATUS_OFFSET          0x20         /**< \brief (QSPI_STATUS offset) Status Register */
-#define QSPI_STATUS_RESETVALUE      _U_(0x00000200) /**< \brief (QSPI_STATUS reset_value) Status Register */
-
-#define QSPI_STATUS_ENABLE_Pos      1            /**< \brief (QSPI_STATUS) Enable */
-#define QSPI_STATUS_ENABLE          (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
-#define QSPI_STATUS_CSSTATUS_Pos    9            /**< \brief (QSPI_STATUS) Chip Select */
-#define QSPI_STATUS_CSSTATUS        (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
-#define QSPI_STATUS_MASK            _U_(0x00000202) /**< \brief (QSPI_STATUS) MASK Register */
-
-/* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:32;          /*!< bit:  0..31  Instruction Address                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_INSTRADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INSTRADDR_OFFSET       0x30         /**< \brief (QSPI_INSTRADDR offset) Instruction Address */
-#define QSPI_INSTRADDR_RESETVALUE   _U_(0x00000000) /**< \brief (QSPI_INSTRADDR reset_value) Instruction Address */
-
-#define QSPI_INSTRADDR_ADDR_Pos     0            /**< \brief (QSPI_INSTRADDR) Instruction Address */
-#define QSPI_INSTRADDR_ADDR_Msk     (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
-#define QSPI_INSTRADDR_ADDR(value)  (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
-#define QSPI_INSTRADDR_MASK         _U_(0xFFFFFFFF) /**< \brief (QSPI_INSTRADDR) MASK Register */
-
-/* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t INSTR:8;          /*!< bit:  0.. 7  Instruction Code                   */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t OPTCODE:8;        /*!< bit: 16..23  Option Code                        */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_INSTRCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INSTRCTRL_OFFSET       0x34         /**< \brief (QSPI_INSTRCTRL offset) Instruction Code */
-#define QSPI_INSTRCTRL_RESETVALUE   _U_(0x00000000) /**< \brief (QSPI_INSTRCTRL reset_value) Instruction Code */
-
-#define QSPI_INSTRCTRL_INSTR_Pos    0            /**< \brief (QSPI_INSTRCTRL) Instruction Code */
-#define QSPI_INSTRCTRL_INSTR_Msk    (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
-#define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
-#define QSPI_INSTRCTRL_OPTCODE_Pos  16           /**< \brief (QSPI_INSTRCTRL) Option Code */
-#define QSPI_INSTRCTRL_OPTCODE_Msk  (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
-#define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
-#define QSPI_INSTRCTRL_MASK         _U_(0x00FF00FF) /**< \brief (QSPI_INSTRCTRL) MASK Register */
-
-/* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WIDTH:3;          /*!< bit:  0.. 2  Instruction Code, Address, Option Code and Data Width */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t INSTREN:1;        /*!< bit:      4  Instruction Enable                 */
-    uint32_t ADDREN:1;         /*!< bit:      5  Address Enable                     */
-    uint32_t OPTCODEEN:1;      /*!< bit:      6  Option Enable                      */
-    uint32_t DATAEN:1;         /*!< bit:      7  Data Enable                        */
-    uint32_t OPTCODELEN:2;     /*!< bit:  8.. 9  Option Code Length                 */
-    uint32_t ADDRLEN:1;        /*!< bit:     10  Address Length                     */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t TFRTYPE:2;        /*!< bit: 12..13  Data Transfer Type                 */
-    uint32_t CRMODE:1;         /*!< bit:     14  Continuous Read Mode               */
-    uint32_t DDREN:1;          /*!< bit:     15  Double Data Rate Enable            */
-    uint32_t DUMMYLEN:5;       /*!< bit: 16..20  Dummy Cycles Length                */
-    uint32_t :11;              /*!< bit: 21..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_INSTRFRAME_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_INSTRFRAME_OFFSET      0x38         /**< \brief (QSPI_INSTRFRAME offset) Instruction Frame */
-#define QSPI_INSTRFRAME_RESETVALUE  _U_(0x00000000) /**< \brief (QSPI_INSTRFRAME reset_value) Instruction Frame */
-
-#define QSPI_INSTRFRAME_WIDTH_Pos   0            /**< \brief (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width */
-#define QSPI_INSTRFRAME_WIDTH_Msk   (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
-#define   QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
-#define   QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
-#define   QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
-#define   QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
-#define   QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4)   /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
-#define   QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5)   /**< \brief (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
-#define   QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6)   /**< \brief (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
-#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
-#define QSPI_INSTRFRAME_INSTREN_Pos 4            /**< \brief (QSPI_INSTRFRAME) Instruction Enable */
-#define QSPI_INSTRFRAME_INSTREN     (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
-#define QSPI_INSTRFRAME_ADDREN_Pos  5            /**< \brief (QSPI_INSTRFRAME) Address Enable */
-#define QSPI_INSTRFRAME_ADDREN      (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
-#define QSPI_INSTRFRAME_OPTCODEEN_Pos 6            /**< \brief (QSPI_INSTRFRAME) Option Enable */
-#define QSPI_INSTRFRAME_OPTCODEEN   (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
-#define QSPI_INSTRFRAME_DATAEN_Pos  7            /**< \brief (QSPI_INSTRFRAME) Data Enable */
-#define QSPI_INSTRFRAME_DATAEN      (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN_Pos 8            /**< \brief (QSPI_INSTRFRAME) Option Code Length */
-#define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
-#define   QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0)   /**< \brief (QSPI_INSTRFRAME) 1-bit length option code */
-#define   QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1)   /**< \brief (QSPI_INSTRFRAME) 2-bits length option code */
-#define   QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2)   /**< \brief (QSPI_INSTRFRAME) 4-bits length option code */
-#define   QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3)   /**< \brief (QSPI_INSTRFRAME) 8-bits length option code */
-#define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
-#define QSPI_INSTRFRAME_ADDRLEN_Pos 10           /**< \brief (QSPI_INSTRFRAME) Address Length */
-#define QSPI_INSTRFRAME_ADDRLEN     (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
-#define   QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0)   /**< \brief (QSPI_INSTRFRAME) 24-bits address length */
-#define   QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1)   /**< \brief (QSPI_INSTRFRAME) 32-bits address length */
-#define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
-#define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE_Pos 12           /**< \brief (QSPI_INSTRFRAME) Data Transfer Type */
-#define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
-#define   QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0)   /**< \brief (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */
-#define   QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1)   /**< \brief (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */
-#define   QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2)   /**< \brief (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. */
-#define   QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3)   /**< \brief (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. */
-#define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
-#define QSPI_INSTRFRAME_CRMODE_Pos  14           /**< \brief (QSPI_INSTRFRAME) Continuous Read Mode */
-#define QSPI_INSTRFRAME_CRMODE      (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
-#define QSPI_INSTRFRAME_DDREN_Pos   15           /**< \brief (QSPI_INSTRFRAME) Double Data Rate Enable */
-#define QSPI_INSTRFRAME_DDREN       (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
-#define QSPI_INSTRFRAME_DUMMYLEN_Pos 16           /**< \brief (QSPI_INSTRFRAME) Dummy Cycles Length */
-#define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
-#define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
-#define QSPI_INSTRFRAME_MASK        _U_(0x001FF7F7) /**< \brief (QSPI_INSTRFRAME) MASK Register */
-
-/* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ENABLE:1;         /*!< bit:      0  Scrambling/Unscrambling Enable     */
-    uint32_t RANDOMDIS:1;      /*!< bit:      1  Scrambling/Unscrambling Random Value Disable */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_SCRAMBCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_SCRAMBCTRL_OFFSET      0x40         /**< \brief (QSPI_SCRAMBCTRL offset) Scrambling Mode */
-#define QSPI_SCRAMBCTRL_RESETVALUE  _U_(0x00000000) /**< \brief (QSPI_SCRAMBCTRL reset_value) Scrambling Mode */
-
-#define QSPI_SCRAMBCTRL_ENABLE_Pos  0            /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable */
-#define QSPI_SCRAMBCTRL_ENABLE      (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
-#define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1            /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable */
-#define QSPI_SCRAMBCTRL_RANDOMDIS   (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
-#define QSPI_SCRAMBCTRL_MASK        _U_(0x00000003) /**< \brief (QSPI_SCRAMBCTRL) MASK Register */
-
-/* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t KEY:32;           /*!< bit:  0..31  Scrambling User Key                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} QSPI_SCRAMBKEY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define QSPI_SCRAMBKEY_OFFSET       0x44         /**< \brief (QSPI_SCRAMBKEY offset) Scrambling Key */
-#define QSPI_SCRAMBKEY_RESETVALUE   _U_(0x00000000) /**< \brief (QSPI_SCRAMBKEY reset_value) Scrambling Key */
-
-#define QSPI_SCRAMBKEY_KEY_Pos      0            /**< \brief (QSPI_SCRAMBKEY) Scrambling User Key */
-#define QSPI_SCRAMBKEY_KEY_Msk      (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
-#define QSPI_SCRAMBKEY_KEY(value)   (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
-#define QSPI_SCRAMBKEY_MASK         _U_(0xFFFFFFFF) /**< \brief (QSPI_SCRAMBKEY) MASK Register */
-
-/** \brief QSPI APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO QSPI_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO QSPI_CTRLB_Type           CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
-  __IO QSPI_BAUD_Type            BAUD;        /**< \brief Offset: 0x08 (R/W 32) Baud Rate */
-  __I  QSPI_RXDATA_Type          RXDATA;      /**< \brief Offset: 0x0C (R/  32) Receive Data */
-  __O  QSPI_TXDATA_Type          TXDATA;      /**< \brief Offset: 0x10 ( /W 32) Transmit Data */
-  __IO QSPI_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Clear */
-  __IO QSPI_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x18 (R/W 32) Interrupt Enable Set */
-  __IO QSPI_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */
-  __I  QSPI_STATUS_Type          STATUS;      /**< \brief Offset: 0x20 (R/  32) Status Register */
-       RoReg8                    Reserved1[0xC];
-  __IO QSPI_INSTRADDR_Type       INSTRADDR;   /**< \brief Offset: 0x30 (R/W 32) Instruction Address */
-  __IO QSPI_INSTRCTRL_Type       INSTRCTRL;   /**< \brief Offset: 0x34 (R/W 32) Instruction Code */
-  __IO QSPI_INSTRFRAME_Type      INSTRFRAME;  /**< \brief Offset: 0x38 (R/W 32) Instruction Frame */
-       RoReg8                    Reserved2[0x4];
-  __IO QSPI_SCRAMBCTRL_Type      SCRAMBCTRL;  /**< \brief Offset: 0x40 (R/W 32) Scrambling Mode */
-  __O  QSPI_SCRAMBKEY_Type       SCRAMBKEY;   /**< \brief Offset: 0x44 ( /W 32) Scrambling Key */
-} Qspi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_QSPI_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ramecc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ramecc.h
deleted file mode 100644
index c5f044685a..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ramecc.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for RAMECC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_RAMECC_COMPONENT_
-#define _SAMD51_RAMECC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR RAMECC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_RAMECC RAM ECC */
-/*@{*/
-
-#define RAMECC_U2268
-#define REV_RAMECC                  0x100
-
-/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SINGLEE:1;        /*!< bit:      0  Single Bit ECC Error Interrupt Enable Clear */
-    uint8_t  DUALE:1;          /*!< bit:      1  Dual Bit ECC Error Interrupt Enable Clear */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RAMECC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_INTENCLR_OFFSET      0x0          /**< \brief (RAMECC_INTENCLR offset) Interrupt Enable Clear */
-#define RAMECC_INTENCLR_RESETVALUE  _U_(0x00)    /**< \brief (RAMECC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define RAMECC_INTENCLR_SINGLEE_Pos 0            /**< \brief (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear */
-#define RAMECC_INTENCLR_SINGLEE     (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
-#define RAMECC_INTENCLR_DUALE_Pos   1            /**< \brief (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear */
-#define RAMECC_INTENCLR_DUALE       (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
-#define RAMECC_INTENCLR_MASK        _U_(0x03)    /**< \brief (RAMECC_INTENCLR) MASK Register */
-
-/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SINGLEE:1;        /*!< bit:      0  Single Bit ECC Error Interrupt Enable Set */
-    uint8_t  DUALE:1;          /*!< bit:      1  Dual Bit ECC Error Interrupt Enable Set */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RAMECC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_INTENSET_OFFSET      0x1          /**< \brief (RAMECC_INTENSET offset) Interrupt Enable Set */
-#define RAMECC_INTENSET_RESETVALUE  _U_(0x00)    /**< \brief (RAMECC_INTENSET reset_value) Interrupt Enable Set */
-
-#define RAMECC_INTENSET_SINGLEE_Pos 0            /**< \brief (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set */
-#define RAMECC_INTENSET_SINGLEE     (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
-#define RAMECC_INTENSET_DUALE_Pos   1            /**< \brief (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set */
-#define RAMECC_INTENSET_DUALE       (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
-#define RAMECC_INTENSET_MASK        _U_(0x03)    /**< \brief (RAMECC_INTENSET) MASK Register */
-
-/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W  8) Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  SINGLEE:1;        /*!< bit:      0  Single Bit ECC Error Interrupt     */
-    __I uint8_t  DUALE:1;          /*!< bit:      1  Dual Bit ECC Error Interrupt       */
-    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RAMECC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_INTFLAG_OFFSET       0x2          /**< \brief (RAMECC_INTFLAG offset) Interrupt Flag */
-#define RAMECC_INTFLAG_RESETVALUE   _U_(0x00)    /**< \brief (RAMECC_INTFLAG reset_value) Interrupt Flag */
-
-#define RAMECC_INTFLAG_SINGLEE_Pos  0            /**< \brief (RAMECC_INTFLAG) Single Bit ECC Error Interrupt */
-#define RAMECC_INTFLAG_SINGLEE      (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
-#define RAMECC_INTFLAG_DUALE_Pos    1            /**< \brief (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt */
-#define RAMECC_INTFLAG_DUALE        (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
-#define RAMECC_INTFLAG_MASK         _U_(0x03)    /**< \brief (RAMECC_INTFLAG) MASK Register */
-
-/* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/   8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ECCDIS:1;         /*!< bit:      0  ECC Disable                        */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RAMECC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_STATUS_OFFSET        0x3          /**< \brief (RAMECC_STATUS offset) Status */
-#define RAMECC_STATUS_RESETVALUE    _U_(0x00)    /**< \brief (RAMECC_STATUS reset_value) Status */
-
-#define RAMECC_STATUS_ECCDIS_Pos    0            /**< \brief (RAMECC_STATUS) ECC Disable */
-#define RAMECC_STATUS_ECCDIS        (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
-#define RAMECC_STATUS_MASK          _U_(0x01)    /**< \brief (RAMECC_STATUS) MASK Register */
-
-/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/  32) Error Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ERRADDR:17;       /*!< bit:  0..16  Error Address                      */
-    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RAMECC_ERRADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_ERRADDR_OFFSET       0x4          /**< \brief (RAMECC_ERRADDR offset) Error Address */
-#define RAMECC_ERRADDR_RESETVALUE   _U_(0x00000000) /**< \brief (RAMECC_ERRADDR reset_value) Error Address */
-
-#define RAMECC_ERRADDR_ERRADDR_Pos  0            /**< \brief (RAMECC_ERRADDR) Error Address */
-#define RAMECC_ERRADDR_ERRADDR_Msk  (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
-#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
-#define RAMECC_ERRADDR_MASK         _U_(0x0001FFFF) /**< \brief (RAMECC_ERRADDR) MASK Register */
-
-/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ECCDIS:1;         /*!< bit:      0  ECC Disable                        */
-    uint8_t  ECCELOG:1;        /*!< bit:      1  ECC Error Log                      */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RAMECC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RAMECC_DBGCTRL_OFFSET       0xF          /**< \brief (RAMECC_DBGCTRL offset) Debug Control */
-#define RAMECC_DBGCTRL_RESETVALUE   _U_(0x00)    /**< \brief (RAMECC_DBGCTRL reset_value) Debug Control */
-
-#define RAMECC_DBGCTRL_ECCDIS_Pos   0            /**< \brief (RAMECC_DBGCTRL) ECC Disable */
-#define RAMECC_DBGCTRL_ECCDIS       (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
-#define RAMECC_DBGCTRL_ECCELOG_Pos  1            /**< \brief (RAMECC_DBGCTRL) ECC Error Log */
-#define RAMECC_DBGCTRL_ECCELOG      (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
-#define RAMECC_DBGCTRL_MASK         _U_(0x03)    /**< \brief (RAMECC_DBGCTRL) MASK Register */
-
-/** \brief RAMECC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO RAMECC_INTENCLR_Type      INTENCLR;    /**< \brief Offset: 0x0 (R/W  8) Interrupt Enable Clear */
-  __IO RAMECC_INTENSET_Type      INTENSET;    /**< \brief Offset: 0x1 (R/W  8) Interrupt Enable Set */
-  __IO RAMECC_INTFLAG_Type       INTFLAG;     /**< \brief Offset: 0x2 (R/W  8) Interrupt Flag */
-  __I  RAMECC_STATUS_Type        STATUS;      /**< \brief Offset: 0x3 (R/   8) Status */
-  __I  RAMECC_ERRADDR_Type       ERRADDR;     /**< \brief Offset: 0x4 (R/  32) Error Address */
-       RoReg8                    Reserved1[0x7];
-  __IO RAMECC_DBGCTRL_Type       DBGCTRL;     /**< \brief Offset: 0xF (R/W  8) Debug Control */
-} Ramecc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_RAMECC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/rstc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/rstc.h
deleted file mode 100644
index 65f4ed76f1..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/rstc.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for RSTC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_RSTC_COMPONENT_
-#define _SAMD51_RSTC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR RSTC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_RSTC Reset Controller */
-/*@{*/
-
-#define RSTC_U2239
-#define REV_RSTC                    0x400
-
-/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/   8) Reset Cause -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  POR:1;            /*!< bit:      0  Power On Reset                     */
-    uint8_t  BODCORE:1;        /*!< bit:      1  Brown Out CORE Detector Reset      */
-    uint8_t  BODVDD:1;         /*!< bit:      2  Brown Out VDD Detector Reset       */
-    uint8_t  NVM:1;            /*!< bit:      3  NVM Reset                          */
-    uint8_t  EXT:1;            /*!< bit:      4  External Reset                     */
-    uint8_t  WDT:1;            /*!< bit:      5  Watchdog Reset                     */
-    uint8_t  SYST:1;           /*!< bit:      6  System Reset Request               */
-    uint8_t  BACKUP:1;         /*!< bit:      7  Backup Reset                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RSTC_RCAUSE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RSTC_RCAUSE_OFFSET          0x00         /**< \brief (RSTC_RCAUSE offset) Reset Cause */
-
-#define RSTC_RCAUSE_POR_Pos         0            /**< \brief (RSTC_RCAUSE) Power On Reset */
-#define RSTC_RCAUSE_POR             (_U_(0x1) << RSTC_RCAUSE_POR_Pos)
-#define RSTC_RCAUSE_BODCORE_Pos     1            /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */
-#define RSTC_RCAUSE_BODCORE         (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos)
-#define RSTC_RCAUSE_BODVDD_Pos      2            /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */
-#define RSTC_RCAUSE_BODVDD          (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos)
-#define RSTC_RCAUSE_NVM_Pos         3            /**< \brief (RSTC_RCAUSE) NVM Reset */
-#define RSTC_RCAUSE_NVM             (_U_(0x1) << RSTC_RCAUSE_NVM_Pos)
-#define RSTC_RCAUSE_EXT_Pos         4            /**< \brief (RSTC_RCAUSE) External Reset */
-#define RSTC_RCAUSE_EXT             (_U_(0x1) << RSTC_RCAUSE_EXT_Pos)
-#define RSTC_RCAUSE_WDT_Pos         5            /**< \brief (RSTC_RCAUSE) Watchdog Reset */
-#define RSTC_RCAUSE_WDT             (_U_(0x1) << RSTC_RCAUSE_WDT_Pos)
-#define RSTC_RCAUSE_SYST_Pos        6            /**< \brief (RSTC_RCAUSE) System Reset Request */
-#define RSTC_RCAUSE_SYST            (_U_(0x1) << RSTC_RCAUSE_SYST_Pos)
-#define RSTC_RCAUSE_BACKUP_Pos      7            /**< \brief (RSTC_RCAUSE) Backup Reset */
-#define RSTC_RCAUSE_BACKUP          (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos)
-#define RSTC_RCAUSE_MASK            _U_(0xFF)    /**< \brief (RSTC_RCAUSE) MASK Register */
-
-/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/   8) Backup Exit Source -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  RTC:1;            /*!< bit:      1  Real Timer Counter Interrupt       */
-    uint8_t  BBPS:1;           /*!< bit:      2  Battery Backup Power Switch        */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  HIB:1;            /*!< bit:      7  Hibernate                          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RSTC_BKUPEXIT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RSTC_BKUPEXIT_OFFSET        0x02         /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */
-#define RSTC_BKUPEXIT_RESETVALUE    _U_(0x00)    /**< \brief (RSTC_BKUPEXIT reset_value) Backup Exit Source */
-
-#define RSTC_BKUPEXIT_RTC_Pos       1            /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */
-#define RSTC_BKUPEXIT_RTC           (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos)
-#define RSTC_BKUPEXIT_BBPS_Pos      2            /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */
-#define RSTC_BKUPEXIT_BBPS          (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos)
-#define RSTC_BKUPEXIT_HIB_Pos       7            /**< \brief (RSTC_BKUPEXIT) Hibernate */
-#define RSTC_BKUPEXIT_HIB           (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos)
-#define RSTC_BKUPEXIT_MASK          _U_(0x86)    /**< \brief (RSTC_BKUPEXIT) MASK Register */
-
-/** \brief RSTC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __I  RSTC_RCAUSE_Type          RCAUSE;      /**< \brief Offset: 0x00 (R/   8) Reset Cause */
-       RoReg8                    Reserved1[0x1];
-  __I  RSTC_BKUPEXIT_Type        BKUPEXIT;    /**< \brief Offset: 0x02 (R/   8) Backup Exit Source */
-} Rstc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_RSTC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/rtc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/rtc.h
deleted file mode 100644
index aafac662bc..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/rtc.h
+++ /dev/null
@@ -1,2098 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for RTC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_RTC_COMPONENT_
-#define _SAMD51_RTC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR RTC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_RTC Real-Time Counter */
-/*@{*/
-
-#define RTC_U2250
-#define REV_RTC                     0x210
-
-/* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
-    uint16_t :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
-    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
-    uint16_t :1;               /*!< bit:     12  Reserved                           */
-    uint16_t BKTRST:1;         /*!< bit:     13  BKUP Registers Reset On Tamper Enable */
-    uint16_t GPTRST:1;         /*!< bit:     14  GP Registers Reset On Tamper Enable */
-    uint16_t COUNTSYNC:1;      /*!< bit:     15  Count Read Synchronization Enable  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_CTRLA_OFFSET      0x00         /**< \brief (RTC_MODE0_CTRLA offset) MODE0 Control A */
-#define RTC_MODE0_CTRLA_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Control A */
-
-#define RTC_MODE0_CTRLA_SWRST_Pos   0            /**< \brief (RTC_MODE0_CTRLA) Software Reset */
-#define RTC_MODE0_CTRLA_SWRST       (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)
-#define RTC_MODE0_CTRLA_ENABLE_Pos  1            /**< \brief (RTC_MODE0_CTRLA) Enable */
-#define RTC_MODE0_CTRLA_ENABLE      (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)
-#define RTC_MODE0_CTRLA_MODE_Pos    2            /**< \brief (RTC_MODE0_CTRLA) Operating Mode */
-#define RTC_MODE0_CTRLA_MODE_Msk    (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)
-#define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))
-#define   RTC_MODE0_CTRLA_MODE_COUNT32_Val _U_(0x0)   /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */
-#define   RTC_MODE0_CTRLA_MODE_COUNT16_Val _U_(0x1)   /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */
-#define   RTC_MODE0_CTRLA_MODE_CLOCK_Val  _U_(0x2)   /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */
-#define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos)
-#define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos)
-#define RTC_MODE0_CTRLA_MODE_CLOCK  (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos)
-#define RTC_MODE0_CTRLA_MATCHCLR_Pos 7            /**< \brief (RTC_MODE0_CTRLA) Clear on Match */
-#define RTC_MODE0_CTRLA_MATCHCLR    (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_Pos 8            /**< \brief (RTC_MODE0_CTRLA) Prescaler */
-#define RTC_MODE0_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))
-#define   RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U_(0x1)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U_(0x2)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U_(0x3)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U_(0x4)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U_(0x5)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U_(0x6)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U_(0x7)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U_(0x8)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U_(0x9)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U_(0xA)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
-#define   RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)   /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
-#define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)
-#define RTC_MODE0_CTRLA_BKTRST_Pos  13           /**< \brief (RTC_MODE0_CTRLA) BKUP Registers Reset On Tamper Enable */
-#define RTC_MODE0_CTRLA_BKTRST      (_U_(0x1) << RTC_MODE0_CTRLA_BKTRST_Pos)
-#define RTC_MODE0_CTRLA_GPTRST_Pos  14           /**< \brief (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable */
-#define RTC_MODE0_CTRLA_GPTRST      (_U_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)
-#define RTC_MODE0_CTRLA_COUNTSYNC_Pos 15           /**< \brief (RTC_MODE0_CTRLA) Count Read Synchronization Enable */
-#define RTC_MODE0_CTRLA_COUNTSYNC   (_U_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
-#define RTC_MODE0_CTRLA_MASK        _U_(0xEF8F)  /**< \brief (RTC_MODE0_CTRLA) MASK Register */
-
-/* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
-    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
-    uint16_t :1;               /*!< bit:     12  Reserved                           */
-    uint16_t BKTRST:1;         /*!< bit:     13  BKUP Registers Reset On Tamper Enable */
-    uint16_t GPTRST:1;         /*!< bit:     14  GP Registers Reset On Tamper Enable */
-    uint16_t COUNTSYNC:1;      /*!< bit:     15  Count Read Synchronization Enable  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_CTRLA_OFFSET      0x00         /**< \brief (RTC_MODE1_CTRLA offset) MODE1 Control A */
-#define RTC_MODE1_CTRLA_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE1_CTRLA reset_value) MODE1 Control A */
-
-#define RTC_MODE1_CTRLA_SWRST_Pos   0            /**< \brief (RTC_MODE1_CTRLA) Software Reset */
-#define RTC_MODE1_CTRLA_SWRST       (_U_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)
-#define RTC_MODE1_CTRLA_ENABLE_Pos  1            /**< \brief (RTC_MODE1_CTRLA) Enable */
-#define RTC_MODE1_CTRLA_ENABLE      (_U_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)
-#define RTC_MODE1_CTRLA_MODE_Pos    2            /**< \brief (RTC_MODE1_CTRLA) Operating Mode */
-#define RTC_MODE1_CTRLA_MODE_Msk    (_U_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)
-#define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))
-#define   RTC_MODE1_CTRLA_MODE_COUNT32_Val _U_(0x0)   /**< \brief (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */
-#define   RTC_MODE1_CTRLA_MODE_COUNT16_Val _U_(0x1)   /**< \brief (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */
-#define   RTC_MODE1_CTRLA_MODE_CLOCK_Val  _U_(0x2)   /**< \brief (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */
-#define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos)
-#define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos)
-#define RTC_MODE1_CTRLA_MODE_CLOCK  (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_Pos 8            /**< \brief (RTC_MODE1_CTRLA) Prescaler */
-#define RTC_MODE1_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))
-#define   RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U_(0x0)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U_(0x1)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U_(0x2)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U_(0x3)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U_(0x4)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U_(0x5)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U_(0x6)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U_(0x7)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U_(0x8)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U_(0x9)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U_(0xA)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
-#define   RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)   /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
-#define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)
-#define RTC_MODE1_CTRLA_BKTRST_Pos  13           /**< \brief (RTC_MODE1_CTRLA) BKUP Registers Reset On Tamper Enable */
-#define RTC_MODE1_CTRLA_BKTRST      (_U_(0x1) << RTC_MODE1_CTRLA_BKTRST_Pos)
-#define RTC_MODE1_CTRLA_GPTRST_Pos  14           /**< \brief (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable */
-#define RTC_MODE1_CTRLA_GPTRST      (_U_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)
-#define RTC_MODE1_CTRLA_COUNTSYNC_Pos 15           /**< \brief (RTC_MODE1_CTRLA) Count Read Synchronization Enable */
-#define RTC_MODE1_CTRLA_COUNTSYNC   (_U_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)
-#define RTC_MODE1_CTRLA_MASK        _U_(0xEF0F)  /**< \brief (RTC_MODE1_CTRLA) MASK Register */
-
-/* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint16_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint16_t MODE:2;           /*!< bit:  2.. 3  Operating Mode                     */
-    uint16_t :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint16_t CLKREP:1;         /*!< bit:      6  Clock Representation               */
-    uint16_t MATCHCLR:1;       /*!< bit:      7  Clear on Match                     */
-    uint16_t PRESCALER:4;      /*!< bit:  8..11  Prescaler                          */
-    uint16_t :1;               /*!< bit:     12  Reserved                           */
-    uint16_t BKTRST:1;         /*!< bit:     13  BKUP Registers Reset On Tamper Enable */
-    uint16_t GPTRST:1;         /*!< bit:     14  GP Registers Reset On Tamper Enable */
-    uint16_t CLOCKSYNC:1;      /*!< bit:     15  Clock Read Synchronization Enable  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_CTRLA_OFFSET      0x00         /**< \brief (RTC_MODE2_CTRLA offset) MODE2 Control A */
-#define RTC_MODE2_CTRLA_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE2_CTRLA reset_value) MODE2 Control A */
-
-#define RTC_MODE2_CTRLA_SWRST_Pos   0            /**< \brief (RTC_MODE2_CTRLA) Software Reset */
-#define RTC_MODE2_CTRLA_SWRST       (_U_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)
-#define RTC_MODE2_CTRLA_ENABLE_Pos  1            /**< \brief (RTC_MODE2_CTRLA) Enable */
-#define RTC_MODE2_CTRLA_ENABLE      (_U_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)
-#define RTC_MODE2_CTRLA_MODE_Pos    2            /**< \brief (RTC_MODE2_CTRLA) Operating Mode */
-#define RTC_MODE2_CTRLA_MODE_Msk    (_U_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)
-#define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))
-#define   RTC_MODE2_CTRLA_MODE_COUNT32_Val _U_(0x0)   /**< \brief (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */
-#define   RTC_MODE2_CTRLA_MODE_COUNT16_Val _U_(0x1)   /**< \brief (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */
-#define   RTC_MODE2_CTRLA_MODE_CLOCK_Val  _U_(0x2)   /**< \brief (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */
-#define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos)
-#define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos)
-#define RTC_MODE2_CTRLA_MODE_CLOCK  (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos)
-#define RTC_MODE2_CTRLA_CLKREP_Pos  6            /**< \brief (RTC_MODE2_CTRLA) Clock Representation */
-#define RTC_MODE2_CTRLA_CLKREP      (_U_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)
-#define RTC_MODE2_CTRLA_MATCHCLR_Pos 7            /**< \brief (RTC_MODE2_CTRLA) Clear on Match */
-#define RTC_MODE2_CTRLA_MATCHCLR    (_U_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_Pos 8            /**< \brief (RTC_MODE2_CTRLA) Prescaler */
-#define RTC_MODE2_CTRLA_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))
-#define   RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U_(0x0)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U_(0x1)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U_(0x2)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U_(0x3)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U_(0x4)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U_(0x5)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U_(0x6)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U_(0x7)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U_(0x8)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U_(0x9)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U_(0xA)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */
-#define   RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)   /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */
-#define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)
-#define RTC_MODE2_CTRLA_BKTRST_Pos  13           /**< \brief (RTC_MODE2_CTRLA) BKUP Registers Reset On Tamper Enable */
-#define RTC_MODE2_CTRLA_BKTRST      (_U_(0x1) << RTC_MODE2_CTRLA_BKTRST_Pos)
-#define RTC_MODE2_CTRLA_GPTRST_Pos  14           /**< \brief (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable */
-#define RTC_MODE2_CTRLA_GPTRST      (_U_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)
-#define RTC_MODE2_CTRLA_CLOCKSYNC_Pos 15           /**< \brief (RTC_MODE2_CTRLA) Clock Read Synchronization Enable */
-#define RTC_MODE2_CTRLA_CLOCKSYNC   (_U_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)
-#define RTC_MODE2_CTRLA_MASK        _U_(0xEFCF)  /**< \brief (RTC_MODE2_CTRLA) MASK Register */
-
-/* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 MODE0 Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t GP0EN:1;          /*!< bit:      0  General Purpose 0 Enable           */
-    uint16_t GP2EN:1;          /*!< bit:      1  General Purpose 2 Enable           */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t DEBMAJ:1;         /*!< bit:      4  Debouncer Majority Enable          */
-    uint16_t DEBASYNC:1;       /*!< bit:      5  Debouncer Asynchronous Enable      */
-    uint16_t RTCOUT:1;         /*!< bit:      6  RTC Output Enable                  */
-    uint16_t DMAEN:1;          /*!< bit:      7  DMA Enable                         */
-    uint16_t DEBF:3;           /*!< bit:  8..10  Debounce Freqnuency                */
-    uint16_t :1;               /*!< bit:     11  Reserved                           */
-    uint16_t ACTF:3;           /*!< bit: 12..14  Active Layer Freqnuency            */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_CTRLB_OFFSET      0x02         /**< \brief (RTC_MODE0_CTRLB offset) MODE0 Control B */
-#define RTC_MODE0_CTRLB_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE0_CTRLB reset_value) MODE0 Control B */
-
-#define RTC_MODE0_CTRLB_GP0EN_Pos   0            /**< \brief (RTC_MODE0_CTRLB) General Purpose 0 Enable */
-#define RTC_MODE0_CTRLB_GP0EN       (_U_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)
-#define RTC_MODE0_CTRLB_GP2EN_Pos   1            /**< \brief (RTC_MODE0_CTRLB) General Purpose 2 Enable */
-#define RTC_MODE0_CTRLB_GP2EN       (_U_(0x1) << RTC_MODE0_CTRLB_GP2EN_Pos)
-#define RTC_MODE0_CTRLB_DEBMAJ_Pos  4            /**< \brief (RTC_MODE0_CTRLB) Debouncer Majority Enable */
-#define RTC_MODE0_CTRLB_DEBMAJ      (_U_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)
-#define RTC_MODE0_CTRLB_DEBASYNC_Pos 5            /**< \brief (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable */
-#define RTC_MODE0_CTRLB_DEBASYNC    (_U_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)
-#define RTC_MODE0_CTRLB_RTCOUT_Pos  6            /**< \brief (RTC_MODE0_CTRLB) RTC Output Enable */
-#define RTC_MODE0_CTRLB_RTCOUT      (_U_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)
-#define RTC_MODE0_CTRLB_DMAEN_Pos   7            /**< \brief (RTC_MODE0_CTRLB) DMA Enable */
-#define RTC_MODE0_CTRLB_DMAEN       (_U_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)
-#define RTC_MODE0_CTRLB_DEBF_Pos    8            /**< \brief (RTC_MODE0_CTRLB) Debounce Freqnuency */
-#define RTC_MODE0_CTRLB_DEBF_Msk    (_U_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF(value) (RTC_MODE0_CTRLB_DEBF_Msk & ((value) << RTC_MODE0_CTRLB_DEBF_Pos))
-#define   RTC_MODE0_CTRLB_DEBF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
-#define   RTC_MODE0_CTRLB_DEBF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
-#define   RTC_MODE0_CTRLB_DEBF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
-#define   RTC_MODE0_CTRLB_DEBF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
-#define   RTC_MODE0_CTRLB_DEBF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
-#define   RTC_MODE0_CTRLB_DEBF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
-#define   RTC_MODE0_CTRLB_DEBF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
-#define   RTC_MODE0_CTRLB_DEBF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
-#define RTC_MODE0_CTRLB_DEBF_DIV2   (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV4   (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV8   (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV16  (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV32  (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV64  (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV128 (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_DEBF_DIV256 (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_Pos    12           /**< \brief (RTC_MODE0_CTRLB) Active Layer Freqnuency */
-#define RTC_MODE0_CTRLB_ACTF_Msk    (_U_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF(value) (RTC_MODE0_CTRLB_ACTF_Msk & ((value) << RTC_MODE0_CTRLB_ACTF_Pos))
-#define   RTC_MODE0_CTRLB_ACTF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
-#define   RTC_MODE0_CTRLB_ACTF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
-#define   RTC_MODE0_CTRLB_ACTF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
-#define   RTC_MODE0_CTRLB_ACTF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
-#define   RTC_MODE0_CTRLB_ACTF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
-#define   RTC_MODE0_CTRLB_ACTF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
-#define   RTC_MODE0_CTRLB_ACTF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
-#define   RTC_MODE0_CTRLB_ACTF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
-#define RTC_MODE0_CTRLB_ACTF_DIV2   (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV4   (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV8   (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV16  (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV32  (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV64  (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV128 (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_ACTF_DIV256 (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos)
-#define RTC_MODE0_CTRLB_MASK        _U_(0x77F3)  /**< \brief (RTC_MODE0_CTRLB) MASK Register */
-
-/* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 MODE1 Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t GP0EN:1;          /*!< bit:      0  General Purpose 0 Enable           */
-    uint16_t GP2EN:1;          /*!< bit:      1  General Purpose 2 Enable           */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t DEBMAJ:1;         /*!< bit:      4  Debouncer Majority Enable          */
-    uint16_t DEBASYNC:1;       /*!< bit:      5  Debouncer Asynchronous Enable      */
-    uint16_t RTCOUT:1;         /*!< bit:      6  RTC Output Enable                  */
-    uint16_t DMAEN:1;          /*!< bit:      7  DMA Enable                         */
-    uint16_t DEBF:3;           /*!< bit:  8..10  Debounce Freqnuency                */
-    uint16_t :1;               /*!< bit:     11  Reserved                           */
-    uint16_t ACTF:3;           /*!< bit: 12..14  Active Layer Freqnuency            */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_CTRLB_OFFSET      0x02         /**< \brief (RTC_MODE1_CTRLB offset) MODE1 Control B */
-#define RTC_MODE1_CTRLB_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE1_CTRLB reset_value) MODE1 Control B */
-
-#define RTC_MODE1_CTRLB_GP0EN_Pos   0            /**< \brief (RTC_MODE1_CTRLB) General Purpose 0 Enable */
-#define RTC_MODE1_CTRLB_GP0EN       (_U_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)
-#define RTC_MODE1_CTRLB_GP2EN_Pos   1            /**< \brief (RTC_MODE1_CTRLB) General Purpose 2 Enable */
-#define RTC_MODE1_CTRLB_GP2EN       (_U_(0x1) << RTC_MODE1_CTRLB_GP2EN_Pos)
-#define RTC_MODE1_CTRLB_DEBMAJ_Pos  4            /**< \brief (RTC_MODE1_CTRLB) Debouncer Majority Enable */
-#define RTC_MODE1_CTRLB_DEBMAJ      (_U_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)
-#define RTC_MODE1_CTRLB_DEBASYNC_Pos 5            /**< \brief (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable */
-#define RTC_MODE1_CTRLB_DEBASYNC    (_U_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)
-#define RTC_MODE1_CTRLB_RTCOUT_Pos  6            /**< \brief (RTC_MODE1_CTRLB) RTC Output Enable */
-#define RTC_MODE1_CTRLB_RTCOUT      (_U_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)
-#define RTC_MODE1_CTRLB_DMAEN_Pos   7            /**< \brief (RTC_MODE1_CTRLB) DMA Enable */
-#define RTC_MODE1_CTRLB_DMAEN       (_U_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)
-#define RTC_MODE1_CTRLB_DEBF_Pos    8            /**< \brief (RTC_MODE1_CTRLB) Debounce Freqnuency */
-#define RTC_MODE1_CTRLB_DEBF_Msk    (_U_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF(value) (RTC_MODE1_CTRLB_DEBF_Msk & ((value) << RTC_MODE1_CTRLB_DEBF_Pos))
-#define   RTC_MODE1_CTRLB_DEBF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
-#define   RTC_MODE1_CTRLB_DEBF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
-#define   RTC_MODE1_CTRLB_DEBF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
-#define   RTC_MODE1_CTRLB_DEBF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
-#define   RTC_MODE1_CTRLB_DEBF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
-#define   RTC_MODE1_CTRLB_DEBF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
-#define   RTC_MODE1_CTRLB_DEBF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
-#define   RTC_MODE1_CTRLB_DEBF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
-#define RTC_MODE1_CTRLB_DEBF_DIV2   (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV4   (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV8   (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV16  (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV32  (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV64  (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV128 (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_DEBF_DIV256 (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_Pos    12           /**< \brief (RTC_MODE1_CTRLB) Active Layer Freqnuency */
-#define RTC_MODE1_CTRLB_ACTF_Msk    (_U_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF(value) (RTC_MODE1_CTRLB_ACTF_Msk & ((value) << RTC_MODE1_CTRLB_ACTF_Pos))
-#define   RTC_MODE1_CTRLB_ACTF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
-#define   RTC_MODE1_CTRLB_ACTF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
-#define   RTC_MODE1_CTRLB_ACTF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
-#define   RTC_MODE1_CTRLB_ACTF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
-#define   RTC_MODE1_CTRLB_ACTF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
-#define   RTC_MODE1_CTRLB_ACTF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
-#define   RTC_MODE1_CTRLB_ACTF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
-#define   RTC_MODE1_CTRLB_ACTF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
-#define RTC_MODE1_CTRLB_ACTF_DIV2   (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV4   (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV8   (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV16  (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV32  (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV64  (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV128 (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_ACTF_DIV256 (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos)
-#define RTC_MODE1_CTRLB_MASK        _U_(0x77F3)  /**< \brief (RTC_MODE1_CTRLB) MASK Register */
-
-/* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 MODE2 Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t GP0EN:1;          /*!< bit:      0  General Purpose 0 Enable           */
-    uint16_t GP2EN:1;          /*!< bit:      1  General Purpose 2 Enable           */
-    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint16_t DEBMAJ:1;         /*!< bit:      4  Debouncer Majority Enable          */
-    uint16_t DEBASYNC:1;       /*!< bit:      5  Debouncer Asynchronous Enable      */
-    uint16_t RTCOUT:1;         /*!< bit:      6  RTC Output Enable                  */
-    uint16_t DMAEN:1;          /*!< bit:      7  DMA Enable                         */
-    uint16_t DEBF:3;           /*!< bit:  8..10  Debounce Freqnuency                */
-    uint16_t :1;               /*!< bit:     11  Reserved                           */
-    uint16_t ACTF:3;           /*!< bit: 12..14  Active Layer Freqnuency            */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_CTRLB_OFFSET      0x02         /**< \brief (RTC_MODE2_CTRLB offset) MODE2 Control B */
-#define RTC_MODE2_CTRLB_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE2_CTRLB reset_value) MODE2 Control B */
-
-#define RTC_MODE2_CTRLB_GP0EN_Pos   0            /**< \brief (RTC_MODE2_CTRLB) General Purpose 0 Enable */
-#define RTC_MODE2_CTRLB_GP0EN       (_U_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)
-#define RTC_MODE2_CTRLB_GP2EN_Pos   1            /**< \brief (RTC_MODE2_CTRLB) General Purpose 2 Enable */
-#define RTC_MODE2_CTRLB_GP2EN       (_U_(0x1) << RTC_MODE2_CTRLB_GP2EN_Pos)
-#define RTC_MODE2_CTRLB_DEBMAJ_Pos  4            /**< \brief (RTC_MODE2_CTRLB) Debouncer Majority Enable */
-#define RTC_MODE2_CTRLB_DEBMAJ      (_U_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)
-#define RTC_MODE2_CTRLB_DEBASYNC_Pos 5            /**< \brief (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable */
-#define RTC_MODE2_CTRLB_DEBASYNC    (_U_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)
-#define RTC_MODE2_CTRLB_RTCOUT_Pos  6            /**< \brief (RTC_MODE2_CTRLB) RTC Output Enable */
-#define RTC_MODE2_CTRLB_RTCOUT      (_U_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)
-#define RTC_MODE2_CTRLB_DMAEN_Pos   7            /**< \brief (RTC_MODE2_CTRLB) DMA Enable */
-#define RTC_MODE2_CTRLB_DMAEN       (_U_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)
-#define RTC_MODE2_CTRLB_DEBF_Pos    8            /**< \brief (RTC_MODE2_CTRLB) Debounce Freqnuency */
-#define RTC_MODE2_CTRLB_DEBF_Msk    (_U_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF(value) (RTC_MODE2_CTRLB_DEBF_Msk & ((value) << RTC_MODE2_CTRLB_DEBF_Pos))
-#define   RTC_MODE2_CTRLB_DEBF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 */
-#define   RTC_MODE2_CTRLB_DEBF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 */
-#define   RTC_MODE2_CTRLB_DEBF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 */
-#define   RTC_MODE2_CTRLB_DEBF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 */
-#define   RTC_MODE2_CTRLB_DEBF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 */
-#define   RTC_MODE2_CTRLB_DEBF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 */
-#define   RTC_MODE2_CTRLB_DEBF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 */
-#define   RTC_MODE2_CTRLB_DEBF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 */
-#define RTC_MODE2_CTRLB_DEBF_DIV2   (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV4   (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV8   (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV16  (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV32  (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV64  (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV128 (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_DEBF_DIV256 (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_Pos    12           /**< \brief (RTC_MODE2_CTRLB) Active Layer Freqnuency */
-#define RTC_MODE2_CTRLB_ACTF_Msk    (_U_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF(value) (RTC_MODE2_CTRLB_ACTF_Msk & ((value) << RTC_MODE2_CTRLB_ACTF_Pos))
-#define   RTC_MODE2_CTRLB_ACTF_DIV2_Val   _U_(0x0)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 */
-#define   RTC_MODE2_CTRLB_ACTF_DIV4_Val   _U_(0x1)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 */
-#define   RTC_MODE2_CTRLB_ACTF_DIV8_Val   _U_(0x2)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 */
-#define   RTC_MODE2_CTRLB_ACTF_DIV16_Val  _U_(0x3)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 */
-#define   RTC_MODE2_CTRLB_ACTF_DIV32_Val  _U_(0x4)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 */
-#define   RTC_MODE2_CTRLB_ACTF_DIV64_Val  _U_(0x5)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 */
-#define   RTC_MODE2_CTRLB_ACTF_DIV128_Val _U_(0x6)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 */
-#define   RTC_MODE2_CTRLB_ACTF_DIV256_Val _U_(0x7)   /**< \brief (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 */
-#define RTC_MODE2_CTRLB_ACTF_DIV2   (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV4   (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV8   (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV16  (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV32  (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV64  (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV128 (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_ACTF_DIV256 (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos)
-#define RTC_MODE2_CTRLB_MASK        _U_(0x77F3)  /**< \brief (RTC_MODE2_CTRLB) MASK Register */
-
-/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
-    uint32_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
-    uint32_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
-    uint32_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
-    uint32_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
-    uint32_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
-    uint32_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
-    uint32_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
-    uint32_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
-    uint32_t CMPEO1:1;         /*!< bit:      9  Compare 1 Event Output Enable      */
-    uint32_t :4;               /*!< bit: 10..13  Reserved                           */
-    uint32_t TAMPEREO:1;       /*!< bit:     14  Tamper Event Output Enable         */
-    uint32_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
-    uint32_t TAMPEVEI:1;       /*!< bit:     16  Tamper Event Input Enable          */
-    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
-    uint32_t CMPEO:2;          /*!< bit:  8.. 9  Compare x Event Output Enable      */
-    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
-#define RTC_MODE0_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
-
-#define RTC_MODE0_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO0     (_U_(1) << RTC_MODE0_EVCTRL_PEREO0_Pos)
-#define RTC_MODE0_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO1     (_U_(1) << RTC_MODE0_EVCTRL_PEREO1_Pos)
-#define RTC_MODE0_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO2     (_U_(1) << RTC_MODE0_EVCTRL_PEREO2_Pos)
-#define RTC_MODE0_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO3     (_U_(1) << RTC_MODE0_EVCTRL_PEREO3_Pos)
-#define RTC_MODE0_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO4     (_U_(1) << RTC_MODE0_EVCTRL_PEREO4_Pos)
-#define RTC_MODE0_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO5     (_U_(1) << RTC_MODE0_EVCTRL_PEREO5_Pos)
-#define RTC_MODE0_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO6     (_U_(1) << RTC_MODE0_EVCTRL_PEREO6_Pos)
-#define RTC_MODE0_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO7     (_U_(1) << RTC_MODE0_EVCTRL_PEREO7_Pos)
-#define RTC_MODE0_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
-#define RTC_MODE0_EVCTRL_PEREO_Msk  (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)
-#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
-#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
-#define RTC_MODE0_EVCTRL_CMPEO0     (_U_(1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)
-#define RTC_MODE0_EVCTRL_CMPEO1_Pos 9            /**< \brief (RTC_MODE0_EVCTRL) Compare 1 Event Output Enable */
-#define RTC_MODE0_EVCTRL_CMPEO1     (_U_(1) << RTC_MODE0_EVCTRL_CMPEO1_Pos)
-#define RTC_MODE0_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
-#define RTC_MODE0_EVCTRL_CMPEO_Msk  (_U_(0x3) << RTC_MODE0_EVCTRL_CMPEO_Pos)
-#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
-#define RTC_MODE0_EVCTRL_TAMPEREO_Pos 14           /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Output Enable */
-#define RTC_MODE0_EVCTRL_TAMPEREO   (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
-#define RTC_MODE0_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
-#define RTC_MODE0_EVCTRL_OVFEO      (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)
-#define RTC_MODE0_EVCTRL_TAMPEVEI_Pos 16           /**< \brief (RTC_MODE0_EVCTRL) Tamper Event Input Enable */
-#define RTC_MODE0_EVCTRL_TAMPEVEI   (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)
-#define RTC_MODE0_EVCTRL_MASK       _U_(0x0001C3FF) /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
-
-/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
-    uint32_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
-    uint32_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
-    uint32_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
-    uint32_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
-    uint32_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
-    uint32_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
-    uint32_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
-    uint32_t CMPEO0:1;         /*!< bit:      8  Compare 0 Event Output Enable      */
-    uint32_t CMPEO1:1;         /*!< bit:      9  Compare 1 Event Output Enable      */
-    uint32_t CMPEO2:1;         /*!< bit:     10  Compare 2 Event Output Enable      */
-    uint32_t CMPEO3:1;         /*!< bit:     11  Compare 3 Event Output Enable      */
-    uint32_t :2;               /*!< bit: 12..13  Reserved                           */
-    uint32_t TAMPEREO:1;       /*!< bit:     14  Tamper Event Output Enable         */
-    uint32_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
-    uint32_t TAMPEVEI:1;       /*!< bit:     16  Tamper Event Input Enable          */
-    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
-    uint32_t CMPEO:4;          /*!< bit:  8..11  Compare x Event Output Enable      */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
-#define RTC_MODE1_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
-
-#define RTC_MODE1_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO0     (_U_(1) << RTC_MODE1_EVCTRL_PEREO0_Pos)
-#define RTC_MODE1_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO1     (_U_(1) << RTC_MODE1_EVCTRL_PEREO1_Pos)
-#define RTC_MODE1_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO2     (_U_(1) << RTC_MODE1_EVCTRL_PEREO2_Pos)
-#define RTC_MODE1_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO3     (_U_(1) << RTC_MODE1_EVCTRL_PEREO3_Pos)
-#define RTC_MODE1_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO4     (_U_(1) << RTC_MODE1_EVCTRL_PEREO4_Pos)
-#define RTC_MODE1_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO5     (_U_(1) << RTC_MODE1_EVCTRL_PEREO5_Pos)
-#define RTC_MODE1_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO6     (_U_(1) << RTC_MODE1_EVCTRL_PEREO6_Pos)
-#define RTC_MODE1_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO7     (_U_(1) << RTC_MODE1_EVCTRL_PEREO7_Pos)
-#define RTC_MODE1_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
-#define RTC_MODE1_EVCTRL_PEREO_Msk  (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)
-#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
-#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8            /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO0     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9            /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO1     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO2_Pos 10           /**< \brief (RTC_MODE1_EVCTRL) Compare 2 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO2     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO2_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO3_Pos 11           /**< \brief (RTC_MODE1_EVCTRL) Compare 3 Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO3     (_U_(1) << RTC_MODE1_EVCTRL_CMPEO3_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO_Pos  8            /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
-#define RTC_MODE1_EVCTRL_CMPEO_Msk  (_U_(0xF) << RTC_MODE1_EVCTRL_CMPEO_Pos)
-#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
-#define RTC_MODE1_EVCTRL_TAMPEREO_Pos 14           /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Output Enable */
-#define RTC_MODE1_EVCTRL_TAMPEREO   (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)
-#define RTC_MODE1_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
-#define RTC_MODE1_EVCTRL_OVFEO      (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)
-#define RTC_MODE1_EVCTRL_TAMPEVEI_Pos 16           /**< \brief (RTC_MODE1_EVCTRL) Tamper Event Input Enable */
-#define RTC_MODE1_EVCTRL_TAMPEVEI   (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)
-#define RTC_MODE1_EVCTRL_MASK       _U_(0x0001CFFF) /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
-
-/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PEREO0:1;         /*!< bit:      0  Periodic Interval 0 Event Output Enable */
-    uint32_t PEREO1:1;         /*!< bit:      1  Periodic Interval 1 Event Output Enable */
-    uint32_t PEREO2:1;         /*!< bit:      2  Periodic Interval 2 Event Output Enable */
-    uint32_t PEREO3:1;         /*!< bit:      3  Periodic Interval 3 Event Output Enable */
-    uint32_t PEREO4:1;         /*!< bit:      4  Periodic Interval 4 Event Output Enable */
-    uint32_t PEREO5:1;         /*!< bit:      5  Periodic Interval 5 Event Output Enable */
-    uint32_t PEREO6:1;         /*!< bit:      6  Periodic Interval 6 Event Output Enable */
-    uint32_t PEREO7:1;         /*!< bit:      7  Periodic Interval 7 Event Output Enable */
-    uint32_t ALARMEO0:1;       /*!< bit:      8  Alarm 0 Event Output Enable        */
-    uint32_t ALARMEO1:1;       /*!< bit:      9  Alarm 1 Event Output Enable        */
-    uint32_t :4;               /*!< bit: 10..13  Reserved                           */
-    uint32_t TAMPEREO:1;       /*!< bit:     14  Tamper Event Output Enable         */
-    uint32_t OVFEO:1;          /*!< bit:     15  Overflow Event Output Enable       */
-    uint32_t TAMPEVEI:1;       /*!< bit:     16  Tamper Event Input Enable          */
-    uint32_t :15;              /*!< bit: 17..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t PEREO:8;          /*!< bit:  0.. 7  Periodic Interval x Event Output Enable */
-    uint32_t ALARMEO:2;        /*!< bit:  8.. 9  Alarm x Event Output Enable        */
-    uint32_t :22;              /*!< bit: 10..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_EVCTRL_OFFSET     0x04         /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
-#define RTC_MODE2_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
-
-#define RTC_MODE2_EVCTRL_PEREO0_Pos 0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO0     (_U_(1) << RTC_MODE2_EVCTRL_PEREO0_Pos)
-#define RTC_MODE2_EVCTRL_PEREO1_Pos 1            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO1     (_U_(1) << RTC_MODE2_EVCTRL_PEREO1_Pos)
-#define RTC_MODE2_EVCTRL_PEREO2_Pos 2            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO2     (_U_(1) << RTC_MODE2_EVCTRL_PEREO2_Pos)
-#define RTC_MODE2_EVCTRL_PEREO3_Pos 3            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO3     (_U_(1) << RTC_MODE2_EVCTRL_PEREO3_Pos)
-#define RTC_MODE2_EVCTRL_PEREO4_Pos 4            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO4     (_U_(1) << RTC_MODE2_EVCTRL_PEREO4_Pos)
-#define RTC_MODE2_EVCTRL_PEREO5_Pos 5            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO5     (_U_(1) << RTC_MODE2_EVCTRL_PEREO5_Pos)
-#define RTC_MODE2_EVCTRL_PEREO6_Pos 6            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO6     (_U_(1) << RTC_MODE2_EVCTRL_PEREO6_Pos)
-#define RTC_MODE2_EVCTRL_PEREO7_Pos 7            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO7     (_U_(1) << RTC_MODE2_EVCTRL_PEREO7_Pos)
-#define RTC_MODE2_EVCTRL_PEREO_Pos  0            /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
-#define RTC_MODE2_EVCTRL_PEREO_Msk  (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)
-#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
-#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
-#define RTC_MODE2_EVCTRL_ALARMEO0   (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
-#define RTC_MODE2_EVCTRL_ALARMEO1_Pos 9            /**< \brief (RTC_MODE2_EVCTRL) Alarm 1 Event Output Enable */
-#define RTC_MODE2_EVCTRL_ALARMEO1   (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO1_Pos)
-#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8            /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
-#define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x3) << RTC_MODE2_EVCTRL_ALARMEO_Pos)
-#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
-#define RTC_MODE2_EVCTRL_TAMPEREO_Pos 14           /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Output Enable */
-#define RTC_MODE2_EVCTRL_TAMPEREO   (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)
-#define RTC_MODE2_EVCTRL_OVFEO_Pos  15           /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
-#define RTC_MODE2_EVCTRL_OVFEO      (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)
-#define RTC_MODE2_EVCTRL_TAMPEVEI_Pos 16           /**< \brief (RTC_MODE2_EVCTRL) Tamper Event Input Enable */
-#define RTC_MODE2_EVCTRL_TAMPEVEI   (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)
-#define RTC_MODE2_EVCTRL_MASK       _U_(0x0001C3FF) /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
-
-/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
-    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
-    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
-    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
-    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
-    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
-    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
-    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
-    uint16_t CMP0:1;           /*!< bit:      8  Compare 0 Interrupt Enable         */
-    uint16_t CMP1:1;           /*!< bit:      9  Compare 1 Interrupt Enable         */
-    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
-    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
-    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
-    uint16_t CMP:2;            /*!< bit:  8.. 9  Compare x Interrupt Enable         */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_INTENCLR_OFFSET   0x08         /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
-#define RTC_MODE0_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
-
-#define RTC_MODE0_INTENCLR_PER0_Pos 0            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER0     (_U_(1) << RTC_MODE0_INTENCLR_PER0_Pos)
-#define RTC_MODE0_INTENCLR_PER1_Pos 1            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER1     (_U_(1) << RTC_MODE0_INTENCLR_PER1_Pos)
-#define RTC_MODE0_INTENCLR_PER2_Pos 2            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER2     (_U_(1) << RTC_MODE0_INTENCLR_PER2_Pos)
-#define RTC_MODE0_INTENCLR_PER3_Pos 3            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER3     (_U_(1) << RTC_MODE0_INTENCLR_PER3_Pos)
-#define RTC_MODE0_INTENCLR_PER4_Pos 4            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER4     (_U_(1) << RTC_MODE0_INTENCLR_PER4_Pos)
-#define RTC_MODE0_INTENCLR_PER5_Pos 5            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER5     (_U_(1) << RTC_MODE0_INTENCLR_PER5_Pos)
-#define RTC_MODE0_INTENCLR_PER6_Pos 6            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER6     (_U_(1) << RTC_MODE0_INTENCLR_PER6_Pos)
-#define RTC_MODE0_INTENCLR_PER7_Pos 7            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER7     (_U_(1) << RTC_MODE0_INTENCLR_PER7_Pos)
-#define RTC_MODE0_INTENCLR_PER_Pos  0            /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable */
-#define RTC_MODE0_INTENCLR_PER_Msk  (_U_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)
-#define RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))
-#define RTC_MODE0_INTENCLR_CMP0_Pos 8            /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_CMP0     (_U_(1) << RTC_MODE0_INTENCLR_CMP0_Pos)
-#define RTC_MODE0_INTENCLR_CMP1_Pos 9            /**< \brief (RTC_MODE0_INTENCLR) Compare 1 Interrupt Enable */
-#define RTC_MODE0_INTENCLR_CMP1     (_U_(1) << RTC_MODE0_INTENCLR_CMP1_Pos)
-#define RTC_MODE0_INTENCLR_CMP_Pos  8            /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
-#define RTC_MODE0_INTENCLR_CMP_Msk  (_U_(0x3) << RTC_MODE0_INTENCLR_CMP_Pos)
-#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
-#define RTC_MODE0_INTENCLR_TAMPER_Pos 14           /**< \brief (RTC_MODE0_INTENCLR) Tamper Enable */
-#define RTC_MODE0_INTENCLR_TAMPER   (_U_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)
-#define RTC_MODE0_INTENCLR_OVF_Pos  15           /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
-#define RTC_MODE0_INTENCLR_OVF      (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)
-#define RTC_MODE0_INTENCLR_MASK     _U_(0xC3FF)  /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
-
-/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
-    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
-    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
-    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
-    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
-    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
-    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
-    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
-    uint16_t CMP0:1;           /*!< bit:      8  Compare 0 Interrupt Enable         */
-    uint16_t CMP1:1;           /*!< bit:      9  Compare 1 Interrupt Enable         */
-    uint16_t CMP2:1;           /*!< bit:     10  Compare 2 Interrupt Enable         */
-    uint16_t CMP3:1;           /*!< bit:     11  Compare 3 Interrupt Enable         */
-    uint16_t :2;               /*!< bit: 12..13  Reserved                           */
-    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
-    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
-    uint16_t CMP:4;            /*!< bit:  8..11  Compare x Interrupt Enable         */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_INTENCLR_OFFSET   0x08         /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
-#define RTC_MODE1_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
-
-#define RTC_MODE1_INTENCLR_PER0_Pos 0            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER0     (_U_(1) << RTC_MODE1_INTENCLR_PER0_Pos)
-#define RTC_MODE1_INTENCLR_PER1_Pos 1            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER1     (_U_(1) << RTC_MODE1_INTENCLR_PER1_Pos)
-#define RTC_MODE1_INTENCLR_PER2_Pos 2            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER2     (_U_(1) << RTC_MODE1_INTENCLR_PER2_Pos)
-#define RTC_MODE1_INTENCLR_PER3_Pos 3            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER3     (_U_(1) << RTC_MODE1_INTENCLR_PER3_Pos)
-#define RTC_MODE1_INTENCLR_PER4_Pos 4            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER4     (_U_(1) << RTC_MODE1_INTENCLR_PER4_Pos)
-#define RTC_MODE1_INTENCLR_PER5_Pos 5            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER5     (_U_(1) << RTC_MODE1_INTENCLR_PER5_Pos)
-#define RTC_MODE1_INTENCLR_PER6_Pos 6            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER6     (_U_(1) << RTC_MODE1_INTENCLR_PER6_Pos)
-#define RTC_MODE1_INTENCLR_PER7_Pos 7            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER7     (_U_(1) << RTC_MODE1_INTENCLR_PER7_Pos)
-#define RTC_MODE1_INTENCLR_PER_Pos  0            /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable */
-#define RTC_MODE1_INTENCLR_PER_Msk  (_U_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)
-#define RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))
-#define RTC_MODE1_INTENCLR_CMP0_Pos 8            /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP0     (_U_(1) << RTC_MODE1_INTENCLR_CMP0_Pos)
-#define RTC_MODE1_INTENCLR_CMP1_Pos 9            /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP1     (_U_(1) << RTC_MODE1_INTENCLR_CMP1_Pos)
-#define RTC_MODE1_INTENCLR_CMP2_Pos 10           /**< \brief (RTC_MODE1_INTENCLR) Compare 2 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP2     (_U_(1) << RTC_MODE1_INTENCLR_CMP2_Pos)
-#define RTC_MODE1_INTENCLR_CMP3_Pos 11           /**< \brief (RTC_MODE1_INTENCLR) Compare 3 Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP3     (_U_(1) << RTC_MODE1_INTENCLR_CMP3_Pos)
-#define RTC_MODE1_INTENCLR_CMP_Pos  8            /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
-#define RTC_MODE1_INTENCLR_CMP_Msk  (_U_(0xF) << RTC_MODE1_INTENCLR_CMP_Pos)
-#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
-#define RTC_MODE1_INTENCLR_TAMPER_Pos 14           /**< \brief (RTC_MODE1_INTENCLR) Tamper Enable */
-#define RTC_MODE1_INTENCLR_TAMPER   (_U_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)
-#define RTC_MODE1_INTENCLR_OVF_Pos  15           /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
-#define RTC_MODE1_INTENCLR_OVF      (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)
-#define RTC_MODE1_INTENCLR_MASK     _U_(0xCFFF)  /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
-
-/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
-    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
-    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
-    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
-    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
-    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
-    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
-    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
-    uint16_t ALARM0:1;         /*!< bit:      8  Alarm 0 Interrupt Enable           */
-    uint16_t ALARM1:1;         /*!< bit:      9  Alarm 1 Interrupt Enable           */
-    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
-    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
-    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
-    uint16_t ALARM:2;          /*!< bit:  8.. 9  Alarm x Interrupt Enable           */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_INTENCLR_OFFSET   0x08         /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
-#define RTC_MODE2_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
-
-#define RTC_MODE2_INTENCLR_PER0_Pos 0            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER0     (_U_(1) << RTC_MODE2_INTENCLR_PER0_Pos)
-#define RTC_MODE2_INTENCLR_PER1_Pos 1            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER1     (_U_(1) << RTC_MODE2_INTENCLR_PER1_Pos)
-#define RTC_MODE2_INTENCLR_PER2_Pos 2            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER2     (_U_(1) << RTC_MODE2_INTENCLR_PER2_Pos)
-#define RTC_MODE2_INTENCLR_PER3_Pos 3            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER3     (_U_(1) << RTC_MODE2_INTENCLR_PER3_Pos)
-#define RTC_MODE2_INTENCLR_PER4_Pos 4            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER4     (_U_(1) << RTC_MODE2_INTENCLR_PER4_Pos)
-#define RTC_MODE2_INTENCLR_PER5_Pos 5            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER5     (_U_(1) << RTC_MODE2_INTENCLR_PER5_Pos)
-#define RTC_MODE2_INTENCLR_PER6_Pos 6            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER6     (_U_(1) << RTC_MODE2_INTENCLR_PER6_Pos)
-#define RTC_MODE2_INTENCLR_PER7_Pos 7            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER7     (_U_(1) << RTC_MODE2_INTENCLR_PER7_Pos)
-#define RTC_MODE2_INTENCLR_PER_Pos  0            /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable */
-#define RTC_MODE2_INTENCLR_PER_Msk  (_U_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)
-#define RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))
-#define RTC_MODE2_INTENCLR_ALARM0_Pos 8            /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_ALARM0   (_U_(1) << RTC_MODE2_INTENCLR_ALARM0_Pos)
-#define RTC_MODE2_INTENCLR_ALARM1_Pos 9            /**< \brief (RTC_MODE2_INTENCLR) Alarm 1 Interrupt Enable */
-#define RTC_MODE2_INTENCLR_ALARM1   (_U_(1) << RTC_MODE2_INTENCLR_ALARM1_Pos)
-#define RTC_MODE2_INTENCLR_ALARM_Pos 8            /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
-#define RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENCLR_ALARM_Pos)
-#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
-#define RTC_MODE2_INTENCLR_TAMPER_Pos 14           /**< \brief (RTC_MODE2_INTENCLR) Tamper Enable */
-#define RTC_MODE2_INTENCLR_TAMPER   (_U_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)
-#define RTC_MODE2_INTENCLR_OVF_Pos  15           /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
-#define RTC_MODE2_INTENCLR_OVF      (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)
-#define RTC_MODE2_INTENCLR_MASK     _U_(0xC3FF)  /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
-
-/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
-    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
-    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
-    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
-    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
-    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
-    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
-    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
-    uint16_t CMP0:1;           /*!< bit:      8  Compare 0 Interrupt Enable         */
-    uint16_t CMP1:1;           /*!< bit:      9  Compare 1 Interrupt Enable         */
-    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
-    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
-    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
-    uint16_t CMP:2;            /*!< bit:  8.. 9  Compare x Interrupt Enable         */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_INTENSET_OFFSET   0x0A         /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
-#define RTC_MODE0_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
-
-#define RTC_MODE0_INTENSET_PER0_Pos 0            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER0     (_U_(1) << RTC_MODE0_INTENSET_PER0_Pos)
-#define RTC_MODE0_INTENSET_PER1_Pos 1            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER1     (_U_(1) << RTC_MODE0_INTENSET_PER1_Pos)
-#define RTC_MODE0_INTENSET_PER2_Pos 2            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER2     (_U_(1) << RTC_MODE0_INTENSET_PER2_Pos)
-#define RTC_MODE0_INTENSET_PER3_Pos 3            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER3     (_U_(1) << RTC_MODE0_INTENSET_PER3_Pos)
-#define RTC_MODE0_INTENSET_PER4_Pos 4            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER4     (_U_(1) << RTC_MODE0_INTENSET_PER4_Pos)
-#define RTC_MODE0_INTENSET_PER5_Pos 5            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER5     (_U_(1) << RTC_MODE0_INTENSET_PER5_Pos)
-#define RTC_MODE0_INTENSET_PER6_Pos 6            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER6     (_U_(1) << RTC_MODE0_INTENSET_PER6_Pos)
-#define RTC_MODE0_INTENSET_PER7_Pos 7            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER7     (_U_(1) << RTC_MODE0_INTENSET_PER7_Pos)
-#define RTC_MODE0_INTENSET_PER_Pos  0            /**< \brief (RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable */
-#define RTC_MODE0_INTENSET_PER_Msk  (_U_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)
-#define RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))
-#define RTC_MODE0_INTENSET_CMP0_Pos 8            /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
-#define RTC_MODE0_INTENSET_CMP0     (_U_(1) << RTC_MODE0_INTENSET_CMP0_Pos)
-#define RTC_MODE0_INTENSET_CMP1_Pos 9            /**< \brief (RTC_MODE0_INTENSET) Compare 1 Interrupt Enable */
-#define RTC_MODE0_INTENSET_CMP1     (_U_(1) << RTC_MODE0_INTENSET_CMP1_Pos)
-#define RTC_MODE0_INTENSET_CMP_Pos  8            /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
-#define RTC_MODE0_INTENSET_CMP_Msk  (_U_(0x3) << RTC_MODE0_INTENSET_CMP_Pos)
-#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
-#define RTC_MODE0_INTENSET_TAMPER_Pos 14           /**< \brief (RTC_MODE0_INTENSET) Tamper Enable */
-#define RTC_MODE0_INTENSET_TAMPER   (_U_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)
-#define RTC_MODE0_INTENSET_OVF_Pos  15           /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
-#define RTC_MODE0_INTENSET_OVF      (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)
-#define RTC_MODE0_INTENSET_MASK     _U_(0xC3FF)  /**< \brief (RTC_MODE0_INTENSET) MASK Register */
-
-/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Interrupt Enable */
-    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Interrupt Enable */
-    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Interrupt Enable */
-    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Interrupt Enable */
-    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Interrupt Enable */
-    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Interrupt Enable */
-    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Interrupt Enable */
-    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Interrupt Enable */
-    uint16_t CMP0:1;           /*!< bit:      8  Compare 0 Interrupt Enable         */
-    uint16_t CMP1:1;           /*!< bit:      9  Compare 1 Interrupt Enable         */
-    uint16_t CMP2:1;           /*!< bit:     10  Compare 2 Interrupt Enable         */
-    uint16_t CMP3:1;           /*!< bit:     11  Compare 3 Interrupt Enable         */
-    uint16_t :2;               /*!< bit: 12..13  Reserved                           */
-    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
-    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Interrupt Enable */
-    uint16_t CMP:4;            /*!< bit:  8..11  Compare x Interrupt Enable         */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_INTENSET_OFFSET   0x0A         /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
-#define RTC_MODE1_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
-
-#define RTC_MODE1_INTENSET_PER0_Pos 0            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER0     (_U_(1) << RTC_MODE1_INTENSET_PER0_Pos)
-#define RTC_MODE1_INTENSET_PER1_Pos 1            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER1     (_U_(1) << RTC_MODE1_INTENSET_PER1_Pos)
-#define RTC_MODE1_INTENSET_PER2_Pos 2            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER2     (_U_(1) << RTC_MODE1_INTENSET_PER2_Pos)
-#define RTC_MODE1_INTENSET_PER3_Pos 3            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER3     (_U_(1) << RTC_MODE1_INTENSET_PER3_Pos)
-#define RTC_MODE1_INTENSET_PER4_Pos 4            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER4     (_U_(1) << RTC_MODE1_INTENSET_PER4_Pos)
-#define RTC_MODE1_INTENSET_PER5_Pos 5            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER5     (_U_(1) << RTC_MODE1_INTENSET_PER5_Pos)
-#define RTC_MODE1_INTENSET_PER6_Pos 6            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER6     (_U_(1) << RTC_MODE1_INTENSET_PER6_Pos)
-#define RTC_MODE1_INTENSET_PER7_Pos 7            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER7     (_U_(1) << RTC_MODE1_INTENSET_PER7_Pos)
-#define RTC_MODE1_INTENSET_PER_Pos  0            /**< \brief (RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable */
-#define RTC_MODE1_INTENSET_PER_Msk  (_U_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)
-#define RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))
-#define RTC_MODE1_INTENSET_CMP0_Pos 8            /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP0     (_U_(1) << RTC_MODE1_INTENSET_CMP0_Pos)
-#define RTC_MODE1_INTENSET_CMP1_Pos 9            /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP1     (_U_(1) << RTC_MODE1_INTENSET_CMP1_Pos)
-#define RTC_MODE1_INTENSET_CMP2_Pos 10           /**< \brief (RTC_MODE1_INTENSET) Compare 2 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP2     (_U_(1) << RTC_MODE1_INTENSET_CMP2_Pos)
-#define RTC_MODE1_INTENSET_CMP3_Pos 11           /**< \brief (RTC_MODE1_INTENSET) Compare 3 Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP3     (_U_(1) << RTC_MODE1_INTENSET_CMP3_Pos)
-#define RTC_MODE1_INTENSET_CMP_Pos  8            /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
-#define RTC_MODE1_INTENSET_CMP_Msk  (_U_(0xF) << RTC_MODE1_INTENSET_CMP_Pos)
-#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
-#define RTC_MODE1_INTENSET_TAMPER_Pos 14           /**< \brief (RTC_MODE1_INTENSET) Tamper Enable */
-#define RTC_MODE1_INTENSET_TAMPER   (_U_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)
-#define RTC_MODE1_INTENSET_OVF_Pos  15           /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
-#define RTC_MODE1_INTENSET_OVF      (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)
-#define RTC_MODE1_INTENSET_MASK     _U_(0xCFFF)  /**< \brief (RTC_MODE1_INTENSET) MASK Register */
-
-/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0 Enable         */
-    uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1 Enable         */
-    uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2 Enable         */
-    uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3 Enable         */
-    uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4 Enable         */
-    uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5 Enable         */
-    uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6 Enable         */
-    uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7 Enable         */
-    uint16_t ALARM0:1;         /*!< bit:      8  Alarm 0 Interrupt Enable           */
-    uint16_t ALARM1:1;         /*!< bit:      9  Alarm 1 Interrupt Enable           */
-    uint16_t :4;               /*!< bit: 10..13  Reserved                           */
-    uint16_t TAMPER:1;         /*!< bit:     14  Tamper Enable                      */
-    uint16_t OVF:1;            /*!< bit:     15  Overflow Interrupt Enable          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x Enable         */
-    uint16_t ALARM:2;          /*!< bit:  8.. 9  Alarm x Interrupt Enable           */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_INTENSET_OFFSET   0x0A         /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
-#define RTC_MODE2_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
-
-#define RTC_MODE2_INTENSET_PER0_Pos 0            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 0 Enable */
-#define RTC_MODE2_INTENSET_PER0     (_U_(1) << RTC_MODE2_INTENSET_PER0_Pos)
-#define RTC_MODE2_INTENSET_PER1_Pos 1            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 1 Enable */
-#define RTC_MODE2_INTENSET_PER1     (_U_(1) << RTC_MODE2_INTENSET_PER1_Pos)
-#define RTC_MODE2_INTENSET_PER2_Pos 2            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 2 Enable */
-#define RTC_MODE2_INTENSET_PER2     (_U_(1) << RTC_MODE2_INTENSET_PER2_Pos)
-#define RTC_MODE2_INTENSET_PER3_Pos 3            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 3 Enable */
-#define RTC_MODE2_INTENSET_PER3     (_U_(1) << RTC_MODE2_INTENSET_PER3_Pos)
-#define RTC_MODE2_INTENSET_PER4_Pos 4            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 4 Enable */
-#define RTC_MODE2_INTENSET_PER4     (_U_(1) << RTC_MODE2_INTENSET_PER4_Pos)
-#define RTC_MODE2_INTENSET_PER5_Pos 5            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 5 Enable */
-#define RTC_MODE2_INTENSET_PER5     (_U_(1) << RTC_MODE2_INTENSET_PER5_Pos)
-#define RTC_MODE2_INTENSET_PER6_Pos 6            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 6 Enable */
-#define RTC_MODE2_INTENSET_PER6     (_U_(1) << RTC_MODE2_INTENSET_PER6_Pos)
-#define RTC_MODE2_INTENSET_PER7_Pos 7            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 7 Enable */
-#define RTC_MODE2_INTENSET_PER7     (_U_(1) << RTC_MODE2_INTENSET_PER7_Pos)
-#define RTC_MODE2_INTENSET_PER_Pos  0            /**< \brief (RTC_MODE2_INTENSET) Periodic Interval x Enable */
-#define RTC_MODE2_INTENSET_PER_Msk  (_U_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)
-#define RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))
-#define RTC_MODE2_INTENSET_ALARM0_Pos 8            /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
-#define RTC_MODE2_INTENSET_ALARM0   (_U_(1) << RTC_MODE2_INTENSET_ALARM0_Pos)
-#define RTC_MODE2_INTENSET_ALARM1_Pos 9            /**< \brief (RTC_MODE2_INTENSET) Alarm 1 Interrupt Enable */
-#define RTC_MODE2_INTENSET_ALARM1   (_U_(1) << RTC_MODE2_INTENSET_ALARM1_Pos)
-#define RTC_MODE2_INTENSET_ALARM_Pos 8            /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
-#define RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTENSET_ALARM_Pos)
-#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
-#define RTC_MODE2_INTENSET_TAMPER_Pos 14           /**< \brief (RTC_MODE2_INTENSET) Tamper Enable */
-#define RTC_MODE2_INTENSET_TAMPER   (_U_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)
-#define RTC_MODE2_INTENSET_OVF_Pos  15           /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
-#define RTC_MODE2_INTENSET_OVF      (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)
-#define RTC_MODE2_INTENSET_MASK     _U_(0xC3FF)  /**< \brief (RTC_MODE2_INTENSET) MASK Register */
-
-/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0                */
-    __I uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1                */
-    __I uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2                */
-    __I uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3                */
-    __I uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4                */
-    __I uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5                */
-    __I uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6                */
-    __I uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7                */
-    __I uint16_t CMP0:1;           /*!< bit:      8  Compare 0                          */
-    __I uint16_t CMP1:1;           /*!< bit:      9  Compare 1                          */
-    __I uint16_t :4;               /*!< bit: 10..13  Reserved                           */
-    __I uint16_t TAMPER:1;         /*!< bit:     14  Tamper                             */
-    __I uint16_t OVF:1;            /*!< bit:     15  Overflow                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x                */
-    __I uint16_t CMP:2;            /*!< bit:  8.. 9  Compare x                          */
-    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_INTFLAG_OFFSET    0x0C         /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
-#define RTC_MODE0_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
-
-#define RTC_MODE0_INTFLAG_PER0_Pos  0            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 0 */
-#define RTC_MODE0_INTFLAG_PER0      (_U_(1) << RTC_MODE0_INTFLAG_PER0_Pos)
-#define RTC_MODE0_INTFLAG_PER1_Pos  1            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 1 */
-#define RTC_MODE0_INTFLAG_PER1      (_U_(1) << RTC_MODE0_INTFLAG_PER1_Pos)
-#define RTC_MODE0_INTFLAG_PER2_Pos  2            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 2 */
-#define RTC_MODE0_INTFLAG_PER2      (_U_(1) << RTC_MODE0_INTFLAG_PER2_Pos)
-#define RTC_MODE0_INTFLAG_PER3_Pos  3            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 3 */
-#define RTC_MODE0_INTFLAG_PER3      (_U_(1) << RTC_MODE0_INTFLAG_PER3_Pos)
-#define RTC_MODE0_INTFLAG_PER4_Pos  4            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 4 */
-#define RTC_MODE0_INTFLAG_PER4      (_U_(1) << RTC_MODE0_INTFLAG_PER4_Pos)
-#define RTC_MODE0_INTFLAG_PER5_Pos  5            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 5 */
-#define RTC_MODE0_INTFLAG_PER5      (_U_(1) << RTC_MODE0_INTFLAG_PER5_Pos)
-#define RTC_MODE0_INTFLAG_PER6_Pos  6            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 6 */
-#define RTC_MODE0_INTFLAG_PER6      (_U_(1) << RTC_MODE0_INTFLAG_PER6_Pos)
-#define RTC_MODE0_INTFLAG_PER7_Pos  7            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 7 */
-#define RTC_MODE0_INTFLAG_PER7      (_U_(1) << RTC_MODE0_INTFLAG_PER7_Pos)
-#define RTC_MODE0_INTFLAG_PER_Pos   0            /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval x */
-#define RTC_MODE0_INTFLAG_PER_Msk   (_U_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)
-#define RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))
-#define RTC_MODE0_INTFLAG_CMP0_Pos  8            /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
-#define RTC_MODE0_INTFLAG_CMP0      (_U_(1) << RTC_MODE0_INTFLAG_CMP0_Pos)
-#define RTC_MODE0_INTFLAG_CMP1_Pos  9            /**< \brief (RTC_MODE0_INTFLAG) Compare 1 */
-#define RTC_MODE0_INTFLAG_CMP1      (_U_(1) << RTC_MODE0_INTFLAG_CMP1_Pos)
-#define RTC_MODE0_INTFLAG_CMP_Pos   8            /**< \brief (RTC_MODE0_INTFLAG) Compare x */
-#define RTC_MODE0_INTFLAG_CMP_Msk   (_U_(0x3) << RTC_MODE0_INTFLAG_CMP_Pos)
-#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
-#define RTC_MODE0_INTFLAG_TAMPER_Pos 14           /**< \brief (RTC_MODE0_INTFLAG) Tamper */
-#define RTC_MODE0_INTFLAG_TAMPER    (_U_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)
-#define RTC_MODE0_INTFLAG_OVF_Pos   15           /**< \brief (RTC_MODE0_INTFLAG) Overflow */
-#define RTC_MODE0_INTFLAG_OVF       (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)
-#define RTC_MODE0_INTFLAG_MASK      _U_(0xC3FF)  /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
-
-/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0                */
-    __I uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1                */
-    __I uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2                */
-    __I uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3                */
-    __I uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4                */
-    __I uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5                */
-    __I uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6                */
-    __I uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7                */
-    __I uint16_t CMP0:1;           /*!< bit:      8  Compare 0                          */
-    __I uint16_t CMP1:1;           /*!< bit:      9  Compare 1                          */
-    __I uint16_t CMP2:1;           /*!< bit:     10  Compare 2                          */
-    __I uint16_t CMP3:1;           /*!< bit:     11  Compare 3                          */
-    __I uint16_t :2;               /*!< bit: 12..13  Reserved                           */
-    __I uint16_t TAMPER:1;         /*!< bit:     14  Tamper                             */
-    __I uint16_t OVF:1;            /*!< bit:     15  Overflow                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x                */
-    __I uint16_t CMP:4;            /*!< bit:  8..11  Compare x                          */
-    __I uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_INTFLAG_OFFSET    0x0C         /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
-#define RTC_MODE1_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
-
-#define RTC_MODE1_INTFLAG_PER0_Pos  0            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 0 */
-#define RTC_MODE1_INTFLAG_PER0      (_U_(1) << RTC_MODE1_INTFLAG_PER0_Pos)
-#define RTC_MODE1_INTFLAG_PER1_Pos  1            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 1 */
-#define RTC_MODE1_INTFLAG_PER1      (_U_(1) << RTC_MODE1_INTFLAG_PER1_Pos)
-#define RTC_MODE1_INTFLAG_PER2_Pos  2            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 2 */
-#define RTC_MODE1_INTFLAG_PER2      (_U_(1) << RTC_MODE1_INTFLAG_PER2_Pos)
-#define RTC_MODE1_INTFLAG_PER3_Pos  3            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 3 */
-#define RTC_MODE1_INTFLAG_PER3      (_U_(1) << RTC_MODE1_INTFLAG_PER3_Pos)
-#define RTC_MODE1_INTFLAG_PER4_Pos  4            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 4 */
-#define RTC_MODE1_INTFLAG_PER4      (_U_(1) << RTC_MODE1_INTFLAG_PER4_Pos)
-#define RTC_MODE1_INTFLAG_PER5_Pos  5            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 5 */
-#define RTC_MODE1_INTFLAG_PER5      (_U_(1) << RTC_MODE1_INTFLAG_PER5_Pos)
-#define RTC_MODE1_INTFLAG_PER6_Pos  6            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 6 */
-#define RTC_MODE1_INTFLAG_PER6      (_U_(1) << RTC_MODE1_INTFLAG_PER6_Pos)
-#define RTC_MODE1_INTFLAG_PER7_Pos  7            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 7 */
-#define RTC_MODE1_INTFLAG_PER7      (_U_(1) << RTC_MODE1_INTFLAG_PER7_Pos)
-#define RTC_MODE1_INTFLAG_PER_Pos   0            /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval x */
-#define RTC_MODE1_INTFLAG_PER_Msk   (_U_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)
-#define RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))
-#define RTC_MODE1_INTFLAG_CMP0_Pos  8            /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
-#define RTC_MODE1_INTFLAG_CMP0      (_U_(1) << RTC_MODE1_INTFLAG_CMP0_Pos)
-#define RTC_MODE1_INTFLAG_CMP1_Pos  9            /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
-#define RTC_MODE1_INTFLAG_CMP1      (_U_(1) << RTC_MODE1_INTFLAG_CMP1_Pos)
-#define RTC_MODE1_INTFLAG_CMP2_Pos  10           /**< \brief (RTC_MODE1_INTFLAG) Compare 2 */
-#define RTC_MODE1_INTFLAG_CMP2      (_U_(1) << RTC_MODE1_INTFLAG_CMP2_Pos)
-#define RTC_MODE1_INTFLAG_CMP3_Pos  11           /**< \brief (RTC_MODE1_INTFLAG) Compare 3 */
-#define RTC_MODE1_INTFLAG_CMP3      (_U_(1) << RTC_MODE1_INTFLAG_CMP3_Pos)
-#define RTC_MODE1_INTFLAG_CMP_Pos   8            /**< \brief (RTC_MODE1_INTFLAG) Compare x */
-#define RTC_MODE1_INTFLAG_CMP_Msk   (_U_(0xF) << RTC_MODE1_INTFLAG_CMP_Pos)
-#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
-#define RTC_MODE1_INTFLAG_TAMPER_Pos 14           /**< \brief (RTC_MODE1_INTFLAG) Tamper */
-#define RTC_MODE1_INTFLAG_TAMPER    (_U_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)
-#define RTC_MODE1_INTFLAG_OVF_Pos   15           /**< \brief (RTC_MODE1_INTFLAG) Overflow */
-#define RTC_MODE1_INTFLAG_OVF       (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)
-#define RTC_MODE1_INTFLAG_MASK      _U_(0xCFFF)  /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
-
-/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t PER0:1;           /*!< bit:      0  Periodic Interval 0                */
-    __I uint16_t PER1:1;           /*!< bit:      1  Periodic Interval 1                */
-    __I uint16_t PER2:1;           /*!< bit:      2  Periodic Interval 2                */
-    __I uint16_t PER3:1;           /*!< bit:      3  Periodic Interval 3                */
-    __I uint16_t PER4:1;           /*!< bit:      4  Periodic Interval 4                */
-    __I uint16_t PER5:1;           /*!< bit:      5  Periodic Interval 5                */
-    __I uint16_t PER6:1;           /*!< bit:      6  Periodic Interval 6                */
-    __I uint16_t PER7:1;           /*!< bit:      7  Periodic Interval 7                */
-    __I uint16_t ALARM0:1;         /*!< bit:      8  Alarm 0                            */
-    __I uint16_t ALARM1:1;         /*!< bit:      9  Alarm 1                            */
-    __I uint16_t :4;               /*!< bit: 10..13  Reserved                           */
-    __I uint16_t TAMPER:1;         /*!< bit:     14  Tamper                             */
-    __I uint16_t OVF:1;            /*!< bit:     15  Overflow                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint16_t PER:8;            /*!< bit:  0.. 7  Periodic Interval x                */
-    __I uint16_t ALARM:2;          /*!< bit:  8.. 9  Alarm x                            */
-    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_INTFLAG_OFFSET    0x0C         /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
-#define RTC_MODE2_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
-
-#define RTC_MODE2_INTFLAG_PER0_Pos  0            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 0 */
-#define RTC_MODE2_INTFLAG_PER0      (_U_(1) << RTC_MODE2_INTFLAG_PER0_Pos)
-#define RTC_MODE2_INTFLAG_PER1_Pos  1            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 1 */
-#define RTC_MODE2_INTFLAG_PER1      (_U_(1) << RTC_MODE2_INTFLAG_PER1_Pos)
-#define RTC_MODE2_INTFLAG_PER2_Pos  2            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 2 */
-#define RTC_MODE2_INTFLAG_PER2      (_U_(1) << RTC_MODE2_INTFLAG_PER2_Pos)
-#define RTC_MODE2_INTFLAG_PER3_Pos  3            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 3 */
-#define RTC_MODE2_INTFLAG_PER3      (_U_(1) << RTC_MODE2_INTFLAG_PER3_Pos)
-#define RTC_MODE2_INTFLAG_PER4_Pos  4            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 4 */
-#define RTC_MODE2_INTFLAG_PER4      (_U_(1) << RTC_MODE2_INTFLAG_PER4_Pos)
-#define RTC_MODE2_INTFLAG_PER5_Pos  5            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 5 */
-#define RTC_MODE2_INTFLAG_PER5      (_U_(1) << RTC_MODE2_INTFLAG_PER5_Pos)
-#define RTC_MODE2_INTFLAG_PER6_Pos  6            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 6 */
-#define RTC_MODE2_INTFLAG_PER6      (_U_(1) << RTC_MODE2_INTFLAG_PER6_Pos)
-#define RTC_MODE2_INTFLAG_PER7_Pos  7            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 7 */
-#define RTC_MODE2_INTFLAG_PER7      (_U_(1) << RTC_MODE2_INTFLAG_PER7_Pos)
-#define RTC_MODE2_INTFLAG_PER_Pos   0            /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval x */
-#define RTC_MODE2_INTFLAG_PER_Msk   (_U_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)
-#define RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))
-#define RTC_MODE2_INTFLAG_ALARM0_Pos 8            /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
-#define RTC_MODE2_INTFLAG_ALARM0    (_U_(1) << RTC_MODE2_INTFLAG_ALARM0_Pos)
-#define RTC_MODE2_INTFLAG_ALARM1_Pos 9            /**< \brief (RTC_MODE2_INTFLAG) Alarm 1 */
-#define RTC_MODE2_INTFLAG_ALARM1    (_U_(1) << RTC_MODE2_INTFLAG_ALARM1_Pos)
-#define RTC_MODE2_INTFLAG_ALARM_Pos 8            /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
-#define RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x3) << RTC_MODE2_INTFLAG_ALARM_Pos)
-#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
-#define RTC_MODE2_INTFLAG_TAMPER_Pos 14           /**< \brief (RTC_MODE2_INTFLAG) Tamper */
-#define RTC_MODE2_INTFLAG_TAMPER    (_U_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)
-#define RTC_MODE2_INTFLAG_OVF_Pos   15           /**< \brief (RTC_MODE2_INTFLAG) Overflow */
-#define RTC_MODE2_INTFLAG_OVF       (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)
-#define RTC_MODE2_INTFLAG_MASK      _U_(0xC3FF)  /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
-
-/* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Run During Debug                   */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_DBGCTRL_OFFSET          0x0E         /**< \brief (RTC_DBGCTRL offset) Debug Control */
-#define RTC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
-
-#define RTC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (RTC_DBGCTRL) Run During Debug */
-#define RTC_DBGCTRL_DBGRUN          (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)
-#define RTC_DBGCTRL_MASK            _U_(0x01)    /**< \brief (RTC_DBGCTRL) MASK Register */
-
-/* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/  32) MODE0 MODE0 Synchronization Busy Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Busy                */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Bit Busy                    */
-    uint32_t FREQCORR:1;       /*!< bit:      2  FREQCORR Register Busy             */
-    uint32_t COUNT:1;          /*!< bit:      3  COUNT Register Busy                */
-    uint32_t :1;               /*!< bit:      4  Reserved                           */
-    uint32_t COMP0:1;          /*!< bit:      5  COMP 0 Register Busy               */
-    uint32_t COMP1:1;          /*!< bit:      6  COMP 1 Register Busy               */
-    uint32_t :8;               /*!< bit:  7..14  Reserved                           */
-    uint32_t COUNTSYNC:1;      /*!< bit:     15  Count Synchronization Enable Bit Busy */
-    uint32_t GP0:1;            /*!< bit:     16  General Purpose 0 Register Busy    */
-    uint32_t GP1:1;            /*!< bit:     17  General Purpose 1 Register Busy    */
-    uint32_t GP2:1;            /*!< bit:     18  General Purpose 2 Register Busy    */
-    uint32_t GP3:1;            /*!< bit:     19  General Purpose 3 Register Busy    */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
-    uint32_t COMP:2;           /*!< bit:  5.. 6  COMP x Register Busy               */
-    uint32_t :9;               /*!< bit:  7..15  Reserved                           */
-    uint32_t GP:4;             /*!< bit: 16..19  General Purpose x Register Busy    */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_SYNCBUSY_OFFSET   0x10         /**< \brief (RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status */
-#define RTC_MODE0_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status */
-
-#define RTC_MODE0_SYNCBUSY_SWRST_Pos 0            /**< \brief (RTC_MODE0_SYNCBUSY) Software Reset Busy */
-#define RTC_MODE0_SYNCBUSY_SWRST    (_U_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)
-#define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1            /**< \brief (RTC_MODE0_SYNCBUSY) Enable Bit Busy */
-#define RTC_MODE0_SYNCBUSY_ENABLE   (_U_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)
-#define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2            /**< \brief (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy */
-#define RTC_MODE0_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)
-#define RTC_MODE0_SYNCBUSY_COUNT_Pos 3            /**< \brief (RTC_MODE0_SYNCBUSY) COUNT Register Busy */
-#define RTC_MODE0_SYNCBUSY_COUNT    (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)
-#define RTC_MODE0_SYNCBUSY_COMP0_Pos 5            /**< \brief (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy */
-#define RTC_MODE0_SYNCBUSY_COMP0    (_U_(1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)
-#define RTC_MODE0_SYNCBUSY_COMP1_Pos 6            /**< \brief (RTC_MODE0_SYNCBUSY) COMP 1 Register Busy */
-#define RTC_MODE0_SYNCBUSY_COMP1    (_U_(1) << RTC_MODE0_SYNCBUSY_COMP1_Pos)
-#define RTC_MODE0_SYNCBUSY_COMP_Pos 5            /**< \brief (RTC_MODE0_SYNCBUSY) COMP x Register Busy */
-#define RTC_MODE0_SYNCBUSY_COMP_Msk (_U_(0x3) << RTC_MODE0_SYNCBUSY_COMP_Pos)
-#define RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))
-#define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos 15           /**< \brief (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy */
-#define RTC_MODE0_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)
-#define RTC_MODE0_SYNCBUSY_GP0_Pos  16           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP0      (_U_(1) << RTC_MODE0_SYNCBUSY_GP0_Pos)
-#define RTC_MODE0_SYNCBUSY_GP1_Pos  17           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP1      (_U_(1) << RTC_MODE0_SYNCBUSY_GP1_Pos)
-#define RTC_MODE0_SYNCBUSY_GP2_Pos  18           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 2 Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP2      (_U_(1) << RTC_MODE0_SYNCBUSY_GP2_Pos)
-#define RTC_MODE0_SYNCBUSY_GP3_Pos  19           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose 3 Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP3      (_U_(1) << RTC_MODE0_SYNCBUSY_GP3_Pos)
-#define RTC_MODE0_SYNCBUSY_GP_Pos   16           /**< \brief (RTC_MODE0_SYNCBUSY) General Purpose x Register Busy */
-#define RTC_MODE0_SYNCBUSY_GP_Msk   (_U_(0xF) << RTC_MODE0_SYNCBUSY_GP_Pos)
-#define RTC_MODE0_SYNCBUSY_GP(value) (RTC_MODE0_SYNCBUSY_GP_Msk & ((value) << RTC_MODE0_SYNCBUSY_GP_Pos))
-#define RTC_MODE0_SYNCBUSY_MASK     _U_(0x000F806F) /**< \brief (RTC_MODE0_SYNCBUSY) MASK Register */
-
-/* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/  32) MODE1 MODE1 Synchronization Busy Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Bit Busy            */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Bit Busy                    */
-    uint32_t FREQCORR:1;       /*!< bit:      2  FREQCORR Register Busy             */
-    uint32_t COUNT:1;          /*!< bit:      3  COUNT Register Busy                */
-    uint32_t PER:1;            /*!< bit:      4  PER Register Busy                  */
-    uint32_t COMP0:1;          /*!< bit:      5  COMP 0 Register Busy               */
-    uint32_t COMP1:1;          /*!< bit:      6  COMP 1 Register Busy               */
-    uint32_t COMP2:1;          /*!< bit:      7  COMP 2 Register Busy               */
-    uint32_t COMP3:1;          /*!< bit:      8  COMP 3 Register Busy               */
-    uint32_t :6;               /*!< bit:  9..14  Reserved                           */
-    uint32_t COUNTSYNC:1;      /*!< bit:     15  Count Synchronization Enable Bit Busy */
-    uint32_t GP0:1;            /*!< bit:     16  General Purpose 0 Register Busy    */
-    uint32_t GP1:1;            /*!< bit:     17  General Purpose 1 Register Busy    */
-    uint32_t GP2:1;            /*!< bit:     18  General Purpose 2 Register Busy    */
-    uint32_t GP3:1;            /*!< bit:     19  General Purpose 3 Register Busy    */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
-    uint32_t COMP:4;           /*!< bit:  5.. 8  COMP x Register Busy               */
-    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GP:4;             /*!< bit: 16..19  General Purpose x Register Busy    */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_SYNCBUSY_OFFSET   0x10         /**< \brief (RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status */
-#define RTC_MODE1_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status */
-
-#define RTC_MODE1_SYNCBUSY_SWRST_Pos 0            /**< \brief (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy */
-#define RTC_MODE1_SYNCBUSY_SWRST    (_U_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)
-#define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1            /**< \brief (RTC_MODE1_SYNCBUSY) Enable Bit Busy */
-#define RTC_MODE1_SYNCBUSY_ENABLE   (_U_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)
-#define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2            /**< \brief (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy */
-#define RTC_MODE1_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)
-#define RTC_MODE1_SYNCBUSY_COUNT_Pos 3            /**< \brief (RTC_MODE1_SYNCBUSY) COUNT Register Busy */
-#define RTC_MODE1_SYNCBUSY_COUNT    (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)
-#define RTC_MODE1_SYNCBUSY_PER_Pos  4            /**< \brief (RTC_MODE1_SYNCBUSY) PER Register Busy */
-#define RTC_MODE1_SYNCBUSY_PER      (_U_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP0_Pos 5            /**< \brief (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP0    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP1_Pos 6            /**< \brief (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP1    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP2_Pos 7            /**< \brief (RTC_MODE1_SYNCBUSY) COMP 2 Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP2    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP2_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP3_Pos 8            /**< \brief (RTC_MODE1_SYNCBUSY) COMP 3 Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP3    (_U_(1) << RTC_MODE1_SYNCBUSY_COMP3_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP_Pos 5            /**< \brief (RTC_MODE1_SYNCBUSY) COMP x Register Busy */
-#define RTC_MODE1_SYNCBUSY_COMP_Msk (_U_(0xF) << RTC_MODE1_SYNCBUSY_COMP_Pos)
-#define RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))
-#define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos 15           /**< \brief (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy */
-#define RTC_MODE1_SYNCBUSY_COUNTSYNC (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)
-#define RTC_MODE1_SYNCBUSY_GP0_Pos  16           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP0      (_U_(1) << RTC_MODE1_SYNCBUSY_GP0_Pos)
-#define RTC_MODE1_SYNCBUSY_GP1_Pos  17           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP1      (_U_(1) << RTC_MODE1_SYNCBUSY_GP1_Pos)
-#define RTC_MODE1_SYNCBUSY_GP2_Pos  18           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 2 Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP2      (_U_(1) << RTC_MODE1_SYNCBUSY_GP2_Pos)
-#define RTC_MODE1_SYNCBUSY_GP3_Pos  19           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose 3 Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP3      (_U_(1) << RTC_MODE1_SYNCBUSY_GP3_Pos)
-#define RTC_MODE1_SYNCBUSY_GP_Pos   16           /**< \brief (RTC_MODE1_SYNCBUSY) General Purpose x Register Busy */
-#define RTC_MODE1_SYNCBUSY_GP_Msk   (_U_(0xF) << RTC_MODE1_SYNCBUSY_GP_Pos)
-#define RTC_MODE1_SYNCBUSY_GP(value) (RTC_MODE1_SYNCBUSY_GP_Msk & ((value) << RTC_MODE1_SYNCBUSY_GP_Pos))
-#define RTC_MODE1_SYNCBUSY_MASK     _U_(0x000F81FF) /**< \brief (RTC_MODE1_SYNCBUSY) MASK Register */
-
-/* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/  32) MODE2 MODE2 Synchronization Busy Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Bit Busy            */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Bit Busy                    */
-    uint32_t FREQCORR:1;       /*!< bit:      2  FREQCORR Register Busy             */
-    uint32_t CLOCK:1;          /*!< bit:      3  CLOCK Register Busy                */
-    uint32_t :1;               /*!< bit:      4  Reserved                           */
-    uint32_t ALARM0:1;         /*!< bit:      5  ALARM 0 Register Busy              */
-    uint32_t ALARM1:1;         /*!< bit:      6  ALARM 1 Register Busy              */
-    uint32_t :4;               /*!< bit:  7..10  Reserved                           */
-    uint32_t MASK0:1;          /*!< bit:     11  MASK 0 Register Busy               */
-    uint32_t MASK1:1;          /*!< bit:     12  MASK 1 Register Busy               */
-    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
-    uint32_t CLOCKSYNC:1;      /*!< bit:     15  Clock Synchronization Enable Bit Busy */
-    uint32_t GP0:1;            /*!< bit:     16  General Purpose 0 Register Busy    */
-    uint32_t GP1:1;            /*!< bit:     17  General Purpose 1 Register Busy    */
-    uint32_t GP2:1;            /*!< bit:     18  General Purpose 2 Register Busy    */
-    uint32_t GP3:1;            /*!< bit:     19  General Purpose 3 Register Busy    */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
-    uint32_t ALARM:2;          /*!< bit:  5.. 6  ALARM x Register Busy              */
-    uint32_t :4;               /*!< bit:  7..10  Reserved                           */
-    uint32_t MASK:2;           /*!< bit: 11..12  MASK x Register Busy               */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t GP:4;             /*!< bit: 16..19  General Purpose x Register Busy    */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_SYNCBUSY_OFFSET   0x10         /**< \brief (RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status */
-#define RTC_MODE2_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status */
-
-#define RTC_MODE2_SYNCBUSY_SWRST_Pos 0            /**< \brief (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy */
-#define RTC_MODE2_SYNCBUSY_SWRST    (_U_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)
-#define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1            /**< \brief (RTC_MODE2_SYNCBUSY) Enable Bit Busy */
-#define RTC_MODE2_SYNCBUSY_ENABLE   (_U_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)
-#define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2            /**< \brief (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy */
-#define RTC_MODE2_SYNCBUSY_FREQCORR (_U_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)
-#define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3            /**< \brief (RTC_MODE2_SYNCBUSY) CLOCK Register Busy */
-#define RTC_MODE2_SYNCBUSY_CLOCK    (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)
-#define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5            /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy */
-#define RTC_MODE2_SYNCBUSY_ALARM0   (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)
-#define RTC_MODE2_SYNCBUSY_ALARM1_Pos 6            /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 1 Register Busy */
-#define RTC_MODE2_SYNCBUSY_ALARM1   (_U_(1) << RTC_MODE2_SYNCBUSY_ALARM1_Pos)
-#define RTC_MODE2_SYNCBUSY_ALARM_Pos 5            /**< \brief (RTC_MODE2_SYNCBUSY) ALARM x Register Busy */
-#define RTC_MODE2_SYNCBUSY_ALARM_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_ALARM_Pos)
-#define RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))
-#define RTC_MODE2_SYNCBUSY_MASK0_Pos 11           /**< \brief (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy */
-#define RTC_MODE2_SYNCBUSY_MASK0    (_U_(1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)
-#define RTC_MODE2_SYNCBUSY_MASK1_Pos 12           /**< \brief (RTC_MODE2_SYNCBUSY) MASK 1 Register Busy */
-#define RTC_MODE2_SYNCBUSY_MASK1    (_U_(1) << RTC_MODE2_SYNCBUSY_MASK1_Pos)
-#define RTC_MODE2_SYNCBUSY_MASK_Pos 11           /**< \brief (RTC_MODE2_SYNCBUSY) MASK x Register Busy */
-#define RTC_MODE2_SYNCBUSY_MASK_Msk (_U_(0x3) << RTC_MODE2_SYNCBUSY_MASK_Pos)
-#define RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))
-#define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos 15           /**< \brief (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy */
-#define RTC_MODE2_SYNCBUSY_CLOCKSYNC (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)
-#define RTC_MODE2_SYNCBUSY_GP0_Pos  16           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP0      (_U_(1) << RTC_MODE2_SYNCBUSY_GP0_Pos)
-#define RTC_MODE2_SYNCBUSY_GP1_Pos  17           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP1      (_U_(1) << RTC_MODE2_SYNCBUSY_GP1_Pos)
-#define RTC_MODE2_SYNCBUSY_GP2_Pos  18           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 2 Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP2      (_U_(1) << RTC_MODE2_SYNCBUSY_GP2_Pos)
-#define RTC_MODE2_SYNCBUSY_GP3_Pos  19           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose 3 Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP3      (_U_(1) << RTC_MODE2_SYNCBUSY_GP3_Pos)
-#define RTC_MODE2_SYNCBUSY_GP_Pos   16           /**< \brief (RTC_MODE2_SYNCBUSY) General Purpose x Register Busy */
-#define RTC_MODE2_SYNCBUSY_GP_Msk   (_U_(0xF) << RTC_MODE2_SYNCBUSY_GP_Pos)
-#define RTC_MODE2_SYNCBUSY_GP(value) (RTC_MODE2_SYNCBUSY_GP_Msk & ((value) << RTC_MODE2_SYNCBUSY_GP_Pos))
-#define RTC_MODE2_SYNCBUSY_MASK_    _U_(0x000F986F) /**< \brief (RTC_MODE2_SYNCBUSY) MASK Register */
-
-/* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W  8) Frequency Correction -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  VALUE:7;          /*!< bit:  0.. 6  Correction Value                   */
-    uint8_t  SIGN:1;           /*!< bit:      7  Correction Sign                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_FREQCORR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_FREQCORR_OFFSET         0x14         /**< \brief (RTC_FREQCORR offset) Frequency Correction */
-#define RTC_FREQCORR_RESETVALUE     _U_(0x00)    /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
-
-#define RTC_FREQCORR_VALUE_Pos      0            /**< \brief (RTC_FREQCORR) Correction Value */
-#define RTC_FREQCORR_VALUE_Msk      (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos)
-#define RTC_FREQCORR_VALUE(value)   (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
-#define RTC_FREQCORR_SIGN_Pos       7            /**< \brief (RTC_FREQCORR) Correction Sign */
-#define RTC_FREQCORR_SIGN           (_U_(0x1) << RTC_FREQCORR_SIGN_Pos)
-#define RTC_FREQCORR_MASK           _U_(0xFF)    /**< \brief (RTC_FREQCORR) MASK Register */
-
-/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_COUNT_OFFSET      0x18         /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
-#define RTC_MODE0_COUNT_RESETVALUE  _U_(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
-
-#define RTC_MODE0_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE0_COUNT) Counter Value */
-#define RTC_MODE0_COUNT_COUNT_Msk   (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)
-#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
-#define RTC_MODE0_COUNT_MASK        _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */
-
-/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_COUNT_OFFSET      0x18         /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
-#define RTC_MODE1_COUNT_RESETVALUE  _U_(0x0000)  /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
-
-#define RTC_MODE1_COUNT_COUNT_Pos   0            /**< \brief (RTC_MODE1_COUNT) Counter Value */
-#define RTC_MODE1_COUNT_COUNT_Msk   (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)
-#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
-#define RTC_MODE1_COUNT_MASK        _U_(0xFFFF)  /**< \brief (RTC_MODE1_COUNT) MASK Register */
-
-/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
-    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
-    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
-    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
-    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
-    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_CLOCK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_CLOCK_OFFSET      0x18         /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
-#define RTC_MODE2_CLOCK_RESETVALUE  _U_(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
-
-#define RTC_MODE2_CLOCK_SECOND_Pos  0            /**< \brief (RTC_MODE2_CLOCK) Second */
-#define RTC_MODE2_CLOCK_SECOND_Msk  (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)
-#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
-#define RTC_MODE2_CLOCK_MINUTE_Pos  6            /**< \brief (RTC_MODE2_CLOCK) Minute */
-#define RTC_MODE2_CLOCK_MINUTE_Msk  (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)
-#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
-#define RTC_MODE2_CLOCK_HOUR_Pos    12           /**< \brief (RTC_MODE2_CLOCK) Hour */
-#define RTC_MODE2_CLOCK_HOUR_Msk    (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)
-#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
-#define   RTC_MODE2_CLOCK_HOUR_AM_Val     _U_(0x0)   /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
-#define   RTC_MODE2_CLOCK_HOUR_PM_Val     _U_(0x10)   /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
-#define RTC_MODE2_CLOCK_HOUR_AM     (RTC_MODE2_CLOCK_HOUR_AM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
-#define RTC_MODE2_CLOCK_HOUR_PM     (RTC_MODE2_CLOCK_HOUR_PM_Val   << RTC_MODE2_CLOCK_HOUR_Pos)
-#define RTC_MODE2_CLOCK_DAY_Pos     17           /**< \brief (RTC_MODE2_CLOCK) Day */
-#define RTC_MODE2_CLOCK_DAY_Msk     (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)
-#define RTC_MODE2_CLOCK_DAY(value)  (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
-#define RTC_MODE2_CLOCK_MONTH_Pos   22           /**< \brief (RTC_MODE2_CLOCK) Month */
-#define RTC_MODE2_CLOCK_MONTH_Msk   (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)
-#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
-#define RTC_MODE2_CLOCK_YEAR_Pos    26           /**< \brief (RTC_MODE2_CLOCK) Year */
-#define RTC_MODE2_CLOCK_YEAR_Msk    (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)
-#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
-#define RTC_MODE2_CLOCK_MASK        _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */
-
-/* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PER:16;           /*!< bit:  0..15  Counter Period                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_PER_OFFSET        0x1C         /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
-#define RTC_MODE1_PER_RESETVALUE    _U_(0x0000)  /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
-
-#define RTC_MODE1_PER_PER_Pos       0            /**< \brief (RTC_MODE1_PER) Counter Period */
-#define RTC_MODE1_PER_PER_Msk       (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos)
-#define RTC_MODE1_PER_PER(value)    (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
-#define RTC_MODE1_PER_MASK          _U_(0xFFFF)  /**< \brief (RTC_MODE1_PER) MASK Register */
-
-/* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t COMP:32;          /*!< bit:  0..31  Compare Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_COMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_COMP_OFFSET       0x20         /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
-#define RTC_MODE0_COMP_RESETVALUE   _U_(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
-
-#define RTC_MODE0_COMP_COMP_Pos     0            /**< \brief (RTC_MODE0_COMP) Compare Value */
-#define RTC_MODE0_COMP_COMP_Msk     (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)
-#define RTC_MODE0_COMP_COMP(value)  (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
-#define RTC_MODE0_COMP_MASK         _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */
-
-/* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t COMP:16;          /*!< bit:  0..15  Compare Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_COMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_COMP_OFFSET       0x20         /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
-#define RTC_MODE1_COMP_RESETVALUE   _U_(0x0000)  /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
-
-#define RTC_MODE1_COMP_COMP_Pos     0            /**< \brief (RTC_MODE1_COMP) Compare Value */
-#define RTC_MODE1_COMP_COMP_Msk     (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)
-#define RTC_MODE1_COMP_COMP(value)  (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
-#define RTC_MODE1_COMP_MASK         _U_(0xFFFF)  /**< \brief (RTC_MODE1_COMP) MASK Register */
-
-/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second                             */
-    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute                             */
-    uint32_t HOUR:5;           /*!< bit: 12..16  Hour                               */
-    uint32_t DAY:5;            /*!< bit: 17..21  Day                                */
-    uint32_t MONTH:4;          /*!< bit: 22..25  Month                              */
-    uint32_t YEAR:6;           /*!< bit: 26..31  Year                               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_ALARM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_ALARM_OFFSET      0x20         /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
-#define RTC_MODE2_ALARM_RESETVALUE  _U_(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
-
-#define RTC_MODE2_ALARM_SECOND_Pos  0            /**< \brief (RTC_MODE2_ALARM) Second */
-#define RTC_MODE2_ALARM_SECOND_Msk  (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)
-#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
-#define RTC_MODE2_ALARM_MINUTE_Pos  6            /**< \brief (RTC_MODE2_ALARM) Minute */
-#define RTC_MODE2_ALARM_MINUTE_Msk  (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)
-#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
-#define RTC_MODE2_ALARM_HOUR_Pos    12           /**< \brief (RTC_MODE2_ALARM) Hour */
-#define RTC_MODE2_ALARM_HOUR_Msk    (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)
-#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
-#define   RTC_MODE2_ALARM_HOUR_AM_Val     _U_(0x0)   /**< \brief (RTC_MODE2_ALARM) Morning hour */
-#define   RTC_MODE2_ALARM_HOUR_PM_Val     _U_(0x10)   /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
-#define RTC_MODE2_ALARM_HOUR_AM     (RTC_MODE2_ALARM_HOUR_AM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
-#define RTC_MODE2_ALARM_HOUR_PM     (RTC_MODE2_ALARM_HOUR_PM_Val   << RTC_MODE2_ALARM_HOUR_Pos)
-#define RTC_MODE2_ALARM_DAY_Pos     17           /**< \brief (RTC_MODE2_ALARM) Day */
-#define RTC_MODE2_ALARM_DAY_Msk     (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)
-#define RTC_MODE2_ALARM_DAY(value)  (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
-#define RTC_MODE2_ALARM_MONTH_Pos   22           /**< \brief (RTC_MODE2_ALARM) Month */
-#define RTC_MODE2_ALARM_MONTH_Msk   (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)
-#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
-#define RTC_MODE2_ALARM_YEAR_Pos    26           /**< \brief (RTC_MODE2_ALARM) Year */
-#define RTC_MODE2_ALARM_YEAR_Msk    (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)
-#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
-#define RTC_MODE2_ALARM_MASK        _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */
-
-/* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W  8) MODE2 MODE2_ALARM Alarm n Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SEL:3;            /*!< bit:  0.. 2  Alarm Mask Selection               */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} RTC_MODE2_MASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_MASK_OFFSET       0x24         /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
-#define RTC_MODE2_MASK_RESETVALUE   _U_(0x00)    /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
-
-#define RTC_MODE2_MASK_SEL_Pos      0            /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
-#define RTC_MODE2_MASK_SEL_Msk      (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL(value)   (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
-#define   RTC_MODE2_MASK_SEL_OFF_Val      _U_(0x0)   /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
-#define   RTC_MODE2_MASK_SEL_SS_Val       _U_(0x1)   /**< \brief (RTC_MODE2_MASK) Match seconds only */
-#define   RTC_MODE2_MASK_SEL_MMSS_Val     _U_(0x2)   /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
-#define   RTC_MODE2_MASK_SEL_HHMMSS_Val   _U_(0x3)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
-#define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
-#define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
-#define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6)   /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
-#define RTC_MODE2_MASK_SEL_OFF      (RTC_MODE2_MASK_SEL_OFF_Val    << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_SS       (RTC_MODE2_MASK_SEL_SS_Val     << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_MMSS     (RTC_MODE2_MASK_SEL_MMSS_Val   << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_HHMMSS   (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
-#define RTC_MODE2_MASK_MASK         _U_(0x07)    /**< \brief (RTC_MODE2_MASK) MASK Register */
-
-/* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t GP:32;            /*!< bit:  0..31  General Purpose                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_GP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_GP_OFFSET               0x40         /**< \brief (RTC_GP offset) General Purpose */
-#define RTC_GP_RESETVALUE           _U_(0x00000000) /**< \brief (RTC_GP reset_value) General Purpose */
-
-#define RTC_GP_GP_Pos               0            /**< \brief (RTC_GP) General Purpose */
-#define RTC_GP_GP_Msk               (_U_(0xFFFFFFFF) << RTC_GP_GP_Pos)
-#define RTC_GP_GP(value)            (RTC_GP_GP_Msk & ((value) << RTC_GP_GP_Pos))
-#define RTC_GP_MASK                 _U_(0xFFFFFFFF) /**< \brief (RTC_GP) MASK Register */
-
-/* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t IN0ACT:2;         /*!< bit:  0.. 1  Tamper Input 0 Action              */
-    uint32_t IN1ACT:2;         /*!< bit:  2.. 3  Tamper Input 1 Action              */
-    uint32_t IN2ACT:2;         /*!< bit:  4.. 5  Tamper Input 2 Action              */
-    uint32_t IN3ACT:2;         /*!< bit:  6.. 7  Tamper Input 3 Action              */
-    uint32_t IN4ACT:2;         /*!< bit:  8.. 9  Tamper Input 4 Action              */
-    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
-    uint32_t TAMLVL0:1;        /*!< bit:     16  Tamper Level Select 0              */
-    uint32_t TAMLVL1:1;        /*!< bit:     17  Tamper Level Select 1              */
-    uint32_t TAMLVL2:1;        /*!< bit:     18  Tamper Level Select 2              */
-    uint32_t TAMLVL3:1;        /*!< bit:     19  Tamper Level Select 3              */
-    uint32_t TAMLVL4:1;        /*!< bit:     20  Tamper Level Select 4              */
-    uint32_t :3;               /*!< bit: 21..23  Reserved                           */
-    uint32_t DEBNC0:1;         /*!< bit:     24  Debouncer Enable 0                 */
-    uint32_t DEBNC1:1;         /*!< bit:     25  Debouncer Enable 1                 */
-    uint32_t DEBNC2:1;         /*!< bit:     26  Debouncer Enable 2                 */
-    uint32_t DEBNC3:1;         /*!< bit:     27  Debouncer Enable 3                 */
-    uint32_t DEBNC4:1;         /*!< bit:     28  Debouncer Enable 4                 */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t TAMLVL:5;         /*!< bit: 16..20  Tamper Level Select x              */
-    uint32_t :3;               /*!< bit: 21..23  Reserved                           */
-    uint32_t DEBNC:5;          /*!< bit: 24..28  Debouncer Enable x                 */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_TAMPCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_TAMPCTRL_OFFSET         0x60         /**< \brief (RTC_TAMPCTRL offset) Tamper Control */
-#define RTC_TAMPCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (RTC_TAMPCTRL reset_value) Tamper Control */
-
-#define RTC_TAMPCTRL_IN0ACT_Pos     0            /**< \brief (RTC_TAMPCTRL) Tamper Input 0 Action */
-#define RTC_TAMPCTRL_IN0ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN0ACT(value)  (RTC_TAMPCTRL_IN0ACT_Msk & ((value) << RTC_TAMPCTRL_IN0ACT_Pos))
-#define   RTC_TAMPCTRL_IN0ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define   RTC_TAMPCTRL_IN0ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define   RTC_TAMPCTRL_IN0ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define   RTC_TAMPCTRL_IN0ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN0 to OUT */
-#define RTC_TAMPCTRL_IN0ACT_OFF     (RTC_TAMPCTRL_IN0ACT_OFF_Val   << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN0ACT_WAKE    (RTC_TAMPCTRL_IN0ACT_WAKE_Val  << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN0ACT_CAPTURE (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN0ACT_ACTL    (RTC_TAMPCTRL_IN0ACT_ACTL_Val  << RTC_TAMPCTRL_IN0ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT_Pos     2            /**< \brief (RTC_TAMPCTRL) Tamper Input 1 Action */
-#define RTC_TAMPCTRL_IN1ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT(value)  (RTC_TAMPCTRL_IN1ACT_Msk & ((value) << RTC_TAMPCTRL_IN1ACT_Pos))
-#define   RTC_TAMPCTRL_IN1ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define   RTC_TAMPCTRL_IN1ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define   RTC_TAMPCTRL_IN1ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define   RTC_TAMPCTRL_IN1ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN1 to OUT */
-#define RTC_TAMPCTRL_IN1ACT_OFF     (RTC_TAMPCTRL_IN1ACT_OFF_Val   << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT_WAKE    (RTC_TAMPCTRL_IN1ACT_WAKE_Val  << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT_CAPTURE (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN1ACT_ACTL    (RTC_TAMPCTRL_IN1ACT_ACTL_Val  << RTC_TAMPCTRL_IN1ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT_Pos     4            /**< \brief (RTC_TAMPCTRL) Tamper Input 2 Action */
-#define RTC_TAMPCTRL_IN2ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT(value)  (RTC_TAMPCTRL_IN2ACT_Msk & ((value) << RTC_TAMPCTRL_IN2ACT_Pos))
-#define   RTC_TAMPCTRL_IN2ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define   RTC_TAMPCTRL_IN2ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define   RTC_TAMPCTRL_IN2ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define   RTC_TAMPCTRL_IN2ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN2 to OUT */
-#define RTC_TAMPCTRL_IN2ACT_OFF     (RTC_TAMPCTRL_IN2ACT_OFF_Val   << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT_WAKE    (RTC_TAMPCTRL_IN2ACT_WAKE_Val  << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT_CAPTURE (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN2ACT_ACTL    (RTC_TAMPCTRL_IN2ACT_ACTL_Val  << RTC_TAMPCTRL_IN2ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT_Pos     6            /**< \brief (RTC_TAMPCTRL) Tamper Input 3 Action */
-#define RTC_TAMPCTRL_IN3ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT(value)  (RTC_TAMPCTRL_IN3ACT_Msk & ((value) << RTC_TAMPCTRL_IN3ACT_Pos))
-#define   RTC_TAMPCTRL_IN3ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define   RTC_TAMPCTRL_IN3ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define   RTC_TAMPCTRL_IN3ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define   RTC_TAMPCTRL_IN3ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN3 to OUT */
-#define RTC_TAMPCTRL_IN3ACT_OFF     (RTC_TAMPCTRL_IN3ACT_OFF_Val   << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT_WAKE    (RTC_TAMPCTRL_IN3ACT_WAKE_Val  << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT_CAPTURE (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN3ACT_ACTL    (RTC_TAMPCTRL_IN3ACT_ACTL_Val  << RTC_TAMPCTRL_IN3ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT_Pos     8            /**< \brief (RTC_TAMPCTRL) Tamper Input 4 Action */
-#define RTC_TAMPCTRL_IN4ACT_Msk     (_U_(0x3) << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT(value)  (RTC_TAMPCTRL_IN4ACT_Msk & ((value) << RTC_TAMPCTRL_IN4ACT_Pos))
-#define   RTC_TAMPCTRL_IN4ACT_OFF_Val     _U_(0x0)   /**< \brief (RTC_TAMPCTRL) Off (Disabled) */
-#define   RTC_TAMPCTRL_IN4ACT_WAKE_Val    _U_(0x1)   /**< \brief (RTC_TAMPCTRL) Wake without timestamp */
-#define   RTC_TAMPCTRL_IN4ACT_CAPTURE_Val _U_(0x2)   /**< \brief (RTC_TAMPCTRL) Capture timestamp */
-#define   RTC_TAMPCTRL_IN4ACT_ACTL_Val    _U_(0x3)   /**< \brief (RTC_TAMPCTRL) Compare IN4 to OUT */
-#define RTC_TAMPCTRL_IN4ACT_OFF     (RTC_TAMPCTRL_IN4ACT_OFF_Val   << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT_WAKE    (RTC_TAMPCTRL_IN4ACT_WAKE_Val  << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT_CAPTURE (RTC_TAMPCTRL_IN4ACT_CAPTURE_Val << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_IN4ACT_ACTL    (RTC_TAMPCTRL_IN4ACT_ACTL_Val  << RTC_TAMPCTRL_IN4ACT_Pos)
-#define RTC_TAMPCTRL_TAMLVL0_Pos    16           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 0 */
-#define RTC_TAMPCTRL_TAMLVL0        (_U_(1) << RTC_TAMPCTRL_TAMLVL0_Pos)
-#define RTC_TAMPCTRL_TAMLVL1_Pos    17           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 1 */
-#define RTC_TAMPCTRL_TAMLVL1        (_U_(1) << RTC_TAMPCTRL_TAMLVL1_Pos)
-#define RTC_TAMPCTRL_TAMLVL2_Pos    18           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 2 */
-#define RTC_TAMPCTRL_TAMLVL2        (_U_(1) << RTC_TAMPCTRL_TAMLVL2_Pos)
-#define RTC_TAMPCTRL_TAMLVL3_Pos    19           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 3 */
-#define RTC_TAMPCTRL_TAMLVL3        (_U_(1) << RTC_TAMPCTRL_TAMLVL3_Pos)
-#define RTC_TAMPCTRL_TAMLVL4_Pos    20           /**< \brief (RTC_TAMPCTRL) Tamper Level Select 4 */
-#define RTC_TAMPCTRL_TAMLVL4        (_U_(1) << RTC_TAMPCTRL_TAMLVL4_Pos)
-#define RTC_TAMPCTRL_TAMLVL_Pos     16           /**< \brief (RTC_TAMPCTRL) Tamper Level Select x */
-#define RTC_TAMPCTRL_TAMLVL_Msk     (_U_(0x1F) << RTC_TAMPCTRL_TAMLVL_Pos)
-#define RTC_TAMPCTRL_TAMLVL(value)  (RTC_TAMPCTRL_TAMLVL_Msk & ((value) << RTC_TAMPCTRL_TAMLVL_Pos))
-#define RTC_TAMPCTRL_DEBNC0_Pos     24           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 0 */
-#define RTC_TAMPCTRL_DEBNC0         (_U_(1) << RTC_TAMPCTRL_DEBNC0_Pos)
-#define RTC_TAMPCTRL_DEBNC1_Pos     25           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 1 */
-#define RTC_TAMPCTRL_DEBNC1         (_U_(1) << RTC_TAMPCTRL_DEBNC1_Pos)
-#define RTC_TAMPCTRL_DEBNC2_Pos     26           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 2 */
-#define RTC_TAMPCTRL_DEBNC2         (_U_(1) << RTC_TAMPCTRL_DEBNC2_Pos)
-#define RTC_TAMPCTRL_DEBNC3_Pos     27           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 3 */
-#define RTC_TAMPCTRL_DEBNC3         (_U_(1) << RTC_TAMPCTRL_DEBNC3_Pos)
-#define RTC_TAMPCTRL_DEBNC4_Pos     28           /**< \brief (RTC_TAMPCTRL) Debouncer Enable 4 */
-#define RTC_TAMPCTRL_DEBNC4         (_U_(1) << RTC_TAMPCTRL_DEBNC4_Pos)
-#define RTC_TAMPCTRL_DEBNC_Pos      24           /**< \brief (RTC_TAMPCTRL) Debouncer Enable x */
-#define RTC_TAMPCTRL_DEBNC_Msk      (_U_(0x1F) << RTC_TAMPCTRL_DEBNC_Pos)
-#define RTC_TAMPCTRL_DEBNC(value)   (RTC_TAMPCTRL_DEBNC_Msk & ((value) << RTC_TAMPCTRL_DEBNC_Pos))
-#define RTC_TAMPCTRL_MASK           _U_(0x1F1F03FF) /**< \brief (RTC_TAMPCTRL) MASK Register */
-
-/* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) (R/  32) MODE0 MODE0 Timestamp -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t COUNT:32;         /*!< bit:  0..31  Count Timestamp Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE0_TIMESTAMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE0_TIMESTAMP_OFFSET  0x64         /**< \brief (RTC_MODE0_TIMESTAMP offset) MODE0 Timestamp */
-#define RTC_MODE0_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_TIMESTAMP reset_value) MODE0 Timestamp */
-
-#define RTC_MODE0_TIMESTAMP_COUNT_Pos 0            /**< \brief (RTC_MODE0_TIMESTAMP) Count Timestamp Value */
-#define RTC_MODE0_TIMESTAMP_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos)
-#define RTC_MODE0_TIMESTAMP_COUNT(value) (RTC_MODE0_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE0_TIMESTAMP_COUNT_Pos))
-#define RTC_MODE0_TIMESTAMP_MASK    _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_TIMESTAMP) MASK Register */
-
-/* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) (R/  32) MODE1 MODE1 Timestamp -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t COUNT:16;         /*!< bit:  0..15  Count Timestamp Value              */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE1_TIMESTAMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE1_TIMESTAMP_OFFSET  0x64         /**< \brief (RTC_MODE1_TIMESTAMP offset) MODE1 Timestamp */
-#define RTC_MODE1_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE1_TIMESTAMP reset_value) MODE1 Timestamp */
-
-#define RTC_MODE1_TIMESTAMP_COUNT_Pos 0            /**< \brief (RTC_MODE1_TIMESTAMP) Count Timestamp Value */
-#define RTC_MODE1_TIMESTAMP_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)
-#define RTC_MODE1_TIMESTAMP_COUNT(value) (RTC_MODE1_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE1_TIMESTAMP_COUNT_Pos))
-#define RTC_MODE1_TIMESTAMP_MASK    _U_(0x0000FFFF) /**< \brief (RTC_MODE1_TIMESTAMP) MASK Register */
-
-/* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) (R/  32) MODE2 MODE2 Timestamp -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SECOND:6;         /*!< bit:  0.. 5  Second Timestamp Value             */
-    uint32_t MINUTE:6;         /*!< bit:  6..11  Minute Timestamp Value             */
-    uint32_t HOUR:5;           /*!< bit: 12..16  Hour Timestamp Value               */
-    uint32_t DAY:5;            /*!< bit: 17..21  Day Timestamp Value                */
-    uint32_t MONTH:4;          /*!< bit: 22..25  Month Timestamp Value              */
-    uint32_t YEAR:6;           /*!< bit: 26..31  Year Timestamp Value               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_MODE2_TIMESTAMP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_MODE2_TIMESTAMP_OFFSET  0x64         /**< \brief (RTC_MODE2_TIMESTAMP offset) MODE2 Timestamp */
-#define RTC_MODE2_TIMESTAMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_TIMESTAMP reset_value) MODE2 Timestamp */
-
-#define RTC_MODE2_TIMESTAMP_SECOND_Pos 0            /**< \brief (RTC_MODE2_TIMESTAMP) Second Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_SECOND_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)
-#define RTC_MODE2_TIMESTAMP_SECOND(value) (RTC_MODE2_TIMESTAMP_SECOND_Msk & ((value) << RTC_MODE2_TIMESTAMP_SECOND_Pos))
-#define RTC_MODE2_TIMESTAMP_MINUTE_Pos 6            /**< \brief (RTC_MODE2_TIMESTAMP) Minute Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)
-#define RTC_MODE2_TIMESTAMP_MINUTE(value) (RTC_MODE2_TIMESTAMP_MINUTE_Msk & ((value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos))
-#define RTC_MODE2_TIMESTAMP_HOUR_Pos 12           /**< \brief (RTC_MODE2_TIMESTAMP) Hour Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_HOUR_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)
-#define RTC_MODE2_TIMESTAMP_HOUR(value) (RTC_MODE2_TIMESTAMP_HOUR_Msk & ((value) << RTC_MODE2_TIMESTAMP_HOUR_Pos))
-#define   RTC_MODE2_TIMESTAMP_HOUR_AM_Val _U_(0x0)   /**< \brief (RTC_MODE2_TIMESTAMP) AM when CLKREP in 12-hour */
-#define   RTC_MODE2_TIMESTAMP_HOUR_PM_Val _U_(0x10)   /**< \brief (RTC_MODE2_TIMESTAMP) PM when CLKREP in 12-hour */
-#define RTC_MODE2_TIMESTAMP_HOUR_AM (RTC_MODE2_TIMESTAMP_HOUR_AM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
-#define RTC_MODE2_TIMESTAMP_HOUR_PM (RTC_MODE2_TIMESTAMP_HOUR_PM_Val << RTC_MODE2_TIMESTAMP_HOUR_Pos)
-#define RTC_MODE2_TIMESTAMP_DAY_Pos 17           /**< \brief (RTC_MODE2_TIMESTAMP) Day Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_DAY_Msk (_U_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)
-#define RTC_MODE2_TIMESTAMP_DAY(value) (RTC_MODE2_TIMESTAMP_DAY_Msk & ((value) << RTC_MODE2_TIMESTAMP_DAY_Pos))
-#define RTC_MODE2_TIMESTAMP_MONTH_Pos 22           /**< \brief (RTC_MODE2_TIMESTAMP) Month Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_MONTH_Msk (_U_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)
-#define RTC_MODE2_TIMESTAMP_MONTH(value) (RTC_MODE2_TIMESTAMP_MONTH_Msk & ((value) << RTC_MODE2_TIMESTAMP_MONTH_Pos))
-#define RTC_MODE2_TIMESTAMP_YEAR_Pos 26           /**< \brief (RTC_MODE2_TIMESTAMP) Year Timestamp Value */
-#define RTC_MODE2_TIMESTAMP_YEAR_Msk (_U_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)
-#define RTC_MODE2_TIMESTAMP_YEAR(value) (RTC_MODE2_TIMESTAMP_YEAR_Msk & ((value) << RTC_MODE2_TIMESTAMP_YEAR_Pos))
-#define RTC_MODE2_TIMESTAMP_MASK    _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_TIMESTAMP) MASK Register */
-
-/* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TAMPID0:1;        /*!< bit:      0  Tamper Input 0 Detected            */
-    uint32_t TAMPID1:1;        /*!< bit:      1  Tamper Input 1 Detected            */
-    uint32_t TAMPID2:1;        /*!< bit:      2  Tamper Input 2 Detected            */
-    uint32_t TAMPID3:1;        /*!< bit:      3  Tamper Input 3 Detected            */
-    uint32_t TAMPID4:1;        /*!< bit:      4  Tamper Input 4 Detected            */
-    uint32_t :26;              /*!< bit:  5..30  Reserved                           */
-    uint32_t TAMPEVT:1;        /*!< bit:     31  Tamper Event Detected              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t TAMPID:5;         /*!< bit:  0.. 4  Tamper Input x Detected            */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_TAMPID_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_TAMPID_OFFSET           0x68         /**< \brief (RTC_TAMPID offset) Tamper ID */
-#define RTC_TAMPID_RESETVALUE       _U_(0x00000000) /**< \brief (RTC_TAMPID reset_value) Tamper ID */
-
-#define RTC_TAMPID_TAMPID0_Pos      0            /**< \brief (RTC_TAMPID) Tamper Input 0 Detected */
-#define RTC_TAMPID_TAMPID0          (_U_(1) << RTC_TAMPID_TAMPID0_Pos)
-#define RTC_TAMPID_TAMPID1_Pos      1            /**< \brief (RTC_TAMPID) Tamper Input 1 Detected */
-#define RTC_TAMPID_TAMPID1          (_U_(1) << RTC_TAMPID_TAMPID1_Pos)
-#define RTC_TAMPID_TAMPID2_Pos      2            /**< \brief (RTC_TAMPID) Tamper Input 2 Detected */
-#define RTC_TAMPID_TAMPID2          (_U_(1) << RTC_TAMPID_TAMPID2_Pos)
-#define RTC_TAMPID_TAMPID3_Pos      3            /**< \brief (RTC_TAMPID) Tamper Input 3 Detected */
-#define RTC_TAMPID_TAMPID3          (_U_(1) << RTC_TAMPID_TAMPID3_Pos)
-#define RTC_TAMPID_TAMPID4_Pos      4            /**< \brief (RTC_TAMPID) Tamper Input 4 Detected */
-#define RTC_TAMPID_TAMPID4          (_U_(1) << RTC_TAMPID_TAMPID4_Pos)
-#define RTC_TAMPID_TAMPID_Pos       0            /**< \brief (RTC_TAMPID) Tamper Input x Detected */
-#define RTC_TAMPID_TAMPID_Msk       (_U_(0x1F) << RTC_TAMPID_TAMPID_Pos)
-#define RTC_TAMPID_TAMPID(value)    (RTC_TAMPID_TAMPID_Msk & ((value) << RTC_TAMPID_TAMPID_Pos))
-#define RTC_TAMPID_TAMPEVT_Pos      31           /**< \brief (RTC_TAMPID) Tamper Event Detected */
-#define RTC_TAMPID_TAMPEVT          (_U_(0x1) << RTC_TAMPID_TAMPEVT_Pos)
-#define RTC_TAMPID_MASK             _U_(0x8000001F) /**< \brief (RTC_TAMPID) MASK Register */
-
-/* -------- RTC_BKUP : (RTC Offset: 0x80) (R/W 32) Backup -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BKUP:32;          /*!< bit:  0..31  Backup                             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} RTC_BKUP_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define RTC_BKUP_OFFSET             0x80         /**< \brief (RTC_BKUP offset) Backup */
-#define RTC_BKUP_RESETVALUE         _U_(0x00000000) /**< \brief (RTC_BKUP reset_value) Backup */
-
-#define RTC_BKUP_BKUP_Pos           0            /**< \brief (RTC_BKUP) Backup */
-#define RTC_BKUP_BKUP_Msk           (_U_(0xFFFFFFFF) << RTC_BKUP_BKUP_Pos)
-#define RTC_BKUP_BKUP(value)        (RTC_BKUP_BKUP_Msk & ((value) << RTC_BKUP_BKUP_Pos))
-#define RTC_BKUP_MASK               _U_(0xFFFFFFFF) /**< \brief (RTC_BKUP) MASK Register */
-
-/** \brief RtcMode2Alarm hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO RTC_MODE2_ALARM_Type      ALARM;       /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
-  __IO RTC_MODE2_MASK_Type       MASK;        /**< \brief Offset: 0x04 (R/W  8) MODE2_ALARM Alarm n Mask */
-       RoReg8                    Reserved1[0x3];
-} RtcMode2Alarm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief RTC_MODE0 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 32-bit Counter with Single 32-bit Compare */
-  __IO RTC_MODE0_CTRLA_Type      CTRLA;       /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */
-  __IO RTC_MODE0_CTRLB_Type      CTRLB;       /**< \brief Offset: 0x02 (R/W 16) MODE0 Control B */
-  __IO RTC_MODE0_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */
-  __IO RTC_MODE0_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */
-  __IO RTC_MODE0_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */
-  __IO RTC_MODE0_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */
-  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0E (R/W  8) Debug Control */
-       RoReg8                    Reserved1[0x1];
-  __I  RTC_MODE0_SYNCBUSY_Type   SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) MODE0 Synchronization Busy Status */
-  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x14 (R/W  8) Frequency Correction */
-       RoReg8                    Reserved2[0x3];
-  __IO RTC_MODE0_COUNT_Type      COUNT;       /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */
-       RoReg8                    Reserved3[0x4];
-  __IO RTC_MODE0_COMP_Type       COMP[2];     /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */
-       RoReg8                    Reserved4[0x18];
-  __IO RTC_GP_Type               GP[4];       /**< \brief Offset: 0x40 (R/W 32) General Purpose */
-       RoReg8                    Reserved5[0x10];
-  __IO RTC_TAMPCTRL_Type         TAMPCTRL;    /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
-  __I  RTC_MODE0_TIMESTAMP_Type  TIMESTAMP;   /**< \brief Offset: 0x64 (R/  32) MODE0 Timestamp */
-  __IO RTC_TAMPID_Type           TAMPID;      /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
-       RoReg8                    Reserved6[0x14];
-  __IO RTC_BKUP_Type             BKUP[8];     /**< \brief Offset: 0x80 (R/W 32) Backup */
-} RtcMode0;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief RTC_MODE1 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 16-bit Counter with Two 16-bit Compares */
-  __IO RTC_MODE1_CTRLA_Type      CTRLA;       /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */
-  __IO RTC_MODE1_CTRLB_Type      CTRLB;       /**< \brief Offset: 0x02 (R/W 16) MODE1 Control B */
-  __IO RTC_MODE1_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */
-  __IO RTC_MODE1_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */
-  __IO RTC_MODE1_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */
-  __IO RTC_MODE1_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */
-  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0E (R/W  8) Debug Control */
-       RoReg8                    Reserved1[0x1];
-  __I  RTC_MODE1_SYNCBUSY_Type   SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) MODE1 Synchronization Busy Status */
-  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x14 (R/W  8) Frequency Correction */
-       RoReg8                    Reserved2[0x3];
-  __IO RTC_MODE1_COUNT_Type      COUNT;       /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */
-       RoReg8                    Reserved3[0x2];
-  __IO RTC_MODE1_PER_Type        PER;         /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */
-       RoReg8                    Reserved4[0x2];
-  __IO RTC_MODE1_COMP_Type       COMP[4];     /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */
-       RoReg8                    Reserved5[0x18];
-  __IO RTC_GP_Type               GP[4];       /**< \brief Offset: 0x40 (R/W 32) General Purpose */
-       RoReg8                    Reserved6[0x10];
-  __IO RTC_TAMPCTRL_Type         TAMPCTRL;    /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
-  __I  RTC_MODE1_TIMESTAMP_Type  TIMESTAMP;   /**< \brief Offset: 0x64 (R/  32) MODE1 Timestamp */
-  __IO RTC_TAMPID_Type           TAMPID;      /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
-       RoReg8                    Reserved7[0x14];
-  __IO RTC_BKUP_Type             BKUP[8];     /**< \brief Offset: 0x80 (R/W 32) Backup */
-} RtcMode1;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief RTC_MODE2 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* Clock/Calendar with Alarm */
-  __IO RTC_MODE2_CTRLA_Type      CTRLA;       /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */
-  __IO RTC_MODE2_CTRLB_Type      CTRLB;       /**< \brief Offset: 0x02 (R/W 16) MODE2 Control B */
-  __IO RTC_MODE2_EVCTRL_Type     EVCTRL;      /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */
-  __IO RTC_MODE2_INTENCLR_Type   INTENCLR;    /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */
-  __IO RTC_MODE2_INTENSET_Type   INTENSET;    /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */
-  __IO RTC_MODE2_INTFLAG_Type    INTFLAG;     /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */
-  __IO RTC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x0E (R/W  8) Debug Control */
-       RoReg8                    Reserved1[0x1];
-  __I  RTC_MODE2_SYNCBUSY_Type   SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) MODE2 Synchronization Busy Status */
-  __IO RTC_FREQCORR_Type         FREQCORR;    /**< \brief Offset: 0x14 (R/W  8) Frequency Correction */
-       RoReg8                    Reserved2[0x3];
-  __IO RTC_MODE2_CLOCK_Type      CLOCK;       /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */
-       RoReg8                    Reserved3[0x4];
-       RtcMode2Alarm             Mode2Alarm[2]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [NUM_OF_ALARMS] */
-       RoReg8                    Reserved4[0x10];
-  __IO RTC_GP_Type               GP[4];       /**< \brief Offset: 0x40 (R/W 32) General Purpose */
-       RoReg8                    Reserved5[0x10];
-  __IO RTC_TAMPCTRL_Type         TAMPCTRL;    /**< \brief Offset: 0x60 (R/W 32) Tamper Control */
-  __I  RTC_MODE2_TIMESTAMP_Type  TIMESTAMP;   /**< \brief Offset: 0x64 (R/  32) MODE2 Timestamp */
-  __IO RTC_TAMPID_Type           TAMPID;      /**< \brief Offset: 0x68 (R/W 32) Tamper ID */
-       RoReg8                    Reserved6[0x14];
-  __IO RTC_BKUP_Type             BKUP[8];     /**< \brief Offset: 0x80 (R/W 32) Backup */
-} RtcMode2;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-       RtcMode0                  MODE0;       /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
-       RtcMode1                  MODE1;       /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
-       RtcMode2                  MODE2;       /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
-} Rtc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_RTC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sdhc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sdhc.h
deleted file mode 100644
index a42b9fc560..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sdhc.h
+++ /dev/null
@@ -1,2599 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for SDHC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SDHC_COMPONENT_
-#define _SAMD51_SDHC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR SDHC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_SDHC SD/MMC Host Controller */
-/*@{*/
-
-#define SDHC_U2011
-#define REV_SDHC                    0x183
-
-/* -------- SDHC_SSAR : (SDHC Offset: 0x000) (R/W 32) SDMA System Address / Argument 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // CMD23 mode
-    uint32_t ARG2:32;          /*!< bit:  0..31  Argument 2                         */
-  } CMD23;                     /*!< Structure used for CMD23                        */
-  struct {
-    uint32_t ADDR:32;          /*!< bit:  0..31  SDMA System Address                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_SSAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_SSAR_OFFSET            0x000        /**< \brief (SDHC_SSAR offset) SDMA System Address / Argument 2 */
-#define SDHC_SSAR_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_SSAR reset_value) SDMA System Address / Argument 2 */
-
-// CMD23 mode
-#define SDHC_SSAR_CMD23_ARG2_Pos    0            /**< \brief (SDHC_SSAR_CMD23) Argument 2 */
-#define SDHC_SSAR_CMD23_ARG2_Msk    (_U_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos)
-#define SDHC_SSAR_CMD23_ARG2(value) (SDHC_SSAR_CMD23_ARG2_Msk & ((value) << SDHC_SSAR_CMD23_ARG2_Pos))
-#define SDHC_SSAR_CMD23_MASK        _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR_CMD23) MASK Register */
-
-#define SDHC_SSAR_ADDR_Pos          0            /**< \brief (SDHC_SSAR) SDMA System Address */
-#define SDHC_SSAR_ADDR_Msk          (_U_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos)
-#define SDHC_SSAR_ADDR(value)       (SDHC_SSAR_ADDR_Msk & ((value) << SDHC_SSAR_ADDR_Pos))
-#define SDHC_SSAR_MASK              _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR) MASK Register */
-
-/* -------- SDHC_BSR : (SDHC Offset: 0x004) (R/W 16) Block Size -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BLOCKSIZE:10;     /*!< bit:  0.. 9  Transfer Block Size                */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t BOUNDARY:3;       /*!< bit: 12..14  SDMA Buffer Boundary               */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_BSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_BSR_OFFSET             0x004        /**< \brief (SDHC_BSR offset) Block Size */
-#define SDHC_BSR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_BSR reset_value) Block Size */
-
-#define SDHC_BSR_BLOCKSIZE_Pos      0            /**< \brief (SDHC_BSR) Transfer Block Size */
-#define SDHC_BSR_BLOCKSIZE_Msk      (_U_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos)
-#define SDHC_BSR_BLOCKSIZE(value)   (SDHC_BSR_BLOCKSIZE_Msk & ((value) << SDHC_BSR_BLOCKSIZE_Pos))
-#define SDHC_BSR_BOUNDARY_Pos       12           /**< \brief (SDHC_BSR) SDMA Buffer Boundary */
-#define SDHC_BSR_BOUNDARY_Msk       (_U_(0x7) << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY(value)    (SDHC_BSR_BOUNDARY_Msk & ((value) << SDHC_BSR_BOUNDARY_Pos))
-#define   SDHC_BSR_BOUNDARY_4K_Val        _U_(0x0)   /**< \brief (SDHC_BSR) 4k bytes */
-#define   SDHC_BSR_BOUNDARY_8K_Val        _U_(0x1)   /**< \brief (SDHC_BSR) 8k bytes */
-#define   SDHC_BSR_BOUNDARY_16K_Val       _U_(0x2)   /**< \brief (SDHC_BSR) 16k bytes */
-#define   SDHC_BSR_BOUNDARY_32K_Val       _U_(0x3)   /**< \brief (SDHC_BSR) 32k bytes */
-#define   SDHC_BSR_BOUNDARY_64K_Val       _U_(0x4)   /**< \brief (SDHC_BSR) 64k bytes */
-#define   SDHC_BSR_BOUNDARY_128K_Val      _U_(0x5)   /**< \brief (SDHC_BSR) 128k bytes */
-#define   SDHC_BSR_BOUNDARY_256K_Val      _U_(0x6)   /**< \brief (SDHC_BSR) 256k bytes */
-#define   SDHC_BSR_BOUNDARY_512K_Val      _U_(0x7)   /**< \brief (SDHC_BSR) 512k bytes */
-#define SDHC_BSR_BOUNDARY_4K        (SDHC_BSR_BOUNDARY_4K_Val      << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_8K        (SDHC_BSR_BOUNDARY_8K_Val      << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_16K       (SDHC_BSR_BOUNDARY_16K_Val     << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_32K       (SDHC_BSR_BOUNDARY_32K_Val     << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_64K       (SDHC_BSR_BOUNDARY_64K_Val     << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_128K      (SDHC_BSR_BOUNDARY_128K_Val    << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_256K      (SDHC_BSR_BOUNDARY_256K_Val    << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_BOUNDARY_512K      (SDHC_BSR_BOUNDARY_512K_Val    << SDHC_BSR_BOUNDARY_Pos)
-#define SDHC_BSR_MASK               _U_(0x73FF)  /**< \brief (SDHC_BSR) MASK Register */
-
-/* -------- SDHC_BCR : (SDHC Offset: 0x006) (R/W 16) Block Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BCNT:16;          /*!< bit:  0..15  Blocks Count for Current Transfer  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_BCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_BCR_OFFSET             0x006        /**< \brief (SDHC_BCR offset) Block Count */
-#define SDHC_BCR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_BCR reset_value) Block Count */
-
-#define SDHC_BCR_BCNT_Pos           0            /**< \brief (SDHC_BCR) Blocks Count for Current Transfer */
-#define SDHC_BCR_BCNT_Msk           (_U_(0xFFFF) << SDHC_BCR_BCNT_Pos)
-#define SDHC_BCR_BCNT(value)        (SDHC_BCR_BCNT_Msk & ((value) << SDHC_BCR_BCNT_Pos))
-#define SDHC_BCR_MASK               _U_(0xFFFF)  /**< \brief (SDHC_BCR) MASK Register */
-
-/* -------- SDHC_ARG1R : (SDHC Offset: 0x008) (R/W 32) Argument 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ARG:32;           /*!< bit:  0..31  Argument 1                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_ARG1R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_ARG1R_OFFSET           0x008        /**< \brief (SDHC_ARG1R offset) Argument 1 */
-#define SDHC_ARG1R_RESETVALUE       _U_(0x00000000) /**< \brief (SDHC_ARG1R reset_value) Argument 1 */
-
-#define SDHC_ARG1R_ARG_Pos          0            /**< \brief (SDHC_ARG1R) Argument 1 */
-#define SDHC_ARG1R_ARG_Msk          (_U_(0xFFFFFFFF) << SDHC_ARG1R_ARG_Pos)
-#define SDHC_ARG1R_ARG(value)       (SDHC_ARG1R_ARG_Msk & ((value) << SDHC_ARG1R_ARG_Pos))
-#define SDHC_ARG1R_MASK             _U_(0xFFFFFFFF) /**< \brief (SDHC_ARG1R) MASK Register */
-
-/* -------- SDHC_TMR : (SDHC Offset: 0x00C) (R/W 16) Transfer Mode -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DMAEN:1;          /*!< bit:      0  DMA Enable                         */
-    uint16_t BCEN:1;           /*!< bit:      1  Block Count Enable                 */
-    uint16_t ACMDEN:2;         /*!< bit:  2.. 3  Auto Command Enable                */
-    uint16_t DTDSEL:1;         /*!< bit:      4  Data Transfer Direction Selection  */
-    uint16_t MSBSEL:1;         /*!< bit:      5  Multi/Single Block Selection       */
-    uint16_t :10;              /*!< bit:  6..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_TMR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_TMR_OFFSET             0x00C        /**< \brief (SDHC_TMR offset) Transfer Mode */
-#define SDHC_TMR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_TMR reset_value) Transfer Mode */
-
-#define SDHC_TMR_DMAEN_Pos          0            /**< \brief (SDHC_TMR) DMA Enable */
-#define SDHC_TMR_DMAEN              (_U_(0x1) << SDHC_TMR_DMAEN_Pos)
-#define   SDHC_TMR_DMAEN_DISABLE_Val      _U_(0x0)   /**< \brief (SDHC_TMR) No data transfer or Non DMA data transfer */
-#define   SDHC_TMR_DMAEN_ENABLE_Val       _U_(0x1)   /**< \brief (SDHC_TMR) DMA data transfer */
-#define SDHC_TMR_DMAEN_DISABLE      (SDHC_TMR_DMAEN_DISABLE_Val    << SDHC_TMR_DMAEN_Pos)
-#define SDHC_TMR_DMAEN_ENABLE       (SDHC_TMR_DMAEN_ENABLE_Val     << SDHC_TMR_DMAEN_Pos)
-#define SDHC_TMR_BCEN_Pos           1            /**< \brief (SDHC_TMR) Block Count Enable */
-#define SDHC_TMR_BCEN               (_U_(0x1) << SDHC_TMR_BCEN_Pos)
-#define   SDHC_TMR_BCEN_DISABLE_Val       _U_(0x0)   /**< \brief (SDHC_TMR) Disable */
-#define   SDHC_TMR_BCEN_ENABLE_Val        _U_(0x1)   /**< \brief (SDHC_TMR) Enable */
-#define SDHC_TMR_BCEN_DISABLE       (SDHC_TMR_BCEN_DISABLE_Val     << SDHC_TMR_BCEN_Pos)
-#define SDHC_TMR_BCEN_ENABLE        (SDHC_TMR_BCEN_ENABLE_Val      << SDHC_TMR_BCEN_Pos)
-#define SDHC_TMR_ACMDEN_Pos         2            /**< \brief (SDHC_TMR) Auto Command Enable */
-#define SDHC_TMR_ACMDEN_Msk         (_U_(0x3) << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_ACMDEN(value)      (SDHC_TMR_ACMDEN_Msk & ((value) << SDHC_TMR_ACMDEN_Pos))
-#define   SDHC_TMR_ACMDEN_DISABLED_Val    _U_(0x0)   /**< \brief (SDHC_TMR) Auto Command Disabled */
-#define   SDHC_TMR_ACMDEN_CMD12_Val       _U_(0x1)   /**< \brief (SDHC_TMR) Auto CMD12 Enable */
-#define   SDHC_TMR_ACMDEN_CMD23_Val       _U_(0x2)   /**< \brief (SDHC_TMR) Auto CMD23 Enable */
-#define   SDHC_TMR_ACMDEN_3_Val           _U_(0x3)   /**< \brief (SDHC_TMR) Reserved */
-#define SDHC_TMR_ACMDEN_DISABLED    (SDHC_TMR_ACMDEN_DISABLED_Val  << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_ACMDEN_CMD12       (SDHC_TMR_ACMDEN_CMD12_Val     << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_ACMDEN_CMD23       (SDHC_TMR_ACMDEN_CMD23_Val     << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_ACMDEN_3           (SDHC_TMR_ACMDEN_3_Val         << SDHC_TMR_ACMDEN_Pos)
-#define SDHC_TMR_DTDSEL_Pos         4            /**< \brief (SDHC_TMR) Data Transfer Direction Selection */
-#define SDHC_TMR_DTDSEL             (_U_(0x1) << SDHC_TMR_DTDSEL_Pos)
-#define   SDHC_TMR_DTDSEL_WRITE_Val       _U_(0x0)   /**< \brief (SDHC_TMR) Write (Host to Card) */
-#define   SDHC_TMR_DTDSEL_READ_Val        _U_(0x1)   /**< \brief (SDHC_TMR) Read (Card to Host) */
-#define SDHC_TMR_DTDSEL_WRITE       (SDHC_TMR_DTDSEL_WRITE_Val     << SDHC_TMR_DTDSEL_Pos)
-#define SDHC_TMR_DTDSEL_READ        (SDHC_TMR_DTDSEL_READ_Val      << SDHC_TMR_DTDSEL_Pos)
-#define SDHC_TMR_MSBSEL_Pos         5            /**< \brief (SDHC_TMR) Multi/Single Block Selection */
-#define SDHC_TMR_MSBSEL             (_U_(0x1) << SDHC_TMR_MSBSEL_Pos)
-#define   SDHC_TMR_MSBSEL_SINGLE_Val      _U_(0x0)   /**< \brief (SDHC_TMR) Single Block */
-#define   SDHC_TMR_MSBSEL_MULTIPLE_Val    _U_(0x1)   /**< \brief (SDHC_TMR) Multiple Block */
-#define SDHC_TMR_MSBSEL_SINGLE      (SDHC_TMR_MSBSEL_SINGLE_Val    << SDHC_TMR_MSBSEL_Pos)
-#define SDHC_TMR_MSBSEL_MULTIPLE    (SDHC_TMR_MSBSEL_MULTIPLE_Val  << SDHC_TMR_MSBSEL_Pos)
-#define SDHC_TMR_MASK               _U_(0x003F)  /**< \brief (SDHC_TMR) MASK Register */
-
-/* -------- SDHC_CR : (SDHC Offset: 0x00E) (R/W 16) Command -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t RESPTYP:2;        /*!< bit:  0.. 1  Response Type                      */
-    uint16_t :1;               /*!< bit:      2  Reserved                           */
-    uint16_t CMDCCEN:1;        /*!< bit:      3  Command CRC Check Enable           */
-    uint16_t CMDICEN:1;        /*!< bit:      4  Command Index Check Enable         */
-    uint16_t DPSEL:1;          /*!< bit:      5  Data Present Select                */
-    uint16_t CMDTYP:2;         /*!< bit:  6.. 7  Command Type                       */
-    uint16_t CMDIDX:6;         /*!< bit:  8..13  Command Index                      */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_CR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CR_OFFSET              0x00E        /**< \brief (SDHC_CR offset) Command */
-#define SDHC_CR_RESETVALUE          _U_(0x0000)  /**< \brief (SDHC_CR reset_value) Command */
-
-#define SDHC_CR_RESPTYP_Pos         0            /**< \brief (SDHC_CR) Response Type */
-#define SDHC_CR_RESPTYP_Msk         (_U_(0x3) << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_RESPTYP(value)      (SDHC_CR_RESPTYP_Msk & ((value) << SDHC_CR_RESPTYP_Pos))
-#define   SDHC_CR_RESPTYP_NONE_Val        _U_(0x0)   /**< \brief (SDHC_CR) No response */
-#define   SDHC_CR_RESPTYP_136_BIT_Val     _U_(0x1)   /**< \brief (SDHC_CR) 136-bit response */
-#define   SDHC_CR_RESPTYP_48_BIT_Val      _U_(0x2)   /**< \brief (SDHC_CR) 48-bit response */
-#define   SDHC_CR_RESPTYP_48_BIT_BUSY_Val _U_(0x3)   /**< \brief (SDHC_CR) 48-bit response check busy after response */
-#define SDHC_CR_RESPTYP_NONE        (SDHC_CR_RESPTYP_NONE_Val      << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_RESPTYP_136_BIT     (SDHC_CR_RESPTYP_136_BIT_Val   << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_RESPTYP_48_BIT      (SDHC_CR_RESPTYP_48_BIT_Val    << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_RESPTYP_48_BIT_BUSY (SDHC_CR_RESPTYP_48_BIT_BUSY_Val << SDHC_CR_RESPTYP_Pos)
-#define SDHC_CR_CMDCCEN_Pos         3            /**< \brief (SDHC_CR) Command CRC Check Enable */
-#define SDHC_CR_CMDCCEN             (_U_(0x1) << SDHC_CR_CMDCCEN_Pos)
-#define   SDHC_CR_CMDCCEN_DISABLE_Val     _U_(0x0)   /**< \brief (SDHC_CR) Disable */
-#define   SDHC_CR_CMDCCEN_ENABLE_Val      _U_(0x1)   /**< \brief (SDHC_CR) Enable */
-#define SDHC_CR_CMDCCEN_DISABLE     (SDHC_CR_CMDCCEN_DISABLE_Val   << SDHC_CR_CMDCCEN_Pos)
-#define SDHC_CR_CMDCCEN_ENABLE      (SDHC_CR_CMDCCEN_ENABLE_Val    << SDHC_CR_CMDCCEN_Pos)
-#define SDHC_CR_CMDICEN_Pos         4            /**< \brief (SDHC_CR) Command Index Check Enable */
-#define SDHC_CR_CMDICEN             (_U_(0x1) << SDHC_CR_CMDICEN_Pos)
-#define   SDHC_CR_CMDICEN_DISABLE_Val     _U_(0x0)   /**< \brief (SDHC_CR) Disable */
-#define   SDHC_CR_CMDICEN_ENABLE_Val      _U_(0x1)   /**< \brief (SDHC_CR) Enable */
-#define SDHC_CR_CMDICEN_DISABLE     (SDHC_CR_CMDICEN_DISABLE_Val   << SDHC_CR_CMDICEN_Pos)
-#define SDHC_CR_CMDICEN_ENABLE      (SDHC_CR_CMDICEN_ENABLE_Val    << SDHC_CR_CMDICEN_Pos)
-#define SDHC_CR_DPSEL_Pos           5            /**< \brief (SDHC_CR) Data Present Select */
-#define SDHC_CR_DPSEL               (_U_(0x1) << SDHC_CR_DPSEL_Pos)
-#define   SDHC_CR_DPSEL_NO_DATA_Val       _U_(0x0)   /**< \brief (SDHC_CR) No Data Present */
-#define   SDHC_CR_DPSEL_DATA_Val          _U_(0x1)   /**< \brief (SDHC_CR) Data Present */
-#define SDHC_CR_DPSEL_NO_DATA       (SDHC_CR_DPSEL_NO_DATA_Val     << SDHC_CR_DPSEL_Pos)
-#define SDHC_CR_DPSEL_DATA          (SDHC_CR_DPSEL_DATA_Val        << SDHC_CR_DPSEL_Pos)
-#define SDHC_CR_CMDTYP_Pos          6            /**< \brief (SDHC_CR) Command Type */
-#define SDHC_CR_CMDTYP_Msk          (_U_(0x3) << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDTYP(value)       (SDHC_CR_CMDTYP_Msk & ((value) << SDHC_CR_CMDTYP_Pos))
-#define   SDHC_CR_CMDTYP_NORMAL_Val       _U_(0x0)   /**< \brief (SDHC_CR) Other commands */
-#define   SDHC_CR_CMDTYP_SUSPEND_Val      _U_(0x1)   /**< \brief (SDHC_CR) CMD52 for writing Bus Suspend in CCCR */
-#define   SDHC_CR_CMDTYP_RESUME_Val       _U_(0x2)   /**< \brief (SDHC_CR) CMD52 for writing Function Select in CCCR */
-#define   SDHC_CR_CMDTYP_ABORT_Val        _U_(0x3)   /**< \brief (SDHC_CR) CMD12, CMD52 for writing I/O Abort in CCCR */
-#define SDHC_CR_CMDTYP_NORMAL       (SDHC_CR_CMDTYP_NORMAL_Val     << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDTYP_SUSPEND      (SDHC_CR_CMDTYP_SUSPEND_Val    << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDTYP_RESUME       (SDHC_CR_CMDTYP_RESUME_Val     << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDTYP_ABORT        (SDHC_CR_CMDTYP_ABORT_Val      << SDHC_CR_CMDTYP_Pos)
-#define SDHC_CR_CMDIDX_Pos          8            /**< \brief (SDHC_CR) Command Index */
-#define SDHC_CR_CMDIDX_Msk          (_U_(0x3F) << SDHC_CR_CMDIDX_Pos)
-#define SDHC_CR_CMDIDX(value)       (SDHC_CR_CMDIDX_Msk & ((value) << SDHC_CR_CMDIDX_Pos))
-#define SDHC_CR_MASK                _U_(0x3FFB)  /**< \brief (SDHC_CR) MASK Register */
-
-/* -------- SDHC_RR : (SDHC Offset: 0x010) (R/  32) Response -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CMDRESP:32;       /*!< bit:  0..31  Command Response                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_RR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_RR_OFFSET              0x010        /**< \brief (SDHC_RR offset) Response */
-#define SDHC_RR_RESETVALUE          _U_(0x00000000) /**< \brief (SDHC_RR reset_value) Response */
-
-#define SDHC_RR_CMDRESP_Pos         0            /**< \brief (SDHC_RR) Command Response */
-#define SDHC_RR_CMDRESP_Msk         (_U_(0xFFFFFFFF) << SDHC_RR_CMDRESP_Pos)
-#define SDHC_RR_CMDRESP(value)      (SDHC_RR_CMDRESP_Msk & ((value) << SDHC_RR_CMDRESP_Pos))
-#define SDHC_RR_MASK                _U_(0xFFFFFFFF) /**< \brief (SDHC_RR) MASK Register */
-
-/* -------- SDHC_BDPR : (SDHC Offset: 0x020) (R/W 32) Buffer Data Port -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BUFDATA:32;       /*!< bit:  0..31  Buffer Data                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_BDPR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_BDPR_OFFSET            0x020        /**< \brief (SDHC_BDPR offset) Buffer Data Port */
-#define SDHC_BDPR_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_BDPR reset_value) Buffer Data Port */
-
-#define SDHC_BDPR_BUFDATA_Pos       0            /**< \brief (SDHC_BDPR) Buffer Data */
-#define SDHC_BDPR_BUFDATA_Msk       (_U_(0xFFFFFFFF) << SDHC_BDPR_BUFDATA_Pos)
-#define SDHC_BDPR_BUFDATA(value)    (SDHC_BDPR_BUFDATA_Msk & ((value) << SDHC_BDPR_BUFDATA_Pos))
-#define SDHC_BDPR_MASK              _U_(0xFFFFFFFF) /**< \brief (SDHC_BDPR) MASK Register */
-
-/* -------- SDHC_PSR : (SDHC Offset: 0x024) (R/  32) Present State -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CMDINHC:1;        /*!< bit:      0  Command Inhibit (CMD)              */
-    uint32_t CMDINHD:1;        /*!< bit:      1  Command Inhibit (DAT)              */
-    uint32_t DLACT:1;          /*!< bit:      2  DAT Line Active                    */
-    uint32_t RTREQ:1;          /*!< bit:      3  Re-Tuning Request                  */
-    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
-    uint32_t WTACT:1;          /*!< bit:      8  Write Transfer Active              */
-    uint32_t RTACT:1;          /*!< bit:      9  Read Transfer Active               */
-    uint32_t BUFWREN:1;        /*!< bit:     10  Buffer Write Enable                */
-    uint32_t BUFRDEN:1;        /*!< bit:     11  Buffer Read Enable                 */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t CARDINS:1;        /*!< bit:     16  Card Inserted                      */
-    uint32_t CARDSS:1;         /*!< bit:     17  Card State Stable                  */
-    uint32_t CARDDPL:1;        /*!< bit:     18  Card Detect Pin Level              */
-    uint32_t WRPPL:1;          /*!< bit:     19  Write Protect Pin Level            */
-    uint32_t DATLL:4;          /*!< bit: 20..23  DAT[3:0] Line Level                */
-    uint32_t CMDLL:1;          /*!< bit:     24  CMD Line Level                     */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_PSR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_PSR_OFFSET             0x024        /**< \brief (SDHC_PSR offset) Present State */
-#define SDHC_PSR_RESETVALUE         _U_(0x00F80000) /**< \brief (SDHC_PSR reset_value) Present State */
-
-#define SDHC_PSR_CMDINHC_Pos        0            /**< \brief (SDHC_PSR) Command Inhibit (CMD) */
-#define SDHC_PSR_CMDINHC            (_U_(0x1) << SDHC_PSR_CMDINHC_Pos)
-#define   SDHC_PSR_CMDINHC_CAN_Val        _U_(0x0)   /**< \brief (SDHC_PSR) Can issue command using only CMD line */
-#define   SDHC_PSR_CMDINHC_CANNOT_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Cannot issue command */
-#define SDHC_PSR_CMDINHC_CAN        (SDHC_PSR_CMDINHC_CAN_Val      << SDHC_PSR_CMDINHC_Pos)
-#define SDHC_PSR_CMDINHC_CANNOT     (SDHC_PSR_CMDINHC_CANNOT_Val   << SDHC_PSR_CMDINHC_Pos)
-#define SDHC_PSR_CMDINHD_Pos        1            /**< \brief (SDHC_PSR) Command Inhibit (DAT) */
-#define SDHC_PSR_CMDINHD            (_U_(0x1) << SDHC_PSR_CMDINHD_Pos)
-#define   SDHC_PSR_CMDINHD_CAN_Val        _U_(0x0)   /**< \brief (SDHC_PSR) Can issue command which uses the DAT line */
-#define   SDHC_PSR_CMDINHD_CANNOT_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Cannot issue command which uses the DAT line */
-#define SDHC_PSR_CMDINHD_CAN        (SDHC_PSR_CMDINHD_CAN_Val      << SDHC_PSR_CMDINHD_Pos)
-#define SDHC_PSR_CMDINHD_CANNOT     (SDHC_PSR_CMDINHD_CANNOT_Val   << SDHC_PSR_CMDINHD_Pos)
-#define SDHC_PSR_DLACT_Pos          2            /**< \brief (SDHC_PSR) DAT Line Active */
-#define SDHC_PSR_DLACT              (_U_(0x1) << SDHC_PSR_DLACT_Pos)
-#define   SDHC_PSR_DLACT_INACTIVE_Val     _U_(0x0)   /**< \brief (SDHC_PSR) DAT Line Inactive */
-#define   SDHC_PSR_DLACT_ACTIVE_Val       _U_(0x1)   /**< \brief (SDHC_PSR) DAT Line Active */
-#define SDHC_PSR_DLACT_INACTIVE     (SDHC_PSR_DLACT_INACTIVE_Val   << SDHC_PSR_DLACT_Pos)
-#define SDHC_PSR_DLACT_ACTIVE       (SDHC_PSR_DLACT_ACTIVE_Val     << SDHC_PSR_DLACT_Pos)
-#define SDHC_PSR_RTREQ_Pos          3            /**< \brief (SDHC_PSR) Re-Tuning Request */
-#define SDHC_PSR_RTREQ              (_U_(0x1) << SDHC_PSR_RTREQ_Pos)
-#define   SDHC_PSR_RTREQ_OK_Val           _U_(0x0)   /**< \brief (SDHC_PSR) Fixed or well-tuned sampling clock */
-#define   SDHC_PSR_RTREQ_REQUIRED_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Sampling clock needs re-tuning */
-#define SDHC_PSR_RTREQ_OK           (SDHC_PSR_RTREQ_OK_Val         << SDHC_PSR_RTREQ_Pos)
-#define SDHC_PSR_RTREQ_REQUIRED     (SDHC_PSR_RTREQ_REQUIRED_Val   << SDHC_PSR_RTREQ_Pos)
-#define SDHC_PSR_WTACT_Pos          8            /**< \brief (SDHC_PSR) Write Transfer Active */
-#define SDHC_PSR_WTACT              (_U_(0x1) << SDHC_PSR_WTACT_Pos)
-#define   SDHC_PSR_WTACT_NO_Val           _U_(0x0)   /**< \brief (SDHC_PSR) No valid data */
-#define   SDHC_PSR_WTACT_YES_Val          _U_(0x1)   /**< \brief (SDHC_PSR) Transferring data */
-#define SDHC_PSR_WTACT_NO           (SDHC_PSR_WTACT_NO_Val         << SDHC_PSR_WTACT_Pos)
-#define SDHC_PSR_WTACT_YES          (SDHC_PSR_WTACT_YES_Val        << SDHC_PSR_WTACT_Pos)
-#define SDHC_PSR_RTACT_Pos          9            /**< \brief (SDHC_PSR) Read Transfer Active */
-#define SDHC_PSR_RTACT              (_U_(0x1) << SDHC_PSR_RTACT_Pos)
-#define   SDHC_PSR_RTACT_NO_Val           _U_(0x0)   /**< \brief (SDHC_PSR) No valid data */
-#define   SDHC_PSR_RTACT_YES_Val          _U_(0x1)   /**< \brief (SDHC_PSR) Transferring data */
-#define SDHC_PSR_RTACT_NO           (SDHC_PSR_RTACT_NO_Val         << SDHC_PSR_RTACT_Pos)
-#define SDHC_PSR_RTACT_YES          (SDHC_PSR_RTACT_YES_Val        << SDHC_PSR_RTACT_Pos)
-#define SDHC_PSR_BUFWREN_Pos        10           /**< \brief (SDHC_PSR) Buffer Write Enable */
-#define SDHC_PSR_BUFWREN            (_U_(0x1) << SDHC_PSR_BUFWREN_Pos)
-#define   SDHC_PSR_BUFWREN_DISABLE_Val    _U_(0x0)   /**< \brief (SDHC_PSR) Write disable */
-#define   SDHC_PSR_BUFWREN_ENABLE_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Write enable */
-#define SDHC_PSR_BUFWREN_DISABLE    (SDHC_PSR_BUFWREN_DISABLE_Val  << SDHC_PSR_BUFWREN_Pos)
-#define SDHC_PSR_BUFWREN_ENABLE     (SDHC_PSR_BUFWREN_ENABLE_Val   << SDHC_PSR_BUFWREN_Pos)
-#define SDHC_PSR_BUFRDEN_Pos        11           /**< \brief (SDHC_PSR) Buffer Read Enable */
-#define SDHC_PSR_BUFRDEN            (_U_(0x1) << SDHC_PSR_BUFRDEN_Pos)
-#define   SDHC_PSR_BUFRDEN_DISABLE_Val    _U_(0x0)   /**< \brief (SDHC_PSR) Read disable */
-#define   SDHC_PSR_BUFRDEN_ENABLE_Val     _U_(0x1)   /**< \brief (SDHC_PSR) Read enable */
-#define SDHC_PSR_BUFRDEN_DISABLE    (SDHC_PSR_BUFRDEN_DISABLE_Val  << SDHC_PSR_BUFRDEN_Pos)
-#define SDHC_PSR_BUFRDEN_ENABLE     (SDHC_PSR_BUFRDEN_ENABLE_Val   << SDHC_PSR_BUFRDEN_Pos)
-#define SDHC_PSR_CARDINS_Pos        16           /**< \brief (SDHC_PSR) Card Inserted */
-#define SDHC_PSR_CARDINS            (_U_(0x1) << SDHC_PSR_CARDINS_Pos)
-#define   SDHC_PSR_CARDINS_NO_Val         _U_(0x0)   /**< \brief (SDHC_PSR) Reset or Debouncing or No Card */
-#define   SDHC_PSR_CARDINS_YES_Val        _U_(0x1)   /**< \brief (SDHC_PSR) Card inserted */
-#define SDHC_PSR_CARDINS_NO         (SDHC_PSR_CARDINS_NO_Val       << SDHC_PSR_CARDINS_Pos)
-#define SDHC_PSR_CARDINS_YES        (SDHC_PSR_CARDINS_YES_Val      << SDHC_PSR_CARDINS_Pos)
-#define SDHC_PSR_CARDSS_Pos         17           /**< \brief (SDHC_PSR) Card State Stable */
-#define SDHC_PSR_CARDSS             (_U_(0x1) << SDHC_PSR_CARDSS_Pos)
-#define   SDHC_PSR_CARDSS_NO_Val          _U_(0x0)   /**< \brief (SDHC_PSR) Reset or Debouncing */
-#define   SDHC_PSR_CARDSS_YES_Val         _U_(0x1)   /**< \brief (SDHC_PSR) No Card or Insered */
-#define SDHC_PSR_CARDSS_NO          (SDHC_PSR_CARDSS_NO_Val        << SDHC_PSR_CARDSS_Pos)
-#define SDHC_PSR_CARDSS_YES         (SDHC_PSR_CARDSS_YES_Val       << SDHC_PSR_CARDSS_Pos)
-#define SDHC_PSR_CARDDPL_Pos        18           /**< \brief (SDHC_PSR) Card Detect Pin Level */
-#define SDHC_PSR_CARDDPL            (_U_(0x1) << SDHC_PSR_CARDDPL_Pos)
-#define   SDHC_PSR_CARDDPL_NO_Val         _U_(0x0)   /**< \brief (SDHC_PSR) No card present (SDCD#=1) */
-#define   SDHC_PSR_CARDDPL_YES_Val        _U_(0x1)   /**< \brief (SDHC_PSR) Card present (SDCD#=0) */
-#define SDHC_PSR_CARDDPL_NO         (SDHC_PSR_CARDDPL_NO_Val       << SDHC_PSR_CARDDPL_Pos)
-#define SDHC_PSR_CARDDPL_YES        (SDHC_PSR_CARDDPL_YES_Val      << SDHC_PSR_CARDDPL_Pos)
-#define SDHC_PSR_WRPPL_Pos          19           /**< \brief (SDHC_PSR) Write Protect Pin Level */
-#define SDHC_PSR_WRPPL              (_U_(0x1) << SDHC_PSR_WRPPL_Pos)
-#define   SDHC_PSR_WRPPL_PROTECTED_Val    _U_(0x0)   /**< \brief (SDHC_PSR) Write protected (SDWP#=0) */
-#define   SDHC_PSR_WRPPL_ENABLED_Val      _U_(0x1)   /**< \brief (SDHC_PSR) Write enabled (SDWP#=1) */
-#define SDHC_PSR_WRPPL_PROTECTED    (SDHC_PSR_WRPPL_PROTECTED_Val  << SDHC_PSR_WRPPL_Pos)
-#define SDHC_PSR_WRPPL_ENABLED      (SDHC_PSR_WRPPL_ENABLED_Val    << SDHC_PSR_WRPPL_Pos)
-#define SDHC_PSR_DATLL_Pos          20           /**< \brief (SDHC_PSR) DAT[3:0] Line Level */
-#define SDHC_PSR_DATLL_Msk          (_U_(0xF) << SDHC_PSR_DATLL_Pos)
-#define SDHC_PSR_DATLL(value)       (SDHC_PSR_DATLL_Msk & ((value) << SDHC_PSR_DATLL_Pos))
-#define SDHC_PSR_CMDLL_Pos          24           /**< \brief (SDHC_PSR) CMD Line Level */
-#define SDHC_PSR_CMDLL              (_U_(0x1) << SDHC_PSR_CMDLL_Pos)
-#define SDHC_PSR_MASK               _U_(0x01FF0F0F) /**< \brief (SDHC_PSR) MASK Register */
-
-/* -------- SDHC_HC1R : (SDHC Offset: 0x028) (R/W  8) Host Control 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  LEDCTRL:1;        /*!< bit:      0  LED Control                        */
-    uint8_t  DW:1;             /*!< bit:      1  Data Width                         */
-    uint8_t  HSEN:1;           /*!< bit:      2  High Speed Enable                  */
-    uint8_t  DMASEL:2;         /*!< bit:  3.. 4  DMA Select                         */
-    uint8_t  :1;               /*!< bit:      5  Reserved                           */
-    uint8_t  CARDDTL:1;        /*!< bit:      6  Card Detect Test Level             */
-    uint8_t  CARDDSEL:1;       /*!< bit:      7  Card Detect Signal Selection       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // EMMC mode
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  DW:1;             /*!< bit:      1  Data Width                         */
-    uint8_t  HSEN:1;           /*!< bit:      2  High Speed Enable                  */
-    uint8_t  DMASEL:2;         /*!< bit:  3.. 4  DMA Select                         */
-    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
-  } EMMC;                      /*!< Structure used for EMMC                         */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_HC1R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_HC1R_OFFSET            0x028        /**< \brief (SDHC_HC1R offset) Host Control 1 */
-#define SDHC_HC1R_RESETVALUE        _U_(0xE00)   /**< \brief (SDHC_HC1R reset_value) Host Control 1 */
-
-#define SDHC_HC1R_LEDCTRL_Pos       0            /**< \brief (SDHC_HC1R) LED Control */
-#define SDHC_HC1R_LEDCTRL           (_U_(0x1) << SDHC_HC1R_LEDCTRL_Pos)
-#define   SDHC_HC1R_LEDCTRL_OFF_Val       _U_(0x0)   /**< \brief (SDHC_HC1R) LED off */
-#define   SDHC_HC1R_LEDCTRL_ON_Val        _U_(0x1)   /**< \brief (SDHC_HC1R) LED on */
-#define SDHC_HC1R_LEDCTRL_OFF       (SDHC_HC1R_LEDCTRL_OFF_Val     << SDHC_HC1R_LEDCTRL_Pos)
-#define SDHC_HC1R_LEDCTRL_ON        (SDHC_HC1R_LEDCTRL_ON_Val      << SDHC_HC1R_LEDCTRL_Pos)
-#define SDHC_HC1R_DW_Pos            1            /**< \brief (SDHC_HC1R) Data Width */
-#define SDHC_HC1R_DW                (_U_(0x1) << SDHC_HC1R_DW_Pos)
-#define   SDHC_HC1R_DW_1BIT_Val           _U_(0x0)   /**< \brief (SDHC_HC1R) 1-bit mode */
-#define   SDHC_HC1R_DW_4BIT_Val           _U_(0x1)   /**< \brief (SDHC_HC1R) 4-bit mode */
-#define SDHC_HC1R_DW_1BIT           (SDHC_HC1R_DW_1BIT_Val         << SDHC_HC1R_DW_Pos)
-#define SDHC_HC1R_DW_4BIT           (SDHC_HC1R_DW_4BIT_Val         << SDHC_HC1R_DW_Pos)
-#define SDHC_HC1R_HSEN_Pos          2            /**< \brief (SDHC_HC1R) High Speed Enable */
-#define SDHC_HC1R_HSEN              (_U_(0x1) << SDHC_HC1R_HSEN_Pos)
-#define   SDHC_HC1R_HSEN_NORMAL_Val       _U_(0x0)   /**< \brief (SDHC_HC1R) Normal Speed mode */
-#define   SDHC_HC1R_HSEN_HIGH_Val         _U_(0x1)   /**< \brief (SDHC_HC1R) High Speed mode */
-#define SDHC_HC1R_HSEN_NORMAL       (SDHC_HC1R_HSEN_NORMAL_Val     << SDHC_HC1R_HSEN_Pos)
-#define SDHC_HC1R_HSEN_HIGH         (SDHC_HC1R_HSEN_HIGH_Val       << SDHC_HC1R_HSEN_Pos)
-#define SDHC_HC1R_DMASEL_Pos        3            /**< \brief (SDHC_HC1R) DMA Select */
-#define SDHC_HC1R_DMASEL_Msk        (_U_(0x3) << SDHC_HC1R_DMASEL_Pos)
-#define SDHC_HC1R_DMASEL(value)     (SDHC_HC1R_DMASEL_Msk & ((value) << SDHC_HC1R_DMASEL_Pos))
-#define   SDHC_HC1R_DMASEL_SDMA_Val       _U_(0x0)   /**< \brief (SDHC_HC1R) SDMA is selected */
-#define   SDHC_HC1R_DMASEL_1_Val          _U_(0x1)   /**< \brief (SDHC_HC1R) Reserved */
-#define   SDHC_HC1R_DMASEL_32BIT_Val      _U_(0x2)   /**< \brief (SDHC_HC1R) 32-bit Address ADMA2 is selected */
-#define SDHC_HC1R_DMASEL_SDMA       (SDHC_HC1R_DMASEL_SDMA_Val     << SDHC_HC1R_DMASEL_Pos)
-#define SDHC_HC1R_DMASEL_1          (SDHC_HC1R_DMASEL_1_Val        << SDHC_HC1R_DMASEL_Pos)
-#define SDHC_HC1R_DMASEL_32BIT      (SDHC_HC1R_DMASEL_32BIT_Val    << SDHC_HC1R_DMASEL_Pos)
-#define SDHC_HC1R_CARDDTL_Pos       6            /**< \brief (SDHC_HC1R) Card Detect Test Level */
-#define SDHC_HC1R_CARDDTL           (_U_(0x1) << SDHC_HC1R_CARDDTL_Pos)
-#define   SDHC_HC1R_CARDDTL_NO_Val        _U_(0x0)   /**< \brief (SDHC_HC1R) No Card */
-#define   SDHC_HC1R_CARDDTL_YES_Val       _U_(0x1)   /**< \brief (SDHC_HC1R) Card Inserted */
-#define SDHC_HC1R_CARDDTL_NO        (SDHC_HC1R_CARDDTL_NO_Val      << SDHC_HC1R_CARDDTL_Pos)
-#define SDHC_HC1R_CARDDTL_YES       (SDHC_HC1R_CARDDTL_YES_Val     << SDHC_HC1R_CARDDTL_Pos)
-#define SDHC_HC1R_CARDDSEL_Pos      7            /**< \brief (SDHC_HC1R) Card Detect Signal Selection */
-#define SDHC_HC1R_CARDDSEL          (_U_(0x1) << SDHC_HC1R_CARDDSEL_Pos)
-#define   SDHC_HC1R_CARDDSEL_NORMAL_Val   _U_(0x0)   /**< \brief (SDHC_HC1R) SDCD# is selected (for normal use) */
-#define   SDHC_HC1R_CARDDSEL_TEST_Val     _U_(0x1)   /**< \brief (SDHC_HC1R) The Card Select Test Level is selected (for test purpose) */
-#define SDHC_HC1R_CARDDSEL_NORMAL   (SDHC_HC1R_CARDDSEL_NORMAL_Val << SDHC_HC1R_CARDDSEL_Pos)
-#define SDHC_HC1R_CARDDSEL_TEST     (SDHC_HC1R_CARDDSEL_TEST_Val   << SDHC_HC1R_CARDDSEL_Pos)
-#define SDHC_HC1R_MASK              _U_(0xDF)    /**< \brief (SDHC_HC1R) MASK Register */
-
-// EMMC mode
-#define SDHC_HC1R_EMMC_DW_Pos       1            /**< \brief (SDHC_HC1R_EMMC) Data Width */
-#define SDHC_HC1R_EMMC_DW           (_U_(0x1) << SDHC_HC1R_EMMC_DW_Pos)
-#define   SDHC_HC1R_EMMC_DW_1BIT_Val      _U_(0x0)   /**< \brief (SDHC_HC1R_EMMC) 1-bit mode */
-#define   SDHC_HC1R_EMMC_DW_4BIT_Val      _U_(0x1)   /**< \brief (SDHC_HC1R_EMMC) 4-bit mode */
-#define SDHC_HC1R_EMMC_DW_1BIT      (SDHC_HC1R_EMMC_DW_1BIT_Val    << SDHC_HC1R_EMMC_DW_Pos)
-#define SDHC_HC1R_EMMC_DW_4BIT      (SDHC_HC1R_EMMC_DW_4BIT_Val    << SDHC_HC1R_EMMC_DW_Pos)
-#define SDHC_HC1R_EMMC_HSEN_Pos     2            /**< \brief (SDHC_HC1R_EMMC) High Speed Enable */
-#define SDHC_HC1R_EMMC_HSEN         (_U_(0x1) << SDHC_HC1R_EMMC_HSEN_Pos)
-#define   SDHC_HC1R_EMMC_HSEN_NORMAL_Val  _U_(0x0)   /**< \brief (SDHC_HC1R_EMMC) Normal Speed mode */
-#define   SDHC_HC1R_EMMC_HSEN_HIGH_Val    _U_(0x1)   /**< \brief (SDHC_HC1R_EMMC) High Speed mode */
-#define SDHC_HC1R_EMMC_HSEN_NORMAL  (SDHC_HC1R_EMMC_HSEN_NORMAL_Val << SDHC_HC1R_EMMC_HSEN_Pos)
-#define SDHC_HC1R_EMMC_HSEN_HIGH    (SDHC_HC1R_EMMC_HSEN_HIGH_Val  << SDHC_HC1R_EMMC_HSEN_Pos)
-#define SDHC_HC1R_EMMC_DMASEL_Pos   3            /**< \brief (SDHC_HC1R_EMMC) DMA Select */
-#define SDHC_HC1R_EMMC_DMASEL_Msk   (_U_(0x3) << SDHC_HC1R_EMMC_DMASEL_Pos)
-#define SDHC_HC1R_EMMC_DMASEL(value) (SDHC_HC1R_EMMC_DMASEL_Msk & ((value) << SDHC_HC1R_EMMC_DMASEL_Pos))
-#define   SDHC_HC1R_EMMC_DMASEL_SDMA_Val  _U_(0x0)   /**< \brief (SDHC_HC1R_EMMC) SDMA is selected */
-#define   SDHC_HC1R_EMMC_DMASEL_1_Val     _U_(0x1)   /**< \brief (SDHC_HC1R_EMMC) Reserved */
-#define   SDHC_HC1R_EMMC_DMASEL_32BIT_Val _U_(0x2)   /**< \brief (SDHC_HC1R_EMMC) 32-bit Address ADMA2 is selected */
-#define SDHC_HC1R_EMMC_DMASEL_SDMA  (SDHC_HC1R_EMMC_DMASEL_SDMA_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
-#define SDHC_HC1R_EMMC_DMASEL_1     (SDHC_HC1R_EMMC_DMASEL_1_Val   << SDHC_HC1R_EMMC_DMASEL_Pos)
-#define SDHC_HC1R_EMMC_DMASEL_32BIT (SDHC_HC1R_EMMC_DMASEL_32BIT_Val << SDHC_HC1R_EMMC_DMASEL_Pos)
-#define SDHC_HC1R_EMMC_MASK         _U_(0x1E)    /**< \brief (SDHC_HC1R_EMMC) MASK Register */
-
-/* -------- SDHC_PCR : (SDHC Offset: 0x029) (R/W  8) Power Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SDBPWR:1;         /*!< bit:      0  SD Bus Power                       */
-    uint8_t  SDBVSEL:3;        /*!< bit:  1.. 3  SD Bus Voltage Select              */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_PCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_PCR_OFFSET             0x029        /**< \brief (SDHC_PCR offset) Power Control */
-#define SDHC_PCR_RESETVALUE         _U_(0x0E)    /**< \brief (SDHC_PCR reset_value) Power Control */
-
-#define SDHC_PCR_SDBPWR_Pos         0            /**< \brief (SDHC_PCR) SD Bus Power */
-#define SDHC_PCR_SDBPWR             (_U_(0x1) << SDHC_PCR_SDBPWR_Pos)
-#define   SDHC_PCR_SDBPWR_OFF_Val         _U_(0x0)   /**< \brief (SDHC_PCR) Power off */
-#define   SDHC_PCR_SDBPWR_ON_Val          _U_(0x1)   /**< \brief (SDHC_PCR) Power on */
-#define SDHC_PCR_SDBPWR_OFF         (SDHC_PCR_SDBPWR_OFF_Val       << SDHC_PCR_SDBPWR_Pos)
-#define SDHC_PCR_SDBPWR_ON          (SDHC_PCR_SDBPWR_ON_Val        << SDHC_PCR_SDBPWR_Pos)
-#define SDHC_PCR_SDBVSEL_Pos        1            /**< \brief (SDHC_PCR) SD Bus Voltage Select */
-#define SDHC_PCR_SDBVSEL_Msk        (_U_(0x7) << SDHC_PCR_SDBVSEL_Pos)
-#define SDHC_PCR_SDBVSEL(value)     (SDHC_PCR_SDBVSEL_Msk & ((value) << SDHC_PCR_SDBVSEL_Pos))
-#define   SDHC_PCR_SDBVSEL_1V8_Val        _U_(0x5)   /**< \brief (SDHC_PCR) 1.8V (Typ.) */
-#define   SDHC_PCR_SDBVSEL_3V0_Val        _U_(0x6)   /**< \brief (SDHC_PCR) 3.0V (Typ.) */
-#define   SDHC_PCR_SDBVSEL_3V3_Val        _U_(0x7)   /**< \brief (SDHC_PCR) 3.3V (Typ.) */
-#define SDHC_PCR_SDBVSEL_1V8        (SDHC_PCR_SDBVSEL_1V8_Val      << SDHC_PCR_SDBVSEL_Pos)
-#define SDHC_PCR_SDBVSEL_3V0        (SDHC_PCR_SDBVSEL_3V0_Val      << SDHC_PCR_SDBVSEL_Pos)
-#define SDHC_PCR_SDBVSEL_3V3        (SDHC_PCR_SDBVSEL_3V3_Val      << SDHC_PCR_SDBVSEL_Pos)
-#define SDHC_PCR_MASK               _U_(0x0F)    /**< \brief (SDHC_PCR) MASK Register */
-
-/* -------- SDHC_BGCR : (SDHC Offset: 0x02A) (R/W  8) Block Gap Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  STPBGR:1;         /*!< bit:      0  Stop at Block Gap Request          */
-    uint8_t  CONTR:1;          /*!< bit:      1  Continue Request                   */
-    uint8_t  RWCTRL:1;         /*!< bit:      2  Read Wait Control                  */
-    uint8_t  INTBG:1;          /*!< bit:      3  Interrupt at Block Gap             */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // EMMC mode
-    uint8_t  STPBGR:1;         /*!< bit:      0  Stop at Block Gap Request          */
-    uint8_t  CONTR:1;          /*!< bit:      1  Continue Request                   */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } EMMC;                      /*!< Structure used for EMMC                         */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_BGCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_BGCR_OFFSET            0x02A        /**< \brief (SDHC_BGCR offset) Block Gap Control */
-#define SDHC_BGCR_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_BGCR reset_value) Block Gap Control */
-
-#define SDHC_BGCR_STPBGR_Pos        0            /**< \brief (SDHC_BGCR) Stop at Block Gap Request */
-#define SDHC_BGCR_STPBGR            (_U_(0x1) << SDHC_BGCR_STPBGR_Pos)
-#define   SDHC_BGCR_STPBGR_TRANSFER_Val   _U_(0x0)   /**< \brief (SDHC_BGCR) Transfer */
-#define   SDHC_BGCR_STPBGR_STOP_Val       _U_(0x1)   /**< \brief (SDHC_BGCR) Stop */
-#define SDHC_BGCR_STPBGR_TRANSFER   (SDHC_BGCR_STPBGR_TRANSFER_Val << SDHC_BGCR_STPBGR_Pos)
-#define SDHC_BGCR_STPBGR_STOP       (SDHC_BGCR_STPBGR_STOP_Val     << SDHC_BGCR_STPBGR_Pos)
-#define SDHC_BGCR_CONTR_Pos         1            /**< \brief (SDHC_BGCR) Continue Request */
-#define SDHC_BGCR_CONTR             (_U_(0x1) << SDHC_BGCR_CONTR_Pos)
-#define   SDHC_BGCR_CONTR_GO_ON_Val       _U_(0x0)   /**< \brief (SDHC_BGCR) Not affected */
-#define   SDHC_BGCR_CONTR_RESTART_Val     _U_(0x1)   /**< \brief (SDHC_BGCR) Restart */
-#define SDHC_BGCR_CONTR_GO_ON       (SDHC_BGCR_CONTR_GO_ON_Val     << SDHC_BGCR_CONTR_Pos)
-#define SDHC_BGCR_CONTR_RESTART     (SDHC_BGCR_CONTR_RESTART_Val   << SDHC_BGCR_CONTR_Pos)
-#define SDHC_BGCR_RWCTRL_Pos        2            /**< \brief (SDHC_BGCR) Read Wait Control */
-#define SDHC_BGCR_RWCTRL            (_U_(0x1) << SDHC_BGCR_RWCTRL_Pos)
-#define   SDHC_BGCR_RWCTRL_DISABLE_Val    _U_(0x0)   /**< \brief (SDHC_BGCR) Disable Read Wait Control */
-#define   SDHC_BGCR_RWCTRL_ENABLE_Val     _U_(0x1)   /**< \brief (SDHC_BGCR) Enable Read Wait Control */
-#define SDHC_BGCR_RWCTRL_DISABLE    (SDHC_BGCR_RWCTRL_DISABLE_Val  << SDHC_BGCR_RWCTRL_Pos)
-#define SDHC_BGCR_RWCTRL_ENABLE     (SDHC_BGCR_RWCTRL_ENABLE_Val   << SDHC_BGCR_RWCTRL_Pos)
-#define SDHC_BGCR_INTBG_Pos         3            /**< \brief (SDHC_BGCR) Interrupt at Block Gap */
-#define SDHC_BGCR_INTBG             (_U_(0x1) << SDHC_BGCR_INTBG_Pos)
-#define   SDHC_BGCR_INTBG_DISABLED_Val    _U_(0x0)   /**< \brief (SDHC_BGCR) Disabled */
-#define   SDHC_BGCR_INTBG_ENABLED_Val     _U_(0x1)   /**< \brief (SDHC_BGCR) Enabled */
-#define SDHC_BGCR_INTBG_DISABLED    (SDHC_BGCR_INTBG_DISABLED_Val  << SDHC_BGCR_INTBG_Pos)
-#define SDHC_BGCR_INTBG_ENABLED     (SDHC_BGCR_INTBG_ENABLED_Val   << SDHC_BGCR_INTBG_Pos)
-#define SDHC_BGCR_MASK              _U_(0x0F)    /**< \brief (SDHC_BGCR) MASK Register */
-
-// EMMC mode
-#define SDHC_BGCR_EMMC_STPBGR_Pos   0            /**< \brief (SDHC_BGCR_EMMC) Stop at Block Gap Request */
-#define SDHC_BGCR_EMMC_STPBGR       (_U_(0x1) << SDHC_BGCR_EMMC_STPBGR_Pos)
-#define   SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val _U_(0x0)   /**< \brief (SDHC_BGCR_EMMC) Transfer */
-#define   SDHC_BGCR_EMMC_STPBGR_STOP_Val  _U_(0x1)   /**< \brief (SDHC_BGCR_EMMC) Stop */
-#define SDHC_BGCR_EMMC_STPBGR_TRANSFER (SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
-#define SDHC_BGCR_EMMC_STPBGR_STOP  (SDHC_BGCR_EMMC_STPBGR_STOP_Val << SDHC_BGCR_EMMC_STPBGR_Pos)
-#define SDHC_BGCR_EMMC_CONTR_Pos    1            /**< \brief (SDHC_BGCR_EMMC) Continue Request */
-#define SDHC_BGCR_EMMC_CONTR        (_U_(0x1) << SDHC_BGCR_EMMC_CONTR_Pos)
-#define   SDHC_BGCR_EMMC_CONTR_GO_ON_Val  _U_(0x0)   /**< \brief (SDHC_BGCR_EMMC) Not affected */
-#define   SDHC_BGCR_EMMC_CONTR_RESTART_Val _U_(0x1)   /**< \brief (SDHC_BGCR_EMMC) Restart */
-#define SDHC_BGCR_EMMC_CONTR_GO_ON  (SDHC_BGCR_EMMC_CONTR_GO_ON_Val << SDHC_BGCR_EMMC_CONTR_Pos)
-#define SDHC_BGCR_EMMC_CONTR_RESTART (SDHC_BGCR_EMMC_CONTR_RESTART_Val << SDHC_BGCR_EMMC_CONTR_Pos)
-#define SDHC_BGCR_EMMC_MASK         _U_(0x03)    /**< \brief (SDHC_BGCR_EMMC) MASK Register */
-
-/* -------- SDHC_WCR : (SDHC Offset: 0x02B) (R/W  8) Wakeup Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  WKENCINT:1;       /*!< bit:      0  Wakeup Event Enable on Card Interrupt */
-    uint8_t  WKENCINS:1;       /*!< bit:      1  Wakeup Event Enable on Card Insertion */
-    uint8_t  WKENCREM:1;       /*!< bit:      2  Wakeup Event Enable on Card Removal */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_WCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_WCR_OFFSET             0x02B        /**< \brief (SDHC_WCR offset) Wakeup Control */
-#define SDHC_WCR_RESETVALUE         _U_(0x00)    /**< \brief (SDHC_WCR reset_value) Wakeup Control */
-
-#define SDHC_WCR_WKENCINT_Pos       0            /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Interrupt */
-#define SDHC_WCR_WKENCINT           (_U_(0x1) << SDHC_WCR_WKENCINT_Pos)
-#define   SDHC_WCR_WKENCINT_DISABLE_Val   _U_(0x0)   /**< \brief (SDHC_WCR) Disable */
-#define   SDHC_WCR_WKENCINT_ENABLE_Val    _U_(0x1)   /**< \brief (SDHC_WCR) Enable */
-#define SDHC_WCR_WKENCINT_DISABLE   (SDHC_WCR_WKENCINT_DISABLE_Val << SDHC_WCR_WKENCINT_Pos)
-#define SDHC_WCR_WKENCINT_ENABLE    (SDHC_WCR_WKENCINT_ENABLE_Val  << SDHC_WCR_WKENCINT_Pos)
-#define SDHC_WCR_WKENCINS_Pos       1            /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Insertion */
-#define SDHC_WCR_WKENCINS           (_U_(0x1) << SDHC_WCR_WKENCINS_Pos)
-#define   SDHC_WCR_WKENCINS_DISABLE_Val   _U_(0x0)   /**< \brief (SDHC_WCR) Disable */
-#define   SDHC_WCR_WKENCINS_ENABLE_Val    _U_(0x1)   /**< \brief (SDHC_WCR) Enable */
-#define SDHC_WCR_WKENCINS_DISABLE   (SDHC_WCR_WKENCINS_DISABLE_Val << SDHC_WCR_WKENCINS_Pos)
-#define SDHC_WCR_WKENCINS_ENABLE    (SDHC_WCR_WKENCINS_ENABLE_Val  << SDHC_WCR_WKENCINS_Pos)
-#define SDHC_WCR_WKENCREM_Pos       2            /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Removal */
-#define SDHC_WCR_WKENCREM           (_U_(0x1) << SDHC_WCR_WKENCREM_Pos)
-#define   SDHC_WCR_WKENCREM_DISABLE_Val   _U_(0x0)   /**< \brief (SDHC_WCR) Disable */
-#define   SDHC_WCR_WKENCREM_ENABLE_Val    _U_(0x1)   /**< \brief (SDHC_WCR) Enable */
-#define SDHC_WCR_WKENCREM_DISABLE   (SDHC_WCR_WKENCREM_DISABLE_Val << SDHC_WCR_WKENCREM_Pos)
-#define SDHC_WCR_WKENCREM_ENABLE    (SDHC_WCR_WKENCREM_ENABLE_Val  << SDHC_WCR_WKENCREM_Pos)
-#define SDHC_WCR_MASK               _U_(0x07)    /**< \brief (SDHC_WCR) MASK Register */
-
-/* -------- SDHC_CCR : (SDHC Offset: 0x02C) (R/W 16) Clock Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t INTCLKEN:1;       /*!< bit:      0  Internal Clock Enable              */
-    uint16_t INTCLKS:1;        /*!< bit:      1  Internal Clock Stable              */
-    uint16_t SDCLKEN:1;        /*!< bit:      2  SD Clock Enable                    */
-    uint16_t :2;               /*!< bit:  3.. 4  Reserved                           */
-    uint16_t CLKGSEL:1;        /*!< bit:      5  Clock Generator Select             */
-    uint16_t USDCLKFSEL:2;     /*!< bit:  6.. 7  Upper Bits of SDCLK Frequency Select */
-    uint16_t SDCLKFSEL:8;      /*!< bit:  8..15  SDCLK Frequency Select             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_CCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CCR_OFFSET             0x02C        /**< \brief (SDHC_CCR offset) Clock Control */
-#define SDHC_CCR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_CCR reset_value) Clock Control */
-
-#define SDHC_CCR_INTCLKEN_Pos       0            /**< \brief (SDHC_CCR) Internal Clock Enable */
-#define SDHC_CCR_INTCLKEN           (_U_(0x1) << SDHC_CCR_INTCLKEN_Pos)
-#define   SDHC_CCR_INTCLKEN_OFF_Val       _U_(0x0)   /**< \brief (SDHC_CCR) Stop */
-#define   SDHC_CCR_INTCLKEN_ON_Val        _U_(0x1)   /**< \brief (SDHC_CCR) Oscillate */
-#define SDHC_CCR_INTCLKEN_OFF       (SDHC_CCR_INTCLKEN_OFF_Val     << SDHC_CCR_INTCLKEN_Pos)
-#define SDHC_CCR_INTCLKEN_ON        (SDHC_CCR_INTCLKEN_ON_Val      << SDHC_CCR_INTCLKEN_Pos)
-#define SDHC_CCR_INTCLKS_Pos        1            /**< \brief (SDHC_CCR) Internal Clock Stable */
-#define SDHC_CCR_INTCLKS            (_U_(0x1) << SDHC_CCR_INTCLKS_Pos)
-#define   SDHC_CCR_INTCLKS_NOT_READY_Val  _U_(0x0)   /**< \brief (SDHC_CCR) Not Ready */
-#define   SDHC_CCR_INTCLKS_READY_Val      _U_(0x1)   /**< \brief (SDHC_CCR) Ready */
-#define SDHC_CCR_INTCLKS_NOT_READY  (SDHC_CCR_INTCLKS_NOT_READY_Val << SDHC_CCR_INTCLKS_Pos)
-#define SDHC_CCR_INTCLKS_READY      (SDHC_CCR_INTCLKS_READY_Val    << SDHC_CCR_INTCLKS_Pos)
-#define SDHC_CCR_SDCLKEN_Pos        2            /**< \brief (SDHC_CCR) SD Clock Enable */
-#define SDHC_CCR_SDCLKEN            (_U_(0x1) << SDHC_CCR_SDCLKEN_Pos)
-#define   SDHC_CCR_SDCLKEN_DISABLE_Val    _U_(0x0)   /**< \brief (SDHC_CCR) Disable */
-#define   SDHC_CCR_SDCLKEN_ENABLE_Val     _U_(0x1)   /**< \brief (SDHC_CCR) Enable */
-#define SDHC_CCR_SDCLKEN_DISABLE    (SDHC_CCR_SDCLKEN_DISABLE_Val  << SDHC_CCR_SDCLKEN_Pos)
-#define SDHC_CCR_SDCLKEN_ENABLE     (SDHC_CCR_SDCLKEN_ENABLE_Val   << SDHC_CCR_SDCLKEN_Pos)
-#define SDHC_CCR_CLKGSEL_Pos        5            /**< \brief (SDHC_CCR) Clock Generator Select */
-#define SDHC_CCR_CLKGSEL            (_U_(0x1) << SDHC_CCR_CLKGSEL_Pos)
-#define   SDHC_CCR_CLKGSEL_DIV_Val        _U_(0x0)   /**< \brief (SDHC_CCR) Divided Clock Mode */
-#define   SDHC_CCR_CLKGSEL_PROG_Val       _U_(0x1)   /**< \brief (SDHC_CCR) Programmable Clock Mode */
-#define SDHC_CCR_CLKGSEL_DIV        (SDHC_CCR_CLKGSEL_DIV_Val      << SDHC_CCR_CLKGSEL_Pos)
-#define SDHC_CCR_CLKGSEL_PROG       (SDHC_CCR_CLKGSEL_PROG_Val     << SDHC_CCR_CLKGSEL_Pos)
-#define SDHC_CCR_USDCLKFSEL_Pos     6            /**< \brief (SDHC_CCR) Upper Bits of SDCLK Frequency Select */
-#define SDHC_CCR_USDCLKFSEL_Msk     (_U_(0x3) << SDHC_CCR_USDCLKFSEL_Pos)
-#define SDHC_CCR_USDCLKFSEL(value)  (SDHC_CCR_USDCLKFSEL_Msk & ((value) << SDHC_CCR_USDCLKFSEL_Pos))
-#define SDHC_CCR_SDCLKFSEL_Pos      8            /**< \brief (SDHC_CCR) SDCLK Frequency Select */
-#define SDHC_CCR_SDCLKFSEL_Msk      (_U_(0xFF) << SDHC_CCR_SDCLKFSEL_Pos)
-#define SDHC_CCR_SDCLKFSEL(value)   (SDHC_CCR_SDCLKFSEL_Msk & ((value) << SDHC_CCR_SDCLKFSEL_Pos))
-#define SDHC_CCR_MASK               _U_(0xFFE7)  /**< \brief (SDHC_CCR) MASK Register */
-
-/* -------- SDHC_TCR : (SDHC Offset: 0x02E) (R/W  8) Timeout Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTCVAL:4;         /*!< bit:  0.. 3  Data Timeout Counter Value         */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_TCR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_TCR_OFFSET             0x02E        /**< \brief (SDHC_TCR offset) Timeout Control */
-#define SDHC_TCR_RESETVALUE         _U_(0x00)    /**< \brief (SDHC_TCR reset_value) Timeout Control */
-
-#define SDHC_TCR_DTCVAL_Pos         0            /**< \brief (SDHC_TCR) Data Timeout Counter Value */
-#define SDHC_TCR_DTCVAL_Msk         (_U_(0xF) << SDHC_TCR_DTCVAL_Pos)
-#define SDHC_TCR_DTCVAL(value)      (SDHC_TCR_DTCVAL_Msk & ((value) << SDHC_TCR_DTCVAL_Pos))
-#define SDHC_TCR_MASK               _U_(0x0F)    /**< \brief (SDHC_TCR) MASK Register */
-
-/* -------- SDHC_SRR : (SDHC Offset: 0x02F) (R/W  8) Software Reset -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRSTALL:1;       /*!< bit:      0  Software Reset For All             */
-    uint8_t  SWRSTCMD:1;       /*!< bit:      1  Software Reset For CMD Line        */
-    uint8_t  SWRSTDAT:1;       /*!< bit:      2  Software Reset For DAT Line        */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_SRR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_SRR_OFFSET             0x02F        /**< \brief (SDHC_SRR offset) Software Reset */
-#define SDHC_SRR_RESETVALUE         _U_(0x00)    /**< \brief (SDHC_SRR reset_value) Software Reset */
-
-#define SDHC_SRR_SWRSTALL_Pos       0            /**< \brief (SDHC_SRR) Software Reset For All */
-#define SDHC_SRR_SWRSTALL           (_U_(0x1) << SDHC_SRR_SWRSTALL_Pos)
-#define   SDHC_SRR_SWRSTALL_WORK_Val      _U_(0x0)   /**< \brief (SDHC_SRR) Work */
-#define   SDHC_SRR_SWRSTALL_RESET_Val     _U_(0x1)   /**< \brief (SDHC_SRR) Reset */
-#define SDHC_SRR_SWRSTALL_WORK      (SDHC_SRR_SWRSTALL_WORK_Val    << SDHC_SRR_SWRSTALL_Pos)
-#define SDHC_SRR_SWRSTALL_RESET     (SDHC_SRR_SWRSTALL_RESET_Val   << SDHC_SRR_SWRSTALL_Pos)
-#define SDHC_SRR_SWRSTCMD_Pos       1            /**< \brief (SDHC_SRR) Software Reset For CMD Line */
-#define SDHC_SRR_SWRSTCMD           (_U_(0x1) << SDHC_SRR_SWRSTCMD_Pos)
-#define   SDHC_SRR_SWRSTCMD_WORK_Val      _U_(0x0)   /**< \brief (SDHC_SRR) Work */
-#define   SDHC_SRR_SWRSTCMD_RESET_Val     _U_(0x1)   /**< \brief (SDHC_SRR) Reset */
-#define SDHC_SRR_SWRSTCMD_WORK      (SDHC_SRR_SWRSTCMD_WORK_Val    << SDHC_SRR_SWRSTCMD_Pos)
-#define SDHC_SRR_SWRSTCMD_RESET     (SDHC_SRR_SWRSTCMD_RESET_Val   << SDHC_SRR_SWRSTCMD_Pos)
-#define SDHC_SRR_SWRSTDAT_Pos       2            /**< \brief (SDHC_SRR) Software Reset For DAT Line */
-#define SDHC_SRR_SWRSTDAT           (_U_(0x1) << SDHC_SRR_SWRSTDAT_Pos)
-#define   SDHC_SRR_SWRSTDAT_WORK_Val      _U_(0x0)   /**< \brief (SDHC_SRR) Work */
-#define   SDHC_SRR_SWRSTDAT_RESET_Val     _U_(0x1)   /**< \brief (SDHC_SRR) Reset */
-#define SDHC_SRR_SWRSTDAT_WORK      (SDHC_SRR_SWRSTDAT_WORK_Val    << SDHC_SRR_SWRSTDAT_Pos)
-#define SDHC_SRR_SWRSTDAT_RESET     (SDHC_SRR_SWRSTDAT_RESET_Val   << SDHC_SRR_SWRSTDAT_Pos)
-#define SDHC_SRR_MASK               _U_(0x07)    /**< \brief (SDHC_SRR) MASK Register */
-
-/* -------- SDHC_NISTR : (SDHC Offset: 0x030) (R/W 16) Normal Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMDC:1;           /*!< bit:      0  Command Complete                   */
-    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete                  */
-    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event                    */
-    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt                      */
-    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready                 */
-    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready                  */
-    uint16_t CINS:1;           /*!< bit:      6  Card Insertion                     */
-    uint16_t CREM:1;           /*!< bit:      7  Card Removal                       */
-    uint16_t CINT:1;           /*!< bit:      8  Card Interrupt                     */
-    uint16_t :6;               /*!< bit:  9..14  Reserved                           */
-    uint16_t ERRINT:1;         /*!< bit:     15  Error Interrupt                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // EMMC mode
-    uint16_t CMDC:1;           /*!< bit:      0  Command Complete                   */
-    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete                  */
-    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event                    */
-    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt                      */
-    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready                 */
-    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready                  */
-    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
-    uint16_t BOOTAR:1;         /*!< bit:     14  Boot Acknowledge Received          */
-    uint16_t ERRINT:1;         /*!< bit:     15  Error Interrupt                    */
-  } EMMC;                      /*!< Structure used for EMMC                         */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_NISTR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_NISTR_OFFSET           0x030        /**< \brief (SDHC_NISTR offset) Normal Interrupt Status */
-#define SDHC_NISTR_RESETVALUE       _U_(0x0000)  /**< \brief (SDHC_NISTR reset_value) Normal Interrupt Status */
-
-#define SDHC_NISTR_CMDC_Pos         0            /**< \brief (SDHC_NISTR) Command Complete */
-#define SDHC_NISTR_CMDC             (_U_(0x1) << SDHC_NISTR_CMDC_Pos)
-#define   SDHC_NISTR_CMDC_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) No command complete */
-#define   SDHC_NISTR_CMDC_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Command complete */
-#define SDHC_NISTR_CMDC_NO          (SDHC_NISTR_CMDC_NO_Val        << SDHC_NISTR_CMDC_Pos)
-#define SDHC_NISTR_CMDC_YES         (SDHC_NISTR_CMDC_YES_Val       << SDHC_NISTR_CMDC_Pos)
-#define SDHC_NISTR_TRFC_Pos         1            /**< \brief (SDHC_NISTR) Transfer Complete */
-#define SDHC_NISTR_TRFC             (_U_(0x1) << SDHC_NISTR_TRFC_Pos)
-#define   SDHC_NISTR_TRFC_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) Not complete */
-#define   SDHC_NISTR_TRFC_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Command execution is completed */
-#define SDHC_NISTR_TRFC_NO          (SDHC_NISTR_TRFC_NO_Val        << SDHC_NISTR_TRFC_Pos)
-#define SDHC_NISTR_TRFC_YES         (SDHC_NISTR_TRFC_YES_Val       << SDHC_NISTR_TRFC_Pos)
-#define SDHC_NISTR_BLKGE_Pos        2            /**< \brief (SDHC_NISTR) Block Gap Event */
-#define SDHC_NISTR_BLKGE            (_U_(0x1) << SDHC_NISTR_BLKGE_Pos)
-#define   SDHC_NISTR_BLKGE_NO_Val         _U_(0x0)   /**< \brief (SDHC_NISTR) No Block Gap Event */
-#define   SDHC_NISTR_BLKGE_STOP_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) Transaction stopped at block gap */
-#define SDHC_NISTR_BLKGE_NO         (SDHC_NISTR_BLKGE_NO_Val       << SDHC_NISTR_BLKGE_Pos)
-#define SDHC_NISTR_BLKGE_STOP       (SDHC_NISTR_BLKGE_STOP_Val     << SDHC_NISTR_BLKGE_Pos)
-#define SDHC_NISTR_DMAINT_Pos       3            /**< \brief (SDHC_NISTR) DMA Interrupt */
-#define SDHC_NISTR_DMAINT           (_U_(0x1) << SDHC_NISTR_DMAINT_Pos)
-#define   SDHC_NISTR_DMAINT_NO_Val        _U_(0x0)   /**< \brief (SDHC_NISTR) No DMA Interrupt */
-#define   SDHC_NISTR_DMAINT_YES_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) DMA Interrupt is generated */
-#define SDHC_NISTR_DMAINT_NO        (SDHC_NISTR_DMAINT_NO_Val      << SDHC_NISTR_DMAINT_Pos)
-#define SDHC_NISTR_DMAINT_YES       (SDHC_NISTR_DMAINT_YES_Val     << SDHC_NISTR_DMAINT_Pos)
-#define SDHC_NISTR_BWRRDY_Pos       4            /**< \brief (SDHC_NISTR) Buffer Write Ready */
-#define SDHC_NISTR_BWRRDY           (_U_(0x1) << SDHC_NISTR_BWRRDY_Pos)
-#define   SDHC_NISTR_BWRRDY_NO_Val        _U_(0x0)   /**< \brief (SDHC_NISTR) Not ready to write buffer */
-#define   SDHC_NISTR_BWRRDY_YES_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) Ready to write buffer */
-#define SDHC_NISTR_BWRRDY_NO        (SDHC_NISTR_BWRRDY_NO_Val      << SDHC_NISTR_BWRRDY_Pos)
-#define SDHC_NISTR_BWRRDY_YES       (SDHC_NISTR_BWRRDY_YES_Val     << SDHC_NISTR_BWRRDY_Pos)
-#define SDHC_NISTR_BRDRDY_Pos       5            /**< \brief (SDHC_NISTR) Buffer Read Ready */
-#define SDHC_NISTR_BRDRDY           (_U_(0x1) << SDHC_NISTR_BRDRDY_Pos)
-#define   SDHC_NISTR_BRDRDY_NO_Val        _U_(0x0)   /**< \brief (SDHC_NISTR) Not ready to read buffer */
-#define   SDHC_NISTR_BRDRDY_YES_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) Ready to read buffer */
-#define SDHC_NISTR_BRDRDY_NO        (SDHC_NISTR_BRDRDY_NO_Val      << SDHC_NISTR_BRDRDY_Pos)
-#define SDHC_NISTR_BRDRDY_YES       (SDHC_NISTR_BRDRDY_YES_Val     << SDHC_NISTR_BRDRDY_Pos)
-#define SDHC_NISTR_CINS_Pos         6            /**< \brief (SDHC_NISTR) Card Insertion */
-#define SDHC_NISTR_CINS             (_U_(0x1) << SDHC_NISTR_CINS_Pos)
-#define   SDHC_NISTR_CINS_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
-#define   SDHC_NISTR_CINS_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Card inserted */
-#define SDHC_NISTR_CINS_NO          (SDHC_NISTR_CINS_NO_Val        << SDHC_NISTR_CINS_Pos)
-#define SDHC_NISTR_CINS_YES         (SDHC_NISTR_CINS_YES_Val       << SDHC_NISTR_CINS_Pos)
-#define SDHC_NISTR_CREM_Pos         7            /**< \brief (SDHC_NISTR) Card Removal */
-#define SDHC_NISTR_CREM             (_U_(0x1) << SDHC_NISTR_CREM_Pos)
-#define   SDHC_NISTR_CREM_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) Card state stable or Debouncing */
-#define   SDHC_NISTR_CREM_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Card Removed */
-#define SDHC_NISTR_CREM_NO          (SDHC_NISTR_CREM_NO_Val        << SDHC_NISTR_CREM_Pos)
-#define SDHC_NISTR_CREM_YES         (SDHC_NISTR_CREM_YES_Val       << SDHC_NISTR_CREM_Pos)
-#define SDHC_NISTR_CINT_Pos         8            /**< \brief (SDHC_NISTR) Card Interrupt */
-#define SDHC_NISTR_CINT             (_U_(0x1) << SDHC_NISTR_CINT_Pos)
-#define   SDHC_NISTR_CINT_NO_Val          _U_(0x0)   /**< \brief (SDHC_NISTR) No Card Interrupt */
-#define   SDHC_NISTR_CINT_YES_Val         _U_(0x1)   /**< \brief (SDHC_NISTR) Generate Card Interrupt */
-#define SDHC_NISTR_CINT_NO          (SDHC_NISTR_CINT_NO_Val        << SDHC_NISTR_CINT_Pos)
-#define SDHC_NISTR_CINT_YES         (SDHC_NISTR_CINT_YES_Val       << SDHC_NISTR_CINT_Pos)
-#define SDHC_NISTR_ERRINT_Pos       15           /**< \brief (SDHC_NISTR) Error Interrupt */
-#define SDHC_NISTR_ERRINT           (_U_(0x1) << SDHC_NISTR_ERRINT_Pos)
-#define   SDHC_NISTR_ERRINT_NO_Val        _U_(0x0)   /**< \brief (SDHC_NISTR) No Error */
-#define   SDHC_NISTR_ERRINT_YES_Val       _U_(0x1)   /**< \brief (SDHC_NISTR) Error */
-#define SDHC_NISTR_ERRINT_NO        (SDHC_NISTR_ERRINT_NO_Val      << SDHC_NISTR_ERRINT_Pos)
-#define SDHC_NISTR_ERRINT_YES       (SDHC_NISTR_ERRINT_YES_Val     << SDHC_NISTR_ERRINT_Pos)
-#define SDHC_NISTR_MASK             _U_(0x81FF)  /**< \brief (SDHC_NISTR) MASK Register */
-
-// EMMC mode
-#define SDHC_NISTR_EMMC_CMDC_Pos    0            /**< \brief (SDHC_NISTR_EMMC) Command Complete */
-#define SDHC_NISTR_EMMC_CMDC        (_U_(0x1) << SDHC_NISTR_EMMC_CMDC_Pos)
-#define   SDHC_NISTR_EMMC_CMDC_NO_Val     _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) No command complete */
-#define   SDHC_NISTR_EMMC_CMDC_YES_Val    _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Command complete */
-#define SDHC_NISTR_EMMC_CMDC_NO     (SDHC_NISTR_EMMC_CMDC_NO_Val   << SDHC_NISTR_EMMC_CMDC_Pos)
-#define SDHC_NISTR_EMMC_CMDC_YES    (SDHC_NISTR_EMMC_CMDC_YES_Val  << SDHC_NISTR_EMMC_CMDC_Pos)
-#define SDHC_NISTR_EMMC_TRFC_Pos    1            /**< \brief (SDHC_NISTR_EMMC) Transfer Complete */
-#define SDHC_NISTR_EMMC_TRFC        (_U_(0x1) << SDHC_NISTR_EMMC_TRFC_Pos)
-#define   SDHC_NISTR_EMMC_TRFC_NO_Val     _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) Not complete */
-#define   SDHC_NISTR_EMMC_TRFC_YES_Val    _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Command execution is completed */
-#define SDHC_NISTR_EMMC_TRFC_NO     (SDHC_NISTR_EMMC_TRFC_NO_Val   << SDHC_NISTR_EMMC_TRFC_Pos)
-#define SDHC_NISTR_EMMC_TRFC_YES    (SDHC_NISTR_EMMC_TRFC_YES_Val  << SDHC_NISTR_EMMC_TRFC_Pos)
-#define SDHC_NISTR_EMMC_BLKGE_Pos   2            /**< \brief (SDHC_NISTR_EMMC) Block Gap Event */
-#define SDHC_NISTR_EMMC_BLKGE       (_U_(0x1) << SDHC_NISTR_EMMC_BLKGE_Pos)
-#define   SDHC_NISTR_EMMC_BLKGE_NO_Val    _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) No Block Gap Event */
-#define   SDHC_NISTR_EMMC_BLKGE_STOP_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Transaction stopped at block gap */
-#define SDHC_NISTR_EMMC_BLKGE_NO    (SDHC_NISTR_EMMC_BLKGE_NO_Val  << SDHC_NISTR_EMMC_BLKGE_Pos)
-#define SDHC_NISTR_EMMC_BLKGE_STOP  (SDHC_NISTR_EMMC_BLKGE_STOP_Val << SDHC_NISTR_EMMC_BLKGE_Pos)
-#define SDHC_NISTR_EMMC_DMAINT_Pos  3            /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt */
-#define SDHC_NISTR_EMMC_DMAINT      (_U_(0x1) << SDHC_NISTR_EMMC_DMAINT_Pos)
-#define   SDHC_NISTR_EMMC_DMAINT_NO_Val   _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) No DMA Interrupt */
-#define   SDHC_NISTR_EMMC_DMAINT_YES_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt is generated */
-#define SDHC_NISTR_EMMC_DMAINT_NO   (SDHC_NISTR_EMMC_DMAINT_NO_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
-#define SDHC_NISTR_EMMC_DMAINT_YES  (SDHC_NISTR_EMMC_DMAINT_YES_Val << SDHC_NISTR_EMMC_DMAINT_Pos)
-#define SDHC_NISTR_EMMC_BWRRDY_Pos  4            /**< \brief (SDHC_NISTR_EMMC) Buffer Write Ready */
-#define SDHC_NISTR_EMMC_BWRRDY      (_U_(0x1) << SDHC_NISTR_EMMC_BWRRDY_Pos)
-#define   SDHC_NISTR_EMMC_BWRRDY_NO_Val   _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) Not ready to write buffer */
-#define   SDHC_NISTR_EMMC_BWRRDY_YES_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Ready to write buffer */
-#define SDHC_NISTR_EMMC_BWRRDY_NO   (SDHC_NISTR_EMMC_BWRRDY_NO_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
-#define SDHC_NISTR_EMMC_BWRRDY_YES  (SDHC_NISTR_EMMC_BWRRDY_YES_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)
-#define SDHC_NISTR_EMMC_BRDRDY_Pos  5            /**< \brief (SDHC_NISTR_EMMC) Buffer Read Ready */
-#define SDHC_NISTR_EMMC_BRDRDY      (_U_(0x1) << SDHC_NISTR_EMMC_BRDRDY_Pos)
-#define   SDHC_NISTR_EMMC_BRDRDY_NO_Val   _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) Not ready to read buffer */
-#define   SDHC_NISTR_EMMC_BRDRDY_YES_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Ready to read buffer */
-#define SDHC_NISTR_EMMC_BRDRDY_NO   (SDHC_NISTR_EMMC_BRDRDY_NO_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
-#define SDHC_NISTR_EMMC_BRDRDY_YES  (SDHC_NISTR_EMMC_BRDRDY_YES_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)
-#define SDHC_NISTR_EMMC_BOOTAR_Pos  14           /**< \brief (SDHC_NISTR_EMMC) Boot Acknowledge Received */
-#define SDHC_NISTR_EMMC_BOOTAR      (_U_(0x1) << SDHC_NISTR_EMMC_BOOTAR_Pos)
-#define SDHC_NISTR_EMMC_ERRINT_Pos  15           /**< \brief (SDHC_NISTR_EMMC) Error Interrupt */
-#define SDHC_NISTR_EMMC_ERRINT      (_U_(0x1) << SDHC_NISTR_EMMC_ERRINT_Pos)
-#define   SDHC_NISTR_EMMC_ERRINT_NO_Val   _U_(0x0)   /**< \brief (SDHC_NISTR_EMMC) No Error */
-#define   SDHC_NISTR_EMMC_ERRINT_YES_Val  _U_(0x1)   /**< \brief (SDHC_NISTR_EMMC) Error */
-#define SDHC_NISTR_EMMC_ERRINT_NO   (SDHC_NISTR_EMMC_ERRINT_NO_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
-#define SDHC_NISTR_EMMC_ERRINT_YES  (SDHC_NISTR_EMMC_ERRINT_YES_Val << SDHC_NISTR_EMMC_ERRINT_Pos)
-#define SDHC_NISTR_EMMC_MASK        _U_(0xC03F)  /**< \brief (SDHC_NISTR_EMMC) MASK Register */
-
-/* -------- SDHC_EISTR : (SDHC Offset: 0x032) (R/W 16) Error Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error              */
-    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error                  */
-    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error              */
-    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error                */
-    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error                 */
-    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error                     */
-    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error                 */
-    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error                */
-    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error                     */
-    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error                         */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // EMMC mode
-    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error              */
-    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error                  */
-    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error              */
-    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error                */
-    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error                 */
-    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error                     */
-    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error                 */
-    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error                */
-    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error                     */
-    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error                         */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t BOOTAE:1;         /*!< bit:     12  Boot Acknowledge Error             */
-    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
-  } EMMC;                      /*!< Structure used for EMMC                         */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_EISTR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_EISTR_OFFSET           0x032        /**< \brief (SDHC_EISTR offset) Error Interrupt Status */
-#define SDHC_EISTR_RESETVALUE       _U_(0x0000)  /**< \brief (SDHC_EISTR reset_value) Error Interrupt Status */
-
-#define SDHC_EISTR_CMDTEO_Pos       0            /**< \brief (SDHC_EISTR) Command Timeout Error */
-#define SDHC_EISTR_CMDTEO           (_U_(0x1) << SDHC_EISTR_CMDTEO_Pos)
-#define   SDHC_EISTR_CMDTEO_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
-#define   SDHC_EISTR_CMDTEO_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Timeout */
-#define SDHC_EISTR_CMDTEO_NO        (SDHC_EISTR_CMDTEO_NO_Val      << SDHC_EISTR_CMDTEO_Pos)
-#define SDHC_EISTR_CMDTEO_YES       (SDHC_EISTR_CMDTEO_YES_Val     << SDHC_EISTR_CMDTEO_Pos)
-#define SDHC_EISTR_CMDCRC_Pos       1            /**< \brief (SDHC_EISTR) Command CRC Error */
-#define SDHC_EISTR_CMDCRC           (_U_(0x1) << SDHC_EISTR_CMDCRC_Pos)
-#define   SDHC_EISTR_CMDCRC_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
-#define   SDHC_EISTR_CMDCRC_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) CRC Error Generated */
-#define SDHC_EISTR_CMDCRC_NO        (SDHC_EISTR_CMDCRC_NO_Val      << SDHC_EISTR_CMDCRC_Pos)
-#define SDHC_EISTR_CMDCRC_YES       (SDHC_EISTR_CMDCRC_YES_Val     << SDHC_EISTR_CMDCRC_Pos)
-#define SDHC_EISTR_CMDEND_Pos       2            /**< \brief (SDHC_EISTR) Command End Bit Error */
-#define SDHC_EISTR_CMDEND           (_U_(0x1) << SDHC_EISTR_CMDEND_Pos)
-#define   SDHC_EISTR_CMDEND_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No error */
-#define   SDHC_EISTR_CMDEND_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) End Bit Error Generated */
-#define SDHC_EISTR_CMDEND_NO        (SDHC_EISTR_CMDEND_NO_Val      << SDHC_EISTR_CMDEND_Pos)
-#define SDHC_EISTR_CMDEND_YES       (SDHC_EISTR_CMDEND_YES_Val     << SDHC_EISTR_CMDEND_Pos)
-#define SDHC_EISTR_CMDIDX_Pos       3            /**< \brief (SDHC_EISTR) Command Index Error */
-#define SDHC_EISTR_CMDIDX           (_U_(0x1) << SDHC_EISTR_CMDIDX_Pos)
-#define   SDHC_EISTR_CMDIDX_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
-#define   SDHC_EISTR_CMDIDX_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_CMDIDX_NO        (SDHC_EISTR_CMDIDX_NO_Val      << SDHC_EISTR_CMDIDX_Pos)
-#define SDHC_EISTR_CMDIDX_YES       (SDHC_EISTR_CMDIDX_YES_Val     << SDHC_EISTR_CMDIDX_Pos)
-#define SDHC_EISTR_DATTEO_Pos       4            /**< \brief (SDHC_EISTR) Data Timeout Error */
-#define SDHC_EISTR_DATTEO           (_U_(0x1) << SDHC_EISTR_DATTEO_Pos)
-#define   SDHC_EISTR_DATTEO_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
-#define   SDHC_EISTR_DATTEO_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Timeout */
-#define SDHC_EISTR_DATTEO_NO        (SDHC_EISTR_DATTEO_NO_Val      << SDHC_EISTR_DATTEO_Pos)
-#define SDHC_EISTR_DATTEO_YES       (SDHC_EISTR_DATTEO_YES_Val     << SDHC_EISTR_DATTEO_Pos)
-#define SDHC_EISTR_DATCRC_Pos       5            /**< \brief (SDHC_EISTR) Data CRC Error */
-#define SDHC_EISTR_DATCRC           (_U_(0x1) << SDHC_EISTR_DATCRC_Pos)
-#define   SDHC_EISTR_DATCRC_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
-#define   SDHC_EISTR_DATCRC_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_DATCRC_NO        (SDHC_EISTR_DATCRC_NO_Val      << SDHC_EISTR_DATCRC_Pos)
-#define SDHC_EISTR_DATCRC_YES       (SDHC_EISTR_DATCRC_YES_Val     << SDHC_EISTR_DATCRC_Pos)
-#define SDHC_EISTR_DATEND_Pos       6            /**< \brief (SDHC_EISTR) Data End Bit Error */
-#define SDHC_EISTR_DATEND           (_U_(0x1) << SDHC_EISTR_DATEND_Pos)
-#define   SDHC_EISTR_DATEND_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
-#define   SDHC_EISTR_DATEND_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_DATEND_NO        (SDHC_EISTR_DATEND_NO_Val      << SDHC_EISTR_DATEND_Pos)
-#define SDHC_EISTR_DATEND_YES       (SDHC_EISTR_DATEND_YES_Val     << SDHC_EISTR_DATEND_Pos)
-#define SDHC_EISTR_CURLIM_Pos       7            /**< \brief (SDHC_EISTR) Current Limit Error */
-#define SDHC_EISTR_CURLIM           (_U_(0x1) << SDHC_EISTR_CURLIM_Pos)
-#define   SDHC_EISTR_CURLIM_NO_Val        _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
-#define   SDHC_EISTR_CURLIM_YES_Val       _U_(0x1)   /**< \brief (SDHC_EISTR) Power Fail */
-#define SDHC_EISTR_CURLIM_NO        (SDHC_EISTR_CURLIM_NO_Val      << SDHC_EISTR_CURLIM_Pos)
-#define SDHC_EISTR_CURLIM_YES       (SDHC_EISTR_CURLIM_YES_Val     << SDHC_EISTR_CURLIM_Pos)
-#define SDHC_EISTR_ACMD_Pos         8            /**< \brief (SDHC_EISTR) Auto CMD Error */
-#define SDHC_EISTR_ACMD             (_U_(0x1) << SDHC_EISTR_ACMD_Pos)
-#define   SDHC_EISTR_ACMD_NO_Val          _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
-#define   SDHC_EISTR_ACMD_YES_Val         _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_ACMD_NO          (SDHC_EISTR_ACMD_NO_Val        << SDHC_EISTR_ACMD_Pos)
-#define SDHC_EISTR_ACMD_YES         (SDHC_EISTR_ACMD_YES_Val       << SDHC_EISTR_ACMD_Pos)
-#define SDHC_EISTR_ADMA_Pos         9            /**< \brief (SDHC_EISTR) ADMA Error */
-#define SDHC_EISTR_ADMA             (_U_(0x1) << SDHC_EISTR_ADMA_Pos)
-#define   SDHC_EISTR_ADMA_NO_Val          _U_(0x0)   /**< \brief (SDHC_EISTR) No Error */
-#define   SDHC_EISTR_ADMA_YES_Val         _U_(0x1)   /**< \brief (SDHC_EISTR) Error */
-#define SDHC_EISTR_ADMA_NO          (SDHC_EISTR_ADMA_NO_Val        << SDHC_EISTR_ADMA_Pos)
-#define SDHC_EISTR_ADMA_YES         (SDHC_EISTR_ADMA_YES_Val       << SDHC_EISTR_ADMA_Pos)
-#define SDHC_EISTR_MASK             _U_(0x03FF)  /**< \brief (SDHC_EISTR) MASK Register */
-
-// EMMC mode
-#define SDHC_EISTR_EMMC_CMDTEO_Pos  0            /**< \brief (SDHC_EISTR_EMMC) Command Timeout Error */
-#define SDHC_EISTR_EMMC_CMDTEO      (_U_(0x1) << SDHC_EISTR_EMMC_CMDTEO_Pos)
-#define   SDHC_EISTR_EMMC_CMDTEO_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define   SDHC_EISTR_EMMC_CMDTEO_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Timeout */
-#define SDHC_EISTR_EMMC_CMDTEO_NO   (SDHC_EISTR_EMMC_CMDTEO_NO_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
-#define SDHC_EISTR_EMMC_CMDTEO_YES  (SDHC_EISTR_EMMC_CMDTEO_YES_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)
-#define SDHC_EISTR_EMMC_CMDCRC_Pos  1            /**< \brief (SDHC_EISTR_EMMC) Command CRC Error */
-#define SDHC_EISTR_EMMC_CMDCRC      (_U_(0x1) << SDHC_EISTR_EMMC_CMDCRC_Pos)
-#define   SDHC_EISTR_EMMC_CMDCRC_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define   SDHC_EISTR_EMMC_CMDCRC_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) CRC Error Generated */
-#define SDHC_EISTR_EMMC_CMDCRC_NO   (SDHC_EISTR_EMMC_CMDCRC_NO_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
-#define SDHC_EISTR_EMMC_CMDCRC_YES  (SDHC_EISTR_EMMC_CMDCRC_YES_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)
-#define SDHC_EISTR_EMMC_CMDEND_Pos  2            /**< \brief (SDHC_EISTR_EMMC) Command End Bit Error */
-#define SDHC_EISTR_EMMC_CMDEND      (_U_(0x1) << SDHC_EISTR_EMMC_CMDEND_Pos)
-#define   SDHC_EISTR_EMMC_CMDEND_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No error */
-#define   SDHC_EISTR_EMMC_CMDEND_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) End Bit Error Generated */
-#define SDHC_EISTR_EMMC_CMDEND_NO   (SDHC_EISTR_EMMC_CMDEND_NO_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
-#define SDHC_EISTR_EMMC_CMDEND_YES  (SDHC_EISTR_EMMC_CMDEND_YES_Val << SDHC_EISTR_EMMC_CMDEND_Pos)
-#define SDHC_EISTR_EMMC_CMDIDX_Pos  3            /**< \brief (SDHC_EISTR_EMMC) Command Index Error */
-#define SDHC_EISTR_EMMC_CMDIDX      (_U_(0x1) << SDHC_EISTR_EMMC_CMDIDX_Pos)
-#define   SDHC_EISTR_EMMC_CMDIDX_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define   SDHC_EISTR_EMMC_CMDIDX_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_CMDIDX_NO   (SDHC_EISTR_EMMC_CMDIDX_NO_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
-#define SDHC_EISTR_EMMC_CMDIDX_YES  (SDHC_EISTR_EMMC_CMDIDX_YES_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)
-#define SDHC_EISTR_EMMC_DATTEO_Pos  4            /**< \brief (SDHC_EISTR_EMMC) Data Timeout Error */
-#define SDHC_EISTR_EMMC_DATTEO      (_U_(0x1) << SDHC_EISTR_EMMC_DATTEO_Pos)
-#define   SDHC_EISTR_EMMC_DATTEO_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define   SDHC_EISTR_EMMC_DATTEO_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Timeout */
-#define SDHC_EISTR_EMMC_DATTEO_NO   (SDHC_EISTR_EMMC_DATTEO_NO_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
-#define SDHC_EISTR_EMMC_DATTEO_YES  (SDHC_EISTR_EMMC_DATTEO_YES_Val << SDHC_EISTR_EMMC_DATTEO_Pos)
-#define SDHC_EISTR_EMMC_DATCRC_Pos  5            /**< \brief (SDHC_EISTR_EMMC) Data CRC Error */
-#define SDHC_EISTR_EMMC_DATCRC      (_U_(0x1) << SDHC_EISTR_EMMC_DATCRC_Pos)
-#define   SDHC_EISTR_EMMC_DATCRC_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define   SDHC_EISTR_EMMC_DATCRC_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_DATCRC_NO   (SDHC_EISTR_EMMC_DATCRC_NO_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
-#define SDHC_EISTR_EMMC_DATCRC_YES  (SDHC_EISTR_EMMC_DATCRC_YES_Val << SDHC_EISTR_EMMC_DATCRC_Pos)
-#define SDHC_EISTR_EMMC_DATEND_Pos  6            /**< \brief (SDHC_EISTR_EMMC) Data End Bit Error */
-#define SDHC_EISTR_EMMC_DATEND      (_U_(0x1) << SDHC_EISTR_EMMC_DATEND_Pos)
-#define   SDHC_EISTR_EMMC_DATEND_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define   SDHC_EISTR_EMMC_DATEND_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_DATEND_NO   (SDHC_EISTR_EMMC_DATEND_NO_Val << SDHC_EISTR_EMMC_DATEND_Pos)
-#define SDHC_EISTR_EMMC_DATEND_YES  (SDHC_EISTR_EMMC_DATEND_YES_Val << SDHC_EISTR_EMMC_DATEND_Pos)
-#define SDHC_EISTR_EMMC_CURLIM_Pos  7            /**< \brief (SDHC_EISTR_EMMC) Current Limit Error */
-#define SDHC_EISTR_EMMC_CURLIM      (_U_(0x1) << SDHC_EISTR_EMMC_CURLIM_Pos)
-#define   SDHC_EISTR_EMMC_CURLIM_NO_Val   _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define   SDHC_EISTR_EMMC_CURLIM_YES_Val  _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Power Fail */
-#define SDHC_EISTR_EMMC_CURLIM_NO   (SDHC_EISTR_EMMC_CURLIM_NO_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
-#define SDHC_EISTR_EMMC_CURLIM_YES  (SDHC_EISTR_EMMC_CURLIM_YES_Val << SDHC_EISTR_EMMC_CURLIM_Pos)
-#define SDHC_EISTR_EMMC_ACMD_Pos    8            /**< \brief (SDHC_EISTR_EMMC) Auto CMD Error */
-#define SDHC_EISTR_EMMC_ACMD        (_U_(0x1) << SDHC_EISTR_EMMC_ACMD_Pos)
-#define   SDHC_EISTR_EMMC_ACMD_NO_Val     _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define   SDHC_EISTR_EMMC_ACMD_YES_Val    _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_ACMD_NO     (SDHC_EISTR_EMMC_ACMD_NO_Val   << SDHC_EISTR_EMMC_ACMD_Pos)
-#define SDHC_EISTR_EMMC_ACMD_YES    (SDHC_EISTR_EMMC_ACMD_YES_Val  << SDHC_EISTR_EMMC_ACMD_Pos)
-#define SDHC_EISTR_EMMC_ADMA_Pos    9            /**< \brief (SDHC_EISTR_EMMC) ADMA Error */
-#define SDHC_EISTR_EMMC_ADMA        (_U_(0x1) << SDHC_EISTR_EMMC_ADMA_Pos)
-#define   SDHC_EISTR_EMMC_ADMA_NO_Val     _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) No Error */
-#define   SDHC_EISTR_EMMC_ADMA_YES_Val    _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) Error */
-#define SDHC_EISTR_EMMC_ADMA_NO     (SDHC_EISTR_EMMC_ADMA_NO_Val   << SDHC_EISTR_EMMC_ADMA_Pos)
-#define SDHC_EISTR_EMMC_ADMA_YES    (SDHC_EISTR_EMMC_ADMA_YES_Val  << SDHC_EISTR_EMMC_ADMA_Pos)
-#define SDHC_EISTR_EMMC_BOOTAE_Pos  12           /**< \brief (SDHC_EISTR_EMMC) Boot Acknowledge Error */
-#define SDHC_EISTR_EMMC_BOOTAE      (_U_(0x1) << SDHC_EISTR_EMMC_BOOTAE_Pos)
-#define   SDHC_EISTR_EMMC_BOOTAE_0_Val    _U_(0x0)   /**< \brief (SDHC_EISTR_EMMC) FIFO contains at least one byte */
-#define   SDHC_EISTR_EMMC_BOOTAE_1_Val    _U_(0x1)   /**< \brief (SDHC_EISTR_EMMC) FIFO is empty */
-#define SDHC_EISTR_EMMC_BOOTAE_0    (SDHC_EISTR_EMMC_BOOTAE_0_Val  << SDHC_EISTR_EMMC_BOOTAE_Pos)
-#define SDHC_EISTR_EMMC_BOOTAE_1    (SDHC_EISTR_EMMC_BOOTAE_1_Val  << SDHC_EISTR_EMMC_BOOTAE_Pos)
-#define SDHC_EISTR_EMMC_MASK        _U_(0x13FF)  /**< \brief (SDHC_EISTR_EMMC) MASK Register */
-
-/* -------- SDHC_NISTER : (SDHC Offset: 0x034) (R/W 16) Normal Interrupt Status Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMDC:1;           /*!< bit:      0  Command Complete Status Enable     */
-    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete Status Enable    */
-    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event Status Enable      */
-    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt Status Enable        */
-    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready Status Enable   */
-    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready Status Enable    */
-    uint16_t CINS:1;           /*!< bit:      6  Card Insertion Status Enable       */
-    uint16_t CREM:1;           /*!< bit:      7  Card Removal Status Enable         */
-    uint16_t CINT:1;           /*!< bit:      8  Card Interrupt Status Enable       */
-    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // EMMC mode
-    uint16_t CMDC:1;           /*!< bit:      0  Command Complete Status Enable     */
-    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete Status Enable    */
-    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event Status Enable      */
-    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt Status Enable        */
-    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready Status Enable   */
-    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready Status Enable    */
-    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
-    uint16_t BOOTAR:1;         /*!< bit:     14  Boot Acknowledge Received Status Enable */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } EMMC;                      /*!< Structure used for EMMC                         */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_NISTER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_NISTER_OFFSET          0x034        /**< \brief (SDHC_NISTER offset) Normal Interrupt Status Enable */
-#define SDHC_NISTER_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_NISTER reset_value) Normal Interrupt Status Enable */
-
-#define SDHC_NISTER_CMDC_Pos        0            /**< \brief (SDHC_NISTER) Command Complete Status Enable */
-#define SDHC_NISTER_CMDC            (_U_(0x1) << SDHC_NISTER_CMDC_Pos)
-#define   SDHC_NISTER_CMDC_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
-#define   SDHC_NISTER_CMDC_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_CMDC_MASKED     (SDHC_NISTER_CMDC_MASKED_Val   << SDHC_NISTER_CMDC_Pos)
-#define SDHC_NISTER_CMDC_ENABLED    (SDHC_NISTER_CMDC_ENABLED_Val  << SDHC_NISTER_CMDC_Pos)
-#define SDHC_NISTER_TRFC_Pos        1            /**< \brief (SDHC_NISTER) Transfer Complete Status Enable */
-#define SDHC_NISTER_TRFC            (_U_(0x1) << SDHC_NISTER_TRFC_Pos)
-#define   SDHC_NISTER_TRFC_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
-#define   SDHC_NISTER_TRFC_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_TRFC_MASKED     (SDHC_NISTER_TRFC_MASKED_Val   << SDHC_NISTER_TRFC_Pos)
-#define SDHC_NISTER_TRFC_ENABLED    (SDHC_NISTER_TRFC_ENABLED_Val  << SDHC_NISTER_TRFC_Pos)
-#define SDHC_NISTER_BLKGE_Pos       2            /**< \brief (SDHC_NISTER) Block Gap Event Status Enable */
-#define SDHC_NISTER_BLKGE           (_U_(0x1) << SDHC_NISTER_BLKGE_Pos)
-#define   SDHC_NISTER_BLKGE_MASKED_Val    _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
-#define   SDHC_NISTER_BLKGE_ENABLED_Val   _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_BLKGE_MASKED    (SDHC_NISTER_BLKGE_MASKED_Val  << SDHC_NISTER_BLKGE_Pos)
-#define SDHC_NISTER_BLKGE_ENABLED   (SDHC_NISTER_BLKGE_ENABLED_Val << SDHC_NISTER_BLKGE_Pos)
-#define SDHC_NISTER_DMAINT_Pos      3            /**< \brief (SDHC_NISTER) DMA Interrupt Status Enable */
-#define SDHC_NISTER_DMAINT          (_U_(0x1) << SDHC_NISTER_DMAINT_Pos)
-#define   SDHC_NISTER_DMAINT_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
-#define   SDHC_NISTER_DMAINT_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_DMAINT_MASKED   (SDHC_NISTER_DMAINT_MASKED_Val << SDHC_NISTER_DMAINT_Pos)
-#define SDHC_NISTER_DMAINT_ENABLED  (SDHC_NISTER_DMAINT_ENABLED_Val << SDHC_NISTER_DMAINT_Pos)
-#define SDHC_NISTER_BWRRDY_Pos      4            /**< \brief (SDHC_NISTER) Buffer Write Ready Status Enable */
-#define SDHC_NISTER_BWRRDY          (_U_(0x1) << SDHC_NISTER_BWRRDY_Pos)
-#define   SDHC_NISTER_BWRRDY_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
-#define   SDHC_NISTER_BWRRDY_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_BWRRDY_MASKED   (SDHC_NISTER_BWRRDY_MASKED_Val << SDHC_NISTER_BWRRDY_Pos)
-#define SDHC_NISTER_BWRRDY_ENABLED  (SDHC_NISTER_BWRRDY_ENABLED_Val << SDHC_NISTER_BWRRDY_Pos)
-#define SDHC_NISTER_BRDRDY_Pos      5            /**< \brief (SDHC_NISTER) Buffer Read Ready Status Enable */
-#define SDHC_NISTER_BRDRDY          (_U_(0x1) << SDHC_NISTER_BRDRDY_Pos)
-#define   SDHC_NISTER_BRDRDY_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
-#define   SDHC_NISTER_BRDRDY_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_BRDRDY_MASKED   (SDHC_NISTER_BRDRDY_MASKED_Val << SDHC_NISTER_BRDRDY_Pos)
-#define SDHC_NISTER_BRDRDY_ENABLED  (SDHC_NISTER_BRDRDY_ENABLED_Val << SDHC_NISTER_BRDRDY_Pos)
-#define SDHC_NISTER_CINS_Pos        6            /**< \brief (SDHC_NISTER) Card Insertion Status Enable */
-#define SDHC_NISTER_CINS            (_U_(0x1) << SDHC_NISTER_CINS_Pos)
-#define   SDHC_NISTER_CINS_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
-#define   SDHC_NISTER_CINS_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_CINS_MASKED     (SDHC_NISTER_CINS_MASKED_Val   << SDHC_NISTER_CINS_Pos)
-#define SDHC_NISTER_CINS_ENABLED    (SDHC_NISTER_CINS_ENABLED_Val  << SDHC_NISTER_CINS_Pos)
-#define SDHC_NISTER_CREM_Pos        7            /**< \brief (SDHC_NISTER) Card Removal Status Enable */
-#define SDHC_NISTER_CREM            (_U_(0x1) << SDHC_NISTER_CREM_Pos)
-#define   SDHC_NISTER_CREM_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
-#define   SDHC_NISTER_CREM_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_CREM_MASKED     (SDHC_NISTER_CREM_MASKED_Val   << SDHC_NISTER_CREM_Pos)
-#define SDHC_NISTER_CREM_ENABLED    (SDHC_NISTER_CREM_ENABLED_Val  << SDHC_NISTER_CREM_Pos)
-#define SDHC_NISTER_CINT_Pos        8            /**< \brief (SDHC_NISTER) Card Interrupt Status Enable */
-#define SDHC_NISTER_CINT            (_U_(0x1) << SDHC_NISTER_CINT_Pos)
-#define   SDHC_NISTER_CINT_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISTER) Masked */
-#define   SDHC_NISTER_CINT_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISTER) Enabled */
-#define SDHC_NISTER_CINT_MASKED     (SDHC_NISTER_CINT_MASKED_Val   << SDHC_NISTER_CINT_Pos)
-#define SDHC_NISTER_CINT_ENABLED    (SDHC_NISTER_CINT_ENABLED_Val  << SDHC_NISTER_CINT_Pos)
-#define SDHC_NISTER_MASK            _U_(0x01FF)  /**< \brief (SDHC_NISTER) MASK Register */
-
-// EMMC mode
-#define SDHC_NISTER_EMMC_CMDC_Pos   0            /**< \brief (SDHC_NISTER_EMMC) Command Complete Status Enable */
-#define SDHC_NISTER_EMMC_CMDC       (_U_(0x1) << SDHC_NISTER_EMMC_CMDC_Pos)
-#define   SDHC_NISTER_EMMC_CMDC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define   SDHC_NISTER_EMMC_CMDC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_CMDC_MASKED (SDHC_NISTER_EMMC_CMDC_MASKED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
-#define SDHC_NISTER_EMMC_CMDC_ENABLED (SDHC_NISTER_EMMC_CMDC_ENABLED_Val << SDHC_NISTER_EMMC_CMDC_Pos)
-#define SDHC_NISTER_EMMC_TRFC_Pos   1            /**< \brief (SDHC_NISTER_EMMC) Transfer Complete Status Enable */
-#define SDHC_NISTER_EMMC_TRFC       (_U_(0x1) << SDHC_NISTER_EMMC_TRFC_Pos)
-#define   SDHC_NISTER_EMMC_TRFC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define   SDHC_NISTER_EMMC_TRFC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_TRFC_MASKED (SDHC_NISTER_EMMC_TRFC_MASKED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
-#define SDHC_NISTER_EMMC_TRFC_ENABLED (SDHC_NISTER_EMMC_TRFC_ENABLED_Val << SDHC_NISTER_EMMC_TRFC_Pos)
-#define SDHC_NISTER_EMMC_BLKGE_Pos  2            /**< \brief (SDHC_NISTER_EMMC) Block Gap Event Status Enable */
-#define SDHC_NISTER_EMMC_BLKGE      (_U_(0x1) << SDHC_NISTER_EMMC_BLKGE_Pos)
-#define   SDHC_NISTER_EMMC_BLKGE_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define   SDHC_NISTER_EMMC_BLKGE_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_BLKGE_MASKED (SDHC_NISTER_EMMC_BLKGE_MASKED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
-#define SDHC_NISTER_EMMC_BLKGE_ENABLED (SDHC_NISTER_EMMC_BLKGE_ENABLED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)
-#define SDHC_NISTER_EMMC_DMAINT_Pos 3            /**< \brief (SDHC_NISTER_EMMC) DMA Interrupt Status Enable */
-#define SDHC_NISTER_EMMC_DMAINT     (_U_(0x1) << SDHC_NISTER_EMMC_DMAINT_Pos)
-#define   SDHC_NISTER_EMMC_DMAINT_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define   SDHC_NISTER_EMMC_DMAINT_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_DMAINT_MASKED (SDHC_NISTER_EMMC_DMAINT_MASKED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
-#define SDHC_NISTER_EMMC_DMAINT_ENABLED (SDHC_NISTER_EMMC_DMAINT_ENABLED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)
-#define SDHC_NISTER_EMMC_BWRRDY_Pos 4            /**< \brief (SDHC_NISTER_EMMC) Buffer Write Ready Status Enable */
-#define SDHC_NISTER_EMMC_BWRRDY     (_U_(0x1) << SDHC_NISTER_EMMC_BWRRDY_Pos)
-#define   SDHC_NISTER_EMMC_BWRRDY_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define   SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_BWRRDY_MASKED (SDHC_NISTER_EMMC_BWRRDY_MASKED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
-#define SDHC_NISTER_EMMC_BWRRDY_ENABLED (SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)
-#define SDHC_NISTER_EMMC_BRDRDY_Pos 5            /**< \brief (SDHC_NISTER_EMMC) Buffer Read Ready Status Enable */
-#define SDHC_NISTER_EMMC_BRDRDY     (_U_(0x1) << SDHC_NISTER_EMMC_BRDRDY_Pos)
-#define   SDHC_NISTER_EMMC_BRDRDY_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISTER_EMMC) Masked */
-#define   SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISTER_EMMC) Enabled */
-#define SDHC_NISTER_EMMC_BRDRDY_MASKED (SDHC_NISTER_EMMC_BRDRDY_MASKED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
-#define SDHC_NISTER_EMMC_BRDRDY_ENABLED (SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)
-#define SDHC_NISTER_EMMC_BOOTAR_Pos 14           /**< \brief (SDHC_NISTER_EMMC) Boot Acknowledge Received Status Enable */
-#define SDHC_NISTER_EMMC_BOOTAR     (_U_(0x1) << SDHC_NISTER_EMMC_BOOTAR_Pos)
-#define SDHC_NISTER_EMMC_MASK       _U_(0x403F)  /**< \brief (SDHC_NISTER_EMMC) MASK Register */
-
-/* -------- SDHC_EISTER : (SDHC Offset: 0x036) (R/W 16) Error Interrupt Status Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error Status Enable */
-    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error Status Enable    */
-    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error Status Enable */
-    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error Status Enable  */
-    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error Status Enable   */
-    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error Status Enable       */
-    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error Status Enable   */
-    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error Status Enable  */
-    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error Status Enable       */
-    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error Status Enable           */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // EMMC mode
-    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error Status Enable */
-    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error Status Enable    */
-    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error Status Enable */
-    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error Status Enable  */
-    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error Status Enable   */
-    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error Status Enable       */
-    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error Status Enable   */
-    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error Status Enable  */
-    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error Status Enable       */
-    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error Status Enable           */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t BOOTAE:1;         /*!< bit:     12  Boot Acknowledge Error Status Enable */
-    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
-  } EMMC;                      /*!< Structure used for EMMC                         */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_EISTER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_EISTER_OFFSET          0x036        /**< \brief (SDHC_EISTER offset) Error Interrupt Status Enable */
-#define SDHC_EISTER_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_EISTER reset_value) Error Interrupt Status Enable */
-
-#define SDHC_EISTER_CMDTEO_Pos      0            /**< \brief (SDHC_EISTER) Command Timeout Error Status Enable */
-#define SDHC_EISTER_CMDTEO          (_U_(0x1) << SDHC_EISTER_CMDTEO_Pos)
-#define   SDHC_EISTER_CMDTEO_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_CMDTEO_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CMDTEO_MASKED   (SDHC_EISTER_CMDTEO_MASKED_Val << SDHC_EISTER_CMDTEO_Pos)
-#define SDHC_EISTER_CMDTEO_ENABLED  (SDHC_EISTER_CMDTEO_ENABLED_Val << SDHC_EISTER_CMDTEO_Pos)
-#define SDHC_EISTER_CMDCRC_Pos      1            /**< \brief (SDHC_EISTER) Command CRC Error Status Enable */
-#define SDHC_EISTER_CMDCRC          (_U_(0x1) << SDHC_EISTER_CMDCRC_Pos)
-#define   SDHC_EISTER_CMDCRC_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_CMDCRC_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CMDCRC_MASKED   (SDHC_EISTER_CMDCRC_MASKED_Val << SDHC_EISTER_CMDCRC_Pos)
-#define SDHC_EISTER_CMDCRC_ENABLED  (SDHC_EISTER_CMDCRC_ENABLED_Val << SDHC_EISTER_CMDCRC_Pos)
-#define SDHC_EISTER_CMDEND_Pos      2            /**< \brief (SDHC_EISTER) Command End Bit Error Status Enable */
-#define SDHC_EISTER_CMDEND          (_U_(0x1) << SDHC_EISTER_CMDEND_Pos)
-#define   SDHC_EISTER_CMDEND_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_CMDEND_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CMDEND_MASKED   (SDHC_EISTER_CMDEND_MASKED_Val << SDHC_EISTER_CMDEND_Pos)
-#define SDHC_EISTER_CMDEND_ENABLED  (SDHC_EISTER_CMDEND_ENABLED_Val << SDHC_EISTER_CMDEND_Pos)
-#define SDHC_EISTER_CMDIDX_Pos      3            /**< \brief (SDHC_EISTER) Command Index Error Status Enable */
-#define SDHC_EISTER_CMDIDX          (_U_(0x1) << SDHC_EISTER_CMDIDX_Pos)
-#define   SDHC_EISTER_CMDIDX_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_CMDIDX_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CMDIDX_MASKED   (SDHC_EISTER_CMDIDX_MASKED_Val << SDHC_EISTER_CMDIDX_Pos)
-#define SDHC_EISTER_CMDIDX_ENABLED  (SDHC_EISTER_CMDIDX_ENABLED_Val << SDHC_EISTER_CMDIDX_Pos)
-#define SDHC_EISTER_DATTEO_Pos      4            /**< \brief (SDHC_EISTER) Data Timeout Error Status Enable */
-#define SDHC_EISTER_DATTEO          (_U_(0x1) << SDHC_EISTER_DATTEO_Pos)
-#define   SDHC_EISTER_DATTEO_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_DATTEO_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_DATTEO_MASKED   (SDHC_EISTER_DATTEO_MASKED_Val << SDHC_EISTER_DATTEO_Pos)
-#define SDHC_EISTER_DATTEO_ENABLED  (SDHC_EISTER_DATTEO_ENABLED_Val << SDHC_EISTER_DATTEO_Pos)
-#define SDHC_EISTER_DATCRC_Pos      5            /**< \brief (SDHC_EISTER) Data CRC Error Status Enable */
-#define SDHC_EISTER_DATCRC          (_U_(0x1) << SDHC_EISTER_DATCRC_Pos)
-#define   SDHC_EISTER_DATCRC_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_DATCRC_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_DATCRC_MASKED   (SDHC_EISTER_DATCRC_MASKED_Val << SDHC_EISTER_DATCRC_Pos)
-#define SDHC_EISTER_DATCRC_ENABLED  (SDHC_EISTER_DATCRC_ENABLED_Val << SDHC_EISTER_DATCRC_Pos)
-#define SDHC_EISTER_DATEND_Pos      6            /**< \brief (SDHC_EISTER) Data End Bit Error Status Enable */
-#define SDHC_EISTER_DATEND          (_U_(0x1) << SDHC_EISTER_DATEND_Pos)
-#define   SDHC_EISTER_DATEND_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_DATEND_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_DATEND_MASKED   (SDHC_EISTER_DATEND_MASKED_Val << SDHC_EISTER_DATEND_Pos)
-#define SDHC_EISTER_DATEND_ENABLED  (SDHC_EISTER_DATEND_ENABLED_Val << SDHC_EISTER_DATEND_Pos)
-#define SDHC_EISTER_CURLIM_Pos      7            /**< \brief (SDHC_EISTER) Current Limit Error Status Enable */
-#define SDHC_EISTER_CURLIM          (_U_(0x1) << SDHC_EISTER_CURLIM_Pos)
-#define   SDHC_EISTER_CURLIM_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_CURLIM_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_CURLIM_MASKED   (SDHC_EISTER_CURLIM_MASKED_Val << SDHC_EISTER_CURLIM_Pos)
-#define SDHC_EISTER_CURLIM_ENABLED  (SDHC_EISTER_CURLIM_ENABLED_Val << SDHC_EISTER_CURLIM_Pos)
-#define SDHC_EISTER_ACMD_Pos        8            /**< \brief (SDHC_EISTER) Auto CMD Error Status Enable */
-#define SDHC_EISTER_ACMD            (_U_(0x1) << SDHC_EISTER_ACMD_Pos)
-#define   SDHC_EISTER_ACMD_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_ACMD_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_ACMD_MASKED     (SDHC_EISTER_ACMD_MASKED_Val   << SDHC_EISTER_ACMD_Pos)
-#define SDHC_EISTER_ACMD_ENABLED    (SDHC_EISTER_ACMD_ENABLED_Val  << SDHC_EISTER_ACMD_Pos)
-#define SDHC_EISTER_ADMA_Pos        9            /**< \brief (SDHC_EISTER) ADMA Error Status Enable */
-#define SDHC_EISTER_ADMA            (_U_(0x1) << SDHC_EISTER_ADMA_Pos)
-#define   SDHC_EISTER_ADMA_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_EISTER) Masked */
-#define   SDHC_EISTER_ADMA_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_EISTER) Enabled */
-#define SDHC_EISTER_ADMA_MASKED     (SDHC_EISTER_ADMA_MASKED_Val   << SDHC_EISTER_ADMA_Pos)
-#define SDHC_EISTER_ADMA_ENABLED    (SDHC_EISTER_ADMA_ENABLED_Val  << SDHC_EISTER_ADMA_Pos)
-#define SDHC_EISTER_MASK            _U_(0x03FF)  /**< \brief (SDHC_EISTER) MASK Register */
-
-// EMMC mode
-#define SDHC_EISTER_EMMC_CMDTEO_Pos 0            /**< \brief (SDHC_EISTER_EMMC) Command Timeout Error Status Enable */
-#define SDHC_EISTER_EMMC_CMDTEO     (_U_(0x1) << SDHC_EISTER_EMMC_CMDTEO_Pos)
-#define   SDHC_EISTER_EMMC_CMDTEO_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CMDTEO_MASKED (SDHC_EISTER_EMMC_CMDTEO_MASKED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
-#define SDHC_EISTER_EMMC_CMDTEO_ENABLED (SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)
-#define SDHC_EISTER_EMMC_CMDCRC_Pos 1            /**< \brief (SDHC_EISTER_EMMC) Command CRC Error Status Enable */
-#define SDHC_EISTER_EMMC_CMDCRC     (_U_(0x1) << SDHC_EISTER_EMMC_CMDCRC_Pos)
-#define   SDHC_EISTER_EMMC_CMDCRC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CMDCRC_MASKED (SDHC_EISTER_EMMC_CMDCRC_MASKED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
-#define SDHC_EISTER_EMMC_CMDCRC_ENABLED (SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)
-#define SDHC_EISTER_EMMC_CMDEND_Pos 2            /**< \brief (SDHC_EISTER_EMMC) Command End Bit Error Status Enable */
-#define SDHC_EISTER_EMMC_CMDEND     (_U_(0x1) << SDHC_EISTER_EMMC_CMDEND_Pos)
-#define   SDHC_EISTER_EMMC_CMDEND_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_CMDEND_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CMDEND_MASKED (SDHC_EISTER_EMMC_CMDEND_MASKED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
-#define SDHC_EISTER_EMMC_CMDEND_ENABLED (SDHC_EISTER_EMMC_CMDEND_ENABLED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)
-#define SDHC_EISTER_EMMC_CMDIDX_Pos 3            /**< \brief (SDHC_EISTER_EMMC) Command Index Error Status Enable */
-#define SDHC_EISTER_EMMC_CMDIDX     (_U_(0x1) << SDHC_EISTER_EMMC_CMDIDX_Pos)
-#define   SDHC_EISTER_EMMC_CMDIDX_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CMDIDX_MASKED (SDHC_EISTER_EMMC_CMDIDX_MASKED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
-#define SDHC_EISTER_EMMC_CMDIDX_ENABLED (SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)
-#define SDHC_EISTER_EMMC_DATTEO_Pos 4            /**< \brief (SDHC_EISTER_EMMC) Data Timeout Error Status Enable */
-#define SDHC_EISTER_EMMC_DATTEO     (_U_(0x1) << SDHC_EISTER_EMMC_DATTEO_Pos)
-#define   SDHC_EISTER_EMMC_DATTEO_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_DATTEO_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_DATTEO_MASKED (SDHC_EISTER_EMMC_DATTEO_MASKED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
-#define SDHC_EISTER_EMMC_DATTEO_ENABLED (SDHC_EISTER_EMMC_DATTEO_ENABLED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)
-#define SDHC_EISTER_EMMC_DATCRC_Pos 5            /**< \brief (SDHC_EISTER_EMMC) Data CRC Error Status Enable */
-#define SDHC_EISTER_EMMC_DATCRC     (_U_(0x1) << SDHC_EISTER_EMMC_DATCRC_Pos)
-#define   SDHC_EISTER_EMMC_DATCRC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_DATCRC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_DATCRC_MASKED (SDHC_EISTER_EMMC_DATCRC_MASKED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
-#define SDHC_EISTER_EMMC_DATCRC_ENABLED (SDHC_EISTER_EMMC_DATCRC_ENABLED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)
-#define SDHC_EISTER_EMMC_DATEND_Pos 6            /**< \brief (SDHC_EISTER_EMMC) Data End Bit Error Status Enable */
-#define SDHC_EISTER_EMMC_DATEND     (_U_(0x1) << SDHC_EISTER_EMMC_DATEND_Pos)
-#define   SDHC_EISTER_EMMC_DATEND_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_DATEND_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_DATEND_MASKED (SDHC_EISTER_EMMC_DATEND_MASKED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
-#define SDHC_EISTER_EMMC_DATEND_ENABLED (SDHC_EISTER_EMMC_DATEND_ENABLED_Val << SDHC_EISTER_EMMC_DATEND_Pos)
-#define SDHC_EISTER_EMMC_CURLIM_Pos 7            /**< \brief (SDHC_EISTER_EMMC) Current Limit Error Status Enable */
-#define SDHC_EISTER_EMMC_CURLIM     (_U_(0x1) << SDHC_EISTER_EMMC_CURLIM_Pos)
-#define   SDHC_EISTER_EMMC_CURLIM_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_CURLIM_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_CURLIM_MASKED (SDHC_EISTER_EMMC_CURLIM_MASKED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
-#define SDHC_EISTER_EMMC_CURLIM_ENABLED (SDHC_EISTER_EMMC_CURLIM_ENABLED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)
-#define SDHC_EISTER_EMMC_ACMD_Pos   8            /**< \brief (SDHC_EISTER_EMMC) Auto CMD Error Status Enable */
-#define SDHC_EISTER_EMMC_ACMD       (_U_(0x1) << SDHC_EISTER_EMMC_ACMD_Pos)
-#define   SDHC_EISTER_EMMC_ACMD_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_ACMD_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_ACMD_MASKED (SDHC_EISTER_EMMC_ACMD_MASKED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
-#define SDHC_EISTER_EMMC_ACMD_ENABLED (SDHC_EISTER_EMMC_ACMD_ENABLED_Val << SDHC_EISTER_EMMC_ACMD_Pos)
-#define SDHC_EISTER_EMMC_ADMA_Pos   9            /**< \brief (SDHC_EISTER_EMMC) ADMA Error Status Enable */
-#define SDHC_EISTER_EMMC_ADMA       (_U_(0x1) << SDHC_EISTER_EMMC_ADMA_Pos)
-#define   SDHC_EISTER_EMMC_ADMA_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISTER_EMMC) Masked */
-#define   SDHC_EISTER_EMMC_ADMA_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISTER_EMMC) Enabled */
-#define SDHC_EISTER_EMMC_ADMA_MASKED (SDHC_EISTER_EMMC_ADMA_MASKED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
-#define SDHC_EISTER_EMMC_ADMA_ENABLED (SDHC_EISTER_EMMC_ADMA_ENABLED_Val << SDHC_EISTER_EMMC_ADMA_Pos)
-#define SDHC_EISTER_EMMC_BOOTAE_Pos 12           /**< \brief (SDHC_EISTER_EMMC) Boot Acknowledge Error Status Enable */
-#define SDHC_EISTER_EMMC_BOOTAE     (_U_(0x1) << SDHC_EISTER_EMMC_BOOTAE_Pos)
-#define SDHC_EISTER_EMMC_MASK       _U_(0x13FF)  /**< \brief (SDHC_EISTER_EMMC) MASK Register */
-
-/* -------- SDHC_NISIER : (SDHC Offset: 0x038) (R/W 16) Normal Interrupt Signal Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMDC:1;           /*!< bit:      0  Command Complete Signal Enable     */
-    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete Signal Enable    */
-    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event Signal Enable      */
-    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt Signal Enable        */
-    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready Signal Enable   */
-    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready Signal Enable    */
-    uint16_t CINS:1;           /*!< bit:      6  Card Insertion Signal Enable       */
-    uint16_t CREM:1;           /*!< bit:      7  Card Removal Signal Enable         */
-    uint16_t CINT:1;           /*!< bit:      8  Card Interrupt Signal Enable       */
-    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // EMMC mode
-    uint16_t CMDC:1;           /*!< bit:      0  Command Complete Signal Enable     */
-    uint16_t TRFC:1;           /*!< bit:      1  Transfer Complete Signal Enable    */
-    uint16_t BLKGE:1;          /*!< bit:      2  Block Gap Event Signal Enable      */
-    uint16_t DMAINT:1;         /*!< bit:      3  DMA Interrupt Signal Enable        */
-    uint16_t BWRRDY:1;         /*!< bit:      4  Buffer Write Ready Signal Enable   */
-    uint16_t BRDRDY:1;         /*!< bit:      5  Buffer Read Ready Signal Enable    */
-    uint16_t :8;               /*!< bit:  6..13  Reserved                           */
-    uint16_t BOOTAR:1;         /*!< bit:     14  Boot Acknowledge Received Signal Enable */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } EMMC;                      /*!< Structure used for EMMC                         */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_NISIER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_NISIER_OFFSET          0x038        /**< \brief (SDHC_NISIER offset) Normal Interrupt Signal Enable */
-#define SDHC_NISIER_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_NISIER reset_value) Normal Interrupt Signal Enable */
-
-#define SDHC_NISIER_CMDC_Pos        0            /**< \brief (SDHC_NISIER) Command Complete Signal Enable */
-#define SDHC_NISIER_CMDC            (_U_(0x1) << SDHC_NISIER_CMDC_Pos)
-#define   SDHC_NISIER_CMDC_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
-#define   SDHC_NISIER_CMDC_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_CMDC_MASKED     (SDHC_NISIER_CMDC_MASKED_Val   << SDHC_NISIER_CMDC_Pos)
-#define SDHC_NISIER_CMDC_ENABLED    (SDHC_NISIER_CMDC_ENABLED_Val  << SDHC_NISIER_CMDC_Pos)
-#define SDHC_NISIER_TRFC_Pos        1            /**< \brief (SDHC_NISIER) Transfer Complete Signal Enable */
-#define SDHC_NISIER_TRFC            (_U_(0x1) << SDHC_NISIER_TRFC_Pos)
-#define   SDHC_NISIER_TRFC_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
-#define   SDHC_NISIER_TRFC_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_TRFC_MASKED     (SDHC_NISIER_TRFC_MASKED_Val   << SDHC_NISIER_TRFC_Pos)
-#define SDHC_NISIER_TRFC_ENABLED    (SDHC_NISIER_TRFC_ENABLED_Val  << SDHC_NISIER_TRFC_Pos)
-#define SDHC_NISIER_BLKGE_Pos       2            /**< \brief (SDHC_NISIER) Block Gap Event Signal Enable */
-#define SDHC_NISIER_BLKGE           (_U_(0x1) << SDHC_NISIER_BLKGE_Pos)
-#define   SDHC_NISIER_BLKGE_MASKED_Val    _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
-#define   SDHC_NISIER_BLKGE_ENABLED_Val   _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_BLKGE_MASKED    (SDHC_NISIER_BLKGE_MASKED_Val  << SDHC_NISIER_BLKGE_Pos)
-#define SDHC_NISIER_BLKGE_ENABLED   (SDHC_NISIER_BLKGE_ENABLED_Val << SDHC_NISIER_BLKGE_Pos)
-#define SDHC_NISIER_DMAINT_Pos      3            /**< \brief (SDHC_NISIER) DMA Interrupt Signal Enable */
-#define SDHC_NISIER_DMAINT          (_U_(0x1) << SDHC_NISIER_DMAINT_Pos)
-#define   SDHC_NISIER_DMAINT_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
-#define   SDHC_NISIER_DMAINT_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_DMAINT_MASKED   (SDHC_NISIER_DMAINT_MASKED_Val << SDHC_NISIER_DMAINT_Pos)
-#define SDHC_NISIER_DMAINT_ENABLED  (SDHC_NISIER_DMAINT_ENABLED_Val << SDHC_NISIER_DMAINT_Pos)
-#define SDHC_NISIER_BWRRDY_Pos      4            /**< \brief (SDHC_NISIER) Buffer Write Ready Signal Enable */
-#define SDHC_NISIER_BWRRDY          (_U_(0x1) << SDHC_NISIER_BWRRDY_Pos)
-#define   SDHC_NISIER_BWRRDY_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
-#define   SDHC_NISIER_BWRRDY_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_BWRRDY_MASKED   (SDHC_NISIER_BWRRDY_MASKED_Val << SDHC_NISIER_BWRRDY_Pos)
-#define SDHC_NISIER_BWRRDY_ENABLED  (SDHC_NISIER_BWRRDY_ENABLED_Val << SDHC_NISIER_BWRRDY_Pos)
-#define SDHC_NISIER_BRDRDY_Pos      5            /**< \brief (SDHC_NISIER) Buffer Read Ready Signal Enable */
-#define SDHC_NISIER_BRDRDY          (_U_(0x1) << SDHC_NISIER_BRDRDY_Pos)
-#define   SDHC_NISIER_BRDRDY_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
-#define   SDHC_NISIER_BRDRDY_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_BRDRDY_MASKED   (SDHC_NISIER_BRDRDY_MASKED_Val << SDHC_NISIER_BRDRDY_Pos)
-#define SDHC_NISIER_BRDRDY_ENABLED  (SDHC_NISIER_BRDRDY_ENABLED_Val << SDHC_NISIER_BRDRDY_Pos)
-#define SDHC_NISIER_CINS_Pos        6            /**< \brief (SDHC_NISIER) Card Insertion Signal Enable */
-#define SDHC_NISIER_CINS            (_U_(0x1) << SDHC_NISIER_CINS_Pos)
-#define   SDHC_NISIER_CINS_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
-#define   SDHC_NISIER_CINS_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_CINS_MASKED     (SDHC_NISIER_CINS_MASKED_Val   << SDHC_NISIER_CINS_Pos)
-#define SDHC_NISIER_CINS_ENABLED    (SDHC_NISIER_CINS_ENABLED_Val  << SDHC_NISIER_CINS_Pos)
-#define SDHC_NISIER_CREM_Pos        7            /**< \brief (SDHC_NISIER) Card Removal Signal Enable */
-#define SDHC_NISIER_CREM            (_U_(0x1) << SDHC_NISIER_CREM_Pos)
-#define   SDHC_NISIER_CREM_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
-#define   SDHC_NISIER_CREM_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_CREM_MASKED     (SDHC_NISIER_CREM_MASKED_Val   << SDHC_NISIER_CREM_Pos)
-#define SDHC_NISIER_CREM_ENABLED    (SDHC_NISIER_CREM_ENABLED_Val  << SDHC_NISIER_CREM_Pos)
-#define SDHC_NISIER_CINT_Pos        8            /**< \brief (SDHC_NISIER) Card Interrupt Signal Enable */
-#define SDHC_NISIER_CINT            (_U_(0x1) << SDHC_NISIER_CINT_Pos)
-#define   SDHC_NISIER_CINT_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_NISIER) Masked */
-#define   SDHC_NISIER_CINT_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_NISIER) Enabled */
-#define SDHC_NISIER_CINT_MASKED     (SDHC_NISIER_CINT_MASKED_Val   << SDHC_NISIER_CINT_Pos)
-#define SDHC_NISIER_CINT_ENABLED    (SDHC_NISIER_CINT_ENABLED_Val  << SDHC_NISIER_CINT_Pos)
-#define SDHC_NISIER_MASK            _U_(0x01FF)  /**< \brief (SDHC_NISIER) MASK Register */
-
-// EMMC mode
-#define SDHC_NISIER_EMMC_CMDC_Pos   0            /**< \brief (SDHC_NISIER_EMMC) Command Complete Signal Enable */
-#define SDHC_NISIER_EMMC_CMDC       (_U_(0x1) << SDHC_NISIER_EMMC_CMDC_Pos)
-#define   SDHC_NISIER_EMMC_CMDC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define   SDHC_NISIER_EMMC_CMDC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_CMDC_MASKED (SDHC_NISIER_EMMC_CMDC_MASKED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
-#define SDHC_NISIER_EMMC_CMDC_ENABLED (SDHC_NISIER_EMMC_CMDC_ENABLED_Val << SDHC_NISIER_EMMC_CMDC_Pos)
-#define SDHC_NISIER_EMMC_TRFC_Pos   1            /**< \brief (SDHC_NISIER_EMMC) Transfer Complete Signal Enable */
-#define SDHC_NISIER_EMMC_TRFC       (_U_(0x1) << SDHC_NISIER_EMMC_TRFC_Pos)
-#define   SDHC_NISIER_EMMC_TRFC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define   SDHC_NISIER_EMMC_TRFC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_TRFC_MASKED (SDHC_NISIER_EMMC_TRFC_MASKED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
-#define SDHC_NISIER_EMMC_TRFC_ENABLED (SDHC_NISIER_EMMC_TRFC_ENABLED_Val << SDHC_NISIER_EMMC_TRFC_Pos)
-#define SDHC_NISIER_EMMC_BLKGE_Pos  2            /**< \brief (SDHC_NISIER_EMMC) Block Gap Event Signal Enable */
-#define SDHC_NISIER_EMMC_BLKGE      (_U_(0x1) << SDHC_NISIER_EMMC_BLKGE_Pos)
-#define   SDHC_NISIER_EMMC_BLKGE_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define   SDHC_NISIER_EMMC_BLKGE_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_BLKGE_MASKED (SDHC_NISIER_EMMC_BLKGE_MASKED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
-#define SDHC_NISIER_EMMC_BLKGE_ENABLED (SDHC_NISIER_EMMC_BLKGE_ENABLED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)
-#define SDHC_NISIER_EMMC_DMAINT_Pos 3            /**< \brief (SDHC_NISIER_EMMC) DMA Interrupt Signal Enable */
-#define SDHC_NISIER_EMMC_DMAINT     (_U_(0x1) << SDHC_NISIER_EMMC_DMAINT_Pos)
-#define   SDHC_NISIER_EMMC_DMAINT_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define   SDHC_NISIER_EMMC_DMAINT_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_DMAINT_MASKED (SDHC_NISIER_EMMC_DMAINT_MASKED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
-#define SDHC_NISIER_EMMC_DMAINT_ENABLED (SDHC_NISIER_EMMC_DMAINT_ENABLED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)
-#define SDHC_NISIER_EMMC_BWRRDY_Pos 4            /**< \brief (SDHC_NISIER_EMMC) Buffer Write Ready Signal Enable */
-#define SDHC_NISIER_EMMC_BWRRDY     (_U_(0x1) << SDHC_NISIER_EMMC_BWRRDY_Pos)
-#define   SDHC_NISIER_EMMC_BWRRDY_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define   SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_BWRRDY_MASKED (SDHC_NISIER_EMMC_BWRRDY_MASKED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
-#define SDHC_NISIER_EMMC_BWRRDY_ENABLED (SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)
-#define SDHC_NISIER_EMMC_BRDRDY_Pos 5            /**< \brief (SDHC_NISIER_EMMC) Buffer Read Ready Signal Enable */
-#define SDHC_NISIER_EMMC_BRDRDY     (_U_(0x1) << SDHC_NISIER_EMMC_BRDRDY_Pos)
-#define   SDHC_NISIER_EMMC_BRDRDY_MASKED_Val _U_(0x0)   /**< \brief (SDHC_NISIER_EMMC) Masked */
-#define   SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_NISIER_EMMC) Enabled */
-#define SDHC_NISIER_EMMC_BRDRDY_MASKED (SDHC_NISIER_EMMC_BRDRDY_MASKED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
-#define SDHC_NISIER_EMMC_BRDRDY_ENABLED (SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)
-#define SDHC_NISIER_EMMC_BOOTAR_Pos 14           /**< \brief (SDHC_NISIER_EMMC) Boot Acknowledge Received Signal Enable */
-#define SDHC_NISIER_EMMC_BOOTAR     (_U_(0x1) << SDHC_NISIER_EMMC_BOOTAR_Pos)
-#define SDHC_NISIER_EMMC_MASK       _U_(0x403F)  /**< \brief (SDHC_NISIER_EMMC) MASK Register */
-
-/* -------- SDHC_EISIER : (SDHC Offset: 0x03A) (R/W 16) Error Interrupt Signal Enable -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error Signal Enable */
-    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error Signal Enable    */
-    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error Signal Enable */
-    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error Signal Enable  */
-    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error Signal Enable   */
-    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error Signal Enable       */
-    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error Signal Enable   */
-    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error Signal Enable  */
-    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error Signal Enable       */
-    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error Signal Enable           */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // EMMC mode
-    uint16_t CMDTEO:1;         /*!< bit:      0  Command Timeout Error Signal Enable */
-    uint16_t CMDCRC:1;         /*!< bit:      1  Command CRC Error Signal Enable    */
-    uint16_t CMDEND:1;         /*!< bit:      2  Command End Bit Error Signal Enable */
-    uint16_t CMDIDX:1;         /*!< bit:      3  Command Index Error Signal Enable  */
-    uint16_t DATTEO:1;         /*!< bit:      4  Data Timeout Error Signal Enable   */
-    uint16_t DATCRC:1;         /*!< bit:      5  Data CRC Error Signal Enable       */
-    uint16_t DATEND:1;         /*!< bit:      6  Data End Bit Error Signal Enable   */
-    uint16_t CURLIM:1;         /*!< bit:      7  Current Limit Error Signal Enable  */
-    uint16_t ACMD:1;           /*!< bit:      8  Auto CMD Error Signal Enable       */
-    uint16_t ADMA:1;           /*!< bit:      9  ADMA Error Signal Enable           */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t BOOTAE:1;         /*!< bit:     12  Boot Acknowledge Error Signal Enable */
-    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
-  } EMMC;                      /*!< Structure used for EMMC                         */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_EISIER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_EISIER_OFFSET          0x03A        /**< \brief (SDHC_EISIER offset) Error Interrupt Signal Enable */
-#define SDHC_EISIER_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_EISIER reset_value) Error Interrupt Signal Enable */
-
-#define SDHC_EISIER_CMDTEO_Pos      0            /**< \brief (SDHC_EISIER) Command Timeout Error Signal Enable */
-#define SDHC_EISIER_CMDTEO          (_U_(0x1) << SDHC_EISIER_CMDTEO_Pos)
-#define   SDHC_EISIER_CMDTEO_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_CMDTEO_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CMDTEO_MASKED   (SDHC_EISIER_CMDTEO_MASKED_Val << SDHC_EISIER_CMDTEO_Pos)
-#define SDHC_EISIER_CMDTEO_ENABLED  (SDHC_EISIER_CMDTEO_ENABLED_Val << SDHC_EISIER_CMDTEO_Pos)
-#define SDHC_EISIER_CMDCRC_Pos      1            /**< \brief (SDHC_EISIER) Command CRC Error Signal Enable */
-#define SDHC_EISIER_CMDCRC          (_U_(0x1) << SDHC_EISIER_CMDCRC_Pos)
-#define   SDHC_EISIER_CMDCRC_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_CMDCRC_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CMDCRC_MASKED   (SDHC_EISIER_CMDCRC_MASKED_Val << SDHC_EISIER_CMDCRC_Pos)
-#define SDHC_EISIER_CMDCRC_ENABLED  (SDHC_EISIER_CMDCRC_ENABLED_Val << SDHC_EISIER_CMDCRC_Pos)
-#define SDHC_EISIER_CMDEND_Pos      2            /**< \brief (SDHC_EISIER) Command End Bit Error Signal Enable */
-#define SDHC_EISIER_CMDEND          (_U_(0x1) << SDHC_EISIER_CMDEND_Pos)
-#define   SDHC_EISIER_CMDEND_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_CMDEND_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CMDEND_MASKED   (SDHC_EISIER_CMDEND_MASKED_Val << SDHC_EISIER_CMDEND_Pos)
-#define SDHC_EISIER_CMDEND_ENABLED  (SDHC_EISIER_CMDEND_ENABLED_Val << SDHC_EISIER_CMDEND_Pos)
-#define SDHC_EISIER_CMDIDX_Pos      3            /**< \brief (SDHC_EISIER) Command Index Error Signal Enable */
-#define SDHC_EISIER_CMDIDX          (_U_(0x1) << SDHC_EISIER_CMDIDX_Pos)
-#define   SDHC_EISIER_CMDIDX_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_CMDIDX_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CMDIDX_MASKED   (SDHC_EISIER_CMDIDX_MASKED_Val << SDHC_EISIER_CMDIDX_Pos)
-#define SDHC_EISIER_CMDIDX_ENABLED  (SDHC_EISIER_CMDIDX_ENABLED_Val << SDHC_EISIER_CMDIDX_Pos)
-#define SDHC_EISIER_DATTEO_Pos      4            /**< \brief (SDHC_EISIER) Data Timeout Error Signal Enable */
-#define SDHC_EISIER_DATTEO          (_U_(0x1) << SDHC_EISIER_DATTEO_Pos)
-#define   SDHC_EISIER_DATTEO_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_DATTEO_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_DATTEO_MASKED   (SDHC_EISIER_DATTEO_MASKED_Val << SDHC_EISIER_DATTEO_Pos)
-#define SDHC_EISIER_DATTEO_ENABLED  (SDHC_EISIER_DATTEO_ENABLED_Val << SDHC_EISIER_DATTEO_Pos)
-#define SDHC_EISIER_DATCRC_Pos      5            /**< \brief (SDHC_EISIER) Data CRC Error Signal Enable */
-#define SDHC_EISIER_DATCRC          (_U_(0x1) << SDHC_EISIER_DATCRC_Pos)
-#define   SDHC_EISIER_DATCRC_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_DATCRC_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_DATCRC_MASKED   (SDHC_EISIER_DATCRC_MASKED_Val << SDHC_EISIER_DATCRC_Pos)
-#define SDHC_EISIER_DATCRC_ENABLED  (SDHC_EISIER_DATCRC_ENABLED_Val << SDHC_EISIER_DATCRC_Pos)
-#define SDHC_EISIER_DATEND_Pos      6            /**< \brief (SDHC_EISIER) Data End Bit Error Signal Enable */
-#define SDHC_EISIER_DATEND          (_U_(0x1) << SDHC_EISIER_DATEND_Pos)
-#define   SDHC_EISIER_DATEND_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_DATEND_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_DATEND_MASKED   (SDHC_EISIER_DATEND_MASKED_Val << SDHC_EISIER_DATEND_Pos)
-#define SDHC_EISIER_DATEND_ENABLED  (SDHC_EISIER_DATEND_ENABLED_Val << SDHC_EISIER_DATEND_Pos)
-#define SDHC_EISIER_CURLIM_Pos      7            /**< \brief (SDHC_EISIER) Current Limit Error Signal Enable */
-#define SDHC_EISIER_CURLIM          (_U_(0x1) << SDHC_EISIER_CURLIM_Pos)
-#define   SDHC_EISIER_CURLIM_MASKED_Val   _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_CURLIM_ENABLED_Val  _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_CURLIM_MASKED   (SDHC_EISIER_CURLIM_MASKED_Val << SDHC_EISIER_CURLIM_Pos)
-#define SDHC_EISIER_CURLIM_ENABLED  (SDHC_EISIER_CURLIM_ENABLED_Val << SDHC_EISIER_CURLIM_Pos)
-#define SDHC_EISIER_ACMD_Pos        8            /**< \brief (SDHC_EISIER) Auto CMD Error Signal Enable */
-#define SDHC_EISIER_ACMD            (_U_(0x1) << SDHC_EISIER_ACMD_Pos)
-#define   SDHC_EISIER_ACMD_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_ACMD_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_ACMD_MASKED     (SDHC_EISIER_ACMD_MASKED_Val   << SDHC_EISIER_ACMD_Pos)
-#define SDHC_EISIER_ACMD_ENABLED    (SDHC_EISIER_ACMD_ENABLED_Val  << SDHC_EISIER_ACMD_Pos)
-#define SDHC_EISIER_ADMA_Pos        9            /**< \brief (SDHC_EISIER) ADMA Error Signal Enable */
-#define SDHC_EISIER_ADMA            (_U_(0x1) << SDHC_EISIER_ADMA_Pos)
-#define   SDHC_EISIER_ADMA_MASKED_Val     _U_(0x0)   /**< \brief (SDHC_EISIER) Masked */
-#define   SDHC_EISIER_ADMA_ENABLED_Val    _U_(0x1)   /**< \brief (SDHC_EISIER) Enabled */
-#define SDHC_EISIER_ADMA_MASKED     (SDHC_EISIER_ADMA_MASKED_Val   << SDHC_EISIER_ADMA_Pos)
-#define SDHC_EISIER_ADMA_ENABLED    (SDHC_EISIER_ADMA_ENABLED_Val  << SDHC_EISIER_ADMA_Pos)
-#define SDHC_EISIER_MASK            _U_(0x03FF)  /**< \brief (SDHC_EISIER) MASK Register */
-
-// EMMC mode
-#define SDHC_EISIER_EMMC_CMDTEO_Pos 0            /**< \brief (SDHC_EISIER_EMMC) Command Timeout Error Signal Enable */
-#define SDHC_EISIER_EMMC_CMDTEO     (_U_(0x1) << SDHC_EISIER_EMMC_CMDTEO_Pos)
-#define   SDHC_EISIER_EMMC_CMDTEO_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CMDTEO_MASKED (SDHC_EISIER_EMMC_CMDTEO_MASKED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
-#define SDHC_EISIER_EMMC_CMDTEO_ENABLED (SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)
-#define SDHC_EISIER_EMMC_CMDCRC_Pos 1            /**< \brief (SDHC_EISIER_EMMC) Command CRC Error Signal Enable */
-#define SDHC_EISIER_EMMC_CMDCRC     (_U_(0x1) << SDHC_EISIER_EMMC_CMDCRC_Pos)
-#define   SDHC_EISIER_EMMC_CMDCRC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CMDCRC_MASKED (SDHC_EISIER_EMMC_CMDCRC_MASKED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
-#define SDHC_EISIER_EMMC_CMDCRC_ENABLED (SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)
-#define SDHC_EISIER_EMMC_CMDEND_Pos 2            /**< \brief (SDHC_EISIER_EMMC) Command End Bit Error Signal Enable */
-#define SDHC_EISIER_EMMC_CMDEND     (_U_(0x1) << SDHC_EISIER_EMMC_CMDEND_Pos)
-#define   SDHC_EISIER_EMMC_CMDEND_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_CMDEND_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CMDEND_MASKED (SDHC_EISIER_EMMC_CMDEND_MASKED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
-#define SDHC_EISIER_EMMC_CMDEND_ENABLED (SDHC_EISIER_EMMC_CMDEND_ENABLED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)
-#define SDHC_EISIER_EMMC_CMDIDX_Pos 3            /**< \brief (SDHC_EISIER_EMMC) Command Index Error Signal Enable */
-#define SDHC_EISIER_EMMC_CMDIDX     (_U_(0x1) << SDHC_EISIER_EMMC_CMDIDX_Pos)
-#define   SDHC_EISIER_EMMC_CMDIDX_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CMDIDX_MASKED (SDHC_EISIER_EMMC_CMDIDX_MASKED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
-#define SDHC_EISIER_EMMC_CMDIDX_ENABLED (SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)
-#define SDHC_EISIER_EMMC_DATTEO_Pos 4            /**< \brief (SDHC_EISIER_EMMC) Data Timeout Error Signal Enable */
-#define SDHC_EISIER_EMMC_DATTEO     (_U_(0x1) << SDHC_EISIER_EMMC_DATTEO_Pos)
-#define   SDHC_EISIER_EMMC_DATTEO_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_DATTEO_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_DATTEO_MASKED (SDHC_EISIER_EMMC_DATTEO_MASKED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
-#define SDHC_EISIER_EMMC_DATTEO_ENABLED (SDHC_EISIER_EMMC_DATTEO_ENABLED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)
-#define SDHC_EISIER_EMMC_DATCRC_Pos 5            /**< \brief (SDHC_EISIER_EMMC) Data CRC Error Signal Enable */
-#define SDHC_EISIER_EMMC_DATCRC     (_U_(0x1) << SDHC_EISIER_EMMC_DATCRC_Pos)
-#define   SDHC_EISIER_EMMC_DATCRC_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_DATCRC_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_DATCRC_MASKED (SDHC_EISIER_EMMC_DATCRC_MASKED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
-#define SDHC_EISIER_EMMC_DATCRC_ENABLED (SDHC_EISIER_EMMC_DATCRC_ENABLED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)
-#define SDHC_EISIER_EMMC_DATEND_Pos 6            /**< \brief (SDHC_EISIER_EMMC) Data End Bit Error Signal Enable */
-#define SDHC_EISIER_EMMC_DATEND     (_U_(0x1) << SDHC_EISIER_EMMC_DATEND_Pos)
-#define   SDHC_EISIER_EMMC_DATEND_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_DATEND_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_DATEND_MASKED (SDHC_EISIER_EMMC_DATEND_MASKED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
-#define SDHC_EISIER_EMMC_DATEND_ENABLED (SDHC_EISIER_EMMC_DATEND_ENABLED_Val << SDHC_EISIER_EMMC_DATEND_Pos)
-#define SDHC_EISIER_EMMC_CURLIM_Pos 7            /**< \brief (SDHC_EISIER_EMMC) Current Limit Error Signal Enable */
-#define SDHC_EISIER_EMMC_CURLIM     (_U_(0x1) << SDHC_EISIER_EMMC_CURLIM_Pos)
-#define   SDHC_EISIER_EMMC_CURLIM_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_CURLIM_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_CURLIM_MASKED (SDHC_EISIER_EMMC_CURLIM_MASKED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
-#define SDHC_EISIER_EMMC_CURLIM_ENABLED (SDHC_EISIER_EMMC_CURLIM_ENABLED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)
-#define SDHC_EISIER_EMMC_ACMD_Pos   8            /**< \brief (SDHC_EISIER_EMMC) Auto CMD Error Signal Enable */
-#define SDHC_EISIER_EMMC_ACMD       (_U_(0x1) << SDHC_EISIER_EMMC_ACMD_Pos)
-#define   SDHC_EISIER_EMMC_ACMD_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_ACMD_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_ACMD_MASKED (SDHC_EISIER_EMMC_ACMD_MASKED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
-#define SDHC_EISIER_EMMC_ACMD_ENABLED (SDHC_EISIER_EMMC_ACMD_ENABLED_Val << SDHC_EISIER_EMMC_ACMD_Pos)
-#define SDHC_EISIER_EMMC_ADMA_Pos   9            /**< \brief (SDHC_EISIER_EMMC) ADMA Error Signal Enable */
-#define SDHC_EISIER_EMMC_ADMA       (_U_(0x1) << SDHC_EISIER_EMMC_ADMA_Pos)
-#define   SDHC_EISIER_EMMC_ADMA_MASKED_Val _U_(0x0)   /**< \brief (SDHC_EISIER_EMMC) Masked */
-#define   SDHC_EISIER_EMMC_ADMA_ENABLED_Val _U_(0x1)   /**< \brief (SDHC_EISIER_EMMC) Enabled */
-#define SDHC_EISIER_EMMC_ADMA_MASKED (SDHC_EISIER_EMMC_ADMA_MASKED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
-#define SDHC_EISIER_EMMC_ADMA_ENABLED (SDHC_EISIER_EMMC_ADMA_ENABLED_Val << SDHC_EISIER_EMMC_ADMA_Pos)
-#define SDHC_EISIER_EMMC_BOOTAE_Pos 12           /**< \brief (SDHC_EISIER_EMMC) Boot Acknowledge Error Signal Enable */
-#define SDHC_EISIER_EMMC_BOOTAE     (_U_(0x1) << SDHC_EISIER_EMMC_BOOTAE_Pos)
-#define SDHC_EISIER_EMMC_MASK       _U_(0x13FF)  /**< \brief (SDHC_EISIER_EMMC) MASK Register */
-
-/* -------- SDHC_ACESR : (SDHC Offset: 0x03C) (R/  16) Auto CMD Error Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t ACMD12NE:1;       /*!< bit:      0  Auto CMD12 Not Executed            */
-    uint16_t ACMDTEO:1;        /*!< bit:      1  Auto CMD Timeout Error             */
-    uint16_t ACMDCRC:1;        /*!< bit:      2  Auto CMD CRC Error                 */
-    uint16_t ACMDEND:1;        /*!< bit:      3  Auto CMD End Bit Error             */
-    uint16_t ACMDIDX:1;        /*!< bit:      4  Auto CMD Index Error               */
-    uint16_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint16_t CMDNI:1;          /*!< bit:      7  Command not Issued By Auto CMD12 Error */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_ACESR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_ACESR_OFFSET           0x03C        /**< \brief (SDHC_ACESR offset) Auto CMD Error Status */
-#define SDHC_ACESR_RESETVALUE       _U_(0x0000)  /**< \brief (SDHC_ACESR reset_value) Auto CMD Error Status */
-
-#define SDHC_ACESR_ACMD12NE_Pos     0            /**< \brief (SDHC_ACESR) Auto CMD12 Not Executed */
-#define SDHC_ACESR_ACMD12NE         (_U_(0x1) << SDHC_ACESR_ACMD12NE_Pos)
-#define   SDHC_ACESR_ACMD12NE_EXEC_Val    _U_(0x0)   /**< \brief (SDHC_ACESR) Executed */
-#define   SDHC_ACESR_ACMD12NE_NOT_EXEC_Val _U_(0x1)   /**< \brief (SDHC_ACESR) Not executed */
-#define SDHC_ACESR_ACMD12NE_EXEC    (SDHC_ACESR_ACMD12NE_EXEC_Val  << SDHC_ACESR_ACMD12NE_Pos)
-#define SDHC_ACESR_ACMD12NE_NOT_EXEC (SDHC_ACESR_ACMD12NE_NOT_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)
-#define SDHC_ACESR_ACMDTEO_Pos      1            /**< \brief (SDHC_ACESR) Auto CMD Timeout Error */
-#define SDHC_ACESR_ACMDTEO          (_U_(0x1) << SDHC_ACESR_ACMDTEO_Pos)
-#define   SDHC_ACESR_ACMDTEO_NO_Val       _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
-#define   SDHC_ACESR_ACMDTEO_YES_Val      _U_(0x1)   /**< \brief (SDHC_ACESR) Timeout */
-#define SDHC_ACESR_ACMDTEO_NO       (SDHC_ACESR_ACMDTEO_NO_Val     << SDHC_ACESR_ACMDTEO_Pos)
-#define SDHC_ACESR_ACMDTEO_YES      (SDHC_ACESR_ACMDTEO_YES_Val    << SDHC_ACESR_ACMDTEO_Pos)
-#define SDHC_ACESR_ACMDCRC_Pos      2            /**< \brief (SDHC_ACESR) Auto CMD CRC Error */
-#define SDHC_ACESR_ACMDCRC          (_U_(0x1) << SDHC_ACESR_ACMDCRC_Pos)
-#define   SDHC_ACESR_ACMDCRC_NO_Val       _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
-#define   SDHC_ACESR_ACMDCRC_YES_Val      _U_(0x1)   /**< \brief (SDHC_ACESR) CRC Error Generated */
-#define SDHC_ACESR_ACMDCRC_NO       (SDHC_ACESR_ACMDCRC_NO_Val     << SDHC_ACESR_ACMDCRC_Pos)
-#define SDHC_ACESR_ACMDCRC_YES      (SDHC_ACESR_ACMDCRC_YES_Val    << SDHC_ACESR_ACMDCRC_Pos)
-#define SDHC_ACESR_ACMDEND_Pos      3            /**< \brief (SDHC_ACESR) Auto CMD End Bit Error */
-#define SDHC_ACESR_ACMDEND          (_U_(0x1) << SDHC_ACESR_ACMDEND_Pos)
-#define   SDHC_ACESR_ACMDEND_NO_Val       _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
-#define   SDHC_ACESR_ACMDEND_YES_Val      _U_(0x1)   /**< \brief (SDHC_ACESR) End Bit Error Generated */
-#define SDHC_ACESR_ACMDEND_NO       (SDHC_ACESR_ACMDEND_NO_Val     << SDHC_ACESR_ACMDEND_Pos)
-#define SDHC_ACESR_ACMDEND_YES      (SDHC_ACESR_ACMDEND_YES_Val    << SDHC_ACESR_ACMDEND_Pos)
-#define SDHC_ACESR_ACMDIDX_Pos      4            /**< \brief (SDHC_ACESR) Auto CMD Index Error */
-#define SDHC_ACESR_ACMDIDX          (_U_(0x1) << SDHC_ACESR_ACMDIDX_Pos)
-#define   SDHC_ACESR_ACMDIDX_NO_Val       _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
-#define   SDHC_ACESR_ACMDIDX_YES_Val      _U_(0x1)   /**< \brief (SDHC_ACESR) Error */
-#define SDHC_ACESR_ACMDIDX_NO       (SDHC_ACESR_ACMDIDX_NO_Val     << SDHC_ACESR_ACMDIDX_Pos)
-#define SDHC_ACESR_ACMDIDX_YES      (SDHC_ACESR_ACMDIDX_YES_Val    << SDHC_ACESR_ACMDIDX_Pos)
-#define SDHC_ACESR_CMDNI_Pos        7            /**< \brief (SDHC_ACESR) Command not Issued By Auto CMD12 Error */
-#define SDHC_ACESR_CMDNI            (_U_(0x1) << SDHC_ACESR_CMDNI_Pos)
-#define   SDHC_ACESR_CMDNI_OK_Val         _U_(0x0)   /**< \brief (SDHC_ACESR) No error */
-#define   SDHC_ACESR_CMDNI_NOT_ISSUED_Val _U_(0x1)   /**< \brief (SDHC_ACESR) Not Issued */
-#define SDHC_ACESR_CMDNI_OK         (SDHC_ACESR_CMDNI_OK_Val       << SDHC_ACESR_CMDNI_Pos)
-#define SDHC_ACESR_CMDNI_NOT_ISSUED (SDHC_ACESR_CMDNI_NOT_ISSUED_Val << SDHC_ACESR_CMDNI_Pos)
-#define SDHC_ACESR_MASK             _U_(0x009F)  /**< \brief (SDHC_ACESR) MASK Register */
-
-/* -------- SDHC_HC2R : (SDHC Offset: 0x03E) (R/W 16) Host Control 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t UHSMS:3;          /*!< bit:  0.. 2  UHS Mode Select                    */
-    uint16_t VS18EN:1;         /*!< bit:      3  1.8V Signaling Enable              */
-    uint16_t DRVSEL:2;         /*!< bit:  4.. 5  Driver Strength Select             */
-    uint16_t EXTUN:1;          /*!< bit:      6  Execute Tuning                     */
-    uint16_t SLCKSEL:1;        /*!< bit:      7  Sampling Clock Select              */
-    uint16_t :6;               /*!< bit:  8..13  Reserved                           */
-    uint16_t ASINTEN:1;        /*!< bit:     14  Asynchronous Interrupt Enable      */
-    uint16_t PVALEN:1;         /*!< bit:     15  Preset Value Enable                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // EMMC mode
-    uint16_t HS200EN:4;        /*!< bit:  0.. 3  HS200 Mode Enable                  */
-    uint16_t DRVSEL:2;         /*!< bit:  4.. 5  Driver Strength Select             */
-    uint16_t EXTUN:1;          /*!< bit:      6  Execute Tuning                     */
-    uint16_t SLCKSEL:1;        /*!< bit:      7  Sampling Clock Select              */
-    uint16_t :7;               /*!< bit:  8..14  Reserved                           */
-    uint16_t PVALEN:1;         /*!< bit:     15  Preset Value Enable                */
-  } EMMC;                      /*!< Structure used for EMMC                         */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_HC2R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_HC2R_OFFSET            0x03E        /**< \brief (SDHC_HC2R offset) Host Control 2 */
-#define SDHC_HC2R_RESETVALUE        _U_(0x0000)  /**< \brief (SDHC_HC2R reset_value) Host Control 2 */
-
-#define SDHC_HC2R_UHSMS_Pos         0            /**< \brief (SDHC_HC2R) UHS Mode Select */
-#define SDHC_HC2R_UHSMS_Msk         (_U_(0x7) << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS(value)      (SDHC_HC2R_UHSMS_Msk & ((value) << SDHC_HC2R_UHSMS_Pos))
-#define   SDHC_HC2R_UHSMS_SDR12_Val       _U_(0x0)   /**< \brief (SDHC_HC2R) SDR12 */
-#define   SDHC_HC2R_UHSMS_SDR25_Val       _U_(0x1)   /**< \brief (SDHC_HC2R) SDR25 */
-#define   SDHC_HC2R_UHSMS_SDR50_Val       _U_(0x2)   /**< \brief (SDHC_HC2R) SDR50 */
-#define   SDHC_HC2R_UHSMS_SDR104_Val      _U_(0x3)   /**< \brief (SDHC_HC2R) SDR104 */
-#define   SDHC_HC2R_UHSMS_DDR50_Val       _U_(0x4)   /**< \brief (SDHC_HC2R) DDR50 */
-#define SDHC_HC2R_UHSMS_SDR12       (SDHC_HC2R_UHSMS_SDR12_Val     << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS_SDR25       (SDHC_HC2R_UHSMS_SDR25_Val     << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS_SDR50       (SDHC_HC2R_UHSMS_SDR50_Val     << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS_SDR104      (SDHC_HC2R_UHSMS_SDR104_Val    << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_UHSMS_DDR50       (SDHC_HC2R_UHSMS_DDR50_Val     << SDHC_HC2R_UHSMS_Pos)
-#define SDHC_HC2R_VS18EN_Pos        3            /**< \brief (SDHC_HC2R) 1.8V Signaling Enable */
-#define SDHC_HC2R_VS18EN            (_U_(0x1) << SDHC_HC2R_VS18EN_Pos)
-#define   SDHC_HC2R_VS18EN_S33V_Val       _U_(0x0)   /**< \brief (SDHC_HC2R) 3.3V Signaling */
-#define   SDHC_HC2R_VS18EN_S18V_Val       _U_(0x1)   /**< \brief (SDHC_HC2R) 1.8V Signaling */
-#define SDHC_HC2R_VS18EN_S33V       (SDHC_HC2R_VS18EN_S33V_Val     << SDHC_HC2R_VS18EN_Pos)
-#define SDHC_HC2R_VS18EN_S18V       (SDHC_HC2R_VS18EN_S18V_Val     << SDHC_HC2R_VS18EN_Pos)
-#define SDHC_HC2R_DRVSEL_Pos        4            /**< \brief (SDHC_HC2R) Driver Strength Select */
-#define SDHC_HC2R_DRVSEL_Msk        (_U_(0x3) << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_DRVSEL(value)     (SDHC_HC2R_DRVSEL_Msk & ((value) << SDHC_HC2R_DRVSEL_Pos))
-#define   SDHC_HC2R_DRVSEL_B_Val          _U_(0x0)   /**< \brief (SDHC_HC2R) Driver Type B is Selected (Default) */
-#define   SDHC_HC2R_DRVSEL_A_Val          _U_(0x1)   /**< \brief (SDHC_HC2R) Driver Type A is Selected */
-#define   SDHC_HC2R_DRVSEL_C_Val          _U_(0x2)   /**< \brief (SDHC_HC2R) Driver Type C is Selected */
-#define   SDHC_HC2R_DRVSEL_D_Val          _U_(0x3)   /**< \brief (SDHC_HC2R) Driver Type D is Selected */
-#define SDHC_HC2R_DRVSEL_B          (SDHC_HC2R_DRVSEL_B_Val        << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_DRVSEL_A          (SDHC_HC2R_DRVSEL_A_Val        << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_DRVSEL_C          (SDHC_HC2R_DRVSEL_C_Val        << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_DRVSEL_D          (SDHC_HC2R_DRVSEL_D_Val        << SDHC_HC2R_DRVSEL_Pos)
-#define SDHC_HC2R_EXTUN_Pos         6            /**< \brief (SDHC_HC2R) Execute Tuning */
-#define SDHC_HC2R_EXTUN             (_U_(0x1) << SDHC_HC2R_EXTUN_Pos)
-#define   SDHC_HC2R_EXTUN_NO_Val          _U_(0x0)   /**< \brief (SDHC_HC2R) Not Tuned or Tuning Completed */
-#define   SDHC_HC2R_EXTUN_REQUESTED_Val   _U_(0x1)   /**< \brief (SDHC_HC2R) Execute Tuning */
-#define SDHC_HC2R_EXTUN_NO          (SDHC_HC2R_EXTUN_NO_Val        << SDHC_HC2R_EXTUN_Pos)
-#define SDHC_HC2R_EXTUN_REQUESTED   (SDHC_HC2R_EXTUN_REQUESTED_Val << SDHC_HC2R_EXTUN_Pos)
-#define SDHC_HC2R_SLCKSEL_Pos       7            /**< \brief (SDHC_HC2R) Sampling Clock Select */
-#define SDHC_HC2R_SLCKSEL           (_U_(0x1) << SDHC_HC2R_SLCKSEL_Pos)
-#define   SDHC_HC2R_SLCKSEL_FIXED_Val     _U_(0x0)   /**< \brief (SDHC_HC2R) Fixed clock is used to sample data */
-#define   SDHC_HC2R_SLCKSEL_TUNED_Val     _U_(0x1)   /**< \brief (SDHC_HC2R) Tuned clock is used to sample data */
-#define SDHC_HC2R_SLCKSEL_FIXED     (SDHC_HC2R_SLCKSEL_FIXED_Val   << SDHC_HC2R_SLCKSEL_Pos)
-#define SDHC_HC2R_SLCKSEL_TUNED     (SDHC_HC2R_SLCKSEL_TUNED_Val   << SDHC_HC2R_SLCKSEL_Pos)
-#define SDHC_HC2R_ASINTEN_Pos       14           /**< \brief (SDHC_HC2R) Asynchronous Interrupt Enable */
-#define SDHC_HC2R_ASINTEN           (_U_(0x1) << SDHC_HC2R_ASINTEN_Pos)
-#define   SDHC_HC2R_ASINTEN_DISABLED_Val  _U_(0x0)   /**< \brief (SDHC_HC2R) Disabled */
-#define   SDHC_HC2R_ASINTEN_ENABLED_Val   _U_(0x1)   /**< \brief (SDHC_HC2R) Enabled */
-#define SDHC_HC2R_ASINTEN_DISABLED  (SDHC_HC2R_ASINTEN_DISABLED_Val << SDHC_HC2R_ASINTEN_Pos)
-#define SDHC_HC2R_ASINTEN_ENABLED   (SDHC_HC2R_ASINTEN_ENABLED_Val << SDHC_HC2R_ASINTEN_Pos)
-#define SDHC_HC2R_PVALEN_Pos        15           /**< \brief (SDHC_HC2R) Preset Value Enable */
-#define SDHC_HC2R_PVALEN            (_U_(0x1) << SDHC_HC2R_PVALEN_Pos)
-#define   SDHC_HC2R_PVALEN_HOST_Val       _U_(0x0)   /**< \brief (SDHC_HC2R) SDCLK and Driver Strength are controlled by Host Controller */
-#define   SDHC_HC2R_PVALEN_AUTO_Val       _U_(0x1)   /**< \brief (SDHC_HC2R) Automatic Selection by Preset Value is Enabled */
-#define SDHC_HC2R_PVALEN_HOST       (SDHC_HC2R_PVALEN_HOST_Val     << SDHC_HC2R_PVALEN_Pos)
-#define SDHC_HC2R_PVALEN_AUTO       (SDHC_HC2R_PVALEN_AUTO_Val     << SDHC_HC2R_PVALEN_Pos)
-#define SDHC_HC2R_MASK              _U_(0xC0FF)  /**< \brief (SDHC_HC2R) MASK Register */
-
-// EMMC mode
-#define SDHC_HC2R_EMMC_HS200EN_Pos  0            /**< \brief (SDHC_HC2R_EMMC) HS200 Mode Enable */
-#define SDHC_HC2R_EMMC_HS200EN_Msk  (_U_(0xF) << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN(value) (SDHC_HC2R_EMMC_HS200EN_Msk & ((value) << SDHC_HC2R_EMMC_HS200EN_Pos))
-#define   SDHC_HC2R_EMMC_HS200EN_SDR12_Val _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) SDR12 */
-#define   SDHC_HC2R_EMMC_HS200EN_SDR25_Val _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) SDR25 */
-#define   SDHC_HC2R_EMMC_HS200EN_SDR50_Val _U_(0x2)   /**< \brief (SDHC_HC2R_EMMC) SDR50 */
-#define   SDHC_HC2R_EMMC_HS200EN_SDR104_Val _U_(0x3)   /**< \brief (SDHC_HC2R_EMMC) SDR104 */
-#define   SDHC_HC2R_EMMC_HS200EN_DDR50_Val _U_(0x4)   /**< \brief (SDHC_HC2R_EMMC) DDR50 */
-#define SDHC_HC2R_EMMC_HS200EN_SDR12 (SDHC_HC2R_EMMC_HS200EN_SDR12_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN_SDR25 (SDHC_HC2R_EMMC_HS200EN_SDR25_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN_SDR50 (SDHC_HC2R_EMMC_HS200EN_SDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN_SDR104 (SDHC_HC2R_EMMC_HS200EN_SDR104_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_HS200EN_DDR50 (SDHC_HC2R_EMMC_HS200EN_DDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL_Pos   4            /**< \brief (SDHC_HC2R_EMMC) Driver Strength Select */
-#define SDHC_HC2R_EMMC_DRVSEL_Msk   (_U_(0x3) << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL(value) (SDHC_HC2R_EMMC_DRVSEL_Msk & ((value) << SDHC_HC2R_EMMC_DRVSEL_Pos))
-#define   SDHC_HC2R_EMMC_DRVSEL_B_Val     _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) Driver Type B is Selected (Default) */
-#define   SDHC_HC2R_EMMC_DRVSEL_A_Val     _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) Driver Type A is Selected */
-#define   SDHC_HC2R_EMMC_DRVSEL_C_Val     _U_(0x2)   /**< \brief (SDHC_HC2R_EMMC) Driver Type C is Selected */
-#define   SDHC_HC2R_EMMC_DRVSEL_D_Val     _U_(0x3)   /**< \brief (SDHC_HC2R_EMMC) Driver Type D is Selected */
-#define SDHC_HC2R_EMMC_DRVSEL_B     (SDHC_HC2R_EMMC_DRVSEL_B_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL_A     (SDHC_HC2R_EMMC_DRVSEL_A_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL_C     (SDHC_HC2R_EMMC_DRVSEL_C_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_DRVSEL_D     (SDHC_HC2R_EMMC_DRVSEL_D_Val   << SDHC_HC2R_EMMC_DRVSEL_Pos)
-#define SDHC_HC2R_EMMC_EXTUN_Pos    6            /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
-#define SDHC_HC2R_EMMC_EXTUN        (_U_(0x1) << SDHC_HC2R_EMMC_EXTUN_Pos)
-#define   SDHC_HC2R_EMMC_EXTUN_NO_Val     _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) Not Tuned or Tuning Completed */
-#define   SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */
-#define SDHC_HC2R_EMMC_EXTUN_NO     (SDHC_HC2R_EMMC_EXTUN_NO_Val   << SDHC_HC2R_EMMC_EXTUN_Pos)
-#define SDHC_HC2R_EMMC_EXTUN_REQUESTED (SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val << SDHC_HC2R_EMMC_EXTUN_Pos)
-#define SDHC_HC2R_EMMC_SLCKSEL_Pos  7            /**< \brief (SDHC_HC2R_EMMC) Sampling Clock Select */
-#define SDHC_HC2R_EMMC_SLCKSEL      (_U_(0x1) << SDHC_HC2R_EMMC_SLCKSEL_Pos)
-#define   SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) Fixed clock is used to sample data */
-#define   SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) Tuned clock is used to sample data */
-#define SDHC_HC2R_EMMC_SLCKSEL_FIXED (SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
-#define SDHC_HC2R_EMMC_SLCKSEL_TUNED (SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)
-#define SDHC_HC2R_EMMC_PVALEN_Pos   15           /**< \brief (SDHC_HC2R_EMMC) Preset Value Enable */
-#define SDHC_HC2R_EMMC_PVALEN       (_U_(0x1) << SDHC_HC2R_EMMC_PVALEN_Pos)
-#define   SDHC_HC2R_EMMC_PVALEN_HOST_Val  _U_(0x0)   /**< \brief (SDHC_HC2R_EMMC) SDCLK and Driver Strength are controlled by Host Controller */
-#define   SDHC_HC2R_EMMC_PVALEN_AUTO_Val  _U_(0x1)   /**< \brief (SDHC_HC2R_EMMC) Automatic Selection by Preset Value is Enabled */
-#define SDHC_HC2R_EMMC_PVALEN_HOST  (SDHC_HC2R_EMMC_PVALEN_HOST_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
-#define SDHC_HC2R_EMMC_PVALEN_AUTO  (SDHC_HC2R_EMMC_PVALEN_AUTO_Val << SDHC_HC2R_EMMC_PVALEN_Pos)
-#define SDHC_HC2R_EMMC_MASK         _U_(0x80FF)  /**< \brief (SDHC_HC2R_EMMC) MASK Register */
-
-/* -------- SDHC_CA0R : (SDHC Offset: 0x040) (R/  32) Capabilities 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t TEOCLKF:6;        /*!< bit:  0.. 5  Timeout Clock Frequency            */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t TEOCLKU:1;        /*!< bit:      7  Timeout Clock Unit                 */
-    uint32_t BASECLKF:8;       /*!< bit:  8..15  Base Clock Frequency               */
-    uint32_t MAXBLKL:2;        /*!< bit: 16..17  Max Block Length                   */
-    uint32_t ED8SUP:1;         /*!< bit:     18  8-bit Support for Embedded Device  */
-    uint32_t ADMA2SUP:1;       /*!< bit:     19  ADMA2 Support                      */
-    uint32_t :1;               /*!< bit:     20  Reserved                           */
-    uint32_t HSSUP:1;          /*!< bit:     21  High Speed Support                 */
-    uint32_t SDMASUP:1;        /*!< bit:     22  SDMA Support                       */
-    uint32_t SRSUP:1;          /*!< bit:     23  Suspend/Resume Support             */
-    uint32_t V33VSUP:1;        /*!< bit:     24  Voltage Support 3.3V               */
-    uint32_t V30VSUP:1;        /*!< bit:     25  Voltage Support 3.0V               */
-    uint32_t V18VSUP:1;        /*!< bit:     26  Voltage Support 1.8V               */
-    uint32_t :1;               /*!< bit:     27  Reserved                           */
-    uint32_t SB64SUP:1;        /*!< bit:     28  64-Bit System Bus Support          */
-    uint32_t ASINTSUP:1;       /*!< bit:     29  Asynchronous Interrupt Support     */
-    uint32_t SLTYPE:2;         /*!< bit: 30..31  Slot Type                          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_CA0R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CA0R_OFFSET            0x040        /**< \brief (SDHC_CA0R offset) Capabilities 0 */
-#define SDHC_CA0R_RESETVALUE        _U_(0x27E80080) /**< \brief (SDHC_CA0R reset_value) Capabilities 0 */
-
-#define SDHC_CA0R_TEOCLKF_Pos       0            /**< \brief (SDHC_CA0R) Timeout Clock Frequency */
-#define SDHC_CA0R_TEOCLKF_Msk       (_U_(0x3F) << SDHC_CA0R_TEOCLKF_Pos)
-#define SDHC_CA0R_TEOCLKF(value)    (SDHC_CA0R_TEOCLKF_Msk & ((value) << SDHC_CA0R_TEOCLKF_Pos))
-#define   SDHC_CA0R_TEOCLKF_OTHER_Val     _U_(0x0)   /**< \brief (SDHC_CA0R) Get information via another method */
-#define SDHC_CA0R_TEOCLKF_OTHER     (SDHC_CA0R_TEOCLKF_OTHER_Val   << SDHC_CA0R_TEOCLKF_Pos)
-#define SDHC_CA0R_TEOCLKU_Pos       7            /**< \brief (SDHC_CA0R) Timeout Clock Unit */
-#define SDHC_CA0R_TEOCLKU           (_U_(0x1) << SDHC_CA0R_TEOCLKU_Pos)
-#define   SDHC_CA0R_TEOCLKU_KHZ_Val       _U_(0x0)   /**< \brief (SDHC_CA0R) kHz */
-#define   SDHC_CA0R_TEOCLKU_MHZ_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) MHz */
-#define SDHC_CA0R_TEOCLKU_KHZ       (SDHC_CA0R_TEOCLKU_KHZ_Val     << SDHC_CA0R_TEOCLKU_Pos)
-#define SDHC_CA0R_TEOCLKU_MHZ       (SDHC_CA0R_TEOCLKU_MHZ_Val     << SDHC_CA0R_TEOCLKU_Pos)
-#define SDHC_CA0R_BASECLKF_Pos      8            /**< \brief (SDHC_CA0R) Base Clock Frequency */
-#define SDHC_CA0R_BASECLKF_Msk      (_U_(0xFF) << SDHC_CA0R_BASECLKF_Pos)
-#define SDHC_CA0R_BASECLKF(value)   (SDHC_CA0R_BASECLKF_Msk & ((value) << SDHC_CA0R_BASECLKF_Pos))
-#define   SDHC_CA0R_BASECLKF_OTHER_Val    _U_(0x0)   /**< \brief (SDHC_CA0R) Get information via another method */
-#define SDHC_CA0R_BASECLKF_OTHER    (SDHC_CA0R_BASECLKF_OTHER_Val  << SDHC_CA0R_BASECLKF_Pos)
-#define SDHC_CA0R_MAXBLKL_Pos       16           /**< \brief (SDHC_CA0R) Max Block Length */
-#define SDHC_CA0R_MAXBLKL_Msk       (_U_(0x3) << SDHC_CA0R_MAXBLKL_Pos)
-#define SDHC_CA0R_MAXBLKL(value)    (SDHC_CA0R_MAXBLKL_Msk & ((value) << SDHC_CA0R_MAXBLKL_Pos))
-#define   SDHC_CA0R_MAXBLKL_512_Val       _U_(0x0)   /**< \brief (SDHC_CA0R) 512 bytes */
-#define   SDHC_CA0R_MAXBLKL_1024_Val      _U_(0x1)   /**< \brief (SDHC_CA0R) 1024 bytes */
-#define   SDHC_CA0R_MAXBLKL_2048_Val      _U_(0x2)   /**< \brief (SDHC_CA0R) 2048 bytes */
-#define SDHC_CA0R_MAXBLKL_512       (SDHC_CA0R_MAXBLKL_512_Val     << SDHC_CA0R_MAXBLKL_Pos)
-#define SDHC_CA0R_MAXBLKL_1024      (SDHC_CA0R_MAXBLKL_1024_Val    << SDHC_CA0R_MAXBLKL_Pos)
-#define SDHC_CA0R_MAXBLKL_2048      (SDHC_CA0R_MAXBLKL_2048_Val    << SDHC_CA0R_MAXBLKL_Pos)
-#define SDHC_CA0R_ED8SUP_Pos        18           /**< \brief (SDHC_CA0R) 8-bit Support for Embedded Device */
-#define SDHC_CA0R_ED8SUP            (_U_(0x1) << SDHC_CA0R_ED8SUP_Pos)
-#define   SDHC_CA0R_ED8SUP_NO_Val         _U_(0x0)   /**< \brief (SDHC_CA0R) 8-bit Bus Width not Supported */
-#define   SDHC_CA0R_ED8SUP_YES_Val        _U_(0x1)   /**< \brief (SDHC_CA0R) 8-bit Bus Width Supported */
-#define SDHC_CA0R_ED8SUP_NO         (SDHC_CA0R_ED8SUP_NO_Val       << SDHC_CA0R_ED8SUP_Pos)
-#define SDHC_CA0R_ED8SUP_YES        (SDHC_CA0R_ED8SUP_YES_Val      << SDHC_CA0R_ED8SUP_Pos)
-#define SDHC_CA0R_ADMA2SUP_Pos      19           /**< \brief (SDHC_CA0R) ADMA2 Support */
-#define SDHC_CA0R_ADMA2SUP          (_U_(0x1) << SDHC_CA0R_ADMA2SUP_Pos)
-#define   SDHC_CA0R_ADMA2SUP_NO_Val       _U_(0x0)   /**< \brief (SDHC_CA0R) ADMA2 not Supported */
-#define   SDHC_CA0R_ADMA2SUP_YES_Val      _U_(0x1)   /**< \brief (SDHC_CA0R) ADMA2 Supported */
-#define SDHC_CA0R_ADMA2SUP_NO       (SDHC_CA0R_ADMA2SUP_NO_Val     << SDHC_CA0R_ADMA2SUP_Pos)
-#define SDHC_CA0R_ADMA2SUP_YES      (SDHC_CA0R_ADMA2SUP_YES_Val    << SDHC_CA0R_ADMA2SUP_Pos)
-#define SDHC_CA0R_HSSUP_Pos         21           /**< \brief (SDHC_CA0R) High Speed Support */
-#define SDHC_CA0R_HSSUP             (_U_(0x1) << SDHC_CA0R_HSSUP_Pos)
-#define   SDHC_CA0R_HSSUP_NO_Val          _U_(0x0)   /**< \brief (SDHC_CA0R) High Speed not Supported */
-#define   SDHC_CA0R_HSSUP_YES_Val         _U_(0x1)   /**< \brief (SDHC_CA0R) High Speed Supported */
-#define SDHC_CA0R_HSSUP_NO          (SDHC_CA0R_HSSUP_NO_Val        << SDHC_CA0R_HSSUP_Pos)
-#define SDHC_CA0R_HSSUP_YES         (SDHC_CA0R_HSSUP_YES_Val       << SDHC_CA0R_HSSUP_Pos)
-#define SDHC_CA0R_SDMASUP_Pos       22           /**< \brief (SDHC_CA0R) SDMA Support */
-#define SDHC_CA0R_SDMASUP           (_U_(0x1) << SDHC_CA0R_SDMASUP_Pos)
-#define   SDHC_CA0R_SDMASUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) SDMA not Supported */
-#define   SDHC_CA0R_SDMASUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) SDMA Supported */
-#define SDHC_CA0R_SDMASUP_NO        (SDHC_CA0R_SDMASUP_NO_Val      << SDHC_CA0R_SDMASUP_Pos)
-#define SDHC_CA0R_SDMASUP_YES       (SDHC_CA0R_SDMASUP_YES_Val     << SDHC_CA0R_SDMASUP_Pos)
-#define SDHC_CA0R_SRSUP_Pos         23           /**< \brief (SDHC_CA0R) Suspend/Resume Support */
-#define SDHC_CA0R_SRSUP             (_U_(0x1) << SDHC_CA0R_SRSUP_Pos)
-#define   SDHC_CA0R_SRSUP_NO_Val          _U_(0x0)   /**< \brief (SDHC_CA0R) Suspend/Resume not Supported */
-#define   SDHC_CA0R_SRSUP_YES_Val         _U_(0x1)   /**< \brief (SDHC_CA0R) Suspend/Resume Supported */
-#define SDHC_CA0R_SRSUP_NO          (SDHC_CA0R_SRSUP_NO_Val        << SDHC_CA0R_SRSUP_Pos)
-#define SDHC_CA0R_SRSUP_YES         (SDHC_CA0R_SRSUP_YES_Val       << SDHC_CA0R_SRSUP_Pos)
-#define SDHC_CA0R_V33VSUP_Pos       24           /**< \brief (SDHC_CA0R) Voltage Support 3.3V */
-#define SDHC_CA0R_V33VSUP           (_U_(0x1) << SDHC_CA0R_V33VSUP_Pos)
-#define   SDHC_CA0R_V33VSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) 3.3V Not Supported */
-#define   SDHC_CA0R_V33VSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) 3.3V Supported */
-#define SDHC_CA0R_V33VSUP_NO        (SDHC_CA0R_V33VSUP_NO_Val      << SDHC_CA0R_V33VSUP_Pos)
-#define SDHC_CA0R_V33VSUP_YES       (SDHC_CA0R_V33VSUP_YES_Val     << SDHC_CA0R_V33VSUP_Pos)
-#define SDHC_CA0R_V30VSUP_Pos       25           /**< \brief (SDHC_CA0R) Voltage Support 3.0V */
-#define SDHC_CA0R_V30VSUP           (_U_(0x1) << SDHC_CA0R_V30VSUP_Pos)
-#define   SDHC_CA0R_V30VSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) 3.0V Not Supported */
-#define   SDHC_CA0R_V30VSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) 3.0V Supported */
-#define SDHC_CA0R_V30VSUP_NO        (SDHC_CA0R_V30VSUP_NO_Val      << SDHC_CA0R_V30VSUP_Pos)
-#define SDHC_CA0R_V30VSUP_YES       (SDHC_CA0R_V30VSUP_YES_Val     << SDHC_CA0R_V30VSUP_Pos)
-#define SDHC_CA0R_V18VSUP_Pos       26           /**< \brief (SDHC_CA0R) Voltage Support 1.8V */
-#define SDHC_CA0R_V18VSUP           (_U_(0x1) << SDHC_CA0R_V18VSUP_Pos)
-#define   SDHC_CA0R_V18VSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) 1.8V Not Supported */
-#define   SDHC_CA0R_V18VSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) 1.8V Supported */
-#define SDHC_CA0R_V18VSUP_NO        (SDHC_CA0R_V18VSUP_NO_Val      << SDHC_CA0R_V18VSUP_Pos)
-#define SDHC_CA0R_V18VSUP_YES       (SDHC_CA0R_V18VSUP_YES_Val     << SDHC_CA0R_V18VSUP_Pos)
-#define SDHC_CA0R_SB64SUP_Pos       28           /**< \brief (SDHC_CA0R) 64-Bit System Bus Support */
-#define SDHC_CA0R_SB64SUP           (_U_(0x1) << SDHC_CA0R_SB64SUP_Pos)
-#define   SDHC_CA0R_SB64SUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA0R) 32-bit Address Descriptors and System Bus */
-#define   SDHC_CA0R_SB64SUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA0R) 64-bit Address Descriptors and System Bus */
-#define SDHC_CA0R_SB64SUP_NO        (SDHC_CA0R_SB64SUP_NO_Val      << SDHC_CA0R_SB64SUP_Pos)
-#define SDHC_CA0R_SB64SUP_YES       (SDHC_CA0R_SB64SUP_YES_Val     << SDHC_CA0R_SB64SUP_Pos)
-#define SDHC_CA0R_ASINTSUP_Pos      29           /**< \brief (SDHC_CA0R) Asynchronous Interrupt Support */
-#define SDHC_CA0R_ASINTSUP          (_U_(0x1) << SDHC_CA0R_ASINTSUP_Pos)
-#define   SDHC_CA0R_ASINTSUP_NO_Val       _U_(0x0)   /**< \brief (SDHC_CA0R) Asynchronous Interrupt not Supported */
-#define   SDHC_CA0R_ASINTSUP_YES_Val      _U_(0x1)   /**< \brief (SDHC_CA0R) Asynchronous Interrupt supported */
-#define SDHC_CA0R_ASINTSUP_NO       (SDHC_CA0R_ASINTSUP_NO_Val     << SDHC_CA0R_ASINTSUP_Pos)
-#define SDHC_CA0R_ASINTSUP_YES      (SDHC_CA0R_ASINTSUP_YES_Val    << SDHC_CA0R_ASINTSUP_Pos)
-#define SDHC_CA0R_SLTYPE_Pos        30           /**< \brief (SDHC_CA0R) Slot Type */
-#define SDHC_CA0R_SLTYPE_Msk        (_U_(0x3) << SDHC_CA0R_SLTYPE_Pos)
-#define SDHC_CA0R_SLTYPE(value)     (SDHC_CA0R_SLTYPE_Msk & ((value) << SDHC_CA0R_SLTYPE_Pos))
-#define   SDHC_CA0R_SLTYPE_REMOVABLE_Val  _U_(0x0)   /**< \brief (SDHC_CA0R) Removable Card Slot */
-#define   SDHC_CA0R_SLTYPE_EMBEDDED_Val   _U_(0x1)   /**< \brief (SDHC_CA0R) Embedded Slot for One Device */
-#define SDHC_CA0R_SLTYPE_REMOVABLE  (SDHC_CA0R_SLTYPE_REMOVABLE_Val << SDHC_CA0R_SLTYPE_Pos)
-#define SDHC_CA0R_SLTYPE_EMBEDDED   (SDHC_CA0R_SLTYPE_EMBEDDED_Val << SDHC_CA0R_SLTYPE_Pos)
-#define SDHC_CA0R_MASK              _U_(0xF7EFFFBF) /**< \brief (SDHC_CA0R) MASK Register */
-
-/* -------- SDHC_CA1R : (SDHC Offset: 0x044) (R/  32) Capabilities 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SDR50SUP:1;       /*!< bit:      0  SDR50 Support                      */
-    uint32_t SDR104SUP:1;      /*!< bit:      1  SDR104 Support                     */
-    uint32_t DDR50SUP:1;       /*!< bit:      2  DDR50 Support                      */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t DRVASUP:1;        /*!< bit:      4  Driver Type A Support              */
-    uint32_t DRVCSUP:1;        /*!< bit:      5  Driver Type C Support              */
-    uint32_t DRVDSUP:1;        /*!< bit:      6  Driver Type D Support              */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t TCNTRT:4;         /*!< bit:  8..11  Timer Count for Re-Tuning          */
-    uint32_t :1;               /*!< bit:     12  Reserved                           */
-    uint32_t TSDR50:1;         /*!< bit:     13  Use Tuning for SDR50               */
-    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
-    uint32_t CLKMULT:8;        /*!< bit: 16..23  Clock Multiplier                   */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_CA1R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CA1R_OFFSET            0x044        /**< \brief (SDHC_CA1R offset) Capabilities 1 */
-#define SDHC_CA1R_RESETVALUE        _U_(0x00000070) /**< \brief (SDHC_CA1R reset_value) Capabilities 1 */
-
-#define SDHC_CA1R_SDR50SUP_Pos      0            /**< \brief (SDHC_CA1R) SDR50 Support */
-#define SDHC_CA1R_SDR50SUP          (_U_(0x1) << SDHC_CA1R_SDR50SUP_Pos)
-#define   SDHC_CA1R_SDR50SUP_NO_Val       _U_(0x0)   /**< \brief (SDHC_CA1R) SDR50 is Not Supported */
-#define   SDHC_CA1R_SDR50SUP_YES_Val      _U_(0x1)   /**< \brief (SDHC_CA1R) SDR50 is Supported */
-#define SDHC_CA1R_SDR50SUP_NO       (SDHC_CA1R_SDR50SUP_NO_Val     << SDHC_CA1R_SDR50SUP_Pos)
-#define SDHC_CA1R_SDR50SUP_YES      (SDHC_CA1R_SDR50SUP_YES_Val    << SDHC_CA1R_SDR50SUP_Pos)
-#define SDHC_CA1R_SDR104SUP_Pos     1            /**< \brief (SDHC_CA1R) SDR104 Support */
-#define SDHC_CA1R_SDR104SUP         (_U_(0x1) << SDHC_CA1R_SDR104SUP_Pos)
-#define   SDHC_CA1R_SDR104SUP_NO_Val      _U_(0x0)   /**< \brief (SDHC_CA1R) SDR104 is Not Supported */
-#define   SDHC_CA1R_SDR104SUP_YES_Val     _U_(0x1)   /**< \brief (SDHC_CA1R) SDR104 is Supported */
-#define SDHC_CA1R_SDR104SUP_NO      (SDHC_CA1R_SDR104SUP_NO_Val    << SDHC_CA1R_SDR104SUP_Pos)
-#define SDHC_CA1R_SDR104SUP_YES     (SDHC_CA1R_SDR104SUP_YES_Val   << SDHC_CA1R_SDR104SUP_Pos)
-#define SDHC_CA1R_DDR50SUP_Pos      2            /**< \brief (SDHC_CA1R) DDR50 Support */
-#define SDHC_CA1R_DDR50SUP          (_U_(0x1) << SDHC_CA1R_DDR50SUP_Pos)
-#define   SDHC_CA1R_DDR50SUP_NO_Val       _U_(0x0)   /**< \brief (SDHC_CA1R) DDR50 is Not Supported */
-#define   SDHC_CA1R_DDR50SUP_YES_Val      _U_(0x1)   /**< \brief (SDHC_CA1R) DDR50 is Supported */
-#define SDHC_CA1R_DDR50SUP_NO       (SDHC_CA1R_DDR50SUP_NO_Val     << SDHC_CA1R_DDR50SUP_Pos)
-#define SDHC_CA1R_DDR50SUP_YES      (SDHC_CA1R_DDR50SUP_YES_Val    << SDHC_CA1R_DDR50SUP_Pos)
-#define SDHC_CA1R_DRVASUP_Pos       4            /**< \brief (SDHC_CA1R) Driver Type A Support */
-#define SDHC_CA1R_DRVASUP           (_U_(0x1) << SDHC_CA1R_DRVASUP_Pos)
-#define   SDHC_CA1R_DRVASUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA1R) Driver Type A is Not Supported */
-#define   SDHC_CA1R_DRVASUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA1R) Driver Type A is Supported */
-#define SDHC_CA1R_DRVASUP_NO        (SDHC_CA1R_DRVASUP_NO_Val      << SDHC_CA1R_DRVASUP_Pos)
-#define SDHC_CA1R_DRVASUP_YES       (SDHC_CA1R_DRVASUP_YES_Val     << SDHC_CA1R_DRVASUP_Pos)
-#define SDHC_CA1R_DRVCSUP_Pos       5            /**< \brief (SDHC_CA1R) Driver Type C Support */
-#define SDHC_CA1R_DRVCSUP           (_U_(0x1) << SDHC_CA1R_DRVCSUP_Pos)
-#define   SDHC_CA1R_DRVCSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA1R) Driver Type C is Not Supported */
-#define   SDHC_CA1R_DRVCSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA1R) Driver Type C is Supported */
-#define SDHC_CA1R_DRVCSUP_NO        (SDHC_CA1R_DRVCSUP_NO_Val      << SDHC_CA1R_DRVCSUP_Pos)
-#define SDHC_CA1R_DRVCSUP_YES       (SDHC_CA1R_DRVCSUP_YES_Val     << SDHC_CA1R_DRVCSUP_Pos)
-#define SDHC_CA1R_DRVDSUP_Pos       6            /**< \brief (SDHC_CA1R) Driver Type D Support */
-#define SDHC_CA1R_DRVDSUP           (_U_(0x1) << SDHC_CA1R_DRVDSUP_Pos)
-#define   SDHC_CA1R_DRVDSUP_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA1R) Driver Type D is Not Supported */
-#define   SDHC_CA1R_DRVDSUP_YES_Val       _U_(0x1)   /**< \brief (SDHC_CA1R) Driver Type D is Supported */
-#define SDHC_CA1R_DRVDSUP_NO        (SDHC_CA1R_DRVDSUP_NO_Val      << SDHC_CA1R_DRVDSUP_Pos)
-#define SDHC_CA1R_DRVDSUP_YES       (SDHC_CA1R_DRVDSUP_YES_Val     << SDHC_CA1R_DRVDSUP_Pos)
-#define SDHC_CA1R_TCNTRT_Pos        8            /**< \brief (SDHC_CA1R) Timer Count for Re-Tuning */
-#define SDHC_CA1R_TCNTRT_Msk        (_U_(0xF) << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT(value)     (SDHC_CA1R_TCNTRT_Msk & ((value) << SDHC_CA1R_TCNTRT_Pos))
-#define   SDHC_CA1R_TCNTRT_DISABLED_Val   _U_(0x0)   /**< \brief (SDHC_CA1R) Re-Tuning Timer disabled */
-#define   SDHC_CA1R_TCNTRT_1S_Val         _U_(0x1)   /**< \brief (SDHC_CA1R) 1 second */
-#define   SDHC_CA1R_TCNTRT_2S_Val         _U_(0x2)   /**< \brief (SDHC_CA1R) 2 seconds */
-#define   SDHC_CA1R_TCNTRT_4S_Val         _U_(0x3)   /**< \brief (SDHC_CA1R) 4 seconds */
-#define   SDHC_CA1R_TCNTRT_8S_Val         _U_(0x4)   /**< \brief (SDHC_CA1R) 8 seconds */
-#define   SDHC_CA1R_TCNTRT_16S_Val        _U_(0x5)   /**< \brief (SDHC_CA1R) 16 seconds */
-#define   SDHC_CA1R_TCNTRT_32S_Val        _U_(0x6)   /**< \brief (SDHC_CA1R) 32 seconds */
-#define   SDHC_CA1R_TCNTRT_64S_Val        _U_(0x7)   /**< \brief (SDHC_CA1R) 64 seconds */
-#define   SDHC_CA1R_TCNTRT_128S_Val       _U_(0x8)   /**< \brief (SDHC_CA1R) 128 seconds */
-#define   SDHC_CA1R_TCNTRT_256S_Val       _U_(0x9)   /**< \brief (SDHC_CA1R) 256 seconds */
-#define   SDHC_CA1R_TCNTRT_512S_Val       _U_(0xA)   /**< \brief (SDHC_CA1R) 512 seconds */
-#define   SDHC_CA1R_TCNTRT_1024S_Val      _U_(0xB)   /**< \brief (SDHC_CA1R) 1024 seconds */
-#define   SDHC_CA1R_TCNTRT_OTHER_Val      _U_(0xF)   /**< \brief (SDHC_CA1R) Get information from other source */
-#define SDHC_CA1R_TCNTRT_DISABLED   (SDHC_CA1R_TCNTRT_DISABLED_Val << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_1S         (SDHC_CA1R_TCNTRT_1S_Val       << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_2S         (SDHC_CA1R_TCNTRT_2S_Val       << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_4S         (SDHC_CA1R_TCNTRT_4S_Val       << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_8S         (SDHC_CA1R_TCNTRT_8S_Val       << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_16S        (SDHC_CA1R_TCNTRT_16S_Val      << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_32S        (SDHC_CA1R_TCNTRT_32S_Val      << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_64S        (SDHC_CA1R_TCNTRT_64S_Val      << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_128S       (SDHC_CA1R_TCNTRT_128S_Val     << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_256S       (SDHC_CA1R_TCNTRT_256S_Val     << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_512S       (SDHC_CA1R_TCNTRT_512S_Val     << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_1024S      (SDHC_CA1R_TCNTRT_1024S_Val    << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TCNTRT_OTHER      (SDHC_CA1R_TCNTRT_OTHER_Val    << SDHC_CA1R_TCNTRT_Pos)
-#define SDHC_CA1R_TSDR50_Pos        13           /**< \brief (SDHC_CA1R) Use Tuning for SDR50 */
-#define SDHC_CA1R_TSDR50            (_U_(0x1) << SDHC_CA1R_TSDR50_Pos)
-#define   SDHC_CA1R_TSDR50_NO_Val         _U_(0x0)   /**< \brief (SDHC_CA1R) SDR50 does not require tuning */
-#define   SDHC_CA1R_TSDR50_YES_Val        _U_(0x1)   /**< \brief (SDHC_CA1R) SDR50 requires tuning */
-#define SDHC_CA1R_TSDR50_NO         (SDHC_CA1R_TSDR50_NO_Val       << SDHC_CA1R_TSDR50_Pos)
-#define SDHC_CA1R_TSDR50_YES        (SDHC_CA1R_TSDR50_YES_Val      << SDHC_CA1R_TSDR50_Pos)
-#define SDHC_CA1R_CLKMULT_Pos       16           /**< \brief (SDHC_CA1R) Clock Multiplier */
-#define SDHC_CA1R_CLKMULT_Msk       (_U_(0xFF) << SDHC_CA1R_CLKMULT_Pos)
-#define SDHC_CA1R_CLKMULT(value)    (SDHC_CA1R_CLKMULT_Msk & ((value) << SDHC_CA1R_CLKMULT_Pos))
-#define   SDHC_CA1R_CLKMULT_NO_Val        _U_(0x0)   /**< \brief (SDHC_CA1R) Clock Multiplier is Not Supported */
-#define SDHC_CA1R_CLKMULT_NO        (SDHC_CA1R_CLKMULT_NO_Val      << SDHC_CA1R_CLKMULT_Pos)
-#define SDHC_CA1R_MASK              _U_(0x00FF2F77) /**< \brief (SDHC_CA1R) MASK Register */
-
-/* -------- SDHC_MCCAR : (SDHC Offset: 0x048) (R/  32) Maximum Current Capabilities -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t MAXCUR33V:8;      /*!< bit:  0.. 7  Maximum Current for 3.3V           */
-    uint32_t MAXCUR30V:8;      /*!< bit:  8..15  Maximum Current for 3.0V           */
-    uint32_t MAXCUR18V:8;      /*!< bit: 16..23  Maximum Current for 1.8V           */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_MCCAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_MCCAR_OFFSET           0x048        /**< \brief (SDHC_MCCAR offset) Maximum Current Capabilities */
-#define SDHC_MCCAR_RESETVALUE       _U_(0x00000000) /**< \brief (SDHC_MCCAR reset_value) Maximum Current Capabilities */
-
-#define SDHC_MCCAR_MAXCUR33V_Pos    0            /**< \brief (SDHC_MCCAR) Maximum Current for 3.3V */
-#define SDHC_MCCAR_MAXCUR33V_Msk    (_U_(0xFF) << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR33V(value) (SDHC_MCCAR_MAXCUR33V_Msk & ((value) << SDHC_MCCAR_MAXCUR33V_Pos))
-#define   SDHC_MCCAR_MAXCUR33V_OTHER_Val  _U_(0x0)   /**< \brief (SDHC_MCCAR) Get information via another method */
-#define   SDHC_MCCAR_MAXCUR33V_4MA_Val    _U_(0x1)   /**< \brief (SDHC_MCCAR) 4mA */
-#define   SDHC_MCCAR_MAXCUR33V_8MA_Val    _U_(0x2)   /**< \brief (SDHC_MCCAR) 8mA */
-#define   SDHC_MCCAR_MAXCUR33V_12MA_Val   _U_(0x3)   /**< \brief (SDHC_MCCAR) 12mA */
-#define SDHC_MCCAR_MAXCUR33V_OTHER  (SDHC_MCCAR_MAXCUR33V_OTHER_Val << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR33V_4MA    (SDHC_MCCAR_MAXCUR33V_4MA_Val  << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR33V_8MA    (SDHC_MCCAR_MAXCUR33V_8MA_Val  << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR33V_12MA   (SDHC_MCCAR_MAXCUR33V_12MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)
-#define SDHC_MCCAR_MAXCUR30V_Pos    8            /**< \brief (SDHC_MCCAR) Maximum Current for 3.0V */
-#define SDHC_MCCAR_MAXCUR30V_Msk    (_U_(0xFF) << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR30V(value) (SDHC_MCCAR_MAXCUR30V_Msk & ((value) << SDHC_MCCAR_MAXCUR30V_Pos))
-#define   SDHC_MCCAR_MAXCUR30V_OTHER_Val  _U_(0x0)   /**< \brief (SDHC_MCCAR) Get information via another method */
-#define   SDHC_MCCAR_MAXCUR30V_4MA_Val    _U_(0x1)   /**< \brief (SDHC_MCCAR) 4mA */
-#define   SDHC_MCCAR_MAXCUR30V_8MA_Val    _U_(0x2)   /**< \brief (SDHC_MCCAR) 8mA */
-#define   SDHC_MCCAR_MAXCUR30V_12MA_Val   _U_(0x3)   /**< \brief (SDHC_MCCAR) 12mA */
-#define SDHC_MCCAR_MAXCUR30V_OTHER  (SDHC_MCCAR_MAXCUR30V_OTHER_Val << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR30V_4MA    (SDHC_MCCAR_MAXCUR30V_4MA_Val  << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR30V_8MA    (SDHC_MCCAR_MAXCUR30V_8MA_Val  << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR30V_12MA   (SDHC_MCCAR_MAXCUR30V_12MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)
-#define SDHC_MCCAR_MAXCUR18V_Pos    16           /**< \brief (SDHC_MCCAR) Maximum Current for 1.8V */
-#define SDHC_MCCAR_MAXCUR18V_Msk    (_U_(0xFF) << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MAXCUR18V(value) (SDHC_MCCAR_MAXCUR18V_Msk & ((value) << SDHC_MCCAR_MAXCUR18V_Pos))
-#define   SDHC_MCCAR_MAXCUR18V_OTHER_Val  _U_(0x0)   /**< \brief (SDHC_MCCAR) Get information via another method */
-#define   SDHC_MCCAR_MAXCUR18V_4MA_Val    _U_(0x1)   /**< \brief (SDHC_MCCAR) 4mA */
-#define   SDHC_MCCAR_MAXCUR18V_8MA_Val    _U_(0x2)   /**< \brief (SDHC_MCCAR) 8mA */
-#define   SDHC_MCCAR_MAXCUR18V_12MA_Val   _U_(0x3)   /**< \brief (SDHC_MCCAR) 12mA */
-#define SDHC_MCCAR_MAXCUR18V_OTHER  (SDHC_MCCAR_MAXCUR18V_OTHER_Val << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MAXCUR18V_4MA    (SDHC_MCCAR_MAXCUR18V_4MA_Val  << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MAXCUR18V_8MA    (SDHC_MCCAR_MAXCUR18V_8MA_Val  << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MAXCUR18V_12MA   (SDHC_MCCAR_MAXCUR18V_12MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)
-#define SDHC_MCCAR_MASK             _U_(0x00FFFFFF) /**< \brief (SDHC_MCCAR) MASK Register */
-
-/* -------- SDHC_FERACES : (SDHC Offset: 0x050) ( /W 16) Force Event for Auto CMD Error Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t ACMD12NE:1;       /*!< bit:      0  Force Event for Auto CMD12 Not Executed */
-    uint16_t ACMDTEO:1;        /*!< bit:      1  Force Event for Auto CMD Timeout Error */
-    uint16_t ACMDCRC:1;        /*!< bit:      2  Force Event for Auto CMD CRC Error */
-    uint16_t ACMDEND:1;        /*!< bit:      3  Force Event for Auto CMD End Bit Error */
-    uint16_t ACMDIDX:1;        /*!< bit:      4  Force Event for Auto CMD Index Error */
-    uint16_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint16_t CMDNI:1;          /*!< bit:      7  Force Event for Command Not Issued By Auto CMD12 Error */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_FERACES_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_FERACES_OFFSET         0x050        /**< \brief (SDHC_FERACES offset) Force Event for Auto CMD Error Status */
-#define SDHC_FERACES_RESETVALUE     _U_(0x0000)  /**< \brief (SDHC_FERACES reset_value) Force Event for Auto CMD Error Status */
-
-#define SDHC_FERACES_ACMD12NE_Pos   0            /**< \brief (SDHC_FERACES) Force Event for Auto CMD12 Not Executed */
-#define SDHC_FERACES_ACMD12NE       (_U_(0x1) << SDHC_FERACES_ACMD12NE_Pos)
-#define   SDHC_FERACES_ACMD12NE_NO_Val    _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
-#define   SDHC_FERACES_ACMD12NE_YES_Val   _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMD12NE_NO    (SDHC_FERACES_ACMD12NE_NO_Val  << SDHC_FERACES_ACMD12NE_Pos)
-#define SDHC_FERACES_ACMD12NE_YES   (SDHC_FERACES_ACMD12NE_YES_Val << SDHC_FERACES_ACMD12NE_Pos)
-#define SDHC_FERACES_ACMDTEO_Pos    1            /**< \brief (SDHC_FERACES) Force Event for Auto CMD Timeout Error */
-#define SDHC_FERACES_ACMDTEO        (_U_(0x1) << SDHC_FERACES_ACMDTEO_Pos)
-#define   SDHC_FERACES_ACMDTEO_NO_Val     _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
-#define   SDHC_FERACES_ACMDTEO_YES_Val    _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMDTEO_NO     (SDHC_FERACES_ACMDTEO_NO_Val   << SDHC_FERACES_ACMDTEO_Pos)
-#define SDHC_FERACES_ACMDTEO_YES    (SDHC_FERACES_ACMDTEO_YES_Val  << SDHC_FERACES_ACMDTEO_Pos)
-#define SDHC_FERACES_ACMDCRC_Pos    2            /**< \brief (SDHC_FERACES) Force Event for Auto CMD CRC Error */
-#define SDHC_FERACES_ACMDCRC        (_U_(0x1) << SDHC_FERACES_ACMDCRC_Pos)
-#define   SDHC_FERACES_ACMDCRC_NO_Val     _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
-#define   SDHC_FERACES_ACMDCRC_YES_Val    _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMDCRC_NO     (SDHC_FERACES_ACMDCRC_NO_Val   << SDHC_FERACES_ACMDCRC_Pos)
-#define SDHC_FERACES_ACMDCRC_YES    (SDHC_FERACES_ACMDCRC_YES_Val  << SDHC_FERACES_ACMDCRC_Pos)
-#define SDHC_FERACES_ACMDEND_Pos    3            /**< \brief (SDHC_FERACES) Force Event for Auto CMD End Bit Error */
-#define SDHC_FERACES_ACMDEND        (_U_(0x1) << SDHC_FERACES_ACMDEND_Pos)
-#define   SDHC_FERACES_ACMDEND_NO_Val     _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
-#define   SDHC_FERACES_ACMDEND_YES_Val    _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMDEND_NO     (SDHC_FERACES_ACMDEND_NO_Val   << SDHC_FERACES_ACMDEND_Pos)
-#define SDHC_FERACES_ACMDEND_YES    (SDHC_FERACES_ACMDEND_YES_Val  << SDHC_FERACES_ACMDEND_Pos)
-#define SDHC_FERACES_ACMDIDX_Pos    4            /**< \brief (SDHC_FERACES) Force Event for Auto CMD Index Error */
-#define SDHC_FERACES_ACMDIDX        (_U_(0x1) << SDHC_FERACES_ACMDIDX_Pos)
-#define   SDHC_FERACES_ACMDIDX_NO_Val     _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
-#define   SDHC_FERACES_ACMDIDX_YES_Val    _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_ACMDIDX_NO     (SDHC_FERACES_ACMDIDX_NO_Val   << SDHC_FERACES_ACMDIDX_Pos)
-#define SDHC_FERACES_ACMDIDX_YES    (SDHC_FERACES_ACMDIDX_YES_Val  << SDHC_FERACES_ACMDIDX_Pos)
-#define SDHC_FERACES_CMDNI_Pos      7            /**< \brief (SDHC_FERACES) Force Event for Command Not Issued By Auto CMD12 Error */
-#define SDHC_FERACES_CMDNI          (_U_(0x1) << SDHC_FERACES_CMDNI_Pos)
-#define   SDHC_FERACES_CMDNI_NO_Val       _U_(0x0)   /**< \brief (SDHC_FERACES) No Interrupt */
-#define   SDHC_FERACES_CMDNI_YES_Val      _U_(0x1)   /**< \brief (SDHC_FERACES) Interrupt is generated */
-#define SDHC_FERACES_CMDNI_NO       (SDHC_FERACES_CMDNI_NO_Val     << SDHC_FERACES_CMDNI_Pos)
-#define SDHC_FERACES_CMDNI_YES      (SDHC_FERACES_CMDNI_YES_Val    << SDHC_FERACES_CMDNI_Pos)
-#define SDHC_FERACES_MASK           _U_(0x009F)  /**< \brief (SDHC_FERACES) MASK Register */
-
-/* -------- SDHC_FEREIS : (SDHC Offset: 0x052) ( /W 16) Force Event for Error Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CMDTEO:1;         /*!< bit:      0  Force Event for Command Timeout Error */
-    uint16_t CMDCRC:1;         /*!< bit:      1  Force Event for Command CRC Error  */
-    uint16_t CMDEND:1;         /*!< bit:      2  Force Event for Command End Bit Error */
-    uint16_t CMDIDX:1;         /*!< bit:      3  Force Event for Command Index Error */
-    uint16_t DATTEO:1;         /*!< bit:      4  Force Event for Data Timeout Error */
-    uint16_t DATCRC:1;         /*!< bit:      5  Force Event for Data CRC Error     */
-    uint16_t DATEND:1;         /*!< bit:      6  Force Event for Data End Bit Error */
-    uint16_t CURLIM:1;         /*!< bit:      7  Force Event for Current Limit Error */
-    uint16_t ACMD:1;           /*!< bit:      8  Force Event for Auto CMD Error     */
-    uint16_t ADMA:1;           /*!< bit:      9  Force Event for ADMA Error         */
-    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
-    uint16_t BOOTAE:1;         /*!< bit:     12  Force Event for Boot Acknowledge Error */
-    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_FEREIS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_FEREIS_OFFSET          0x052        /**< \brief (SDHC_FEREIS offset) Force Event for Error Interrupt Status */
-#define SDHC_FEREIS_RESETVALUE      _U_(0x0000)  /**< \brief (SDHC_FEREIS reset_value) Force Event for Error Interrupt Status */
-
-#define SDHC_FEREIS_CMDTEO_Pos      0            /**< \brief (SDHC_FEREIS) Force Event for Command Timeout Error */
-#define SDHC_FEREIS_CMDTEO          (_U_(0x1) << SDHC_FEREIS_CMDTEO_Pos)
-#define   SDHC_FEREIS_CMDTEO_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_CMDTEO_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CMDTEO_NO       (SDHC_FEREIS_CMDTEO_NO_Val     << SDHC_FEREIS_CMDTEO_Pos)
-#define SDHC_FEREIS_CMDTEO_YES      (SDHC_FEREIS_CMDTEO_YES_Val    << SDHC_FEREIS_CMDTEO_Pos)
-#define SDHC_FEREIS_CMDCRC_Pos      1            /**< \brief (SDHC_FEREIS) Force Event for Command CRC Error */
-#define SDHC_FEREIS_CMDCRC          (_U_(0x1) << SDHC_FEREIS_CMDCRC_Pos)
-#define   SDHC_FEREIS_CMDCRC_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_CMDCRC_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CMDCRC_NO       (SDHC_FEREIS_CMDCRC_NO_Val     << SDHC_FEREIS_CMDCRC_Pos)
-#define SDHC_FEREIS_CMDCRC_YES      (SDHC_FEREIS_CMDCRC_YES_Val    << SDHC_FEREIS_CMDCRC_Pos)
-#define SDHC_FEREIS_CMDEND_Pos      2            /**< \brief (SDHC_FEREIS) Force Event for Command End Bit Error */
-#define SDHC_FEREIS_CMDEND          (_U_(0x1) << SDHC_FEREIS_CMDEND_Pos)
-#define   SDHC_FEREIS_CMDEND_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_CMDEND_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CMDEND_NO       (SDHC_FEREIS_CMDEND_NO_Val     << SDHC_FEREIS_CMDEND_Pos)
-#define SDHC_FEREIS_CMDEND_YES      (SDHC_FEREIS_CMDEND_YES_Val    << SDHC_FEREIS_CMDEND_Pos)
-#define SDHC_FEREIS_CMDIDX_Pos      3            /**< \brief (SDHC_FEREIS) Force Event for Command Index Error */
-#define SDHC_FEREIS_CMDIDX          (_U_(0x1) << SDHC_FEREIS_CMDIDX_Pos)
-#define   SDHC_FEREIS_CMDIDX_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_CMDIDX_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CMDIDX_NO       (SDHC_FEREIS_CMDIDX_NO_Val     << SDHC_FEREIS_CMDIDX_Pos)
-#define SDHC_FEREIS_CMDIDX_YES      (SDHC_FEREIS_CMDIDX_YES_Val    << SDHC_FEREIS_CMDIDX_Pos)
-#define SDHC_FEREIS_DATTEO_Pos      4            /**< \brief (SDHC_FEREIS) Force Event for Data Timeout Error */
-#define SDHC_FEREIS_DATTEO          (_U_(0x1) << SDHC_FEREIS_DATTEO_Pos)
-#define   SDHC_FEREIS_DATTEO_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_DATTEO_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_DATTEO_NO       (SDHC_FEREIS_DATTEO_NO_Val     << SDHC_FEREIS_DATTEO_Pos)
-#define SDHC_FEREIS_DATTEO_YES      (SDHC_FEREIS_DATTEO_YES_Val    << SDHC_FEREIS_DATTEO_Pos)
-#define SDHC_FEREIS_DATCRC_Pos      5            /**< \brief (SDHC_FEREIS) Force Event for Data CRC Error */
-#define SDHC_FEREIS_DATCRC          (_U_(0x1) << SDHC_FEREIS_DATCRC_Pos)
-#define   SDHC_FEREIS_DATCRC_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_DATCRC_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_DATCRC_NO       (SDHC_FEREIS_DATCRC_NO_Val     << SDHC_FEREIS_DATCRC_Pos)
-#define SDHC_FEREIS_DATCRC_YES      (SDHC_FEREIS_DATCRC_YES_Val    << SDHC_FEREIS_DATCRC_Pos)
-#define SDHC_FEREIS_DATEND_Pos      6            /**< \brief (SDHC_FEREIS) Force Event for Data End Bit Error */
-#define SDHC_FEREIS_DATEND          (_U_(0x1) << SDHC_FEREIS_DATEND_Pos)
-#define   SDHC_FEREIS_DATEND_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_DATEND_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_DATEND_NO       (SDHC_FEREIS_DATEND_NO_Val     << SDHC_FEREIS_DATEND_Pos)
-#define SDHC_FEREIS_DATEND_YES      (SDHC_FEREIS_DATEND_YES_Val    << SDHC_FEREIS_DATEND_Pos)
-#define SDHC_FEREIS_CURLIM_Pos      7            /**< \brief (SDHC_FEREIS) Force Event for Current Limit Error */
-#define SDHC_FEREIS_CURLIM          (_U_(0x1) << SDHC_FEREIS_CURLIM_Pos)
-#define   SDHC_FEREIS_CURLIM_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_CURLIM_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_CURLIM_NO       (SDHC_FEREIS_CURLIM_NO_Val     << SDHC_FEREIS_CURLIM_Pos)
-#define SDHC_FEREIS_CURLIM_YES      (SDHC_FEREIS_CURLIM_YES_Val    << SDHC_FEREIS_CURLIM_Pos)
-#define SDHC_FEREIS_ACMD_Pos        8            /**< \brief (SDHC_FEREIS) Force Event for Auto CMD Error */
-#define SDHC_FEREIS_ACMD            (_U_(0x1) << SDHC_FEREIS_ACMD_Pos)
-#define   SDHC_FEREIS_ACMD_NO_Val         _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_ACMD_YES_Val        _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_ACMD_NO         (SDHC_FEREIS_ACMD_NO_Val       << SDHC_FEREIS_ACMD_Pos)
-#define SDHC_FEREIS_ACMD_YES        (SDHC_FEREIS_ACMD_YES_Val      << SDHC_FEREIS_ACMD_Pos)
-#define SDHC_FEREIS_ADMA_Pos        9            /**< \brief (SDHC_FEREIS) Force Event for ADMA Error */
-#define SDHC_FEREIS_ADMA            (_U_(0x1) << SDHC_FEREIS_ADMA_Pos)
-#define   SDHC_FEREIS_ADMA_NO_Val         _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_ADMA_YES_Val        _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_ADMA_NO         (SDHC_FEREIS_ADMA_NO_Val       << SDHC_FEREIS_ADMA_Pos)
-#define SDHC_FEREIS_ADMA_YES        (SDHC_FEREIS_ADMA_YES_Val      << SDHC_FEREIS_ADMA_Pos)
-#define SDHC_FEREIS_BOOTAE_Pos      12           /**< \brief (SDHC_FEREIS) Force Event for Boot Acknowledge Error */
-#define SDHC_FEREIS_BOOTAE          (_U_(0x1) << SDHC_FEREIS_BOOTAE_Pos)
-#define   SDHC_FEREIS_BOOTAE_NO_Val       _U_(0x0)   /**< \brief (SDHC_FEREIS) No Interrupt */
-#define   SDHC_FEREIS_BOOTAE_YES_Val      _U_(0x1)   /**< \brief (SDHC_FEREIS) Interrupt is generated */
-#define SDHC_FEREIS_BOOTAE_NO       (SDHC_FEREIS_BOOTAE_NO_Val     << SDHC_FEREIS_BOOTAE_Pos)
-#define SDHC_FEREIS_BOOTAE_YES      (SDHC_FEREIS_BOOTAE_YES_Val    << SDHC_FEREIS_BOOTAE_Pos)
-#define SDHC_FEREIS_MASK            _U_(0x13FF)  /**< \brief (SDHC_FEREIS) MASK Register */
-
-/* -------- SDHC_AESR : (SDHC Offset: 0x054) (R/   8) ADMA Error Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ERRST:2;          /*!< bit:  0.. 1  ADMA Error State                   */
-    uint8_t  LMIS:1;           /*!< bit:      2  ADMA Length Mismatch Error         */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_AESR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_AESR_OFFSET            0x054        /**< \brief (SDHC_AESR offset) ADMA Error Status */
-#define SDHC_AESR_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_AESR reset_value) ADMA Error Status */
-
-#define SDHC_AESR_ERRST_Pos         0            /**< \brief (SDHC_AESR) ADMA Error State */
-#define SDHC_AESR_ERRST_Msk         (_U_(0x3) << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_ERRST(value)      (SDHC_AESR_ERRST_Msk & ((value) << SDHC_AESR_ERRST_Pos))
-#define   SDHC_AESR_ERRST_STOP_Val        _U_(0x0)   /**< \brief (SDHC_AESR) ST_STOP (Stop DMA) */
-#define   SDHC_AESR_ERRST_FDS_Val         _U_(0x1)   /**< \brief (SDHC_AESR) ST_FDS (Fetch Descriptor) */
-#define   SDHC_AESR_ERRST_2_Val           _U_(0x2)   /**< \brief (SDHC_AESR) Reserved */
-#define   SDHC_AESR_ERRST_TFR_Val         _U_(0x3)   /**< \brief (SDHC_AESR) ST_TFR (Transfer Data) */
-#define SDHC_AESR_ERRST_STOP        (SDHC_AESR_ERRST_STOP_Val      << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_ERRST_FDS         (SDHC_AESR_ERRST_FDS_Val       << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_ERRST_2           (SDHC_AESR_ERRST_2_Val         << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_ERRST_TFR         (SDHC_AESR_ERRST_TFR_Val       << SDHC_AESR_ERRST_Pos)
-#define SDHC_AESR_LMIS_Pos          2            /**< \brief (SDHC_AESR) ADMA Length Mismatch Error */
-#define SDHC_AESR_LMIS              (_U_(0x1) << SDHC_AESR_LMIS_Pos)
-#define   SDHC_AESR_LMIS_NO_Val           _U_(0x0)   /**< \brief (SDHC_AESR) No Error */
-#define   SDHC_AESR_LMIS_YES_Val          _U_(0x1)   /**< \brief (SDHC_AESR) Error */
-#define SDHC_AESR_LMIS_NO           (SDHC_AESR_LMIS_NO_Val         << SDHC_AESR_LMIS_Pos)
-#define SDHC_AESR_LMIS_YES          (SDHC_AESR_LMIS_YES_Val        << SDHC_AESR_LMIS_Pos)
-#define SDHC_AESR_MASK              _U_(0x07)    /**< \brief (SDHC_AESR) MASK Register */
-
-/* -------- SDHC_ASAR : (SDHC Offset: 0x058) (R/W 32) ADMA System Address n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADMASA:32;        /*!< bit:  0..31  ADMA System Address                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_ASAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_ASAR_OFFSET            0x058        /**< \brief (SDHC_ASAR offset) ADMA System Address n */
-#define SDHC_ASAR_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_ASAR reset_value) ADMA System Address n */
-
-#define SDHC_ASAR_ADMASA_Pos        0            /**< \brief (SDHC_ASAR) ADMA System Address */
-#define SDHC_ASAR_ADMASA_Msk        (_U_(0xFFFFFFFF) << SDHC_ASAR_ADMASA_Pos)
-#define SDHC_ASAR_ADMASA(value)     (SDHC_ASAR_ADMASA_Msk & ((value) << SDHC_ASAR_ADMASA_Pos))
-#define SDHC_ASAR_MASK              _U_(0xFFFFFFFF) /**< \brief (SDHC_ASAR) MASK Register */
-
-/* -------- SDHC_PVR : (SDHC Offset: 0x060) (R/W 16) Preset Value n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SDCLKFSEL:10;     /*!< bit:  0.. 9  SDCLK Frequency Select Value for Initialization */
-    uint16_t CLKGSEL:1;        /*!< bit:     10  Clock Generator Select Value for Initialization */
-    uint16_t :3;               /*!< bit: 11..13  Reserved                           */
-    uint16_t DRVSEL:2;         /*!< bit: 14..15  Driver Strength Select Value for Initialization */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_PVR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_PVR_OFFSET             0x060        /**< \brief (SDHC_PVR offset) Preset Value n */
-#define SDHC_PVR_RESETVALUE         _U_(0x0000)  /**< \brief (SDHC_PVR reset_value) Preset Value n */
-
-#define SDHC_PVR_SDCLKFSEL_Pos      0            /**< \brief (SDHC_PVR) SDCLK Frequency Select Value for Initialization */
-#define SDHC_PVR_SDCLKFSEL_Msk      (_U_(0x3FF) << SDHC_PVR_SDCLKFSEL_Pos)
-#define SDHC_PVR_SDCLKFSEL(value)   (SDHC_PVR_SDCLKFSEL_Msk & ((value) << SDHC_PVR_SDCLKFSEL_Pos))
-#define SDHC_PVR_CLKGSEL_Pos        10           /**< \brief (SDHC_PVR) Clock Generator Select Value for Initialization */
-#define SDHC_PVR_CLKGSEL            (_U_(0x1) << SDHC_PVR_CLKGSEL_Pos)
-#define   SDHC_PVR_CLKGSEL_DIV_Val        _U_(0x0)   /**< \brief (SDHC_PVR) Host Controller Ver2.00 Compatible Clock Generator (Divider) */
-#define   SDHC_PVR_CLKGSEL_PROG_Val       _U_(0x1)   /**< \brief (SDHC_PVR) Programmable Clock Generator */
-#define SDHC_PVR_CLKGSEL_DIV        (SDHC_PVR_CLKGSEL_DIV_Val      << SDHC_PVR_CLKGSEL_Pos)
-#define SDHC_PVR_CLKGSEL_PROG       (SDHC_PVR_CLKGSEL_PROG_Val     << SDHC_PVR_CLKGSEL_Pos)
-#define SDHC_PVR_DRVSEL_Pos         14           /**< \brief (SDHC_PVR) Driver Strength Select Value for Initialization */
-#define SDHC_PVR_DRVSEL_Msk         (_U_(0x3) << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_DRVSEL(value)      (SDHC_PVR_DRVSEL_Msk & ((value) << SDHC_PVR_DRVSEL_Pos))
-#define   SDHC_PVR_DRVSEL_B_Val           _U_(0x0)   /**< \brief (SDHC_PVR) Driver Type B is Selected */
-#define   SDHC_PVR_DRVSEL_A_Val           _U_(0x1)   /**< \brief (SDHC_PVR) Driver Type A is Selected */
-#define   SDHC_PVR_DRVSEL_C_Val           _U_(0x2)   /**< \brief (SDHC_PVR) Driver Type C is Selected */
-#define   SDHC_PVR_DRVSEL_D_Val           _U_(0x3)   /**< \brief (SDHC_PVR) Driver Type D is Selected */
-#define SDHC_PVR_DRVSEL_B           (SDHC_PVR_DRVSEL_B_Val         << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_DRVSEL_A           (SDHC_PVR_DRVSEL_A_Val         << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_DRVSEL_C           (SDHC_PVR_DRVSEL_C_Val         << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_DRVSEL_D           (SDHC_PVR_DRVSEL_D_Val         << SDHC_PVR_DRVSEL_Pos)
-#define SDHC_PVR_MASK               _U_(0xC7FF)  /**< \brief (SDHC_PVR) MASK Register */
-
-/* -------- SDHC_SISR : (SDHC Offset: 0x0FC) (R/  16) Slot Interrupt Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t INTSSL:1;         /*!< bit:      0  Interrupt Signal for Each Slot     */
-    uint16_t :15;              /*!< bit:  1..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_SISR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_SISR_OFFSET            0x0FC        /**< \brief (SDHC_SISR offset) Slot Interrupt Status */
-#define SDHC_SISR_RESETVALUE        _U_(0x20000) /**< \brief (SDHC_SISR reset_value) Slot Interrupt Status */
-
-#define SDHC_SISR_INTSSL_Pos        0            /**< \brief (SDHC_SISR) Interrupt Signal for Each Slot */
-#define SDHC_SISR_INTSSL_Msk        (_U_(0x1) << SDHC_SISR_INTSSL_Pos)
-#define SDHC_SISR_INTSSL(value)     (SDHC_SISR_INTSSL_Msk & ((value) << SDHC_SISR_INTSSL_Pos))
-#define SDHC_SISR_MASK              _U_(0x0001)  /**< \brief (SDHC_SISR) MASK Register */
-
-/* -------- SDHC_HCVR : (SDHC Offset: 0x0FE) (R/  16) Host Controller Version -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SVER:8;           /*!< bit:  0.. 7  Spec Version                       */
-    uint16_t VVER:8;           /*!< bit:  8..15  Vendor Version                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SDHC_HCVR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_HCVR_OFFSET            0x0FE        /**< \brief (SDHC_HCVR offset) Host Controller Version */
-#define SDHC_HCVR_RESETVALUE        _U_(0x1802)  /**< \brief (SDHC_HCVR reset_value) Host Controller Version */
-
-#define SDHC_HCVR_SVER_Pos          0            /**< \brief (SDHC_HCVR) Spec Version */
-#define SDHC_HCVR_SVER_Msk          (_U_(0xFF) << SDHC_HCVR_SVER_Pos)
-#define SDHC_HCVR_SVER(value)       (SDHC_HCVR_SVER_Msk & ((value) << SDHC_HCVR_SVER_Pos))
-#define SDHC_HCVR_VVER_Pos          8            /**< \brief (SDHC_HCVR) Vendor Version */
-#define SDHC_HCVR_VVER_Msk          (_U_(0xFF) << SDHC_HCVR_VVER_Pos)
-#define SDHC_HCVR_VVER(value)       (SDHC_HCVR_VVER_Msk & ((value) << SDHC_HCVR_VVER_Pos))
-#define SDHC_HCVR_MASK              _U_(0xFFFF)  /**< \brief (SDHC_HCVR) MASK Register */
-
-/* -------- SDHC_MC1R : (SDHC Offset: 0x204) (R/W  8) MMC Control 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CMDTYP:2;         /*!< bit:  0.. 1  e.MMC Command Type                 */
-    uint8_t  :1;               /*!< bit:      2  Reserved                           */
-    uint8_t  DDR:1;            /*!< bit:      3  e.MMC HSDDR Mode                   */
-    uint8_t  OPD:1;            /*!< bit:      4  e.MMC Open Drain Mode              */
-    uint8_t  BOOTA:1;          /*!< bit:      5  e.MMC Boot Acknowledge Enable      */
-    uint8_t  RSTN:1;           /*!< bit:      6  e.MMC Reset Signal                 */
-    uint8_t  FCD:1;            /*!< bit:      7  e.MMC Force Card Detect            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_MC1R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_MC1R_OFFSET            0x204        /**< \brief (SDHC_MC1R offset) MMC Control 1 */
-#define SDHC_MC1R_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_MC1R reset_value) MMC Control 1 */
-
-#define SDHC_MC1R_CMDTYP_Pos        0            /**< \brief (SDHC_MC1R) e.MMC Command Type */
-#define SDHC_MC1R_CMDTYP_Msk        (_U_(0x3) << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_CMDTYP(value)     (SDHC_MC1R_CMDTYP_Msk & ((value) << SDHC_MC1R_CMDTYP_Pos))
-#define   SDHC_MC1R_CMDTYP_NORMAL_Val     _U_(0x0)   /**< \brief (SDHC_MC1R) Not a MMC specific command */
-#define   SDHC_MC1R_CMDTYP_WAITIRQ_Val    _U_(0x1)   /**< \brief (SDHC_MC1R) Wait IRQ Command */
-#define   SDHC_MC1R_CMDTYP_STREAM_Val     _U_(0x2)   /**< \brief (SDHC_MC1R) Stream Command */
-#define   SDHC_MC1R_CMDTYP_BOOT_Val       _U_(0x3)   /**< \brief (SDHC_MC1R) Boot Command */
-#define SDHC_MC1R_CMDTYP_NORMAL     (SDHC_MC1R_CMDTYP_NORMAL_Val   << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_CMDTYP_WAITIRQ    (SDHC_MC1R_CMDTYP_WAITIRQ_Val  << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_CMDTYP_STREAM     (SDHC_MC1R_CMDTYP_STREAM_Val   << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_CMDTYP_BOOT       (SDHC_MC1R_CMDTYP_BOOT_Val     << SDHC_MC1R_CMDTYP_Pos)
-#define SDHC_MC1R_DDR_Pos           3            /**< \brief (SDHC_MC1R) e.MMC HSDDR Mode */
-#define SDHC_MC1R_DDR               (_U_(0x1) << SDHC_MC1R_DDR_Pos)
-#define SDHC_MC1R_OPD_Pos           4            /**< \brief (SDHC_MC1R) e.MMC Open Drain Mode */
-#define SDHC_MC1R_OPD               (_U_(0x1) << SDHC_MC1R_OPD_Pos)
-#define SDHC_MC1R_BOOTA_Pos         5            /**< \brief (SDHC_MC1R) e.MMC Boot Acknowledge Enable */
-#define SDHC_MC1R_BOOTA             (_U_(0x1) << SDHC_MC1R_BOOTA_Pos)
-#define SDHC_MC1R_RSTN_Pos          6            /**< \brief (SDHC_MC1R) e.MMC Reset Signal */
-#define SDHC_MC1R_RSTN              (_U_(0x1) << SDHC_MC1R_RSTN_Pos)
-#define SDHC_MC1R_FCD_Pos           7            /**< \brief (SDHC_MC1R) e.MMC Force Card Detect */
-#define SDHC_MC1R_FCD               (_U_(0x1) << SDHC_MC1R_FCD_Pos)
-#define SDHC_MC1R_MASK              _U_(0xFB)    /**< \brief (SDHC_MC1R) MASK Register */
-
-/* -------- SDHC_MC2R : (SDHC Offset: 0x205) ( /W  8) MMC Control 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SRESP:1;          /*!< bit:      0  e.MMC Abort Wait IRQ               */
-    uint8_t  ABOOT:1;          /*!< bit:      1  e.MMC Abort Boot                   */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_MC2R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_MC2R_OFFSET            0x205        /**< \brief (SDHC_MC2R offset) MMC Control 2 */
-#define SDHC_MC2R_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_MC2R reset_value) MMC Control 2 */
-
-#define SDHC_MC2R_SRESP_Pos         0            /**< \brief (SDHC_MC2R) e.MMC Abort Wait IRQ */
-#define SDHC_MC2R_SRESP             (_U_(0x1) << SDHC_MC2R_SRESP_Pos)
-#define SDHC_MC2R_ABOOT_Pos         1            /**< \brief (SDHC_MC2R) e.MMC Abort Boot */
-#define SDHC_MC2R_ABOOT             (_U_(0x1) << SDHC_MC2R_ABOOT_Pos)
-#define SDHC_MC2R_MASK              _U_(0x03)    /**< \brief (SDHC_MC2R) MASK Register */
-
-/* -------- SDHC_ACR : (SDHC Offset: 0x208) (R/W 32) AHB Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BMAX:2;           /*!< bit:  0.. 1  AHB Maximum Burst                  */
-    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_ACR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_ACR_OFFSET             0x208        /**< \brief (SDHC_ACR offset) AHB Control */
-#define SDHC_ACR_RESETVALUE         _U_(0x00000000) /**< \brief (SDHC_ACR reset_value) AHB Control */
-
-#define SDHC_ACR_BMAX_Pos           0            /**< \brief (SDHC_ACR) AHB Maximum Burst */
-#define SDHC_ACR_BMAX_Msk           (_U_(0x3) << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_BMAX(value)        (SDHC_ACR_BMAX_Msk & ((value) << SDHC_ACR_BMAX_Pos))
-#define   SDHC_ACR_BMAX_INCR16_Val        _U_(0x0)   /**< \brief (SDHC_ACR)  */
-#define   SDHC_ACR_BMAX_INCR8_Val         _U_(0x1)   /**< \brief (SDHC_ACR)  */
-#define   SDHC_ACR_BMAX_INCR4_Val         _U_(0x2)   /**< \brief (SDHC_ACR)  */
-#define   SDHC_ACR_BMAX_SINGLE_Val        _U_(0x3)   /**< \brief (SDHC_ACR)  */
-#define SDHC_ACR_BMAX_INCR16        (SDHC_ACR_BMAX_INCR16_Val      << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_BMAX_INCR8         (SDHC_ACR_BMAX_INCR8_Val       << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_BMAX_INCR4         (SDHC_ACR_BMAX_INCR4_Val       << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_BMAX_SINGLE        (SDHC_ACR_BMAX_SINGLE_Val      << SDHC_ACR_BMAX_Pos)
-#define SDHC_ACR_MASK               _U_(0x00000003) /**< \brief (SDHC_ACR) MASK Register */
-
-/* -------- SDHC_CC2R : (SDHC Offset: 0x20C) (R/W 32) Clock Control 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t FSDCLKD:1;        /*!< bit:      0  Force SDCK Disabled                */
-    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_CC2R_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CC2R_OFFSET            0x20C        /**< \brief (SDHC_CC2R offset) Clock Control 2 */
-#define SDHC_CC2R_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_CC2R reset_value) Clock Control 2 */
-
-#define SDHC_CC2R_FSDCLKD_Pos       0            /**< \brief (SDHC_CC2R) Force SDCK Disabled */
-#define SDHC_CC2R_FSDCLKD           (_U_(0x1) << SDHC_CC2R_FSDCLKD_Pos)
-#define   SDHC_CC2R_FSDCLKD_NOEFFECT_Val  _U_(0x0)   /**< \brief (SDHC_CC2R) No effect */
-#define   SDHC_CC2R_FSDCLKD_DISABLE_Val   _U_(0x1)   /**< \brief (SDHC_CC2R) SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled */
-#define SDHC_CC2R_FSDCLKD_NOEFFECT  (SDHC_CC2R_FSDCLKD_NOEFFECT_Val << SDHC_CC2R_FSDCLKD_Pos)
-#define SDHC_CC2R_FSDCLKD_DISABLE   (SDHC_CC2R_FSDCLKD_DISABLE_Val << SDHC_CC2R_FSDCLKD_Pos)
-#define SDHC_CC2R_MASK              _U_(0x00000001) /**< \brief (SDHC_CC2R) MASK Register */
-
-/* -------- SDHC_CACR : (SDHC Offset: 0x230) (R/W 32) Capabilities Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CAPWREN:1;        /*!< bit:      0  Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
-    uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
-    uint32_t KEY:8;            /*!< bit:  8..15  Key (0x46)                         */
-    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SDHC_CACR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_CACR_OFFSET            0x230        /**< \brief (SDHC_CACR offset) Capabilities Control */
-#define SDHC_CACR_RESETVALUE        _U_(0x00000000) /**< \brief (SDHC_CACR reset_value) Capabilities Control */
-
-#define SDHC_CACR_CAPWREN_Pos       0            /**< \brief (SDHC_CACR) Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */
-#define SDHC_CACR_CAPWREN           (_U_(0x1) << SDHC_CACR_CAPWREN_Pos)
-#define SDHC_CACR_KEY_Pos           8            /**< \brief (SDHC_CACR) Key (0x46) */
-#define SDHC_CACR_KEY_Msk           (_U_(0xFF) << SDHC_CACR_KEY_Pos)
-#define SDHC_CACR_KEY(value)        (SDHC_CACR_KEY_Msk & ((value) << SDHC_CACR_KEY_Pos))
-#define SDHC_CACR_MASK              _U_(0x0000FF01) /**< \brief (SDHC_CACR) MASK Register */
-
-/* -------- SDHC_DBGR : (SDHC Offset: 0x234) (R/W  8) Debug -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  NIDBG:1;          /*!< bit:      0  Non-intrusive debug enable         */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SDHC_DBGR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SDHC_DBGR_OFFSET            0x234        /**< \brief (SDHC_DBGR offset) Debug */
-#define SDHC_DBGR_RESETVALUE        _U_(0x00)    /**< \brief (SDHC_DBGR reset_value) Debug */
-
-#define SDHC_DBGR_NIDBG_Pos         0            /**< \brief (SDHC_DBGR) Non-intrusive debug enable */
-#define SDHC_DBGR_NIDBG             (_U_(0x1) << SDHC_DBGR_NIDBG_Pos)
-#define   SDHC_DBGR_NIDBG_IDBG_Val        _U_(0x0)   /**< \brief (SDHC_DBGR) Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) */
-#define   SDHC_DBGR_NIDBG_NIDBG_Val       _U_(0x1)   /**< \brief (SDHC_DBGR) Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) */
-#define SDHC_DBGR_NIDBG_IDBG        (SDHC_DBGR_NIDBG_IDBG_Val      << SDHC_DBGR_NIDBG_Pos)
-#define SDHC_DBGR_NIDBG_NIDBG       (SDHC_DBGR_NIDBG_NIDBG_Val     << SDHC_DBGR_NIDBG_Pos)
-#define SDHC_DBGR_MASK              _U_(0x01)    /**< \brief (SDHC_DBGR) MASK Register */
-
-/** \brief SDHC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO SDHC_SSAR_Type            SSAR;        /**< \brief Offset: 0x000 (R/W 32) SDMA System Address / Argument 2 */
-  __IO SDHC_BSR_Type             BSR;         /**< \brief Offset: 0x004 (R/W 16) Block Size */
-  __IO SDHC_BCR_Type             BCR;         /**< \brief Offset: 0x006 (R/W 16) Block Count */
-  __IO SDHC_ARG1R_Type           ARG1R;       /**< \brief Offset: 0x008 (R/W 32) Argument 1 */
-  __IO SDHC_TMR_Type             TMR;         /**< \brief Offset: 0x00C (R/W 16) Transfer Mode */
-  __IO SDHC_CR_Type              CR;          /**< \brief Offset: 0x00E (R/W 16) Command */
-  __I  SDHC_RR_Type              RR[4];       /**< \brief Offset: 0x010 (R/  32) Response */
-  __IO SDHC_BDPR_Type            BDPR;        /**< \brief Offset: 0x020 (R/W 32) Buffer Data Port */
-  __I  SDHC_PSR_Type             PSR;         /**< \brief Offset: 0x024 (R/  32) Present State */
-  __IO SDHC_HC1R_Type            HC1R;        /**< \brief Offset: 0x028 (R/W  8) Host Control 1 */
-  __IO SDHC_PCR_Type             PCR;         /**< \brief Offset: 0x029 (R/W  8) Power Control */
-  __IO SDHC_BGCR_Type            BGCR;        /**< \brief Offset: 0x02A (R/W  8) Block Gap Control */
-  __IO SDHC_WCR_Type             WCR;         /**< \brief Offset: 0x02B (R/W  8) Wakeup Control */
-  __IO SDHC_CCR_Type             CCR;         /**< \brief Offset: 0x02C (R/W 16) Clock Control */
-  __IO SDHC_TCR_Type             TCR;         /**< \brief Offset: 0x02E (R/W  8) Timeout Control */
-  __IO SDHC_SRR_Type             SRR;         /**< \brief Offset: 0x02F (R/W  8) Software Reset */
-  __IO SDHC_NISTR_Type           NISTR;       /**< \brief Offset: 0x030 (R/W 16) Normal Interrupt Status */
-  __IO SDHC_EISTR_Type           EISTR;       /**< \brief Offset: 0x032 (R/W 16) Error Interrupt Status */
-  __IO SDHC_NISTER_Type          NISTER;      /**< \brief Offset: 0x034 (R/W 16) Normal Interrupt Status Enable */
-  __IO SDHC_EISTER_Type          EISTER;      /**< \brief Offset: 0x036 (R/W 16) Error Interrupt Status Enable */
-  __IO SDHC_NISIER_Type          NISIER;      /**< \brief Offset: 0x038 (R/W 16) Normal Interrupt Signal Enable */
-  __IO SDHC_EISIER_Type          EISIER;      /**< \brief Offset: 0x03A (R/W 16) Error Interrupt Signal Enable */
-  __I  SDHC_ACESR_Type           ACESR;       /**< \brief Offset: 0x03C (R/  16) Auto CMD Error Status */
-  __IO SDHC_HC2R_Type            HC2R;        /**< \brief Offset: 0x03E (R/W 16) Host Control 2 */
-  __I  SDHC_CA0R_Type            CA0R;        /**< \brief Offset: 0x040 (R/  32) Capabilities 0 */
-  __I  SDHC_CA1R_Type            CA1R;        /**< \brief Offset: 0x044 (R/  32) Capabilities 1 */
-  __I  SDHC_MCCAR_Type           MCCAR;       /**< \brief Offset: 0x048 (R/  32) Maximum Current Capabilities */
-       RoReg8                    Reserved1[0x4];
-  __O  SDHC_FERACES_Type         FERACES;     /**< \brief Offset: 0x050 ( /W 16) Force Event for Auto CMD Error Status */
-  __O  SDHC_FEREIS_Type          FEREIS;      /**< \brief Offset: 0x052 ( /W 16) Force Event for Error Interrupt Status */
-  __I  SDHC_AESR_Type            AESR;        /**< \brief Offset: 0x054 (R/   8) ADMA Error Status */
-       RoReg8                    Reserved2[0x3];
-  __IO SDHC_ASAR_Type            ASAR[1];     /**< \brief Offset: 0x058 (R/W 32) ADMA System Address n */
-       RoReg8                    Reserved3[0x4];
-  __IO SDHC_PVR_Type             PVR[8];      /**< \brief Offset: 0x060 (R/W 16) Preset Value n */
-       RoReg8                    Reserved4[0x8C];
-  __I  SDHC_SISR_Type            SISR;        /**< \brief Offset: 0x0FC (R/  16) Slot Interrupt Status */
-  __I  SDHC_HCVR_Type            HCVR;        /**< \brief Offset: 0x0FE (R/  16) Host Controller Version */
-       RoReg8                    Reserved5[0x104];
-  __IO SDHC_MC1R_Type            MC1R;        /**< \brief Offset: 0x204 (R/W  8) MMC Control 1 */
-  __O  SDHC_MC2R_Type            MC2R;        /**< \brief Offset: 0x205 ( /W  8) MMC Control 2 */
-       RoReg8                    Reserved6[0x2];
-  __IO SDHC_ACR_Type             ACR;         /**< \brief Offset: 0x208 (R/W 32) AHB Control */
-  __IO SDHC_CC2R_Type            CC2R;        /**< \brief Offset: 0x20C (R/W 32) Clock Control 2 */
-       RoReg8                    Reserved7[0x20];
-  __IO SDHC_CACR_Type            CACR;        /**< \brief Offset: 0x230 (R/W 32) Capabilities Control */
-  __IO SDHC_DBGR_Type            DBGR;        /**< \brief Offset: 0x234 (R/W  8) Debug */
-} Sdhc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_SDHC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sercom.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sercom.h
deleted file mode 100644
index f884c127a5..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sercom.h
+++ /dev/null
@@ -1,1680 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for SERCOM
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SERCOM_COMPONENT_
-#define _SAMD51_SERCOM_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR SERCOM */
-/* ========================================================================== */
-/** \addtogroup SAMD51_SERCOM Serial Communication Interface */
-/*@{*/
-
-#define SERCOM_U2201
-#define REV_SERCOM                  0x500
-
-/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run in Standby                     */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
-    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
-    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
-    uint32_t MEXTTOEN:1;       /*!< bit:     22  Master SCL Low Extend Timeout      */
-    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
-    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
-    uint32_t :1;               /*!< bit:     26  Reserved                           */
-    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
-    uint32_t INACTOUT:2;       /*!< bit: 28..29  Inactive Time-Out                  */
-    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
-#define SERCOM_I2CM_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
-
-#define SERCOM_I2CM_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
-#define SERCOM_I2CM_CTRLA_SWRST     (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)
-#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_CTRLA) Enable */
-#define SERCOM_I2CM_CTRLA_ENABLE    (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
-#define SERCOM_I2CM_CTRLA_MODE_Msk  (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)
-#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
-#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
-#define SERCOM_I2CM_CTRLA_RUNSTDBY  (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
-#define SERCOM_I2CM_CTRLA_PINOUT    (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)
-#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
-#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
-#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
-#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22           /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
-#define SERCOM_I2CM_CTRLA_MEXTTOEN  (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
-#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CM_CTRLA_SEXTTOEN  (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
-#define SERCOM_I2CM_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
-#define SERCOM_I2CM_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)
-#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
-#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
-#define SERCOM_I2CM_CTRLA_SCLSM     (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)
-#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28           /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
-#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
-#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
-#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
-#define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
-#define SERCOM_I2CM_CTRLA_MASK      _U_(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
-
-/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t PINOUT:1;         /*!< bit:     16  Pin Usage                          */
-    uint32_t :3;               /*!< bit: 17..19  Reserved                           */
-    uint32_t SDAHOLD:2;        /*!< bit: 20..21  SDA Hold Time                      */
-    uint32_t :1;               /*!< bit:     22  Reserved                           */
-    uint32_t SEXTTOEN:1;       /*!< bit:     23  Slave SCL Low Extend Timeout       */
-    uint32_t SPEED:2;          /*!< bit: 24..25  Transfer Speed                     */
-    uint32_t :1;               /*!< bit:     26  Reserved                           */
-    uint32_t SCLSM:1;          /*!< bit:     27  SCL Clock Stretch Mode             */
-    uint32_t :2;               /*!< bit: 28..29  Reserved                           */
-    uint32_t LOWTOUTEN:1;      /*!< bit:     30  SCL Low Timeout Enable             */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_CTRLA_OFFSET    0x00         /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
-#define SERCOM_I2CS_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
-
-#define SERCOM_I2CS_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
-#define SERCOM_I2CS_CTRLA_SWRST     (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)
-#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_CTRLA) Enable */
-#define SERCOM_I2CS_CTRLA_ENABLE    (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE_Pos  2            /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
-#define SERCOM_I2CS_CTRLA_MODE_Msk  (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)
-#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
-#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
-#define SERCOM_I2CS_CTRLA_RUNSTDBY  (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16           /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
-#define SERCOM_I2CS_CTRLA_PINOUT    (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)
-#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20           /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
-#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
-#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
-#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23           /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CS_CTRLA_SEXTTOEN  (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
-#define SERCOM_I2CS_CTRLA_SPEED_Pos 24           /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
-#define SERCOM_I2CS_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)
-#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
-#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27           /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
-#define SERCOM_I2CS_CTRLA_SCLSM     (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)
-#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30           /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
-#define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
-#define SERCOM_I2CS_CTRLA_MASK      _U_(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
-
-/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
-    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
-    uint32_t :7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t DOPO:2;           /*!< bit: 16..17  Data Out Pinout                    */
-    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
-    uint32_t DIPO:2;           /*!< bit: 20..21  Data In Pinout                     */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
-    uint32_t CPHA:1;           /*!< bit:     28  Clock Phase                        */
-    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
-    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_CTRLA_OFFSET     0x00         /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
-#define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
-
-#define SERCOM_SPI_CTRLA_SWRST_Pos  0            /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
-#define SERCOM_SPI_CTRLA_SWRST      (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos)
-#define SERCOM_SPI_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_CTRLA) Enable */
-#define SERCOM_SPI_CTRLA_ENABLE     (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos)
-#define SERCOM_SPI_CTRLA_MODE_Pos   2            /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
-#define SERCOM_SPI_CTRLA_MODE_Msk   (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos)
-#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
-#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
-#define SERCOM_SPI_CTRLA_RUNSTDBY   (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_SPI_CTRLA_IBON_Pos   8            /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
-#define SERCOM_SPI_CTRLA_IBON       (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos)
-#define SERCOM_SPI_CTRLA_DOPO_Pos   16           /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
-#define SERCOM_SPI_CTRLA_DOPO_Msk   (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos)
-#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
-#define SERCOM_SPI_CTRLA_DIPO_Pos   20           /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
-#define SERCOM_SPI_CTRLA_DIPO_Msk   (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos)
-#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
-#define SERCOM_SPI_CTRLA_FORM_Pos   24           /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
-#define SERCOM_SPI_CTRLA_FORM_Msk   (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos)
-#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
-#define SERCOM_SPI_CTRLA_CPHA_Pos   28           /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
-#define SERCOM_SPI_CTRLA_CPHA       (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos)
-#define SERCOM_SPI_CTRLA_CPOL_Pos   29           /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
-#define SERCOM_SPI_CTRLA_CPOL       (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos)
-#define SERCOM_SPI_CTRLA_DORD_Pos   30           /**< \brief (SERCOM_SPI_CTRLA) Data Order */
-#define SERCOM_SPI_CTRLA_DORD       (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos)
-#define SERCOM_SPI_CTRLA_MASK       _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
-
-/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:3;           /*!< bit:  2.. 4  Operating Mode                     */
-    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      7  Run during Standby                 */
-    uint32_t IBON:1;           /*!< bit:      8  Immediate Buffer Overflow Notification */
-    uint32_t TXINV:1;          /*!< bit:      9  Transmit Data Invert               */
-    uint32_t RXINV:1;          /*!< bit:     10  Receive Data Invert                */
-    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
-    uint32_t SAMPR:3;          /*!< bit: 13..15  Sample                             */
-    uint32_t TXPO:2;           /*!< bit: 16..17  Transmit Data Pinout               */
-    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
-    uint32_t RXPO:2;           /*!< bit: 20..21  Receive Data Pinout                */
-    uint32_t SAMPA:2;          /*!< bit: 22..23  Sample Adjustment                  */
-    uint32_t FORM:4;           /*!< bit: 24..27  Frame Format                       */
-    uint32_t CMODE:1;          /*!< bit:     28  Communication Mode                 */
-    uint32_t CPOL:1;           /*!< bit:     29  Clock Polarity                     */
-    uint32_t DORD:1;           /*!< bit:     30  Data Order                         */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_CTRLA_OFFSET   0x00         /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
-#define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
-
-#define SERCOM_USART_CTRLA_SWRST_Pos 0            /**< \brief (SERCOM_USART_CTRLA) Software Reset */
-#define SERCOM_USART_CTRLA_SWRST    (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos)
-#define SERCOM_USART_CTRLA_ENABLE_Pos 1            /**< \brief (SERCOM_USART_CTRLA) Enable */
-#define SERCOM_USART_CTRLA_ENABLE   (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos)
-#define SERCOM_USART_CTRLA_MODE_Pos 2            /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
-#define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos)
-#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
-#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7            /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
-#define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
-#define SERCOM_USART_CTRLA_IBON_Pos 8            /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
-#define SERCOM_USART_CTRLA_IBON     (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos)
-#define SERCOM_USART_CTRLA_TXINV_Pos 9            /**< \brief (SERCOM_USART_CTRLA) Transmit Data Invert */
-#define SERCOM_USART_CTRLA_TXINV    (_U_(0x1) << SERCOM_USART_CTRLA_TXINV_Pos)
-#define SERCOM_USART_CTRLA_RXINV_Pos 10           /**< \brief (SERCOM_USART_CTRLA) Receive Data Invert */
-#define SERCOM_USART_CTRLA_RXINV    (_U_(0x1) << SERCOM_USART_CTRLA_RXINV_Pos)
-#define SERCOM_USART_CTRLA_SAMPR_Pos 13           /**< \brief (SERCOM_USART_CTRLA) Sample */
-#define SERCOM_USART_CTRLA_SAMPR_Msk (_U_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos)
-#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
-#define SERCOM_USART_CTRLA_TXPO_Pos 16           /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
-#define SERCOM_USART_CTRLA_TXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos)
-#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
-#define SERCOM_USART_CTRLA_RXPO_Pos 20           /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
-#define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos)
-#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
-#define SERCOM_USART_CTRLA_SAMPA_Pos 22           /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
-#define SERCOM_USART_CTRLA_SAMPA_Msk (_U_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos)
-#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
-#define SERCOM_USART_CTRLA_FORM_Pos 24           /**< \brief (SERCOM_USART_CTRLA) Frame Format */
-#define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos)
-#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
-#define SERCOM_USART_CTRLA_CMODE_Pos 28           /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
-#define SERCOM_USART_CTRLA_CMODE    (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos)
-#define SERCOM_USART_CTRLA_CPOL_Pos 29           /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
-#define SERCOM_USART_CTRLA_CPOL     (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos)
-#define SERCOM_USART_CTRLA_DORD_Pos 30           /**< \brief (SERCOM_USART_CTRLA) Data Order */
-#define SERCOM_USART_CTRLA_DORD     (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos)
-#define SERCOM_USART_CTRLA_MASK     _U_(0x7FF3E79F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */
-
-/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
-    uint32_t QCEN:1;           /*!< bit:      9  Quick Command Enable               */
-    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
-    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
-    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
-    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
-#define SERCOM_I2CM_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
-
-#define SERCOM_I2CM_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
-#define SERCOM_I2CM_CTRLB_SMEN      (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)
-#define SERCOM_I2CM_CTRLB_QCEN_Pos  9            /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
-#define SERCOM_I2CM_CTRLB_QCEN      (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)
-#define SERCOM_I2CM_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CM_CTRLB) Command */
-#define SERCOM_I2CM_CTRLB_CMD_Msk   (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)
-#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
-#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
-#define SERCOM_I2CM_CTRLB_ACKACT    (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)
-#define SERCOM_I2CM_CTRLB_MASK      _U_(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
-
-/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t SMEN:1;           /*!< bit:      8  Smart Mode Enable                  */
-    uint32_t GCMD:1;           /*!< bit:      9  PMBus Group Command                */
-    uint32_t AACKEN:1;         /*!< bit:     10  Automatic Address Acknowledge      */
-    uint32_t :3;               /*!< bit: 11..13  Reserved                           */
-    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
-    uint32_t CMD:2;            /*!< bit: 16..17  Command                            */
-    uint32_t ACKACT:1;         /*!< bit:     18  Acknowledge Action                 */
-    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_CTRLB_OFFSET    0x04         /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
-#define SERCOM_I2CS_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
-
-#define SERCOM_I2CS_CTRLB_SMEN_Pos  8            /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
-#define SERCOM_I2CS_CTRLB_SMEN      (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)
-#define SERCOM_I2CS_CTRLB_GCMD_Pos  9            /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
-#define SERCOM_I2CS_CTRLB_GCMD      (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)
-#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10           /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
-#define SERCOM_I2CS_CTRLB_AACKEN    (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)
-#define SERCOM_I2CS_CTRLB_AMODE_Pos 14           /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
-#define SERCOM_I2CS_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)
-#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
-#define SERCOM_I2CS_CTRLB_CMD_Pos   16           /**< \brief (SERCOM_I2CS_CTRLB) Command */
-#define SERCOM_I2CS_CTRLB_CMD_Msk   (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)
-#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
-#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18           /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
-#define SERCOM_I2CS_CTRLB_ACKACT    (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)
-#define SERCOM_I2CS_CTRLB_MASK      _U_(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
-
-/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
-    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint32_t PLOADEN:1;        /*!< bit:      6  Data Preload Enable                */
-    uint32_t :2;               /*!< bit:  7.. 8  Reserved                           */
-    uint32_t SSDE:1;           /*!< bit:      9  Slave Select Low Detect Enable     */
-    uint32_t :3;               /*!< bit: 10..12  Reserved                           */
-    uint32_t MSSEN:1;          /*!< bit:     13  Master Slave Select Enable         */
-    uint32_t AMODE:2;          /*!< bit: 14..15  Address Mode                       */
-    uint32_t :1;               /*!< bit:     16  Reserved                           */
-    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
-    uint32_t :14;              /*!< bit: 18..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_CTRLB_OFFSET     0x04         /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
-#define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
-
-#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_SPI_CTRLB) Character Size */
-#define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos)
-#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
-#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6            /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
-#define SERCOM_SPI_CTRLB_PLOADEN    (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos)
-#define SERCOM_SPI_CTRLB_SSDE_Pos   9            /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
-#define SERCOM_SPI_CTRLB_SSDE       (_U_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos)
-#define SERCOM_SPI_CTRLB_MSSEN_Pos  13           /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
-#define SERCOM_SPI_CTRLB_MSSEN      (_U_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos)
-#define SERCOM_SPI_CTRLB_AMODE_Pos  14           /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
-#define SERCOM_SPI_CTRLB_AMODE_Msk  (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos)
-#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
-#define SERCOM_SPI_CTRLB_RXEN_Pos   17           /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
-#define SERCOM_SPI_CTRLB_RXEN       (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos)
-#define SERCOM_SPI_CTRLB_MASK       _U_(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
-
-/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CHSIZE:3;         /*!< bit:  0.. 2  Character Size                     */
-    uint32_t :3;               /*!< bit:  3.. 5  Reserved                           */
-    uint32_t SBMODE:1;         /*!< bit:      6  Stop Bit Mode                      */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t COLDEN:1;         /*!< bit:      8  Collision Detection Enable         */
-    uint32_t SFDE:1;           /*!< bit:      9  Start of Frame Detection Enable    */
-    uint32_t ENC:1;            /*!< bit:     10  Encoding Format                    */
-    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
-    uint32_t PMODE:1;          /*!< bit:     13  Parity Mode                        */
-    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
-    uint32_t TXEN:1;           /*!< bit:     16  Transmitter Enable                 */
-    uint32_t RXEN:1;           /*!< bit:     17  Receiver Enable                    */
-    uint32_t :6;               /*!< bit: 18..23  Reserved                           */
-    uint32_t LINCMD:2;         /*!< bit: 24..25  LIN Command                        */
-    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_CTRLB_OFFSET   0x04         /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
-#define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
-
-#define SERCOM_USART_CTRLB_CHSIZE_Pos 0            /**< \brief (SERCOM_USART_CTRLB) Character Size */
-#define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos)
-#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
-#define SERCOM_USART_CTRLB_SBMODE_Pos 6            /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
-#define SERCOM_USART_CTRLB_SBMODE   (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos)
-#define SERCOM_USART_CTRLB_COLDEN_Pos 8            /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
-#define SERCOM_USART_CTRLB_COLDEN   (_U_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos)
-#define SERCOM_USART_CTRLB_SFDE_Pos 9            /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
-#define SERCOM_USART_CTRLB_SFDE     (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos)
-#define SERCOM_USART_CTRLB_ENC_Pos  10           /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
-#define SERCOM_USART_CTRLB_ENC      (_U_(0x1) << SERCOM_USART_CTRLB_ENC_Pos)
-#define SERCOM_USART_CTRLB_PMODE_Pos 13           /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
-#define SERCOM_USART_CTRLB_PMODE    (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos)
-#define SERCOM_USART_CTRLB_TXEN_Pos 16           /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
-#define SERCOM_USART_CTRLB_TXEN     (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos)
-#define SERCOM_USART_CTRLB_RXEN_Pos 17           /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
-#define SERCOM_USART_CTRLB_RXEN     (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos)
-#define SERCOM_USART_CTRLB_LINCMD_Pos 24           /**< \brief (SERCOM_USART_CTRLB) LIN Command */
-#define SERCOM_USART_CTRLB_LINCMD_Msk (_U_(0x3) << SERCOM_USART_CTRLB_LINCMD_Pos)
-#define SERCOM_USART_CTRLB_LINCMD(value) (SERCOM_USART_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_CTRLB_LINCMD_Pos))
-#define SERCOM_USART_CTRLB_MASK     _U_(0x03032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */
-
-/* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM I2CM Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
-    uint32_t DATA32B:1;        /*!< bit:     24  Data 32 Bit                        */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_CTRLC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_CTRLC_OFFSET    0x08         /**< \brief (SERCOM_I2CM_CTRLC offset) I2CM Control C */
-#define SERCOM_I2CM_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLC reset_value) I2CM Control C */
-
-#define SERCOM_I2CM_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_I2CM_CTRLC) Data 32 Bit */
-#define SERCOM_I2CM_CTRLC_DATA32B   (_U_(0x1) << SERCOM_I2CM_CTRLC_DATA32B_Pos)
-#define SERCOM_I2CM_CTRLC_MASK      _U_(0x01000000) /**< \brief (SERCOM_I2CM_CTRLC) MASK Register */
-
-/* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS I2CS Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SDASETUP:4;       /*!< bit:  0.. 3  SDA Setup Time                     */
-    uint32_t :20;              /*!< bit:  4..23  Reserved                           */
-    uint32_t DATA32B:1;        /*!< bit:     24  Data 32 Bit                        */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_CTRLC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_CTRLC_OFFSET    0x08         /**< \brief (SERCOM_I2CS_CTRLC offset) I2CS Control C */
-#define SERCOM_I2CS_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLC reset_value) I2CS Control C */
-
-#define SERCOM_I2CS_CTRLC_SDASETUP_Pos 0            /**< \brief (SERCOM_I2CS_CTRLC) SDA Setup Time */
-#define SERCOM_I2CS_CTRLC_SDASETUP_Msk (_U_(0xF) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)
-#define SERCOM_I2CS_CTRLC_SDASETUP(value) (SERCOM_I2CS_CTRLC_SDASETUP_Msk & ((value) << SERCOM_I2CS_CTRLC_SDASETUP_Pos))
-#define SERCOM_I2CS_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_I2CS_CTRLC) Data 32 Bit */
-#define SERCOM_I2CS_CTRLC_DATA32B   (_U_(0x1) << SERCOM_I2CS_CTRLC_DATA32B_Pos)
-#define SERCOM_I2CS_CTRLC_MASK      _U_(0x0100000F) /**< \brief (SERCOM_I2CS_CTRLC) MASK Register */
-
-/* -------- SERCOM_SPI_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPI SPI Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ICSPACE:6;        /*!< bit:  0.. 5  Inter-Character Spacing            */
-    uint32_t :18;              /*!< bit:  6..23  Reserved                           */
-    uint32_t DATA32B:1;        /*!< bit:     24  Data 32 Bit                        */
-    uint32_t :7;               /*!< bit: 25..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_CTRLC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_CTRLC_OFFSET     0x08         /**< \brief (SERCOM_SPI_CTRLC offset) SPI Control C */
-#define SERCOM_SPI_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLC reset_value) SPI Control C */
-
-#define SERCOM_SPI_CTRLC_ICSPACE_Pos 0            /**< \brief (SERCOM_SPI_CTRLC) Inter-Character Spacing */
-#define SERCOM_SPI_CTRLC_ICSPACE_Msk (_U_(0x3F) << SERCOM_SPI_CTRLC_ICSPACE_Pos)
-#define SERCOM_SPI_CTRLC_ICSPACE(value) (SERCOM_SPI_CTRLC_ICSPACE_Msk & ((value) << SERCOM_SPI_CTRLC_ICSPACE_Pos))
-#define SERCOM_SPI_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_SPI_CTRLC) Data 32 Bit */
-#define SERCOM_SPI_CTRLC_DATA32B    (_U_(0x1) << SERCOM_SPI_CTRLC_DATA32B_Pos)
-#define SERCOM_SPI_CTRLC_MASK       _U_(0x0100003F) /**< \brief (SERCOM_SPI_CTRLC) MASK Register */
-
-/* -------- SERCOM_USART_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART USART Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t GTIME:3;          /*!< bit:  0.. 2  Guard Time                         */
-    uint32_t :5;               /*!< bit:  3.. 7  Reserved                           */
-    uint32_t BRKLEN:2;         /*!< bit:  8.. 9  LIN Master Break Length            */
-    uint32_t HDRDLY:2;         /*!< bit: 10..11  LIN Master Header Delay            */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t INACK:1;          /*!< bit:     16  Inhibit Not Acknowledge            */
-    uint32_t DSNACK:1;         /*!< bit:     17  Disable Successive NACK            */
-    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
-    uint32_t MAXITER:3;        /*!< bit: 20..22  Maximum Iterations                 */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t DATA32B:2;        /*!< bit: 24..25  Data 32 Bit                        */
-    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_CTRLC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_CTRLC_OFFSET   0x08         /**< \brief (SERCOM_USART_CTRLC offset) USART Control C */
-#define SERCOM_USART_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLC reset_value) USART Control C */
-
-#define SERCOM_USART_CTRLC_GTIME_Pos 0            /**< \brief (SERCOM_USART_CTRLC) Guard Time */
-#define SERCOM_USART_CTRLC_GTIME_Msk (_U_(0x7) << SERCOM_USART_CTRLC_GTIME_Pos)
-#define SERCOM_USART_CTRLC_GTIME(value) (SERCOM_USART_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_CTRLC_GTIME_Pos))
-#define SERCOM_USART_CTRLC_BRKLEN_Pos 8            /**< \brief (SERCOM_USART_CTRLC) LIN Master Break Length */
-#define SERCOM_USART_CTRLC_BRKLEN_Msk (_U_(0x3) << SERCOM_USART_CTRLC_BRKLEN_Pos)
-#define SERCOM_USART_CTRLC_BRKLEN(value) (SERCOM_USART_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_CTRLC_BRKLEN_Pos))
-#define SERCOM_USART_CTRLC_HDRDLY_Pos 10           /**< \brief (SERCOM_USART_CTRLC) LIN Master Header Delay */
-#define SERCOM_USART_CTRLC_HDRDLY_Msk (_U_(0x3) << SERCOM_USART_CTRLC_HDRDLY_Pos)
-#define SERCOM_USART_CTRLC_HDRDLY(value) (SERCOM_USART_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_CTRLC_HDRDLY_Pos))
-#define SERCOM_USART_CTRLC_INACK_Pos 16           /**< \brief (SERCOM_USART_CTRLC) Inhibit Not Acknowledge */
-#define SERCOM_USART_CTRLC_INACK    (_U_(0x1) << SERCOM_USART_CTRLC_INACK_Pos)
-#define SERCOM_USART_CTRLC_DSNACK_Pos 17           /**< \brief (SERCOM_USART_CTRLC) Disable Successive NACK */
-#define SERCOM_USART_CTRLC_DSNACK   (_U_(0x1) << SERCOM_USART_CTRLC_DSNACK_Pos)
-#define SERCOM_USART_CTRLC_MAXITER_Pos 20           /**< \brief (SERCOM_USART_CTRLC) Maximum Iterations */
-#define SERCOM_USART_CTRLC_MAXITER_Msk (_U_(0x7) << SERCOM_USART_CTRLC_MAXITER_Pos)
-#define SERCOM_USART_CTRLC_MAXITER(value) (SERCOM_USART_CTRLC_MAXITER_Msk & ((value) << SERCOM_USART_CTRLC_MAXITER_Pos))
-#define SERCOM_USART_CTRLC_DATA32B_Pos 24           /**< \brief (SERCOM_USART_CTRLC) Data 32 Bit */
-#define SERCOM_USART_CTRLC_DATA32B_Msk (_U_(0x3) << SERCOM_USART_CTRLC_DATA32B_Pos)
-#define SERCOM_USART_CTRLC_DATA32B(value) (SERCOM_USART_CTRLC_DATA32B_Msk & ((value) << SERCOM_USART_CTRLC_DATA32B_Pos))
-#define SERCOM_USART_CTRLC_MASK     _U_(0x03730F07) /**< \brief (SERCOM_USART_CTRLC) MASK Register */
-
-/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
-    uint32_t BAUDLOW:8;        /*!< bit:  8..15  Baud Rate Value Low                */
-    uint32_t HSBAUD:8;         /*!< bit: 16..23  High Speed Baud Rate Value         */
-    uint32_t HSBAUDLOW:8;      /*!< bit: 24..31  High Speed Baud Rate Value Low     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_BAUD_OFFSET     0x0C         /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
-#define SERCOM_I2CM_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
-
-#define SERCOM_I2CM_BAUD_BAUD_Pos   0            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
-#define SERCOM_I2CM_BAUD_BAUD_Msk   (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)
-#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
-#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8            /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
-#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
-#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
-#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
-#define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)
-#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
-#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24           /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
-#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
-#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
-#define SERCOM_I2CM_BAUD_MASK       _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
-
-/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W  8) SPI SPI Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  BAUD:8;           /*!< bit:  0.. 7  Baud Rate Value                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_BAUD_OFFSET      0x0C         /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
-#define SERCOM_SPI_BAUD_RESETVALUE  _U_(0x00)    /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
-
-#define SERCOM_SPI_BAUD_BAUD_Pos    0            /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
-#define SERCOM_SPI_BAUD_BAUD_Msk    (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos)
-#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
-#define SERCOM_SPI_BAUD_MASK        _U_(0xFF)    /**< \brief (SERCOM_SPI_BAUD) MASK Register */
-
-/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct { // FRAC mode
-    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
-    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
-  } FRAC;                      /*!< Structure used for FRAC                         */
-  struct { // FRACFP mode
-    uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
-    uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
-  } FRACFP;                    /*!< Structure used for FRACFP                       */
-  struct { // USARTFP mode
-    uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
-  } USARTFP;                   /*!< Structure used for USARTFP                      */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_BAUD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_BAUD_OFFSET    0x0C         /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
-#define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
-
-#define SERCOM_USART_BAUD_BAUD_Pos  0            /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
-#define SERCOM_USART_BAUD_BAUD_Msk  (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos)
-#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
-#define SERCOM_USART_BAUD_MASK      _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD) MASK Register */
-
-// FRAC mode
-#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
-#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
-#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
-#define SERCOM_USART_BAUD_FRAC_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
-#define SERCOM_USART_BAUD_FRAC_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos)
-#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
-#define SERCOM_USART_BAUD_FRAC_MASK _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
-
-// FRACFP mode
-#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
-#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
-#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
-#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13           /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
-#define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos)
-#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
-#define SERCOM_USART_BAUD_FRACFP_MASK _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
-
-// USARTFP mode
-#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
-#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
-#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
-#define SERCOM_USART_BAUD_USARTFP_MASK _U_(0xFFFF)  /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
-
-/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W  8) USART USART Receive Pulse Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  RXPL:8;           /*!< bit:  0.. 7  Receive Pulse Length               */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_RXPL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_RXPL_OFFSET    0x0E         /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
-#define SERCOM_USART_RXPL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
-
-#define SERCOM_USART_RXPL_RXPL_Pos  0            /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
-#define SERCOM_USART_RXPL_RXPL_Msk  (_U_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos)
-#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
-#define SERCOM_USART_RXPL_MASK      _U_(0xFF)    /**< \brief (SERCOM_USART_RXPL) MASK Register */
-
-/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CM I2CM Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Disable    */
-    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Disable     */
-    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CM_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
-#define SERCOM_I2CM_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
-
-#define SERCOM_I2CM_INTENCLR_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
-#define SERCOM_I2CM_INTENCLR_MB     (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)
-#define SERCOM_I2CM_INTENCLR_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
-#define SERCOM_I2CM_INTENCLR_SB     (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)
-#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_I2CM_INTENCLR_ERROR  (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)
-#define SERCOM_I2CM_INTENCLR_MASK   _U_(0x83)    /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
-
-/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) I2CS I2CS Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Disable    */
-    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Disable    */
-    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Disable             */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CS_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
-#define SERCOM_I2CS_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
-
-#define SERCOM_I2CS_INTENCLR_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_PREC   (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)
-#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
-#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_DRDY   (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)
-#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_I2CS_INTENCLR_ERROR  (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)
-#define SERCOM_I2CS_INTENCLR_MASK   _U_(0x87)    /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
-
-/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) SPI SPI Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
-    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
-    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
-    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Disable */
-    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_INTENCLR_OFFSET  0x14         /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
-#define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
-
-#define SERCOM_SPI_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_DRE     (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos)
-#define SERCOM_SPI_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_TXC     (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos)
-#define SERCOM_SPI_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_RXC     (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos)
-#define SERCOM_SPI_INTENCLR_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_SSL     (_U_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos)
-#define SERCOM_SPI_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_SPI_INTENCLR_ERROR   (_U_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos)
-#define SERCOM_SPI_INTENCLR_MASK    _U_(0x8F)    /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
-
-/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W  8) USART USART Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Disable */
-    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Disable */
-    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Disable */
-    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Disable    */
-    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Disable */
-    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Disable   */
-    uint8_t  :1;               /*!< bit:      6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Disable   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_INTENCLR_OFFSET 0x14         /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
-#define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
-
-#define SERCOM_USART_INTENCLR_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
-#define SERCOM_USART_INTENCLR_DRE   (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos)
-#define SERCOM_USART_INTENCLR_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
-#define SERCOM_USART_INTENCLR_TXC   (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos)
-#define SERCOM_USART_INTENCLR_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
-#define SERCOM_USART_INTENCLR_RXC   (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos)
-#define SERCOM_USART_INTENCLR_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
-#define SERCOM_USART_INTENCLR_RXS   (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos)
-#define SERCOM_USART_INTENCLR_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
-#define SERCOM_USART_INTENCLR_CTSIC (_U_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos)
-#define SERCOM_USART_INTENCLR_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
-#define SERCOM_USART_INTENCLR_RXBRK (_U_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos)
-#define SERCOM_USART_INTENCLR_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
-#define SERCOM_USART_INTENCLR_ERROR (_U_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos)
-#define SERCOM_USART_INTENCLR_MASK  _U_(0xBF)    /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
-
-/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CM I2CM Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt Enable     */
-    uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt Enable      */
-    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CM_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
-#define SERCOM_I2CM_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
-
-#define SERCOM_I2CM_INTENSET_MB_Pos 0            /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
-#define SERCOM_I2CM_INTENSET_MB     (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)
-#define SERCOM_I2CM_INTENSET_SB_Pos 1            /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
-#define SERCOM_I2CM_INTENSET_SB     (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)
-#define SERCOM_I2CM_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_I2CM_INTENSET_ERROR  (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)
-#define SERCOM_I2CM_INTENSET_MASK   _U_(0x83)    /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
-
-/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W  8) I2CS I2CS Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt Enable     */
-    uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt Enable     */
-    uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt Enable              */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CS_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
-#define SERCOM_I2CS_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
-
-#define SERCOM_I2CS_INTENSET_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_PREC   (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)
-#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)
-#define SERCOM_I2CS_INTENSET_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_DRDY   (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)
-#define SERCOM_I2CS_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_I2CS_INTENSET_ERROR  (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)
-#define SERCOM_I2CS_INTENSET_MASK   _U_(0x87)    /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
-
-/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W  8) SPI SPI Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
-    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
-    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
-    uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Enable  */
-    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_INTENSET_OFFSET  0x16         /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
-#define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
-
-#define SERCOM_SPI_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
-#define SERCOM_SPI_INTENSET_DRE     (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos)
-#define SERCOM_SPI_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
-#define SERCOM_SPI_INTENSET_TXC     (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos)
-#define SERCOM_SPI_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
-#define SERCOM_SPI_INTENSET_RXC     (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos)
-#define SERCOM_SPI_INTENSET_SSL_Pos 3            /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
-#define SERCOM_SPI_INTENSET_SSL     (_U_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos)
-#define SERCOM_SPI_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_SPI_INTENSET_ERROR   (_U_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos)
-#define SERCOM_SPI_INTENSET_MASK    _U_(0x8F)    /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
-
-/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W  8) USART USART Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt Enable */
-    uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt Enable */
-    uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt Enable  */
-    uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt Enable     */
-    uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt Enable */
-    uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt Enable    */
-    uint8_t  :1;               /*!< bit:      6  Reserved                           */
-    uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt Enable    */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_INTENSET_OFFSET 0x16         /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
-#define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
-
-#define SERCOM_USART_INTENSET_DRE_Pos 0            /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
-#define SERCOM_USART_INTENSET_DRE   (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos)
-#define SERCOM_USART_INTENSET_TXC_Pos 1            /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
-#define SERCOM_USART_INTENSET_TXC   (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos)
-#define SERCOM_USART_INTENSET_RXC_Pos 2            /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
-#define SERCOM_USART_INTENSET_RXC   (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos)
-#define SERCOM_USART_INTENSET_RXS_Pos 3            /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
-#define SERCOM_USART_INTENSET_RXS   (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos)
-#define SERCOM_USART_INTENSET_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
-#define SERCOM_USART_INTENSET_CTSIC (_U_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos)
-#define SERCOM_USART_INTENSET_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
-#define SERCOM_USART_INTENSET_RXBRK (_U_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos)
-#define SERCOM_USART_INTENSET_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
-#define SERCOM_USART_INTENSET_ERROR (_U_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos)
-#define SERCOM_USART_INTENSET_MASK  _U_(0xBF)    /**< \brief (SERCOM_USART_INTENSET) MASK Register */
-
-/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CM I2CM Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt            */
-    __I uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt             */
-    __I uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
-    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CM_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
-#define SERCOM_I2CM_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
-
-#define SERCOM_I2CM_INTFLAG_MB_Pos  0            /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
-#define SERCOM_I2CM_INTFLAG_MB      (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)
-#define SERCOM_I2CM_INTFLAG_SB_Pos  1            /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
-#define SERCOM_I2CM_INTFLAG_SB      (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)
-#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
-#define SERCOM_I2CM_INTFLAG_ERROR   (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)
-#define SERCOM_I2CM_INTFLAG_MASK    _U_(0x83)    /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
-
-/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CS I2CS Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt            */
-    __I uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt            */
-    __I uint8_t  DRDY:1;           /*!< bit:      2  Data Interrupt                     */
-    __I uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CS_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_INTFLAG_OFFSET  0x18         /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
-#define SERCOM_I2CS_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
-
-#define SERCOM_I2CS_INTFLAG_PREC_Pos 0            /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
-#define SERCOM_I2CS_INTFLAG_PREC    (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)
-#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1            /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
-#define SERCOM_I2CS_INTFLAG_AMATCH  (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
-#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2            /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
-#define SERCOM_I2CS_INTFLAG_DRDY    (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)
-#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
-#define SERCOM_I2CS_INTFLAG_ERROR   (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)
-#define SERCOM_I2CS_INTFLAG_MASK    _U_(0x87)    /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
-
-/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) SPI SPI Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
-    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
-    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
-    __I uint8_t  SSL:1;            /*!< bit:      3  Slave Select Low Interrupt Flag    */
-    __I uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_INTFLAG_OFFSET   0x18         /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
-#define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
-
-#define SERCOM_SPI_INTFLAG_DRE_Pos  0            /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
-#define SERCOM_SPI_INTFLAG_DRE      (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos)
-#define SERCOM_SPI_INTFLAG_TXC_Pos  1            /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
-#define SERCOM_SPI_INTFLAG_TXC      (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos)
-#define SERCOM_SPI_INTFLAG_RXC_Pos  2            /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
-#define SERCOM_SPI_INTFLAG_RXC      (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos)
-#define SERCOM_SPI_INTFLAG_SSL_Pos  3            /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
-#define SERCOM_SPI_INTFLAG_SSL      (_U_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos)
-#define SERCOM_SPI_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
-#define SERCOM_SPI_INTFLAG_ERROR    (_U_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos)
-#define SERCOM_SPI_INTFLAG_MASK     _U_(0x8F)    /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
-
-/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) USART USART Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
-    __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
-    __I uint8_t  RXC:1;            /*!< bit:      2  Receive Complete Interrupt         */
-    __I uint8_t  RXS:1;            /*!< bit:      3  Receive Start Interrupt            */
-    __I uint8_t  CTSIC:1;          /*!< bit:      4  Clear To Send Input Change Interrupt */
-    __I uint8_t  RXBRK:1;          /*!< bit:      5  Break Received Interrupt           */
-    __I uint8_t  :1;               /*!< bit:      6  Reserved                           */
-    __I uint8_t  ERROR:1;          /*!< bit:      7  Combined Error Interrupt           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_INTFLAG_OFFSET 0x18         /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
-#define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
-
-#define SERCOM_USART_INTFLAG_DRE_Pos 0            /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
-#define SERCOM_USART_INTFLAG_DRE    (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos)
-#define SERCOM_USART_INTFLAG_TXC_Pos 1            /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
-#define SERCOM_USART_INTFLAG_TXC    (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos)
-#define SERCOM_USART_INTFLAG_RXC_Pos 2            /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
-#define SERCOM_USART_INTFLAG_RXC    (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos)
-#define SERCOM_USART_INTFLAG_RXS_Pos 3            /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
-#define SERCOM_USART_INTFLAG_RXS    (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos)
-#define SERCOM_USART_INTFLAG_CTSIC_Pos 4            /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
-#define SERCOM_USART_INTFLAG_CTSIC  (_U_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos)
-#define SERCOM_USART_INTFLAG_RXBRK_Pos 5            /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
-#define SERCOM_USART_INTFLAG_RXBRK  (_U_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos)
-#define SERCOM_USART_INTFLAG_ERROR_Pos 7            /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
-#define SERCOM_USART_INTFLAG_ERROR  (_U_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos)
-#define SERCOM_USART_INTFLAG_MASK   _U_(0xBF)    /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
-
-/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
-    uint16_t ARBLOST:1;        /*!< bit:      1  Arbitration Lost                   */
-    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
-    uint16_t :1;               /*!< bit:      3  Reserved                           */
-    uint16_t BUSSTATE:2;       /*!< bit:  4.. 5  Bus State                          */
-    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
-    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
-    uint16_t MEXTTOUT:1;       /*!< bit:      8  Master SCL Low Extend Timeout      */
-    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
-    uint16_t LENERR:1;         /*!< bit:     10  Length Error                       */
-    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
-#define SERCOM_I2CM_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
-
-#define SERCOM_I2CM_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
-#define SERCOM_I2CM_STATUS_BUSERR   (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)
-#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1            /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
-#define SERCOM_I2CM_STATUS_ARBLOST  (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)
-#define SERCOM_I2CM_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
-#define SERCOM_I2CM_STATUS_RXNACK   (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)
-#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4            /**< \brief (SERCOM_I2CM_STATUS) Bus State */
-#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
-#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
-#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
-#define SERCOM_I2CM_STATUS_LOWTOUT  (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
-#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
-#define SERCOM_I2CM_STATUS_CLKHOLD  (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
-#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8            /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
-#define SERCOM_I2CM_STATUS_MEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
-#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CM_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
-#define SERCOM_I2CM_STATUS_LENERR_Pos 10           /**< \brief (SERCOM_I2CM_STATUS) Length Error */
-#define SERCOM_I2CM_STATUS_LENERR   (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)
-#define SERCOM_I2CM_STATUS_MASK     _U_(0x07F7)  /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
-
-/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BUSERR:1;         /*!< bit:      0  Bus Error                          */
-    uint16_t COLL:1;           /*!< bit:      1  Transmit Collision                 */
-    uint16_t RXNACK:1;         /*!< bit:      2  Received Not Acknowledge           */
-    uint16_t DIR:1;            /*!< bit:      3  Read/Write Direction               */
-    uint16_t SR:1;             /*!< bit:      4  Repeated Start                     */
-    uint16_t :1;               /*!< bit:      5  Reserved                           */
-    uint16_t LOWTOUT:1;        /*!< bit:      6  SCL Low Timeout                    */
-    uint16_t CLKHOLD:1;        /*!< bit:      7  Clock Hold                         */
-    uint16_t :1;               /*!< bit:      8  Reserved                           */
-    uint16_t SEXTTOUT:1;       /*!< bit:      9  Slave SCL Low Extend Timeout       */
-    uint16_t HS:1;             /*!< bit:     10  High Speed                         */
-    uint16_t LENERR:1;         /*!< bit:     11  Transaction Length Error           */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_STATUS_OFFSET   0x1A         /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
-#define SERCOM_I2CS_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
-
-#define SERCOM_I2CS_STATUS_BUSERR_Pos 0            /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
-#define SERCOM_I2CS_STATUS_BUSERR   (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)
-#define SERCOM_I2CS_STATUS_COLL_Pos 1            /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
-#define SERCOM_I2CS_STATUS_COLL     (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)
-#define SERCOM_I2CS_STATUS_RXNACK_Pos 2            /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
-#define SERCOM_I2CS_STATUS_RXNACK   (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)
-#define SERCOM_I2CS_STATUS_DIR_Pos  3            /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
-#define SERCOM_I2CS_STATUS_DIR      (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)
-#define SERCOM_I2CS_STATUS_SR_Pos   4            /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
-#define SERCOM_I2CS_STATUS_SR       (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)
-#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6            /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
-#define SERCOM_I2CS_STATUS_LOWTOUT  (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
-#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7            /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
-#define SERCOM_I2CS_STATUS_CLKHOLD  (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
-#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9            /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
-#define SERCOM_I2CS_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
-#define SERCOM_I2CS_STATUS_HS_Pos   10           /**< \brief (SERCOM_I2CS_STATUS) High Speed */
-#define SERCOM_I2CS_STATUS_HS       (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)
-#define SERCOM_I2CS_STATUS_LENERR_Pos 11           /**< \brief (SERCOM_I2CS_STATUS) Transaction Length Error */
-#define SERCOM_I2CS_STATUS_LENERR   (_U_(0x1) << SERCOM_I2CS_STATUS_LENERR_Pos)
-#define SERCOM_I2CS_STATUS_MASK     _U_(0x0EDF)  /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
-
-/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
-    uint16_t :8;               /*!< bit:  3..10  Reserved                           */
-    uint16_t LENERR:1;         /*!< bit:     11  Transaction Length Error           */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_STATUS_OFFSET    0x1A         /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
-#define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
-
-#define SERCOM_SPI_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
-#define SERCOM_SPI_STATUS_BUFOVF    (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos)
-#define SERCOM_SPI_STATUS_LENERR_Pos 11           /**< \brief (SERCOM_SPI_STATUS) Transaction Length Error */
-#define SERCOM_SPI_STATUS_LENERR    (_U_(0x1) << SERCOM_SPI_STATUS_LENERR_Pos)
-#define SERCOM_SPI_STATUS_MASK      _U_(0x0804)  /**< \brief (SERCOM_SPI_STATUS) MASK Register */
-
-/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PERR:1;           /*!< bit:      0  Parity Error                       */
-    uint16_t FERR:1;           /*!< bit:      1  Frame Error                        */
-    uint16_t BUFOVF:1;         /*!< bit:      2  Buffer Overflow                    */
-    uint16_t CTS:1;            /*!< bit:      3  Clear To Send                      */
-    uint16_t ISF:1;            /*!< bit:      4  Inconsistent Sync Field            */
-    uint16_t COLL:1;           /*!< bit:      5  Collision Detected                 */
-    uint16_t TXE:1;            /*!< bit:      6  Transmitter Empty                  */
-    uint16_t ITER:1;           /*!< bit:      7  Maximum Number of Repetitions Reached */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_STATUS_OFFSET  0x1A         /**< \brief (SERCOM_USART_STATUS offset) USART Status */
-#define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
-
-#define SERCOM_USART_STATUS_PERR_Pos 0            /**< \brief (SERCOM_USART_STATUS) Parity Error */
-#define SERCOM_USART_STATUS_PERR    (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos)
-#define SERCOM_USART_STATUS_FERR_Pos 1            /**< \brief (SERCOM_USART_STATUS) Frame Error */
-#define SERCOM_USART_STATUS_FERR    (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos)
-#define SERCOM_USART_STATUS_BUFOVF_Pos 2            /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
-#define SERCOM_USART_STATUS_BUFOVF  (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos)
-#define SERCOM_USART_STATUS_CTS_Pos 3            /**< \brief (SERCOM_USART_STATUS) Clear To Send */
-#define SERCOM_USART_STATUS_CTS     (_U_(0x1) << SERCOM_USART_STATUS_CTS_Pos)
-#define SERCOM_USART_STATUS_ISF_Pos 4            /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
-#define SERCOM_USART_STATUS_ISF     (_U_(0x1) << SERCOM_USART_STATUS_ISF_Pos)
-#define SERCOM_USART_STATUS_COLL_Pos 5            /**< \brief (SERCOM_USART_STATUS) Collision Detected */
-#define SERCOM_USART_STATUS_COLL    (_U_(0x1) << SERCOM_USART_STATUS_COLL_Pos)
-#define SERCOM_USART_STATUS_TXE_Pos 6            /**< \brief (SERCOM_USART_STATUS) Transmitter Empty */
-#define SERCOM_USART_STATUS_TXE     (_U_(0x1) << SERCOM_USART_STATUS_TXE_Pos)
-#define SERCOM_USART_STATUS_ITER_Pos 7            /**< \brief (SERCOM_USART_STATUS) Maximum Number of Repetitions Reached */
-#define SERCOM_USART_STATUS_ITER    (_U_(0x1) << SERCOM_USART_STATUS_ITER_Pos)
-#define SERCOM_USART_STATUS_MASK    _U_(0x00FF)  /**< \brief (SERCOM_USART_STATUS) MASK Register */
-
-/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CM I2CM Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
-    uint32_t SYSOP:1;          /*!< bit:      2  System Operation Synchronization Busy */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t LENGTH:1;         /*!< bit:      4  Length Synchronization Busy        */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
-
-#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_SWRST  (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
-#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2            /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_SYSOP  (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
-#define SERCOM_I2CM_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy */
-#define SERCOM_I2CM_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos)
-#define SERCOM_I2CM_SYNCBUSY_MASK   _U_(0x00000017) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) I2CS I2CS Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
-    uint32_t :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint32_t LENGTH:1;         /*!< bit:      4  Length Synchronization Busy        */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
-
-#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_SWRST  (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
-#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_I2CS_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy */
-#define SERCOM_I2CS_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)
-#define SERCOM_I2CS_SYNCBUSY_MASK   _U_(0x00000013) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) SPI SPI Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
-    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t LENGTH:1;         /*!< bit:      4  LENGTH Synchronization Busy        */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_SYNCBUSY_OFFSET  0x1C         /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
-
-#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_SWRST   (_U_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
-#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_ENABLE  (_U_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_CTRLB   (_U_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
-#define SERCOM_SPI_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_SPI_SYNCBUSY) LENGTH Synchronization Busy */
-#define SERCOM_SPI_SYNCBUSY_LENGTH  (_U_(0x1) << SERCOM_SPI_SYNCBUSY_LENGTH_Pos)
-#define SERCOM_SPI_SYNCBUSY_MASK    _U_(0x00000017) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/  32) USART USART Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint32_t ENABLE:1;         /*!< bit:      1  SERCOM Enable Synchronization Busy */
-    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB Synchronization Busy         */
-    uint32_t RXERRCNT:1;       /*!< bit:      3  RXERRCNT Synchronization Busy      */
-    uint32_t LENGTH:1;         /*!< bit:      4  LENGTH Synchronization Busy        */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C         /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
-
-#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0            /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos)
-#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1            /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
-#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2            /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
-#define SERCOM_USART_SYNCBUSY_RXERRCNT_Pos 3            /**< \brief (SERCOM_USART_SYNCBUSY) RXERRCNT Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_RXERRCNT (_U_(0x1) << SERCOM_USART_SYNCBUSY_RXERRCNT_Pos)
-#define SERCOM_USART_SYNCBUSY_LENGTH_Pos 4            /**< \brief (SERCOM_USART_SYNCBUSY) LENGTH Synchronization Busy */
-#define SERCOM_USART_SYNCBUSY_LENGTH (_U_(0x1) << SERCOM_USART_SYNCBUSY_LENGTH_Pos)
-#define SERCOM_USART_SYNCBUSY_MASK  _U_(0x0000001F) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
-
-/* -------- SERCOM_USART_RXERRCNT : (SERCOM Offset: 0x20) (R/   8) USART USART Receive Error Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_RXERRCNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_RXERRCNT_OFFSET 0x20         /**< \brief (SERCOM_USART_RXERRCNT offset) USART Receive Error Count */
-#define SERCOM_USART_RXERRCNT_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_RXERRCNT reset_value) USART Receive Error Count */
-#define SERCOM_USART_RXERRCNT_MASK  _U_(0xFF)    /**< \brief (SERCOM_USART_RXERRCNT) MASK Register */
-
-/* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS I2CS Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t LEN:8;            /*!< bit:  0.. 7  Data Length                        */
-    uint16_t LENEN:1;          /*!< bit:      8  Data Length Enable                 */
-    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_LENGTH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_LENGTH_OFFSET   0x22         /**< \brief (SERCOM_I2CS_LENGTH offset) I2CS Length */
-#define SERCOM_I2CS_LENGTH_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_I2CS_LENGTH reset_value) I2CS Length */
-
-#define SERCOM_I2CS_LENGTH_LEN_Pos  0            /**< \brief (SERCOM_I2CS_LENGTH) Data Length */
-#define SERCOM_I2CS_LENGTH_LEN_Msk  (_U_(0xFF) << SERCOM_I2CS_LENGTH_LEN_Pos)
-#define SERCOM_I2CS_LENGTH_LEN(value) (SERCOM_I2CS_LENGTH_LEN_Msk & ((value) << SERCOM_I2CS_LENGTH_LEN_Pos))
-#define SERCOM_I2CS_LENGTH_LENEN_Pos 8            /**< \brief (SERCOM_I2CS_LENGTH) Data Length Enable */
-#define SERCOM_I2CS_LENGTH_LENEN    (_U_(0x1) << SERCOM_I2CS_LENGTH_LENEN_Pos)
-#define SERCOM_I2CS_LENGTH_MASK     _U_(0x01FF)  /**< \brief (SERCOM_I2CS_LENGTH) MASK Register */
-
-/* -------- SERCOM_SPI_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPI SPI Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t LEN:8;            /*!< bit:  0.. 7  Data Length                        */
-    uint16_t LENEN:1;          /*!< bit:      8  Data Length Enable                 */
-    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_LENGTH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_LENGTH_OFFSET    0x22         /**< \brief (SERCOM_SPI_LENGTH offset) SPI Length */
-#define SERCOM_SPI_LENGTH_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_SPI_LENGTH reset_value) SPI Length */
-
-#define SERCOM_SPI_LENGTH_LEN_Pos   0            /**< \brief (SERCOM_SPI_LENGTH) Data Length */
-#define SERCOM_SPI_LENGTH_LEN_Msk   (_U_(0xFF) << SERCOM_SPI_LENGTH_LEN_Pos)
-#define SERCOM_SPI_LENGTH_LEN(value) (SERCOM_SPI_LENGTH_LEN_Msk & ((value) << SERCOM_SPI_LENGTH_LEN_Pos))
-#define SERCOM_SPI_LENGTH_LENEN_Pos 8            /**< \brief (SERCOM_SPI_LENGTH) Data Length Enable */
-#define SERCOM_SPI_LENGTH_LENEN     (_U_(0x1) << SERCOM_SPI_LENGTH_LENEN_Pos)
-#define SERCOM_SPI_LENGTH_MASK      _U_(0x01FF)  /**< \brief (SERCOM_SPI_LENGTH) MASK Register */
-
-/* -------- SERCOM_USART_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART USART Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t LEN:8;            /*!< bit:  0.. 7  Data Length                        */
-    uint16_t LENEN:2;          /*!< bit:  8.. 9  Data Length Enable                 */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_LENGTH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_LENGTH_OFFSET  0x22         /**< \brief (SERCOM_USART_LENGTH offset) USART Length */
-#define SERCOM_USART_LENGTH_RESETVALUE _U_(0x0000)  /**< \brief (SERCOM_USART_LENGTH reset_value) USART Length */
-
-#define SERCOM_USART_LENGTH_LEN_Pos 0            /**< \brief (SERCOM_USART_LENGTH) Data Length */
-#define SERCOM_USART_LENGTH_LEN_Msk (_U_(0xFF) << SERCOM_USART_LENGTH_LEN_Pos)
-#define SERCOM_USART_LENGTH_LEN(value) (SERCOM_USART_LENGTH_LEN_Msk & ((value) << SERCOM_USART_LENGTH_LEN_Pos))
-#define SERCOM_USART_LENGTH_LENEN_Pos 8            /**< \brief (SERCOM_USART_LENGTH) Data Length Enable */
-#define SERCOM_USART_LENGTH_LENEN_Msk (_U_(0x3) << SERCOM_USART_LENGTH_LENEN_Pos)
-#define SERCOM_USART_LENGTH_LENEN(value) (SERCOM_USART_LENGTH_LENEN_Msk & ((value) << SERCOM_USART_LENGTH_LENEN_Pos))
-#define SERCOM_USART_LENGTH_MASK    _U_(0x03FF)  /**< \brief (SERCOM_USART_LENGTH) MASK Register */
-
-/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:11;          /*!< bit:  0..10  Address Value                      */
-    uint32_t :2;               /*!< bit: 11..12  Reserved                           */
-    uint32_t LENEN:1;          /*!< bit:     13  Length Enable                      */
-    uint32_t HS:1;             /*!< bit:     14  High Speed Mode                    */
-    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
-    uint32_t LEN:8;            /*!< bit: 16..23  Length                             */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
-#define SERCOM_I2CM_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
-
-#define SERCOM_I2CM_ADDR_ADDR_Pos   0            /**< \brief (SERCOM_I2CM_ADDR) Address Value */
-#define SERCOM_I2CM_ADDR_ADDR_Msk   (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)
-#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
-#define SERCOM_I2CM_ADDR_LENEN_Pos  13           /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
-#define SERCOM_I2CM_ADDR_LENEN      (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)
-#define SERCOM_I2CM_ADDR_HS_Pos     14           /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
-#define SERCOM_I2CM_ADDR_HS         (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)
-#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
-#define SERCOM_I2CM_ADDR_TENBITEN   (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)
-#define SERCOM_I2CM_ADDR_LEN_Pos    16           /**< \brief (SERCOM_I2CM_ADDR) Length */
-#define SERCOM_I2CM_ADDR_LEN_Msk    (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)
-#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
-#define SERCOM_I2CM_ADDR_MASK       _U_(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
-
-/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t GENCEN:1;         /*!< bit:      0  General Call Address Enable        */
-    uint32_t ADDR:10;          /*!< bit:  1..10  Address Value                      */
-    uint32_t :4;               /*!< bit: 11..14  Reserved                           */
-    uint32_t TENBITEN:1;       /*!< bit:     15  Ten Bit Addressing Enable          */
-    uint32_t :1;               /*!< bit:     16  Reserved                           */
-    uint32_t ADDRMASK:10;      /*!< bit: 17..26  Address Mask                       */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_ADDR_OFFSET     0x24         /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
-#define SERCOM_I2CS_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
-
-#define SERCOM_I2CS_ADDR_GENCEN_Pos 0            /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
-#define SERCOM_I2CS_ADDR_GENCEN     (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)
-#define SERCOM_I2CS_ADDR_ADDR_Pos   1            /**< \brief (SERCOM_I2CS_ADDR) Address Value */
-#define SERCOM_I2CS_ADDR_ADDR_Msk   (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)
-#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
-#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15           /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
-#define SERCOM_I2CS_ADDR_TENBITEN   (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)
-#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17           /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
-#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
-#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
-#define SERCOM_I2CS_ADDR_MASK       _U_(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
-
-/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:8;           /*!< bit:  0.. 7  Address Value                      */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t ADDRMASK:8;       /*!< bit: 16..23  Address Mask                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_ADDR_OFFSET      0x24         /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
-#define SERCOM_SPI_ADDR_RESETVALUE  _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
-
-#define SERCOM_SPI_ADDR_ADDR_Pos    0            /**< \brief (SERCOM_SPI_ADDR) Address Value */
-#define SERCOM_SPI_ADDR_ADDR_Msk    (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos)
-#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
-#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16           /**< \brief (SERCOM_SPI_ADDR) Address Mask */
-#define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos)
-#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
-#define SERCOM_SPI_ADDR_MASK        _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */
-
-/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CM I2CM Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CM_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
-#define SERCOM_I2CM_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
-
-#define SERCOM_I2CM_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CM_DATA) Data Value */
-#define SERCOM_I2CM_DATA_DATA_Msk   (_U_(0xFFFFFFFF) << SERCOM_I2CM_DATA_DATA_Pos)
-#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
-#define SERCOM_I2CM_DATA_MASK       _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */
-
-/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS I2CS Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_I2CS_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CS_DATA_OFFSET     0x28         /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
-#define SERCOM_I2CS_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
-
-#define SERCOM_I2CS_DATA_DATA_Pos   0            /**< \brief (SERCOM_I2CS_DATA) Data Value */
-#define SERCOM_I2CS_DATA_DATA_Msk   (_U_(0xFFFFFFFF) << SERCOM_I2CS_DATA_DATA_Pos)
-#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
-#define SERCOM_I2CS_DATA_MASK       _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */
-
-/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_SPI_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_DATA_OFFSET      0x28         /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
-#define SERCOM_SPI_DATA_RESETVALUE  _U_(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
-
-#define SERCOM_SPI_DATA_DATA_Pos    0            /**< \brief (SERCOM_SPI_DATA) Data Value */
-#define SERCOM_SPI_DATA_DATA_Msk    (_U_(0xFFFFFFFF) << SERCOM_SPI_DATA_DATA_Pos)
-#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
-#define SERCOM_SPI_DATA_MASK        _U_(0xFFFFFFFF) /**< \brief (SERCOM_SPI_DATA) MASK Register */
-
-/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 32) USART USART Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Data Value                         */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SERCOM_USART_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_DATA_OFFSET    0x28         /**< \brief (SERCOM_USART_DATA offset) USART Data */
-#define SERCOM_USART_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
-
-#define SERCOM_USART_DATA_DATA_Pos  0            /**< \brief (SERCOM_USART_DATA) Data Value */
-#define SERCOM_USART_DATA_DATA_Msk  (_U_(0xFFFFFFFF) << SERCOM_USART_DATA_DATA_Pos)
-#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
-#define SERCOM_USART_DATA_MASK      _U_(0xFFFFFFFF) /**< \brief (SERCOM_USART_DATA) MASK Register */
-
-/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) I2CM I2CM Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_I2CM_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_I2CM_DBGCTRL_OFFSET  0x30         /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
-#define SERCOM_I2CM_DBGCTRL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
-
-#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
-#define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
-#define SERCOM_I2CM_DBGCTRL_MASK    _U_(0x01)    /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
-
-/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) SPI SPI Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_SPI_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_SPI_DBGCTRL_OFFSET   0x30         /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
-#define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
-
-#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
-#define SERCOM_SPI_DBGCTRL_DBGSTOP  (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
-#define SERCOM_SPI_DBGCTRL_MASK     _U_(0x01)    /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
-
-/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W  8) USART USART Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGSTOP:1;        /*!< bit:      0  Debug Mode                         */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} SERCOM_USART_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SERCOM_USART_DBGCTRL_OFFSET 0x30         /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
-#define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00)    /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
-
-#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0            /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
-#define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
-#define SERCOM_USART_DBGCTRL_MASK   _U_(0x01)    /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
-
-/** \brief SERCOM_I2CM hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* I2C Master Mode */
-  __IO SERCOM_I2CM_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
-  __IO SERCOM_I2CM_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
-  __IO SERCOM_I2CM_CTRLC_Type    CTRLC;       /**< \brief Offset: 0x08 (R/W 32) I2CM Control C */
-  __IO SERCOM_I2CM_BAUD_Type     BAUD;        /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
-       RoReg8                    Reserved1[0x4];
-  __IO SERCOM_I2CM_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
-       RoReg8                    Reserved2[0x1];
-  __IO SERCOM_I2CM_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
-       RoReg8                    Reserved3[0x1];
-  __IO SERCOM_I2CM_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x1];
-  __IO SERCOM_I2CM_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
-  __I  SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CM Synchronization Busy */
-       RoReg8                    Reserved5[0x4];
-  __IO SERCOM_I2CM_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
-  __IO SERCOM_I2CM_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W 32) I2CM Data */
-       RoReg8                    Reserved6[0x4];
-  __IO SERCOM_I2CM_DBGCTRL_Type  DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) I2CM Debug Control */
-} SercomI2cm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief SERCOM_I2CS hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* I2C Slave Mode */
-  __IO SERCOM_I2CS_CTRLA_Type    CTRLA;       /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
-  __IO SERCOM_I2CS_CTRLB_Type    CTRLB;       /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
-  __IO SERCOM_I2CS_CTRLC_Type    CTRLC;       /**< \brief Offset: 0x08 (R/W 32) I2CS Control C */
-       RoReg8                    Reserved1[0x8];
-  __IO SERCOM_I2CS_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
-       RoReg8                    Reserved2[0x1];
-  __IO SERCOM_I2CS_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
-       RoReg8                    Reserved3[0x1];
-  __IO SERCOM_I2CS_INTFLAG_Type  INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x1];
-  __IO SERCOM_I2CS_STATUS_Type   STATUS;      /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
-  __I  SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) I2CS Synchronization Busy */
-       RoReg8                    Reserved5[0x2];
-  __IO SERCOM_I2CS_LENGTH_Type   LENGTH;      /**< \brief Offset: 0x22 (R/W 16) I2CS Length */
-  __IO SERCOM_I2CS_ADDR_Type     ADDR;        /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
-  __IO SERCOM_I2CS_DATA_Type     DATA;        /**< \brief Offset: 0x28 (R/W 32) I2CS Data */
-} SercomI2cs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief SERCOM_SPI hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* SPI Mode */
-  __IO SERCOM_SPI_CTRLA_Type     CTRLA;       /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
-  __IO SERCOM_SPI_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
-  __IO SERCOM_SPI_CTRLC_Type     CTRLC;       /**< \brief Offset: 0x08 (R/W 32) SPI Control C */
-  __IO SERCOM_SPI_BAUD_Type      BAUD;        /**< \brief Offset: 0x0C (R/W  8) SPI Baud Rate */
-       RoReg8                    Reserved1[0x7];
-  __IO SERCOM_SPI_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) SPI Interrupt Enable Clear */
-       RoReg8                    Reserved2[0x1];
-  __IO SERCOM_SPI_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x16 (R/W  8) SPI Interrupt Enable Set */
-       RoReg8                    Reserved3[0x1];
-  __IO SERCOM_SPI_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) SPI Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x1];
-  __IO SERCOM_SPI_STATUS_Type    STATUS;      /**< \brief Offset: 0x1A (R/W 16) SPI Status */
-  __I  SERCOM_SPI_SYNCBUSY_Type  SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) SPI Synchronization Busy */
-       RoReg8                    Reserved5[0x2];
-  __IO SERCOM_SPI_LENGTH_Type    LENGTH;      /**< \brief Offset: 0x22 (R/W 16) SPI Length */
-  __IO SERCOM_SPI_ADDR_Type      ADDR;        /**< \brief Offset: 0x24 (R/W 32) SPI Address */
-  __IO SERCOM_SPI_DATA_Type      DATA;        /**< \brief Offset: 0x28 (R/W 32) SPI Data */
-       RoReg8                    Reserved6[0x4];
-  __IO SERCOM_SPI_DBGCTRL_Type   DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) SPI Debug Control */
-} SercomSpi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief SERCOM_USART hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USART Mode */
-  __IO SERCOM_USART_CTRLA_Type   CTRLA;       /**< \brief Offset: 0x00 (R/W 32) USART Control A */
-  __IO SERCOM_USART_CTRLB_Type   CTRLB;       /**< \brief Offset: 0x04 (R/W 32) USART Control B */
-  __IO SERCOM_USART_CTRLC_Type   CTRLC;       /**< \brief Offset: 0x08 (R/W 32) USART Control C */
-  __IO SERCOM_USART_BAUD_Type    BAUD;        /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
-  __IO SERCOM_USART_RXPL_Type    RXPL;        /**< \brief Offset: 0x0E (R/W  8) USART Receive Pulse Length */
-       RoReg8                    Reserved1[0x5];
-  __IO SERCOM_USART_INTENCLR_Type INTENCLR;    /**< \brief Offset: 0x14 (R/W  8) USART Interrupt Enable Clear */
-       RoReg8                    Reserved2[0x1];
-  __IO SERCOM_USART_INTENSET_Type INTENSET;    /**< \brief Offset: 0x16 (R/W  8) USART Interrupt Enable Set */
-       RoReg8                    Reserved3[0x1];
-  __IO SERCOM_USART_INTFLAG_Type INTFLAG;     /**< \brief Offset: 0x18 (R/W  8) USART Interrupt Flag Status and Clear */
-       RoReg8                    Reserved4[0x1];
-  __IO SERCOM_USART_STATUS_Type  STATUS;      /**< \brief Offset: 0x1A (R/W 16) USART Status */
-  __I  SERCOM_USART_SYNCBUSY_Type SYNCBUSY;    /**< \brief Offset: 0x1C (R/  32) USART Synchronization Busy */
-  __I  SERCOM_USART_RXERRCNT_Type RXERRCNT;    /**< \brief Offset: 0x20 (R/   8) USART Receive Error Count */
-       RoReg8                    Reserved5[0x1];
-  __IO SERCOM_USART_LENGTH_Type  LENGTH;      /**< \brief Offset: 0x22 (R/W 16) USART Length */
-       RoReg8                    Reserved6[0x4];
-  __IO SERCOM_USART_DATA_Type    DATA;        /**< \brief Offset: 0x28 (R/W 32) USART Data */
-       RoReg8                    Reserved7[0x4];
-  __IO SERCOM_USART_DBGCTRL_Type DBGCTRL;     /**< \brief Offset: 0x30 (R/W  8) USART Debug Control */
-} SercomUsart;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-       SercomI2cm                I2CM;        /**< \brief Offset: 0x00 I2C Master Mode */
-       SercomI2cs                I2CS;        /**< \brief Offset: 0x00 I2C Slave Mode */
-       SercomSpi                 SPI;         /**< \brief Offset: 0x00 SPI Mode */
-       SercomUsart               USART;       /**< \brief Offset: 0x00 USART Mode */
-} Sercom;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_SERCOM_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/supc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/supc.h
deleted file mode 100644
index 9963fa336a..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/supc.h
+++ /dev/null
@@ -1,554 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for SUPC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SUPC_COMPONENT_
-#define _SAMD51_SUPC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR SUPC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_SUPC Supply Controller */
-/*@{*/
-
-#define SUPC_U2407
-#define REV_SUPC                    0x100
-
-/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BOD33RDY:1;       /*!< bit:      0  BOD33 Ready                        */
-    uint32_t BOD33DET:1;       /*!< bit:      1  BOD33 Detection                    */
-    uint32_t B33SRDY:1;        /*!< bit:      2  BOD33 Synchronization Ready        */
-    uint32_t BOD12RDY:1;       /*!< bit:      3  BOD12 Ready                        */
-    uint32_t BOD12DET:1;       /*!< bit:      4  BOD12 Detection                    */
-    uint32_t B12SRDY:1;        /*!< bit:      5  BOD12 Synchronization Ready        */
-    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint32_t VREGRDY:1;        /*!< bit:      8  Voltage Regulator Ready            */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t VCORERDY:1;       /*!< bit:     10  VDDCORE Ready                      */
-    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_INTENCLR_OFFSET        0x00         /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */
-#define SUPC_INTENCLR_RESETVALUE    _U_(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define SUPC_INTENCLR_BOD33RDY_Pos  0            /**< \brief (SUPC_INTENCLR) BOD33 Ready */
-#define SUPC_INTENCLR_BOD33RDY      (_U_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos)
-#define SUPC_INTENCLR_BOD33DET_Pos  1            /**< \brief (SUPC_INTENCLR) BOD33 Detection */
-#define SUPC_INTENCLR_BOD33DET      (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos)
-#define SUPC_INTENCLR_B33SRDY_Pos   2            /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */
-#define SUPC_INTENCLR_B33SRDY       (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos)
-#define SUPC_INTENCLR_BOD12RDY_Pos  3            /**< \brief (SUPC_INTENCLR) BOD12 Ready */
-#define SUPC_INTENCLR_BOD12RDY      (_U_(0x1) << SUPC_INTENCLR_BOD12RDY_Pos)
-#define SUPC_INTENCLR_BOD12DET_Pos  4            /**< \brief (SUPC_INTENCLR) BOD12 Detection */
-#define SUPC_INTENCLR_BOD12DET      (_U_(0x1) << SUPC_INTENCLR_BOD12DET_Pos)
-#define SUPC_INTENCLR_B12SRDY_Pos   5            /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */
-#define SUPC_INTENCLR_B12SRDY       (_U_(0x1) << SUPC_INTENCLR_B12SRDY_Pos)
-#define SUPC_INTENCLR_VREGRDY_Pos   8            /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */
-#define SUPC_INTENCLR_VREGRDY       (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos)
-#define SUPC_INTENCLR_VCORERDY_Pos  10           /**< \brief (SUPC_INTENCLR) VDDCORE Ready */
-#define SUPC_INTENCLR_VCORERDY      (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos)
-#define SUPC_INTENCLR_MASK          _U_(0x0000053F) /**< \brief (SUPC_INTENCLR) MASK Register */
-
-/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BOD33RDY:1;       /*!< bit:      0  BOD33 Ready                        */
-    uint32_t BOD33DET:1;       /*!< bit:      1  BOD33 Detection                    */
-    uint32_t B33SRDY:1;        /*!< bit:      2  BOD33 Synchronization Ready        */
-    uint32_t BOD12RDY:1;       /*!< bit:      3  BOD12 Ready                        */
-    uint32_t BOD12DET:1;       /*!< bit:      4  BOD12 Detection                    */
-    uint32_t B12SRDY:1;        /*!< bit:      5  BOD12 Synchronization Ready        */
-    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint32_t VREGRDY:1;        /*!< bit:      8  Voltage Regulator Ready            */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t VCORERDY:1;       /*!< bit:     10  VDDCORE Ready                      */
-    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_INTENSET_OFFSET        0x04         /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */
-#define SUPC_INTENSET_RESETVALUE    _U_(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */
-
-#define SUPC_INTENSET_BOD33RDY_Pos  0            /**< \brief (SUPC_INTENSET) BOD33 Ready */
-#define SUPC_INTENSET_BOD33RDY      (_U_(0x1) << SUPC_INTENSET_BOD33RDY_Pos)
-#define SUPC_INTENSET_BOD33DET_Pos  1            /**< \brief (SUPC_INTENSET) BOD33 Detection */
-#define SUPC_INTENSET_BOD33DET      (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos)
-#define SUPC_INTENSET_B33SRDY_Pos   2            /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */
-#define SUPC_INTENSET_B33SRDY       (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos)
-#define SUPC_INTENSET_BOD12RDY_Pos  3            /**< \brief (SUPC_INTENSET) BOD12 Ready */
-#define SUPC_INTENSET_BOD12RDY      (_U_(0x1) << SUPC_INTENSET_BOD12RDY_Pos)
-#define SUPC_INTENSET_BOD12DET_Pos  4            /**< \brief (SUPC_INTENSET) BOD12 Detection */
-#define SUPC_INTENSET_BOD12DET      (_U_(0x1) << SUPC_INTENSET_BOD12DET_Pos)
-#define SUPC_INTENSET_B12SRDY_Pos   5            /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */
-#define SUPC_INTENSET_B12SRDY       (_U_(0x1) << SUPC_INTENSET_B12SRDY_Pos)
-#define SUPC_INTENSET_VREGRDY_Pos   8            /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */
-#define SUPC_INTENSET_VREGRDY       (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos)
-#define SUPC_INTENSET_VCORERDY_Pos  10           /**< \brief (SUPC_INTENSET) VDDCORE Ready */
-#define SUPC_INTENSET_VCORERDY      (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos)
-#define SUPC_INTENSET_MASK          _U_(0x0000053F) /**< \brief (SUPC_INTENSET) MASK Register */
-
-/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t BOD33RDY:1;       /*!< bit:      0  BOD33 Ready                        */
-    __I uint32_t BOD33DET:1;       /*!< bit:      1  BOD33 Detection                    */
-    __I uint32_t B33SRDY:1;        /*!< bit:      2  BOD33 Synchronization Ready        */
-    __I uint32_t BOD12RDY:1;       /*!< bit:      3  BOD12 Ready                        */
-    __I uint32_t BOD12DET:1;       /*!< bit:      4  BOD12 Detection                    */
-    __I uint32_t B12SRDY:1;        /*!< bit:      5  BOD12 Synchronization Ready        */
-    __I uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    __I uint32_t VREGRDY:1;        /*!< bit:      8  Voltage Regulator Ready            */
-    __I uint32_t :1;               /*!< bit:      9  Reserved                           */
-    __I uint32_t VCORERDY:1;       /*!< bit:     10  VDDCORE Ready                      */
-    __I uint32_t :21;              /*!< bit: 11..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_INTFLAG_OFFSET         0x08         /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define SUPC_INTFLAG_RESETVALUE     _U_(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define SUPC_INTFLAG_BOD33RDY_Pos   0            /**< \brief (SUPC_INTFLAG) BOD33 Ready */
-#define SUPC_INTFLAG_BOD33RDY       (_U_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos)
-#define SUPC_INTFLAG_BOD33DET_Pos   1            /**< \brief (SUPC_INTFLAG) BOD33 Detection */
-#define SUPC_INTFLAG_BOD33DET       (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos)
-#define SUPC_INTFLAG_B33SRDY_Pos    2            /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */
-#define SUPC_INTFLAG_B33SRDY        (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos)
-#define SUPC_INTFLAG_BOD12RDY_Pos   3            /**< \brief (SUPC_INTFLAG) BOD12 Ready */
-#define SUPC_INTFLAG_BOD12RDY       (_U_(0x1) << SUPC_INTFLAG_BOD12RDY_Pos)
-#define SUPC_INTFLAG_BOD12DET_Pos   4            /**< \brief (SUPC_INTFLAG) BOD12 Detection */
-#define SUPC_INTFLAG_BOD12DET       (_U_(0x1) << SUPC_INTFLAG_BOD12DET_Pos)
-#define SUPC_INTFLAG_B12SRDY_Pos    5            /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */
-#define SUPC_INTFLAG_B12SRDY        (_U_(0x1) << SUPC_INTFLAG_B12SRDY_Pos)
-#define SUPC_INTFLAG_VREGRDY_Pos    8            /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */
-#define SUPC_INTFLAG_VREGRDY        (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos)
-#define SUPC_INTFLAG_VCORERDY_Pos   10           /**< \brief (SUPC_INTFLAG) VDDCORE Ready */
-#define SUPC_INTFLAG_VCORERDY       (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos)
-#define SUPC_INTFLAG_MASK           _U_(0x0000053F) /**< \brief (SUPC_INTFLAG) MASK Register */
-
-/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BOD33RDY:1;       /*!< bit:      0  BOD33 Ready                        */
-    uint32_t BOD33DET:1;       /*!< bit:      1  BOD33 Detection                    */
-    uint32_t B33SRDY:1;        /*!< bit:      2  BOD33 Synchronization Ready        */
-    uint32_t BOD12RDY:1;       /*!< bit:      3  BOD12 Ready                        */
-    uint32_t BOD12DET:1;       /*!< bit:      4  BOD12 Detection                    */
-    uint32_t B12SRDY:1;        /*!< bit:      5  BOD12 Synchronization Ready        */
-    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint32_t VREGRDY:1;        /*!< bit:      8  Voltage Regulator Ready            */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t VCORERDY:1;       /*!< bit:     10  VDDCORE Ready                      */
-    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_STATUS_OFFSET          0x0C         /**< \brief (SUPC_STATUS offset) Power and Clocks Status */
-#define SUPC_STATUS_RESETVALUE      _U_(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */
-
-#define SUPC_STATUS_BOD33RDY_Pos    0            /**< \brief (SUPC_STATUS) BOD33 Ready */
-#define SUPC_STATUS_BOD33RDY        (_U_(0x1) << SUPC_STATUS_BOD33RDY_Pos)
-#define SUPC_STATUS_BOD33DET_Pos    1            /**< \brief (SUPC_STATUS) BOD33 Detection */
-#define SUPC_STATUS_BOD33DET        (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos)
-#define SUPC_STATUS_B33SRDY_Pos     2            /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */
-#define SUPC_STATUS_B33SRDY         (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos)
-#define SUPC_STATUS_BOD12RDY_Pos    3            /**< \brief (SUPC_STATUS) BOD12 Ready */
-#define SUPC_STATUS_BOD12RDY        (_U_(0x1) << SUPC_STATUS_BOD12RDY_Pos)
-#define SUPC_STATUS_BOD12DET_Pos    4            /**< \brief (SUPC_STATUS) BOD12 Detection */
-#define SUPC_STATUS_BOD12DET        (_U_(0x1) << SUPC_STATUS_BOD12DET_Pos)
-#define SUPC_STATUS_B12SRDY_Pos     5            /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */
-#define SUPC_STATUS_B12SRDY         (_U_(0x1) << SUPC_STATUS_B12SRDY_Pos)
-#define SUPC_STATUS_VREGRDY_Pos     8            /**< \brief (SUPC_STATUS) Voltage Regulator Ready */
-#define SUPC_STATUS_VREGRDY         (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos)
-#define SUPC_STATUS_VCORERDY_Pos    10           /**< \brief (SUPC_STATUS) VDDCORE Ready */
-#define SUPC_STATUS_VCORERDY        (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos)
-#define SUPC_STATUS_MASK            _U_(0x0000053F) /**< \brief (SUPC_STATUS) MASK Register */
-
-/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t ACTION:2;         /*!< bit:  2.. 3  Action when Threshold Crossed      */
-    uint32_t STDBYCFG:1;       /*!< bit:      4  Configuration in Standby mode      */
-    uint32_t RUNSTDBY:1;       /*!< bit:      5  Run in Standby mode                */
-    uint32_t RUNHIB:1;         /*!< bit:      6  Run in Hibernate mode              */
-    uint32_t RUNBKUP:1;        /*!< bit:      7  Run in Backup mode                 */
-    uint32_t HYST:4;           /*!< bit:  8..11  Hysteresis value                   */
-    uint32_t PSEL:3;           /*!< bit: 12..14  Prescaler Select                   */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t LEVEL:8;          /*!< bit: 16..23  Threshold Level for VDD            */
-    uint32_t VBATLEVEL:8;      /*!< bit: 24..31  Threshold Level in battery backup sleep mode for VBAT */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_BOD33_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_BOD33_OFFSET           0x10         /**< \brief (SUPC_BOD33 offset) BOD33 Control */
-#define SUPC_BOD33_RESETVALUE       _U_(0x00000000) /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */
-
-#define SUPC_BOD33_ENABLE_Pos       1            /**< \brief (SUPC_BOD33) Enable */
-#define SUPC_BOD33_ENABLE           (_U_(0x1) << SUPC_BOD33_ENABLE_Pos)
-#define SUPC_BOD33_ACTION_Pos       2            /**< \brief (SUPC_BOD33) Action when Threshold Crossed */
-#define SUPC_BOD33_ACTION_Msk       (_U_(0x3) << SUPC_BOD33_ACTION_Pos)
-#define SUPC_BOD33_ACTION(value)    (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))
-#define   SUPC_BOD33_ACTION_NONE_Val      _U_(0x0)   /**< \brief (SUPC_BOD33) No action */
-#define   SUPC_BOD33_ACTION_RESET_Val     _U_(0x1)   /**< \brief (SUPC_BOD33) The BOD33 generates a reset */
-#define   SUPC_BOD33_ACTION_INT_Val       _U_(0x2)   /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */
-#define   SUPC_BOD33_ACTION_BKUP_Val      _U_(0x3)   /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode */
-#define SUPC_BOD33_ACTION_NONE      (SUPC_BOD33_ACTION_NONE_Val    << SUPC_BOD33_ACTION_Pos)
-#define SUPC_BOD33_ACTION_RESET     (SUPC_BOD33_ACTION_RESET_Val   << SUPC_BOD33_ACTION_Pos)
-#define SUPC_BOD33_ACTION_INT       (SUPC_BOD33_ACTION_INT_Val     << SUPC_BOD33_ACTION_Pos)
-#define SUPC_BOD33_ACTION_BKUP      (SUPC_BOD33_ACTION_BKUP_Val    << SUPC_BOD33_ACTION_Pos)
-#define SUPC_BOD33_STDBYCFG_Pos     4            /**< \brief (SUPC_BOD33) Configuration in Standby mode */
-#define SUPC_BOD33_STDBYCFG         (_U_(0x1) << SUPC_BOD33_STDBYCFG_Pos)
-#define SUPC_BOD33_RUNSTDBY_Pos     5            /**< \brief (SUPC_BOD33) Run in Standby mode */
-#define SUPC_BOD33_RUNSTDBY         (_U_(0x1) << SUPC_BOD33_RUNSTDBY_Pos)
-#define SUPC_BOD33_RUNHIB_Pos       6            /**< \brief (SUPC_BOD33) Run in Hibernate mode */
-#define SUPC_BOD33_RUNHIB           (_U_(0x1) << SUPC_BOD33_RUNHIB_Pos)
-#define SUPC_BOD33_RUNBKUP_Pos      7            /**< \brief (SUPC_BOD33) Run in Backup mode */
-#define SUPC_BOD33_RUNBKUP          (_U_(0x1) << SUPC_BOD33_RUNBKUP_Pos)
-#define SUPC_BOD33_HYST_Pos         8            /**< \brief (SUPC_BOD33) Hysteresis value */
-#define SUPC_BOD33_HYST_Msk         (_U_(0xF) << SUPC_BOD33_HYST_Pos)
-#define SUPC_BOD33_HYST(value)      (SUPC_BOD33_HYST_Msk & ((value) << SUPC_BOD33_HYST_Pos))
-#define SUPC_BOD33_PSEL_Pos         12           /**< \brief (SUPC_BOD33) Prescaler Select */
-#define SUPC_BOD33_PSEL_Msk         (_U_(0x7) << SUPC_BOD33_PSEL_Pos)
-#define SUPC_BOD33_PSEL(value)      (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))
-#define   SUPC_BOD33_PSEL_NODIV_Val       _U_(0x0)   /**< \brief (SUPC_BOD33) Not divided */
-#define   SUPC_BOD33_PSEL_DIV4_Val        _U_(0x1)   /**< \brief (SUPC_BOD33) Divide clock by 4 */
-#define   SUPC_BOD33_PSEL_DIV8_Val        _U_(0x2)   /**< \brief (SUPC_BOD33) Divide clock by 8 */
-#define   SUPC_BOD33_PSEL_DIV16_Val       _U_(0x3)   /**< \brief (SUPC_BOD33) Divide clock by 16 */
-#define   SUPC_BOD33_PSEL_DIV32_Val       _U_(0x4)   /**< \brief (SUPC_BOD33) Divide clock by 32 */
-#define   SUPC_BOD33_PSEL_DIV64_Val       _U_(0x5)   /**< \brief (SUPC_BOD33) Divide clock by 64 */
-#define   SUPC_BOD33_PSEL_DIV128_Val      _U_(0x6)   /**< \brief (SUPC_BOD33) Divide clock by 128 */
-#define   SUPC_BOD33_PSEL_DIV256_Val      _U_(0x7)   /**< \brief (SUPC_BOD33) Divide clock by 256 */
-#define SUPC_BOD33_PSEL_NODIV       (SUPC_BOD33_PSEL_NODIV_Val     << SUPC_BOD33_PSEL_Pos)
-#define SUPC_BOD33_PSEL_DIV4        (SUPC_BOD33_PSEL_DIV4_Val      << SUPC_BOD33_PSEL_Pos)
-#define SUPC_BOD33_PSEL_DIV8        (SUPC_BOD33_PSEL_DIV8_Val      << SUPC_BOD33_PSEL_Pos)
-#define SUPC_BOD33_PSEL_DIV16       (SUPC_BOD33_PSEL_DIV16_Val     << SUPC_BOD33_PSEL_Pos)
-#define SUPC_BOD33_PSEL_DIV32       (SUPC_BOD33_PSEL_DIV32_Val     << SUPC_BOD33_PSEL_Pos)
-#define SUPC_BOD33_PSEL_DIV64       (SUPC_BOD33_PSEL_DIV64_Val     << SUPC_BOD33_PSEL_Pos)
-#define SUPC_BOD33_PSEL_DIV128      (SUPC_BOD33_PSEL_DIV128_Val    << SUPC_BOD33_PSEL_Pos)
-#define SUPC_BOD33_PSEL_DIV256      (SUPC_BOD33_PSEL_DIV256_Val    << SUPC_BOD33_PSEL_Pos)
-#define SUPC_BOD33_LEVEL_Pos        16           /**< \brief (SUPC_BOD33) Threshold Level for VDD */
-#define SUPC_BOD33_LEVEL_Msk        (_U_(0xFF) << SUPC_BOD33_LEVEL_Pos)
-#define SUPC_BOD33_LEVEL(value)     (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))
-#define SUPC_BOD33_VBATLEVEL_Pos    24           /**< \brief (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT */
-#define SUPC_BOD33_VBATLEVEL_Msk    (_U_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos)
-#define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))
-#define SUPC_BOD33_MASK             _U_(0xFFFF7FFE) /**< \brief (SUPC_BOD33) MASK Register */
-
-/* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t HYST:1;           /*!< bit:      2  Hysteresis Enable                  */
-    uint32_t ACTION:2;         /*!< bit:  3.. 4  Action when Threshold Crossed      */
-    uint32_t STDBYCFG:1;       /*!< bit:      5  Configuration in Standby mode      */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t ACTCFG:1;         /*!< bit:      8  Configuration in Active mode       */
-    uint32_t :3;               /*!< bit:  9..11  Reserved                           */
-    uint32_t PSEL:4;           /*!< bit: 12..15  Prescaler Select                   */
-    uint32_t LEVEL:6;          /*!< bit: 16..21  Threshold Level                    */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_BOD12_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_BOD12_OFFSET           0x14         /**< \brief (SUPC_BOD12 offset) BOD12 Control */
-#define SUPC_BOD12_RESETVALUE       _U_(0x00000000) /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */
-
-#define SUPC_BOD12_ENABLE_Pos       1            /**< \brief (SUPC_BOD12) Enable */
-#define SUPC_BOD12_ENABLE           (_U_(0x1) << SUPC_BOD12_ENABLE_Pos)
-#define SUPC_BOD12_HYST_Pos         2            /**< \brief (SUPC_BOD12) Hysteresis Enable */
-#define SUPC_BOD12_HYST             (_U_(0x1) << SUPC_BOD12_HYST_Pos)
-#define SUPC_BOD12_ACTION_Pos       3            /**< \brief (SUPC_BOD12) Action when Threshold Crossed */
-#define SUPC_BOD12_ACTION_Msk       (_U_(0x3) << SUPC_BOD12_ACTION_Pos)
-#define SUPC_BOD12_ACTION(value)    (SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos))
-#define   SUPC_BOD12_ACTION_NONE_Val      _U_(0x0)   /**< \brief (SUPC_BOD12) No action */
-#define   SUPC_BOD12_ACTION_RESET_Val     _U_(0x1)   /**< \brief (SUPC_BOD12) The BOD12 generates a reset */
-#define   SUPC_BOD12_ACTION_INT_Val       _U_(0x2)   /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */
-#define SUPC_BOD12_ACTION_NONE      (SUPC_BOD12_ACTION_NONE_Val    << SUPC_BOD12_ACTION_Pos)
-#define SUPC_BOD12_ACTION_RESET     (SUPC_BOD12_ACTION_RESET_Val   << SUPC_BOD12_ACTION_Pos)
-#define SUPC_BOD12_ACTION_INT       (SUPC_BOD12_ACTION_INT_Val     << SUPC_BOD12_ACTION_Pos)
-#define SUPC_BOD12_STDBYCFG_Pos     5            /**< \brief (SUPC_BOD12) Configuration in Standby mode */
-#define SUPC_BOD12_STDBYCFG         (_U_(0x1) << SUPC_BOD12_STDBYCFG_Pos)
-#define SUPC_BOD12_RUNSTDBY_Pos     6            /**< \brief (SUPC_BOD12) Run during Standby */
-#define SUPC_BOD12_RUNSTDBY         (_U_(0x1) << SUPC_BOD12_RUNSTDBY_Pos)
-#define SUPC_BOD12_ACTCFG_Pos       8            /**< \brief (SUPC_BOD12) Configuration in Active mode */
-#define SUPC_BOD12_ACTCFG           (_U_(0x1) << SUPC_BOD12_ACTCFG_Pos)
-#define SUPC_BOD12_PSEL_Pos         12           /**< \brief (SUPC_BOD12) Prescaler Select */
-#define SUPC_BOD12_PSEL_Msk         (_U_(0xF) << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL(value)      (SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos))
-#define   SUPC_BOD12_PSEL_DIV2_Val        _U_(0x0)   /**< \brief (SUPC_BOD12) Divide clock by 2 */
-#define   SUPC_BOD12_PSEL_DIV4_Val        _U_(0x1)   /**< \brief (SUPC_BOD12) Divide clock by 4 */
-#define   SUPC_BOD12_PSEL_DIV8_Val        _U_(0x2)   /**< \brief (SUPC_BOD12) Divide clock by 8 */
-#define   SUPC_BOD12_PSEL_DIV16_Val       _U_(0x3)   /**< \brief (SUPC_BOD12) Divide clock by 16 */
-#define   SUPC_BOD12_PSEL_DIV32_Val       _U_(0x4)   /**< \brief (SUPC_BOD12) Divide clock by 32 */
-#define   SUPC_BOD12_PSEL_DIV64_Val       _U_(0x5)   /**< \brief (SUPC_BOD12) Divide clock by 64 */
-#define   SUPC_BOD12_PSEL_DIV128_Val      _U_(0x6)   /**< \brief (SUPC_BOD12) Divide clock by 128 */
-#define   SUPC_BOD12_PSEL_DIV256_Val      _U_(0x7)   /**< \brief (SUPC_BOD12) Divide clock by 256 */
-#define   SUPC_BOD12_PSEL_DIV512_Val      _U_(0x8)   /**< \brief (SUPC_BOD12) Divide clock by 512 */
-#define   SUPC_BOD12_PSEL_DIV1024_Val     _U_(0x9)   /**< \brief (SUPC_BOD12) Divide clock by 1024 */
-#define   SUPC_BOD12_PSEL_DIV2048_Val     _U_(0xA)   /**< \brief (SUPC_BOD12) Divide clock by 2048 */
-#define   SUPC_BOD12_PSEL_DIV4096_Val     _U_(0xB)   /**< \brief (SUPC_BOD12) Divide clock by 4096 */
-#define   SUPC_BOD12_PSEL_DIV8192_Val     _U_(0xC)   /**< \brief (SUPC_BOD12) Divide clock by 8192 */
-#define   SUPC_BOD12_PSEL_DIV16384_Val    _U_(0xD)   /**< \brief (SUPC_BOD12) Divide clock by 16384 */
-#define   SUPC_BOD12_PSEL_DIV32768_Val    _U_(0xE)   /**< \brief (SUPC_BOD12) Divide clock by 32768 */
-#define   SUPC_BOD12_PSEL_DIV65536_Val    _U_(0xF)   /**< \brief (SUPC_BOD12) Divide clock by 65536 */
-#define SUPC_BOD12_PSEL_DIV2        (SUPC_BOD12_PSEL_DIV2_Val      << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV4        (SUPC_BOD12_PSEL_DIV4_Val      << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV8        (SUPC_BOD12_PSEL_DIV8_Val      << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV16       (SUPC_BOD12_PSEL_DIV16_Val     << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV32       (SUPC_BOD12_PSEL_DIV32_Val     << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV64       (SUPC_BOD12_PSEL_DIV64_Val     << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV128      (SUPC_BOD12_PSEL_DIV128_Val    << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV256      (SUPC_BOD12_PSEL_DIV256_Val    << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV512      (SUPC_BOD12_PSEL_DIV512_Val    << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV1024     (SUPC_BOD12_PSEL_DIV1024_Val   << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV2048     (SUPC_BOD12_PSEL_DIV2048_Val   << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV4096     (SUPC_BOD12_PSEL_DIV4096_Val   << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV8192     (SUPC_BOD12_PSEL_DIV8192_Val   << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV16384    (SUPC_BOD12_PSEL_DIV16384_Val  << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV32768    (SUPC_BOD12_PSEL_DIV32768_Val  << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_PSEL_DIV65536    (SUPC_BOD12_PSEL_DIV65536_Val  << SUPC_BOD12_PSEL_Pos)
-#define SUPC_BOD12_LEVEL_Pos        16           /**< \brief (SUPC_BOD12) Threshold Level */
-#define SUPC_BOD12_LEVEL_Msk        (_U_(0x3F) << SUPC_BOD12_LEVEL_Pos)
-#define SUPC_BOD12_LEVEL(value)     (SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos))
-#define SUPC_BOD12_MASK             _U_(0x003FF17E) /**< \brief (SUPC_BOD12) MASK Register */
-
-/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t SEL:1;            /*!< bit:      2  Voltage Regulator Selection        */
-    uint32_t :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint32_t RUNBKUP:1;        /*!< bit:      7  Run in Backup mode                 */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t VSEN:1;           /*!< bit:     16  Voltage Scaling Enable             */
-    uint32_t :7;               /*!< bit: 17..23  Reserved                           */
-    uint32_t VSPER:3;          /*!< bit: 24..26  Voltage Scaling Period             */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_VREG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_VREG_OFFSET            0x18         /**< \brief (SUPC_VREG offset) VREG Control */
-#define SUPC_VREG_RESETVALUE        _U_(0x00000002) /**< \brief (SUPC_VREG reset_value) VREG Control */
-
-#define SUPC_VREG_ENABLE_Pos        1            /**< \brief (SUPC_VREG) Enable */
-#define SUPC_VREG_ENABLE            (_U_(0x1) << SUPC_VREG_ENABLE_Pos)
-#define SUPC_VREG_SEL_Pos           2            /**< \brief (SUPC_VREG) Voltage Regulator Selection */
-#define SUPC_VREG_SEL               (_U_(0x1) << SUPC_VREG_SEL_Pos)
-#define   SUPC_VREG_SEL_LDO_Val           _U_(0x0)   /**< \brief (SUPC_VREG) LDO selection */
-#define   SUPC_VREG_SEL_BUCK_Val          _U_(0x1)   /**< \brief (SUPC_VREG) Buck selection */
-#define SUPC_VREG_SEL_LDO           (SUPC_VREG_SEL_LDO_Val         << SUPC_VREG_SEL_Pos)
-#define SUPC_VREG_SEL_BUCK          (SUPC_VREG_SEL_BUCK_Val        << SUPC_VREG_SEL_Pos)
-#define SUPC_VREG_RUNBKUP_Pos       7            /**< \brief (SUPC_VREG) Run in Backup mode */
-#define SUPC_VREG_RUNBKUP           (_U_(0x1) << SUPC_VREG_RUNBKUP_Pos)
-#define SUPC_VREG_VSEN_Pos          16           /**< \brief (SUPC_VREG) Voltage Scaling Enable */
-#define SUPC_VREG_VSEN              (_U_(0x1) << SUPC_VREG_VSEN_Pos)
-#define SUPC_VREG_VSPER_Pos         24           /**< \brief (SUPC_VREG) Voltage Scaling Period */
-#define SUPC_VREG_VSPER_Msk         (_U_(0x7) << SUPC_VREG_VSPER_Pos)
-#define SUPC_VREG_VSPER(value)      (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))
-#define SUPC_VREG_MASK              _U_(0x07010086) /**< \brief (SUPC_VREG) MASK Register */
-
-/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t TSEN:1;           /*!< bit:      1  Temperature Sensor Output Enable   */
-    uint32_t VREFOE:1;         /*!< bit:      2  Voltage Reference Output Enable    */
-    uint32_t TSSEL:1;          /*!< bit:      3  Temperature Sensor Selection       */
-    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
-    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Contrl                   */
-    uint32_t :8;               /*!< bit:  8..15  Reserved                           */
-    uint32_t SEL:4;            /*!< bit: 16..19  Voltage Reference Selection        */
-    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_VREF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_VREF_OFFSET            0x1C         /**< \brief (SUPC_VREF offset) VREF Control */
-#define SUPC_VREF_RESETVALUE        _U_(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */
-
-#define SUPC_VREF_TSEN_Pos          1            /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */
-#define SUPC_VREF_TSEN              (_U_(0x1) << SUPC_VREF_TSEN_Pos)
-#define SUPC_VREF_VREFOE_Pos        2            /**< \brief (SUPC_VREF) Voltage Reference Output Enable */
-#define SUPC_VREF_VREFOE            (_U_(0x1) << SUPC_VREF_VREFOE_Pos)
-#define SUPC_VREF_TSSEL_Pos         3            /**< \brief (SUPC_VREF) Temperature Sensor Selection */
-#define SUPC_VREF_TSSEL             (_U_(0x1) << SUPC_VREF_TSSEL_Pos)
-#define SUPC_VREF_RUNSTDBY_Pos      6            /**< \brief (SUPC_VREF) Run during Standby */
-#define SUPC_VREF_RUNSTDBY          (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos)
-#define SUPC_VREF_ONDEMAND_Pos      7            /**< \brief (SUPC_VREF) On Demand Contrl */
-#define SUPC_VREF_ONDEMAND          (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos)
-#define SUPC_VREF_SEL_Pos           16           /**< \brief (SUPC_VREF) Voltage Reference Selection */
-#define SUPC_VREF_SEL_Msk           (_U_(0xF) << SUPC_VREF_SEL_Pos)
-#define SUPC_VREF_SEL(value)        (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))
-#define   SUPC_VREF_SEL_1V0_Val           _U_(0x0)   /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */
-#define   SUPC_VREF_SEL_1V1_Val           _U_(0x1)   /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */
-#define   SUPC_VREF_SEL_1V2_Val           _U_(0x2)   /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */
-#define   SUPC_VREF_SEL_1V25_Val          _U_(0x3)   /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */
-#define   SUPC_VREF_SEL_2V0_Val           _U_(0x4)   /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */
-#define   SUPC_VREF_SEL_2V2_Val           _U_(0x5)   /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */
-#define   SUPC_VREF_SEL_2V4_Val           _U_(0x6)   /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */
-#define   SUPC_VREF_SEL_2V5_Val           _U_(0x7)   /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */
-#define SUPC_VREF_SEL_1V0           (SUPC_VREF_SEL_1V0_Val         << SUPC_VREF_SEL_Pos)
-#define SUPC_VREF_SEL_1V1           (SUPC_VREF_SEL_1V1_Val         << SUPC_VREF_SEL_Pos)
-#define SUPC_VREF_SEL_1V2           (SUPC_VREF_SEL_1V2_Val         << SUPC_VREF_SEL_Pos)
-#define SUPC_VREF_SEL_1V25          (SUPC_VREF_SEL_1V25_Val        << SUPC_VREF_SEL_Pos)
-#define SUPC_VREF_SEL_2V0           (SUPC_VREF_SEL_2V0_Val         << SUPC_VREF_SEL_Pos)
-#define SUPC_VREF_SEL_2V2           (SUPC_VREF_SEL_2V2_Val         << SUPC_VREF_SEL_Pos)
-#define SUPC_VREF_SEL_2V4           (SUPC_VREF_SEL_2V4_Val         << SUPC_VREF_SEL_Pos)
-#define SUPC_VREF_SEL_2V5           (SUPC_VREF_SEL_2V5_Val         << SUPC_VREF_SEL_Pos)
-#define SUPC_VREF_MASK              _U_(0x000F00CE) /**< \brief (SUPC_VREF) MASK Register */
-
-/* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CONF:1;           /*!< bit:      0  Battery Backup Configuration       */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t WAKEEN:1;         /*!< bit:      2  Wake Enable                        */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_BBPS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_BBPS_OFFSET            0x20         /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */
-#define SUPC_BBPS_RESETVALUE        _U_(0x00000000) /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */
-
-#define SUPC_BBPS_CONF_Pos          0            /**< \brief (SUPC_BBPS) Battery Backup Configuration */
-#define SUPC_BBPS_CONF              (_U_(0x1) << SUPC_BBPS_CONF_Pos)
-#define   SUPC_BBPS_CONF_BOD33_Val        _U_(0x0)   /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */
-#define   SUPC_BBPS_CONF_FORCED_Val       _U_(0x1)   /**< \brief (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power */
-#define SUPC_BBPS_CONF_BOD33        (SUPC_BBPS_CONF_BOD33_Val      << SUPC_BBPS_CONF_Pos)
-#define SUPC_BBPS_CONF_FORCED       (SUPC_BBPS_CONF_FORCED_Val     << SUPC_BBPS_CONF_Pos)
-#define SUPC_BBPS_WAKEEN_Pos        2            /**< \brief (SUPC_BBPS) Wake Enable */
-#define SUPC_BBPS_WAKEEN            (_U_(0x1) << SUPC_BBPS_WAKEEN_Pos)
-#define SUPC_BBPS_MASK              _U_(0x00000005) /**< \brief (SUPC_BBPS) MASK Register */
-
-/* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EN:2;             /*!< bit:  0.. 1  Enable Output                      */
-    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
-    uint32_t CLR:2;            /*!< bit:  8.. 9  Clear Output                       */
-    uint32_t :6;               /*!< bit: 10..15  Reserved                           */
-    uint32_t SET:2;            /*!< bit: 16..17  Set Output                         */
-    uint32_t :6;               /*!< bit: 18..23  Reserved                           */
-    uint32_t RTCTGL:2;         /*!< bit: 24..25  RTC Toggle Output                  */
-    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_BKOUT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_BKOUT_OFFSET           0x24         /**< \brief (SUPC_BKOUT offset) Backup Output Control */
-#define SUPC_BKOUT_RESETVALUE       _U_(0x00000000) /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */
-
-#define SUPC_BKOUT_EN_Pos           0            /**< \brief (SUPC_BKOUT) Enable Output */
-#define SUPC_BKOUT_EN_Msk           (_U_(0x3) << SUPC_BKOUT_EN_Pos)
-#define SUPC_BKOUT_EN(value)        (SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))
-#define SUPC_BKOUT_CLR_Pos          8            /**< \brief (SUPC_BKOUT) Clear Output */
-#define SUPC_BKOUT_CLR_Msk          (_U_(0x3) << SUPC_BKOUT_CLR_Pos)
-#define SUPC_BKOUT_CLR(value)       (SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))
-#define SUPC_BKOUT_SET_Pos          16           /**< \brief (SUPC_BKOUT) Set Output */
-#define SUPC_BKOUT_SET_Msk          (_U_(0x3) << SUPC_BKOUT_SET_Pos)
-#define SUPC_BKOUT_SET(value)       (SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))
-#define SUPC_BKOUT_RTCTGL_Pos       24           /**< \brief (SUPC_BKOUT) RTC Toggle Output */
-#define SUPC_BKOUT_RTCTGL_Msk       (_U_(0x3) << SUPC_BKOUT_RTCTGL_Pos)
-#define SUPC_BKOUT_RTCTGL(value)    (SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))
-#define SUPC_BKOUT_MASK             _U_(0x03030303) /**< \brief (SUPC_BKOUT) MASK Register */
-
-/* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/  32) Backup Input Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BKIN:8;           /*!< bit:  0.. 7  Backup Input Value                 */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} SUPC_BKIN_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SUPC_BKIN_OFFSET            0x28         /**< \brief (SUPC_BKIN offset) Backup Input Control */
-#define SUPC_BKIN_RESETVALUE        _U_(0x00000000) /**< \brief (SUPC_BKIN reset_value) Backup Input Control */
-
-#define SUPC_BKIN_BKIN_Pos          0            /**< \brief (SUPC_BKIN) Backup Input Value */
-#define SUPC_BKIN_BKIN_Msk          (_U_(0xFF) << SUPC_BKIN_BKIN_Pos)
-#define SUPC_BKIN_BKIN(value)       (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))
-#define SUPC_BKIN_MASK              _U_(0x000000FF) /**< \brief (SUPC_BKIN) MASK Register */
-
-/** \brief SUPC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO SUPC_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
-  __IO SUPC_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
-  __IO SUPC_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
-  __I  SUPC_STATUS_Type          STATUS;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
-  __IO SUPC_BOD33_Type           BOD33;       /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */
-  __IO SUPC_BOD12_Type           BOD12;       /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */
-  __IO SUPC_VREG_Type            VREG;        /**< \brief Offset: 0x18 (R/W 32) VREG Control */
-  __IO SUPC_VREF_Type            VREF;        /**< \brief Offset: 0x1C (R/W 32) VREF Control */
-  __IO SUPC_BBPS_Type            BBPS;        /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */
-  __IO SUPC_BKOUT_Type           BKOUT;       /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */
-  __I  SUPC_BKIN_Type            BKIN;        /**< \brief Offset: 0x28 (R/  32) Backup Input Control */
-} Supc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_SUPC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tal.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tal.h
deleted file mode 100644
index dc904e5569..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tal.h
+++ /dev/null
@@ -1,1842 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for TAL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TAL_COMPONENT_
-#define _SAMD51_TAL_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR TAL */
-/* ========================================================================== */
-/** \addtogroup SAMD51_TAL Trigger Allocator */
-/*@{*/
-
-#define TAL_U2253
-#define REV_TAL                     0x200
-
-/* -------- TAL_CTRLA : (TAL Offset: 0x000) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_CTRLA_OFFSET            0x000        /**< \brief (TAL_CTRLA offset) Control A */
-#define TAL_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (TAL_CTRLA reset_value) Control A */
-
-#define TAL_CTRLA_SWRST_Pos         0            /**< \brief (TAL_CTRLA) Software Reset */
-#define TAL_CTRLA_SWRST             (_U_(0x1) << TAL_CTRLA_SWRST_Pos)
-#define TAL_CTRLA_ENABLE_Pos        1            /**< \brief (TAL_CTRLA) Enable */
-#define TAL_CTRLA_ENABLE            (_U_(0x1) << TAL_CTRLA_ENABLE_Pos)
-#define TAL_CTRLA_MASK              _U_(0x03)    /**< \brief (TAL_CTRLA) MASK Register */
-
-/* -------- TAL_EXTCTRL : (TAL Offset: 0x001) (R/W  8) External Break Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  ENABLE:1;         /*!< bit:      0  Enable BRK Pin                     */
-    uint8_t  INV:1;            /*!< bit:      1  Invert BRK Pin                     */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_EXTCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_EXTCTRL_OFFSET          0x001        /**< \brief (TAL_EXTCTRL offset) External Break Control */
-#define TAL_EXTCTRL_RESETVALUE      _U_(0x00)    /**< \brief (TAL_EXTCTRL reset_value) External Break Control */
-
-#define TAL_EXTCTRL_ENABLE_Pos      0            /**< \brief (TAL_EXTCTRL) Enable BRK Pin */
-#define TAL_EXTCTRL_ENABLE          (_U_(0x1) << TAL_EXTCTRL_ENABLE_Pos)
-#define TAL_EXTCTRL_INV_Pos         1            /**< \brief (TAL_EXTCTRL) Invert BRK Pin */
-#define TAL_EXTCTRL_INV             (_U_(0x1) << TAL_EXTCTRL_INV_Pos)
-#define TAL_EXTCTRL_MASK            _U_(0x03)    /**< \brief (TAL_EXTCTRL) MASK Register */
-
-/* -------- TAL_EVCTRL : (TAL Offset: 0x004) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t BRKEI:1;          /*!< bit:      0  Break Input Event Enable           */
-    uint16_t BRKEO:1;          /*!< bit:      1  Break Output Event Enable          */
-    uint16_t IRQMONEO0:1;      /*!< bit:      2  Interrupt Request Monitor 0 Output Event Enable */
-    uint16_t :13;              /*!< bit:  3..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t IRQMONEO:1;       /*!< bit:      2  Interrupt Request Monitor x Output Event Enable */
-    uint16_t :13;              /*!< bit:  3..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TAL_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_EVCTRL_OFFSET           0x004        /**< \brief (TAL_EVCTRL offset) Event Control */
-#define TAL_EVCTRL_RESETVALUE       _U_(0x0000)  /**< \brief (TAL_EVCTRL reset_value) Event Control */
-
-#define TAL_EVCTRL_BRKEI_Pos        0            /**< \brief (TAL_EVCTRL) Break Input Event Enable */
-#define TAL_EVCTRL_BRKEI            (_U_(0x1) << TAL_EVCTRL_BRKEI_Pos)
-#define TAL_EVCTRL_BRKEO_Pos        1            /**< \brief (TAL_EVCTRL) Break Output Event Enable */
-#define TAL_EVCTRL_BRKEO            (_U_(0x1) << TAL_EVCTRL_BRKEO_Pos)
-#define TAL_EVCTRL_IRQMONEO0_Pos    2            /**< \brief (TAL_EVCTRL) Interrupt Request Monitor 0 Output Event Enable */
-#define TAL_EVCTRL_IRQMONEO0        (_U_(1) << TAL_EVCTRL_IRQMONEO0_Pos)
-#define TAL_EVCTRL_IRQMONEO_Pos     2            /**< \brief (TAL_EVCTRL) Interrupt Request Monitor x Output Event Enable */
-#define TAL_EVCTRL_IRQMONEO_Msk     (_U_(0x1) << TAL_EVCTRL_IRQMONEO_Pos)
-#define TAL_EVCTRL_IRQMONEO(value)  (TAL_EVCTRL_IRQMONEO_Msk & ((value) << TAL_EVCTRL_IRQMONEO_Pos))
-#define TAL_EVCTRL_MASK             _U_(0x0007)  /**< \brief (TAL_EVCTRL) MASK Register */
-
-/* -------- TAL_INTENCLR : (TAL Offset: 0x008) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  BRK:1;            /*!< bit:      0  Break Interrupt Enable             */
-    uint8_t  IPS0:1;           /*!< bit:      1  Inter-Processor Signal Interrupt Enable for CPU 0 */
-    uint8_t  IPS1:1;           /*!< bit:      2  Inter-Processor Signal Interrupt Enable for CPU 1 */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  IPS:2;            /*!< bit:  1.. 2  Inter-Processor Signal Interrupt Enable for CPU x */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTENCLR_OFFSET         0x008        /**< \brief (TAL_INTENCLR offset) Interrupt Enable Clear */
-#define TAL_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (TAL_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TAL_INTENCLR_BRK_Pos        0            /**< \brief (TAL_INTENCLR) Break Interrupt Enable */
-#define TAL_INTENCLR_BRK            (_U_(0x1) << TAL_INTENCLR_BRK_Pos)
-#define TAL_INTENCLR_IPS0_Pos       1            /**< \brief (TAL_INTENCLR) Inter-Processor Signal Interrupt Enable for CPU 0 */
-#define TAL_INTENCLR_IPS0           (_U_(1) << TAL_INTENCLR_IPS0_Pos)
-#define TAL_INTENCLR_IPS1_Pos       2            /**< \brief (TAL_INTENCLR) Inter-Processor Signal Interrupt Enable for CPU 1 */
-#define TAL_INTENCLR_IPS1           (_U_(1) << TAL_INTENCLR_IPS1_Pos)
-#define TAL_INTENCLR_IPS_Pos        1            /**< \brief (TAL_INTENCLR) Inter-Processor Signal Interrupt Enable for CPU x */
-#define TAL_INTENCLR_IPS_Msk        (_U_(0x3) << TAL_INTENCLR_IPS_Pos)
-#define TAL_INTENCLR_IPS(value)     (TAL_INTENCLR_IPS_Msk & ((value) << TAL_INTENCLR_IPS_Pos))
-#define TAL_INTENCLR_MASK           _U_(0x07)    /**< \brief (TAL_INTENCLR) MASK Register */
-
-/* -------- TAL_INTENSET : (TAL Offset: 0x009) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  BRK:1;            /*!< bit:      0  Break Interrupt Enable             */
-    uint8_t  IPS0:1;           /*!< bit:      1  Inter-Processor Signal Interrupt Enable for CPU 0 */
-    uint8_t  IPS1:1;           /*!< bit:      2  Inter-Processor Signal Interrupt Enable for CPU 1 */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  IPS:2;            /*!< bit:  1.. 2  Inter-Processor Signal Interrupt Enable for CPU x */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTENSET_OFFSET         0x009        /**< \brief (TAL_INTENSET offset) Interrupt Enable Set */
-#define TAL_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (TAL_INTENSET reset_value) Interrupt Enable Set */
-
-#define TAL_INTENSET_BRK_Pos        0            /**< \brief (TAL_INTENSET) Break Interrupt Enable */
-#define TAL_INTENSET_BRK            (_U_(0x1) << TAL_INTENSET_BRK_Pos)
-#define TAL_INTENSET_IPS0_Pos       1            /**< \brief (TAL_INTENSET) Inter-Processor Signal Interrupt Enable for CPU 0 */
-#define TAL_INTENSET_IPS0           (_U_(1) << TAL_INTENSET_IPS0_Pos)
-#define TAL_INTENSET_IPS1_Pos       2            /**< \brief (TAL_INTENSET) Inter-Processor Signal Interrupt Enable for CPU 1 */
-#define TAL_INTENSET_IPS1           (_U_(1) << TAL_INTENSET_IPS1_Pos)
-#define TAL_INTENSET_IPS_Pos        1            /**< \brief (TAL_INTENSET) Inter-Processor Signal Interrupt Enable for CPU x */
-#define TAL_INTENSET_IPS_Msk        (_U_(0x3) << TAL_INTENSET_IPS_Pos)
-#define TAL_INTENSET_IPS(value)     (TAL_INTENSET_IPS_Msk & ((value) << TAL_INTENSET_IPS_Pos))
-#define TAL_INTENSET_MASK           _U_(0x07)    /**< \brief (TAL_INTENSET) MASK Register */
-
-/* -------- TAL_INTFLAG : (TAL Offset: 0x00A) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  BRK:1;            /*!< bit:      0  Break                              */
-    __I uint8_t  IPS0:1;           /*!< bit:      1  Inter-Processor Signal for CPU 0   */
-    __I uint8_t  IPS1:1;           /*!< bit:      2  Inter-Processor Signal for CPU 1   */
-    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    __I uint8_t  IPS:2;            /*!< bit:  1.. 2  Inter-Processor Signal for CPU x   */
-    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTFLAG_OFFSET          0x00A        /**< \brief (TAL_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TAL_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (TAL_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TAL_INTFLAG_BRK_Pos         0            /**< \brief (TAL_INTFLAG) Break */
-#define TAL_INTFLAG_BRK             (_U_(0x1) << TAL_INTFLAG_BRK_Pos)
-#define TAL_INTFLAG_IPS0_Pos        1            /**< \brief (TAL_INTFLAG) Inter-Processor Signal for CPU 0 */
-#define TAL_INTFLAG_IPS0            (_U_(1) << TAL_INTFLAG_IPS0_Pos)
-#define TAL_INTFLAG_IPS1_Pos        2            /**< \brief (TAL_INTFLAG) Inter-Processor Signal for CPU 1 */
-#define TAL_INTFLAG_IPS1            (_U_(1) << TAL_INTFLAG_IPS1_Pos)
-#define TAL_INTFLAG_IPS_Pos         1            /**< \brief (TAL_INTFLAG) Inter-Processor Signal for CPU x */
-#define TAL_INTFLAG_IPS_Msk         (_U_(0x3) << TAL_INTFLAG_IPS_Pos)
-#define TAL_INTFLAG_IPS(value)      (TAL_INTFLAG_IPS_Msk & ((value) << TAL_INTFLAG_IPS_Pos))
-#define TAL_INTFLAG_MASK            _U_(0x07)    /**< \brief (TAL_INTFLAG) MASK Register */
-
-/* -------- TAL_GLOBMASK : (TAL Offset: 0x00B) (R/W  8) Global Break Requests Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CPU0:1;           /*!< bit:      0  CPU 0 Break Master                 */
-    uint8_t  CPU1:1;           /*!< bit:      1  CPU 1 Break Master                 */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  EVBRK:1;          /*!< bit:      6  Event Break Master                 */
-    uint8_t  EXTBRK:1;         /*!< bit:      7  External Break Master              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  CPU:2;            /*!< bit:  0.. 1  CPU x Break Master                 */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_GLOBMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_GLOBMASK_OFFSET         0x00B        /**< \brief (TAL_GLOBMASK offset) Global Break Requests Mask */
-#define TAL_GLOBMASK_RESETVALUE     _U_(0x00)    /**< \brief (TAL_GLOBMASK reset_value) Global Break Requests Mask */
-
-#define TAL_GLOBMASK_CPU0_Pos       0            /**< \brief (TAL_GLOBMASK) CPU 0 Break Master */
-#define TAL_GLOBMASK_CPU0           (_U_(1) << TAL_GLOBMASK_CPU0_Pos)
-#define TAL_GLOBMASK_CPU1_Pos       1            /**< \brief (TAL_GLOBMASK) CPU 1 Break Master */
-#define TAL_GLOBMASK_CPU1           (_U_(1) << TAL_GLOBMASK_CPU1_Pos)
-#define TAL_GLOBMASK_CPU_Pos        0            /**< \brief (TAL_GLOBMASK) CPU x Break Master */
-#define TAL_GLOBMASK_CPU_Msk        (_U_(0x3) << TAL_GLOBMASK_CPU_Pos)
-#define TAL_GLOBMASK_CPU(value)     (TAL_GLOBMASK_CPU_Msk & ((value) << TAL_GLOBMASK_CPU_Pos))
-#define TAL_GLOBMASK_EVBRK_Pos      6            /**< \brief (TAL_GLOBMASK) Event Break Master */
-#define TAL_GLOBMASK_EVBRK          (_U_(0x1) << TAL_GLOBMASK_EVBRK_Pos)
-#define TAL_GLOBMASK_EXTBRK_Pos     7            /**< \brief (TAL_GLOBMASK) External Break Master */
-#define TAL_GLOBMASK_EXTBRK         (_U_(0x1) << TAL_GLOBMASK_EXTBRK_Pos)
-#define TAL_GLOBMASK_MASK           _U_(0xC3)    /**< \brief (TAL_GLOBMASK) MASK Register */
-
-/* -------- TAL_HALT : (TAL Offset: 0x00C) ( /W  8) Debug Halt Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CPU0:1;           /*!< bit:      0  CPU 0 Break Master                 */
-    uint8_t  CPU1:1;           /*!< bit:      1  CPU 1 Break Master                 */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  EVBRK:1;          /*!< bit:      6  Event Break Master                 */
-    uint8_t  EXTBRK:1;         /*!< bit:      7  External Break Master              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  CPU:2;            /*!< bit:  0.. 1  CPU x Break Master                 */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_HALT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_HALT_OFFSET             0x00C        /**< \brief (TAL_HALT offset) Debug Halt Request */
-#define TAL_HALT_RESETVALUE         _U_(0x00)    /**< \brief (TAL_HALT reset_value) Debug Halt Request */
-
-#define TAL_HALT_CPU0_Pos           0            /**< \brief (TAL_HALT) CPU 0 Break Master */
-#define TAL_HALT_CPU0               (_U_(1) << TAL_HALT_CPU0_Pos)
-#define TAL_HALT_CPU1_Pos           1            /**< \brief (TAL_HALT) CPU 1 Break Master */
-#define TAL_HALT_CPU1               (_U_(1) << TAL_HALT_CPU1_Pos)
-#define TAL_HALT_CPU_Pos            0            /**< \brief (TAL_HALT) CPU x Break Master */
-#define TAL_HALT_CPU_Msk            (_U_(0x3) << TAL_HALT_CPU_Pos)
-#define TAL_HALT_CPU(value)         (TAL_HALT_CPU_Msk & ((value) << TAL_HALT_CPU_Pos))
-#define TAL_HALT_EVBRK_Pos          6            /**< \brief (TAL_HALT) Event Break Master */
-#define TAL_HALT_EVBRK              (_U_(0x1) << TAL_HALT_EVBRK_Pos)
-#define TAL_HALT_EXTBRK_Pos         7            /**< \brief (TAL_HALT) External Break Master */
-#define TAL_HALT_EXTBRK             (_U_(0x1) << TAL_HALT_EXTBRK_Pos)
-#define TAL_HALT_MASK               _U_(0xC3)    /**< \brief (TAL_HALT) MASK Register */
-
-/* -------- TAL_RESTART : (TAL Offset: 0x00D) ( /W  8) Debug Restart Request -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CPU0:1;           /*!< bit:      0  CPU 0 Break Master                 */
-    uint8_t  CPU1:1;           /*!< bit:      1  CPU 1 Break Master                 */
-    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
-    uint8_t  EXTBRK:1;         /*!< bit:      7  External Break Master              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  CPU:2;            /*!< bit:  0.. 1  CPU x Break Master                 */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_RESTART_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_RESTART_OFFSET          0x00D        /**< \brief (TAL_RESTART offset) Debug Restart Request */
-#define TAL_RESTART_RESETVALUE      _U_(0x00)    /**< \brief (TAL_RESTART reset_value) Debug Restart Request */
-
-#define TAL_RESTART_CPU0_Pos        0            /**< \brief (TAL_RESTART) CPU 0 Break Master */
-#define TAL_RESTART_CPU0            (_U_(1) << TAL_RESTART_CPU0_Pos)
-#define TAL_RESTART_CPU1_Pos        1            /**< \brief (TAL_RESTART) CPU 1 Break Master */
-#define TAL_RESTART_CPU1            (_U_(1) << TAL_RESTART_CPU1_Pos)
-#define TAL_RESTART_CPU_Pos         0            /**< \brief (TAL_RESTART) CPU x Break Master */
-#define TAL_RESTART_CPU_Msk         (_U_(0x3) << TAL_RESTART_CPU_Pos)
-#define TAL_RESTART_CPU(value)      (TAL_RESTART_CPU_Msk & ((value) << TAL_RESTART_CPU_Pos))
-#define TAL_RESTART_EXTBRK_Pos      7            /**< \brief (TAL_RESTART) External Break Master */
-#define TAL_RESTART_EXTBRK          (_U_(0x1) << TAL_RESTART_EXTBRK_Pos)
-#define TAL_RESTART_MASK            _U_(0x83)    /**< \brief (TAL_RESTART) MASK Register */
-
-/* -------- TAL_BRKSTATUS : (TAL Offset: 0x00E) (R/  16) Break Request Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CPU0:2;           /*!< bit:  0.. 1  CPU 0 Break Request                */
-    uint16_t CPU1:2;           /*!< bit:  2.. 3  CPU 1 Break Request                */
-    uint16_t :8;               /*!< bit:  4..11  Reserved                           */
-    uint16_t EVBRK:2;          /*!< bit: 12..13  Event Break Request                */
-    uint16_t EXTBRK:2;         /*!< bit: 14..15  External Break Request             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TAL_BRKSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_BRKSTATUS_OFFSET        0x00E        /**< \brief (TAL_BRKSTATUS offset) Break Request Status */
-#define TAL_BRKSTATUS_RESETVALUE    _U_(0x0000)  /**< \brief (TAL_BRKSTATUS reset_value) Break Request Status */
-
-#define TAL_BRKSTATUS_CPU0_Pos      0            /**< \brief (TAL_BRKSTATUS) CPU 0 Break Request */
-#define TAL_BRKSTATUS_CPU0_Msk      (_U_(0x3) << TAL_BRKSTATUS_CPU0_Pos)
-#define TAL_BRKSTATUS_CPU0(value)   (TAL_BRKSTATUS_CPU0_Msk & ((value) << TAL_BRKSTATUS_CPU0_Pos))
-#define TAL_BRKSTATUS_CPU1_Pos      2            /**< \brief (TAL_BRKSTATUS) CPU 1 Break Request */
-#define TAL_BRKSTATUS_CPU1_Msk      (_U_(0x3) << TAL_BRKSTATUS_CPU1_Pos)
-#define TAL_BRKSTATUS_CPU1(value)   (TAL_BRKSTATUS_CPU1_Msk & ((value) << TAL_BRKSTATUS_CPU1_Pos))
-#define TAL_BRKSTATUS_EVBRK_Pos     12           /**< \brief (TAL_BRKSTATUS) Event Break Request */
-#define TAL_BRKSTATUS_EVBRK_Msk     (_U_(0x3) << TAL_BRKSTATUS_EVBRK_Pos)
-#define TAL_BRKSTATUS_EVBRK(value)  (TAL_BRKSTATUS_EVBRK_Msk & ((value) << TAL_BRKSTATUS_EVBRK_Pos))
-#define TAL_BRKSTATUS_EXTBRK_Pos    14           /**< \brief (TAL_BRKSTATUS) External Break Request */
-#define TAL_BRKSTATUS_EXTBRK_Msk    (_U_(0x3) << TAL_BRKSTATUS_EXTBRK_Pos)
-#define TAL_BRKSTATUS_EXTBRK(value) (TAL_BRKSTATUS_EXTBRK_Msk & ((value) << TAL_BRKSTATUS_EXTBRK_Pos))
-#define TAL_BRKSTATUS_MASK          _U_(0xF00F)  /**< \brief (TAL_BRKSTATUS) MASK Register */
-
-/* -------- TAL_CTICTRLA : (TAL Offset: 0x010) (R/W  8) CTIS Cross-Trigger Interface n Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  BRK:2;            /*!< bit:  0.. 1  Action when global break issued    */
-    uint8_t  RESTART:1;        /*!< bit:      2  Action when global restart issued  */
-    uint8_t  IPS:1;            /*!< bit:      3  Action when inter-process resource freed */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_CTICTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_CTICTRLA_OFFSET         0x010        /**< \brief (TAL_CTICTRLA offset) Cross-Trigger Interface n Control A */
-#define TAL_CTICTRLA_RESETVALUE     _U_(0x00)    /**< \brief (TAL_CTICTRLA reset_value) Cross-Trigger Interface n Control A */
-
-#define TAL_CTICTRLA_BRK_Pos        0            /**< \brief (TAL_CTICTRLA) Action when global break issued */
-#define TAL_CTICTRLA_BRK_Msk        (_U_(0x3) << TAL_CTICTRLA_BRK_Pos)
-#define TAL_CTICTRLA_BRK(value)     (TAL_CTICTRLA_BRK_Msk & ((value) << TAL_CTICTRLA_BRK_Pos))
-#define   TAL_CTICTRLA_BRK_BREAK_Val      _U_(0x0)   /**< \brief (TAL_CTICTRLA) Break when requested */
-#define   TAL_CTICTRLA_BRK_INTERRUPT_Val  _U_(0x1)   /**< \brief (TAL_CTICTRLA) Trigger DBG interrupt instead of break */
-#define   TAL_CTICTRLA_BRK_IGNORE_Val     _U_(0x2)   /**< \brief (TAL_CTICTRLA) Ignore break request */
-#define TAL_CTICTRLA_BRK_BREAK      (TAL_CTICTRLA_BRK_BREAK_Val    << TAL_CTICTRLA_BRK_Pos)
-#define TAL_CTICTRLA_BRK_INTERRUPT  (TAL_CTICTRLA_BRK_INTERRUPT_Val << TAL_CTICTRLA_BRK_Pos)
-#define TAL_CTICTRLA_BRK_IGNORE     (TAL_CTICTRLA_BRK_IGNORE_Val   << TAL_CTICTRLA_BRK_Pos)
-#define TAL_CTICTRLA_RESTART_Pos    2            /**< \brief (TAL_CTICTRLA) Action when global restart issued */
-#define TAL_CTICTRLA_RESTART        (_U_(0x1) << TAL_CTICTRLA_RESTART_Pos)
-#define   TAL_CTICTRLA_RESTART_RESTART_Val _U_(0x0)   /**< \brief (TAL_CTICTRLA) Restart when requested */
-#define   TAL_CTICTRLA_RESTART_IGNORE_Val _U_(0x1)   /**< \brief (TAL_CTICTRLA) Ignore restart request */
-#define TAL_CTICTRLA_RESTART_RESTART (TAL_CTICTRLA_RESTART_RESTART_Val << TAL_CTICTRLA_RESTART_Pos)
-#define TAL_CTICTRLA_RESTART_IGNORE (TAL_CTICTRLA_RESTART_IGNORE_Val << TAL_CTICTRLA_RESTART_Pos)
-#define TAL_CTICTRLA_IPS_Pos        3            /**< \brief (TAL_CTICTRLA) Action when inter-process resource freed */
-#define TAL_CTICTRLA_IPS            (_U_(0x1) << TAL_CTICTRLA_IPS_Pos)
-#define   TAL_CTICTRLA_IPS_EVENT_Val      _U_(0x0)   /**< \brief (TAL_CTICTRLA) Generate CPU Event when awaited resource is freed. */
-#define   TAL_CTICTRLA_IPS_INTERRUPT_Val  _U_(0x1)   /**< \brief (TAL_CTICTRLA) Generate Interrupt when awaited resource is freed. */
-#define TAL_CTICTRLA_IPS_EVENT      (TAL_CTICTRLA_IPS_EVENT_Val    << TAL_CTICTRLA_IPS_Pos)
-#define TAL_CTICTRLA_IPS_INTERRUPT  (TAL_CTICTRLA_IPS_INTERRUPT_Val << TAL_CTICTRLA_IPS_Pos)
-#define TAL_CTICTRLA_MASK           _U_(0x0F)    /**< \brief (TAL_CTICTRLA) MASK Register */
-
-/* -------- TAL_CTIMASK : (TAL Offset: 0x011) (R/W  8) CTIS Cross-Trigger Interface n Mask -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CPU0:1;           /*!< bit:      0  CPU 0 Break Master                 */
-    uint8_t  CPU1:1;           /*!< bit:      1  CPU 1 Break Master                 */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  EVBRK:1;          /*!< bit:      6  Event Break Master                 */
-    uint8_t  EXTBRK:1;         /*!< bit:      7  External Break Master              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  CPU:2;            /*!< bit:  0.. 1  CPU x Break Master                 */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_CTIMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_CTIMASK_OFFSET          0x011        /**< \brief (TAL_CTIMASK offset) Cross-Trigger Interface n Mask */
-#define TAL_CTIMASK_RESETVALUE      _U_(0x00)    /**< \brief (TAL_CTIMASK reset_value) Cross-Trigger Interface n Mask */
-
-#define TAL_CTIMASK_CPU0_Pos        0            /**< \brief (TAL_CTIMASK) CPU 0 Break Master */
-#define TAL_CTIMASK_CPU0            (_U_(1) << TAL_CTIMASK_CPU0_Pos)
-#define TAL_CTIMASK_CPU1_Pos        1            /**< \brief (TAL_CTIMASK) CPU 1 Break Master */
-#define TAL_CTIMASK_CPU1            (_U_(1) << TAL_CTIMASK_CPU1_Pos)
-#define TAL_CTIMASK_CPU_Pos         0            /**< \brief (TAL_CTIMASK) CPU x Break Master */
-#define TAL_CTIMASK_CPU_Msk         (_U_(0x3) << TAL_CTIMASK_CPU_Pos)
-#define TAL_CTIMASK_CPU(value)      (TAL_CTIMASK_CPU_Msk & ((value) << TAL_CTIMASK_CPU_Pos))
-#define TAL_CTIMASK_EVBRK_Pos       6            /**< \brief (TAL_CTIMASK) Event Break Master */
-#define TAL_CTIMASK_EVBRK           (_U_(0x1) << TAL_CTIMASK_EVBRK_Pos)
-#define TAL_CTIMASK_EXTBRK_Pos      7            /**< \brief (TAL_CTIMASK) External Break Master */
-#define TAL_CTIMASK_EXTBRK          (_U_(0x1) << TAL_CTIMASK_EXTBRK_Pos)
-#define TAL_CTIMASK_MASK            _U_(0xC3)    /**< \brief (TAL_CTIMASK) MASK Register */
-
-/* -------- TAL_INTSTATUS : (TAL Offset: 0x020) (R/   8) Interrupt n Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  IRQ0:1;           /*!< bit:      0  Interrupt Status for Interrupt Request 0 within Interrupt n */
-    uint8_t  IRQ1:1;           /*!< bit:      1  Interrupt Status for Interrupt Request 1 within Interrupt n */
-    uint8_t  IRQ2:1;           /*!< bit:      2  Interrupt Status for Interrupt Request 2 within Interrupt n */
-    uint8_t  IRQ3:1;           /*!< bit:      3  Interrupt Status for Interrupt Request 3 within Interrupt n */
-    uint8_t  IRQ4:1;           /*!< bit:      4  Interrupt Status for Interrupt Request 4 within Interrupt n */
-    uint8_t  IRQ5:1;           /*!< bit:      5  Interrupt Status for Interrupt Request 5 within Interrupt n */
-    uint8_t  IRQ6:1;           /*!< bit:      6  Interrupt Status for Interrupt Request 6 within Interrupt n */
-    uint8_t  IRQ7:1;           /*!< bit:      7  Interrupt Status for Interrupt Request 7 within Interrupt n */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  IRQ:8;            /*!< bit:  0.. 7  Interrupt Status for Interrupt Request x within Interrupt n */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_INTSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTSTATUS_OFFSET        0x020        /**< \brief (TAL_INTSTATUS offset) Interrupt n Status */
-#define TAL_INTSTATUS_RESETVALUE    _U_(0x00)    /**< \brief (TAL_INTSTATUS reset_value) Interrupt n Status */
-
-#define TAL_INTSTATUS_IRQ0_Pos      0            /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 0 within Interrupt n */
-#define TAL_INTSTATUS_IRQ0          (_U_(1) << TAL_INTSTATUS_IRQ0_Pos)
-#define TAL_INTSTATUS_IRQ1_Pos      1            /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 1 within Interrupt n */
-#define TAL_INTSTATUS_IRQ1          (_U_(1) << TAL_INTSTATUS_IRQ1_Pos)
-#define TAL_INTSTATUS_IRQ2_Pos      2            /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 2 within Interrupt n */
-#define TAL_INTSTATUS_IRQ2          (_U_(1) << TAL_INTSTATUS_IRQ2_Pos)
-#define TAL_INTSTATUS_IRQ3_Pos      3            /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 3 within Interrupt n */
-#define TAL_INTSTATUS_IRQ3          (_U_(1) << TAL_INTSTATUS_IRQ3_Pos)
-#define TAL_INTSTATUS_IRQ4_Pos      4            /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 4 within Interrupt n */
-#define TAL_INTSTATUS_IRQ4          (_U_(1) << TAL_INTSTATUS_IRQ4_Pos)
-#define TAL_INTSTATUS_IRQ5_Pos      5            /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 5 within Interrupt n */
-#define TAL_INTSTATUS_IRQ5          (_U_(1) << TAL_INTSTATUS_IRQ5_Pos)
-#define TAL_INTSTATUS_IRQ6_Pos      6            /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 6 within Interrupt n */
-#define TAL_INTSTATUS_IRQ6          (_U_(1) << TAL_INTSTATUS_IRQ6_Pos)
-#define TAL_INTSTATUS_IRQ7_Pos      7            /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 7 within Interrupt n */
-#define TAL_INTSTATUS_IRQ7          (_U_(1) << TAL_INTSTATUS_IRQ7_Pos)
-#define TAL_INTSTATUS_IRQ_Pos       0            /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request x within Interrupt n */
-#define TAL_INTSTATUS_IRQ_Msk       (_U_(0xFF) << TAL_INTSTATUS_IRQ_Pos)
-#define TAL_INTSTATUS_IRQ(value)    (TAL_INTSTATUS_IRQ_Msk & ((value) << TAL_INTSTATUS_IRQ_Pos))
-#define TAL_INTSTATUS_MASK          _U_(0xFF)    /**< \brief (TAL_INTSTATUS) MASK Register */
-
-/* -------- TAL_DMACPUSEL0 : (TAL Offset: 0x110) (R/W 32) DMA Channel Interrupts CPU Select 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CH0:1;            /*!< bit:      0  DMA Channel 0 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t CH1:1;            /*!< bit:      2  DMA Channel 1 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t CH2:1;            /*!< bit:      4  DMA Channel 2 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t CH3:1;            /*!< bit:      6  DMA Channel 3 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t CH4:1;            /*!< bit:      8  DMA Channel 4 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t CH5:1;            /*!< bit:     10  DMA Channel 5 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t CH6:1;            /*!< bit:     12  DMA Channel 6 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     13  Reserved                           */
-    uint32_t CH7:1;            /*!< bit:     14  DMA Channel 7 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t CH8:1;            /*!< bit:     16  DMA Channel 8 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     17  Reserved                           */
-    uint32_t CH9:1;            /*!< bit:     18  DMA Channel 9 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t CH10:1;           /*!< bit:     20  DMA Channel 10 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     21  Reserved                           */
-    uint32_t CH11:1;           /*!< bit:     22  DMA Channel 11 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t CH12:1;           /*!< bit:     24  DMA Channel 12 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     25  Reserved                           */
-    uint32_t CH13:1;           /*!< bit:     26  DMA Channel 13 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     27  Reserved                           */
-    uint32_t CH14:1;           /*!< bit:     28  DMA Channel 14 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     29  Reserved                           */
-    uint32_t CH15:1;           /*!< bit:     30  DMA Channel 15 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_DMACPUSEL0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_DMACPUSEL0_OFFSET       0x110        /**< \brief (TAL_DMACPUSEL0 offset) DMA Channel Interrupts CPU Select 0 */
-#define TAL_DMACPUSEL0_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_DMACPUSEL0 reset_value) DMA Channel Interrupts CPU Select 0 */
-
-#define TAL_DMACPUSEL0_CH0_Pos      0            /**< \brief (TAL_DMACPUSEL0) DMA Channel 0 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH0_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH0_Pos)
-#define TAL_DMACPUSEL0_CH0(value)   (TAL_DMACPUSEL0_CH0_Msk & ((value) << TAL_DMACPUSEL0_CH0_Pos))
-#define TAL_DMACPUSEL0_CH1_Pos      2            /**< \brief (TAL_DMACPUSEL0) DMA Channel 1 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH1_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH1_Pos)
-#define TAL_DMACPUSEL0_CH1(value)   (TAL_DMACPUSEL0_CH1_Msk & ((value) << TAL_DMACPUSEL0_CH1_Pos))
-#define TAL_DMACPUSEL0_CH2_Pos      4            /**< \brief (TAL_DMACPUSEL0) DMA Channel 2 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH2_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH2_Pos)
-#define TAL_DMACPUSEL0_CH2(value)   (TAL_DMACPUSEL0_CH2_Msk & ((value) << TAL_DMACPUSEL0_CH2_Pos))
-#define TAL_DMACPUSEL0_CH3_Pos      6            /**< \brief (TAL_DMACPUSEL0) DMA Channel 3 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH3_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH3_Pos)
-#define TAL_DMACPUSEL0_CH3(value)   (TAL_DMACPUSEL0_CH3_Msk & ((value) << TAL_DMACPUSEL0_CH3_Pos))
-#define TAL_DMACPUSEL0_CH4_Pos      8            /**< \brief (TAL_DMACPUSEL0) DMA Channel 4 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH4_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH4_Pos)
-#define TAL_DMACPUSEL0_CH4(value)   (TAL_DMACPUSEL0_CH4_Msk & ((value) << TAL_DMACPUSEL0_CH4_Pos))
-#define TAL_DMACPUSEL0_CH5_Pos      10           /**< \brief (TAL_DMACPUSEL0) DMA Channel 5 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH5_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH5_Pos)
-#define TAL_DMACPUSEL0_CH5(value)   (TAL_DMACPUSEL0_CH5_Msk & ((value) << TAL_DMACPUSEL0_CH5_Pos))
-#define TAL_DMACPUSEL0_CH6_Pos      12           /**< \brief (TAL_DMACPUSEL0) DMA Channel 6 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH6_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH6_Pos)
-#define TAL_DMACPUSEL0_CH6(value)   (TAL_DMACPUSEL0_CH6_Msk & ((value) << TAL_DMACPUSEL0_CH6_Pos))
-#define TAL_DMACPUSEL0_CH7_Pos      14           /**< \brief (TAL_DMACPUSEL0) DMA Channel 7 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH7_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH7_Pos)
-#define TAL_DMACPUSEL0_CH7(value)   (TAL_DMACPUSEL0_CH7_Msk & ((value) << TAL_DMACPUSEL0_CH7_Pos))
-#define TAL_DMACPUSEL0_CH8_Pos      16           /**< \brief (TAL_DMACPUSEL0) DMA Channel 8 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH8_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH8_Pos)
-#define TAL_DMACPUSEL0_CH8(value)   (TAL_DMACPUSEL0_CH8_Msk & ((value) << TAL_DMACPUSEL0_CH8_Pos))
-#define TAL_DMACPUSEL0_CH9_Pos      18           /**< \brief (TAL_DMACPUSEL0) DMA Channel 9 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH9_Msk      (_U_(0x1) << TAL_DMACPUSEL0_CH9_Pos)
-#define TAL_DMACPUSEL0_CH9(value)   (TAL_DMACPUSEL0_CH9_Msk & ((value) << TAL_DMACPUSEL0_CH9_Pos))
-#define TAL_DMACPUSEL0_CH10_Pos     20           /**< \brief (TAL_DMACPUSEL0) DMA Channel 10 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH10_Msk     (_U_(0x1) << TAL_DMACPUSEL0_CH10_Pos)
-#define TAL_DMACPUSEL0_CH10(value)  (TAL_DMACPUSEL0_CH10_Msk & ((value) << TAL_DMACPUSEL0_CH10_Pos))
-#define TAL_DMACPUSEL0_CH11_Pos     22           /**< \brief (TAL_DMACPUSEL0) DMA Channel 11 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH11_Msk     (_U_(0x1) << TAL_DMACPUSEL0_CH11_Pos)
-#define TAL_DMACPUSEL0_CH11(value)  (TAL_DMACPUSEL0_CH11_Msk & ((value) << TAL_DMACPUSEL0_CH11_Pos))
-#define TAL_DMACPUSEL0_CH12_Pos     24           /**< \brief (TAL_DMACPUSEL0) DMA Channel 12 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH12_Msk     (_U_(0x1) << TAL_DMACPUSEL0_CH12_Pos)
-#define TAL_DMACPUSEL0_CH12(value)  (TAL_DMACPUSEL0_CH12_Msk & ((value) << TAL_DMACPUSEL0_CH12_Pos))
-#define TAL_DMACPUSEL0_CH13_Pos     26           /**< \brief (TAL_DMACPUSEL0) DMA Channel 13 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH13_Msk     (_U_(0x1) << TAL_DMACPUSEL0_CH13_Pos)
-#define TAL_DMACPUSEL0_CH13(value)  (TAL_DMACPUSEL0_CH13_Msk & ((value) << TAL_DMACPUSEL0_CH13_Pos))
-#define TAL_DMACPUSEL0_CH14_Pos     28           /**< \brief (TAL_DMACPUSEL0) DMA Channel 14 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH14_Msk     (_U_(0x1) << TAL_DMACPUSEL0_CH14_Pos)
-#define TAL_DMACPUSEL0_CH14(value)  (TAL_DMACPUSEL0_CH14_Msk & ((value) << TAL_DMACPUSEL0_CH14_Pos))
-#define TAL_DMACPUSEL0_CH15_Pos     30           /**< \brief (TAL_DMACPUSEL0) DMA Channel 15 Interrupt CPU Select */
-#define TAL_DMACPUSEL0_CH15_Msk     (_U_(0x1) << TAL_DMACPUSEL0_CH15_Pos)
-#define TAL_DMACPUSEL0_CH15(value)  (TAL_DMACPUSEL0_CH15_Msk & ((value) << TAL_DMACPUSEL0_CH15_Pos))
-#define TAL_DMACPUSEL0_MASK         _U_(0x55555555) /**< \brief (TAL_DMACPUSEL0) MASK Register */
-
-/* -------- TAL_DMACPUSEL1 : (TAL Offset: 0x114) (R/W 32) DMA Channel Interrupts CPU Select 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CH16:1;           /*!< bit:      0  DMA Channel 16 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t CH17:1;           /*!< bit:      2  DMA Channel 17 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t CH18:1;           /*!< bit:      4  DMA Channel 18 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t CH19:1;           /*!< bit:      6  DMA Channel 19 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t CH20:1;           /*!< bit:      8  DMA Channel 20 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t CH21:1;           /*!< bit:     10  DMA Channel 21 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t CH22:1;           /*!< bit:     12  DMA Channel 22 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     13  Reserved                           */
-    uint32_t CH23:1;           /*!< bit:     14  DMA Channel 23 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t CH24:1;           /*!< bit:     16  DMA Channel 24 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     17  Reserved                           */
-    uint32_t CH25:1;           /*!< bit:     18  DMA Channel 25 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t CH26:1;           /*!< bit:     20  DMA Channel 26 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     21  Reserved                           */
-    uint32_t CH27:1;           /*!< bit:     22  DMA Channel 27 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t CH28:1;           /*!< bit:     24  DMA Channel 28 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     25  Reserved                           */
-    uint32_t CH29:1;           /*!< bit:     26  DMA Channel 29 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     27  Reserved                           */
-    uint32_t CH30:1;           /*!< bit:     28  DMA Channel 30 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     29  Reserved                           */
-    uint32_t CH31:1;           /*!< bit:     30  DMA Channel 31 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_DMACPUSEL1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_DMACPUSEL1_OFFSET       0x114        /**< \brief (TAL_DMACPUSEL1 offset) DMA Channel Interrupts CPU Select 1 */
-#define TAL_DMACPUSEL1_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_DMACPUSEL1 reset_value) DMA Channel Interrupts CPU Select 1 */
-
-#define TAL_DMACPUSEL1_CH16_Pos     0            /**< \brief (TAL_DMACPUSEL1) DMA Channel 16 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH16_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH16_Pos)
-#define TAL_DMACPUSEL1_CH16(value)  (TAL_DMACPUSEL1_CH16_Msk & ((value) << TAL_DMACPUSEL1_CH16_Pos))
-#define TAL_DMACPUSEL1_CH17_Pos     2            /**< \brief (TAL_DMACPUSEL1) DMA Channel 17 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH17_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH17_Pos)
-#define TAL_DMACPUSEL1_CH17(value)  (TAL_DMACPUSEL1_CH17_Msk & ((value) << TAL_DMACPUSEL1_CH17_Pos))
-#define TAL_DMACPUSEL1_CH18_Pos     4            /**< \brief (TAL_DMACPUSEL1) DMA Channel 18 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH18_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH18_Pos)
-#define TAL_DMACPUSEL1_CH18(value)  (TAL_DMACPUSEL1_CH18_Msk & ((value) << TAL_DMACPUSEL1_CH18_Pos))
-#define TAL_DMACPUSEL1_CH19_Pos     6            /**< \brief (TAL_DMACPUSEL1) DMA Channel 19 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH19_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH19_Pos)
-#define TAL_DMACPUSEL1_CH19(value)  (TAL_DMACPUSEL1_CH19_Msk & ((value) << TAL_DMACPUSEL1_CH19_Pos))
-#define TAL_DMACPUSEL1_CH20_Pos     8            /**< \brief (TAL_DMACPUSEL1) DMA Channel 20 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH20_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH20_Pos)
-#define TAL_DMACPUSEL1_CH20(value)  (TAL_DMACPUSEL1_CH20_Msk & ((value) << TAL_DMACPUSEL1_CH20_Pos))
-#define TAL_DMACPUSEL1_CH21_Pos     10           /**< \brief (TAL_DMACPUSEL1) DMA Channel 21 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH21_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH21_Pos)
-#define TAL_DMACPUSEL1_CH21(value)  (TAL_DMACPUSEL1_CH21_Msk & ((value) << TAL_DMACPUSEL1_CH21_Pos))
-#define TAL_DMACPUSEL1_CH22_Pos     12           /**< \brief (TAL_DMACPUSEL1) DMA Channel 22 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH22_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH22_Pos)
-#define TAL_DMACPUSEL1_CH22(value)  (TAL_DMACPUSEL1_CH22_Msk & ((value) << TAL_DMACPUSEL1_CH22_Pos))
-#define TAL_DMACPUSEL1_CH23_Pos     14           /**< \brief (TAL_DMACPUSEL1) DMA Channel 23 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH23_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH23_Pos)
-#define TAL_DMACPUSEL1_CH23(value)  (TAL_DMACPUSEL1_CH23_Msk & ((value) << TAL_DMACPUSEL1_CH23_Pos))
-#define TAL_DMACPUSEL1_CH24_Pos     16           /**< \brief (TAL_DMACPUSEL1) DMA Channel 24 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH24_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH24_Pos)
-#define TAL_DMACPUSEL1_CH24(value)  (TAL_DMACPUSEL1_CH24_Msk & ((value) << TAL_DMACPUSEL1_CH24_Pos))
-#define TAL_DMACPUSEL1_CH25_Pos     18           /**< \brief (TAL_DMACPUSEL1) DMA Channel 25 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH25_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH25_Pos)
-#define TAL_DMACPUSEL1_CH25(value)  (TAL_DMACPUSEL1_CH25_Msk & ((value) << TAL_DMACPUSEL1_CH25_Pos))
-#define TAL_DMACPUSEL1_CH26_Pos     20           /**< \brief (TAL_DMACPUSEL1) DMA Channel 26 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH26_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH26_Pos)
-#define TAL_DMACPUSEL1_CH26(value)  (TAL_DMACPUSEL1_CH26_Msk & ((value) << TAL_DMACPUSEL1_CH26_Pos))
-#define TAL_DMACPUSEL1_CH27_Pos     22           /**< \brief (TAL_DMACPUSEL1) DMA Channel 27 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH27_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH27_Pos)
-#define TAL_DMACPUSEL1_CH27(value)  (TAL_DMACPUSEL1_CH27_Msk & ((value) << TAL_DMACPUSEL1_CH27_Pos))
-#define TAL_DMACPUSEL1_CH28_Pos     24           /**< \brief (TAL_DMACPUSEL1) DMA Channel 28 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH28_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH28_Pos)
-#define TAL_DMACPUSEL1_CH28(value)  (TAL_DMACPUSEL1_CH28_Msk & ((value) << TAL_DMACPUSEL1_CH28_Pos))
-#define TAL_DMACPUSEL1_CH29_Pos     26           /**< \brief (TAL_DMACPUSEL1) DMA Channel 29 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH29_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH29_Pos)
-#define TAL_DMACPUSEL1_CH29(value)  (TAL_DMACPUSEL1_CH29_Msk & ((value) << TAL_DMACPUSEL1_CH29_Pos))
-#define TAL_DMACPUSEL1_CH30_Pos     28           /**< \brief (TAL_DMACPUSEL1) DMA Channel 30 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH30_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH30_Pos)
-#define TAL_DMACPUSEL1_CH30(value)  (TAL_DMACPUSEL1_CH30_Msk & ((value) << TAL_DMACPUSEL1_CH30_Pos))
-#define TAL_DMACPUSEL1_CH31_Pos     30           /**< \brief (TAL_DMACPUSEL1) DMA Channel 31 Interrupt CPU Select */
-#define TAL_DMACPUSEL1_CH31_Msk     (_U_(0x1) << TAL_DMACPUSEL1_CH31_Pos)
-#define TAL_DMACPUSEL1_CH31(value)  (TAL_DMACPUSEL1_CH31_Msk & ((value) << TAL_DMACPUSEL1_CH31_Pos))
-#define TAL_DMACPUSEL1_MASK         _U_(0x55555555) /**< \brief (TAL_DMACPUSEL1) MASK Register */
-
-/* -------- TAL_EVCPUSEL0 : (TAL Offset: 0x118) (R/W 32) EVSYS Channel Interrupts CPU Select 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CH0:1;            /*!< bit:      0  Event Channel 0 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t CH1:1;            /*!< bit:      2  Event Channel 1 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t CH2:1;            /*!< bit:      4  Event Channel 2 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t CH3:1;            /*!< bit:      6  Event Channel 3 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t CH4:1;            /*!< bit:      8  Event Channel 4 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t CH5:1;            /*!< bit:     10  Event Channel 5 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t CH6:1;            /*!< bit:     12  Event Channel 6 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     13  Reserved                           */
-    uint32_t CH7:1;            /*!< bit:     14  Event Channel 7 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t CH8:1;            /*!< bit:     16  Event Channel 8 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     17  Reserved                           */
-    uint32_t CH9:1;            /*!< bit:     18  Event Channel 9 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t CH10:1;           /*!< bit:     20  Event Channel 10 Interrupt CPU Select */
-    uint32_t :1;               /*!< bit:     21  Reserved                           */
-    uint32_t CH11:1;           /*!< bit:     22  Event Channel 11 Interrupt CPU Select */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_EVCPUSEL0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_EVCPUSEL0_OFFSET        0x118        /**< \brief (TAL_EVCPUSEL0 offset) EVSYS Channel Interrupts CPU Select 0 */
-#define TAL_EVCPUSEL0_RESETVALUE    _U_(0x00000000) /**< \brief (TAL_EVCPUSEL0 reset_value) EVSYS Channel Interrupts CPU Select 0 */
-
-#define TAL_EVCPUSEL0_CH0_Pos       0            /**< \brief (TAL_EVCPUSEL0) Event Channel 0 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH0_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH0_Pos)
-#define TAL_EVCPUSEL0_CH0(value)    (TAL_EVCPUSEL0_CH0_Msk & ((value) << TAL_EVCPUSEL0_CH0_Pos))
-#define TAL_EVCPUSEL0_CH1_Pos       2            /**< \brief (TAL_EVCPUSEL0) Event Channel 1 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH1_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH1_Pos)
-#define TAL_EVCPUSEL0_CH1(value)    (TAL_EVCPUSEL0_CH1_Msk & ((value) << TAL_EVCPUSEL0_CH1_Pos))
-#define TAL_EVCPUSEL0_CH2_Pos       4            /**< \brief (TAL_EVCPUSEL0) Event Channel 2 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH2_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH2_Pos)
-#define TAL_EVCPUSEL0_CH2(value)    (TAL_EVCPUSEL0_CH2_Msk & ((value) << TAL_EVCPUSEL0_CH2_Pos))
-#define TAL_EVCPUSEL0_CH3_Pos       6            /**< \brief (TAL_EVCPUSEL0) Event Channel 3 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH3_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH3_Pos)
-#define TAL_EVCPUSEL0_CH3(value)    (TAL_EVCPUSEL0_CH3_Msk & ((value) << TAL_EVCPUSEL0_CH3_Pos))
-#define TAL_EVCPUSEL0_CH4_Pos       8            /**< \brief (TAL_EVCPUSEL0) Event Channel 4 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH4_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH4_Pos)
-#define TAL_EVCPUSEL0_CH4(value)    (TAL_EVCPUSEL0_CH4_Msk & ((value) << TAL_EVCPUSEL0_CH4_Pos))
-#define TAL_EVCPUSEL0_CH5_Pos       10           /**< \brief (TAL_EVCPUSEL0) Event Channel 5 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH5_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH5_Pos)
-#define TAL_EVCPUSEL0_CH5(value)    (TAL_EVCPUSEL0_CH5_Msk & ((value) << TAL_EVCPUSEL0_CH5_Pos))
-#define TAL_EVCPUSEL0_CH6_Pos       12           /**< \brief (TAL_EVCPUSEL0) Event Channel 6 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH6_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH6_Pos)
-#define TAL_EVCPUSEL0_CH6(value)    (TAL_EVCPUSEL0_CH6_Msk & ((value) << TAL_EVCPUSEL0_CH6_Pos))
-#define TAL_EVCPUSEL0_CH7_Pos       14           /**< \brief (TAL_EVCPUSEL0) Event Channel 7 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH7_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH7_Pos)
-#define TAL_EVCPUSEL0_CH7(value)    (TAL_EVCPUSEL0_CH7_Msk & ((value) << TAL_EVCPUSEL0_CH7_Pos))
-#define TAL_EVCPUSEL0_CH8_Pos       16           /**< \brief (TAL_EVCPUSEL0) Event Channel 8 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH8_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH8_Pos)
-#define TAL_EVCPUSEL0_CH8(value)    (TAL_EVCPUSEL0_CH8_Msk & ((value) << TAL_EVCPUSEL0_CH8_Pos))
-#define TAL_EVCPUSEL0_CH9_Pos       18           /**< \brief (TAL_EVCPUSEL0) Event Channel 9 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH9_Msk       (_U_(0x1) << TAL_EVCPUSEL0_CH9_Pos)
-#define TAL_EVCPUSEL0_CH9(value)    (TAL_EVCPUSEL0_CH9_Msk & ((value) << TAL_EVCPUSEL0_CH9_Pos))
-#define TAL_EVCPUSEL0_CH10_Pos      20           /**< \brief (TAL_EVCPUSEL0) Event Channel 10 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH10_Msk      (_U_(0x1) << TAL_EVCPUSEL0_CH10_Pos)
-#define TAL_EVCPUSEL0_CH10(value)   (TAL_EVCPUSEL0_CH10_Msk & ((value) << TAL_EVCPUSEL0_CH10_Pos))
-#define TAL_EVCPUSEL0_CH11_Pos      22           /**< \brief (TAL_EVCPUSEL0) Event Channel 11 Interrupt CPU Select */
-#define TAL_EVCPUSEL0_CH11_Msk      (_U_(0x1) << TAL_EVCPUSEL0_CH11_Pos)
-#define TAL_EVCPUSEL0_CH11(value)   (TAL_EVCPUSEL0_CH11_Msk & ((value) << TAL_EVCPUSEL0_CH11_Pos))
-#define TAL_EVCPUSEL0_MASK          _U_(0x00555555) /**< \brief (TAL_EVCPUSEL0) MASK Register */
-
-/* -------- TAL_EICCPUSEL0 : (TAL Offset: 0x120) (R/W 32) EIC External Interrupts CPU Select 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0 CPU Select    */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t EXTINT1:1;        /*!< bit:      2  External Interrupt 1 CPU Select    */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t EXTINT2:1;        /*!< bit:      4  External Interrupt 2 CPU Select    */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t EXTINT3:1;        /*!< bit:      6  External Interrupt 3 CPU Select    */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t EXTINT4:1;        /*!< bit:      8  External Interrupt 4 CPU Select    */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t EXTINT5:1;        /*!< bit:     10  External Interrupt 5 CPU Select    */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t EXTINT6:1;        /*!< bit:     12  External Interrupt 6 CPU Select    */
-    uint32_t :1;               /*!< bit:     13  Reserved                           */
-    uint32_t EXTINT7:1;        /*!< bit:     14  External Interrupt 7 CPU Select    */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t EXTINT8:1;        /*!< bit:     16  External Interrupt 8 CPU Select    */
-    uint32_t :1;               /*!< bit:     17  Reserved                           */
-    uint32_t EXTINT9:1;        /*!< bit:     18  External Interrupt 9 CPU Select    */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t EXTINT10:1;       /*!< bit:     20  External Interrupt 10 CPU Select   */
-    uint32_t :1;               /*!< bit:     21  Reserved                           */
-    uint32_t EXTINT11:1;       /*!< bit:     22  External Interrupt 11 CPU Select   */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t EXTINT12:1;       /*!< bit:     24  External Interrupt 12 CPU Select   */
-    uint32_t :1;               /*!< bit:     25  Reserved                           */
-    uint32_t EXTINT13:1;       /*!< bit:     26  External Interrupt 13 CPU Select   */
-    uint32_t :1;               /*!< bit:     27  Reserved                           */
-    uint32_t EXTINT14:1;       /*!< bit:     28  External Interrupt 14 CPU Select   */
-    uint32_t :1;               /*!< bit:     29  Reserved                           */
-    uint32_t EXTINT15:1;       /*!< bit:     30  External Interrupt 15 CPU Select   */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_EICCPUSEL0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_EICCPUSEL0_OFFSET       0x120        /**< \brief (TAL_EICCPUSEL0 offset) EIC External Interrupts CPU Select 0 */
-#define TAL_EICCPUSEL0_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_EICCPUSEL0 reset_value) EIC External Interrupts CPU Select 0 */
-
-#define TAL_EICCPUSEL0_EXTINT0_Pos  0            /**< \brief (TAL_EICCPUSEL0) External Interrupt 0 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT0_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT0_Pos)
-#define TAL_EICCPUSEL0_EXTINT0(value) (TAL_EICCPUSEL0_EXTINT0_Msk & ((value) << TAL_EICCPUSEL0_EXTINT0_Pos))
-#define TAL_EICCPUSEL0_EXTINT1_Pos  2            /**< \brief (TAL_EICCPUSEL0) External Interrupt 1 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT1_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT1_Pos)
-#define TAL_EICCPUSEL0_EXTINT1(value) (TAL_EICCPUSEL0_EXTINT1_Msk & ((value) << TAL_EICCPUSEL0_EXTINT1_Pos))
-#define TAL_EICCPUSEL0_EXTINT2_Pos  4            /**< \brief (TAL_EICCPUSEL0) External Interrupt 2 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT2_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT2_Pos)
-#define TAL_EICCPUSEL0_EXTINT2(value) (TAL_EICCPUSEL0_EXTINT2_Msk & ((value) << TAL_EICCPUSEL0_EXTINT2_Pos))
-#define TAL_EICCPUSEL0_EXTINT3_Pos  6            /**< \brief (TAL_EICCPUSEL0) External Interrupt 3 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT3_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT3_Pos)
-#define TAL_EICCPUSEL0_EXTINT3(value) (TAL_EICCPUSEL0_EXTINT3_Msk & ((value) << TAL_EICCPUSEL0_EXTINT3_Pos))
-#define TAL_EICCPUSEL0_EXTINT4_Pos  8            /**< \brief (TAL_EICCPUSEL0) External Interrupt 4 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT4_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT4_Pos)
-#define TAL_EICCPUSEL0_EXTINT4(value) (TAL_EICCPUSEL0_EXTINT4_Msk & ((value) << TAL_EICCPUSEL0_EXTINT4_Pos))
-#define TAL_EICCPUSEL0_EXTINT5_Pos  10           /**< \brief (TAL_EICCPUSEL0) External Interrupt 5 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT5_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT5_Pos)
-#define TAL_EICCPUSEL0_EXTINT5(value) (TAL_EICCPUSEL0_EXTINT5_Msk & ((value) << TAL_EICCPUSEL0_EXTINT5_Pos))
-#define TAL_EICCPUSEL0_EXTINT6_Pos  12           /**< \brief (TAL_EICCPUSEL0) External Interrupt 6 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT6_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT6_Pos)
-#define TAL_EICCPUSEL0_EXTINT6(value) (TAL_EICCPUSEL0_EXTINT6_Msk & ((value) << TAL_EICCPUSEL0_EXTINT6_Pos))
-#define TAL_EICCPUSEL0_EXTINT7_Pos  14           /**< \brief (TAL_EICCPUSEL0) External Interrupt 7 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT7_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT7_Pos)
-#define TAL_EICCPUSEL0_EXTINT7(value) (TAL_EICCPUSEL0_EXTINT7_Msk & ((value) << TAL_EICCPUSEL0_EXTINT7_Pos))
-#define TAL_EICCPUSEL0_EXTINT8_Pos  16           /**< \brief (TAL_EICCPUSEL0) External Interrupt 8 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT8_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT8_Pos)
-#define TAL_EICCPUSEL0_EXTINT8(value) (TAL_EICCPUSEL0_EXTINT8_Msk & ((value) << TAL_EICCPUSEL0_EXTINT8_Pos))
-#define TAL_EICCPUSEL0_EXTINT9_Pos  18           /**< \brief (TAL_EICCPUSEL0) External Interrupt 9 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT9_Msk  (_U_(0x1) << TAL_EICCPUSEL0_EXTINT9_Pos)
-#define TAL_EICCPUSEL0_EXTINT9(value) (TAL_EICCPUSEL0_EXTINT9_Msk & ((value) << TAL_EICCPUSEL0_EXTINT9_Pos))
-#define TAL_EICCPUSEL0_EXTINT10_Pos 20           /**< \brief (TAL_EICCPUSEL0) External Interrupt 10 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT10_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT10_Pos)
-#define TAL_EICCPUSEL0_EXTINT10(value) (TAL_EICCPUSEL0_EXTINT10_Msk & ((value) << TAL_EICCPUSEL0_EXTINT10_Pos))
-#define TAL_EICCPUSEL0_EXTINT11_Pos 22           /**< \brief (TAL_EICCPUSEL0) External Interrupt 11 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT11_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT11_Pos)
-#define TAL_EICCPUSEL0_EXTINT11(value) (TAL_EICCPUSEL0_EXTINT11_Msk & ((value) << TAL_EICCPUSEL0_EXTINT11_Pos))
-#define TAL_EICCPUSEL0_EXTINT12_Pos 24           /**< \brief (TAL_EICCPUSEL0) External Interrupt 12 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT12_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT12_Pos)
-#define TAL_EICCPUSEL0_EXTINT12(value) (TAL_EICCPUSEL0_EXTINT12_Msk & ((value) << TAL_EICCPUSEL0_EXTINT12_Pos))
-#define TAL_EICCPUSEL0_EXTINT13_Pos 26           /**< \brief (TAL_EICCPUSEL0) External Interrupt 13 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT13_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT13_Pos)
-#define TAL_EICCPUSEL0_EXTINT13(value) (TAL_EICCPUSEL0_EXTINT13_Msk & ((value) << TAL_EICCPUSEL0_EXTINT13_Pos))
-#define TAL_EICCPUSEL0_EXTINT14_Pos 28           /**< \brief (TAL_EICCPUSEL0) External Interrupt 14 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT14_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT14_Pos)
-#define TAL_EICCPUSEL0_EXTINT14(value) (TAL_EICCPUSEL0_EXTINT14_Msk & ((value) << TAL_EICCPUSEL0_EXTINT14_Pos))
-#define TAL_EICCPUSEL0_EXTINT15_Pos 30           /**< \brief (TAL_EICCPUSEL0) External Interrupt 15 CPU Select */
-#define TAL_EICCPUSEL0_EXTINT15_Msk (_U_(0x1) << TAL_EICCPUSEL0_EXTINT15_Pos)
-#define TAL_EICCPUSEL0_EXTINT15(value) (TAL_EICCPUSEL0_EXTINT15_Msk & ((value) << TAL_EICCPUSEL0_EXTINT15_Pos))
-#define TAL_EICCPUSEL0_MASK         _U_(0x55555555) /**< \brief (TAL_EICCPUSEL0) MASK Register */
-
-/* -------- TAL_INTCPUSEL0 : (TAL Offset: 0x128) (R/W 32) Interrupts CPU Select 0 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t PAC:1;            /*!< bit:      0  PAC Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t PM:1;             /*!< bit:      2  PM Interrupt CPU Select            */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t MCLK:1;           /*!< bit:      4  MCLK Interrupt CPU Select          */
-    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
-    uint32_t OSCCTRL:1;        /*!< bit:      8  OSCCTRL Interrupt CPU Select       */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t OSC32KCTRL:1;     /*!< bit:     10  OSC32KCTRL Interrupt CPU Select    */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t SUPC:1;           /*!< bit:     12  SUPC Interrupt CPU Select          */
-    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
-    uint32_t WDT:1;            /*!< bit:     16  WDT Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     17  Reserved                           */
-    uint32_t RTC:1;            /*!< bit:     18  RTC Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t EIC:1;            /*!< bit:     20  EIC Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     21  Reserved                           */
-    uint32_t FREQM:1;          /*!< bit:     22  FREQM Interrupt CPU Select         */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t SERCOM0:1;        /*!< bit:     24  SERCOM0 Interrupt CPU Select       */
-    uint32_t :1;               /*!< bit:     25  Reserved                           */
-    uint32_t SERCOM1:1;        /*!< bit:     26  SERCOM1 Interrupt CPU Select       */
-    uint32_t :1;               /*!< bit:     27  Reserved                           */
-    uint32_t TC0:1;            /*!< bit:     28  TC0 Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     29  Reserved                           */
-    uint32_t TC1:1;            /*!< bit:     30  TC1 Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_INTCPUSEL0_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTCPUSEL0_OFFSET       0x128        /**< \brief (TAL_INTCPUSEL0 offset) Interrupts CPU Select 0 */
-#define TAL_INTCPUSEL0_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_INTCPUSEL0 reset_value) Interrupts CPU Select 0 */
-
-#define TAL_INTCPUSEL0_PAC_Pos      0            /**< \brief (TAL_INTCPUSEL0) PAC Interrupt CPU Select */
-#define TAL_INTCPUSEL0_PAC_Msk      (_U_(0x1) << TAL_INTCPUSEL0_PAC_Pos)
-#define TAL_INTCPUSEL0_PAC(value)   (TAL_INTCPUSEL0_PAC_Msk & ((value) << TAL_INTCPUSEL0_PAC_Pos))
-#define TAL_INTCPUSEL0_PM_Pos       2            /**< \brief (TAL_INTCPUSEL0) PM Interrupt CPU Select */
-#define TAL_INTCPUSEL0_PM_Msk       (_U_(0x1) << TAL_INTCPUSEL0_PM_Pos)
-#define TAL_INTCPUSEL0_PM(value)    (TAL_INTCPUSEL0_PM_Msk & ((value) << TAL_INTCPUSEL0_PM_Pos))
-#define TAL_INTCPUSEL0_MCLK_Pos     4            /**< \brief (TAL_INTCPUSEL0) MCLK Interrupt CPU Select */
-#define TAL_INTCPUSEL0_MCLK_Msk     (_U_(0x1) << TAL_INTCPUSEL0_MCLK_Pos)
-#define TAL_INTCPUSEL0_MCLK(value)  (TAL_INTCPUSEL0_MCLK_Msk & ((value) << TAL_INTCPUSEL0_MCLK_Pos))
-#define TAL_INTCPUSEL0_OSCCTRL_Pos  8            /**< \brief (TAL_INTCPUSEL0) OSCCTRL Interrupt CPU Select */
-#define TAL_INTCPUSEL0_OSCCTRL_Msk  (_U_(0x1) << TAL_INTCPUSEL0_OSCCTRL_Pos)
-#define TAL_INTCPUSEL0_OSCCTRL(value) (TAL_INTCPUSEL0_OSCCTRL_Msk & ((value) << TAL_INTCPUSEL0_OSCCTRL_Pos))
-#define TAL_INTCPUSEL0_OSC32KCTRL_Pos 10           /**< \brief (TAL_INTCPUSEL0) OSC32KCTRL Interrupt CPU Select */
-#define TAL_INTCPUSEL0_OSC32KCTRL_Msk (_U_(0x1) << TAL_INTCPUSEL0_OSC32KCTRL_Pos)
-#define TAL_INTCPUSEL0_OSC32KCTRL(value) (TAL_INTCPUSEL0_OSC32KCTRL_Msk & ((value) << TAL_INTCPUSEL0_OSC32KCTRL_Pos))
-#define TAL_INTCPUSEL0_SUPC_Pos     12           /**< \brief (TAL_INTCPUSEL0) SUPC Interrupt CPU Select */
-#define TAL_INTCPUSEL0_SUPC_Msk     (_U_(0x1) << TAL_INTCPUSEL0_SUPC_Pos)
-#define TAL_INTCPUSEL0_SUPC(value)  (TAL_INTCPUSEL0_SUPC_Msk & ((value) << TAL_INTCPUSEL0_SUPC_Pos))
-#define TAL_INTCPUSEL0_WDT_Pos      16           /**< \brief (TAL_INTCPUSEL0) WDT Interrupt CPU Select */
-#define TAL_INTCPUSEL0_WDT_Msk      (_U_(0x1) << TAL_INTCPUSEL0_WDT_Pos)
-#define TAL_INTCPUSEL0_WDT(value)   (TAL_INTCPUSEL0_WDT_Msk & ((value) << TAL_INTCPUSEL0_WDT_Pos))
-#define TAL_INTCPUSEL0_RTC_Pos      18           /**< \brief (TAL_INTCPUSEL0) RTC Interrupt CPU Select */
-#define TAL_INTCPUSEL0_RTC_Msk      (_U_(0x1) << TAL_INTCPUSEL0_RTC_Pos)
-#define TAL_INTCPUSEL0_RTC(value)   (TAL_INTCPUSEL0_RTC_Msk & ((value) << TAL_INTCPUSEL0_RTC_Pos))
-#define TAL_INTCPUSEL0_EIC_Pos      20           /**< \brief (TAL_INTCPUSEL0) EIC Interrupt CPU Select */
-#define TAL_INTCPUSEL0_EIC_Msk      (_U_(0x1) << TAL_INTCPUSEL0_EIC_Pos)
-#define TAL_INTCPUSEL0_EIC(value)   (TAL_INTCPUSEL0_EIC_Msk & ((value) << TAL_INTCPUSEL0_EIC_Pos))
-#define TAL_INTCPUSEL0_FREQM_Pos    22           /**< \brief (TAL_INTCPUSEL0) FREQM Interrupt CPU Select */
-#define TAL_INTCPUSEL0_FREQM_Msk    (_U_(0x1) << TAL_INTCPUSEL0_FREQM_Pos)
-#define TAL_INTCPUSEL0_FREQM(value) (TAL_INTCPUSEL0_FREQM_Msk & ((value) << TAL_INTCPUSEL0_FREQM_Pos))
-#define TAL_INTCPUSEL0_SERCOM0_Pos  24           /**< \brief (TAL_INTCPUSEL0) SERCOM0 Interrupt CPU Select */
-#define TAL_INTCPUSEL0_SERCOM0_Msk  (_U_(0x1) << TAL_INTCPUSEL0_SERCOM0_Pos)
-#define TAL_INTCPUSEL0_SERCOM0(value) (TAL_INTCPUSEL0_SERCOM0_Msk & ((value) << TAL_INTCPUSEL0_SERCOM0_Pos))
-#define TAL_INTCPUSEL0_SERCOM1_Pos  26           /**< \brief (TAL_INTCPUSEL0) SERCOM1 Interrupt CPU Select */
-#define TAL_INTCPUSEL0_SERCOM1_Msk  (_U_(0x1) << TAL_INTCPUSEL0_SERCOM1_Pos)
-#define TAL_INTCPUSEL0_SERCOM1(value) (TAL_INTCPUSEL0_SERCOM1_Msk & ((value) << TAL_INTCPUSEL0_SERCOM1_Pos))
-#define TAL_INTCPUSEL0_TC0_Pos      28           /**< \brief (TAL_INTCPUSEL0) TC0 Interrupt CPU Select */
-#define TAL_INTCPUSEL0_TC0_Msk      (_U_(0x1) << TAL_INTCPUSEL0_TC0_Pos)
-#define TAL_INTCPUSEL0_TC0(value)   (TAL_INTCPUSEL0_TC0_Msk & ((value) << TAL_INTCPUSEL0_TC0_Pos))
-#define TAL_INTCPUSEL0_TC1_Pos      30           /**< \brief (TAL_INTCPUSEL0) TC1 Interrupt CPU Select */
-#define TAL_INTCPUSEL0_TC1_Msk      (_U_(0x1) << TAL_INTCPUSEL0_TC1_Pos)
-#define TAL_INTCPUSEL0_TC1(value)   (TAL_INTCPUSEL0_TC1_Msk & ((value) << TAL_INTCPUSEL0_TC1_Pos))
-#define TAL_INTCPUSEL0_MASK         _U_(0x55551515) /**< \brief (TAL_INTCPUSEL0) MASK Register */
-
-/* -------- TAL_INTCPUSEL1 : (TAL Offset: 0x12C) (R/W 32) Interrupts CPU Select 1 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_INTCPUSEL1_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTCPUSEL1_OFFSET       0x12C        /**< \brief (TAL_INTCPUSEL1 offset) Interrupts CPU Select 1 */
-#define TAL_INTCPUSEL1_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_INTCPUSEL1 reset_value) Interrupts CPU Select 1 */
-#define TAL_INTCPUSEL1_MASK         _U_(0x00000000) /**< \brief (TAL_INTCPUSEL1) MASK Register */
-
-/* -------- TAL_INTCPUSEL2 : (TAL Offset: 0x130) (R/W 32) Interrupts CPU Select 2 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t USB:1;            /*!< bit:      0  USB Interrupt CPU Select           */
-    uint32_t :3;               /*!< bit:  1.. 3  Reserved                           */
-    uint32_t NVMCTRL:1;        /*!< bit:      4  NVMCTRL Interrupt CPU Select       */
-    uint32_t :5;               /*!< bit:  5.. 9  Reserved                           */
-    uint32_t DMAC:1;           /*!< bit:     10  DMAC Interrupt CPU Select          */
-    uint32_t :3;               /*!< bit: 11..13  Reserved                           */
-    uint32_t EVSYS:1;          /*!< bit:     14  EVSYS Interrupt CPU Select         */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t PICOP:1;          /*!< bit:     16  PICOP Interrupt CPU Select         */
-    uint32_t :1;               /*!< bit:     17  Reserved                           */
-    uint32_t SERCOM2:1;        /*!< bit:     18  SERCOM2 Interrupt CPU Select       */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t SERCOM3:1;        /*!< bit:     20  SERCOM3 Interrupt CPU Select       */
-    uint32_t :1;               /*!< bit:     21  Reserved                           */
-    uint32_t TCC0:1;           /*!< bit:     22  TCC0 Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t TCC1:1;           /*!< bit:     24  TCC1 Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:     25  Reserved                           */
-    uint32_t TC2:1;            /*!< bit:     26  TC2 Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     27  Reserved                           */
-    uint32_t TC3:1;            /*!< bit:     28  TC3 Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     29  Reserved                           */
-    uint32_t TAL:1;            /*!< bit:     30  TAL Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_INTCPUSEL2_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTCPUSEL2_OFFSET       0x130        /**< \brief (TAL_INTCPUSEL2 offset) Interrupts CPU Select 2 */
-#define TAL_INTCPUSEL2_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_INTCPUSEL2 reset_value) Interrupts CPU Select 2 */
-
-#define TAL_INTCPUSEL2_USB_Pos      0            /**< \brief (TAL_INTCPUSEL2) USB Interrupt CPU Select */
-#define TAL_INTCPUSEL2_USB_Msk      (_U_(0x1) << TAL_INTCPUSEL2_USB_Pos)
-#define TAL_INTCPUSEL2_USB(value)   (TAL_INTCPUSEL2_USB_Msk & ((value) << TAL_INTCPUSEL2_USB_Pos))
-#define TAL_INTCPUSEL2_NVMCTRL_Pos  4            /**< \brief (TAL_INTCPUSEL2) NVMCTRL Interrupt CPU Select */
-#define TAL_INTCPUSEL2_NVMCTRL_Msk  (_U_(0x1) << TAL_INTCPUSEL2_NVMCTRL_Pos)
-#define TAL_INTCPUSEL2_NVMCTRL(value) (TAL_INTCPUSEL2_NVMCTRL_Msk & ((value) << TAL_INTCPUSEL2_NVMCTRL_Pos))
-#define TAL_INTCPUSEL2_DMAC_Pos     10           /**< \brief (TAL_INTCPUSEL2) DMAC Interrupt CPU Select */
-#define TAL_INTCPUSEL2_DMAC_Msk     (_U_(0x1) << TAL_INTCPUSEL2_DMAC_Pos)
-#define TAL_INTCPUSEL2_DMAC(value)  (TAL_INTCPUSEL2_DMAC_Msk & ((value) << TAL_INTCPUSEL2_DMAC_Pos))
-#define TAL_INTCPUSEL2_EVSYS_Pos    14           /**< \brief (TAL_INTCPUSEL2) EVSYS Interrupt CPU Select */
-#define TAL_INTCPUSEL2_EVSYS_Msk    (_U_(0x1) << TAL_INTCPUSEL2_EVSYS_Pos)
-#define TAL_INTCPUSEL2_EVSYS(value) (TAL_INTCPUSEL2_EVSYS_Msk & ((value) << TAL_INTCPUSEL2_EVSYS_Pos))
-#define TAL_INTCPUSEL2_PICOP_Pos    16           /**< \brief (TAL_INTCPUSEL2) PICOP Interrupt CPU Select */
-#define TAL_INTCPUSEL2_PICOP_Msk    (_U_(0x1) << TAL_INTCPUSEL2_PICOP_Pos)
-#define TAL_INTCPUSEL2_PICOP(value) (TAL_INTCPUSEL2_PICOP_Msk & ((value) << TAL_INTCPUSEL2_PICOP_Pos))
-#define TAL_INTCPUSEL2_SERCOM2_Pos  18           /**< \brief (TAL_INTCPUSEL2) SERCOM2 Interrupt CPU Select */
-#define TAL_INTCPUSEL2_SERCOM2_Msk  (_U_(0x1) << TAL_INTCPUSEL2_SERCOM2_Pos)
-#define TAL_INTCPUSEL2_SERCOM2(value) (TAL_INTCPUSEL2_SERCOM2_Msk & ((value) << TAL_INTCPUSEL2_SERCOM2_Pos))
-#define TAL_INTCPUSEL2_SERCOM3_Pos  20           /**< \brief (TAL_INTCPUSEL2) SERCOM3 Interrupt CPU Select */
-#define TAL_INTCPUSEL2_SERCOM3_Msk  (_U_(0x1) << TAL_INTCPUSEL2_SERCOM3_Pos)
-#define TAL_INTCPUSEL2_SERCOM3(value) (TAL_INTCPUSEL2_SERCOM3_Msk & ((value) << TAL_INTCPUSEL2_SERCOM3_Pos))
-#define TAL_INTCPUSEL2_TCC0_Pos     22           /**< \brief (TAL_INTCPUSEL2) TCC0 Interrupt CPU Select */
-#define TAL_INTCPUSEL2_TCC0_Msk     (_U_(0x1) << TAL_INTCPUSEL2_TCC0_Pos)
-#define TAL_INTCPUSEL2_TCC0(value)  (TAL_INTCPUSEL2_TCC0_Msk & ((value) << TAL_INTCPUSEL2_TCC0_Pos))
-#define TAL_INTCPUSEL2_TCC1_Pos     24           /**< \brief (TAL_INTCPUSEL2) TCC1 Interrupt CPU Select */
-#define TAL_INTCPUSEL2_TCC1_Msk     (_U_(0x1) << TAL_INTCPUSEL2_TCC1_Pos)
-#define TAL_INTCPUSEL2_TCC1(value)  (TAL_INTCPUSEL2_TCC1_Msk & ((value) << TAL_INTCPUSEL2_TCC1_Pos))
-#define TAL_INTCPUSEL2_TC2_Pos      26           /**< \brief (TAL_INTCPUSEL2) TC2 Interrupt CPU Select */
-#define TAL_INTCPUSEL2_TC2_Msk      (_U_(0x1) << TAL_INTCPUSEL2_TC2_Pos)
-#define TAL_INTCPUSEL2_TC2(value)   (TAL_INTCPUSEL2_TC2_Msk & ((value) << TAL_INTCPUSEL2_TC2_Pos))
-#define TAL_INTCPUSEL2_TC3_Pos      28           /**< \brief (TAL_INTCPUSEL2) TC3 Interrupt CPU Select */
-#define TAL_INTCPUSEL2_TC3_Msk      (_U_(0x1) << TAL_INTCPUSEL2_TC3_Pos)
-#define TAL_INTCPUSEL2_TC3(value)   (TAL_INTCPUSEL2_TC3_Msk & ((value) << TAL_INTCPUSEL2_TC3_Pos))
-#define TAL_INTCPUSEL2_TAL_Pos      30           /**< \brief (TAL_INTCPUSEL2) TAL Interrupt CPU Select */
-#define TAL_INTCPUSEL2_TAL_Msk      (_U_(0x1) << TAL_INTCPUSEL2_TAL_Pos)
-#define TAL_INTCPUSEL2_TAL(value)   (TAL_INTCPUSEL2_TAL_Msk & ((value) << TAL_INTCPUSEL2_TAL_Pos))
-#define TAL_INTCPUSEL2_MASK         _U_(0x55554411) /**< \brief (TAL_INTCPUSEL2) MASK Register */
-
-/* -------- TAL_INTCPUSEL3 : (TAL Offset: 0x134) (R/W 32) Interrupts CPU Select 3 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t RAMECC:1;         /*!< bit:      0  RAMECC Interrupt CPU Select        */
-    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_INTCPUSEL3_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTCPUSEL3_OFFSET       0x134        /**< \brief (TAL_INTCPUSEL3 offset) Interrupts CPU Select 3 */
-#define TAL_INTCPUSEL3_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_INTCPUSEL3 reset_value) Interrupts CPU Select 3 */
-
-#define TAL_INTCPUSEL3_RAMECC_Pos   0            /**< \brief (TAL_INTCPUSEL3) RAMECC Interrupt CPU Select */
-#define TAL_INTCPUSEL3_RAMECC_Msk   (_U_(0x1) << TAL_INTCPUSEL3_RAMECC_Pos)
-#define TAL_INTCPUSEL3_RAMECC(value) (TAL_INTCPUSEL3_RAMECC_Msk & ((value) << TAL_INTCPUSEL3_RAMECC_Pos))
-#define TAL_INTCPUSEL3_MASK         _U_(0x00000001) /**< \brief (TAL_INTCPUSEL3) MASK Register */
-
-/* -------- TAL_INTCPUSEL4 : (TAL Offset: 0x138) (R/W 32) Interrupts CPU Select 4 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CAN0:1;           /*!< bit:      0  CAN0 Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t CAN1:1;           /*!< bit:      2  CAN1 Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t GMAC:1;           /*!< bit:      4  GMAC Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t TCC2:1;           /*!< bit:      6  TCC2 Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t TCC3:1;           /*!< bit:      8  TCC3 Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t TC4:1;            /*!< bit:     10  TC4 Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t TC5:1;            /*!< bit:     12  TC5 Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     13  Reserved                           */
-    uint32_t PDEC:1;           /*!< bit:     14  PDEC Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t AC:1;             /*!< bit:     16  AC Interrupt CPU Select            */
-    uint32_t :1;               /*!< bit:     17  Reserved                           */
-    uint32_t AES:1;            /*!< bit:     18  AES Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t TRNG:1;           /*!< bit:     20  TRNG Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:     21  Reserved                           */
-    uint32_t ICM:1;            /*!< bit:     22  ICM Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     23  Reserved                           */
-    uint32_t PUKCC:1;          /*!< bit:     24  PUKCC Interrupt CPU Select         */
-    uint32_t :1;               /*!< bit:     25  Reserved                           */
-    uint32_t QSPI:1;           /*!< bit:     26  QSPI Interrupt CPU Select          */
-    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_INTCPUSEL4_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTCPUSEL4_OFFSET       0x138        /**< \brief (TAL_INTCPUSEL4 offset) Interrupts CPU Select 4 */
-#define TAL_INTCPUSEL4_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_INTCPUSEL4 reset_value) Interrupts CPU Select 4 */
-
-#define TAL_INTCPUSEL4_CAN0_Pos     0            /**< \brief (TAL_INTCPUSEL4) CAN0 Interrupt CPU Select */
-#define TAL_INTCPUSEL4_CAN0_Msk     (_U_(0x1) << TAL_INTCPUSEL4_CAN0_Pos)
-#define TAL_INTCPUSEL4_CAN0(value)  (TAL_INTCPUSEL4_CAN0_Msk & ((value) << TAL_INTCPUSEL4_CAN0_Pos))
-#define TAL_INTCPUSEL4_CAN1_Pos     2            /**< \brief (TAL_INTCPUSEL4) CAN1 Interrupt CPU Select */
-#define TAL_INTCPUSEL4_CAN1_Msk     (_U_(0x1) << TAL_INTCPUSEL4_CAN1_Pos)
-#define TAL_INTCPUSEL4_CAN1(value)  (TAL_INTCPUSEL4_CAN1_Msk & ((value) << TAL_INTCPUSEL4_CAN1_Pos))
-#define TAL_INTCPUSEL4_GMAC_Pos     4            /**< \brief (TAL_INTCPUSEL4) GMAC Interrupt CPU Select */
-#define TAL_INTCPUSEL4_GMAC_Msk     (_U_(0x1) << TAL_INTCPUSEL4_GMAC_Pos)
-#define TAL_INTCPUSEL4_GMAC(value)  (TAL_INTCPUSEL4_GMAC_Msk & ((value) << TAL_INTCPUSEL4_GMAC_Pos))
-#define TAL_INTCPUSEL4_TCC2_Pos     6            /**< \brief (TAL_INTCPUSEL4) TCC2 Interrupt CPU Select */
-#define TAL_INTCPUSEL4_TCC2_Msk     (_U_(0x1) << TAL_INTCPUSEL4_TCC2_Pos)
-#define TAL_INTCPUSEL4_TCC2(value)  (TAL_INTCPUSEL4_TCC2_Msk & ((value) << TAL_INTCPUSEL4_TCC2_Pos))
-#define TAL_INTCPUSEL4_TCC3_Pos     8            /**< \brief (TAL_INTCPUSEL4) TCC3 Interrupt CPU Select */
-#define TAL_INTCPUSEL4_TCC3_Msk     (_U_(0x1) << TAL_INTCPUSEL4_TCC3_Pos)
-#define TAL_INTCPUSEL4_TCC3(value)  (TAL_INTCPUSEL4_TCC3_Msk & ((value) << TAL_INTCPUSEL4_TCC3_Pos))
-#define TAL_INTCPUSEL4_TC4_Pos      10           /**< \brief (TAL_INTCPUSEL4) TC4 Interrupt CPU Select */
-#define TAL_INTCPUSEL4_TC4_Msk      (_U_(0x1) << TAL_INTCPUSEL4_TC4_Pos)
-#define TAL_INTCPUSEL4_TC4(value)   (TAL_INTCPUSEL4_TC4_Msk & ((value) << TAL_INTCPUSEL4_TC4_Pos))
-#define TAL_INTCPUSEL4_TC5_Pos      12           /**< \brief (TAL_INTCPUSEL4) TC5 Interrupt CPU Select */
-#define TAL_INTCPUSEL4_TC5_Msk      (_U_(0x1) << TAL_INTCPUSEL4_TC5_Pos)
-#define TAL_INTCPUSEL4_TC5(value)   (TAL_INTCPUSEL4_TC5_Msk & ((value) << TAL_INTCPUSEL4_TC5_Pos))
-#define TAL_INTCPUSEL4_PDEC_Pos     14           /**< \brief (TAL_INTCPUSEL4) PDEC Interrupt CPU Select */
-#define TAL_INTCPUSEL4_PDEC_Msk     (_U_(0x1) << TAL_INTCPUSEL4_PDEC_Pos)
-#define TAL_INTCPUSEL4_PDEC(value)  (TAL_INTCPUSEL4_PDEC_Msk & ((value) << TAL_INTCPUSEL4_PDEC_Pos))
-#define TAL_INTCPUSEL4_AC_Pos       16           /**< \brief (TAL_INTCPUSEL4) AC Interrupt CPU Select */
-#define TAL_INTCPUSEL4_AC_Msk       (_U_(0x1) << TAL_INTCPUSEL4_AC_Pos)
-#define TAL_INTCPUSEL4_AC(value)    (TAL_INTCPUSEL4_AC_Msk & ((value) << TAL_INTCPUSEL4_AC_Pos))
-#define TAL_INTCPUSEL4_AES_Pos      18           /**< \brief (TAL_INTCPUSEL4) AES Interrupt CPU Select */
-#define TAL_INTCPUSEL4_AES_Msk      (_U_(0x1) << TAL_INTCPUSEL4_AES_Pos)
-#define TAL_INTCPUSEL4_AES(value)   (TAL_INTCPUSEL4_AES_Msk & ((value) << TAL_INTCPUSEL4_AES_Pos))
-#define TAL_INTCPUSEL4_TRNG_Pos     20           /**< \brief (TAL_INTCPUSEL4) TRNG Interrupt CPU Select */
-#define TAL_INTCPUSEL4_TRNG_Msk     (_U_(0x1) << TAL_INTCPUSEL4_TRNG_Pos)
-#define TAL_INTCPUSEL4_TRNG(value)  (TAL_INTCPUSEL4_TRNG_Msk & ((value) << TAL_INTCPUSEL4_TRNG_Pos))
-#define TAL_INTCPUSEL4_ICM_Pos      22           /**< \brief (TAL_INTCPUSEL4) ICM Interrupt CPU Select */
-#define TAL_INTCPUSEL4_ICM_Msk      (_U_(0x1) << TAL_INTCPUSEL4_ICM_Pos)
-#define TAL_INTCPUSEL4_ICM(value)   (TAL_INTCPUSEL4_ICM_Msk & ((value) << TAL_INTCPUSEL4_ICM_Pos))
-#define TAL_INTCPUSEL4_PUKCC_Pos    24           /**< \brief (TAL_INTCPUSEL4) PUKCC Interrupt CPU Select */
-#define TAL_INTCPUSEL4_PUKCC_Msk    (_U_(0x1) << TAL_INTCPUSEL4_PUKCC_Pos)
-#define TAL_INTCPUSEL4_PUKCC(value) (TAL_INTCPUSEL4_PUKCC_Msk & ((value) << TAL_INTCPUSEL4_PUKCC_Pos))
-#define TAL_INTCPUSEL4_QSPI_Pos     26           /**< \brief (TAL_INTCPUSEL4) QSPI Interrupt CPU Select */
-#define TAL_INTCPUSEL4_QSPI_Msk     (_U_(0x1) << TAL_INTCPUSEL4_QSPI_Pos)
-#define TAL_INTCPUSEL4_QSPI(value)  (TAL_INTCPUSEL4_QSPI_Msk & ((value) << TAL_INTCPUSEL4_QSPI_Pos))
-#define TAL_INTCPUSEL4_MASK         _U_(0x05555555) /**< \brief (TAL_INTCPUSEL4) MASK Register */
-
-/* -------- TAL_INTCPUSEL5 : (TAL Offset: 0x13C) (R/W 32) Interrupts CPU Select 5 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_INTCPUSEL5_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTCPUSEL5_OFFSET       0x13C        /**< \brief (TAL_INTCPUSEL5 offset) Interrupts CPU Select 5 */
-#define TAL_INTCPUSEL5_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_INTCPUSEL5 reset_value) Interrupts CPU Select 5 */
-#define TAL_INTCPUSEL5_MASK         _U_(0x00000000) /**< \brief (TAL_INTCPUSEL5) MASK Register */
-
-/* -------- TAL_INTCPUSEL6 : (TAL Offset: 0x140) (R/W 32) Interrupts CPU Select 6 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SERCOM4:1;        /*!< bit:      0  SERCOM4 Interrupt CPU Select       */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t SERCOM5:1;        /*!< bit:      2  SERCOM5 Interrupt CPU Select       */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t SERCOM6:1;        /*!< bit:      4  SERCOM6 Interrupt CPU Select       */
-    uint32_t :1;               /*!< bit:      5  Reserved                           */
-    uint32_t SERCOM7:1;        /*!< bit:      6  SERCOM7 Interrupt CPU Select       */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t TCC4:1;           /*!< bit:      8  TCC4 Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:      9  Reserved                           */
-    uint32_t TC6:1;            /*!< bit:     10  TC6 Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t TC7:1;            /*!< bit:     12  TC7 Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     13  Reserved                           */
-    uint32_t ADC0:1;           /*!< bit:     14  ADC0 Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:     15  Reserved                           */
-    uint32_t ADC1:1;           /*!< bit:     16  ADC1 Interrupt CPU Select          */
-    uint32_t :1;               /*!< bit:     17  Reserved                           */
-    uint32_t DAC:1;            /*!< bit:     18  DAC Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     19  Reserved                           */
-    uint32_t I2S:1;            /*!< bit:     20  I2S Interrupt CPU Select           */
-    uint32_t :1;               /*!< bit:     21  Reserved                           */
-    uint32_t PCC:1;            /*!< bit:     22  PCC Interrupt CPU Select           */
-    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_INTCPUSEL6_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTCPUSEL6_OFFSET       0x140        /**< \brief (TAL_INTCPUSEL6 offset) Interrupts CPU Select 6 */
-#define TAL_INTCPUSEL6_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_INTCPUSEL6 reset_value) Interrupts CPU Select 6 */
-
-#define TAL_INTCPUSEL6_SERCOM4_Pos  0            /**< \brief (TAL_INTCPUSEL6) SERCOM4 Interrupt CPU Select */
-#define TAL_INTCPUSEL6_SERCOM4_Msk  (_U_(0x1) << TAL_INTCPUSEL6_SERCOM4_Pos)
-#define TAL_INTCPUSEL6_SERCOM4(value) (TAL_INTCPUSEL6_SERCOM4_Msk & ((value) << TAL_INTCPUSEL6_SERCOM4_Pos))
-#define TAL_INTCPUSEL6_SERCOM5_Pos  2            /**< \brief (TAL_INTCPUSEL6) SERCOM5 Interrupt CPU Select */
-#define TAL_INTCPUSEL6_SERCOM5_Msk  (_U_(0x1) << TAL_INTCPUSEL6_SERCOM5_Pos)
-#define TAL_INTCPUSEL6_SERCOM5(value) (TAL_INTCPUSEL6_SERCOM5_Msk & ((value) << TAL_INTCPUSEL6_SERCOM5_Pos))
-#define TAL_INTCPUSEL6_SERCOM6_Pos  4            /**< \brief (TAL_INTCPUSEL6) SERCOM6 Interrupt CPU Select */
-#define TAL_INTCPUSEL6_SERCOM6_Msk  (_U_(0x1) << TAL_INTCPUSEL6_SERCOM6_Pos)
-#define TAL_INTCPUSEL6_SERCOM6(value) (TAL_INTCPUSEL6_SERCOM6_Msk & ((value) << TAL_INTCPUSEL6_SERCOM6_Pos))
-#define TAL_INTCPUSEL6_SERCOM7_Pos  6            /**< \brief (TAL_INTCPUSEL6) SERCOM7 Interrupt CPU Select */
-#define TAL_INTCPUSEL6_SERCOM7_Msk  (_U_(0x1) << TAL_INTCPUSEL6_SERCOM7_Pos)
-#define TAL_INTCPUSEL6_SERCOM7(value) (TAL_INTCPUSEL6_SERCOM7_Msk & ((value) << TAL_INTCPUSEL6_SERCOM7_Pos))
-#define TAL_INTCPUSEL6_TCC4_Pos     8            /**< \brief (TAL_INTCPUSEL6) TCC4 Interrupt CPU Select */
-#define TAL_INTCPUSEL6_TCC4_Msk     (_U_(0x1) << TAL_INTCPUSEL6_TCC4_Pos)
-#define TAL_INTCPUSEL6_TCC4(value)  (TAL_INTCPUSEL6_TCC4_Msk & ((value) << TAL_INTCPUSEL6_TCC4_Pos))
-#define TAL_INTCPUSEL6_TC6_Pos      10           /**< \brief (TAL_INTCPUSEL6) TC6 Interrupt CPU Select */
-#define TAL_INTCPUSEL6_TC6_Msk      (_U_(0x1) << TAL_INTCPUSEL6_TC6_Pos)
-#define TAL_INTCPUSEL6_TC6(value)   (TAL_INTCPUSEL6_TC6_Msk & ((value) << TAL_INTCPUSEL6_TC6_Pos))
-#define TAL_INTCPUSEL6_TC7_Pos      12           /**< \brief (TAL_INTCPUSEL6) TC7 Interrupt CPU Select */
-#define TAL_INTCPUSEL6_TC7_Msk      (_U_(0x1) << TAL_INTCPUSEL6_TC7_Pos)
-#define TAL_INTCPUSEL6_TC7(value)   (TAL_INTCPUSEL6_TC7_Msk & ((value) << TAL_INTCPUSEL6_TC7_Pos))
-#define TAL_INTCPUSEL6_ADC0_Pos     14           /**< \brief (TAL_INTCPUSEL6) ADC0 Interrupt CPU Select */
-#define TAL_INTCPUSEL6_ADC0_Msk     (_U_(0x1) << TAL_INTCPUSEL6_ADC0_Pos)
-#define TAL_INTCPUSEL6_ADC0(value)  (TAL_INTCPUSEL6_ADC0_Msk & ((value) << TAL_INTCPUSEL6_ADC0_Pos))
-#define TAL_INTCPUSEL6_ADC1_Pos     16           /**< \brief (TAL_INTCPUSEL6) ADC1 Interrupt CPU Select */
-#define TAL_INTCPUSEL6_ADC1_Msk     (_U_(0x1) << TAL_INTCPUSEL6_ADC1_Pos)
-#define TAL_INTCPUSEL6_ADC1(value)  (TAL_INTCPUSEL6_ADC1_Msk & ((value) << TAL_INTCPUSEL6_ADC1_Pos))
-#define TAL_INTCPUSEL6_DAC_Pos      18           /**< \brief (TAL_INTCPUSEL6) DAC Interrupt CPU Select */
-#define TAL_INTCPUSEL6_DAC_Msk      (_U_(0x1) << TAL_INTCPUSEL6_DAC_Pos)
-#define TAL_INTCPUSEL6_DAC(value)   (TAL_INTCPUSEL6_DAC_Msk & ((value) << TAL_INTCPUSEL6_DAC_Pos))
-#define TAL_INTCPUSEL6_I2S_Pos      20           /**< \brief (TAL_INTCPUSEL6) I2S Interrupt CPU Select */
-#define TAL_INTCPUSEL6_I2S_Msk      (_U_(0x1) << TAL_INTCPUSEL6_I2S_Pos)
-#define TAL_INTCPUSEL6_I2S(value)   (TAL_INTCPUSEL6_I2S_Msk & ((value) << TAL_INTCPUSEL6_I2S_Pos))
-#define TAL_INTCPUSEL6_PCC_Pos      22           /**< \brief (TAL_INTCPUSEL6) PCC Interrupt CPU Select */
-#define TAL_INTCPUSEL6_PCC_Msk      (_U_(0x1) << TAL_INTCPUSEL6_PCC_Pos)
-#define TAL_INTCPUSEL6_PCC(value)   (TAL_INTCPUSEL6_PCC_Msk & ((value) << TAL_INTCPUSEL6_PCC_Pos))
-#define TAL_INTCPUSEL6_MASK         _U_(0x00555555) /**< \brief (TAL_INTCPUSEL6) MASK Register */
-
-/* -------- TAL_INTCPUSEL7 : (TAL Offset: 0x144) (R/W 32) Interrupts CPU Select 7 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_INTCPUSEL7_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTCPUSEL7_OFFSET       0x144        /**< \brief (TAL_INTCPUSEL7 offset) Interrupts CPU Select 7 */
-#define TAL_INTCPUSEL7_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_INTCPUSEL7 reset_value) Interrupts CPU Select 7 */
-#define TAL_INTCPUSEL7_MASK         _U_(0x00000000) /**< \brief (TAL_INTCPUSEL7) MASK Register */
-
-/* -------- TAL_INTCPUSEL8 : (TAL Offset: 0x148) (R/W 32) Interrupts CPU Select 8 -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SDHC0:1;          /*!< bit:      0  SDHC0 Interrupt CPU Select         */
-    uint32_t :1;               /*!< bit:      1  Reserved                           */
-    uint32_t SDHC1:1;          /*!< bit:      2  SDHC1 Interrupt CPU Select         */
-    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_INTCPUSEL8_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_INTCPUSEL8_OFFSET       0x148        /**< \brief (TAL_INTCPUSEL8 offset) Interrupts CPU Select 8 */
-#define TAL_INTCPUSEL8_RESETVALUE   _U_(0x00000000) /**< \brief (TAL_INTCPUSEL8 reset_value) Interrupts CPU Select 8 */
-
-#define TAL_INTCPUSEL8_SDHC0_Pos    0            /**< \brief (TAL_INTCPUSEL8) SDHC0 Interrupt CPU Select */
-#define TAL_INTCPUSEL8_SDHC0_Msk    (_U_(0x1) << TAL_INTCPUSEL8_SDHC0_Pos)
-#define TAL_INTCPUSEL8_SDHC0(value) (TAL_INTCPUSEL8_SDHC0_Msk & ((value) << TAL_INTCPUSEL8_SDHC0_Pos))
-#define TAL_INTCPUSEL8_SDHC1_Pos    2            /**< \brief (TAL_INTCPUSEL8) SDHC1 Interrupt CPU Select */
-#define TAL_INTCPUSEL8_SDHC1_Msk    (_U_(0x1) << TAL_INTCPUSEL8_SDHC1_Pos)
-#define TAL_INTCPUSEL8_SDHC1(value) (TAL_INTCPUSEL8_SDHC1_Msk & ((value) << TAL_INTCPUSEL8_SDHC1_Pos))
-#define TAL_INTCPUSEL8_MASK         _U_(0x00000005) /**< \brief (TAL_INTCPUSEL8) MASK Register */
-
-/* -------- TAL_IRQTRIG : (TAL Offset: 0x164) (R/W 32) Interrupt Trigger -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ENABLE:1;         /*!< bit:      0  Trigger Enable                     */
-    uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
-    uint32_t IRQNUM:8;         /*!< bit:  8..15  Interrupt Request Number           */
-    uint32_t OVERRIDE:8;       /*!< bit: 16..23  Interrupt Request Override Value   */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_IRQTRIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_IRQTRIG_OFFSET          0x164        /**< \brief (TAL_IRQTRIG offset) Interrupt Trigger */
-#define TAL_IRQTRIG_RESETVALUE      _U_(0x00000000) /**< \brief (TAL_IRQTRIG reset_value) Interrupt Trigger */
-
-#define TAL_IRQTRIG_ENABLE_Pos      0            /**< \brief (TAL_IRQTRIG) Trigger Enable */
-#define TAL_IRQTRIG_ENABLE          (_U_(0x1) << TAL_IRQTRIG_ENABLE_Pos)
-#define TAL_IRQTRIG_IRQNUM_Pos      8            /**< \brief (TAL_IRQTRIG) Interrupt Request Number */
-#define TAL_IRQTRIG_IRQNUM_Msk      (_U_(0xFF) << TAL_IRQTRIG_IRQNUM_Pos)
-#define TAL_IRQTRIG_IRQNUM(value)   (TAL_IRQTRIG_IRQNUM_Msk & ((value) << TAL_IRQTRIG_IRQNUM_Pos))
-#define TAL_IRQTRIG_OVERRIDE_Pos    16           /**< \brief (TAL_IRQTRIG) Interrupt Request Override Value */
-#define TAL_IRQTRIG_OVERRIDE_Msk    (_U_(0xFF) << TAL_IRQTRIG_OVERRIDE_Pos)
-#define TAL_IRQTRIG_OVERRIDE(value) (TAL_IRQTRIG_OVERRIDE_Msk & ((value) << TAL_IRQTRIG_OVERRIDE_Pos))
-#define TAL_IRQTRIG_MASK            _U_(0x00FFFF01) /**< \brief (TAL_IRQTRIG) MASK Register */
-
-/* -------- TAL_IRQMON : (TAL Offset: 0x168) (R/W 16) Interrupt Monitor Select -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t EXTEND:1;         /*!< bit:      0  Extended Interrupt Request         */
-    uint16_t DROP:1;           /*!< bit:      1  Drop Shortened Events              */
-    uint16_t CPUID:1;          /*!< bit:      2  ID of CPU currently servicing this IRQ */
-    uint16_t :5;               /*!< bit:  3.. 7  Reserved                           */
-    uint16_t IRQNUM:8;         /*!< bit:  8..15  Interrupt Request Number           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TAL_IRQMON_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_IRQMON_OFFSET           0x168        /**< \brief (TAL_IRQMON offset) Interrupt Monitor Select */
-#define TAL_IRQMON_RESETVALUE       _U_(0x0000)  /**< \brief (TAL_IRQMON reset_value) Interrupt Monitor Select */
-
-#define TAL_IRQMON_EXTEND_Pos       0            /**< \brief (TAL_IRQMON) Extended Interrupt Request */
-#define TAL_IRQMON_EXTEND           (_U_(0x1) << TAL_IRQMON_EXTEND_Pos)
-#define   TAL_IRQMON_EXTEND_NO_Val        _U_(0x0)   /**< \brief (TAL_IRQMON) Event is Interrupt Request signal */
-#define   TAL_IRQMON_EXTEND_YES_Val       _U_(0x1)   /**< \brief (TAL_IRQMON) Event is Interrupt Request signal extended until end of Interrupt Handler */
-#define TAL_IRQMON_EXTEND_NO        (TAL_IRQMON_EXTEND_NO_Val      << TAL_IRQMON_EXTEND_Pos)
-#define TAL_IRQMON_EXTEND_YES       (TAL_IRQMON_EXTEND_YES_Val     << TAL_IRQMON_EXTEND_Pos)
-#define TAL_IRQMON_DROP_Pos         1            /**< \brief (TAL_IRQMON) Drop Shortened Events */
-#define TAL_IRQMON_DROP             (_U_(0x1) << TAL_IRQMON_DROP_Pos)
-#define TAL_IRQMON_CPUID_Pos        2            /**< \brief (TAL_IRQMON) ID of CPU currently servicing this IRQ */
-#define TAL_IRQMON_CPUID_Msk        (_U_(0x1) << TAL_IRQMON_CPUID_Pos)
-#define TAL_IRQMON_CPUID(value)     (TAL_IRQMON_CPUID_Msk & ((value) << TAL_IRQMON_CPUID_Pos))
-#define TAL_IRQMON_IRQNUM_Pos       8            /**< \brief (TAL_IRQMON) Interrupt Request Number */
-#define TAL_IRQMON_IRQNUM_Msk       (_U_(0xFF) << TAL_IRQMON_IRQNUM_Pos)
-#define TAL_IRQMON_IRQNUM(value)    (TAL_IRQMON_IRQNUM_Msk & ((value) << TAL_IRQMON_IRQNUM_Pos))
-#define TAL_IRQMON_MASK             _U_(0xFF07)  /**< \brief (TAL_IRQMON) MASK Register */
-
-/* -------- TAL_CPUIRQS : (TAL Offset: 0x180) (R/  32) CPUIRQS Interrupt Status m for CPU n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CPUIRQS:32;       /*!< bit:  0..31  Interrupt Requests for CPU n       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_CPUIRQS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_CPUIRQS_OFFSET          0x180        /**< \brief (TAL_CPUIRQS offset) Interrupt Status m for CPU n */
-#define TAL_CPUIRQS_RESETVALUE      _U_(0x00000000) /**< \brief (TAL_CPUIRQS reset_value) Interrupt Status m for CPU n */
-
-#define TAL_CPUIRQS_CPUIRQS_Pos     0            /**< \brief (TAL_CPUIRQS) Interrupt Requests for CPU n */
-#define TAL_CPUIRQS_CPUIRQS_Msk     (_U_(0xFFFFFFFF) << TAL_CPUIRQS_CPUIRQS_Pos)
-#define TAL_CPUIRQS_CPUIRQS(value)  (TAL_CPUIRQS_CPUIRQS_Msk & ((value) << TAL_CPUIRQS_CPUIRQS_Pos))
-#define TAL_CPUIRQS_MASK            _U_(0xFFFFFFFF) /**< \brief (TAL_CPUIRQS) MASK Register */
-
-/* -------- TAL_SMASK : (TAL Offset: 0x200) (R/W 32) SMASKS Inter-Process Signal Mask m for CPU n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t IPS0:1;           /*!< bit:      0  Inter-Process Signal 0             */
-    uint32_t IPS1:1;           /*!< bit:      1  Inter-Process Signal 1             */
-    uint32_t IPS2:1;           /*!< bit:      2  Inter-Process Signal 2             */
-    uint32_t IPS3:1;           /*!< bit:      3  Inter-Process Signal 3             */
-    uint32_t IPS4:1;           /*!< bit:      4  Inter-Process Signal 4             */
-    uint32_t IPS5:1;           /*!< bit:      5  Inter-Process Signal 5             */
-    uint32_t IPS6:1;           /*!< bit:      6  Inter-Process Signal 6             */
-    uint32_t IPS7:1;           /*!< bit:      7  Inter-Process Signal 7             */
-    uint32_t IPS8:1;           /*!< bit:      8  Inter-Process Signal 8             */
-    uint32_t IPS9:1;           /*!< bit:      9  Inter-Process Signal 9             */
-    uint32_t IPS10:1;          /*!< bit:     10  Inter-Process Signal 10            */
-    uint32_t IPS11:1;          /*!< bit:     11  Inter-Process Signal 11            */
-    uint32_t IPS12:1;          /*!< bit:     12  Inter-Process Signal 12            */
-    uint32_t IPS13:1;          /*!< bit:     13  Inter-Process Signal 13            */
-    uint32_t IPS14:1;          /*!< bit:     14  Inter-Process Signal 14            */
-    uint32_t IPS15:1;          /*!< bit:     15  Inter-Process Signal 15            */
-    uint32_t IPS16:1;          /*!< bit:     16  Inter-Process Signal 16            */
-    uint32_t IPS17:1;          /*!< bit:     17  Inter-Process Signal 17            */
-    uint32_t IPS18:1;          /*!< bit:     18  Inter-Process Signal 18            */
-    uint32_t IPS19:1;          /*!< bit:     19  Inter-Process Signal 19            */
-    uint32_t IPS20:1;          /*!< bit:     20  Inter-Process Signal 20            */
-    uint32_t IPS21:1;          /*!< bit:     21  Inter-Process Signal 21            */
-    uint32_t IPS22:1;          /*!< bit:     22  Inter-Process Signal 22            */
-    uint32_t IPS23:1;          /*!< bit:     23  Inter-Process Signal 23            */
-    uint32_t IPS24:1;          /*!< bit:     24  Inter-Process Signal 24            */
-    uint32_t IPS25:1;          /*!< bit:     25  Inter-Process Signal 25            */
-    uint32_t IPS26:1;          /*!< bit:     26  Inter-Process Signal 26            */
-    uint32_t IPS27:1;          /*!< bit:     27  Inter-Process Signal 27            */
-    uint32_t IPS28:1;          /*!< bit:     28  Inter-Process Signal 28            */
-    uint32_t IPS29:1;          /*!< bit:     29  Inter-Process Signal 29            */
-    uint32_t IPS30:1;          /*!< bit:     30  Inter-Process Signal 30            */
-    uint32_t IPS31:1;          /*!< bit:     31  Inter-Process Signal 31            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t IPS:32;           /*!< bit:  0..31  Inter-Process Signal x             */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_SMASK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_SMASK_OFFSET            0x200        /**< \brief (TAL_SMASK offset) Inter-Process Signal Mask m for CPU n */
-#define TAL_SMASK_RESETVALUE        _U_(0x00000000) /**< \brief (TAL_SMASK reset_value) Inter-Process Signal Mask m for CPU n */
-
-#define TAL_SMASK_IPS0_Pos          0            /**< \brief (TAL_SMASK) Inter-Process Signal 0 */
-#define TAL_SMASK_IPS0              (_U_(1) << TAL_SMASK_IPS0_Pos)
-#define TAL_SMASK_IPS1_Pos          1            /**< \brief (TAL_SMASK) Inter-Process Signal 1 */
-#define TAL_SMASK_IPS1              (_U_(1) << TAL_SMASK_IPS1_Pos)
-#define TAL_SMASK_IPS2_Pos          2            /**< \brief (TAL_SMASK) Inter-Process Signal 2 */
-#define TAL_SMASK_IPS2              (_U_(1) << TAL_SMASK_IPS2_Pos)
-#define TAL_SMASK_IPS3_Pos          3            /**< \brief (TAL_SMASK) Inter-Process Signal 3 */
-#define TAL_SMASK_IPS3              (_U_(1) << TAL_SMASK_IPS3_Pos)
-#define TAL_SMASK_IPS4_Pos          4            /**< \brief (TAL_SMASK) Inter-Process Signal 4 */
-#define TAL_SMASK_IPS4              (_U_(1) << TAL_SMASK_IPS4_Pos)
-#define TAL_SMASK_IPS5_Pos          5            /**< \brief (TAL_SMASK) Inter-Process Signal 5 */
-#define TAL_SMASK_IPS5              (_U_(1) << TAL_SMASK_IPS5_Pos)
-#define TAL_SMASK_IPS6_Pos          6            /**< \brief (TAL_SMASK) Inter-Process Signal 6 */
-#define TAL_SMASK_IPS6              (_U_(1) << TAL_SMASK_IPS6_Pos)
-#define TAL_SMASK_IPS7_Pos          7            /**< \brief (TAL_SMASK) Inter-Process Signal 7 */
-#define TAL_SMASK_IPS7              (_U_(1) << TAL_SMASK_IPS7_Pos)
-#define TAL_SMASK_IPS8_Pos          8            /**< \brief (TAL_SMASK) Inter-Process Signal 8 */
-#define TAL_SMASK_IPS8              (_U_(1) << TAL_SMASK_IPS8_Pos)
-#define TAL_SMASK_IPS9_Pos          9            /**< \brief (TAL_SMASK) Inter-Process Signal 9 */
-#define TAL_SMASK_IPS9              (_U_(1) << TAL_SMASK_IPS9_Pos)
-#define TAL_SMASK_IPS10_Pos         10           /**< \brief (TAL_SMASK) Inter-Process Signal 10 */
-#define TAL_SMASK_IPS10             (_U_(1) << TAL_SMASK_IPS10_Pos)
-#define TAL_SMASK_IPS11_Pos         11           /**< \brief (TAL_SMASK) Inter-Process Signal 11 */
-#define TAL_SMASK_IPS11             (_U_(1) << TAL_SMASK_IPS11_Pos)
-#define TAL_SMASK_IPS12_Pos         12           /**< \brief (TAL_SMASK) Inter-Process Signal 12 */
-#define TAL_SMASK_IPS12             (_U_(1) << TAL_SMASK_IPS12_Pos)
-#define TAL_SMASK_IPS13_Pos         13           /**< \brief (TAL_SMASK) Inter-Process Signal 13 */
-#define TAL_SMASK_IPS13             (_U_(1) << TAL_SMASK_IPS13_Pos)
-#define TAL_SMASK_IPS14_Pos         14           /**< \brief (TAL_SMASK) Inter-Process Signal 14 */
-#define TAL_SMASK_IPS14             (_U_(1) << TAL_SMASK_IPS14_Pos)
-#define TAL_SMASK_IPS15_Pos         15           /**< \brief (TAL_SMASK) Inter-Process Signal 15 */
-#define TAL_SMASK_IPS15             (_U_(1) << TAL_SMASK_IPS15_Pos)
-#define TAL_SMASK_IPS16_Pos         16           /**< \brief (TAL_SMASK) Inter-Process Signal 16 */
-#define TAL_SMASK_IPS16             (_U_(1) << TAL_SMASK_IPS16_Pos)
-#define TAL_SMASK_IPS17_Pos         17           /**< \brief (TAL_SMASK) Inter-Process Signal 17 */
-#define TAL_SMASK_IPS17             (_U_(1) << TAL_SMASK_IPS17_Pos)
-#define TAL_SMASK_IPS18_Pos         18           /**< \brief (TAL_SMASK) Inter-Process Signal 18 */
-#define TAL_SMASK_IPS18             (_U_(1) << TAL_SMASK_IPS18_Pos)
-#define TAL_SMASK_IPS19_Pos         19           /**< \brief (TAL_SMASK) Inter-Process Signal 19 */
-#define TAL_SMASK_IPS19             (_U_(1) << TAL_SMASK_IPS19_Pos)
-#define TAL_SMASK_IPS20_Pos         20           /**< \brief (TAL_SMASK) Inter-Process Signal 20 */
-#define TAL_SMASK_IPS20             (_U_(1) << TAL_SMASK_IPS20_Pos)
-#define TAL_SMASK_IPS21_Pos         21           /**< \brief (TAL_SMASK) Inter-Process Signal 21 */
-#define TAL_SMASK_IPS21             (_U_(1) << TAL_SMASK_IPS21_Pos)
-#define TAL_SMASK_IPS22_Pos         22           /**< \brief (TAL_SMASK) Inter-Process Signal 22 */
-#define TAL_SMASK_IPS22             (_U_(1) << TAL_SMASK_IPS22_Pos)
-#define TAL_SMASK_IPS23_Pos         23           /**< \brief (TAL_SMASK) Inter-Process Signal 23 */
-#define TAL_SMASK_IPS23             (_U_(1) << TAL_SMASK_IPS23_Pos)
-#define TAL_SMASK_IPS24_Pos         24           /**< \brief (TAL_SMASK) Inter-Process Signal 24 */
-#define TAL_SMASK_IPS24             (_U_(1) << TAL_SMASK_IPS24_Pos)
-#define TAL_SMASK_IPS25_Pos         25           /**< \brief (TAL_SMASK) Inter-Process Signal 25 */
-#define TAL_SMASK_IPS25             (_U_(1) << TAL_SMASK_IPS25_Pos)
-#define TAL_SMASK_IPS26_Pos         26           /**< \brief (TAL_SMASK) Inter-Process Signal 26 */
-#define TAL_SMASK_IPS26             (_U_(1) << TAL_SMASK_IPS26_Pos)
-#define TAL_SMASK_IPS27_Pos         27           /**< \brief (TAL_SMASK) Inter-Process Signal 27 */
-#define TAL_SMASK_IPS27             (_U_(1) << TAL_SMASK_IPS27_Pos)
-#define TAL_SMASK_IPS28_Pos         28           /**< \brief (TAL_SMASK) Inter-Process Signal 28 */
-#define TAL_SMASK_IPS28             (_U_(1) << TAL_SMASK_IPS28_Pos)
-#define TAL_SMASK_IPS29_Pos         29           /**< \brief (TAL_SMASK) Inter-Process Signal 29 */
-#define TAL_SMASK_IPS29             (_U_(1) << TAL_SMASK_IPS29_Pos)
-#define TAL_SMASK_IPS30_Pos         30           /**< \brief (TAL_SMASK) Inter-Process Signal 30 */
-#define TAL_SMASK_IPS30             (_U_(1) << TAL_SMASK_IPS30_Pos)
-#define TAL_SMASK_IPS31_Pos         31           /**< \brief (TAL_SMASK) Inter-Process Signal 31 */
-#define TAL_SMASK_IPS31             (_U_(1) << TAL_SMASK_IPS31_Pos)
-#define TAL_SMASK_IPS_Pos           0            /**< \brief (TAL_SMASK) Inter-Process Signal x */
-#define TAL_SMASK_IPS_Msk           (_U_(0xFFFFFFFF) << TAL_SMASK_IPS_Pos)
-#define TAL_SMASK_IPS(value)        (TAL_SMASK_IPS_Msk & ((value) << TAL_SMASK_IPS_Pos))
-#define TAL_SMASK_MASK              _U_(0xFFFFFFFF) /**< \brief (TAL_SMASK) MASK Register */
-
-/* -------- TAL_SFLAGCLR : (TAL Offset: 0x220) ( /W 32) Inter-Process Signal Flag Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t IPS0:1;           /*!< bit:      0  Inter-Process Signal 0             */
-    uint32_t IPS1:1;           /*!< bit:      1  Inter-Process Signal 1             */
-    uint32_t IPS2:1;           /*!< bit:      2  Inter-Process Signal 2             */
-    uint32_t IPS3:1;           /*!< bit:      3  Inter-Process Signal 3             */
-    uint32_t IPS4:1;           /*!< bit:      4  Inter-Process Signal 4             */
-    uint32_t IPS5:1;           /*!< bit:      5  Inter-Process Signal 5             */
-    uint32_t IPS6:1;           /*!< bit:      6  Inter-Process Signal 6             */
-    uint32_t IPS7:1;           /*!< bit:      7  Inter-Process Signal 7             */
-    uint32_t IPS8:1;           /*!< bit:      8  Inter-Process Signal 8             */
-    uint32_t IPS9:1;           /*!< bit:      9  Inter-Process Signal 9             */
-    uint32_t IPS10:1;          /*!< bit:     10  Inter-Process Signal 10            */
-    uint32_t IPS11:1;          /*!< bit:     11  Inter-Process Signal 11            */
-    uint32_t IPS12:1;          /*!< bit:     12  Inter-Process Signal 12            */
-    uint32_t IPS13:1;          /*!< bit:     13  Inter-Process Signal 13            */
-    uint32_t IPS14:1;          /*!< bit:     14  Inter-Process Signal 14            */
-    uint32_t IPS15:1;          /*!< bit:     15  Inter-Process Signal 15            */
-    uint32_t IPS16:1;          /*!< bit:     16  Inter-Process Signal 16            */
-    uint32_t IPS17:1;          /*!< bit:     17  Inter-Process Signal 17            */
-    uint32_t IPS18:1;          /*!< bit:     18  Inter-Process Signal 18            */
-    uint32_t IPS19:1;          /*!< bit:     19  Inter-Process Signal 19            */
-    uint32_t IPS20:1;          /*!< bit:     20  Inter-Process Signal 20            */
-    uint32_t IPS21:1;          /*!< bit:     21  Inter-Process Signal 21            */
-    uint32_t IPS22:1;          /*!< bit:     22  Inter-Process Signal 22            */
-    uint32_t IPS23:1;          /*!< bit:     23  Inter-Process Signal 23            */
-    uint32_t IPS24:1;          /*!< bit:     24  Inter-Process Signal 24            */
-    uint32_t IPS25:1;          /*!< bit:     25  Inter-Process Signal 25            */
-    uint32_t IPS26:1;          /*!< bit:     26  Inter-Process Signal 26            */
-    uint32_t IPS27:1;          /*!< bit:     27  Inter-Process Signal 27            */
-    uint32_t IPS28:1;          /*!< bit:     28  Inter-Process Signal 28            */
-    uint32_t IPS29:1;          /*!< bit:     29  Inter-Process Signal 29            */
-    uint32_t IPS30:1;          /*!< bit:     30  Inter-Process Signal 30            */
-    uint32_t IPS31:1;          /*!< bit:     31  Inter-Process Signal 31            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t IPS:32;           /*!< bit:  0..31  Inter-Process Signal x             */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_SFLAGCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_SFLAGCLR_OFFSET         0x220        /**< \brief (TAL_SFLAGCLR offset) Inter-Process Signal Flag Clear */
-#define TAL_SFLAGCLR_RESETVALUE     _U_(0x00000000) /**< \brief (TAL_SFLAGCLR reset_value) Inter-Process Signal Flag Clear */
-
-#define TAL_SFLAGCLR_IPS0_Pos       0            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 0 */
-#define TAL_SFLAGCLR_IPS0           (_U_(1) << TAL_SFLAGCLR_IPS0_Pos)
-#define TAL_SFLAGCLR_IPS1_Pos       1            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 1 */
-#define TAL_SFLAGCLR_IPS1           (_U_(1) << TAL_SFLAGCLR_IPS1_Pos)
-#define TAL_SFLAGCLR_IPS2_Pos       2            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 2 */
-#define TAL_SFLAGCLR_IPS2           (_U_(1) << TAL_SFLAGCLR_IPS2_Pos)
-#define TAL_SFLAGCLR_IPS3_Pos       3            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 3 */
-#define TAL_SFLAGCLR_IPS3           (_U_(1) << TAL_SFLAGCLR_IPS3_Pos)
-#define TAL_SFLAGCLR_IPS4_Pos       4            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 4 */
-#define TAL_SFLAGCLR_IPS4           (_U_(1) << TAL_SFLAGCLR_IPS4_Pos)
-#define TAL_SFLAGCLR_IPS5_Pos       5            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 5 */
-#define TAL_SFLAGCLR_IPS5           (_U_(1) << TAL_SFLAGCLR_IPS5_Pos)
-#define TAL_SFLAGCLR_IPS6_Pos       6            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 6 */
-#define TAL_SFLAGCLR_IPS6           (_U_(1) << TAL_SFLAGCLR_IPS6_Pos)
-#define TAL_SFLAGCLR_IPS7_Pos       7            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 7 */
-#define TAL_SFLAGCLR_IPS7           (_U_(1) << TAL_SFLAGCLR_IPS7_Pos)
-#define TAL_SFLAGCLR_IPS8_Pos       8            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 8 */
-#define TAL_SFLAGCLR_IPS8           (_U_(1) << TAL_SFLAGCLR_IPS8_Pos)
-#define TAL_SFLAGCLR_IPS9_Pos       9            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 9 */
-#define TAL_SFLAGCLR_IPS9           (_U_(1) << TAL_SFLAGCLR_IPS9_Pos)
-#define TAL_SFLAGCLR_IPS10_Pos      10           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 10 */
-#define TAL_SFLAGCLR_IPS10          (_U_(1) << TAL_SFLAGCLR_IPS10_Pos)
-#define TAL_SFLAGCLR_IPS11_Pos      11           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 11 */
-#define TAL_SFLAGCLR_IPS11          (_U_(1) << TAL_SFLAGCLR_IPS11_Pos)
-#define TAL_SFLAGCLR_IPS12_Pos      12           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 12 */
-#define TAL_SFLAGCLR_IPS12          (_U_(1) << TAL_SFLAGCLR_IPS12_Pos)
-#define TAL_SFLAGCLR_IPS13_Pos      13           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 13 */
-#define TAL_SFLAGCLR_IPS13          (_U_(1) << TAL_SFLAGCLR_IPS13_Pos)
-#define TAL_SFLAGCLR_IPS14_Pos      14           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 14 */
-#define TAL_SFLAGCLR_IPS14          (_U_(1) << TAL_SFLAGCLR_IPS14_Pos)
-#define TAL_SFLAGCLR_IPS15_Pos      15           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 15 */
-#define TAL_SFLAGCLR_IPS15          (_U_(1) << TAL_SFLAGCLR_IPS15_Pos)
-#define TAL_SFLAGCLR_IPS16_Pos      16           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 16 */
-#define TAL_SFLAGCLR_IPS16          (_U_(1) << TAL_SFLAGCLR_IPS16_Pos)
-#define TAL_SFLAGCLR_IPS17_Pos      17           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 17 */
-#define TAL_SFLAGCLR_IPS17          (_U_(1) << TAL_SFLAGCLR_IPS17_Pos)
-#define TAL_SFLAGCLR_IPS18_Pos      18           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 18 */
-#define TAL_SFLAGCLR_IPS18          (_U_(1) << TAL_SFLAGCLR_IPS18_Pos)
-#define TAL_SFLAGCLR_IPS19_Pos      19           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 19 */
-#define TAL_SFLAGCLR_IPS19          (_U_(1) << TAL_SFLAGCLR_IPS19_Pos)
-#define TAL_SFLAGCLR_IPS20_Pos      20           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 20 */
-#define TAL_SFLAGCLR_IPS20          (_U_(1) << TAL_SFLAGCLR_IPS20_Pos)
-#define TAL_SFLAGCLR_IPS21_Pos      21           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 21 */
-#define TAL_SFLAGCLR_IPS21          (_U_(1) << TAL_SFLAGCLR_IPS21_Pos)
-#define TAL_SFLAGCLR_IPS22_Pos      22           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 22 */
-#define TAL_SFLAGCLR_IPS22          (_U_(1) << TAL_SFLAGCLR_IPS22_Pos)
-#define TAL_SFLAGCLR_IPS23_Pos      23           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 23 */
-#define TAL_SFLAGCLR_IPS23          (_U_(1) << TAL_SFLAGCLR_IPS23_Pos)
-#define TAL_SFLAGCLR_IPS24_Pos      24           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 24 */
-#define TAL_SFLAGCLR_IPS24          (_U_(1) << TAL_SFLAGCLR_IPS24_Pos)
-#define TAL_SFLAGCLR_IPS25_Pos      25           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 25 */
-#define TAL_SFLAGCLR_IPS25          (_U_(1) << TAL_SFLAGCLR_IPS25_Pos)
-#define TAL_SFLAGCLR_IPS26_Pos      26           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 26 */
-#define TAL_SFLAGCLR_IPS26          (_U_(1) << TAL_SFLAGCLR_IPS26_Pos)
-#define TAL_SFLAGCLR_IPS27_Pos      27           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 27 */
-#define TAL_SFLAGCLR_IPS27          (_U_(1) << TAL_SFLAGCLR_IPS27_Pos)
-#define TAL_SFLAGCLR_IPS28_Pos      28           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 28 */
-#define TAL_SFLAGCLR_IPS28          (_U_(1) << TAL_SFLAGCLR_IPS28_Pos)
-#define TAL_SFLAGCLR_IPS29_Pos      29           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 29 */
-#define TAL_SFLAGCLR_IPS29          (_U_(1) << TAL_SFLAGCLR_IPS29_Pos)
-#define TAL_SFLAGCLR_IPS30_Pos      30           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 30 */
-#define TAL_SFLAGCLR_IPS30          (_U_(1) << TAL_SFLAGCLR_IPS30_Pos)
-#define TAL_SFLAGCLR_IPS31_Pos      31           /**< \brief (TAL_SFLAGCLR) Inter-Process Signal 31 */
-#define TAL_SFLAGCLR_IPS31          (_U_(1) << TAL_SFLAGCLR_IPS31_Pos)
-#define TAL_SFLAGCLR_IPS_Pos        0            /**< \brief (TAL_SFLAGCLR) Inter-Process Signal x */
-#define TAL_SFLAGCLR_IPS_Msk        (_U_(0xFFFFFFFF) << TAL_SFLAGCLR_IPS_Pos)
-#define TAL_SFLAGCLR_IPS(value)     (TAL_SFLAGCLR_IPS_Msk & ((value) << TAL_SFLAGCLR_IPS_Pos))
-#define TAL_SFLAGCLR_MASK           _U_(0xFFFFFFFF) /**< \brief (TAL_SFLAGCLR) MASK Register */
-
-/* -------- TAL_SFLAGSET : (TAL Offset: 0x228) ( /W 32) Inter-Process Signal Flag Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t IPS0:1;           /*!< bit:      0  Inter-Process Signal 0             */
-    uint32_t IPS1:1;           /*!< bit:      1  Inter-Process Signal 1             */
-    uint32_t IPS2:1;           /*!< bit:      2  Inter-Process Signal 2             */
-    uint32_t IPS3:1;           /*!< bit:      3  Inter-Process Signal 3             */
-    uint32_t IPS4:1;           /*!< bit:      4  Inter-Process Signal 4             */
-    uint32_t IPS5:1;           /*!< bit:      5  Inter-Process Signal 5             */
-    uint32_t IPS6:1;           /*!< bit:      6  Inter-Process Signal 6             */
-    uint32_t IPS7:1;           /*!< bit:      7  Inter-Process Signal 7             */
-    uint32_t IPS8:1;           /*!< bit:      8  Inter-Process Signal 8             */
-    uint32_t IPS9:1;           /*!< bit:      9  Inter-Process Signal 9             */
-    uint32_t IPS10:1;          /*!< bit:     10  Inter-Process Signal 10            */
-    uint32_t IPS11:1;          /*!< bit:     11  Inter-Process Signal 11            */
-    uint32_t IPS12:1;          /*!< bit:     12  Inter-Process Signal 12            */
-    uint32_t IPS13:1;          /*!< bit:     13  Inter-Process Signal 13            */
-    uint32_t IPS14:1;          /*!< bit:     14  Inter-Process Signal 14            */
-    uint32_t IPS15:1;          /*!< bit:     15  Inter-Process Signal 15            */
-    uint32_t IPS16:1;          /*!< bit:     16  Inter-Process Signal 16            */
-    uint32_t IPS17:1;          /*!< bit:     17  Inter-Process Signal 17            */
-    uint32_t IPS18:1;          /*!< bit:     18  Inter-Process Signal 18            */
-    uint32_t IPS19:1;          /*!< bit:     19  Inter-Process Signal 19            */
-    uint32_t IPS20:1;          /*!< bit:     20  Inter-Process Signal 20            */
-    uint32_t IPS21:1;          /*!< bit:     21  Inter-Process Signal 21            */
-    uint32_t IPS22:1;          /*!< bit:     22  Inter-Process Signal 22            */
-    uint32_t IPS23:1;          /*!< bit:     23  Inter-Process Signal 23            */
-    uint32_t IPS24:1;          /*!< bit:     24  Inter-Process Signal 24            */
-    uint32_t IPS25:1;          /*!< bit:     25  Inter-Process Signal 25            */
-    uint32_t IPS26:1;          /*!< bit:     26  Inter-Process Signal 26            */
-    uint32_t IPS27:1;          /*!< bit:     27  Inter-Process Signal 27            */
-    uint32_t IPS28:1;          /*!< bit:     28  Inter-Process Signal 28            */
-    uint32_t IPS29:1;          /*!< bit:     29  Inter-Process Signal 29            */
-    uint32_t IPS30:1;          /*!< bit:     30  Inter-Process Signal 30            */
-    uint32_t IPS31:1;          /*!< bit:     31  Inter-Process Signal 31            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t IPS:32;           /*!< bit:  0..31  Inter-Process Signal x             */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_SFLAGSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_SFLAGSET_OFFSET         0x228        /**< \brief (TAL_SFLAGSET offset) Inter-Process Signal Flag Set */
-#define TAL_SFLAGSET_RESETVALUE     _U_(0x00000000) /**< \brief (TAL_SFLAGSET reset_value) Inter-Process Signal Flag Set */
-
-#define TAL_SFLAGSET_IPS0_Pos       0            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 0 */
-#define TAL_SFLAGSET_IPS0           (_U_(1) << TAL_SFLAGSET_IPS0_Pos)
-#define TAL_SFLAGSET_IPS1_Pos       1            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 1 */
-#define TAL_SFLAGSET_IPS1           (_U_(1) << TAL_SFLAGSET_IPS1_Pos)
-#define TAL_SFLAGSET_IPS2_Pos       2            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 2 */
-#define TAL_SFLAGSET_IPS2           (_U_(1) << TAL_SFLAGSET_IPS2_Pos)
-#define TAL_SFLAGSET_IPS3_Pos       3            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 3 */
-#define TAL_SFLAGSET_IPS3           (_U_(1) << TAL_SFLAGSET_IPS3_Pos)
-#define TAL_SFLAGSET_IPS4_Pos       4            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 4 */
-#define TAL_SFLAGSET_IPS4           (_U_(1) << TAL_SFLAGSET_IPS4_Pos)
-#define TAL_SFLAGSET_IPS5_Pos       5            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 5 */
-#define TAL_SFLAGSET_IPS5           (_U_(1) << TAL_SFLAGSET_IPS5_Pos)
-#define TAL_SFLAGSET_IPS6_Pos       6            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 6 */
-#define TAL_SFLAGSET_IPS6           (_U_(1) << TAL_SFLAGSET_IPS6_Pos)
-#define TAL_SFLAGSET_IPS7_Pos       7            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 7 */
-#define TAL_SFLAGSET_IPS7           (_U_(1) << TAL_SFLAGSET_IPS7_Pos)
-#define TAL_SFLAGSET_IPS8_Pos       8            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 8 */
-#define TAL_SFLAGSET_IPS8           (_U_(1) << TAL_SFLAGSET_IPS8_Pos)
-#define TAL_SFLAGSET_IPS9_Pos       9            /**< \brief (TAL_SFLAGSET) Inter-Process Signal 9 */
-#define TAL_SFLAGSET_IPS9           (_U_(1) << TAL_SFLAGSET_IPS9_Pos)
-#define TAL_SFLAGSET_IPS10_Pos      10           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 10 */
-#define TAL_SFLAGSET_IPS10          (_U_(1) << TAL_SFLAGSET_IPS10_Pos)
-#define TAL_SFLAGSET_IPS11_Pos      11           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 11 */
-#define TAL_SFLAGSET_IPS11          (_U_(1) << TAL_SFLAGSET_IPS11_Pos)
-#define TAL_SFLAGSET_IPS12_Pos      12           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 12 */
-#define TAL_SFLAGSET_IPS12          (_U_(1) << TAL_SFLAGSET_IPS12_Pos)
-#define TAL_SFLAGSET_IPS13_Pos      13           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 13 */
-#define TAL_SFLAGSET_IPS13          (_U_(1) << TAL_SFLAGSET_IPS13_Pos)
-#define TAL_SFLAGSET_IPS14_Pos      14           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 14 */
-#define TAL_SFLAGSET_IPS14          (_U_(1) << TAL_SFLAGSET_IPS14_Pos)
-#define TAL_SFLAGSET_IPS15_Pos      15           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 15 */
-#define TAL_SFLAGSET_IPS15          (_U_(1) << TAL_SFLAGSET_IPS15_Pos)
-#define TAL_SFLAGSET_IPS16_Pos      16           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 16 */
-#define TAL_SFLAGSET_IPS16          (_U_(1) << TAL_SFLAGSET_IPS16_Pos)
-#define TAL_SFLAGSET_IPS17_Pos      17           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 17 */
-#define TAL_SFLAGSET_IPS17          (_U_(1) << TAL_SFLAGSET_IPS17_Pos)
-#define TAL_SFLAGSET_IPS18_Pos      18           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 18 */
-#define TAL_SFLAGSET_IPS18          (_U_(1) << TAL_SFLAGSET_IPS18_Pos)
-#define TAL_SFLAGSET_IPS19_Pos      19           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 19 */
-#define TAL_SFLAGSET_IPS19          (_U_(1) << TAL_SFLAGSET_IPS19_Pos)
-#define TAL_SFLAGSET_IPS20_Pos      20           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 20 */
-#define TAL_SFLAGSET_IPS20          (_U_(1) << TAL_SFLAGSET_IPS20_Pos)
-#define TAL_SFLAGSET_IPS21_Pos      21           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 21 */
-#define TAL_SFLAGSET_IPS21          (_U_(1) << TAL_SFLAGSET_IPS21_Pos)
-#define TAL_SFLAGSET_IPS22_Pos      22           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 22 */
-#define TAL_SFLAGSET_IPS22          (_U_(1) << TAL_SFLAGSET_IPS22_Pos)
-#define TAL_SFLAGSET_IPS23_Pos      23           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 23 */
-#define TAL_SFLAGSET_IPS23          (_U_(1) << TAL_SFLAGSET_IPS23_Pos)
-#define TAL_SFLAGSET_IPS24_Pos      24           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 24 */
-#define TAL_SFLAGSET_IPS24          (_U_(1) << TAL_SFLAGSET_IPS24_Pos)
-#define TAL_SFLAGSET_IPS25_Pos      25           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 25 */
-#define TAL_SFLAGSET_IPS25          (_U_(1) << TAL_SFLAGSET_IPS25_Pos)
-#define TAL_SFLAGSET_IPS26_Pos      26           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 26 */
-#define TAL_SFLAGSET_IPS26          (_U_(1) << TAL_SFLAGSET_IPS26_Pos)
-#define TAL_SFLAGSET_IPS27_Pos      27           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 27 */
-#define TAL_SFLAGSET_IPS27          (_U_(1) << TAL_SFLAGSET_IPS27_Pos)
-#define TAL_SFLAGSET_IPS28_Pos      28           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 28 */
-#define TAL_SFLAGSET_IPS28          (_U_(1) << TAL_SFLAGSET_IPS28_Pos)
-#define TAL_SFLAGSET_IPS29_Pos      29           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 29 */
-#define TAL_SFLAGSET_IPS29          (_U_(1) << TAL_SFLAGSET_IPS29_Pos)
-#define TAL_SFLAGSET_IPS30_Pos      30           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 30 */
-#define TAL_SFLAGSET_IPS30          (_U_(1) << TAL_SFLAGSET_IPS30_Pos)
-#define TAL_SFLAGSET_IPS31_Pos      31           /**< \brief (TAL_SFLAGSET) Inter-Process Signal 31 */
-#define TAL_SFLAGSET_IPS31          (_U_(1) << TAL_SFLAGSET_IPS31_Pos)
-#define TAL_SFLAGSET_IPS_Pos        0            /**< \brief (TAL_SFLAGSET) Inter-Process Signal x */
-#define TAL_SFLAGSET_IPS_Msk        (_U_(0xFFFFFFFF) << TAL_SFLAGSET_IPS_Pos)
-#define TAL_SFLAGSET_IPS(value)     (TAL_SFLAGSET_IPS_Msk & ((value) << TAL_SFLAGSET_IPS_Pos))
-#define TAL_SFLAGSET_MASK           _U_(0xFFFFFFFF) /**< \brief (TAL_SFLAGSET) MASK Register */
-
-/* -------- TAL_SFLAG : (TAL Offset: 0x230) (R/  32) Inter-Process Signal Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t IPS0:1;           /*!< bit:      0  Inter-Process Signal 0             */
-    uint32_t IPS1:1;           /*!< bit:      1  Inter-Process Signal 1             */
-    uint32_t IPS2:1;           /*!< bit:      2  Inter-Process Signal 2             */
-    uint32_t IPS3:1;           /*!< bit:      3  Inter-Process Signal 3             */
-    uint32_t IPS4:1;           /*!< bit:      4  Inter-Process Signal 4             */
-    uint32_t IPS5:1;           /*!< bit:      5  Inter-Process Signal 5             */
-    uint32_t IPS6:1;           /*!< bit:      6  Inter-Process Signal 6             */
-    uint32_t IPS7:1;           /*!< bit:      7  Inter-Process Signal 7             */
-    uint32_t IPS8:1;           /*!< bit:      8  Inter-Process Signal 8             */
-    uint32_t IPS9:1;           /*!< bit:      9  Inter-Process Signal 9             */
-    uint32_t IPS10:1;          /*!< bit:     10  Inter-Process Signal 10            */
-    uint32_t IPS11:1;          /*!< bit:     11  Inter-Process Signal 11            */
-    uint32_t IPS12:1;          /*!< bit:     12  Inter-Process Signal 12            */
-    uint32_t IPS13:1;          /*!< bit:     13  Inter-Process Signal 13            */
-    uint32_t IPS14:1;          /*!< bit:     14  Inter-Process Signal 14            */
-    uint32_t IPS15:1;          /*!< bit:     15  Inter-Process Signal 15            */
-    uint32_t IPS16:1;          /*!< bit:     16  Inter-Process Signal 16            */
-    uint32_t IPS17:1;          /*!< bit:     17  Inter-Process Signal 17            */
-    uint32_t IPS18:1;          /*!< bit:     18  Inter-Process Signal 18            */
-    uint32_t IPS19:1;          /*!< bit:     19  Inter-Process Signal 19            */
-    uint32_t IPS20:1;          /*!< bit:     20  Inter-Process Signal 20            */
-    uint32_t IPS21:1;          /*!< bit:     21  Inter-Process Signal 21            */
-    uint32_t IPS22:1;          /*!< bit:     22  Inter-Process Signal 22            */
-    uint32_t IPS23:1;          /*!< bit:     23  Inter-Process Signal 23            */
-    uint32_t IPS24:1;          /*!< bit:     24  Inter-Process Signal 24            */
-    uint32_t IPS25:1;          /*!< bit:     25  Inter-Process Signal 25            */
-    uint32_t IPS26:1;          /*!< bit:     26  Inter-Process Signal 26            */
-    uint32_t IPS27:1;          /*!< bit:     27  Inter-Process Signal 27            */
-    uint32_t IPS28:1;          /*!< bit:     28  Inter-Process Signal 28            */
-    uint32_t IPS29:1;          /*!< bit:     29  Inter-Process Signal 29            */
-    uint32_t IPS30:1;          /*!< bit:     30  Inter-Process Signal 30            */
-    uint32_t IPS31:1;          /*!< bit:     31  Inter-Process Signal 31            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t IPS:32;           /*!< bit:  0..31  Inter-Process Signal x             */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TAL_SFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_SFLAG_OFFSET            0x230        /**< \brief (TAL_SFLAG offset) Inter-Process Signal Flag */
-#define TAL_SFLAG_RESETVALUE        _U_(0x00000000) /**< \brief (TAL_SFLAG reset_value) Inter-Process Signal Flag */
-
-#define TAL_SFLAG_IPS0_Pos          0            /**< \brief (TAL_SFLAG) Inter-Process Signal 0 */
-#define TAL_SFLAG_IPS0              (_U_(1) << TAL_SFLAG_IPS0_Pos)
-#define TAL_SFLAG_IPS1_Pos          1            /**< \brief (TAL_SFLAG) Inter-Process Signal 1 */
-#define TAL_SFLAG_IPS1              (_U_(1) << TAL_SFLAG_IPS1_Pos)
-#define TAL_SFLAG_IPS2_Pos          2            /**< \brief (TAL_SFLAG) Inter-Process Signal 2 */
-#define TAL_SFLAG_IPS2              (_U_(1) << TAL_SFLAG_IPS2_Pos)
-#define TAL_SFLAG_IPS3_Pos          3            /**< \brief (TAL_SFLAG) Inter-Process Signal 3 */
-#define TAL_SFLAG_IPS3              (_U_(1) << TAL_SFLAG_IPS3_Pos)
-#define TAL_SFLAG_IPS4_Pos          4            /**< \brief (TAL_SFLAG) Inter-Process Signal 4 */
-#define TAL_SFLAG_IPS4              (_U_(1) << TAL_SFLAG_IPS4_Pos)
-#define TAL_SFLAG_IPS5_Pos          5            /**< \brief (TAL_SFLAG) Inter-Process Signal 5 */
-#define TAL_SFLAG_IPS5              (_U_(1) << TAL_SFLAG_IPS5_Pos)
-#define TAL_SFLAG_IPS6_Pos          6            /**< \brief (TAL_SFLAG) Inter-Process Signal 6 */
-#define TAL_SFLAG_IPS6              (_U_(1) << TAL_SFLAG_IPS6_Pos)
-#define TAL_SFLAG_IPS7_Pos          7            /**< \brief (TAL_SFLAG) Inter-Process Signal 7 */
-#define TAL_SFLAG_IPS7              (_U_(1) << TAL_SFLAG_IPS7_Pos)
-#define TAL_SFLAG_IPS8_Pos          8            /**< \brief (TAL_SFLAG) Inter-Process Signal 8 */
-#define TAL_SFLAG_IPS8              (_U_(1) << TAL_SFLAG_IPS8_Pos)
-#define TAL_SFLAG_IPS9_Pos          9            /**< \brief (TAL_SFLAG) Inter-Process Signal 9 */
-#define TAL_SFLAG_IPS9              (_U_(1) << TAL_SFLAG_IPS9_Pos)
-#define TAL_SFLAG_IPS10_Pos         10           /**< \brief (TAL_SFLAG) Inter-Process Signal 10 */
-#define TAL_SFLAG_IPS10             (_U_(1) << TAL_SFLAG_IPS10_Pos)
-#define TAL_SFLAG_IPS11_Pos         11           /**< \brief (TAL_SFLAG) Inter-Process Signal 11 */
-#define TAL_SFLAG_IPS11             (_U_(1) << TAL_SFLAG_IPS11_Pos)
-#define TAL_SFLAG_IPS12_Pos         12           /**< \brief (TAL_SFLAG) Inter-Process Signal 12 */
-#define TAL_SFLAG_IPS12             (_U_(1) << TAL_SFLAG_IPS12_Pos)
-#define TAL_SFLAG_IPS13_Pos         13           /**< \brief (TAL_SFLAG) Inter-Process Signal 13 */
-#define TAL_SFLAG_IPS13             (_U_(1) << TAL_SFLAG_IPS13_Pos)
-#define TAL_SFLAG_IPS14_Pos         14           /**< \brief (TAL_SFLAG) Inter-Process Signal 14 */
-#define TAL_SFLAG_IPS14             (_U_(1) << TAL_SFLAG_IPS14_Pos)
-#define TAL_SFLAG_IPS15_Pos         15           /**< \brief (TAL_SFLAG) Inter-Process Signal 15 */
-#define TAL_SFLAG_IPS15             (_U_(1) << TAL_SFLAG_IPS15_Pos)
-#define TAL_SFLAG_IPS16_Pos         16           /**< \brief (TAL_SFLAG) Inter-Process Signal 16 */
-#define TAL_SFLAG_IPS16             (_U_(1) << TAL_SFLAG_IPS16_Pos)
-#define TAL_SFLAG_IPS17_Pos         17           /**< \brief (TAL_SFLAG) Inter-Process Signal 17 */
-#define TAL_SFLAG_IPS17             (_U_(1) << TAL_SFLAG_IPS17_Pos)
-#define TAL_SFLAG_IPS18_Pos         18           /**< \brief (TAL_SFLAG) Inter-Process Signal 18 */
-#define TAL_SFLAG_IPS18             (_U_(1) << TAL_SFLAG_IPS18_Pos)
-#define TAL_SFLAG_IPS19_Pos         19           /**< \brief (TAL_SFLAG) Inter-Process Signal 19 */
-#define TAL_SFLAG_IPS19             (_U_(1) << TAL_SFLAG_IPS19_Pos)
-#define TAL_SFLAG_IPS20_Pos         20           /**< \brief (TAL_SFLAG) Inter-Process Signal 20 */
-#define TAL_SFLAG_IPS20             (_U_(1) << TAL_SFLAG_IPS20_Pos)
-#define TAL_SFLAG_IPS21_Pos         21           /**< \brief (TAL_SFLAG) Inter-Process Signal 21 */
-#define TAL_SFLAG_IPS21             (_U_(1) << TAL_SFLAG_IPS21_Pos)
-#define TAL_SFLAG_IPS22_Pos         22           /**< \brief (TAL_SFLAG) Inter-Process Signal 22 */
-#define TAL_SFLAG_IPS22             (_U_(1) << TAL_SFLAG_IPS22_Pos)
-#define TAL_SFLAG_IPS23_Pos         23           /**< \brief (TAL_SFLAG) Inter-Process Signal 23 */
-#define TAL_SFLAG_IPS23             (_U_(1) << TAL_SFLAG_IPS23_Pos)
-#define TAL_SFLAG_IPS24_Pos         24           /**< \brief (TAL_SFLAG) Inter-Process Signal 24 */
-#define TAL_SFLAG_IPS24             (_U_(1) << TAL_SFLAG_IPS24_Pos)
-#define TAL_SFLAG_IPS25_Pos         25           /**< \brief (TAL_SFLAG) Inter-Process Signal 25 */
-#define TAL_SFLAG_IPS25             (_U_(1) << TAL_SFLAG_IPS25_Pos)
-#define TAL_SFLAG_IPS26_Pos         26           /**< \brief (TAL_SFLAG) Inter-Process Signal 26 */
-#define TAL_SFLAG_IPS26             (_U_(1) << TAL_SFLAG_IPS26_Pos)
-#define TAL_SFLAG_IPS27_Pos         27           /**< \brief (TAL_SFLAG) Inter-Process Signal 27 */
-#define TAL_SFLAG_IPS27             (_U_(1) << TAL_SFLAG_IPS27_Pos)
-#define TAL_SFLAG_IPS28_Pos         28           /**< \brief (TAL_SFLAG) Inter-Process Signal 28 */
-#define TAL_SFLAG_IPS28             (_U_(1) << TAL_SFLAG_IPS28_Pos)
-#define TAL_SFLAG_IPS29_Pos         29           /**< \brief (TAL_SFLAG) Inter-Process Signal 29 */
-#define TAL_SFLAG_IPS29             (_U_(1) << TAL_SFLAG_IPS29_Pos)
-#define TAL_SFLAG_IPS30_Pos         30           /**< \brief (TAL_SFLAG) Inter-Process Signal 30 */
-#define TAL_SFLAG_IPS30             (_U_(1) << TAL_SFLAG_IPS30_Pos)
-#define TAL_SFLAG_IPS31_Pos         31           /**< \brief (TAL_SFLAG) Inter-Process Signal 31 */
-#define TAL_SFLAG_IPS31             (_U_(1) << TAL_SFLAG_IPS31_Pos)
-#define TAL_SFLAG_IPS_Pos           0            /**< \brief (TAL_SFLAG) Inter-Process Signal x */
-#define TAL_SFLAG_IPS_Msk           (_U_(0xFFFFFFFF) << TAL_SFLAG_IPS_Pos)
-#define TAL_SFLAG_IPS(value)        (TAL_SFLAG_IPS_Msk & ((value) << TAL_SFLAG_IPS_Pos))
-#define TAL_SFLAG_MASK              _U_(0xFFFFFFFF) /**< \brief (TAL_SFLAG) MASK Register */
-
-/* -------- TAL_SFLAGCLRR : (TAL Offset: 0x300) (R/W  8) Inter-Process Signal Flag Bit n -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  IPS:1;            /*!< bit:      0  Inter-Process Signal n             */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TAL_SFLAGCLRR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TAL_SFLAGCLRR_OFFSET        0x300        /**< \brief (TAL_SFLAGCLRR offset) Inter-Process Signal Flag Bit n */
-#define TAL_SFLAGCLRR_RESETVALUE    _U_(0x00)    /**< \brief (TAL_SFLAGCLRR reset_value) Inter-Process Signal Flag Bit n */
-
-#define TAL_SFLAGCLRR_IPS_Pos       0            /**< \brief (TAL_SFLAGCLRR) Inter-Process Signal n */
-#define TAL_SFLAGCLRR_IPS           (_U_(0x1) << TAL_SFLAGCLRR_IPS_Pos)
-#define TAL_SFLAGCLRR_MASK          _U_(0x01)    /**< \brief (TAL_SFLAGCLRR) MASK Register */
-
-/** \brief TalCpuirqs hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __I  TAL_CPUIRQS_Type          CPUIRQS[5];  /**< \brief Offset: 0x000 (R/  32) Interrupt Status m for CPU n */
-       RoReg8                    Reserved1[0xC];
-} TalCpuirqs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief TalCtis hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO TAL_CTICTRLA_Type         CTICTRLA;    /**< \brief Offset: 0x000 (R/W  8) Cross-Trigger Interface n Control A */
-  __IO TAL_CTIMASK_Type          CTIMASK;     /**< \brief Offset: 0x001 (R/W  8) Cross-Trigger Interface n Mask */
-} TalCtis;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief TalSmasks hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO TAL_SMASK_Type            SMASK[2];    /**< \brief Offset: 0x000 (R/W 32) Inter-Process Signal Mask m for CPU n */
-} TalSmasks;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief TAL hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO TAL_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
-  __IO TAL_EXTCTRL_Type          EXTCTRL;     /**< \brief Offset: 0x001 (R/W  8) External Break Control */
-       RoReg8                    Reserved1[0x2];
-  __IO TAL_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x004 (R/W 16) Event Control */
-       RoReg8                    Reserved2[0x2];
-  __IO TAL_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x008 (R/W  8) Interrupt Enable Clear */
-  __IO TAL_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x009 (R/W  8) Interrupt Enable Set */
-  __IO TAL_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x00A (R/W  8) Interrupt Flag Status and Clear */
-  __IO TAL_GLOBMASK_Type         GLOBMASK;    /**< \brief Offset: 0x00B (R/W  8) Global Break Requests Mask */
-  __O  TAL_HALT_Type             HALT;        /**< \brief Offset: 0x00C ( /W  8) Debug Halt Request */
-  __O  TAL_RESTART_Type          RESTART;     /**< \brief Offset: 0x00D ( /W  8) Debug Restart Request */
-  __I  TAL_BRKSTATUS_Type        BRKSTATUS;   /**< \brief Offset: 0x00E (R/  16) Break Request Status */
-       TalCtis                   Ctis[4];     /**< \brief Offset: 0x010 TalCtis groups [CTI_NUM] */
-       RoReg8                    Reserved3[0x8];
-  __I  TAL_INTSTATUS_Type        INTSTATUS[137]; /**< \brief Offset: 0x020 (R/   8) Interrupt n Status */
-       RoReg8                    Reserved4[0x67];
-  __IO TAL_DMACPUSEL0_Type       DMACPUSEL0;  /**< \brief Offset: 0x110 (R/W 32) DMA Channel Interrupts CPU Select 0 */
-  __IO TAL_DMACPUSEL1_Type       DMACPUSEL1;  /**< \brief Offset: 0x114 (R/W 32) DMA Channel Interrupts CPU Select 1 */
-  __IO TAL_EVCPUSEL0_Type        EVCPUSEL0;   /**< \brief Offset: 0x118 (R/W 32) EVSYS Channel Interrupts CPU Select 0 */
-       RoReg8                    Reserved5[0x4];
-  __IO TAL_EICCPUSEL0_Type       EICCPUSEL0;  /**< \brief Offset: 0x120 (R/W 32) EIC External Interrupts CPU Select 0 */
-       RoReg8                    Reserved6[0x4];
-  __IO TAL_INTCPUSEL0_Type       INTCPUSEL0;  /**< \brief Offset: 0x128 (R/W 32) Interrupts CPU Select 0 */
-  __IO TAL_INTCPUSEL1_Type       INTCPUSEL1;  /**< \brief Offset: 0x12C (R/W 32) Interrupts CPU Select 1 */
-  __IO TAL_INTCPUSEL2_Type       INTCPUSEL2;  /**< \brief Offset: 0x130 (R/W 32) Interrupts CPU Select 2 */
-  __IO TAL_INTCPUSEL3_Type       INTCPUSEL3;  /**< \brief Offset: 0x134 (R/W 32) Interrupts CPU Select 3 */
-  __IO TAL_INTCPUSEL4_Type       INTCPUSEL4;  /**< \brief Offset: 0x138 (R/W 32) Interrupts CPU Select 4 */
-  __IO TAL_INTCPUSEL5_Type       INTCPUSEL5;  /**< \brief Offset: 0x13C (R/W 32) Interrupts CPU Select 5 */
-  __IO TAL_INTCPUSEL6_Type       INTCPUSEL6;  /**< \brief Offset: 0x140 (R/W 32) Interrupts CPU Select 6 */
-  __IO TAL_INTCPUSEL7_Type       INTCPUSEL7;  /**< \brief Offset: 0x144 (R/W 32) Interrupts CPU Select 7 */
-  __IO TAL_INTCPUSEL8_Type       INTCPUSEL8;  /**< \brief Offset: 0x148 (R/W 32) Interrupts CPU Select 8 */
-       RoReg8                    Reserved7[0x18];
-  __IO TAL_IRQTRIG_Type          IRQTRIG;     /**< \brief Offset: 0x164 (R/W 32) Interrupt Trigger */
-  __IO TAL_IRQMON_Type           IRQMON[1];   /**< \brief Offset: 0x168 (R/W 16) Interrupt Monitor Select */
-       RoReg8                    Reserved8[0x16];
-       TalCpuirqs                Cpuirqs[2];  /**< \brief Offset: 0x180 TalCpuirqs groups [CPU_NUM] */
-       RoReg8                    Reserved9[0x40];
-       TalSmasks                 Smasks[2];   /**< \brief Offset: 0x200 TalSmasks groups [CPU_NUM] */
-       RoReg8                    Reserved10[0x10];
-  __O  TAL_SFLAGCLR_Type         SFLAGCLR[2]; /**< \brief Offset: 0x220 ( /W 32) Inter-Process Signal Flag Clear */
-  __O  TAL_SFLAGSET_Type         SFLAGSET[2]; /**< \brief Offset: 0x228 ( /W 32) Inter-Process Signal Flag Set */
-  __I  TAL_SFLAG_Type            SFLAG[2];    /**< \brief Offset: 0x230 (R/  32) Inter-Process Signal Flag */
-       RoReg8                    Reserved11[0xC8];
-  __IO TAL_SFLAGCLRR_Type        SFLAGCLRR[64]; /**< \brief Offset: 0x300 (R/W  8) Inter-Process Signal Flag Bit n */
-} Tal;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_TAL_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tc.h
deleted file mode 100644
index f4c0daf344..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tc.h
+++ /dev/null
@@ -1,851 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for TC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TC_COMPONENT_
-#define _SAMD51_TC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR TC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_TC Basic Timer Counter */
-/*@{*/
-
-#define TC_U2249
-#define REV_TC                      0x300
-
-/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t MODE:2;           /*!< bit:  2.. 3  Timer Counter Mode                 */
-    uint32_t PRESCSYNC:2;      /*!< bit:  4.. 5  Prescaler and Counter Synchronization */
-    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
-    uint32_t ONDEMAND:1;       /*!< bit:      7  Clock On Demand                    */
-    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
-    uint32_t ALOCK:1;          /*!< bit:     11  Auto Lock                          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t CAPTEN0:1;        /*!< bit:     16  Capture Channel 0 Enable           */
-    uint32_t CAPTEN1:1;        /*!< bit:     17  Capture Channel 1 Enable           */
-    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
-    uint32_t COPEN0:1;         /*!< bit:     20  Capture On Pin 0 Enable            */
-    uint32_t COPEN1:1;         /*!< bit:     21  Capture On Pin 1 Enable            */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t CAPTMODE0:2;      /*!< bit: 24..25  Capture Mode Channel 0             */
-    uint32_t :1;               /*!< bit:     26  Reserved                           */
-    uint32_t CAPTMODE1:2;      /*!< bit: 27..28  Capture mode Channel 1             */
-    uint32_t :3;               /*!< bit: 29..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t CAPTEN:2;         /*!< bit: 16..17  Capture Channel x Enable           */
-    uint32_t :2;               /*!< bit: 18..19  Reserved                           */
-    uint32_t COPEN:2;          /*!< bit: 20..21  Capture On Pin x Enable            */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLA_OFFSET             0x00         /**< \brief (TC_CTRLA offset) Control A */
-#define TC_CTRLA_RESETVALUE         _U_(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */
-
-#define TC_CTRLA_SWRST_Pos          0            /**< \brief (TC_CTRLA) Software Reset */
-#define TC_CTRLA_SWRST              (_U_(0x1) << TC_CTRLA_SWRST_Pos)
-#define TC_CTRLA_ENABLE_Pos         1            /**< \brief (TC_CTRLA) Enable */
-#define TC_CTRLA_ENABLE             (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
-#define TC_CTRLA_MODE_Pos           2            /**< \brief (TC_CTRLA) Timer Counter Mode */
-#define TC_CTRLA_MODE_Msk           (_U_(0x3) << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_MODE(value)        (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
-#define   TC_CTRLA_MODE_COUNT16_Val       _U_(0x0)   /**< \brief (TC_CTRLA) Counter in 16-bit mode */
-#define   TC_CTRLA_MODE_COUNT8_Val        _U_(0x1)   /**< \brief (TC_CTRLA) Counter in 8-bit mode */
-#define   TC_CTRLA_MODE_COUNT32_Val       _U_(0x2)   /**< \brief (TC_CTRLA) Counter in 32-bit mode */
-#define TC_CTRLA_MODE_COUNT16       (TC_CTRLA_MODE_COUNT16_Val     << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_MODE_COUNT8        (TC_CTRLA_MODE_COUNT8_Val      << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_MODE_COUNT32       (TC_CTRLA_MODE_COUNT32_Val     << TC_CTRLA_MODE_Pos)
-#define TC_CTRLA_PRESCSYNC_Pos      4            /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
-#define TC_CTRLA_PRESCSYNC_Msk      (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_PRESCSYNC(value)   (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
-#define   TC_CTRLA_PRESCSYNC_GCLK_Val     _U_(0x0)   /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
-#define   TC_CTRLA_PRESCSYNC_PRESC_Val    _U_(0x1)   /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
-#define   TC_CTRLA_PRESCSYNC_RESYNC_Val   _U_(0x2)   /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */
-#define TC_CTRLA_PRESCSYNC_GCLK     (TC_CTRLA_PRESCSYNC_GCLK_Val   << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_PRESCSYNC_PRESC    (TC_CTRLA_PRESCSYNC_PRESC_Val  << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_PRESCSYNC_RESYNC   (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
-#define TC_CTRLA_RUNSTDBY_Pos       6            /**< \brief (TC_CTRLA) Run during Standby */
-#define TC_CTRLA_RUNSTDBY           (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
-#define TC_CTRLA_ONDEMAND_Pos       7            /**< \brief (TC_CTRLA) Clock On Demand */
-#define TC_CTRLA_ONDEMAND           (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
-#define TC_CTRLA_PRESCALER_Pos      8            /**< \brief (TC_CTRLA) Prescaler */
-#define TC_CTRLA_PRESCALER_Msk      (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER(value)   (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
-#define   TC_CTRLA_PRESCALER_DIV1_Val     _U_(0x0)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
-#define   TC_CTRLA_PRESCALER_DIV2_Val     _U_(0x1)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
-#define   TC_CTRLA_PRESCALER_DIV4_Val     _U_(0x2)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
-#define   TC_CTRLA_PRESCALER_DIV8_Val     _U_(0x3)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
-#define   TC_CTRLA_PRESCALER_DIV16_Val    _U_(0x4)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
-#define   TC_CTRLA_PRESCALER_DIV64_Val    _U_(0x5)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
-#define   TC_CTRLA_PRESCALER_DIV256_Val   _U_(0x6)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
-#define   TC_CTRLA_PRESCALER_DIV1024_Val  _U_(0x7)   /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
-#define TC_CTRLA_PRESCALER_DIV1     (TC_CTRLA_PRESCALER_DIV1_Val   << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV2     (TC_CTRLA_PRESCALER_DIV2_Val   << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV4     (TC_CTRLA_PRESCALER_DIV4_Val   << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV8     (TC_CTRLA_PRESCALER_DIV8_Val   << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV16    (TC_CTRLA_PRESCALER_DIV16_Val  << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV64    (TC_CTRLA_PRESCALER_DIV64_Val  << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV256   (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_PRESCALER_DIV1024  (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
-#define TC_CTRLA_ALOCK_Pos          11           /**< \brief (TC_CTRLA) Auto Lock */
-#define TC_CTRLA_ALOCK              (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
-#define TC_CTRLA_CAPTEN0_Pos        16           /**< \brief (TC_CTRLA) Capture Channel 0 Enable */
-#define TC_CTRLA_CAPTEN0            (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
-#define TC_CTRLA_CAPTEN1_Pos        17           /**< \brief (TC_CTRLA) Capture Channel 1 Enable */
-#define TC_CTRLA_CAPTEN1            (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
-#define TC_CTRLA_CAPTEN_Pos         16           /**< \brief (TC_CTRLA) Capture Channel x Enable */
-#define TC_CTRLA_CAPTEN_Msk         (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
-#define TC_CTRLA_CAPTEN(value)      (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
-#define TC_CTRLA_COPEN0_Pos         20           /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */
-#define TC_CTRLA_COPEN0             (_U_(1) << TC_CTRLA_COPEN0_Pos)
-#define TC_CTRLA_COPEN1_Pos         21           /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */
-#define TC_CTRLA_COPEN1             (_U_(1) << TC_CTRLA_COPEN1_Pos)
-#define TC_CTRLA_COPEN_Pos          20           /**< \brief (TC_CTRLA) Capture On Pin x Enable */
-#define TC_CTRLA_COPEN_Msk          (_U_(0x3) << TC_CTRLA_COPEN_Pos)
-#define TC_CTRLA_COPEN(value)       (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
-#define TC_CTRLA_CAPTMODE0_Pos      24           /**< \brief (TC_CTRLA) Capture Mode Channel 0 */
-#define TC_CTRLA_CAPTMODE0_Msk      (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos)
-#define TC_CTRLA_CAPTMODE0(value)   (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
-#define   TC_CTRLA_CAPTMODE0_DEFAULT_Val  _U_(0x0)   /**< \brief (TC_CTRLA) Default capture */
-#define   TC_CTRLA_CAPTMODE0_CAPTMIN_Val  _U_(0x1)   /**< \brief (TC_CTRLA) Minimum capture */
-#define   TC_CTRLA_CAPTMODE0_CAPTMAX_Val  _U_(0x2)   /**< \brief (TC_CTRLA) Maximum capture */
-#define TC_CTRLA_CAPTMODE0_DEFAULT  (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos)
-#define TC_CTRLA_CAPTMODE0_CAPTMIN  (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos)
-#define TC_CTRLA_CAPTMODE0_CAPTMAX  (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos)
-#define TC_CTRLA_CAPTMODE1_Pos      27           /**< \brief (TC_CTRLA) Capture mode Channel 1 */
-#define TC_CTRLA_CAPTMODE1_Msk      (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos)
-#define TC_CTRLA_CAPTMODE1(value)   (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
-#define   TC_CTRLA_CAPTMODE1_DEFAULT_Val  _U_(0x0)   /**< \brief (TC_CTRLA) Default capture */
-#define   TC_CTRLA_CAPTMODE1_CAPTMIN_Val  _U_(0x1)   /**< \brief (TC_CTRLA) Minimum capture */
-#define   TC_CTRLA_CAPTMODE1_CAPTMAX_Val  _U_(0x2)   /**< \brief (TC_CTRLA) Maximum capture */
-#define TC_CTRLA_CAPTMODE1_DEFAULT  (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos)
-#define TC_CTRLA_CAPTMODE1_CAPTMIN  (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos)
-#define TC_CTRLA_CAPTMODE1_CAPTMAX  (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos)
-#define TC_CTRLA_MASK               _U_(0x1B330FFF) /**< \brief (TC_CTRLA) MASK Register */
-
-/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W  8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot on Counter                */
-    uint8_t  :2;               /*!< bit:  3.. 4  Reserved                           */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  Command                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLBCLR_OFFSET          0x04         /**< \brief (TC_CTRLBCLR offset) Control B Clear */
-#define TC_CTRLBCLR_RESETVALUE      _U_(0x00)    /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
-
-#define TC_CTRLBCLR_DIR_Pos         0            /**< \brief (TC_CTRLBCLR) Counter Direction */
-#define TC_CTRLBCLR_DIR             (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
-#define TC_CTRLBCLR_LUPD_Pos        1            /**< \brief (TC_CTRLBCLR) Lock Update */
-#define TC_CTRLBCLR_LUPD            (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
-#define TC_CTRLBCLR_ONESHOT_Pos     2            /**< \brief (TC_CTRLBCLR) One-Shot on Counter */
-#define TC_CTRLBCLR_ONESHOT         (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
-#define TC_CTRLBCLR_CMD_Pos         5            /**< \brief (TC_CTRLBCLR) Command */
-#define TC_CTRLBCLR_CMD_Msk         (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD(value)      (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
-#define   TC_CTRLBCLR_CMD_NONE_Val        _U_(0x0)   /**< \brief (TC_CTRLBCLR) No action */
-#define   TC_CTRLBCLR_CMD_RETRIGGER_Val   _U_(0x1)   /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
-#define   TC_CTRLBCLR_CMD_STOP_Val        _U_(0x2)   /**< \brief (TC_CTRLBCLR) Force a stop */
-#define   TC_CTRLBCLR_CMD_UPDATE_Val      _U_(0x3)   /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */
-#define   TC_CTRLBCLR_CMD_READSYNC_Val    _U_(0x4)   /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */
-#define   TC_CTRLBCLR_CMD_DMAOS_Val       _U_(0x5)   /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */
-#define TC_CTRLBCLR_CMD_NONE        (TC_CTRLBCLR_CMD_NONE_Val      << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_RETRIGGER   (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_STOP        (TC_CTRLBCLR_CMD_STOP_Val      << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_UPDATE      (TC_CTRLBCLR_CMD_UPDATE_Val    << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_READSYNC    (TC_CTRLBCLR_CMD_READSYNC_Val  << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_CMD_DMAOS       (TC_CTRLBCLR_CMD_DMAOS_Val     << TC_CTRLBCLR_CMD_Pos)
-#define TC_CTRLBCLR_MASK            _U_(0xE7)    /**< \brief (TC_CTRLBCLR) MASK Register */
-
-/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W  8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot on Counter                */
-    uint8_t  :2;               /*!< bit:  3.. 4  Reserved                           */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  Command                            */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_CTRLBSET_OFFSET          0x05         /**< \brief (TC_CTRLBSET offset) Control B Set */
-#define TC_CTRLBSET_RESETVALUE      _U_(0x00)    /**< \brief (TC_CTRLBSET reset_value) Control B Set */
-
-#define TC_CTRLBSET_DIR_Pos         0            /**< \brief (TC_CTRLBSET) Counter Direction */
-#define TC_CTRLBSET_DIR             (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
-#define TC_CTRLBSET_LUPD_Pos        1            /**< \brief (TC_CTRLBSET) Lock Update */
-#define TC_CTRLBSET_LUPD            (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
-#define TC_CTRLBSET_ONESHOT_Pos     2            /**< \brief (TC_CTRLBSET) One-Shot on Counter */
-#define TC_CTRLBSET_ONESHOT         (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
-#define TC_CTRLBSET_CMD_Pos         5            /**< \brief (TC_CTRLBSET) Command */
-#define TC_CTRLBSET_CMD_Msk         (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD(value)      (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
-#define   TC_CTRLBSET_CMD_NONE_Val        _U_(0x0)   /**< \brief (TC_CTRLBSET) No action */
-#define   TC_CTRLBSET_CMD_RETRIGGER_Val   _U_(0x1)   /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
-#define   TC_CTRLBSET_CMD_STOP_Val        _U_(0x2)   /**< \brief (TC_CTRLBSET) Force a stop */
-#define   TC_CTRLBSET_CMD_UPDATE_Val      _U_(0x3)   /**< \brief (TC_CTRLBSET) Force update of double-buffered register */
-#define   TC_CTRLBSET_CMD_READSYNC_Val    _U_(0x4)   /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */
-#define   TC_CTRLBSET_CMD_DMAOS_Val       _U_(0x5)   /**< \brief (TC_CTRLBSET) One-shot DMA trigger */
-#define TC_CTRLBSET_CMD_NONE        (TC_CTRLBSET_CMD_NONE_Val      << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_RETRIGGER   (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_STOP        (TC_CTRLBSET_CMD_STOP_Val      << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_UPDATE      (TC_CTRLBSET_CMD_UPDATE_Val    << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_READSYNC    (TC_CTRLBSET_CMD_READSYNC_Val  << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_CMD_DMAOS       (TC_CTRLBSET_CMD_DMAOS_Val     << TC_CTRLBSET_CMD_Pos)
-#define TC_CTRLBSET_MASK            _U_(0xE7)    /**< \brief (TC_CTRLBSET) MASK Register */
-
-/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t EVACT:3;          /*!< bit:  0.. 2  Event Action                       */
-    uint16_t :1;               /*!< bit:      3  Reserved                           */
-    uint16_t TCINV:1;          /*!< bit:      4  TC Event Input Polarity            */
-    uint16_t TCEI:1;           /*!< bit:      5  TC Event Enable                    */
-    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
-    uint16_t OVFEO:1;          /*!< bit:      8  Event Output Enable                */
-    uint16_t :3;               /*!< bit:  9..11  Reserved                           */
-    uint16_t MCEO0:1;          /*!< bit:     12  MC Event Output Enable 0           */
-    uint16_t MCEO1:1;          /*!< bit:     13  MC Event Output Enable 1           */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t :12;              /*!< bit:  0..11  Reserved                           */
-    uint16_t MCEO:2;           /*!< bit: 12..13  MC Event Output Enable x           */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_EVCTRL_OFFSET            0x06         /**< \brief (TC_EVCTRL offset) Event Control */
-#define TC_EVCTRL_RESETVALUE        _U_(0x0000)  /**< \brief (TC_EVCTRL reset_value) Event Control */
-
-#define TC_EVCTRL_EVACT_Pos         0            /**< \brief (TC_EVCTRL) Event Action */
-#define TC_EVCTRL_EVACT_Msk         (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT(value)      (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
-#define   TC_EVCTRL_EVACT_OFF_Val         _U_(0x0)   /**< \brief (TC_EVCTRL) Event action disabled */
-#define   TC_EVCTRL_EVACT_RETRIGGER_Val   _U_(0x1)   /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
-#define   TC_EVCTRL_EVACT_COUNT_Val       _U_(0x2)   /**< \brief (TC_EVCTRL) Count on event */
-#define   TC_EVCTRL_EVACT_START_Val       _U_(0x3)   /**< \brief (TC_EVCTRL) Start TC on event */
-#define   TC_EVCTRL_EVACT_STAMP_Val       _U_(0x4)   /**< \brief (TC_EVCTRL) Time stamp capture */
-#define   TC_EVCTRL_EVACT_PPW_Val         _U_(0x5)   /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */
-#define   TC_EVCTRL_EVACT_PWP_Val         _U_(0x6)   /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */
-#define   TC_EVCTRL_EVACT_PW_Val          _U_(0x7)   /**< \brief (TC_EVCTRL) Pulse width capture */
-#define TC_EVCTRL_EVACT_OFF         (TC_EVCTRL_EVACT_OFF_Val       << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_RETRIGGER   (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_COUNT       (TC_EVCTRL_EVACT_COUNT_Val     << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_START       (TC_EVCTRL_EVACT_START_Val     << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_STAMP       (TC_EVCTRL_EVACT_STAMP_Val     << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_PPW         (TC_EVCTRL_EVACT_PPW_Val       << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_PWP         (TC_EVCTRL_EVACT_PWP_Val       << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_EVACT_PW          (TC_EVCTRL_EVACT_PW_Val        << TC_EVCTRL_EVACT_Pos)
-#define TC_EVCTRL_TCINV_Pos         4            /**< \brief (TC_EVCTRL) TC Event Input Polarity */
-#define TC_EVCTRL_TCINV             (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
-#define TC_EVCTRL_TCEI_Pos          5            /**< \brief (TC_EVCTRL) TC Event Enable */
-#define TC_EVCTRL_TCEI              (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
-#define TC_EVCTRL_OVFEO_Pos         8            /**< \brief (TC_EVCTRL) Event Output Enable */
-#define TC_EVCTRL_OVFEO             (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
-#define TC_EVCTRL_MCEO0_Pos         12           /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */
-#define TC_EVCTRL_MCEO0             (_U_(1) << TC_EVCTRL_MCEO0_Pos)
-#define TC_EVCTRL_MCEO1_Pos         13           /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */
-#define TC_EVCTRL_MCEO1             (_U_(1) << TC_EVCTRL_MCEO1_Pos)
-#define TC_EVCTRL_MCEO_Pos          12           /**< \brief (TC_EVCTRL) MC Event Output Enable x */
-#define TC_EVCTRL_MCEO_Msk          (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
-#define TC_EVCTRL_MCEO(value)       (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
-#define TC_EVCTRL_MASK              _U_(0x3137)  /**< \brief (TC_EVCTRL) MASK Register */
-
-/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  OVF:1;            /*!< bit:      0  OVF Interrupt Disable              */
-    uint8_t  ERR:1;            /*!< bit:      1  ERR Interrupt Disable              */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  MC0:1;            /*!< bit:      4  MC Interrupt Disable 0             */
-    uint8_t  MC1:1;            /*!< bit:      5  MC Interrupt Disable 1             */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  MC:2;             /*!< bit:  4.. 5  MC Interrupt Disable x             */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_INTENCLR_OFFSET          0x08         /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
-#define TC_INTENCLR_RESETVALUE      _U_(0x00)    /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TC_INTENCLR_OVF_Pos         0            /**< \brief (TC_INTENCLR) OVF Interrupt Disable */
-#define TC_INTENCLR_OVF             (_U_(0x1) << TC_INTENCLR_OVF_Pos)
-#define TC_INTENCLR_ERR_Pos         1            /**< \brief (TC_INTENCLR) ERR Interrupt Disable */
-#define TC_INTENCLR_ERR             (_U_(0x1) << TC_INTENCLR_ERR_Pos)
-#define TC_INTENCLR_MC0_Pos         4            /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */
-#define TC_INTENCLR_MC0             (_U_(1) << TC_INTENCLR_MC0_Pos)
-#define TC_INTENCLR_MC1_Pos         5            /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */
-#define TC_INTENCLR_MC1             (_U_(1) << TC_INTENCLR_MC1_Pos)
-#define TC_INTENCLR_MC_Pos          4            /**< \brief (TC_INTENCLR) MC Interrupt Disable x */
-#define TC_INTENCLR_MC_Msk          (_U_(0x3) << TC_INTENCLR_MC_Pos)
-#define TC_INTENCLR_MC(value)       (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
-#define TC_INTENCLR_MASK            _U_(0x33)    /**< \brief (TC_INTENCLR) MASK Register */
-
-/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  OVF:1;            /*!< bit:      0  OVF Interrupt Enable               */
-    uint8_t  ERR:1;            /*!< bit:      1  ERR Interrupt Enable               */
-    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    uint8_t  MC0:1;            /*!< bit:      4  MC Interrupt Enable 0              */
-    uint8_t  MC1:1;            /*!< bit:      5  MC Interrupt Enable 1              */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  MC:2;             /*!< bit:  4.. 5  MC Interrupt Enable x              */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_INTENSET_OFFSET          0x09         /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
-#define TC_INTENSET_RESETVALUE      _U_(0x00)    /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
-
-#define TC_INTENSET_OVF_Pos         0            /**< \brief (TC_INTENSET) OVF Interrupt Enable */
-#define TC_INTENSET_OVF             (_U_(0x1) << TC_INTENSET_OVF_Pos)
-#define TC_INTENSET_ERR_Pos         1            /**< \brief (TC_INTENSET) ERR Interrupt Enable */
-#define TC_INTENSET_ERR             (_U_(0x1) << TC_INTENSET_ERR_Pos)
-#define TC_INTENSET_MC0_Pos         4            /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */
-#define TC_INTENSET_MC0             (_U_(1) << TC_INTENSET_MC0_Pos)
-#define TC_INTENSET_MC1_Pos         5            /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */
-#define TC_INTENSET_MC1             (_U_(1) << TC_INTENSET_MC1_Pos)
-#define TC_INTENSET_MC_Pos          4            /**< \brief (TC_INTENSET) MC Interrupt Enable x */
-#define TC_INTENSET_MC_Msk          (_U_(0x3) << TC_INTENSET_MC_Pos)
-#define TC_INTENSET_MC(value)       (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
-#define TC_INTENSET_MASK            _U_(0x33)    /**< \brief (TC_INTENSET) MASK Register */
-
-/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  OVF:1;            /*!< bit:      0  OVF Interrupt Flag                 */
-    __I uint8_t  ERR:1;            /*!< bit:      1  ERR Interrupt Flag                 */
-    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
-    __I uint8_t  MC0:1;            /*!< bit:      4  MC Interrupt Flag 0                */
-    __I uint8_t  MC1:1;            /*!< bit:      5  MC Interrupt Flag 1                */
-    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    __I uint8_t  MC:2;             /*!< bit:  4.. 5  MC Interrupt Flag x                */
-    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_INTFLAG_OFFSET           0x0A         /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TC_INTFLAG_RESETVALUE       _U_(0x00)    /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TC_INTFLAG_OVF_Pos          0            /**< \brief (TC_INTFLAG) OVF Interrupt Flag */
-#define TC_INTFLAG_OVF              (_U_(0x1) << TC_INTFLAG_OVF_Pos)
-#define TC_INTFLAG_ERR_Pos          1            /**< \brief (TC_INTFLAG) ERR Interrupt Flag */
-#define TC_INTFLAG_ERR              (_U_(0x1) << TC_INTFLAG_ERR_Pos)
-#define TC_INTFLAG_MC0_Pos          4            /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */
-#define TC_INTFLAG_MC0              (_U_(1) << TC_INTFLAG_MC0_Pos)
-#define TC_INTFLAG_MC1_Pos          5            /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */
-#define TC_INTFLAG_MC1              (_U_(1) << TC_INTFLAG_MC1_Pos)
-#define TC_INTFLAG_MC_Pos           4            /**< \brief (TC_INTFLAG) MC Interrupt Flag x */
-#define TC_INTFLAG_MC_Msk           (_U_(0x3) << TC_INTFLAG_MC_Pos)
-#define TC_INTFLAG_MC(value)        (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
-#define TC_INTFLAG_MASK             _U_(0x33)    /**< \brief (TC_INTFLAG) MASK Register */
-
-/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W  8) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  STOP:1;           /*!< bit:      0  Stop Status Flag                   */
-    uint8_t  SLAVE:1;          /*!< bit:      1  Slave Status Flag                  */
-    uint8_t  :1;               /*!< bit:      2  Reserved                           */
-    uint8_t  PERBUFV:1;        /*!< bit:      3  Synchronization Busy Status        */
-    uint8_t  CCBUFV0:1;        /*!< bit:      4  Compare channel buffer 0 valid     */
-    uint8_t  CCBUFV1:1;        /*!< bit:      5  Compare channel buffer 1 valid     */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  CCBUFV:2;         /*!< bit:  4.. 5  Compare channel buffer x valid     */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_STATUS_OFFSET            0x0B         /**< \brief (TC_STATUS offset) Status */
-#define TC_STATUS_RESETVALUE        _U_(0x01)    /**< \brief (TC_STATUS reset_value) Status */
-
-#define TC_STATUS_STOP_Pos          0            /**< \brief (TC_STATUS) Stop Status Flag */
-#define TC_STATUS_STOP              (_U_(0x1) << TC_STATUS_STOP_Pos)
-#define TC_STATUS_SLAVE_Pos         1            /**< \brief (TC_STATUS) Slave Status Flag */
-#define TC_STATUS_SLAVE             (_U_(0x1) << TC_STATUS_SLAVE_Pos)
-#define TC_STATUS_PERBUFV_Pos       3            /**< \brief (TC_STATUS) Synchronization Busy Status */
-#define TC_STATUS_PERBUFV           (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
-#define TC_STATUS_CCBUFV0_Pos       4            /**< \brief (TC_STATUS) Compare channel buffer 0 valid */
-#define TC_STATUS_CCBUFV0           (_U_(1) << TC_STATUS_CCBUFV0_Pos)
-#define TC_STATUS_CCBUFV1_Pos       5            /**< \brief (TC_STATUS) Compare channel buffer 1 valid */
-#define TC_STATUS_CCBUFV1           (_U_(1) << TC_STATUS_CCBUFV1_Pos)
-#define TC_STATUS_CCBUFV_Pos        4            /**< \brief (TC_STATUS) Compare channel buffer x valid */
-#define TC_STATUS_CCBUFV_Msk        (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
-#define TC_STATUS_CCBUFV(value)     (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
-#define TC_STATUS_MASK              _U_(0x3B)    /**< \brief (TC_STATUS) MASK Register */
-
-/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W  8) Waveform Generation Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  WAVEGEN:2;        /*!< bit:  0.. 1  Waveform Generation Mode           */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_WAVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_WAVE_OFFSET              0x0C         /**< \brief (TC_WAVE offset) Waveform Generation Control */
-#define TC_WAVE_RESETVALUE          _U_(0x00)    /**< \brief (TC_WAVE reset_value) Waveform Generation Control */
-
-#define TC_WAVE_WAVEGEN_Pos         0            /**< \brief (TC_WAVE) Waveform Generation Mode */
-#define TC_WAVE_WAVEGEN_Msk         (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_WAVEGEN(value)      (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
-#define   TC_WAVE_WAVEGEN_NFRQ_Val        _U_(0x0)   /**< \brief (TC_WAVE) Normal frequency */
-#define   TC_WAVE_WAVEGEN_MFRQ_Val        _U_(0x1)   /**< \brief (TC_WAVE) Match frequency */
-#define   TC_WAVE_WAVEGEN_NPWM_Val        _U_(0x2)   /**< \brief (TC_WAVE) Normal PWM */
-#define   TC_WAVE_WAVEGEN_MPWM_Val        _U_(0x3)   /**< \brief (TC_WAVE) Match PWM */
-#define TC_WAVE_WAVEGEN_NFRQ        (TC_WAVE_WAVEGEN_NFRQ_Val      << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_WAVEGEN_MFRQ        (TC_WAVE_WAVEGEN_MFRQ_Val      << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_WAVEGEN_NPWM        (TC_WAVE_WAVEGEN_NPWM_Val      << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_WAVEGEN_MPWM        (TC_WAVE_WAVEGEN_MPWM_Val      << TC_WAVE_WAVEGEN_Pos)
-#define TC_WAVE_MASK                _U_(0x03)    /**< \brief (TC_WAVE) MASK Register */
-
-/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W  8) Control C -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  INVEN0:1;         /*!< bit:      0  Output Waveform Invert Enable 0    */
-    uint8_t  INVEN1:1;         /*!< bit:      1  Output Waveform Invert Enable 1    */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  INVEN:2;          /*!< bit:  0.. 1  Output Waveform Invert Enable x    */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_DRVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_DRVCTRL_OFFSET           0x0D         /**< \brief (TC_DRVCTRL offset) Control C */
-#define TC_DRVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (TC_DRVCTRL reset_value) Control C */
-
-#define TC_DRVCTRL_INVEN0_Pos       0            /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */
-#define TC_DRVCTRL_INVEN0           (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
-#define TC_DRVCTRL_INVEN1_Pos       1            /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */
-#define TC_DRVCTRL_INVEN1           (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
-#define TC_DRVCTRL_INVEN_Pos        0            /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */
-#define TC_DRVCTRL_INVEN_Msk        (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
-#define TC_DRVCTRL_INVEN(value)     (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
-#define TC_DRVCTRL_MASK             _U_(0x03)    /**< \brief (TC_DRVCTRL) MASK Register */
-
-/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Run During Debug                   */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_DBGCTRL_OFFSET           0x0F         /**< \brief (TC_DBGCTRL offset) Debug Control */
-#define TC_DBGCTRL_RESETVALUE       _U_(0x00)    /**< \brief (TC_DBGCTRL reset_value) Debug Control */
-
-#define TC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (TC_DBGCTRL) Run During Debug */
-#define TC_DBGCTRL_DBGRUN           (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
-#define TC_DBGCTRL_MASK             _U_(0x01)    /**< \brief (TC_DBGCTRL) MASK Register */
-
-/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/  32) Synchronization Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  swrst                              */
-    uint32_t ENABLE:1;         /*!< bit:      1  enable                             */
-    uint32_t CTRLB:1;          /*!< bit:      2  CTRLB                              */
-    uint32_t STATUS:1;         /*!< bit:      3  STATUS                             */
-    uint32_t COUNT:1;          /*!< bit:      4  Counter                            */
-    uint32_t PER:1;            /*!< bit:      5  Period                             */
-    uint32_t CC0:1;            /*!< bit:      6  Compare Channel 0                  */
-    uint32_t CC1:1;            /*!< bit:      7  Compare Channel 1                  */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
-    uint32_t CC:2;             /*!< bit:  6.. 7  Compare Channel x                  */
-    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_SYNCBUSY_OFFSET          0x10         /**< \brief (TC_SYNCBUSY offset) Synchronization Status */
-#define TC_SYNCBUSY_RESETVALUE      _U_(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */
-
-#define TC_SYNCBUSY_SWRST_Pos       0            /**< \brief (TC_SYNCBUSY) swrst */
-#define TC_SYNCBUSY_SWRST           (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
-#define TC_SYNCBUSY_ENABLE_Pos      1            /**< \brief (TC_SYNCBUSY) enable */
-#define TC_SYNCBUSY_ENABLE          (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
-#define TC_SYNCBUSY_CTRLB_Pos       2            /**< \brief (TC_SYNCBUSY) CTRLB */
-#define TC_SYNCBUSY_CTRLB           (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
-#define TC_SYNCBUSY_STATUS_Pos      3            /**< \brief (TC_SYNCBUSY) STATUS */
-#define TC_SYNCBUSY_STATUS          (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
-#define TC_SYNCBUSY_COUNT_Pos       4            /**< \brief (TC_SYNCBUSY) Counter */
-#define TC_SYNCBUSY_COUNT           (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
-#define TC_SYNCBUSY_PER_Pos         5            /**< \brief (TC_SYNCBUSY) Period */
-#define TC_SYNCBUSY_PER             (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
-#define TC_SYNCBUSY_CC0_Pos         6            /**< \brief (TC_SYNCBUSY) Compare Channel 0 */
-#define TC_SYNCBUSY_CC0             (_U_(1) << TC_SYNCBUSY_CC0_Pos)
-#define TC_SYNCBUSY_CC1_Pos         7            /**< \brief (TC_SYNCBUSY) Compare Channel 1 */
-#define TC_SYNCBUSY_CC1             (_U_(1) << TC_SYNCBUSY_CC1_Pos)
-#define TC_SYNCBUSY_CC_Pos          6            /**< \brief (TC_SYNCBUSY) Compare Channel x */
-#define TC_SYNCBUSY_CC_Msk          (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
-#define TC_SYNCBUSY_CC(value)       (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
-#define TC_SYNCBUSY_MASK            _U_(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */
-
-/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t COUNT:16;         /*!< bit:  0..15  Counter Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TC_COUNT16_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT16_COUNT_OFFSET     0x14         /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */
-#define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000)  /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */
-
-#define TC_COUNT16_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT16_COUNT) Counter Value */
-#define TC_COUNT16_COUNT_COUNT_Msk  (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
-#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
-#define TC_COUNT16_COUNT_MASK       _U_(0xFFFF)  /**< \brief (TC_COUNT16_COUNT) MASK Register */
-
-/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t COUNT:32;         /*!< bit:  0..31  Counter Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TC_COUNT32_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT32_COUNT_OFFSET     0x14         /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */
-#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */
-
-#define TC_COUNT32_COUNT_COUNT_Pos  0            /**< \brief (TC_COUNT32_COUNT) Counter Value */
-#define TC_COUNT32_COUNT_COUNT_Msk  (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
-#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
-#define TC_COUNT32_COUNT_MASK       _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */
-
-/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W  8) COUNT8 COUNT8 Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  COUNT:8;          /*!< bit:  0.. 7  Counter Value                      */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_COUNT8_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_COUNT_OFFSET      0x14         /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */
-#define TC_COUNT8_COUNT_RESETVALUE  _U_(0x00)    /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */
-
-#define TC_COUNT8_COUNT_COUNT_Pos   0            /**< \brief (TC_COUNT8_COUNT) Counter Value */
-#define TC_COUNT8_COUNT_COUNT_Msk   (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
-#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
-#define TC_COUNT8_COUNT_MASK        _U_(0xFF)    /**< \brief (TC_COUNT8_COUNT) MASK Register */
-
-/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W  8) COUNT8 COUNT8 Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PER:8;            /*!< bit:  0.. 7  Period Value                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_COUNT8_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_PER_OFFSET        0x1B         /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */
-#define TC_COUNT8_PER_RESETVALUE    _U_(0xFF)    /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */
-
-#define TC_COUNT8_PER_PER_Pos       0            /**< \brief (TC_COUNT8_PER) Period Value */
-#define TC_COUNT8_PER_PER_Msk       (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
-#define TC_COUNT8_PER_PER(value)    (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
-#define TC_COUNT8_PER_MASK          _U_(0xFF)    /**< \brief (TC_COUNT8_PER) MASK Register */
-
-/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CC:16;            /*!< bit:  0..15  Counter/Compare Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TC_COUNT16_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT16_CC_OFFSET        0x1C         /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */
-#define TC_COUNT16_CC_RESETVALUE    _U_(0x0000)  /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */
-
-#define TC_COUNT16_CC_CC_Pos        0            /**< \brief (TC_COUNT16_CC) Counter/Compare Value */
-#define TC_COUNT16_CC_CC_Msk        (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
-#define TC_COUNT16_CC_CC(value)     (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
-#define TC_COUNT16_CC_MASK          _U_(0xFFFF)  /**< \brief (TC_COUNT16_CC) MASK Register */
-
-/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CC:32;            /*!< bit:  0..31  Counter/Compare Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TC_COUNT32_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT32_CC_OFFSET        0x1C         /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */
-#define TC_COUNT32_CC_RESETVALUE    _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */
-
-#define TC_COUNT32_CC_CC_Pos        0            /**< \brief (TC_COUNT32_CC) Counter/Compare Value */
-#define TC_COUNT32_CC_CC_Msk        (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
-#define TC_COUNT32_CC_CC(value)     (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
-#define TC_COUNT32_CC_MASK          _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */
-
-/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W  8) COUNT8 COUNT8 Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CC:8;             /*!< bit:  0.. 7  Counter/Compare Value              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_COUNT8_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_CC_OFFSET         0x1C         /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */
-#define TC_COUNT8_CC_RESETVALUE     _U_(0x00)    /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */
-
-#define TC_COUNT8_CC_CC_Pos         0            /**< \brief (TC_COUNT8_CC) Counter/Compare Value */
-#define TC_COUNT8_CC_CC_Msk         (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
-#define TC_COUNT8_CC_CC(value)      (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
-#define TC_COUNT8_CC_MASK           _U_(0xFF)    /**< \brief (TC_COUNT8_CC) MASK Register */
-
-/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W  8) COUNT8 COUNT8 Period Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PERBUF:8;         /*!< bit:  0.. 7  Period Buffer Value                */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_COUNT8_PERBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_PERBUF_OFFSET     0x2F         /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */
-#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF)    /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */
-
-#define TC_COUNT8_PERBUF_PERBUF_Pos 0            /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */
-#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
-#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
-#define TC_COUNT8_PERBUF_MASK       _U_(0xFF)    /**< \brief (TC_COUNT8_PERBUF) MASK Register */
-
-/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t CCBUF:16;         /*!< bit:  0..15  Counter/Compare Buffer Value       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TC_COUNT16_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT16_CCBUF_OFFSET     0x30         /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */
-#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000)  /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */
-
-#define TC_COUNT16_CCBUF_CCBUF_Pos  0            /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */
-#define TC_COUNT16_CCBUF_CCBUF_Msk  (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
-#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
-#define TC_COUNT16_CCBUF_MASK       _U_(0xFFFF)  /**< \brief (TC_COUNT16_CCBUF) MASK Register */
-
-/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t CCBUF:32;         /*!< bit:  0..31  Counter/Compare Buffer Value       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TC_COUNT32_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT32_CCBUF_OFFSET     0x30         /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */
-#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */
-
-#define TC_COUNT32_CCBUF_CCBUF_Pos  0            /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */
-#define TC_COUNT32_CCBUF_CCBUF_Msk  (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
-#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
-#define TC_COUNT32_CCBUF_MASK       _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */
-
-/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W  8) COUNT8 COUNT8 Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CCBUF:8;          /*!< bit:  0.. 7  Counter/Compare Buffer Value       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TC_COUNT8_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TC_COUNT8_CCBUF_OFFSET      0x30         /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */
-#define TC_COUNT8_CCBUF_RESETVALUE  _U_(0x00)    /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */
-
-#define TC_COUNT8_CCBUF_CCBUF_Pos   0            /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */
-#define TC_COUNT8_CCBUF_CCBUF_Msk   (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
-#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
-#define TC_COUNT8_CCBUF_MASK        _U_(0xFF)    /**< \brief (TC_COUNT8_CCBUF) MASK Register */
-
-/** \brief TC_COUNT8 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 8-bit Counter Mode */
-  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x06 (R/W 16) Event Control */
-  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
-  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
-  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
-  __IO TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0B (R/W  8) Status */
-  __IO TC_WAVE_Type              WAVE;        /**< \brief Offset: 0x0C (R/W  8) Waveform Generation Control */
-  __IO TC_DRVCTRL_Type           DRVCTRL;     /**< \brief Offset: 0x0D (R/W  8) Control C */
-       RoReg8                    Reserved1[0x1];
-  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x0F (R/W  8) Debug Control */
-  __I  TC_SYNCBUSY_Type          SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) Synchronization Status */
-  __IO TC_COUNT8_COUNT_Type      COUNT;       /**< \brief Offset: 0x14 (R/W  8) COUNT8 Count */
-       RoReg8                    Reserved2[0x6];
-  __IO TC_COUNT8_PER_Type        PER;         /**< \brief Offset: 0x1B (R/W  8) COUNT8 Period */
-  __IO TC_COUNT8_CC_Type         CC[2];       /**< \brief Offset: 0x1C (R/W  8) COUNT8 Compare and Capture */
-       RoReg8                    Reserved3[0x11];
-  __IO TC_COUNT8_PERBUF_Type     PERBUF;      /**< \brief Offset: 0x2F (R/W  8) COUNT8 Period Buffer */
-  __IO TC_COUNT8_CCBUF_Type      CCBUF[2];    /**< \brief Offset: 0x30 (R/W  8) COUNT8 Compare and Capture Buffer */
-} TcCount8;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief TC_COUNT16 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 16-bit Counter Mode */
-  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x06 (R/W 16) Event Control */
-  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
-  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
-  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
-  __IO TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0B (R/W  8) Status */
-  __IO TC_WAVE_Type              WAVE;        /**< \brief Offset: 0x0C (R/W  8) Waveform Generation Control */
-  __IO TC_DRVCTRL_Type           DRVCTRL;     /**< \brief Offset: 0x0D (R/W  8) Control C */
-       RoReg8                    Reserved1[0x1];
-  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x0F (R/W  8) Debug Control */
-  __I  TC_SYNCBUSY_Type          SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) Synchronization Status */
-  __IO TC_COUNT16_COUNT_Type     COUNT;       /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */
-       RoReg8                    Reserved2[0x6];
-  __IO TC_COUNT16_CC_Type        CC[2];       /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */
-       RoReg8                    Reserved3[0x10];
-  __IO TC_COUNT16_CCBUF_Type     CCBUF[2];    /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */
-} TcCount16;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief TC_COUNT32 hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* 32-bit Counter Mode */
-  __IO TC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO TC_CTRLBCLR_Type          CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TC_CTRLBSET_Type          CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-  __IO TC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x06 (R/W 16) Event Control */
-  __IO TC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
-  __IO TC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
-  __IO TC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
-  __IO TC_STATUS_Type            STATUS;      /**< \brief Offset: 0x0B (R/W  8) Status */
-  __IO TC_WAVE_Type              WAVE;        /**< \brief Offset: 0x0C (R/W  8) Waveform Generation Control */
-  __IO TC_DRVCTRL_Type           DRVCTRL;     /**< \brief Offset: 0x0D (R/W  8) Control C */
-       RoReg8                    Reserved1[0x1];
-  __IO TC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x0F (R/W  8) Debug Control */
-  __I  TC_SYNCBUSY_Type          SYNCBUSY;    /**< \brief Offset: 0x10 (R/  32) Synchronization Status */
-  __IO TC_COUNT32_COUNT_Type     COUNT;       /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */
-       RoReg8                    Reserved2[0x4];
-  __IO TC_COUNT32_CC_Type        CC[2];       /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */
-       RoReg8                    Reserved3[0xC];
-  __IO TC_COUNT32_CCBUF_Type     CCBUF[2];    /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */
-} TcCount32;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-       TcCount8                  COUNT8;      /**< \brief Offset: 0x00 8-bit Counter Mode */
-       TcCount16                 COUNT16;     /**< \brief Offset: 0x00 16-bit Counter Mode */
-       TcCount32                 COUNT32;     /**< \brief Offset: 0x00 32-bit Counter Mode */
-} Tc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_TC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tcc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tcc.h
deleted file mode 100644
index a32abe964d..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tcc.h
+++ /dev/null
@@ -1,1762 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for TCC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TCC_COMPONENT_
-#define _SAMD51_TCC_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR TCC */
-/* ========================================================================== */
-/** \addtogroup SAMD51_TCC Timer Counter Control */
-/*@{*/
-
-#define TCC_U2213
-#define REV_TCC                     0x310
-
-/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint32_t :3;               /*!< bit:  2.. 4  Reserved                           */
-    uint32_t RESOLUTION:2;     /*!< bit:  5.. 6  Enhanced Resolution                */
-    uint32_t :1;               /*!< bit:      7  Reserved                           */
-    uint32_t PRESCALER:3;      /*!< bit:  8..10  Prescaler                          */
-    uint32_t RUNSTDBY:1;       /*!< bit:     11  Run in Standby                     */
-    uint32_t PRESCSYNC:2;      /*!< bit: 12..13  Prescaler and Counter Synchronization Selection */
-    uint32_t ALOCK:1;          /*!< bit:     14  Auto Lock                          */
-    uint32_t MSYNC:1;          /*!< bit:     15  Master Synchronization (only for TCC Slave Instance) */
-    uint32_t :7;               /*!< bit: 16..22  Reserved                           */
-    uint32_t DMAOS:1;          /*!< bit:     23  DMA One-shot Trigger Mode          */
-    uint32_t CPTEN0:1;         /*!< bit:     24  Capture Channel 0 Enable           */
-    uint32_t CPTEN1:1;         /*!< bit:     25  Capture Channel 1 Enable           */
-    uint32_t CPTEN2:1;         /*!< bit:     26  Capture Channel 2 Enable           */
-    uint32_t CPTEN3:1;         /*!< bit:     27  Capture Channel 3 Enable           */
-    uint32_t CPTEN4:1;         /*!< bit:     28  Capture Channel 4 Enable           */
-    uint32_t CPTEN5:1;         /*!< bit:     29  Capture Channel 5 Enable           */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :24;              /*!< bit:  0..23  Reserved                           */
-    uint32_t CPTEN:6;          /*!< bit: 24..29  Capture Channel x Enable           */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLA_OFFSET            0x00         /**< \brief (TCC_CTRLA offset) Control A */
-#define TCC_CTRLA_RESETVALUE        _U_(0x00000000) /**< \brief (TCC_CTRLA reset_value) Control A */
-
-#define TCC_CTRLA_SWRST_Pos         0            /**< \brief (TCC_CTRLA) Software Reset */
-#define TCC_CTRLA_SWRST             (_U_(0x1) << TCC_CTRLA_SWRST_Pos)
-#define TCC_CTRLA_ENABLE_Pos        1            /**< \brief (TCC_CTRLA) Enable */
-#define TCC_CTRLA_ENABLE            (_U_(0x1) << TCC_CTRLA_ENABLE_Pos)
-#define TCC_CTRLA_RESOLUTION_Pos    5            /**< \brief (TCC_CTRLA) Enhanced Resolution */
-#define TCC_CTRLA_RESOLUTION_Msk    (_U_(0x3) << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
-#define   TCC_CTRLA_RESOLUTION_NONE_Val   _U_(0x0)   /**< \brief (TCC_CTRLA) Dithering is disabled */
-#define   TCC_CTRLA_RESOLUTION_DITH4_Val  _U_(0x1)   /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
-#define   TCC_CTRLA_RESOLUTION_DITH5_Val  _U_(0x2)   /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
-#define   TCC_CTRLA_RESOLUTION_DITH6_Val  _U_(0x3)   /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
-#define TCC_CTRLA_RESOLUTION_NONE   (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH4  (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH5  (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_RESOLUTION_DITH6  (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
-#define TCC_CTRLA_PRESCALER_Pos     8            /**< \brief (TCC_CTRLA) Prescaler */
-#define TCC_CTRLA_PRESCALER_Msk     (_U_(0x7) << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER(value)  (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
-#define   TCC_CTRLA_PRESCALER_DIV1_Val    _U_(0x0)   /**< \brief (TCC_CTRLA) No division */
-#define   TCC_CTRLA_PRESCALER_DIV2_Val    _U_(0x1)   /**< \brief (TCC_CTRLA) Divide by 2 */
-#define   TCC_CTRLA_PRESCALER_DIV4_Val    _U_(0x2)   /**< \brief (TCC_CTRLA) Divide by 4 */
-#define   TCC_CTRLA_PRESCALER_DIV8_Val    _U_(0x3)   /**< \brief (TCC_CTRLA) Divide by 8 */
-#define   TCC_CTRLA_PRESCALER_DIV16_Val   _U_(0x4)   /**< \brief (TCC_CTRLA) Divide by 16 */
-#define   TCC_CTRLA_PRESCALER_DIV64_Val   _U_(0x5)   /**< \brief (TCC_CTRLA) Divide by 64 */
-#define   TCC_CTRLA_PRESCALER_DIV256_Val  _U_(0x6)   /**< \brief (TCC_CTRLA) Divide by 256 */
-#define   TCC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7)   /**< \brief (TCC_CTRLA) Divide by 1024 */
-#define TCC_CTRLA_PRESCALER_DIV1    (TCC_CTRLA_PRESCALER_DIV1_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV2    (TCC_CTRLA_PRESCALER_DIV2_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV4    (TCC_CTRLA_PRESCALER_DIV4_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV8    (TCC_CTRLA_PRESCALER_DIV8_Val  << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV16   (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV64   (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV256  (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
-#define TCC_CTRLA_RUNSTDBY_Pos      11           /**< \brief (TCC_CTRLA) Run in Standby */
-#define TCC_CTRLA_RUNSTDBY          (_U_(0x1) << TCC_CTRLA_RUNSTDBY_Pos)
-#define TCC_CTRLA_PRESCSYNC_Pos     12           /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
-#define TCC_CTRLA_PRESCSYNC_Msk     (_U_(0x3) << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC(value)  (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
-#define   TCC_CTRLA_PRESCSYNC_GCLK_Val    _U_(0x0)   /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
-#define   TCC_CTRLA_PRESCSYNC_PRESC_Val   _U_(0x1)   /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
-#define   TCC_CTRLA_PRESCSYNC_RESYNC_Val  _U_(0x2)   /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
-#define TCC_CTRLA_PRESCSYNC_GCLK    (TCC_CTRLA_PRESCSYNC_GCLK_Val  << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_PRESC   (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_PRESCSYNC_RESYNC  (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
-#define TCC_CTRLA_ALOCK_Pos         14           /**< \brief (TCC_CTRLA) Auto Lock */
-#define TCC_CTRLA_ALOCK             (_U_(0x1) << TCC_CTRLA_ALOCK_Pos)
-#define TCC_CTRLA_MSYNC_Pos         15           /**< \brief (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) */
-#define TCC_CTRLA_MSYNC             (_U_(0x1) << TCC_CTRLA_MSYNC_Pos)
-#define TCC_CTRLA_DMAOS_Pos         23           /**< \brief (TCC_CTRLA) DMA One-shot Trigger Mode */
-#define TCC_CTRLA_DMAOS             (_U_(0x1) << TCC_CTRLA_DMAOS_Pos)
-#define TCC_CTRLA_CPTEN0_Pos        24           /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
-#define TCC_CTRLA_CPTEN0            (_U_(1) << TCC_CTRLA_CPTEN0_Pos)
-#define TCC_CTRLA_CPTEN1_Pos        25           /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
-#define TCC_CTRLA_CPTEN1            (_U_(1) << TCC_CTRLA_CPTEN1_Pos)
-#define TCC_CTRLA_CPTEN2_Pos        26           /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
-#define TCC_CTRLA_CPTEN2            (_U_(1) << TCC_CTRLA_CPTEN2_Pos)
-#define TCC_CTRLA_CPTEN3_Pos        27           /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
-#define TCC_CTRLA_CPTEN3            (_U_(1) << TCC_CTRLA_CPTEN3_Pos)
-#define TCC_CTRLA_CPTEN4_Pos        28           /**< \brief (TCC_CTRLA) Capture Channel 4 Enable */
-#define TCC_CTRLA_CPTEN4            (_U_(1) << TCC_CTRLA_CPTEN4_Pos)
-#define TCC_CTRLA_CPTEN5_Pos        29           /**< \brief (TCC_CTRLA) Capture Channel 5 Enable */
-#define TCC_CTRLA_CPTEN5            (_U_(1) << TCC_CTRLA_CPTEN5_Pos)
-#define TCC_CTRLA_CPTEN_Pos         24           /**< \brief (TCC_CTRLA) Capture Channel x Enable */
-#define TCC_CTRLA_CPTEN_Msk         (_U_(0x3F) << TCC_CTRLA_CPTEN_Pos)
-#define TCC_CTRLA_CPTEN(value)      (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
-#define TCC_CTRLA_MASK              _U_(0x3F80FF63) /**< \brief (TCC_CTRLA) MASK Register */
-
-/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W  8) Control B Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_CTRLBCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBCLR_OFFSET         0x04         /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
-#define TCC_CTRLBCLR_RESETVALUE     _U_(0x00)    /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
-
-#define TCC_CTRLBCLR_DIR_Pos        0            /**< \brief (TCC_CTRLBCLR) Counter Direction */
-#define TCC_CTRLBCLR_DIR            (_U_(0x1) << TCC_CTRLBCLR_DIR_Pos)
-#define TCC_CTRLBCLR_LUPD_Pos       1            /**< \brief (TCC_CTRLBCLR) Lock Update */
-#define TCC_CTRLBCLR_LUPD           (_U_(0x1) << TCC_CTRLBCLR_LUPD_Pos)
-#define TCC_CTRLBCLR_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBCLR) One-Shot */
-#define TCC_CTRLBCLR_ONESHOT        (_U_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos)
-#define TCC_CTRLBCLR_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
-#define TCC_CTRLBCLR_IDXCMD_Msk     (_U_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD(value)  (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
-#define   TCC_CTRLBCLR_IDXCMD_DISABLE_Val _U_(0x0)   /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
-#define   TCC_CTRLBCLR_IDXCMD_SET_Val     _U_(0x1)   /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
-#define   TCC_CTRLBCLR_IDXCMD_CLEAR_Val   _U_(0x2)   /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
-#define   TCC_CTRLBCLR_IDXCMD_HOLD_Val    _U_(0x3)   /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_SET     (TCC_CTRLBCLR_IDXCMD_SET_Val   << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_CLEAR   (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_IDXCMD_HOLD    (TCC_CTRLBCLR_IDXCMD_HOLD_Val  << TCC_CTRLBCLR_IDXCMD_Pos)
-#define TCC_CTRLBCLR_CMD_Pos        5            /**< \brief (TCC_CTRLBCLR) TCC Command */
-#define TCC_CTRLBCLR_CMD_Msk        (_U_(0x7) << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD(value)     (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
-#define   TCC_CTRLBCLR_CMD_NONE_Val       _U_(0x0)   /**< \brief (TCC_CTRLBCLR) No action */
-#define   TCC_CTRLBCLR_CMD_RETRIGGER_Val  _U_(0x1)   /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
-#define   TCC_CTRLBCLR_CMD_STOP_Val       _U_(0x2)   /**< \brief (TCC_CTRLBCLR) Force stop */
-#define   TCC_CTRLBCLR_CMD_UPDATE_Val     _U_(0x3)   /**< \brief (TCC_CTRLBCLR) Force update or double buffered registers */
-#define   TCC_CTRLBCLR_CMD_READSYNC_Val   _U_(0x4)   /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
-#define   TCC_CTRLBCLR_CMD_DMAOS_Val      _U_(0x5)   /**< \brief (TCC_CTRLBCLR) One-shot DMA trigger */
-#define TCC_CTRLBCLR_CMD_NONE       (TCC_CTRLBCLR_CMD_NONE_Val     << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_RETRIGGER  (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_STOP       (TCC_CTRLBCLR_CMD_STOP_Val     << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_UPDATE     (TCC_CTRLBCLR_CMD_UPDATE_Val   << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_READSYNC   (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_CMD_DMAOS      (TCC_CTRLBCLR_CMD_DMAOS_Val    << TCC_CTRLBCLR_CMD_Pos)
-#define TCC_CTRLBCLR_MASK           _U_(0xFF)    /**< \brief (TCC_CTRLBCLR) MASK Register */
-
-/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W  8) Control B Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DIR:1;            /*!< bit:      0  Counter Direction                  */
-    uint8_t  LUPD:1;           /*!< bit:      1  Lock Update                        */
-    uint8_t  ONESHOT:1;        /*!< bit:      2  One-Shot                           */
-    uint8_t  IDXCMD:2;         /*!< bit:  3.. 4  Ramp Index Command                 */
-    uint8_t  CMD:3;            /*!< bit:  5.. 7  TCC Command                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_CTRLBSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CTRLBSET_OFFSET         0x05         /**< \brief (TCC_CTRLBSET offset) Control B Set */
-#define TCC_CTRLBSET_RESETVALUE     _U_(0x00)    /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
-
-#define TCC_CTRLBSET_DIR_Pos        0            /**< \brief (TCC_CTRLBSET) Counter Direction */
-#define TCC_CTRLBSET_DIR            (_U_(0x1) << TCC_CTRLBSET_DIR_Pos)
-#define TCC_CTRLBSET_LUPD_Pos       1            /**< \brief (TCC_CTRLBSET) Lock Update */
-#define TCC_CTRLBSET_LUPD           (_U_(0x1) << TCC_CTRLBSET_LUPD_Pos)
-#define TCC_CTRLBSET_ONESHOT_Pos    2            /**< \brief (TCC_CTRLBSET) One-Shot */
-#define TCC_CTRLBSET_ONESHOT        (_U_(0x1) << TCC_CTRLBSET_ONESHOT_Pos)
-#define TCC_CTRLBSET_IDXCMD_Pos     3            /**< \brief (TCC_CTRLBSET) Ramp Index Command */
-#define TCC_CTRLBSET_IDXCMD_Msk     (_U_(0x3) << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD(value)  (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
-#define   TCC_CTRLBSET_IDXCMD_DISABLE_Val _U_(0x0)   /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
-#define   TCC_CTRLBSET_IDXCMD_SET_Val     _U_(0x1)   /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
-#define   TCC_CTRLBSET_IDXCMD_CLEAR_Val   _U_(0x2)   /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
-#define   TCC_CTRLBSET_IDXCMD_HOLD_Val    _U_(0x3)   /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
-#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_SET     (TCC_CTRLBSET_IDXCMD_SET_Val   << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_CLEAR   (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_IDXCMD_HOLD    (TCC_CTRLBSET_IDXCMD_HOLD_Val  << TCC_CTRLBSET_IDXCMD_Pos)
-#define TCC_CTRLBSET_CMD_Pos        5            /**< \brief (TCC_CTRLBSET) TCC Command */
-#define TCC_CTRLBSET_CMD_Msk        (_U_(0x7) << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD(value)     (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
-#define   TCC_CTRLBSET_CMD_NONE_Val       _U_(0x0)   /**< \brief (TCC_CTRLBSET) No action */
-#define   TCC_CTRLBSET_CMD_RETRIGGER_Val  _U_(0x1)   /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
-#define   TCC_CTRLBSET_CMD_STOP_Val       _U_(0x2)   /**< \brief (TCC_CTRLBSET) Force stop */
-#define   TCC_CTRLBSET_CMD_UPDATE_Val     _U_(0x3)   /**< \brief (TCC_CTRLBSET) Force update or double buffered registers */
-#define   TCC_CTRLBSET_CMD_READSYNC_Val   _U_(0x4)   /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
-#define   TCC_CTRLBSET_CMD_DMAOS_Val      _U_(0x5)   /**< \brief (TCC_CTRLBSET) One-shot DMA trigger */
-#define TCC_CTRLBSET_CMD_NONE       (TCC_CTRLBSET_CMD_NONE_Val     << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_RETRIGGER  (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_STOP       (TCC_CTRLBSET_CMD_STOP_Val     << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_UPDATE     (TCC_CTRLBSET_CMD_UPDATE_Val   << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_READSYNC   (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_CMD_DMAOS      (TCC_CTRLBSET_CMD_DMAOS_Val    << TCC_CTRLBSET_CMD_Pos)
-#define TCC_CTRLBSET_MASK           _U_(0xFF)    /**< \brief (TCC_CTRLBSET) MASK Register */
-
-/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SWRST:1;          /*!< bit:      0  Swrst Busy                         */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Busy                        */
-    uint32_t CTRLB:1;          /*!< bit:      2  Ctrlb Busy                         */
-    uint32_t STATUS:1;         /*!< bit:      3  Status Busy                        */
-    uint32_t COUNT:1;          /*!< bit:      4  Count Busy                         */
-    uint32_t PATT:1;           /*!< bit:      5  Pattern Busy                       */
-    uint32_t WAVE:1;           /*!< bit:      6  Wave Busy                          */
-    uint32_t PER:1;            /*!< bit:      7  Period Busy                        */
-    uint32_t CC0:1;            /*!< bit:      8  Compare Channel 0 Busy             */
-    uint32_t CC1:1;            /*!< bit:      9  Compare Channel 1 Busy             */
-    uint32_t CC2:1;            /*!< bit:     10  Compare Channel 2 Busy             */
-    uint32_t CC3:1;            /*!< bit:     11  Compare Channel 3 Busy             */
-    uint32_t CC4:1;            /*!< bit:     12  Compare Channel 4 Busy             */
-    uint32_t CC5:1;            /*!< bit:     13  Compare Channel 5 Busy             */
-    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CC:6;             /*!< bit:  8..13  Compare Channel x Busy             */
-    uint32_t :18;              /*!< bit: 14..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_SYNCBUSY_OFFSET         0x08         /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
-#define TCC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
-
-#define TCC_SYNCBUSY_SWRST_Pos      0            /**< \brief (TCC_SYNCBUSY) Swrst Busy */
-#define TCC_SYNCBUSY_SWRST          (_U_(0x1) << TCC_SYNCBUSY_SWRST_Pos)
-#define TCC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (TCC_SYNCBUSY) Enable Busy */
-#define TCC_SYNCBUSY_ENABLE         (_U_(0x1) << TCC_SYNCBUSY_ENABLE_Pos)
-#define TCC_SYNCBUSY_CTRLB_Pos      2            /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
-#define TCC_SYNCBUSY_CTRLB          (_U_(0x1) << TCC_SYNCBUSY_CTRLB_Pos)
-#define TCC_SYNCBUSY_STATUS_Pos     3            /**< \brief (TCC_SYNCBUSY) Status Busy */
-#define TCC_SYNCBUSY_STATUS         (_U_(0x1) << TCC_SYNCBUSY_STATUS_Pos)
-#define TCC_SYNCBUSY_COUNT_Pos      4            /**< \brief (TCC_SYNCBUSY) Count Busy */
-#define TCC_SYNCBUSY_COUNT          (_U_(0x1) << TCC_SYNCBUSY_COUNT_Pos)
-#define TCC_SYNCBUSY_PATT_Pos       5            /**< \brief (TCC_SYNCBUSY) Pattern Busy */
-#define TCC_SYNCBUSY_PATT           (_U_(0x1) << TCC_SYNCBUSY_PATT_Pos)
-#define TCC_SYNCBUSY_WAVE_Pos       6            /**< \brief (TCC_SYNCBUSY) Wave Busy */
-#define TCC_SYNCBUSY_WAVE           (_U_(0x1) << TCC_SYNCBUSY_WAVE_Pos)
-#define TCC_SYNCBUSY_PER_Pos        7            /**< \brief (TCC_SYNCBUSY) Period Busy */
-#define TCC_SYNCBUSY_PER            (_U_(0x1) << TCC_SYNCBUSY_PER_Pos)
-#define TCC_SYNCBUSY_CC0_Pos        8            /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
-#define TCC_SYNCBUSY_CC0            (_U_(1) << TCC_SYNCBUSY_CC0_Pos)
-#define TCC_SYNCBUSY_CC1_Pos        9            /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
-#define TCC_SYNCBUSY_CC1            (_U_(1) << TCC_SYNCBUSY_CC1_Pos)
-#define TCC_SYNCBUSY_CC2_Pos        10           /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
-#define TCC_SYNCBUSY_CC2            (_U_(1) << TCC_SYNCBUSY_CC2_Pos)
-#define TCC_SYNCBUSY_CC3_Pos        11           /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
-#define TCC_SYNCBUSY_CC3            (_U_(1) << TCC_SYNCBUSY_CC3_Pos)
-#define TCC_SYNCBUSY_CC4_Pos        12           /**< \brief (TCC_SYNCBUSY) Compare Channel 4 Busy */
-#define TCC_SYNCBUSY_CC4            (_U_(1) << TCC_SYNCBUSY_CC4_Pos)
-#define TCC_SYNCBUSY_CC5_Pos        13           /**< \brief (TCC_SYNCBUSY) Compare Channel 5 Busy */
-#define TCC_SYNCBUSY_CC5            (_U_(1) << TCC_SYNCBUSY_CC5_Pos)
-#define TCC_SYNCBUSY_CC_Pos         8            /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
-#define TCC_SYNCBUSY_CC_Msk         (_U_(0x3F) << TCC_SYNCBUSY_CC_Pos)
-#define TCC_SYNCBUSY_CC(value)      (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
-#define TCC_SYNCBUSY_MASK           _U_(0x00003FFF) /**< \brief (TCC_SYNCBUSY) MASK Register */
-
-/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault A Source                     */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t KEEP:1;           /*!< bit:      3  Fault A Keeper                     */
-    uint32_t QUAL:1;           /*!< bit:      4  Fault A Qualification              */
-    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault A Blanking Mode              */
-    uint32_t RESTART:1;        /*!< bit:      7  Fault A Restart                    */
-    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault A Halt Mode                  */
-    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault A Capture Channel            */
-    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault A Capture Action             */
-    uint32_t BLANKPRESC:1;     /*!< bit:     15  Fault A Blanking Prescaler         */
-    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault A Blanking Time              */
-    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault A Filter Value               */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_FCTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLA_OFFSET           0x0C         /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
-#define TCC_FCTRLA_RESETVALUE       _U_(0x00000000) /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
-
-#define TCC_FCTRLA_SRC_Pos          0            /**< \brief (TCC_FCTRLA) Fault A Source */
-#define TCC_FCTRLA_SRC_Msk          (_U_(0x3) << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC(value)       (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
-#define   TCC_FCTRLA_SRC_DISABLE_Val      _U_(0x0)   /**< \brief (TCC_FCTRLA) Fault input disabled */
-#define   TCC_FCTRLA_SRC_ENABLE_Val       _U_(0x1)   /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
-#define   TCC_FCTRLA_SRC_INVERT_Val       _U_(0x2)   /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
-#define   TCC_FCTRLA_SRC_ALTFAULT_Val     _U_(0x3)   /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLA_SRC_DISABLE      (TCC_FCTRLA_SRC_DISABLE_Val    << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ENABLE       (TCC_FCTRLA_SRC_ENABLE_Val     << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_INVERT       (TCC_FCTRLA_SRC_INVERT_Val     << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_SRC_ALTFAULT     (TCC_FCTRLA_SRC_ALTFAULT_Val   << TCC_FCTRLA_SRC_Pos)
-#define TCC_FCTRLA_KEEP_Pos         3            /**< \brief (TCC_FCTRLA) Fault A Keeper */
-#define TCC_FCTRLA_KEEP             (_U_(0x1) << TCC_FCTRLA_KEEP_Pos)
-#define TCC_FCTRLA_QUAL_Pos         4            /**< \brief (TCC_FCTRLA) Fault A Qualification */
-#define TCC_FCTRLA_QUAL             (_U_(0x1) << TCC_FCTRLA_QUAL_Pos)
-#define TCC_FCTRLA_BLANK_Pos        5            /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
-#define TCC_FCTRLA_BLANK_Msk        (_U_(0x3) << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK(value)     (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
-#define   TCC_FCTRLA_BLANK_START_Val      _U_(0x0)   /**< \brief (TCC_FCTRLA) Blanking applied from start of the ramp */
-#define   TCC_FCTRLA_BLANK_RISE_Val       _U_(0x1)   /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
-#define   TCC_FCTRLA_BLANK_FALL_Val       _U_(0x2)   /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
-#define   TCC_FCTRLA_BLANK_BOTH_Val       _U_(0x3)   /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLA_BLANK_START      (TCC_FCTRLA_BLANK_START_Val    << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_RISE       (TCC_FCTRLA_BLANK_RISE_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_FALL       (TCC_FCTRLA_BLANK_FALL_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_BLANK_BOTH       (TCC_FCTRLA_BLANK_BOTH_Val     << TCC_FCTRLA_BLANK_Pos)
-#define TCC_FCTRLA_RESTART_Pos      7            /**< \brief (TCC_FCTRLA) Fault A Restart */
-#define TCC_FCTRLA_RESTART          (_U_(0x1) << TCC_FCTRLA_RESTART_Pos)
-#define TCC_FCTRLA_HALT_Pos         8            /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
-#define TCC_FCTRLA_HALT_Msk         (_U_(0x3) << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT(value)      (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
-#define   TCC_FCTRLA_HALT_DISABLE_Val     _U_(0x0)   /**< \brief (TCC_FCTRLA) Halt action disabled */
-#define   TCC_FCTRLA_HALT_HW_Val          _U_(0x1)   /**< \brief (TCC_FCTRLA) Hardware halt action */
-#define   TCC_FCTRLA_HALT_SW_Val          _U_(0x2)   /**< \brief (TCC_FCTRLA) Software halt action */
-#define   TCC_FCTRLA_HALT_NR_Val          _U_(0x3)   /**< \brief (TCC_FCTRLA) Non-recoverable fault */
-#define TCC_FCTRLA_HALT_DISABLE     (TCC_FCTRLA_HALT_DISABLE_Val   << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_HW          (TCC_FCTRLA_HALT_HW_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_SW          (TCC_FCTRLA_HALT_SW_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_HALT_NR          (TCC_FCTRLA_HALT_NR_Val        << TCC_FCTRLA_HALT_Pos)
-#define TCC_FCTRLA_CHSEL_Pos        10           /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
-#define TCC_FCTRLA_CHSEL_Msk        (_U_(0x3) << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL(value)     (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
-#define   TCC_FCTRLA_CHSEL_CC0_Val        _U_(0x0)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
-#define   TCC_FCTRLA_CHSEL_CC1_Val        _U_(0x1)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
-#define   TCC_FCTRLA_CHSEL_CC2_Val        _U_(0x2)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
-#define   TCC_FCTRLA_CHSEL_CC3_Val        _U_(0x3)   /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
-#define TCC_FCTRLA_CHSEL_CC0        (TCC_FCTRLA_CHSEL_CC0_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC1        (TCC_FCTRLA_CHSEL_CC1_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC2        (TCC_FCTRLA_CHSEL_CC2_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CHSEL_CC3        (TCC_FCTRLA_CHSEL_CC3_Val      << TCC_FCTRLA_CHSEL_Pos)
-#define TCC_FCTRLA_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLA) Fault A Capture Action */
-#define TCC_FCTRLA_CAPTURE_Msk      (_U_(0x7) << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE(value)   (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
-#define   TCC_FCTRLA_CAPTURE_DISABLE_Val  _U_(0x0)   /**< \brief (TCC_FCTRLA) No capture */
-#define   TCC_FCTRLA_CAPTURE_CAPT_Val     _U_(0x1)   /**< \brief (TCC_FCTRLA) Capture on fault */
-#define   TCC_FCTRLA_CAPTURE_CAPTMIN_Val  _U_(0x2)   /**< \brief (TCC_FCTRLA) Minimum capture */
-#define   TCC_FCTRLA_CAPTURE_CAPTMAX_Val  _U_(0x3)   /**< \brief (TCC_FCTRLA) Maximum capture */
-#define   TCC_FCTRLA_CAPTURE_LOCMIN_Val   _U_(0x4)   /**< \brief (TCC_FCTRLA) Minimum local detection */
-#define   TCC_FCTRLA_CAPTURE_LOCMAX_Val   _U_(0x5)   /**< \brief (TCC_FCTRLA) Maximum local detection */
-#define   TCC_FCTRLA_CAPTURE_DERIV0_Val   _U_(0x6)   /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
-#define   TCC_FCTRLA_CAPTURE_CAPTMARK_Val _U_(0x7)   /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
-#define TCC_FCTRLA_CAPTURE_DISABLE  (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPT     (TCC_FCTRLA_CAPTURE_CAPT_Val   << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMIN  (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMAX  (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMIN   (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_LOCMAX   (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_DERIV0   (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
-#define TCC_FCTRLA_BLANKPRESC_Pos   15           /**< \brief (TCC_FCTRLA) Fault A Blanking Prescaler */
-#define TCC_FCTRLA_BLANKPRESC       (_U_(0x1) << TCC_FCTRLA_BLANKPRESC_Pos)
-#define TCC_FCTRLA_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
-#define TCC_FCTRLA_BLANKVAL_Msk     (_U_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos)
-#define TCC_FCTRLA_BLANKVAL(value)  (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
-#define TCC_FCTRLA_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLA) Fault A Filter Value */
-#define TCC_FCTRLA_FILTERVAL_Msk    (_U_(0xF) << TCC_FCTRLA_FILTERVAL_Pos)
-#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
-#define TCC_FCTRLA_MASK             _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLA) MASK Register */
-
-/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t SRC:2;            /*!< bit:  0.. 1  Fault B Source                     */
-    uint32_t :1;               /*!< bit:      2  Reserved                           */
-    uint32_t KEEP:1;           /*!< bit:      3  Fault B Keeper                     */
-    uint32_t QUAL:1;           /*!< bit:      4  Fault B Qualification              */
-    uint32_t BLANK:2;          /*!< bit:  5.. 6  Fault B Blanking Mode              */
-    uint32_t RESTART:1;        /*!< bit:      7  Fault B Restart                    */
-    uint32_t HALT:2;           /*!< bit:  8.. 9  Fault B Halt Mode                  */
-    uint32_t CHSEL:2;          /*!< bit: 10..11  Fault B Capture Channel            */
-    uint32_t CAPTURE:3;        /*!< bit: 12..14  Fault B Capture Action             */
-    uint32_t BLANKPRESC:1;     /*!< bit:     15  Fault B Blanking Prescaler         */
-    uint32_t BLANKVAL:8;       /*!< bit: 16..23  Fault B Blanking Time              */
-    uint32_t FILTERVAL:4;      /*!< bit: 24..27  Fault B Filter Value               */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_FCTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_FCTRLB_OFFSET           0x10         /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
-#define TCC_FCTRLB_RESETVALUE       _U_(0x00000000) /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
-
-#define TCC_FCTRLB_SRC_Pos          0            /**< \brief (TCC_FCTRLB) Fault B Source */
-#define TCC_FCTRLB_SRC_Msk          (_U_(0x3) << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC(value)       (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
-#define   TCC_FCTRLB_SRC_DISABLE_Val      _U_(0x0)   /**< \brief (TCC_FCTRLB) Fault input disabled */
-#define   TCC_FCTRLB_SRC_ENABLE_Val       _U_(0x1)   /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
-#define   TCC_FCTRLB_SRC_INVERT_Val       _U_(0x2)   /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
-#define   TCC_FCTRLB_SRC_ALTFAULT_Val     _U_(0x3)   /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
-#define TCC_FCTRLB_SRC_DISABLE      (TCC_FCTRLB_SRC_DISABLE_Val    << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ENABLE       (TCC_FCTRLB_SRC_ENABLE_Val     << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_INVERT       (TCC_FCTRLB_SRC_INVERT_Val     << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_SRC_ALTFAULT     (TCC_FCTRLB_SRC_ALTFAULT_Val   << TCC_FCTRLB_SRC_Pos)
-#define TCC_FCTRLB_KEEP_Pos         3            /**< \brief (TCC_FCTRLB) Fault B Keeper */
-#define TCC_FCTRLB_KEEP             (_U_(0x1) << TCC_FCTRLB_KEEP_Pos)
-#define TCC_FCTRLB_QUAL_Pos         4            /**< \brief (TCC_FCTRLB) Fault B Qualification */
-#define TCC_FCTRLB_QUAL             (_U_(0x1) << TCC_FCTRLB_QUAL_Pos)
-#define TCC_FCTRLB_BLANK_Pos        5            /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
-#define TCC_FCTRLB_BLANK_Msk        (_U_(0x3) << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK(value)     (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
-#define   TCC_FCTRLB_BLANK_START_Val      _U_(0x0)   /**< \brief (TCC_FCTRLB) Blanking applied from start of the ramp */
-#define   TCC_FCTRLB_BLANK_RISE_Val       _U_(0x1)   /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
-#define   TCC_FCTRLB_BLANK_FALL_Val       _U_(0x2)   /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
-#define   TCC_FCTRLB_BLANK_BOTH_Val       _U_(0x3)   /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
-#define TCC_FCTRLB_BLANK_START      (TCC_FCTRLB_BLANK_START_Val    << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_RISE       (TCC_FCTRLB_BLANK_RISE_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_FALL       (TCC_FCTRLB_BLANK_FALL_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_BLANK_BOTH       (TCC_FCTRLB_BLANK_BOTH_Val     << TCC_FCTRLB_BLANK_Pos)
-#define TCC_FCTRLB_RESTART_Pos      7            /**< \brief (TCC_FCTRLB) Fault B Restart */
-#define TCC_FCTRLB_RESTART          (_U_(0x1) << TCC_FCTRLB_RESTART_Pos)
-#define TCC_FCTRLB_HALT_Pos         8            /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
-#define TCC_FCTRLB_HALT_Msk         (_U_(0x3) << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT(value)      (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
-#define   TCC_FCTRLB_HALT_DISABLE_Val     _U_(0x0)   /**< \brief (TCC_FCTRLB) Halt action disabled */
-#define   TCC_FCTRLB_HALT_HW_Val          _U_(0x1)   /**< \brief (TCC_FCTRLB) Hardware halt action */
-#define   TCC_FCTRLB_HALT_SW_Val          _U_(0x2)   /**< \brief (TCC_FCTRLB) Software halt action */
-#define   TCC_FCTRLB_HALT_NR_Val          _U_(0x3)   /**< \brief (TCC_FCTRLB) Non-recoverable fault */
-#define TCC_FCTRLB_HALT_DISABLE     (TCC_FCTRLB_HALT_DISABLE_Val   << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_HW          (TCC_FCTRLB_HALT_HW_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_SW          (TCC_FCTRLB_HALT_SW_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_HALT_NR          (TCC_FCTRLB_HALT_NR_Val        << TCC_FCTRLB_HALT_Pos)
-#define TCC_FCTRLB_CHSEL_Pos        10           /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
-#define TCC_FCTRLB_CHSEL_Msk        (_U_(0x3) << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL(value)     (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
-#define   TCC_FCTRLB_CHSEL_CC0_Val        _U_(0x0)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
-#define   TCC_FCTRLB_CHSEL_CC1_Val        _U_(0x1)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
-#define   TCC_FCTRLB_CHSEL_CC2_Val        _U_(0x2)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
-#define   TCC_FCTRLB_CHSEL_CC3_Val        _U_(0x3)   /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
-#define TCC_FCTRLB_CHSEL_CC0        (TCC_FCTRLB_CHSEL_CC0_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC1        (TCC_FCTRLB_CHSEL_CC1_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC2        (TCC_FCTRLB_CHSEL_CC2_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CHSEL_CC3        (TCC_FCTRLB_CHSEL_CC3_Val      << TCC_FCTRLB_CHSEL_Pos)
-#define TCC_FCTRLB_CAPTURE_Pos      12           /**< \brief (TCC_FCTRLB) Fault B Capture Action */
-#define TCC_FCTRLB_CAPTURE_Msk      (_U_(0x7) << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE(value)   (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
-#define   TCC_FCTRLB_CAPTURE_DISABLE_Val  _U_(0x0)   /**< \brief (TCC_FCTRLB) No capture */
-#define   TCC_FCTRLB_CAPTURE_CAPT_Val     _U_(0x1)   /**< \brief (TCC_FCTRLB) Capture on fault */
-#define   TCC_FCTRLB_CAPTURE_CAPTMIN_Val  _U_(0x2)   /**< \brief (TCC_FCTRLB) Minimum capture */
-#define   TCC_FCTRLB_CAPTURE_CAPTMAX_Val  _U_(0x3)   /**< \brief (TCC_FCTRLB) Maximum capture */
-#define   TCC_FCTRLB_CAPTURE_LOCMIN_Val   _U_(0x4)   /**< \brief (TCC_FCTRLB) Minimum local detection */
-#define   TCC_FCTRLB_CAPTURE_LOCMAX_Val   _U_(0x5)   /**< \brief (TCC_FCTRLB) Maximum local detection */
-#define   TCC_FCTRLB_CAPTURE_DERIV0_Val   _U_(0x6)   /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
-#define   TCC_FCTRLB_CAPTURE_CAPTMARK_Val _U_(0x7)   /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
-#define TCC_FCTRLB_CAPTURE_DISABLE  (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPT     (TCC_FCTRLB_CAPTURE_CAPT_Val   << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMIN  (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMAX  (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMIN   (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_LOCMAX   (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_DERIV0   (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
-#define TCC_FCTRLB_BLANKPRESC_Pos   15           /**< \brief (TCC_FCTRLB) Fault B Blanking Prescaler */
-#define TCC_FCTRLB_BLANKPRESC       (_U_(0x1) << TCC_FCTRLB_BLANKPRESC_Pos)
-#define TCC_FCTRLB_BLANKVAL_Pos     16           /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
-#define TCC_FCTRLB_BLANKVAL_Msk     (_U_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos)
-#define TCC_FCTRLB_BLANKVAL(value)  (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
-#define TCC_FCTRLB_FILTERVAL_Pos    24           /**< \brief (TCC_FCTRLB) Fault B Filter Value */
-#define TCC_FCTRLB_FILTERVAL_Msk    (_U_(0xF) << TCC_FCTRLB_FILTERVAL_Pos)
-#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
-#define TCC_FCTRLB_MASK             _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLB) MASK Register */
-
-/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OTMX:2;           /*!< bit:  0.. 1  Output Matrix                      */
-    uint32_t :6;               /*!< bit:  2.. 7  Reserved                           */
-    uint32_t DTIEN0:1;         /*!< bit:      8  Dead-time Insertion Generator 0 Enable */
-    uint32_t DTIEN1:1;         /*!< bit:      9  Dead-time Insertion Generator 1 Enable */
-    uint32_t DTIEN2:1;         /*!< bit:     10  Dead-time Insertion Generator 2 Enable */
-    uint32_t DTIEN3:1;         /*!< bit:     11  Dead-time Insertion Generator 3 Enable */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t DTLS:8;           /*!< bit: 16..23  Dead-time Low Side Outputs Value   */
-    uint32_t DTHS:8;           /*!< bit: 24..31  Dead-time High Side Outputs Value  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t DTIEN:4;          /*!< bit:  8..11  Dead-time Insertion Generator x Enable */
-    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WEXCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WEXCTRL_OFFSET          0x14         /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
-#define TCC_WEXCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
-
-#define TCC_WEXCTRL_OTMX_Pos        0            /**< \brief (TCC_WEXCTRL) Output Matrix */
-#define TCC_WEXCTRL_OTMX_Msk        (_U_(0x3) << TCC_WEXCTRL_OTMX_Pos)
-#define TCC_WEXCTRL_OTMX(value)     (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
-#define TCC_WEXCTRL_DTIEN0_Pos      8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
-#define TCC_WEXCTRL_DTIEN0          (_U_(1) << TCC_WEXCTRL_DTIEN0_Pos)
-#define TCC_WEXCTRL_DTIEN1_Pos      9            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
-#define TCC_WEXCTRL_DTIEN1          (_U_(1) << TCC_WEXCTRL_DTIEN1_Pos)
-#define TCC_WEXCTRL_DTIEN2_Pos      10           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
-#define TCC_WEXCTRL_DTIEN2          (_U_(1) << TCC_WEXCTRL_DTIEN2_Pos)
-#define TCC_WEXCTRL_DTIEN3_Pos      11           /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
-#define TCC_WEXCTRL_DTIEN3          (_U_(1) << TCC_WEXCTRL_DTIEN3_Pos)
-#define TCC_WEXCTRL_DTIEN_Pos       8            /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
-#define TCC_WEXCTRL_DTIEN_Msk       (_U_(0xF) << TCC_WEXCTRL_DTIEN_Pos)
-#define TCC_WEXCTRL_DTIEN(value)    (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
-#define TCC_WEXCTRL_DTLS_Pos        16           /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
-#define TCC_WEXCTRL_DTLS_Msk        (_U_(0xFF) << TCC_WEXCTRL_DTLS_Pos)
-#define TCC_WEXCTRL_DTLS(value)     (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
-#define TCC_WEXCTRL_DTHS_Pos        24           /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
-#define TCC_WEXCTRL_DTHS_Msk        (_U_(0xFF) << TCC_WEXCTRL_DTHS_Pos)
-#define TCC_WEXCTRL_DTHS(value)     (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
-#define TCC_WEXCTRL_MASK            _U_(0xFFFF0F03) /**< \brief (TCC_WEXCTRL) MASK Register */
-
-/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t NRE0:1;           /*!< bit:      0  Non-Recoverable State 0 Output Enable */
-    uint32_t NRE1:1;           /*!< bit:      1  Non-Recoverable State 1 Output Enable */
-    uint32_t NRE2:1;           /*!< bit:      2  Non-Recoverable State 2 Output Enable */
-    uint32_t NRE3:1;           /*!< bit:      3  Non-Recoverable State 3 Output Enable */
-    uint32_t NRE4:1;           /*!< bit:      4  Non-Recoverable State 4 Output Enable */
-    uint32_t NRE5:1;           /*!< bit:      5  Non-Recoverable State 5 Output Enable */
-    uint32_t NRE6:1;           /*!< bit:      6  Non-Recoverable State 6 Output Enable */
-    uint32_t NRE7:1;           /*!< bit:      7  Non-Recoverable State 7 Output Enable */
-    uint32_t NRV0:1;           /*!< bit:      8  Non-Recoverable State 0 Output Value */
-    uint32_t NRV1:1;           /*!< bit:      9  Non-Recoverable State 1 Output Value */
-    uint32_t NRV2:1;           /*!< bit:     10  Non-Recoverable State 2 Output Value */
-    uint32_t NRV3:1;           /*!< bit:     11  Non-Recoverable State 3 Output Value */
-    uint32_t NRV4:1;           /*!< bit:     12  Non-Recoverable State 4 Output Value */
-    uint32_t NRV5:1;           /*!< bit:     13  Non-Recoverable State 5 Output Value */
-    uint32_t NRV6:1;           /*!< bit:     14  Non-Recoverable State 6 Output Value */
-    uint32_t NRV7:1;           /*!< bit:     15  Non-Recoverable State 7 Output Value */
-    uint32_t INVEN0:1;         /*!< bit:     16  Output Waveform 0 Inversion        */
-    uint32_t INVEN1:1;         /*!< bit:     17  Output Waveform 1 Inversion        */
-    uint32_t INVEN2:1;         /*!< bit:     18  Output Waveform 2 Inversion        */
-    uint32_t INVEN3:1;         /*!< bit:     19  Output Waveform 3 Inversion        */
-    uint32_t INVEN4:1;         /*!< bit:     20  Output Waveform 4 Inversion        */
-    uint32_t INVEN5:1;         /*!< bit:     21  Output Waveform 5 Inversion        */
-    uint32_t INVEN6:1;         /*!< bit:     22  Output Waveform 6 Inversion        */
-    uint32_t INVEN7:1;         /*!< bit:     23  Output Waveform 7 Inversion        */
-    uint32_t FILTERVAL0:4;     /*!< bit: 24..27  Non-Recoverable Fault Input 0 Filter Value */
-    uint32_t FILTERVAL1:4;     /*!< bit: 28..31  Non-Recoverable Fault Input 1 Filter Value */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t NRE:8;            /*!< bit:  0.. 7  Non-Recoverable State x Output Enable */
-    uint32_t NRV:8;            /*!< bit:  8..15  Non-Recoverable State x Output Value */
-    uint32_t INVEN:8;          /*!< bit: 16..23  Output Waveform x Inversion        */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_DRVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DRVCTRL_OFFSET          0x18         /**< \brief (TCC_DRVCTRL offset) Driver Control */
-#define TCC_DRVCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
-
-#define TCC_DRVCTRL_NRE0_Pos        0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
-#define TCC_DRVCTRL_NRE0            (_U_(1) << TCC_DRVCTRL_NRE0_Pos)
-#define TCC_DRVCTRL_NRE1_Pos        1            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
-#define TCC_DRVCTRL_NRE1            (_U_(1) << TCC_DRVCTRL_NRE1_Pos)
-#define TCC_DRVCTRL_NRE2_Pos        2            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
-#define TCC_DRVCTRL_NRE2            (_U_(1) << TCC_DRVCTRL_NRE2_Pos)
-#define TCC_DRVCTRL_NRE3_Pos        3            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
-#define TCC_DRVCTRL_NRE3            (_U_(1) << TCC_DRVCTRL_NRE3_Pos)
-#define TCC_DRVCTRL_NRE4_Pos        4            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
-#define TCC_DRVCTRL_NRE4            (_U_(1) << TCC_DRVCTRL_NRE4_Pos)
-#define TCC_DRVCTRL_NRE5_Pos        5            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
-#define TCC_DRVCTRL_NRE5            (_U_(1) << TCC_DRVCTRL_NRE5_Pos)
-#define TCC_DRVCTRL_NRE6_Pos        6            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
-#define TCC_DRVCTRL_NRE6            (_U_(1) << TCC_DRVCTRL_NRE6_Pos)
-#define TCC_DRVCTRL_NRE7_Pos        7            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
-#define TCC_DRVCTRL_NRE7            (_U_(1) << TCC_DRVCTRL_NRE7_Pos)
-#define TCC_DRVCTRL_NRE_Pos         0            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
-#define TCC_DRVCTRL_NRE_Msk         (_U_(0xFF) << TCC_DRVCTRL_NRE_Pos)
-#define TCC_DRVCTRL_NRE(value)      (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
-#define TCC_DRVCTRL_NRV0_Pos        8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
-#define TCC_DRVCTRL_NRV0            (_U_(1) << TCC_DRVCTRL_NRV0_Pos)
-#define TCC_DRVCTRL_NRV1_Pos        9            /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
-#define TCC_DRVCTRL_NRV1            (_U_(1) << TCC_DRVCTRL_NRV1_Pos)
-#define TCC_DRVCTRL_NRV2_Pos        10           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
-#define TCC_DRVCTRL_NRV2            (_U_(1) << TCC_DRVCTRL_NRV2_Pos)
-#define TCC_DRVCTRL_NRV3_Pos        11           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
-#define TCC_DRVCTRL_NRV3            (_U_(1) << TCC_DRVCTRL_NRV3_Pos)
-#define TCC_DRVCTRL_NRV4_Pos        12           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
-#define TCC_DRVCTRL_NRV4            (_U_(1) << TCC_DRVCTRL_NRV4_Pos)
-#define TCC_DRVCTRL_NRV5_Pos        13           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
-#define TCC_DRVCTRL_NRV5            (_U_(1) << TCC_DRVCTRL_NRV5_Pos)
-#define TCC_DRVCTRL_NRV6_Pos        14           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
-#define TCC_DRVCTRL_NRV6            (_U_(1) << TCC_DRVCTRL_NRV6_Pos)
-#define TCC_DRVCTRL_NRV7_Pos        15           /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
-#define TCC_DRVCTRL_NRV7            (_U_(1) << TCC_DRVCTRL_NRV7_Pos)
-#define TCC_DRVCTRL_NRV_Pos         8            /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
-#define TCC_DRVCTRL_NRV_Msk         (_U_(0xFF) << TCC_DRVCTRL_NRV_Pos)
-#define TCC_DRVCTRL_NRV(value)      (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
-#define TCC_DRVCTRL_INVEN0_Pos      16           /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
-#define TCC_DRVCTRL_INVEN0          (_U_(1) << TCC_DRVCTRL_INVEN0_Pos)
-#define TCC_DRVCTRL_INVEN1_Pos      17           /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
-#define TCC_DRVCTRL_INVEN1          (_U_(1) << TCC_DRVCTRL_INVEN1_Pos)
-#define TCC_DRVCTRL_INVEN2_Pos      18           /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
-#define TCC_DRVCTRL_INVEN2          (_U_(1) << TCC_DRVCTRL_INVEN2_Pos)
-#define TCC_DRVCTRL_INVEN3_Pos      19           /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
-#define TCC_DRVCTRL_INVEN3          (_U_(1) << TCC_DRVCTRL_INVEN3_Pos)
-#define TCC_DRVCTRL_INVEN4_Pos      20           /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
-#define TCC_DRVCTRL_INVEN4          (_U_(1) << TCC_DRVCTRL_INVEN4_Pos)
-#define TCC_DRVCTRL_INVEN5_Pos      21           /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
-#define TCC_DRVCTRL_INVEN5          (_U_(1) << TCC_DRVCTRL_INVEN5_Pos)
-#define TCC_DRVCTRL_INVEN6_Pos      22           /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
-#define TCC_DRVCTRL_INVEN6          (_U_(1) << TCC_DRVCTRL_INVEN6_Pos)
-#define TCC_DRVCTRL_INVEN7_Pos      23           /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
-#define TCC_DRVCTRL_INVEN7          (_U_(1) << TCC_DRVCTRL_INVEN7_Pos)
-#define TCC_DRVCTRL_INVEN_Pos       16           /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
-#define TCC_DRVCTRL_INVEN_Msk       (_U_(0xFF) << TCC_DRVCTRL_INVEN_Pos)
-#define TCC_DRVCTRL_INVEN(value)    (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
-#define TCC_DRVCTRL_FILTERVAL0_Pos  24           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL0_Msk  (_U_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos)
-#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
-#define TCC_DRVCTRL_FILTERVAL1_Pos  28           /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
-#define TCC_DRVCTRL_FILTERVAL1_Msk  (_U_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos)
-#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
-#define TCC_DRVCTRL_MASK            _U_(0xFFFFFFFF) /**< \brief (TCC_DRVCTRL) MASK Register */
-
-/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W  8) Debug Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Running Mode                 */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  FDDBD:1;          /*!< bit:      2  Fault Detection on Debug Break Detection */
-    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TCC_DBGCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_DBGCTRL_OFFSET          0x1E         /**< \brief (TCC_DBGCTRL offset) Debug Control */
-#define TCC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
-
-#define TCC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (TCC_DBGCTRL) Debug Running Mode */
-#define TCC_DBGCTRL_DBGRUN          (_U_(0x1) << TCC_DBGCTRL_DBGRUN_Pos)
-#define TCC_DBGCTRL_FDDBD_Pos       2            /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
-#define TCC_DBGCTRL_FDDBD           (_U_(0x1) << TCC_DBGCTRL_FDDBD_Pos)
-#define TCC_DBGCTRL_MASK            _U_(0x05)    /**< \brief (TCC_DBGCTRL) MASK Register */
-
-/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t EVACT0:3;         /*!< bit:  0.. 2  Timer/counter Input Event0 Action  */
-    uint32_t EVACT1:3;         /*!< bit:  3.. 5  Timer/counter Input Event1 Action  */
-    uint32_t CNTSEL:2;         /*!< bit:  6.. 7  Timer/counter Output Event Mode    */
-    uint32_t OVFEO:1;          /*!< bit:      8  Overflow/Underflow Output Event Enable */
-    uint32_t TRGEO:1;          /*!< bit:      9  Retrigger Output Event Enable      */
-    uint32_t CNTEO:1;          /*!< bit:     10  Timer/counter Output Event Enable  */
-    uint32_t :1;               /*!< bit:     11  Reserved                           */
-    uint32_t TCINV0:1;         /*!< bit:     12  Inverted Event 0 Input Enable      */
-    uint32_t TCINV1:1;         /*!< bit:     13  Inverted Event 1 Input Enable      */
-    uint32_t TCEI0:1;          /*!< bit:     14  Timer/counter Event 0 Input Enable */
-    uint32_t TCEI1:1;          /*!< bit:     15  Timer/counter Event 1 Input Enable */
-    uint32_t MCEI0:1;          /*!< bit:     16  Match or Capture Channel 0 Event Input Enable */
-    uint32_t MCEI1:1;          /*!< bit:     17  Match or Capture Channel 1 Event Input Enable */
-    uint32_t MCEI2:1;          /*!< bit:     18  Match or Capture Channel 2 Event Input Enable */
-    uint32_t MCEI3:1;          /*!< bit:     19  Match or Capture Channel 3 Event Input Enable */
-    uint32_t MCEI4:1;          /*!< bit:     20  Match or Capture Channel 4 Event Input Enable */
-    uint32_t MCEI5:1;          /*!< bit:     21  Match or Capture Channel 5 Event Input Enable */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t MCEO0:1;          /*!< bit:     24  Match or Capture Channel 0 Event Output Enable */
-    uint32_t MCEO1:1;          /*!< bit:     25  Match or Capture Channel 1 Event Output Enable */
-    uint32_t MCEO2:1;          /*!< bit:     26  Match or Capture Channel 2 Event Output Enable */
-    uint32_t MCEO3:1;          /*!< bit:     27  Match or Capture Channel 3 Event Output Enable */
-    uint32_t MCEO4:1;          /*!< bit:     28  Match or Capture Channel 4 Event Output Enable */
-    uint32_t MCEO5:1;          /*!< bit:     29  Match or Capture Channel 5 Event Output Enable */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :12;              /*!< bit:  0..11  Reserved                           */
-    uint32_t TCINV:2;          /*!< bit: 12..13  Inverted Event x Input Enable      */
-    uint32_t TCEI:2;           /*!< bit: 14..15  Timer/counter Event x Input Enable */
-    uint32_t MCEI:6;           /*!< bit: 16..21  Match or Capture Channel x Event Input Enable */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t MCEO:6;           /*!< bit: 24..29  Match or Capture Channel x Event Output Enable */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_EVCTRL_OFFSET           0x20         /**< \brief (TCC_EVCTRL offset) Event Control */
-#define TCC_EVCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (TCC_EVCTRL reset_value) Event Control */
-
-#define TCC_EVCTRL_EVACT0_Pos       0            /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
-#define TCC_EVCTRL_EVACT0_Msk       (_U_(0x7) << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0(value)    (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
-#define   TCC_EVCTRL_EVACT0_OFF_Val       _U_(0x0)   /**< \brief (TCC_EVCTRL) Event action disabled */
-#define   TCC_EVCTRL_EVACT0_RETRIGGER_Val _U_(0x1)   /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
-#define   TCC_EVCTRL_EVACT0_COUNTEV_Val   _U_(0x2)   /**< \brief (TCC_EVCTRL) Count on event */
-#define   TCC_EVCTRL_EVACT0_START_Val     _U_(0x3)   /**< \brief (TCC_EVCTRL) Start counter on event */
-#define   TCC_EVCTRL_EVACT0_INC_Val       _U_(0x4)   /**< \brief (TCC_EVCTRL) Increment counter on event */
-#define   TCC_EVCTRL_EVACT0_COUNT_Val     _U_(0x5)   /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
-#define   TCC_EVCTRL_EVACT0_STAMP_Val     _U_(0x6)   /**< \brief (TCC_EVCTRL) Stamp capture */
-#define   TCC_EVCTRL_EVACT0_FAULT_Val     _U_(0x7)   /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT0_OFF       (TCC_EVCTRL_EVACT0_OFF_Val     << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNTEV   (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_START     (TCC_EVCTRL_EVACT0_START_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_INC       (TCC_EVCTRL_EVACT0_INC_Val     << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_COUNT     (TCC_EVCTRL_EVACT0_COUNT_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_STAMP     (TCC_EVCTRL_EVACT0_STAMP_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT0_FAULT     (TCC_EVCTRL_EVACT0_FAULT_Val   << TCC_EVCTRL_EVACT0_Pos)
-#define TCC_EVCTRL_EVACT1_Pos       3            /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
-#define TCC_EVCTRL_EVACT1_Msk       (_U_(0x7) << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1(value)    (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
-#define   TCC_EVCTRL_EVACT1_OFF_Val       _U_(0x0)   /**< \brief (TCC_EVCTRL) Event action disabled */
-#define   TCC_EVCTRL_EVACT1_RETRIGGER_Val _U_(0x1)   /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
-#define   TCC_EVCTRL_EVACT1_DIR_Val       _U_(0x2)   /**< \brief (TCC_EVCTRL) Direction control */
-#define   TCC_EVCTRL_EVACT1_STOP_Val      _U_(0x3)   /**< \brief (TCC_EVCTRL) Stop counter on event */
-#define   TCC_EVCTRL_EVACT1_DEC_Val       _U_(0x4)   /**< \brief (TCC_EVCTRL) Decrement counter on event */
-#define   TCC_EVCTRL_EVACT1_PPW_Val       _U_(0x5)   /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
-#define   TCC_EVCTRL_EVACT1_PWP_Val       _U_(0x6)   /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
-#define   TCC_EVCTRL_EVACT1_FAULT_Val     _U_(0x7)   /**< \brief (TCC_EVCTRL) Non-recoverable fault */
-#define TCC_EVCTRL_EVACT1_OFF       (TCC_EVCTRL_EVACT1_OFF_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DIR       (TCC_EVCTRL_EVACT1_DIR_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_STOP      (TCC_EVCTRL_EVACT1_STOP_Val    << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_DEC       (TCC_EVCTRL_EVACT1_DEC_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PPW       (TCC_EVCTRL_EVACT1_PPW_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_PWP       (TCC_EVCTRL_EVACT1_PWP_Val     << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_EVACT1_FAULT     (TCC_EVCTRL_EVACT1_FAULT_Val   << TCC_EVCTRL_EVACT1_Pos)
-#define TCC_EVCTRL_CNTSEL_Pos       6            /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
-#define TCC_EVCTRL_CNTSEL_Msk       (_U_(0x3) << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL(value)    (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
-#define   TCC_EVCTRL_CNTSEL_START_Val     _U_(0x0)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
-#define   TCC_EVCTRL_CNTSEL_END_Val       _U_(0x1)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
-#define   TCC_EVCTRL_CNTSEL_BETWEEN_Val   _U_(0x2)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
-#define   TCC_EVCTRL_CNTSEL_BOUNDARY_Val  _U_(0x3)   /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
-#define TCC_EVCTRL_CNTSEL_START     (TCC_EVCTRL_CNTSEL_START_Val   << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_END       (TCC_EVCTRL_CNTSEL_END_Val     << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BETWEEN   (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_CNTSEL_BOUNDARY  (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
-#define TCC_EVCTRL_OVFEO_Pos        8            /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
-#define TCC_EVCTRL_OVFEO            (_U_(0x1) << TCC_EVCTRL_OVFEO_Pos)
-#define TCC_EVCTRL_TRGEO_Pos        9            /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
-#define TCC_EVCTRL_TRGEO            (_U_(0x1) << TCC_EVCTRL_TRGEO_Pos)
-#define TCC_EVCTRL_CNTEO_Pos        10           /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
-#define TCC_EVCTRL_CNTEO            (_U_(0x1) << TCC_EVCTRL_CNTEO_Pos)
-#define TCC_EVCTRL_TCINV0_Pos       12           /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
-#define TCC_EVCTRL_TCINV0           (_U_(1) << TCC_EVCTRL_TCINV0_Pos)
-#define TCC_EVCTRL_TCINV1_Pos       13           /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
-#define TCC_EVCTRL_TCINV1           (_U_(1) << TCC_EVCTRL_TCINV1_Pos)
-#define TCC_EVCTRL_TCINV_Pos        12           /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
-#define TCC_EVCTRL_TCINV_Msk        (_U_(0x3) << TCC_EVCTRL_TCINV_Pos)
-#define TCC_EVCTRL_TCINV(value)     (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
-#define TCC_EVCTRL_TCEI0_Pos        14           /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
-#define TCC_EVCTRL_TCEI0            (_U_(1) << TCC_EVCTRL_TCEI0_Pos)
-#define TCC_EVCTRL_TCEI1_Pos        15           /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
-#define TCC_EVCTRL_TCEI1            (_U_(1) << TCC_EVCTRL_TCEI1_Pos)
-#define TCC_EVCTRL_TCEI_Pos         14           /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
-#define TCC_EVCTRL_TCEI_Msk         (_U_(0x3) << TCC_EVCTRL_TCEI_Pos)
-#define TCC_EVCTRL_TCEI(value)      (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
-#define TCC_EVCTRL_MCEI0_Pos        16           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
-#define TCC_EVCTRL_MCEI0            (_U_(1) << TCC_EVCTRL_MCEI0_Pos)
-#define TCC_EVCTRL_MCEI1_Pos        17           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
-#define TCC_EVCTRL_MCEI1            (_U_(1) << TCC_EVCTRL_MCEI1_Pos)
-#define TCC_EVCTRL_MCEI2_Pos        18           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
-#define TCC_EVCTRL_MCEI2            (_U_(1) << TCC_EVCTRL_MCEI2_Pos)
-#define TCC_EVCTRL_MCEI3_Pos        19           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
-#define TCC_EVCTRL_MCEI3            (_U_(1) << TCC_EVCTRL_MCEI3_Pos)
-#define TCC_EVCTRL_MCEI4_Pos        20           /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Input Enable */
-#define TCC_EVCTRL_MCEI4            (_U_(1) << TCC_EVCTRL_MCEI4_Pos)
-#define TCC_EVCTRL_MCEI5_Pos        21           /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Input Enable */
-#define TCC_EVCTRL_MCEI5            (_U_(1) << TCC_EVCTRL_MCEI5_Pos)
-#define TCC_EVCTRL_MCEI_Pos         16           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
-#define TCC_EVCTRL_MCEI_Msk         (_U_(0x3F) << TCC_EVCTRL_MCEI_Pos)
-#define TCC_EVCTRL_MCEI(value)      (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
-#define TCC_EVCTRL_MCEO0_Pos        24           /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
-#define TCC_EVCTRL_MCEO0            (_U_(1) << TCC_EVCTRL_MCEO0_Pos)
-#define TCC_EVCTRL_MCEO1_Pos        25           /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
-#define TCC_EVCTRL_MCEO1            (_U_(1) << TCC_EVCTRL_MCEO1_Pos)
-#define TCC_EVCTRL_MCEO2_Pos        26           /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
-#define TCC_EVCTRL_MCEO2            (_U_(1) << TCC_EVCTRL_MCEO2_Pos)
-#define TCC_EVCTRL_MCEO3_Pos        27           /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
-#define TCC_EVCTRL_MCEO3            (_U_(1) << TCC_EVCTRL_MCEO3_Pos)
-#define TCC_EVCTRL_MCEO4_Pos        28           /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Output Enable */
-#define TCC_EVCTRL_MCEO4            (_U_(1) << TCC_EVCTRL_MCEO4_Pos)
-#define TCC_EVCTRL_MCEO5_Pos        29           /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Output Enable */
-#define TCC_EVCTRL_MCEO5            (_U_(1) << TCC_EVCTRL_MCEO5_Pos)
-#define TCC_EVCTRL_MCEO_Pos         24           /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
-#define TCC_EVCTRL_MCEO_Msk         (_U_(0x3F) << TCC_EVCTRL_MCEO_Pos)
-#define TCC_EVCTRL_MCEO(value)      (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
-#define TCC_EVCTRL_MASK             _U_(0x3F3FF7FF) /**< \brief (TCC_EVCTRL) MASK Register */
-
-/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
-    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
-    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
-    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
-    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
-    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
-    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
-    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
-    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
-    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
-    uint32_t MC4:1;            /*!< bit:     20  Match or Capture Channel 4 Interrupt Enable */
-    uint32_t MC5:1;            /*!< bit:     21  Match or Capture Channel 5 Interrupt Enable */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t MC:6;             /*!< bit: 16..21  Match or Capture Channel x Interrupt Enable */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENCLR_OFFSET         0x24         /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
-#define TCC_INTENCLR_RESETVALUE     _U_(0x00000000) /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TCC_INTENCLR_OVF_Pos        0            /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
-#define TCC_INTENCLR_OVF            (_U_(0x1) << TCC_INTENCLR_OVF_Pos)
-#define TCC_INTENCLR_TRG_Pos        1            /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
-#define TCC_INTENCLR_TRG            (_U_(0x1) << TCC_INTENCLR_TRG_Pos)
-#define TCC_INTENCLR_CNT_Pos        2            /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
-#define TCC_INTENCLR_CNT            (_U_(0x1) << TCC_INTENCLR_CNT_Pos)
-#define TCC_INTENCLR_ERR_Pos        3            /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
-#define TCC_INTENCLR_ERR            (_U_(0x1) << TCC_INTENCLR_ERR_Pos)
-#define TCC_INTENCLR_UFS_Pos        10           /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
-#define TCC_INTENCLR_UFS            (_U_(0x1) << TCC_INTENCLR_UFS_Pos)
-#define TCC_INTENCLR_DFS_Pos        11           /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENCLR_DFS            (_U_(0x1) << TCC_INTENCLR_DFS_Pos)
-#define TCC_INTENCLR_FAULTA_Pos     12           /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENCLR_FAULTA         (_U_(0x1) << TCC_INTENCLR_FAULTA_Pos)
-#define TCC_INTENCLR_FAULTB_Pos     13           /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENCLR_FAULTB         (_U_(0x1) << TCC_INTENCLR_FAULTB_Pos)
-#define TCC_INTENCLR_FAULT0_Pos     14           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENCLR_FAULT0         (_U_(0x1) << TCC_INTENCLR_FAULT0_Pos)
-#define TCC_INTENCLR_FAULT1_Pos     15           /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENCLR_FAULT1         (_U_(0x1) << TCC_INTENCLR_FAULT1_Pos)
-#define TCC_INTENCLR_MC0_Pos        16           /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENCLR_MC0            (_U_(1) << TCC_INTENCLR_MC0_Pos)
-#define TCC_INTENCLR_MC1_Pos        17           /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENCLR_MC1            (_U_(1) << TCC_INTENCLR_MC1_Pos)
-#define TCC_INTENCLR_MC2_Pos        18           /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENCLR_MC2            (_U_(1) << TCC_INTENCLR_MC2_Pos)
-#define TCC_INTENCLR_MC3_Pos        19           /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENCLR_MC3            (_U_(1) << TCC_INTENCLR_MC3_Pos)
-#define TCC_INTENCLR_MC4_Pos        20           /**< \brief (TCC_INTENCLR) Match or Capture Channel 4 Interrupt Enable */
-#define TCC_INTENCLR_MC4            (_U_(1) << TCC_INTENCLR_MC4_Pos)
-#define TCC_INTENCLR_MC5_Pos        21           /**< \brief (TCC_INTENCLR) Match or Capture Channel 5 Interrupt Enable */
-#define TCC_INTENCLR_MC5            (_U_(1) << TCC_INTENCLR_MC5_Pos)
-#define TCC_INTENCLR_MC_Pos         16           /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENCLR_MC_Msk         (_U_(0x3F) << TCC_INTENCLR_MC_Pos)
-#define TCC_INTENCLR_MC(value)      (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
-#define TCC_INTENCLR_MASK           _U_(0x003FFC0F) /**< \brief (TCC_INTENCLR) MASK Register */
-
-/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t OVF:1;            /*!< bit:      0  Overflow Interrupt Enable          */
-    uint32_t TRG:1;            /*!< bit:      1  Retrigger Interrupt Enable         */
-    uint32_t CNT:1;            /*!< bit:      2  Counter Interrupt Enable           */
-    uint32_t ERR:1;            /*!< bit:      3  Error Interrupt Enable             */
-    uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
-    uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault Interrupt Enable */
-    uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault Interrupt Enable */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A Interrupt Enable */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B Interrupt Enable */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 Interrupt Enable */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 Interrupt Enable */
-    uint32_t MC0:1;            /*!< bit:     16  Match or Capture Channel 0 Interrupt Enable */
-    uint32_t MC1:1;            /*!< bit:     17  Match or Capture Channel 1 Interrupt Enable */
-    uint32_t MC2:1;            /*!< bit:     18  Match or Capture Channel 2 Interrupt Enable */
-    uint32_t MC3:1;            /*!< bit:     19  Match or Capture Channel 3 Interrupt Enable */
-    uint32_t MC4:1;            /*!< bit:     20  Match or Capture Channel 4 Interrupt Enable */
-    uint32_t MC5:1;            /*!< bit:     21  Match or Capture Channel 5 Interrupt Enable */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t MC:6;             /*!< bit: 16..21  Match or Capture Channel x Interrupt Enable */
-    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTENSET_OFFSET         0x28         /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
-#define TCC_INTENSET_RESETVALUE     _U_(0x00000000) /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
-
-#define TCC_INTENSET_OVF_Pos        0            /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
-#define TCC_INTENSET_OVF            (_U_(0x1) << TCC_INTENSET_OVF_Pos)
-#define TCC_INTENSET_TRG_Pos        1            /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
-#define TCC_INTENSET_TRG            (_U_(0x1) << TCC_INTENSET_TRG_Pos)
-#define TCC_INTENSET_CNT_Pos        2            /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
-#define TCC_INTENSET_CNT            (_U_(0x1) << TCC_INTENSET_CNT_Pos)
-#define TCC_INTENSET_ERR_Pos        3            /**< \brief (TCC_INTENSET) Error Interrupt Enable */
-#define TCC_INTENSET_ERR            (_U_(0x1) << TCC_INTENSET_ERR_Pos)
-#define TCC_INTENSET_UFS_Pos        10           /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
-#define TCC_INTENSET_UFS            (_U_(0x1) << TCC_INTENSET_UFS_Pos)
-#define TCC_INTENSET_DFS_Pos        11           /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
-#define TCC_INTENSET_DFS            (_U_(0x1) << TCC_INTENSET_DFS_Pos)
-#define TCC_INTENSET_FAULTA_Pos     12           /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
-#define TCC_INTENSET_FAULTA         (_U_(0x1) << TCC_INTENSET_FAULTA_Pos)
-#define TCC_INTENSET_FAULTB_Pos     13           /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
-#define TCC_INTENSET_FAULTB         (_U_(0x1) << TCC_INTENSET_FAULTB_Pos)
-#define TCC_INTENSET_FAULT0_Pos     14           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
-#define TCC_INTENSET_FAULT0         (_U_(0x1) << TCC_INTENSET_FAULT0_Pos)
-#define TCC_INTENSET_FAULT1_Pos     15           /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
-#define TCC_INTENSET_FAULT1         (_U_(0x1) << TCC_INTENSET_FAULT1_Pos)
-#define TCC_INTENSET_MC0_Pos        16           /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
-#define TCC_INTENSET_MC0            (_U_(1) << TCC_INTENSET_MC0_Pos)
-#define TCC_INTENSET_MC1_Pos        17           /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
-#define TCC_INTENSET_MC1            (_U_(1) << TCC_INTENSET_MC1_Pos)
-#define TCC_INTENSET_MC2_Pos        18           /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
-#define TCC_INTENSET_MC2            (_U_(1) << TCC_INTENSET_MC2_Pos)
-#define TCC_INTENSET_MC3_Pos        19           /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
-#define TCC_INTENSET_MC3            (_U_(1) << TCC_INTENSET_MC3_Pos)
-#define TCC_INTENSET_MC4_Pos        20           /**< \brief (TCC_INTENSET) Match or Capture Channel 4 Interrupt Enable */
-#define TCC_INTENSET_MC4            (_U_(1) << TCC_INTENSET_MC4_Pos)
-#define TCC_INTENSET_MC5_Pos        21           /**< \brief (TCC_INTENSET) Match or Capture Channel 5 Interrupt Enable */
-#define TCC_INTENSET_MC5            (_U_(1) << TCC_INTENSET_MC5_Pos)
-#define TCC_INTENSET_MC_Pos         16           /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
-#define TCC_INTENSET_MC_Msk         (_U_(0x3F) << TCC_INTENSET_MC_Pos)
-#define TCC_INTENSET_MC(value)      (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
-#define TCC_INTENSET_MASK           _U_(0x003FFC0F) /**< \brief (TCC_INTENSET) MASK Register */
-
-/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
-    __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
-    __I uint32_t CNT:1;            /*!< bit:      2  Counter                            */
-    __I uint32_t ERR:1;            /*!< bit:      3  Error                              */
-    __I uint32_t :6;               /*!< bit:  4.. 9  Reserved                           */
-    __I uint32_t UFS:1;            /*!< bit:     10  Non-Recoverable Update Fault       */
-    __I uint32_t DFS:1;            /*!< bit:     11  Non-Recoverable Debug Fault        */
-    __I uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A                */
-    __I uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B                */
-    __I uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0            */
-    __I uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1            */
-    __I uint32_t MC0:1;            /*!< bit:     16  Match or Capture 0                 */
-    __I uint32_t MC1:1;            /*!< bit:     17  Match or Capture 1                 */
-    __I uint32_t MC2:1;            /*!< bit:     18  Match or Capture 2                 */
-    __I uint32_t MC3:1;            /*!< bit:     19  Match or Capture 3                 */
-    __I uint32_t MC4:1;            /*!< bit:     20  Match or Capture 4                 */
-    __I uint32_t MC5:1;            /*!< bit:     21  Match or Capture 5                 */
-    __I uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    __I uint32_t MC:6;             /*!< bit: 16..21  Match or Capture x                 */
-    __I uint32_t :10;              /*!< bit: 22..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_INTFLAG_OFFSET          0x2C         /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TCC_INTFLAG_RESETVALUE      _U_(0x00000000) /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TCC_INTFLAG_OVF_Pos         0            /**< \brief (TCC_INTFLAG) Overflow */
-#define TCC_INTFLAG_OVF             (_U_(0x1) << TCC_INTFLAG_OVF_Pos)
-#define TCC_INTFLAG_TRG_Pos         1            /**< \brief (TCC_INTFLAG) Retrigger */
-#define TCC_INTFLAG_TRG             (_U_(0x1) << TCC_INTFLAG_TRG_Pos)
-#define TCC_INTFLAG_CNT_Pos         2            /**< \brief (TCC_INTFLAG) Counter */
-#define TCC_INTFLAG_CNT             (_U_(0x1) << TCC_INTFLAG_CNT_Pos)
-#define TCC_INTFLAG_ERR_Pos         3            /**< \brief (TCC_INTFLAG) Error */
-#define TCC_INTFLAG_ERR             (_U_(0x1) << TCC_INTFLAG_ERR_Pos)
-#define TCC_INTFLAG_UFS_Pos         10           /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
-#define TCC_INTFLAG_UFS             (_U_(0x1) << TCC_INTFLAG_UFS_Pos)
-#define TCC_INTFLAG_DFS_Pos         11           /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
-#define TCC_INTFLAG_DFS             (_U_(0x1) << TCC_INTFLAG_DFS_Pos)
-#define TCC_INTFLAG_FAULTA_Pos      12           /**< \brief (TCC_INTFLAG) Recoverable Fault A */
-#define TCC_INTFLAG_FAULTA          (_U_(0x1) << TCC_INTFLAG_FAULTA_Pos)
-#define TCC_INTFLAG_FAULTB_Pos      13           /**< \brief (TCC_INTFLAG) Recoverable Fault B */
-#define TCC_INTFLAG_FAULTB          (_U_(0x1) << TCC_INTFLAG_FAULTB_Pos)
-#define TCC_INTFLAG_FAULT0_Pos      14           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
-#define TCC_INTFLAG_FAULT0          (_U_(0x1) << TCC_INTFLAG_FAULT0_Pos)
-#define TCC_INTFLAG_FAULT1_Pos      15           /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
-#define TCC_INTFLAG_FAULT1          (_U_(0x1) << TCC_INTFLAG_FAULT1_Pos)
-#define TCC_INTFLAG_MC0_Pos         16           /**< \brief (TCC_INTFLAG) Match or Capture 0 */
-#define TCC_INTFLAG_MC0             (_U_(1) << TCC_INTFLAG_MC0_Pos)
-#define TCC_INTFLAG_MC1_Pos         17           /**< \brief (TCC_INTFLAG) Match or Capture 1 */
-#define TCC_INTFLAG_MC1             (_U_(1) << TCC_INTFLAG_MC1_Pos)
-#define TCC_INTFLAG_MC2_Pos         18           /**< \brief (TCC_INTFLAG) Match or Capture 2 */
-#define TCC_INTFLAG_MC2             (_U_(1) << TCC_INTFLAG_MC2_Pos)
-#define TCC_INTFLAG_MC3_Pos         19           /**< \brief (TCC_INTFLAG) Match or Capture 3 */
-#define TCC_INTFLAG_MC3             (_U_(1) << TCC_INTFLAG_MC3_Pos)
-#define TCC_INTFLAG_MC4_Pos         20           /**< \brief (TCC_INTFLAG) Match or Capture 4 */
-#define TCC_INTFLAG_MC4             (_U_(1) << TCC_INTFLAG_MC4_Pos)
-#define TCC_INTFLAG_MC5_Pos         21           /**< \brief (TCC_INTFLAG) Match or Capture 5 */
-#define TCC_INTFLAG_MC5             (_U_(1) << TCC_INTFLAG_MC5_Pos)
-#define TCC_INTFLAG_MC_Pos          16           /**< \brief (TCC_INTFLAG) Match or Capture x */
-#define TCC_INTFLAG_MC_Msk          (_U_(0x3F) << TCC_INTFLAG_MC_Pos)
-#define TCC_INTFLAG_MC(value)       (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
-#define TCC_INTFLAG_MASK            _U_(0x003FFC0F) /**< \brief (TCC_INTFLAG) MASK Register */
-
-/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t STOP:1;           /*!< bit:      0  Stop                               */
-    uint32_t IDX:1;            /*!< bit:      1  Ramp                               */
-    uint32_t UFS:1;            /*!< bit:      2  Non-recoverable Update Fault State */
-    uint32_t DFS:1;            /*!< bit:      3  Non-Recoverable Debug Fault State  */
-    uint32_t SLAVE:1;          /*!< bit:      4  Slave                              */
-    uint32_t PATTBUFV:1;       /*!< bit:      5  Pattern Buffer Valid               */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t PERBUFV:1;        /*!< bit:      7  Period Buffer Valid                */
-    uint32_t FAULTAIN:1;       /*!< bit:      8  Recoverable Fault A Input          */
-    uint32_t FAULTBIN:1;       /*!< bit:      9  Recoverable Fault B Input          */
-    uint32_t FAULT0IN:1;       /*!< bit:     10  Non-Recoverable Fault0 Input       */
-    uint32_t FAULT1IN:1;       /*!< bit:     11  Non-Recoverable Fault1 Input       */
-    uint32_t FAULTA:1;         /*!< bit:     12  Recoverable Fault A State          */
-    uint32_t FAULTB:1;         /*!< bit:     13  Recoverable Fault B State          */
-    uint32_t FAULT0:1;         /*!< bit:     14  Non-Recoverable Fault 0 State      */
-    uint32_t FAULT1:1;         /*!< bit:     15  Non-Recoverable Fault 1 State      */
-    uint32_t CCBUFV0:1;        /*!< bit:     16  Compare Channel 0 Buffer Valid     */
-    uint32_t CCBUFV1:1;        /*!< bit:     17  Compare Channel 1 Buffer Valid     */
-    uint32_t CCBUFV2:1;        /*!< bit:     18  Compare Channel 2 Buffer Valid     */
-    uint32_t CCBUFV3:1;        /*!< bit:     19  Compare Channel 3 Buffer Valid     */
-    uint32_t CCBUFV4:1;        /*!< bit:     20  Compare Channel 4 Buffer Valid     */
-    uint32_t CCBUFV5:1;        /*!< bit:     21  Compare Channel 5 Buffer Valid     */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t CMP0:1;           /*!< bit:     24  Compare Channel 0 Value            */
-    uint32_t CMP1:1;           /*!< bit:     25  Compare Channel 1 Value            */
-    uint32_t CMP2:1;           /*!< bit:     26  Compare Channel 2 Value            */
-    uint32_t CMP3:1;           /*!< bit:     27  Compare Channel 3 Value            */
-    uint32_t CMP4:1;           /*!< bit:     28  Compare Channel 4 Value            */
-    uint32_t CMP5:1;           /*!< bit:     29  Compare Channel 5 Value            */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t CCBUFV:6;         /*!< bit: 16..21  Compare Channel x Buffer Valid     */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t CMP:6;            /*!< bit: 24..29  Compare Channel x Value            */
-    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_STATUS_OFFSET           0x30         /**< \brief (TCC_STATUS offset) Status */
-#define TCC_STATUS_RESETVALUE       _U_(0x00000001) /**< \brief (TCC_STATUS reset_value) Status */
-
-#define TCC_STATUS_STOP_Pos         0            /**< \brief (TCC_STATUS) Stop */
-#define TCC_STATUS_STOP             (_U_(0x1) << TCC_STATUS_STOP_Pos)
-#define TCC_STATUS_IDX_Pos          1            /**< \brief (TCC_STATUS) Ramp */
-#define TCC_STATUS_IDX              (_U_(0x1) << TCC_STATUS_IDX_Pos)
-#define TCC_STATUS_UFS_Pos          2            /**< \brief (TCC_STATUS) Non-recoverable Update Fault State */
-#define TCC_STATUS_UFS              (_U_(0x1) << TCC_STATUS_UFS_Pos)
-#define TCC_STATUS_DFS_Pos          3            /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
-#define TCC_STATUS_DFS              (_U_(0x1) << TCC_STATUS_DFS_Pos)
-#define TCC_STATUS_SLAVE_Pos        4            /**< \brief (TCC_STATUS) Slave */
-#define TCC_STATUS_SLAVE            (_U_(0x1) << TCC_STATUS_SLAVE_Pos)
-#define TCC_STATUS_PATTBUFV_Pos     5            /**< \brief (TCC_STATUS) Pattern Buffer Valid */
-#define TCC_STATUS_PATTBUFV         (_U_(0x1) << TCC_STATUS_PATTBUFV_Pos)
-#define TCC_STATUS_PERBUFV_Pos      7            /**< \brief (TCC_STATUS) Period Buffer Valid */
-#define TCC_STATUS_PERBUFV          (_U_(0x1) << TCC_STATUS_PERBUFV_Pos)
-#define TCC_STATUS_FAULTAIN_Pos     8            /**< \brief (TCC_STATUS) Recoverable Fault A Input */
-#define TCC_STATUS_FAULTAIN         (_U_(0x1) << TCC_STATUS_FAULTAIN_Pos)
-#define TCC_STATUS_FAULTBIN_Pos     9            /**< \brief (TCC_STATUS) Recoverable Fault B Input */
-#define TCC_STATUS_FAULTBIN         (_U_(0x1) << TCC_STATUS_FAULTBIN_Pos)
-#define TCC_STATUS_FAULT0IN_Pos     10           /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
-#define TCC_STATUS_FAULT0IN         (_U_(0x1) << TCC_STATUS_FAULT0IN_Pos)
-#define TCC_STATUS_FAULT1IN_Pos     11           /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
-#define TCC_STATUS_FAULT1IN         (_U_(0x1) << TCC_STATUS_FAULT1IN_Pos)
-#define TCC_STATUS_FAULTA_Pos       12           /**< \brief (TCC_STATUS) Recoverable Fault A State */
-#define TCC_STATUS_FAULTA           (_U_(0x1) << TCC_STATUS_FAULTA_Pos)
-#define TCC_STATUS_FAULTB_Pos       13           /**< \brief (TCC_STATUS) Recoverable Fault B State */
-#define TCC_STATUS_FAULTB           (_U_(0x1) << TCC_STATUS_FAULTB_Pos)
-#define TCC_STATUS_FAULT0_Pos       14           /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
-#define TCC_STATUS_FAULT0           (_U_(0x1) << TCC_STATUS_FAULT0_Pos)
-#define TCC_STATUS_FAULT1_Pos       15           /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
-#define TCC_STATUS_FAULT1           (_U_(0x1) << TCC_STATUS_FAULT1_Pos)
-#define TCC_STATUS_CCBUFV0_Pos      16           /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
-#define TCC_STATUS_CCBUFV0          (_U_(1) << TCC_STATUS_CCBUFV0_Pos)
-#define TCC_STATUS_CCBUFV1_Pos      17           /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
-#define TCC_STATUS_CCBUFV1          (_U_(1) << TCC_STATUS_CCBUFV1_Pos)
-#define TCC_STATUS_CCBUFV2_Pos      18           /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
-#define TCC_STATUS_CCBUFV2          (_U_(1) << TCC_STATUS_CCBUFV2_Pos)
-#define TCC_STATUS_CCBUFV3_Pos      19           /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
-#define TCC_STATUS_CCBUFV3          (_U_(1) << TCC_STATUS_CCBUFV3_Pos)
-#define TCC_STATUS_CCBUFV4_Pos      20           /**< \brief (TCC_STATUS) Compare Channel 4 Buffer Valid */
-#define TCC_STATUS_CCBUFV4          (_U_(1) << TCC_STATUS_CCBUFV4_Pos)
-#define TCC_STATUS_CCBUFV5_Pos      21           /**< \brief (TCC_STATUS) Compare Channel 5 Buffer Valid */
-#define TCC_STATUS_CCBUFV5          (_U_(1) << TCC_STATUS_CCBUFV5_Pos)
-#define TCC_STATUS_CCBUFV_Pos       16           /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
-#define TCC_STATUS_CCBUFV_Msk       (_U_(0x3F) << TCC_STATUS_CCBUFV_Pos)
-#define TCC_STATUS_CCBUFV(value)    (TCC_STATUS_CCBUFV_Msk & ((value) << TCC_STATUS_CCBUFV_Pos))
-#define TCC_STATUS_CMP0_Pos         24           /**< \brief (TCC_STATUS) Compare Channel 0 Value */
-#define TCC_STATUS_CMP0             (_U_(1) << TCC_STATUS_CMP0_Pos)
-#define TCC_STATUS_CMP1_Pos         25           /**< \brief (TCC_STATUS) Compare Channel 1 Value */
-#define TCC_STATUS_CMP1             (_U_(1) << TCC_STATUS_CMP1_Pos)
-#define TCC_STATUS_CMP2_Pos         26           /**< \brief (TCC_STATUS) Compare Channel 2 Value */
-#define TCC_STATUS_CMP2             (_U_(1) << TCC_STATUS_CMP2_Pos)
-#define TCC_STATUS_CMP3_Pos         27           /**< \brief (TCC_STATUS) Compare Channel 3 Value */
-#define TCC_STATUS_CMP3             (_U_(1) << TCC_STATUS_CMP3_Pos)
-#define TCC_STATUS_CMP4_Pos         28           /**< \brief (TCC_STATUS) Compare Channel 4 Value */
-#define TCC_STATUS_CMP4             (_U_(1) << TCC_STATUS_CMP4_Pos)
-#define TCC_STATUS_CMP5_Pos         29           /**< \brief (TCC_STATUS) Compare Channel 5 Value */
-#define TCC_STATUS_CMP5             (_U_(1) << TCC_STATUS_CMP5_Pos)
-#define TCC_STATUS_CMP_Pos          24           /**< \brief (TCC_STATUS) Compare Channel x Value */
-#define TCC_STATUS_CMP_Msk          (_U_(0x3F) << TCC_STATUS_CMP_Pos)
-#define TCC_STATUS_CMP(value)       (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
-#define TCC_STATUS_MASK             _U_(0x3F3FFFBF) /**< \brief (TCC_STATUS) MASK Register */
-
-/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
-    uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
-    uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t COUNT:24;         /*!< bit:  0..23  Counter Value                      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_COUNT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
-#define TCC_COUNT_RESETVALUE        _U_(0x00000000) /**< \brief (TCC_COUNT reset_value) Count */
-
-// DITH4 mode
-#define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
-#define TCC_COUNT_DITH4_COUNT_Msk   (_U_(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos)
-#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
-#define TCC_COUNT_DITH4_MASK        _U_(0x00FFFFF0) /**< \brief (TCC_COUNT_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
-#define TCC_COUNT_DITH5_COUNT_Msk   (_U_(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos)
-#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
-#define TCC_COUNT_DITH5_MASK        _U_(0x00FFFFE0) /**< \brief (TCC_COUNT_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
-#define TCC_COUNT_DITH6_COUNT_Msk   (_U_(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos)
-#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
-#define TCC_COUNT_DITH6_MASK        _U_(0x00FFFFC0) /**< \brief (TCC_COUNT_DITH6) MASK Register */
-
-#define TCC_COUNT_COUNT_Pos         0            /**< \brief (TCC_COUNT) Counter Value */
-#define TCC_COUNT_COUNT_Msk         (_U_(0xFFFFFF) << TCC_COUNT_COUNT_Pos)
-#define TCC_COUNT_COUNT(value)      (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
-#define TCC_COUNT_MASK              _U_(0x00FFFFFF) /**< \brief (TCC_COUNT) MASK Register */
-
-/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PGE0:1;           /*!< bit:      0  Pattern Generator 0 Output Enable  */
-    uint16_t PGE1:1;           /*!< bit:      1  Pattern Generator 1 Output Enable  */
-    uint16_t PGE2:1;           /*!< bit:      2  Pattern Generator 2 Output Enable  */
-    uint16_t PGE3:1;           /*!< bit:      3  Pattern Generator 3 Output Enable  */
-    uint16_t PGE4:1;           /*!< bit:      4  Pattern Generator 4 Output Enable  */
-    uint16_t PGE5:1;           /*!< bit:      5  Pattern Generator 5 Output Enable  */
-    uint16_t PGE6:1;           /*!< bit:      6  Pattern Generator 6 Output Enable  */
-    uint16_t PGE7:1;           /*!< bit:      7  Pattern Generator 7 Output Enable  */
-    uint16_t PGV0:1;           /*!< bit:      8  Pattern Generator 0 Output Value   */
-    uint16_t PGV1:1;           /*!< bit:      9  Pattern Generator 1 Output Value   */
-    uint16_t PGV2:1;           /*!< bit:     10  Pattern Generator 2 Output Value   */
-    uint16_t PGV3:1;           /*!< bit:     11  Pattern Generator 3 Output Value   */
-    uint16_t PGV4:1;           /*!< bit:     12  Pattern Generator 4 Output Value   */
-    uint16_t PGV5:1;           /*!< bit:     13  Pattern Generator 5 Output Value   */
-    uint16_t PGV6:1;           /*!< bit:     14  Pattern Generator 6 Output Value   */
-    uint16_t PGV7:1;           /*!< bit:     15  Pattern Generator 7 Output Value   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PGE:8;            /*!< bit:  0.. 7  Pattern Generator x Output Enable  */
-    uint16_t PGV:8;            /*!< bit:  8..15  Pattern Generator x Output Value   */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TCC_PATT_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATT_OFFSET             0x38         /**< \brief (TCC_PATT offset) Pattern */
-#define TCC_PATT_RESETVALUE         _U_(0x0000)  /**< \brief (TCC_PATT reset_value) Pattern */
-
-#define TCC_PATT_PGE0_Pos           0            /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
-#define TCC_PATT_PGE0               (_U_(1) << TCC_PATT_PGE0_Pos)
-#define TCC_PATT_PGE1_Pos           1            /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
-#define TCC_PATT_PGE1               (_U_(1) << TCC_PATT_PGE1_Pos)
-#define TCC_PATT_PGE2_Pos           2            /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
-#define TCC_PATT_PGE2               (_U_(1) << TCC_PATT_PGE2_Pos)
-#define TCC_PATT_PGE3_Pos           3            /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
-#define TCC_PATT_PGE3               (_U_(1) << TCC_PATT_PGE3_Pos)
-#define TCC_PATT_PGE4_Pos           4            /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
-#define TCC_PATT_PGE4               (_U_(1) << TCC_PATT_PGE4_Pos)
-#define TCC_PATT_PGE5_Pos           5            /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
-#define TCC_PATT_PGE5               (_U_(1) << TCC_PATT_PGE5_Pos)
-#define TCC_PATT_PGE6_Pos           6            /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
-#define TCC_PATT_PGE6               (_U_(1) << TCC_PATT_PGE6_Pos)
-#define TCC_PATT_PGE7_Pos           7            /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
-#define TCC_PATT_PGE7               (_U_(1) << TCC_PATT_PGE7_Pos)
-#define TCC_PATT_PGE_Pos            0            /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
-#define TCC_PATT_PGE_Msk            (_U_(0xFF) << TCC_PATT_PGE_Pos)
-#define TCC_PATT_PGE(value)         (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
-#define TCC_PATT_PGV0_Pos           8            /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
-#define TCC_PATT_PGV0               (_U_(1) << TCC_PATT_PGV0_Pos)
-#define TCC_PATT_PGV1_Pos           9            /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
-#define TCC_PATT_PGV1               (_U_(1) << TCC_PATT_PGV1_Pos)
-#define TCC_PATT_PGV2_Pos           10           /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
-#define TCC_PATT_PGV2               (_U_(1) << TCC_PATT_PGV2_Pos)
-#define TCC_PATT_PGV3_Pos           11           /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
-#define TCC_PATT_PGV3               (_U_(1) << TCC_PATT_PGV3_Pos)
-#define TCC_PATT_PGV4_Pos           12           /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
-#define TCC_PATT_PGV4               (_U_(1) << TCC_PATT_PGV4_Pos)
-#define TCC_PATT_PGV5_Pos           13           /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
-#define TCC_PATT_PGV5               (_U_(1) << TCC_PATT_PGV5_Pos)
-#define TCC_PATT_PGV6_Pos           14           /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
-#define TCC_PATT_PGV6               (_U_(1) << TCC_PATT_PGV6_Pos)
-#define TCC_PATT_PGV7_Pos           15           /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
-#define TCC_PATT_PGV7               (_U_(1) << TCC_PATT_PGV7_Pos)
-#define TCC_PATT_PGV_Pos            8            /**< \brief (TCC_PATT) Pattern Generator x Output Value */
-#define TCC_PATT_PGV_Msk            (_U_(0xFF) << TCC_PATT_PGV_Pos)
-#define TCC_PATT_PGV(value)         (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
-#define TCC_PATT_MASK               _U_(0xFFFF)  /**< \brief (TCC_PATT) MASK Register */
-
-/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t WAVEGEN:3;        /*!< bit:  0.. 2  Waveform Generation                */
-    uint32_t :1;               /*!< bit:      3  Reserved                           */
-    uint32_t RAMP:2;           /*!< bit:  4.. 5  Ramp Mode                          */
-    uint32_t :1;               /*!< bit:      6  Reserved                           */
-    uint32_t CIPEREN:1;        /*!< bit:      7  Circular period Enable             */
-    uint32_t CICCEN0:1;        /*!< bit:      8  Circular Channel 0 Enable          */
-    uint32_t CICCEN1:1;        /*!< bit:      9  Circular Channel 1 Enable          */
-    uint32_t CICCEN2:1;        /*!< bit:     10  Circular Channel 2 Enable          */
-    uint32_t CICCEN3:1;        /*!< bit:     11  Circular Channel 3 Enable          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POL0:1;           /*!< bit:     16  Channel 0 Polarity                 */
-    uint32_t POL1:1;           /*!< bit:     17  Channel 1 Polarity                 */
-    uint32_t POL2:1;           /*!< bit:     18  Channel 2 Polarity                 */
-    uint32_t POL3:1;           /*!< bit:     19  Channel 3 Polarity                 */
-    uint32_t POL4:1;           /*!< bit:     20  Channel 4 Polarity                 */
-    uint32_t POL5:1;           /*!< bit:     21  Channel 5 Polarity                 */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t SWAP0:1;          /*!< bit:     24  Swap DTI Output Pair 0             */
-    uint32_t SWAP1:1;          /*!< bit:     25  Swap DTI Output Pair 1             */
-    uint32_t SWAP2:1;          /*!< bit:     26  Swap DTI Output Pair 2             */
-    uint32_t SWAP3:1;          /*!< bit:     27  Swap DTI Output Pair 3             */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
-    uint32_t CICCEN:4;         /*!< bit:  8..11  Circular Channel x Enable          */
-    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
-    uint32_t POL:6;            /*!< bit: 16..21  Channel x Polarity                 */
-    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
-    uint32_t SWAP:4;           /*!< bit: 24..27  Swap DTI Output Pair x             */
-    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_WAVE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_WAVE_OFFSET             0x3C         /**< \brief (TCC_WAVE offset) Waveform Control */
-#define TCC_WAVE_RESETVALUE         _U_(0x00000000) /**< \brief (TCC_WAVE reset_value) Waveform Control */
-
-#define TCC_WAVE_WAVEGEN_Pos        0            /**< \brief (TCC_WAVE) Waveform Generation */
-#define TCC_WAVE_WAVEGEN_Msk        (_U_(0x7) << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN(value)     (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
-#define   TCC_WAVE_WAVEGEN_NFRQ_Val       _U_(0x0)   /**< \brief (TCC_WAVE) Normal frequency */
-#define   TCC_WAVE_WAVEGEN_MFRQ_Val       _U_(0x1)   /**< \brief (TCC_WAVE) Match frequency */
-#define   TCC_WAVE_WAVEGEN_NPWM_Val       _U_(0x2)   /**< \brief (TCC_WAVE) Normal PWM */
-#define   TCC_WAVE_WAVEGEN_DSCRITICAL_Val _U_(0x4)   /**< \brief (TCC_WAVE) Dual-slope critical */
-#define   TCC_WAVE_WAVEGEN_DSBOTTOM_Val   _U_(0x5)   /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
-#define   TCC_WAVE_WAVEGEN_DSBOTH_Val     _U_(0x6)   /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
-#define   TCC_WAVE_WAVEGEN_DSTOP_Val      _U_(0x7)   /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
-#define TCC_WAVE_WAVEGEN_NFRQ       (TCC_WAVE_WAVEGEN_NFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_MFRQ       (TCC_WAVE_WAVEGEN_MFRQ_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_NPWM       (TCC_WAVE_WAVEGEN_NPWM_Val     << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTTOM   (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSBOTH     (TCC_WAVE_WAVEGEN_DSBOTH_Val   << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_WAVEGEN_DSTOP      (TCC_WAVE_WAVEGEN_DSTOP_Val    << TCC_WAVE_WAVEGEN_Pos)
-#define TCC_WAVE_RAMP_Pos           4            /**< \brief (TCC_WAVE) Ramp Mode */
-#define TCC_WAVE_RAMP_Msk           (_U_(0x3) << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP(value)        (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
-#define   TCC_WAVE_RAMP_RAMP1_Val         _U_(0x0)   /**< \brief (TCC_WAVE) RAMP1 operation */
-#define   TCC_WAVE_RAMP_RAMP2A_Val        _U_(0x1)   /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
-#define   TCC_WAVE_RAMP_RAMP2_Val         _U_(0x2)   /**< \brief (TCC_WAVE) RAMP2 operation */
-#define   TCC_WAVE_RAMP_RAMP2C_Val        _U_(0x3)   /**< \brief (TCC_WAVE) Critical RAMP2 operation */
-#define TCC_WAVE_RAMP_RAMP1         (TCC_WAVE_RAMP_RAMP1_Val       << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2A        (TCC_WAVE_RAMP_RAMP2A_Val      << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2         (TCC_WAVE_RAMP_RAMP2_Val       << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_RAMP_RAMP2C        (TCC_WAVE_RAMP_RAMP2C_Val      << TCC_WAVE_RAMP_Pos)
-#define TCC_WAVE_CIPEREN_Pos        7            /**< \brief (TCC_WAVE) Circular period Enable */
-#define TCC_WAVE_CIPEREN            (_U_(0x1) << TCC_WAVE_CIPEREN_Pos)
-#define TCC_WAVE_CICCEN0_Pos        8            /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
-#define TCC_WAVE_CICCEN0            (_U_(1) << TCC_WAVE_CICCEN0_Pos)
-#define TCC_WAVE_CICCEN1_Pos        9            /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
-#define TCC_WAVE_CICCEN1            (_U_(1) << TCC_WAVE_CICCEN1_Pos)
-#define TCC_WAVE_CICCEN2_Pos        10           /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
-#define TCC_WAVE_CICCEN2            (_U_(1) << TCC_WAVE_CICCEN2_Pos)
-#define TCC_WAVE_CICCEN3_Pos        11           /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
-#define TCC_WAVE_CICCEN3            (_U_(1) << TCC_WAVE_CICCEN3_Pos)
-#define TCC_WAVE_CICCEN_Pos         8            /**< \brief (TCC_WAVE) Circular Channel x Enable */
-#define TCC_WAVE_CICCEN_Msk         (_U_(0xF) << TCC_WAVE_CICCEN_Pos)
-#define TCC_WAVE_CICCEN(value)      (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
-#define TCC_WAVE_POL0_Pos           16           /**< \brief (TCC_WAVE) Channel 0 Polarity */
-#define TCC_WAVE_POL0               (_U_(1) << TCC_WAVE_POL0_Pos)
-#define TCC_WAVE_POL1_Pos           17           /**< \brief (TCC_WAVE) Channel 1 Polarity */
-#define TCC_WAVE_POL1               (_U_(1) << TCC_WAVE_POL1_Pos)
-#define TCC_WAVE_POL2_Pos           18           /**< \brief (TCC_WAVE) Channel 2 Polarity */
-#define TCC_WAVE_POL2               (_U_(1) << TCC_WAVE_POL2_Pos)
-#define TCC_WAVE_POL3_Pos           19           /**< \brief (TCC_WAVE) Channel 3 Polarity */
-#define TCC_WAVE_POL3               (_U_(1) << TCC_WAVE_POL3_Pos)
-#define TCC_WAVE_POL4_Pos           20           /**< \brief (TCC_WAVE) Channel 4 Polarity */
-#define TCC_WAVE_POL4               (_U_(1) << TCC_WAVE_POL4_Pos)
-#define TCC_WAVE_POL5_Pos           21           /**< \brief (TCC_WAVE) Channel 5 Polarity */
-#define TCC_WAVE_POL5               (_U_(1) << TCC_WAVE_POL5_Pos)
-#define TCC_WAVE_POL_Pos            16           /**< \brief (TCC_WAVE) Channel x Polarity */
-#define TCC_WAVE_POL_Msk            (_U_(0x3F) << TCC_WAVE_POL_Pos)
-#define TCC_WAVE_POL(value)         (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
-#define TCC_WAVE_SWAP0_Pos          24           /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
-#define TCC_WAVE_SWAP0              (_U_(1) << TCC_WAVE_SWAP0_Pos)
-#define TCC_WAVE_SWAP1_Pos          25           /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
-#define TCC_WAVE_SWAP1              (_U_(1) << TCC_WAVE_SWAP1_Pos)
-#define TCC_WAVE_SWAP2_Pos          26           /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
-#define TCC_WAVE_SWAP2              (_U_(1) << TCC_WAVE_SWAP2_Pos)
-#define TCC_WAVE_SWAP3_Pos          27           /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
-#define TCC_WAVE_SWAP3              (_U_(1) << TCC_WAVE_SWAP3_Pos)
-#define TCC_WAVE_SWAP_Pos           24           /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
-#define TCC_WAVE_SWAP_Msk           (_U_(0xF) << TCC_WAVE_SWAP_Pos)
-#define TCC_WAVE_SWAP(value)        (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
-#define TCC_WAVE_MASK               _U_(0x0F3F0FB7) /**< \brief (TCC_WAVE) MASK Register */
-
-/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHER:4;         /*!< bit:  0.. 3  Dithering Cycle Number             */
-    uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHER:5;         /*!< bit:  0.. 4  Dithering Cycle Number             */
-    uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHER:6;         /*!< bit:  0.. 5  Dithering Cycle Number             */
-    uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t PER:24;           /*!< bit:  0..23  Period Value                       */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_PER_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
-#define TCC_PER_RESETVALUE          _U_(0xFFFFFFFF) /**< \brief (TCC_PER reset_value) Period */
-
-// DITH4 mode
-#define TCC_PER_DITH4_DITHER_Pos    0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
-#define TCC_PER_DITH4_DITHER_Msk    (_U_(0xF) << TCC_PER_DITH4_DITHER_Pos)
-#define TCC_PER_DITH4_DITHER(value) (TCC_PER_DITH4_DITHER_Msk & ((value) << TCC_PER_DITH4_DITHER_Pos))
-#define TCC_PER_DITH4_PER_Pos       4            /**< \brief (TCC_PER_DITH4) Period Value */
-#define TCC_PER_DITH4_PER_Msk       (_U_(0xFFFFF) << TCC_PER_DITH4_PER_Pos)
-#define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
-#define TCC_PER_DITH4_MASK          _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PER_DITH5_DITHER_Pos    0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
-#define TCC_PER_DITH5_DITHER_Msk    (_U_(0x1F) << TCC_PER_DITH5_DITHER_Pos)
-#define TCC_PER_DITH5_DITHER(value) (TCC_PER_DITH5_DITHER_Msk & ((value) << TCC_PER_DITH5_DITHER_Pos))
-#define TCC_PER_DITH5_PER_Pos       5            /**< \brief (TCC_PER_DITH5) Period Value */
-#define TCC_PER_DITH5_PER_Msk       (_U_(0x7FFFF) << TCC_PER_DITH5_PER_Pos)
-#define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
-#define TCC_PER_DITH5_MASK          _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PER_DITH6_DITHER_Pos    0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
-#define TCC_PER_DITH6_DITHER_Msk    (_U_(0x3F) << TCC_PER_DITH6_DITHER_Pos)
-#define TCC_PER_DITH6_DITHER(value) (TCC_PER_DITH6_DITHER_Msk & ((value) << TCC_PER_DITH6_DITHER_Pos))
-#define TCC_PER_DITH6_PER_Pos       6            /**< \brief (TCC_PER_DITH6) Period Value */
-#define TCC_PER_DITH6_PER_Msk       (_U_(0x3FFFF) << TCC_PER_DITH6_PER_Pos)
-#define TCC_PER_DITH6_PER(value)    (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
-#define TCC_PER_DITH6_MASK          _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH6) MASK Register */
-
-#define TCC_PER_PER_Pos             0            /**< \brief (TCC_PER) Period Value */
-#define TCC_PER_PER_Msk             (_U_(0xFFFFFF) << TCC_PER_PER_Pos)
-#define TCC_PER_PER(value)          (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
-#define TCC_PER_MASK                _U_(0x00FFFFFF) /**< \brief (TCC_PER) MASK Register */
-
-/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHER:4;         /*!< bit:  0.. 3  Dithering Cycle Number             */
-    uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHER:5;         /*!< bit:  0.. 4  Dithering Cycle Number             */
-    uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHER:6;         /*!< bit:  0.. 5  Dithering Cycle Number             */
-    uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t CC:24;            /*!< bit:  0..23  Channel Compare/Capture Value      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
-#define TCC_CC_RESETVALUE           _U_(0x00000000) /**< \brief (TCC_CC reset_value) Compare and Capture */
-
-// DITH4 mode
-#define TCC_CC_DITH4_DITHER_Pos     0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
-#define TCC_CC_DITH4_DITHER_Msk     (_U_(0xF) << TCC_CC_DITH4_DITHER_Pos)
-#define TCC_CC_DITH4_DITHER(value)  (TCC_CC_DITH4_DITHER_Msk & ((value) << TCC_CC_DITH4_DITHER_Pos))
-#define TCC_CC_DITH4_CC_Pos         4            /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
-#define TCC_CC_DITH4_CC_Msk         (_U_(0xFFFFF) << TCC_CC_DITH4_CC_Pos)
-#define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
-#define TCC_CC_DITH4_MASK           _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CC_DITH5_DITHER_Pos     0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
-#define TCC_CC_DITH5_DITHER_Msk     (_U_(0x1F) << TCC_CC_DITH5_DITHER_Pos)
-#define TCC_CC_DITH5_DITHER(value)  (TCC_CC_DITH5_DITHER_Msk & ((value) << TCC_CC_DITH5_DITHER_Pos))
-#define TCC_CC_DITH5_CC_Pos         5            /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
-#define TCC_CC_DITH5_CC_Msk         (_U_(0x7FFFF) << TCC_CC_DITH5_CC_Pos)
-#define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
-#define TCC_CC_DITH5_MASK           _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CC_DITH6_DITHER_Pos     0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
-#define TCC_CC_DITH6_DITHER_Msk     (_U_(0x3F) << TCC_CC_DITH6_DITHER_Pos)
-#define TCC_CC_DITH6_DITHER(value)  (TCC_CC_DITH6_DITHER_Msk & ((value) << TCC_CC_DITH6_DITHER_Pos))
-#define TCC_CC_DITH6_CC_Pos         6            /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
-#define TCC_CC_DITH6_CC_Msk         (_U_(0x3FFFF) << TCC_CC_DITH6_CC_Pos)
-#define TCC_CC_DITH6_CC(value)      (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
-#define TCC_CC_DITH6_MASK           _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH6) MASK Register */
-
-#define TCC_CC_CC_Pos               0            /**< \brief (TCC_CC) Channel Compare/Capture Value */
-#define TCC_CC_CC_Msk               (_U_(0xFFFFFF) << TCC_CC_CC_Pos)
-#define TCC_CC_CC(value)            (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
-#define TCC_CC_MASK                 _U_(0x00FFFFFF) /**< \brief (TCC_CC) MASK Register */
-
-/* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PGEB0:1;          /*!< bit:      0  Pattern Generator 0 Output Enable Buffer */
-    uint16_t PGEB1:1;          /*!< bit:      1  Pattern Generator 1 Output Enable Buffer */
-    uint16_t PGEB2:1;          /*!< bit:      2  Pattern Generator 2 Output Enable Buffer */
-    uint16_t PGEB3:1;          /*!< bit:      3  Pattern Generator 3 Output Enable Buffer */
-    uint16_t PGEB4:1;          /*!< bit:      4  Pattern Generator 4 Output Enable Buffer */
-    uint16_t PGEB5:1;          /*!< bit:      5  Pattern Generator 5 Output Enable Buffer */
-    uint16_t PGEB6:1;          /*!< bit:      6  Pattern Generator 6 Output Enable Buffer */
-    uint16_t PGEB7:1;          /*!< bit:      7  Pattern Generator 7 Output Enable Buffer */
-    uint16_t PGVB0:1;          /*!< bit:      8  Pattern Generator 0 Output Enable  */
-    uint16_t PGVB1:1;          /*!< bit:      9  Pattern Generator 1 Output Enable  */
-    uint16_t PGVB2:1;          /*!< bit:     10  Pattern Generator 2 Output Enable  */
-    uint16_t PGVB3:1;          /*!< bit:     11  Pattern Generator 3 Output Enable  */
-    uint16_t PGVB4:1;          /*!< bit:     12  Pattern Generator 4 Output Enable  */
-    uint16_t PGVB5:1;          /*!< bit:     13  Pattern Generator 5 Output Enable  */
-    uint16_t PGVB6:1;          /*!< bit:     14  Pattern Generator 6 Output Enable  */
-    uint16_t PGVB7:1;          /*!< bit:     15  Pattern Generator 7 Output Enable  */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t PGEB:8;           /*!< bit:  0.. 7  Pattern Generator x Output Enable Buffer */
-    uint16_t PGVB:8;           /*!< bit:  8..15  Pattern Generator x Output Enable  */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} TCC_PATTBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PATTBUF_OFFSET          0x64         /**< \brief (TCC_PATTBUF offset) Pattern Buffer */
-#define TCC_PATTBUF_RESETVALUE      _U_(0x0000)  /**< \brief (TCC_PATTBUF reset_value) Pattern Buffer */
-
-#define TCC_PATTBUF_PGEB0_Pos       0            /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB0           (_U_(1) << TCC_PATTBUF_PGEB0_Pos)
-#define TCC_PATTBUF_PGEB1_Pos       1            /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB1           (_U_(1) << TCC_PATTBUF_PGEB1_Pos)
-#define TCC_PATTBUF_PGEB2_Pos       2            /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB2           (_U_(1) << TCC_PATTBUF_PGEB2_Pos)
-#define TCC_PATTBUF_PGEB3_Pos       3            /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB3           (_U_(1) << TCC_PATTBUF_PGEB3_Pos)
-#define TCC_PATTBUF_PGEB4_Pos       4            /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB4           (_U_(1) << TCC_PATTBUF_PGEB4_Pos)
-#define TCC_PATTBUF_PGEB5_Pos       5            /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB5           (_U_(1) << TCC_PATTBUF_PGEB5_Pos)
-#define TCC_PATTBUF_PGEB6_Pos       6            /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB6           (_U_(1) << TCC_PATTBUF_PGEB6_Pos)
-#define TCC_PATTBUF_PGEB7_Pos       7            /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer */
-#define TCC_PATTBUF_PGEB7           (_U_(1) << TCC_PATTBUF_PGEB7_Pos)
-#define TCC_PATTBUF_PGEB_Pos        0            /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable Buffer */
-#define TCC_PATTBUF_PGEB_Msk        (_U_(0xFF) << TCC_PATTBUF_PGEB_Pos)
-#define TCC_PATTBUF_PGEB(value)     (TCC_PATTBUF_PGEB_Msk & ((value) << TCC_PATTBUF_PGEB_Pos))
-#define TCC_PATTBUF_PGVB0_Pos       8            /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable */
-#define TCC_PATTBUF_PGVB0           (_U_(1) << TCC_PATTBUF_PGVB0_Pos)
-#define TCC_PATTBUF_PGVB1_Pos       9            /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable */
-#define TCC_PATTBUF_PGVB1           (_U_(1) << TCC_PATTBUF_PGVB1_Pos)
-#define TCC_PATTBUF_PGVB2_Pos       10           /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable */
-#define TCC_PATTBUF_PGVB2           (_U_(1) << TCC_PATTBUF_PGVB2_Pos)
-#define TCC_PATTBUF_PGVB3_Pos       11           /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable */
-#define TCC_PATTBUF_PGVB3           (_U_(1) << TCC_PATTBUF_PGVB3_Pos)
-#define TCC_PATTBUF_PGVB4_Pos       12           /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable */
-#define TCC_PATTBUF_PGVB4           (_U_(1) << TCC_PATTBUF_PGVB4_Pos)
-#define TCC_PATTBUF_PGVB5_Pos       13           /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable */
-#define TCC_PATTBUF_PGVB5           (_U_(1) << TCC_PATTBUF_PGVB5_Pos)
-#define TCC_PATTBUF_PGVB6_Pos       14           /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable */
-#define TCC_PATTBUF_PGVB6           (_U_(1) << TCC_PATTBUF_PGVB6_Pos)
-#define TCC_PATTBUF_PGVB7_Pos       15           /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable */
-#define TCC_PATTBUF_PGVB7           (_U_(1) << TCC_PATTBUF_PGVB7_Pos)
-#define TCC_PATTBUF_PGVB_Pos        8            /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable */
-#define TCC_PATTBUF_PGVB_Msk        (_U_(0xFF) << TCC_PATTBUF_PGVB_Pos)
-#define TCC_PATTBUF_PGVB(value)     (TCC_PATTBUF_PGVB_Msk & ((value) << TCC_PATTBUF_PGVB_Pos))
-#define TCC_PATTBUF_MASK            _U_(0xFFFF)  /**< \brief (TCC_PATTBUF) MASK Register */
-
-/* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t DITHERBUF:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
-    uint32_t PERBUF:20;        /*!< bit:  4..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERBUF:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
-    uint32_t PERBUF:19;        /*!< bit:  5..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERBUF:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
-    uint32_t PERBUF:18;        /*!< bit:  6..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t PERBUF:24;        /*!< bit:  0..23  Period Buffer Value                */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_PERBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_PERBUF_OFFSET           0x6C         /**< \brief (TCC_PERBUF offset) Period Buffer */
-#define TCC_PERBUF_RESETVALUE       _U_(0xFFFFFFFF) /**< \brief (TCC_PERBUF reset_value) Period Buffer */
-
-// DITH4 mode
-#define TCC_PERBUF_DITH4_DITHERBUF_Pos 0            /**< \brief (TCC_PERBUF_DITH4) Dithering Buffer Cycle Number */
-#define TCC_PERBUF_DITH4_DITHERBUF_Msk (_U_(0xF) << TCC_PERBUF_DITH4_DITHERBUF_Pos)
-#define TCC_PERBUF_DITH4_DITHERBUF(value) (TCC_PERBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH4_DITHERBUF_Pos))
-#define TCC_PERBUF_DITH4_PERBUF_Pos 4            /**< \brief (TCC_PERBUF_DITH4) Period Buffer Value */
-#define TCC_PERBUF_DITH4_PERBUF_Msk (_U_(0xFFFFF) << TCC_PERBUF_DITH4_PERBUF_Pos)
-#define TCC_PERBUF_DITH4_PERBUF(value) (TCC_PERBUF_DITH4_PERBUF_Msk & ((value) << TCC_PERBUF_DITH4_PERBUF_Pos))
-#define TCC_PERBUF_DITH4_MASK       _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_PERBUF_DITH5_DITHERBUF_Pos 0            /**< \brief (TCC_PERBUF_DITH5) Dithering Buffer Cycle Number */
-#define TCC_PERBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_PERBUF_DITH5_DITHERBUF_Pos)
-#define TCC_PERBUF_DITH5_DITHERBUF(value) (TCC_PERBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH5_DITHERBUF_Pos))
-#define TCC_PERBUF_DITH5_PERBUF_Pos 5            /**< \brief (TCC_PERBUF_DITH5) Period Buffer Value */
-#define TCC_PERBUF_DITH5_PERBUF_Msk (_U_(0x7FFFF) << TCC_PERBUF_DITH5_PERBUF_Pos)
-#define TCC_PERBUF_DITH5_PERBUF(value) (TCC_PERBUF_DITH5_PERBUF_Msk & ((value) << TCC_PERBUF_DITH5_PERBUF_Pos))
-#define TCC_PERBUF_DITH5_MASK       _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_PERBUF_DITH6_DITHERBUF_Pos 0            /**< \brief (TCC_PERBUF_DITH6) Dithering Buffer Cycle Number */
-#define TCC_PERBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_PERBUF_DITH6_DITHERBUF_Pos)
-#define TCC_PERBUF_DITH6_DITHERBUF(value) (TCC_PERBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH6_DITHERBUF_Pos))
-#define TCC_PERBUF_DITH6_PERBUF_Pos 6            /**< \brief (TCC_PERBUF_DITH6) Period Buffer Value */
-#define TCC_PERBUF_DITH6_PERBUF_Msk (_U_(0x3FFFF) << TCC_PERBUF_DITH6_PERBUF_Pos)
-#define TCC_PERBUF_DITH6_PERBUF(value) (TCC_PERBUF_DITH6_PERBUF_Msk & ((value) << TCC_PERBUF_DITH6_PERBUF_Pos))
-#define TCC_PERBUF_DITH6_MASK       _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH6) MASK Register */
-
-#define TCC_PERBUF_PERBUF_Pos       0            /**< \brief (TCC_PERBUF) Period Buffer Value */
-#define TCC_PERBUF_PERBUF_Msk       (_U_(0xFFFFFF) << TCC_PERBUF_PERBUF_Pos)
-#define TCC_PERBUF_PERBUF(value)    (TCC_PERBUF_PERBUF_Msk & ((value) << TCC_PERBUF_PERBUF_Pos))
-#define TCC_PERBUF_MASK             _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF) MASK Register */
-
-/* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct { // DITH4 mode
-    uint32_t CCBUF:4;          /*!< bit:  0.. 3  Channel Compare/Capture Buffer Value */
-    uint32_t DITHERBUF:20;     /*!< bit:  4..23  Dithering Buffer Cycle Number      */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
-    uint32_t DITHERBUF:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
-    uint32_t CCBUF:19;         /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
-    uint32_t DITHERBUF:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
-    uint32_t CCBUF:18;         /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } DITH6;                     /*!< Structure used for DITH6                        */
-  struct {
-    uint32_t CCBUF:24;         /*!< bit:  0..23  Channel Compare/Capture Buffer Value */
-    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TCC_CCBUF_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TCC_CCBUF_OFFSET            0x70         /**< \brief (TCC_CCBUF offset) Compare and Capture Buffer */
-#define TCC_CCBUF_RESETVALUE        _U_(0x00000000) /**< \brief (TCC_CCBUF reset_value) Compare and Capture Buffer */
-
-// DITH4 mode
-#define TCC_CCBUF_DITH4_CCBUF_Pos   0            /**< \brief (TCC_CCBUF_DITH4) Channel Compare/Capture Buffer Value */
-#define TCC_CCBUF_DITH4_CCBUF_Msk   (_U_(0xF) << TCC_CCBUF_DITH4_CCBUF_Pos)
-#define TCC_CCBUF_DITH4_CCBUF(value) (TCC_CCBUF_DITH4_CCBUF_Msk & ((value) << TCC_CCBUF_DITH4_CCBUF_Pos))
-#define TCC_CCBUF_DITH4_DITHERBUF_Pos 4            /**< \brief (TCC_CCBUF_DITH4) Dithering Buffer Cycle Number */
-#define TCC_CCBUF_DITH4_DITHERBUF_Msk (_U_(0xFFFFF) << TCC_CCBUF_DITH4_DITHERBUF_Pos)
-#define TCC_CCBUF_DITH4_DITHERBUF(value) (TCC_CCBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH4_DITHERBUF_Pos))
-#define TCC_CCBUF_DITH4_MASK        _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH4) MASK Register */
-
-// DITH5 mode
-#define TCC_CCBUF_DITH5_DITHERBUF_Pos 0            /**< \brief (TCC_CCBUF_DITH5) Dithering Buffer Cycle Number */
-#define TCC_CCBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_CCBUF_DITH5_DITHERBUF_Pos)
-#define TCC_CCBUF_DITH5_DITHERBUF(value) (TCC_CCBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH5_DITHERBUF_Pos))
-#define TCC_CCBUF_DITH5_CCBUF_Pos   5            /**< \brief (TCC_CCBUF_DITH5) Channel Compare/Capture Buffer Value */
-#define TCC_CCBUF_DITH5_CCBUF_Msk   (_U_(0x7FFFF) << TCC_CCBUF_DITH5_CCBUF_Pos)
-#define TCC_CCBUF_DITH5_CCBUF(value) (TCC_CCBUF_DITH5_CCBUF_Msk & ((value) << TCC_CCBUF_DITH5_CCBUF_Pos))
-#define TCC_CCBUF_DITH5_MASK        _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH5) MASK Register */
-
-// DITH6 mode
-#define TCC_CCBUF_DITH6_DITHERBUF_Pos 0            /**< \brief (TCC_CCBUF_DITH6) Dithering Buffer Cycle Number */
-#define TCC_CCBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_CCBUF_DITH6_DITHERBUF_Pos)
-#define TCC_CCBUF_DITH6_DITHERBUF(value) (TCC_CCBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH6_DITHERBUF_Pos))
-#define TCC_CCBUF_DITH6_CCBUF_Pos   6            /**< \brief (TCC_CCBUF_DITH6) Channel Compare/Capture Buffer Value */
-#define TCC_CCBUF_DITH6_CCBUF_Msk   (_U_(0x3FFFF) << TCC_CCBUF_DITH6_CCBUF_Pos)
-#define TCC_CCBUF_DITH6_CCBUF(value) (TCC_CCBUF_DITH6_CCBUF_Msk & ((value) << TCC_CCBUF_DITH6_CCBUF_Pos))
-#define TCC_CCBUF_DITH6_MASK        _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH6) MASK Register */
-
-#define TCC_CCBUF_CCBUF_Pos         0            /**< \brief (TCC_CCBUF) Channel Compare/Capture Buffer Value */
-#define TCC_CCBUF_CCBUF_Msk         (_U_(0xFFFFFF) << TCC_CCBUF_CCBUF_Pos)
-#define TCC_CCBUF_CCBUF(value)      (TCC_CCBUF_CCBUF_Msk & ((value) << TCC_CCBUF_CCBUF_Pos))
-#define TCC_CCBUF_MASK              _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF) MASK Register */
-
-/** \brief TCC hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO TCC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
-  __IO TCC_CTRLBCLR_Type         CTRLBCLR;    /**< \brief Offset: 0x04 (R/W  8) Control B Clear */
-  __IO TCC_CTRLBSET_Type         CTRLBSET;    /**< \brief Offset: 0x05 (R/W  8) Control B Set */
-       RoReg8                    Reserved1[0x2];
-  __I  TCC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
-  __IO TCC_FCTRLA_Type           FCTRLA;      /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
-  __IO TCC_FCTRLB_Type           FCTRLB;      /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
-  __IO TCC_WEXCTRL_Type          WEXCTRL;     /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
-  __IO TCC_DRVCTRL_Type          DRVCTRL;     /**< \brief Offset: 0x18 (R/W 32) Driver Control */
-       RoReg8                    Reserved2[0x2];
-  __IO TCC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1E (R/W  8) Debug Control */
-       RoReg8                    Reserved3[0x1];
-  __IO TCC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x20 (R/W 32) Event Control */
-  __IO TCC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
-  __IO TCC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
-  __IO TCC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
-  __IO TCC_STATUS_Type           STATUS;      /**< \brief Offset: 0x30 (R/W 32) Status */
-  __IO TCC_COUNT_Type            COUNT;       /**< \brief Offset: 0x34 (R/W 32) Count */
-  __IO TCC_PATT_Type             PATT;        /**< \brief Offset: 0x38 (R/W 16) Pattern */
-       RoReg8                    Reserved4[0x2];
-  __IO TCC_WAVE_Type             WAVE;        /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
-  __IO TCC_PER_Type              PER;         /**< \brief Offset: 0x40 (R/W 32) Period */
-  __IO TCC_CC_Type               CC[6];       /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
-       RoReg8                    Reserved5[0x8];
-  __IO TCC_PATTBUF_Type          PATTBUF;     /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
-       RoReg8                    Reserved6[0x6];
-  __IO TCC_PERBUF_Type           PERBUF;      /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
-  __IO TCC_CCBUF_Type            CCBUF[6];    /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
-} Tcc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_TCC_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/trng.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/trng.h
deleted file mode 100644
index f81d228383..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/trng.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for TRNG
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TRNG_COMPONENT_
-#define _SAMD51_TRNG_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR TRNG */
-/* ========================================================================== */
-/** \addtogroup SAMD51_TRNG True Random Generator */
-/*@{*/
-
-#define TRNG_U2242
-#define REV_TRNG                    0x110
-
-/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TRNG_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_CTRLA_OFFSET           0x00         /**< \brief (TRNG_CTRLA offset) Control A */
-#define TRNG_CTRLA_RESETVALUE       _U_(0x00)    /**< \brief (TRNG_CTRLA reset_value) Control A */
-
-#define TRNG_CTRLA_ENABLE_Pos       1            /**< \brief (TRNG_CTRLA) Enable */
-#define TRNG_CTRLA_ENABLE           (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos)
-#define TRNG_CTRLA_RUNSTDBY_Pos     6            /**< \brief (TRNG_CTRLA) Run in Standby */
-#define TRNG_CTRLA_RUNSTDBY         (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos)
-#define TRNG_CTRLA_MASK             _U_(0x42)    /**< \brief (TRNG_CTRLA) MASK Register */
-
-/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W  8) Event Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DATARDYEO:1;      /*!< bit:      0  Data Ready Event Output            */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TRNG_EVCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_EVCTRL_OFFSET          0x04         /**< \brief (TRNG_EVCTRL offset) Event Control */
-#define TRNG_EVCTRL_RESETVALUE      _U_(0x00)    /**< \brief (TRNG_EVCTRL reset_value) Event Control */
-
-#define TRNG_EVCTRL_DATARDYEO_Pos   0            /**< \brief (TRNG_EVCTRL) Data Ready Event Output */
-#define TRNG_EVCTRL_DATARDYEO       (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos)
-#define TRNG_EVCTRL_MASK            _U_(0x01)    /**< \brief (TRNG_EVCTRL) MASK Register */
-
-/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DATARDY:1;        /*!< bit:      0  Data Ready Interrupt Enable        */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TRNG_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_INTENCLR_OFFSET        0x08         /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */
-#define TRNG_INTENCLR_RESETVALUE    _U_(0x00)    /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define TRNG_INTENCLR_DATARDY_Pos   0            /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */
-#define TRNG_INTENCLR_DATARDY       (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos)
-#define TRNG_INTENCLR_MASK          _U_(0x01)    /**< \brief (TRNG_INTENCLR) MASK Register */
-
-/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DATARDY:1;        /*!< bit:      0  Data Ready Interrupt Enable        */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TRNG_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_INTENSET_OFFSET        0x09         /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */
-#define TRNG_INTENSET_RESETVALUE    _U_(0x00)    /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */
-
-#define TRNG_INTENSET_DATARDY_Pos   0            /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */
-#define TRNG_INTENSET_DATARDY       (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos)
-#define TRNG_INTENSET_MASK          _U_(0x01)    /**< \brief (TRNG_INTENSET) MASK Register */
-
-/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  DATARDY:1;        /*!< bit:      0  Data Ready Interrupt Flag          */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} TRNG_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_INTFLAG_OFFSET         0x0A         /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */
-#define TRNG_INTFLAG_RESETVALUE     _U_(0x00)    /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define TRNG_INTFLAG_DATARDY_Pos    0            /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */
-#define TRNG_INTFLAG_DATARDY        (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos)
-#define TRNG_INTFLAG_MASK           _U_(0x01)    /**< \brief (TRNG_INTFLAG) MASK Register */
-
-/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/  32) Output Data -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DATA:32;          /*!< bit:  0..31  Output Data                        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} TRNG_DATA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define TRNG_DATA_OFFSET            0x20         /**< \brief (TRNG_DATA offset) Output Data */
-#define TRNG_DATA_RESETVALUE        _U_(0x00000000) /**< \brief (TRNG_DATA reset_value) Output Data */
-
-#define TRNG_DATA_DATA_Pos          0            /**< \brief (TRNG_DATA) Output Data */
-#define TRNG_DATA_DATA_Msk          (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos)
-#define TRNG_DATA_DATA(value)       (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))
-#define TRNG_DATA_MASK              _U_(0xFFFFFFFF) /**< \brief (TRNG_DATA) MASK Register */
-
-/** \brief TRNG hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO TRNG_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
-       RoReg8                    Reserved1[0x3];
-  __IO TRNG_EVCTRL_Type          EVCTRL;      /**< \brief Offset: 0x04 (R/W  8) Event Control */
-       RoReg8                    Reserved2[0x3];
-  __IO TRNG_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt Enable Clear */
-  __IO TRNG_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt Enable Set */
-  __IO TRNG_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x0A (R/W  8) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved3[0x15];
-  __I  TRNG_DATA_Type            DATA;        /**< \brief Offset: 0x20 (R/  32) Output Data */
-} Trng;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_TRNG_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/usb.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/usb.h
deleted file mode 100644
index 1c56e1dd02..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/usb.h
+++ /dev/null
@@ -1,1777 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for USB
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_USB_COMPONENT_
-#define _SAMD51_USB_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR USB */
-/* ========================================================================== */
-/** \addtogroup SAMD51_USB Universal Serial Bus */
-/*@{*/
-
-#define USB_U2222
-#define REV_USB                     0x120
-
-/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W  8) Control A -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  RUNSTDBY:1;       /*!< bit:      2  Run in Standby Mode                */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  MODE:1;           /*!< bit:      7  Operating Mode                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_CTRLA_OFFSET            0x000        /**< \brief (USB_CTRLA offset) Control A */
-#define USB_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (USB_CTRLA reset_value) Control A */
-
-#define USB_CTRLA_SWRST_Pos         0            /**< \brief (USB_CTRLA) Software Reset */
-#define USB_CTRLA_SWRST             (_U_(0x1) << USB_CTRLA_SWRST_Pos)
-#define USB_CTRLA_ENABLE_Pos        1            /**< \brief (USB_CTRLA) Enable */
-#define USB_CTRLA_ENABLE            (_U_(0x1) << USB_CTRLA_ENABLE_Pos)
-#define USB_CTRLA_RUNSTDBY_Pos      2            /**< \brief (USB_CTRLA) Run in Standby Mode */
-#define USB_CTRLA_RUNSTDBY          (_U_(0x1) << USB_CTRLA_RUNSTDBY_Pos)
-#define USB_CTRLA_MODE_Pos          7            /**< \brief (USB_CTRLA) Operating Mode */
-#define USB_CTRLA_MODE              (_U_(0x1) << USB_CTRLA_MODE_Pos)
-#define   USB_CTRLA_MODE_DEVICE_Val       _U_(0x0)   /**< \brief (USB_CTRLA) Device Mode */
-#define   USB_CTRLA_MODE_HOST_Val         _U_(0x1)   /**< \brief (USB_CTRLA) Host Mode */
-#define USB_CTRLA_MODE_DEVICE       (USB_CTRLA_MODE_DEVICE_Val     << USB_CTRLA_MODE_Pos)
-#define USB_CTRLA_MODE_HOST         (USB_CTRLA_MODE_HOST_Val       << USB_CTRLA_MODE_Pos)
-#define USB_CTRLA_MASK              _U_(0x87)    /**< \brief (USB_CTRLA) MASK Register */
-
-/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/   8) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_SYNCBUSY_OFFSET         0x002        /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
-#define USB_SYNCBUSY_RESETVALUE     _U_(0x00)    /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
-
-#define USB_SYNCBUSY_SWRST_Pos      0            /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
-#define USB_SYNCBUSY_SWRST          (_U_(0x1) << USB_SYNCBUSY_SWRST_Pos)
-#define USB_SYNCBUSY_ENABLE_Pos     1            /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
-#define USB_SYNCBUSY_ENABLE         (_U_(0x1) << USB_SYNCBUSY_ENABLE_Pos)
-#define USB_SYNCBUSY_MASK           _U_(0x03)    /**< \brief (USB_SYNCBUSY) MASK Register */
-
-/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W  8) USB Quality Of Service -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CQOS:2;           /*!< bit:  0.. 1  Configuration Quality of Service   */
-    uint8_t  DQOS:2;           /*!< bit:  2.. 3  Data Quality of Service            */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_QOSCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_QOSCTRL_OFFSET          0x003        /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
-#define USB_QOSCTRL_RESETVALUE      _U_(0x0F)    /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
-
-#define USB_QOSCTRL_CQOS_Pos        0            /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
-#define USB_QOSCTRL_CQOS_Msk        (_U_(0x3) << USB_QOSCTRL_CQOS_Pos)
-#define USB_QOSCTRL_CQOS(value)     (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
-#define USB_QOSCTRL_DQOS_Pos        2            /**< \brief (USB_QOSCTRL) Data Quality of Service */
-#define USB_QOSCTRL_DQOS_Msk        (_U_(0x3) << USB_QOSCTRL_DQOS_Pos)
-#define USB_QOSCTRL_DQOS(value)     (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
-#define USB_QOSCTRL_MASK            _U_(0x0F)    /**< \brief (USB_QOSCTRL) MASK Register */
-
-/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DETACH:1;         /*!< bit:      0  Detach                             */
-    uint16_t UPRSM:1;          /*!< bit:      1  Upstream Resume                    */
-    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration                */
-    uint16_t NREPLY:1;         /*!< bit:      4  No Reply                           */
-    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
-    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
-    uint16_t TSTPCKT:1;        /*!< bit:      7  Test packet mode                   */
-    uint16_t OPMODE2:1;        /*!< bit:      8  Specific Operational Mode          */
-    uint16_t GNAK:1;           /*!< bit:      9  Global NAK                         */
-    uint16_t LPMHDSK:2;        /*!< bit: 10..11  Link Power Management Handshake    */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_CTRLB_OFFSET     0x008        /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
-#define USB_DEVICE_CTRLB_RESETVALUE _U_(0x0001)  /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
-
-#define USB_DEVICE_CTRLB_DETACH_Pos 0            /**< \brief (USB_DEVICE_CTRLB) Detach */
-#define USB_DEVICE_CTRLB_DETACH     (_U_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos)
-#define USB_DEVICE_CTRLB_UPRSM_Pos  1            /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
-#define USB_DEVICE_CTRLB_UPRSM      (_U_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_Pos 2            /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
-#define USB_DEVICE_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
-#define   USB_DEVICE_CTRLB_SPDCONF_FS_Val _U_(0x0)   /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
-#define   USB_DEVICE_CTRLB_SPDCONF_LS_Val _U_(0x1)   /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
-#define   USB_DEVICE_CTRLB_SPDCONF_HS_Val _U_(0x2)   /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
-#define   USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U_(0x3)   /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
-#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
-#define USB_DEVICE_CTRLB_NREPLY_Pos 4            /**< \brief (USB_DEVICE_CTRLB) No Reply */
-#define USB_DEVICE_CTRLB_NREPLY     (_U_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos)
-#define USB_DEVICE_CTRLB_TSTJ_Pos   5            /**< \brief (USB_DEVICE_CTRLB) Test mode J */
-#define USB_DEVICE_CTRLB_TSTJ       (_U_(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos)
-#define USB_DEVICE_CTRLB_TSTK_Pos   6            /**< \brief (USB_DEVICE_CTRLB) Test mode K */
-#define USB_DEVICE_CTRLB_TSTK       (_U_(0x1) << USB_DEVICE_CTRLB_TSTK_Pos)
-#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7            /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
-#define USB_DEVICE_CTRLB_TSTPCKT    (_U_(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos)
-#define USB_DEVICE_CTRLB_OPMODE2_Pos 8            /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
-#define USB_DEVICE_CTRLB_OPMODE2    (_U_(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos)
-#define USB_DEVICE_CTRLB_GNAK_Pos   9            /**< \brief (USB_DEVICE_CTRLB) Global NAK */
-#define USB_DEVICE_CTRLB_GNAK       (_U_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10           /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
-#define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
-#define   USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U_(0x0)   /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
-#define   USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U_(0x1)   /**< \brief (USB_DEVICE_CTRLB) ACK */
-#define   USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U_(0x2)   /**< \brief (USB_DEVICE_CTRLB) NYET */
-#define   USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U_(0x3)   /**< \brief (USB_DEVICE_CTRLB) STALL */
-#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
-#define USB_DEVICE_CTRLB_MASK       _U_(0x0FFF)  /**< \brief (USB_DEVICE_CTRLB) MASK Register */
-
-/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :1;               /*!< bit:      0  Reserved                           */
-    uint16_t RESUME:1;         /*!< bit:      1  Send USB Resume                    */
-    uint16_t SPDCONF:2;        /*!< bit:  2.. 3  Speed Configuration for Host       */
-    uint16_t AUTORESUME:1;     /*!< bit:      4  Auto Resume Enable                 */
-    uint16_t TSTJ:1;           /*!< bit:      5  Test mode J                        */
-    uint16_t TSTK:1;           /*!< bit:      6  Test mode K                        */
-    uint16_t :1;               /*!< bit:      7  Reserved                           */
-    uint16_t SOFE:1;           /*!< bit:      8  Start of Frame Generation Enable   */
-    uint16_t BUSRESET:1;       /*!< bit:      9  Send USB Reset                     */
-    uint16_t VBUSOK:1;         /*!< bit:     10  VBUS is OK                         */
-    uint16_t L1RESUME:1;       /*!< bit:     11  Send L1 Resume                     */
-    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_CTRLB_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_CTRLB_OFFSET       0x008        /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
-#define USB_HOST_CTRLB_RESETVALUE   _U_(0x0000)  /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
-
-#define USB_HOST_CTRLB_RESUME_Pos   1            /**< \brief (USB_HOST_CTRLB) Send USB Resume */
-#define USB_HOST_CTRLB_RESUME       (_U_(0x1) << USB_HOST_CTRLB_RESUME_Pos)
-#define USB_HOST_CTRLB_SPDCONF_Pos  2            /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
-#define USB_HOST_CTRLB_SPDCONF_Msk  (_U_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos)
-#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
-#define   USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U_(0x0)   /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
-#define   USB_HOST_CTRLB_SPDCONF_FS_Val   _U_(0x3)   /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
-#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
-#define USB_HOST_CTRLB_SPDCONF_FS   (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
-#define USB_HOST_CTRLB_AUTORESUME_Pos 4            /**< \brief (USB_HOST_CTRLB) Auto Resume Enable */
-#define USB_HOST_CTRLB_AUTORESUME   (_U_(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos)
-#define USB_HOST_CTRLB_TSTJ_Pos     5            /**< \brief (USB_HOST_CTRLB) Test mode J */
-#define USB_HOST_CTRLB_TSTJ         (_U_(0x1) << USB_HOST_CTRLB_TSTJ_Pos)
-#define USB_HOST_CTRLB_TSTK_Pos     6            /**< \brief (USB_HOST_CTRLB) Test mode K */
-#define USB_HOST_CTRLB_TSTK         (_U_(0x1) << USB_HOST_CTRLB_TSTK_Pos)
-#define USB_HOST_CTRLB_SOFE_Pos     8            /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
-#define USB_HOST_CTRLB_SOFE         (_U_(0x1) << USB_HOST_CTRLB_SOFE_Pos)
-#define USB_HOST_CTRLB_BUSRESET_Pos 9            /**< \brief (USB_HOST_CTRLB) Send USB Reset */
-#define USB_HOST_CTRLB_BUSRESET     (_U_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos)
-#define USB_HOST_CTRLB_VBUSOK_Pos   10           /**< \brief (USB_HOST_CTRLB) VBUS is OK */
-#define USB_HOST_CTRLB_VBUSOK       (_U_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos)
-#define USB_HOST_CTRLB_L1RESUME_Pos 11           /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
-#define USB_HOST_CTRLB_L1RESUME     (_U_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos)
-#define USB_HOST_CTRLB_MASK         _U_(0x0F7E)  /**< \brief (USB_HOST_CTRLB) MASK Register */
-
-/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE Device Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DADD:7;           /*!< bit:  0.. 6  Device Address                     */
-    uint8_t  ADDEN:1;          /*!< bit:      7  Device Address Enable              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_DADD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_DADD_OFFSET      0x00A        /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
-#define USB_DEVICE_DADD_RESETVALUE  _U_(0x00)    /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
-
-#define USB_DEVICE_DADD_DADD_Pos    0            /**< \brief (USB_DEVICE_DADD) Device Address */
-#define USB_DEVICE_DADD_DADD_Msk    (_U_(0x7F) << USB_DEVICE_DADD_DADD_Pos)
-#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
-#define USB_DEVICE_DADD_ADDEN_Pos   7            /**< \brief (USB_DEVICE_DADD) Device Address Enable */
-#define USB_DEVICE_DADD_ADDEN       (_U_(0x1) << USB_DEVICE_DADD_ADDEN_Pos)
-#define USB_DEVICE_DADD_MASK        _U_(0xFF)    /**< \brief (USB_DEVICE_DADD) MASK Register */
-
-/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W  8) HOST HOST Host Start Of Frame Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FLENC:4;          /*!< bit:  0.. 3  Frame Length Control               */
-    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
-    uint8_t  FLENCE:1;         /*!< bit:      7  Frame Length Control Enable        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_HSOFC_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_HSOFC_OFFSET       0x00A        /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
-#define USB_HOST_HSOFC_RESETVALUE   _U_(0x00)    /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
-
-#define USB_HOST_HSOFC_FLENC_Pos    0            /**< \brief (USB_HOST_HSOFC) Frame Length Control */
-#define USB_HOST_HSOFC_FLENC_Msk    (_U_(0xF) << USB_HOST_HSOFC_FLENC_Pos)
-#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
-#define USB_HOST_HSOFC_FLENCE_Pos   7            /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
-#define USB_HOST_HSOFC_FLENCE       (_U_(0x1) << USB_HOST_HSOFC_FLENCE_Pos)
-#define USB_HOST_HSOFC_MASK         _U_(0x8F)    /**< \brief (USB_HOST_HSOFC) MASK Register */
-
-/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/   8) DEVICE DEVICE Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
-    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_STATUS_OFFSET    0x00C        /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
-#define USB_DEVICE_STATUS_RESETVALUE _U_(0x40)    /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
-
-#define USB_DEVICE_STATUS_SPEED_Pos 2            /**< \brief (USB_DEVICE_STATUS) Speed Status */
-#define USB_DEVICE_STATUS_SPEED_Msk (_U_(0x3) << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
-#define   USB_DEVICE_STATUS_SPEED_FS_Val  _U_(0x0)   /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
-#define   USB_DEVICE_STATUS_SPEED_LS_Val  _U_(0x1)   /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
-#define   USB_DEVICE_STATUS_SPEED_HS_Val  _U_(0x2)   /**< \brief (USB_DEVICE_STATUS) High-speed mode */
-#define USB_DEVICE_STATUS_SPEED_FS  (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_SPEED_LS  (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_SPEED_HS  (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
-#define USB_DEVICE_STATUS_LINESTATE_Pos 6            /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
-#define USB_DEVICE_STATUS_LINESTATE_Msk (_U_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
-#define   USB_DEVICE_STATUS_LINESTATE_0_Val _U_(0x0)   /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
-#define   USB_DEVICE_STATUS_LINESTATE_1_Val _U_(0x1)   /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
-#define   USB_DEVICE_STATUS_LINESTATE_2_Val _U_(0x2)   /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
-#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
-#define USB_DEVICE_STATUS_MASK      _U_(0xCC)    /**< \brief (USB_DEVICE_STATUS) MASK Register */
-
-/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W  8) HOST HOST Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint8_t  SPEED:2;          /*!< bit:  2.. 3  Speed Status                       */
-    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
-    uint8_t  LINESTATE:2;      /*!< bit:  6.. 7  USB Line State Status              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_STATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_STATUS_OFFSET      0x00C        /**< \brief (USB_HOST_STATUS offset) HOST Status */
-#define USB_HOST_STATUS_RESETVALUE  _U_(0x00)    /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
-
-#define USB_HOST_STATUS_SPEED_Pos   2            /**< \brief (USB_HOST_STATUS) Speed Status */
-#define USB_HOST_STATUS_SPEED_Msk   (_U_(0x3) << USB_HOST_STATUS_SPEED_Pos)
-#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
-#define USB_HOST_STATUS_LINESTATE_Pos 6            /**< \brief (USB_HOST_STATUS) USB Line State Status */
-#define USB_HOST_STATUS_LINESTATE_Msk (_U_(0x3) << USB_HOST_STATUS_LINESTATE_Pos)
-#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
-#define USB_HOST_STATUS_MASK        _U_(0xCC)    /**< \brief (USB_HOST_STATUS) MASK Register */
-
-/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/   8) Finite State Machine Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FSMSTATE:7;       /*!< bit:  0.. 6  Fine State Machine Status          */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_FSMSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_FSMSTATUS_OFFSET        0x00D        /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
-#define USB_FSMSTATUS_RESETVALUE    _U_(0x01)    /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
-
-#define USB_FSMSTATUS_FSMSTATE_Pos  0            /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
-#define USB_FSMSTATUS_FSMSTATE_Msk  (_U_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
-#define   USB_FSMSTATUS_FSMSTATE_OFF_Val  _U_(0x1)   /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
-#define   USB_FSMSTATUS_FSMSTATE_ON_Val   _U_(0x2)   /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
-#define   USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U_(0x4)   /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
-#define   USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U_(0x8)   /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
-#define   USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U_(0x10)   /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
-#define   USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U_(0x20)   /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
-#define   USB_FSMSTATUS_FSMSTATE_RESET_Val _U_(0x40)   /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
-#define USB_FSMSTATUS_FSMSTATE_OFF  (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_ON   (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
-#define USB_FSMSTATUS_MASK          _U_(0x7F)    /**< \brief (USB_FSMSTATUS) MASK Register */
-
-/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/  16) DEVICE DEVICE Device Frame Number -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
-    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
-    uint16_t :1;               /*!< bit:     14  Reserved                           */
-    uint16_t FNCERR:1;         /*!< bit:     15  Frame Number CRC Error             */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_FNUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_FNUM_OFFSET      0x010        /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
-#define USB_DEVICE_FNUM_RESETVALUE  _U_(0x0000)  /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
-
-#define USB_DEVICE_FNUM_MFNUM_Pos   0            /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
-#define USB_DEVICE_FNUM_MFNUM_Msk   (_U_(0x7) << USB_DEVICE_FNUM_MFNUM_Pos)
-#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
-#define USB_DEVICE_FNUM_FNUM_Pos    3            /**< \brief (USB_DEVICE_FNUM) Frame Number */
-#define USB_DEVICE_FNUM_FNUM_Msk    (_U_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos)
-#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
-#define USB_DEVICE_FNUM_FNCERR_Pos  15           /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
-#define USB_DEVICE_FNUM_FNCERR      (_U_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos)
-#define USB_DEVICE_FNUM_MASK        _U_(0xBFFF)  /**< \brief (USB_DEVICE_FNUM) MASK Register */
-
-/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t MFNUM:3;          /*!< bit:  0.. 2  Micro Frame Number                 */
-    uint16_t FNUM:11;          /*!< bit:  3..13  Frame Number                       */
-    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_FNUM_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_FNUM_OFFSET        0x010        /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
-#define USB_HOST_FNUM_RESETVALUE    _U_(0x0000)  /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
-
-#define USB_HOST_FNUM_MFNUM_Pos     0            /**< \brief (USB_HOST_FNUM) Micro Frame Number */
-#define USB_HOST_FNUM_MFNUM_Msk     (_U_(0x7) << USB_HOST_FNUM_MFNUM_Pos)
-#define USB_HOST_FNUM_MFNUM(value)  (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
-#define USB_HOST_FNUM_FNUM_Pos      3            /**< \brief (USB_HOST_FNUM) Frame Number */
-#define USB_HOST_FNUM_FNUM_Msk      (_U_(0x7FF) << USB_HOST_FNUM_FNUM_Pos)
-#define USB_HOST_FNUM_FNUM(value)   (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
-#define USB_HOST_FNUM_MASK          _U_(0x3FFF)  /**< \brief (USB_HOST_FNUM) MASK Register */
-
-/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/   8) HOST HOST Host Frame Length -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  FLENHIGH:8;       /*!< bit:  0.. 7  Frame Length                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_FLENHIGH_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_FLENHIGH_OFFSET    0x012        /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
-#define USB_HOST_FLENHIGH_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
-
-#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0            /**< \brief (USB_HOST_FLENHIGH) Frame Length */
-#define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos)
-#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
-#define USB_HOST_FLENHIGH_MASK      _U_(0xFF)    /**< \brief (USB_HOST_FLENHIGH) MASK Register */
-
-/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
-    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
-    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
-    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
-    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
-    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
-    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
-    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
-    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
-    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_INTENCLR_OFFSET  0x014        /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
-#define USB_DEVICE_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
-
-#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
-#define USB_DEVICE_INTENCLR_SUSPEND (_U_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos)
-#define USB_DEVICE_INTENCLR_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
-#define USB_DEVICE_INTENCLR_MSOF    (_U_(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos)
-#define USB_DEVICE_INTENCLR_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
-#define USB_DEVICE_INTENCLR_SOF     (_U_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos)
-#define USB_DEVICE_INTENCLR_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
-#define USB_DEVICE_INTENCLR_EORST   (_U_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos)
-#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
-#define USB_DEVICE_INTENCLR_WAKEUP  (_U_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos)
-#define USB_DEVICE_INTENCLR_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
-#define USB_DEVICE_INTENCLR_EORSM   (_U_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos)
-#define USB_DEVICE_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
-#define USB_DEVICE_INTENCLR_UPRSM   (_U_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos)
-#define USB_DEVICE_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
-#define USB_DEVICE_INTENCLR_RAMACER (_U_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos)
-#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
-#define USB_DEVICE_INTENCLR_LPMNYET (_U_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos)
-#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
-#define USB_DEVICE_INTENCLR_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
-#define USB_DEVICE_INTENCLR_MASK    _U_(0x03FF)  /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
-
-/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Disable */
-    uint16_t RST:1;            /*!< bit:      3  BUS Reset Interrupt Disable        */
-    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Disable          */
-    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to Device Interrupt Disable */
-    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from Device Interrupt Disable */
-    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Disable       */
-    uint16_t DCONN:1;          /*!< bit:      8  Device Connection Interrupt Disable */
-    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Disable */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_INTENCLR_OFFSET    0x014        /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
-#define USB_HOST_INTENCLR_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
-
-#define USB_HOST_INTENCLR_HSOF_Pos  2            /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
-#define USB_HOST_INTENCLR_HSOF      (_U_(0x1) << USB_HOST_INTENCLR_HSOF_Pos)
-#define USB_HOST_INTENCLR_RST_Pos   3            /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
-#define USB_HOST_INTENCLR_RST       (_U_(0x1) << USB_HOST_INTENCLR_RST_Pos)
-#define USB_HOST_INTENCLR_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
-#define USB_HOST_INTENCLR_WAKEUP    (_U_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos)
-#define USB_HOST_INTENCLR_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
-#define USB_HOST_INTENCLR_DNRSM     (_U_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos)
-#define USB_HOST_INTENCLR_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
-#define USB_HOST_INTENCLR_UPRSM     (_U_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos)
-#define USB_HOST_INTENCLR_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
-#define USB_HOST_INTENCLR_RAMACER   (_U_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos)
-#define USB_HOST_INTENCLR_DCONN_Pos 8            /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
-#define USB_HOST_INTENCLR_DCONN     (_U_(0x1) << USB_HOST_INTENCLR_DCONN_Pos)
-#define USB_HOST_INTENCLR_DDISC_Pos 9            /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
-#define USB_HOST_INTENCLR_DDISC     (_U_(0x1) << USB_HOST_INTENCLR_DDISC_Pos)
-#define USB_HOST_INTENCLR_MASK      _U_(0x03FC)  /**< \brief (USB_HOST_INTENCLR) MASK Register */
-
-/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SUSPEND:1;        /*!< bit:      0  Suspend Interrupt Enable           */
-    uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame Interrupt Enable in High Speed Mode */
-    uint16_t SOF:1;            /*!< bit:      2  Start Of Frame Interrupt Enable    */
-    uint16_t EORST:1;          /*!< bit:      3  End of Reset Interrupt Enable      */
-    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
-    uint16_t EORSM:1;          /*!< bit:      5  End Of Resume Interrupt Enable     */
-    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume Interrupt Enable   */
-    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
-    uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet Interrupt Enable */
-    uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend Interrupt Enable */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_INTENSET_OFFSET  0x018        /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
-#define USB_DEVICE_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
-
-#define USB_DEVICE_INTENSET_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
-#define USB_DEVICE_INTENSET_SUSPEND (_U_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos)
-#define USB_DEVICE_INTENSET_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
-#define USB_DEVICE_INTENSET_MSOF    (_U_(0x1) << USB_DEVICE_INTENSET_MSOF_Pos)
-#define USB_DEVICE_INTENSET_SOF_Pos 2            /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
-#define USB_DEVICE_INTENSET_SOF     (_U_(0x1) << USB_DEVICE_INTENSET_SOF_Pos)
-#define USB_DEVICE_INTENSET_EORST_Pos 3            /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
-#define USB_DEVICE_INTENSET_EORST   (_U_(0x1) << USB_DEVICE_INTENSET_EORST_Pos)
-#define USB_DEVICE_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
-#define USB_DEVICE_INTENSET_WAKEUP  (_U_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos)
-#define USB_DEVICE_INTENSET_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
-#define USB_DEVICE_INTENSET_EORSM   (_U_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos)
-#define USB_DEVICE_INTENSET_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
-#define USB_DEVICE_INTENSET_UPRSM   (_U_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos)
-#define USB_DEVICE_INTENSET_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
-#define USB_DEVICE_INTENSET_RAMACER (_U_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos)
-#define USB_DEVICE_INTENSET_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
-#define USB_DEVICE_INTENSET_LPMNYET (_U_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos)
-#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
-#define USB_DEVICE_INTENSET_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos)
-#define USB_DEVICE_INTENSET_MASK    _U_(0x03FF)  /**< \brief (USB_DEVICE_INTENSET) MASK Register */
-
-/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame Interrupt Enable */
-    uint16_t RST:1;            /*!< bit:      3  Bus Reset Interrupt Enable         */
-    uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up Interrupt Enable           */
-    uint16_t DNRSM:1;          /*!< bit:      5  DownStream to the Device Interrupt Enable */
-    uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume fromthe device Interrupt Enable */
-    uint16_t RAMACER:1;        /*!< bit:      7  Ram Access Interrupt Enable        */
-    uint16_t DCONN:1;          /*!< bit:      8  Link Power Management Interrupt Enable */
-    uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection Interrupt Enable */
-    uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_INTENSET_OFFSET    0x018        /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
-#define USB_HOST_INTENSET_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
-
-#define USB_HOST_INTENSET_HSOF_Pos  2            /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
-#define USB_HOST_INTENSET_HSOF      (_U_(0x1) << USB_HOST_INTENSET_HSOF_Pos)
-#define USB_HOST_INTENSET_RST_Pos   3            /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
-#define USB_HOST_INTENSET_RST       (_U_(0x1) << USB_HOST_INTENSET_RST_Pos)
-#define USB_HOST_INTENSET_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
-#define USB_HOST_INTENSET_WAKEUP    (_U_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos)
-#define USB_HOST_INTENSET_DNRSM_Pos 5            /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
-#define USB_HOST_INTENSET_DNRSM     (_U_(0x1) << USB_HOST_INTENSET_DNRSM_Pos)
-#define USB_HOST_INTENSET_UPRSM_Pos 6            /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
-#define USB_HOST_INTENSET_UPRSM     (_U_(0x1) << USB_HOST_INTENSET_UPRSM_Pos)
-#define USB_HOST_INTENSET_RAMACER_Pos 7            /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
-#define USB_HOST_INTENSET_RAMACER   (_U_(0x1) << USB_HOST_INTENSET_RAMACER_Pos)
-#define USB_HOST_INTENSET_DCONN_Pos 8            /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
-#define USB_HOST_INTENSET_DCONN     (_U_(0x1) << USB_HOST_INTENSET_DCONN_Pos)
-#define USB_HOST_INTENSET_DDISC_Pos 9            /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
-#define USB_HOST_INTENSET_DDISC     (_U_(0x1) << USB_HOST_INTENSET_DDISC_Pos)
-#define USB_HOST_INTENSET_MASK      _U_(0x03FC)  /**< \brief (USB_HOST_INTENSET) MASK Register */
-
-/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t SUSPEND:1;        /*!< bit:      0  Suspend                            */
-    __I uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame in High Speed Mode */
-    __I uint16_t SOF:1;            /*!< bit:      2  Start Of Frame                     */
-    __I uint16_t EORST:1;          /*!< bit:      3  End of Reset                       */
-    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
-    __I uint16_t EORSM:1;          /*!< bit:      5  End Of Resume                      */
-    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume                    */
-    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
-    __I uint16_t LPMNYET:1;        /*!< bit:      8  Link Power Management Not Yet      */
-    __I uint16_t LPMSUSP:1;        /*!< bit:      9  Link Power Management Suspend      */
-    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_INTFLAG_OFFSET   0x01C        /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
-#define USB_DEVICE_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
-
-#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0            /**< \brief (USB_DEVICE_INTFLAG) Suspend */
-#define USB_DEVICE_INTFLAG_SUSPEND  (_U_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos)
-#define USB_DEVICE_INTFLAG_MSOF_Pos 1            /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
-#define USB_DEVICE_INTFLAG_MSOF     (_U_(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos)
-#define USB_DEVICE_INTFLAG_SOF_Pos  2            /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
-#define USB_DEVICE_INTFLAG_SOF      (_U_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos)
-#define USB_DEVICE_INTFLAG_EORST_Pos 3            /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
-#define USB_DEVICE_INTFLAG_EORST    (_U_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos)
-#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
-#define USB_DEVICE_INTFLAG_WAKEUP   (_U_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos)
-#define USB_DEVICE_INTFLAG_EORSM_Pos 5            /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
-#define USB_DEVICE_INTFLAG_EORSM    (_U_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos)
-#define USB_DEVICE_INTFLAG_UPRSM_Pos 6            /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
-#define USB_DEVICE_INTFLAG_UPRSM    (_U_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos)
-#define USB_DEVICE_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
-#define USB_DEVICE_INTFLAG_RAMACER  (_U_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos)
-#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
-#define USB_DEVICE_INTFLAG_LPMNYET  (_U_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos)
-#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9            /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
-#define USB_DEVICE_INTFLAG_LPMSUSP  (_U_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
-#define USB_DEVICE_INTFLAG_MASK     _U_(0x03FF)  /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
-
-/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
-    __I uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame                */
-    __I uint16_t RST:1;            /*!< bit:      3  Bus Reset                          */
-    __I uint16_t WAKEUP:1;         /*!< bit:      4  Wake Up                            */
-    __I uint16_t DNRSM:1;          /*!< bit:      5  Downstream                         */
-    __I uint16_t UPRSM:1;          /*!< bit:      6  Upstream Resume from the Device    */
-    __I uint16_t RAMACER:1;        /*!< bit:      7  Ram Access                         */
-    __I uint16_t DCONN:1;          /*!< bit:      8  Device Connection                  */
-    __I uint16_t DDISC:1;          /*!< bit:      9  Device Disconnection               */
-    __I uint16_t :6;               /*!< bit: 10..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_INTFLAG_OFFSET     0x01C        /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
-#define USB_HOST_INTFLAG_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
-
-#define USB_HOST_INTFLAG_HSOF_Pos   2            /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
-#define USB_HOST_INTFLAG_HSOF       (_U_(0x1) << USB_HOST_INTFLAG_HSOF_Pos)
-#define USB_HOST_INTFLAG_RST_Pos    3            /**< \brief (USB_HOST_INTFLAG) Bus Reset */
-#define USB_HOST_INTFLAG_RST        (_U_(0x1) << USB_HOST_INTFLAG_RST_Pos)
-#define USB_HOST_INTFLAG_WAKEUP_Pos 4            /**< \brief (USB_HOST_INTFLAG) Wake Up */
-#define USB_HOST_INTFLAG_WAKEUP     (_U_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos)
-#define USB_HOST_INTFLAG_DNRSM_Pos  5            /**< \brief (USB_HOST_INTFLAG) Downstream */
-#define USB_HOST_INTFLAG_DNRSM      (_U_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos)
-#define USB_HOST_INTFLAG_UPRSM_Pos  6            /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
-#define USB_HOST_INTFLAG_UPRSM      (_U_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos)
-#define USB_HOST_INTFLAG_RAMACER_Pos 7            /**< \brief (USB_HOST_INTFLAG) Ram Access */
-#define USB_HOST_INTFLAG_RAMACER    (_U_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos)
-#define USB_HOST_INTFLAG_DCONN_Pos  8            /**< \brief (USB_HOST_INTFLAG) Device Connection */
-#define USB_HOST_INTFLAG_DCONN      (_U_(0x1) << USB_HOST_INTFLAG_DCONN_Pos)
-#define USB_HOST_INTFLAG_DDISC_Pos  9            /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
-#define USB_HOST_INTFLAG_DDISC      (_U_(0x1) << USB_HOST_INTFLAG_DDISC_Pos)
-#define USB_HOST_INTFLAG_MASK       _U_(0x03FC)  /**< \brief (USB_HOST_INTFLAG) MASK Register */
-
-/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/  16) DEVICE DEVICE End Point Interrupt Summary -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t EPINT0:1;         /*!< bit:      0  End Point 0 Interrupt              */
-    uint16_t EPINT1:1;         /*!< bit:      1  End Point 1 Interrupt              */
-    uint16_t EPINT2:1;         /*!< bit:      2  End Point 2 Interrupt              */
-    uint16_t EPINT3:1;         /*!< bit:      3  End Point 3 Interrupt              */
-    uint16_t EPINT4:1;         /*!< bit:      4  End Point 4 Interrupt              */
-    uint16_t EPINT5:1;         /*!< bit:      5  End Point 5 Interrupt              */
-    uint16_t EPINT6:1;         /*!< bit:      6  End Point 6 Interrupt              */
-    uint16_t EPINT7:1;         /*!< bit:      7  End Point 7 Interrupt              */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t EPINT:8;          /*!< bit:  0.. 7  End Point x Interrupt              */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_EPINTSMRY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTSMRY_OFFSET 0x020        /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
-#define USB_DEVICE_EPINTSMRY_RESETVALUE _U_(0x0000)  /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
-
-#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT0 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT1 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT2 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT3 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT4 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT5 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT6 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7            /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT7 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0            /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
-#define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos)
-#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
-#define USB_DEVICE_EPINTSMRY_MASK   _U_(0x00FF)  /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
-
-/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/  16) HOST HOST Pipe Interrupt Summary -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t EPINT0:1;         /*!< bit:      0  Pipe 0 Interrupt                   */
-    uint16_t EPINT1:1;         /*!< bit:      1  Pipe 1 Interrupt                   */
-    uint16_t EPINT2:1;         /*!< bit:      2  Pipe 2 Interrupt                   */
-    uint16_t EPINT3:1;         /*!< bit:      3  Pipe 3 Interrupt                   */
-    uint16_t EPINT4:1;         /*!< bit:      4  Pipe 4 Interrupt                   */
-    uint16_t EPINT5:1;         /*!< bit:      5  Pipe 5 Interrupt                   */
-    uint16_t EPINT6:1;         /*!< bit:      6  Pipe 6 Interrupt                   */
-    uint16_t EPINT7:1;         /*!< bit:      7  Pipe 7 Interrupt                   */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint16_t EPINT:8;          /*!< bit:  0.. 7  Pipe x Interrupt                   */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_PINTSMRY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTSMRY_OFFSET    0x020        /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
-#define USB_HOST_PINTSMRY_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
-
-#define USB_HOST_PINTSMRY_EPINT0_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT0    (_U_(1) << USB_HOST_PINTSMRY_EPINT0_Pos)
-#define USB_HOST_PINTSMRY_EPINT1_Pos 1            /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT1    (_U_(1) << USB_HOST_PINTSMRY_EPINT1_Pos)
-#define USB_HOST_PINTSMRY_EPINT2_Pos 2            /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT2    (_U_(1) << USB_HOST_PINTSMRY_EPINT2_Pos)
-#define USB_HOST_PINTSMRY_EPINT3_Pos 3            /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT3    (_U_(1) << USB_HOST_PINTSMRY_EPINT3_Pos)
-#define USB_HOST_PINTSMRY_EPINT4_Pos 4            /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT4    (_U_(1) << USB_HOST_PINTSMRY_EPINT4_Pos)
-#define USB_HOST_PINTSMRY_EPINT5_Pos 5            /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT5    (_U_(1) << USB_HOST_PINTSMRY_EPINT5_Pos)
-#define USB_HOST_PINTSMRY_EPINT6_Pos 6            /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT6    (_U_(1) << USB_HOST_PINTSMRY_EPINT6_Pos)
-#define USB_HOST_PINTSMRY_EPINT7_Pos 7            /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
-#define USB_HOST_PINTSMRY_EPINT7    (_U_(1) << USB_HOST_PINTSMRY_EPINT7_Pos)
-#define USB_HOST_PINTSMRY_EPINT_Pos 0            /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
-#define USB_HOST_PINTSMRY_EPINT_Msk (_U_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos)
-#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
-#define USB_HOST_PINTSMRY_MASK      _U_(0x00FF)  /**< \brief (USB_HOST_PINTSMRY) MASK Register */
-
-/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t DESCADD:32;       /*!< bit:  0..31  Descriptor Address Value           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_DESCADD_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DESCADD_OFFSET          0x024        /**< \brief (USB_DESCADD offset) Descriptor Address */
-#define USB_DESCADD_RESETVALUE      _U_(0x00000000) /**< \brief (USB_DESCADD reset_value) Descriptor Address */
-
-#define USB_DESCADD_DESCADD_Pos     0            /**< \brief (USB_DESCADD) Descriptor Address Value */
-#define USB_DESCADD_DESCADD_Msk     (_U_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos)
-#define USB_DESCADD_DESCADD(value)  (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
-#define USB_DESCADD_MASK            _U_(0xFFFFFFFF) /**< \brief (USB_DESCADD) MASK Register */
-
-/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t TRANSP:5;         /*!< bit:  0.. 4  USB Pad Transp calibration         */
-    uint16_t :1;               /*!< bit:      5  Reserved                           */
-    uint16_t TRANSN:5;         /*!< bit:  6..10  USB Pad Transn calibration         */
-    uint16_t :1;               /*!< bit:     11  Reserved                           */
-    uint16_t TRIM:3;           /*!< bit: 12..14  USB Pad Trim calibration           */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_PADCAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_PADCAL_OFFSET           0x028        /**< \brief (USB_PADCAL offset) USB PAD Calibration */
-#define USB_PADCAL_RESETVALUE       _U_(0x0000)  /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
-
-#define USB_PADCAL_TRANSP_Pos       0            /**< \brief (USB_PADCAL) USB Pad Transp calibration */
-#define USB_PADCAL_TRANSP_Msk       (_U_(0x1F) << USB_PADCAL_TRANSP_Pos)
-#define USB_PADCAL_TRANSP(value)    (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
-#define USB_PADCAL_TRANSN_Pos       6            /**< \brief (USB_PADCAL) USB Pad Transn calibration */
-#define USB_PADCAL_TRANSN_Msk       (_U_(0x1F) << USB_PADCAL_TRANSN_Pos)
-#define USB_PADCAL_TRANSN(value)    (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
-#define USB_PADCAL_TRIM_Pos         12           /**< \brief (USB_PADCAL) USB Pad Trim calibration */
-#define USB_PADCAL_TRIM_Msk         (_U_(0x7) << USB_PADCAL_TRIM_Pos)
-#define USB_PADCAL_TRIM(value)      (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
-#define USB_PADCAL_MASK             _U_(0x77DF)  /**< \brief (USB_PADCAL) MASK Register */
-
-/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EPTYPE0:3;        /*!< bit:  0.. 2  End Point Type0                    */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  EPTYPE1:3;        /*!< bit:  4.. 6  End Point Type1                    */
-    uint8_t  NYETDIS:1;        /*!< bit:      7  NYET Token Disable                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPCFG_OFFSET     0x100        /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
-#define USB_DEVICE_EPCFG_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
-
-#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0            /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
-#define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos)
-#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
-#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4            /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
-#define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos)
-#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
-#define USB_DEVICE_EPCFG_NYETDIS_Pos 7            /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
-#define USB_DEVICE_EPCFG_NYETDIS    (_U_(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos)
-#define USB_DEVICE_EPCFG_MASK       _U_(0xF7)    /**< \brief (USB_DEVICE_EPCFG) MASK Register */
-
-/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W  8) HOST HOST_PIPE End Point Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PTOKEN:2;         /*!< bit:  0.. 1  Pipe Token                         */
-    uint8_t  BK:1;             /*!< bit:      2  Pipe Bank                          */
-    uint8_t  PTYPE:3;          /*!< bit:  3.. 5  Pipe Type                          */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PCFG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PCFG_OFFSET        0x100        /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
-#define USB_HOST_PCFG_RESETVALUE    _U_(0x00)    /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
-
-#define USB_HOST_PCFG_PTOKEN_Pos    0            /**< \brief (USB_HOST_PCFG) Pipe Token */
-#define USB_HOST_PCFG_PTOKEN_Msk    (_U_(0x3) << USB_HOST_PCFG_PTOKEN_Pos)
-#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
-#define USB_HOST_PCFG_BK_Pos        2            /**< \brief (USB_HOST_PCFG) Pipe Bank */
-#define USB_HOST_PCFG_BK            (_U_(0x1) << USB_HOST_PCFG_BK_Pos)
-#define USB_HOST_PCFG_PTYPE_Pos     3            /**< \brief (USB_HOST_PCFG) Pipe Type */
-#define USB_HOST_PCFG_PTYPE_Msk     (_U_(0x7) << USB_HOST_PCFG_PTYPE_Pos)
-#define USB_HOST_PCFG_PTYPE(value)  (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
-#define USB_HOST_PCFG_MASK          _U_(0x3F)    /**< \brief (USB_HOST_PCFG) MASK Register */
-
-/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W  8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  BITINTERVAL:8;    /*!< bit:  0.. 7  Bit Interval                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_BINTERVAL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_BINTERVAL_OFFSET   0x103        /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
-#define USB_HOST_BINTERVAL_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
-
-#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0            /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
-#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
-#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
-#define USB_HOST_BINTERVAL_MASK     _U_(0xFF)    /**< \brief (USB_HOST_BINTERVAL) MASK Register */
-
-/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Clear              */
-    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Clear               */
-    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Clear                 */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Clear              */
-    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Clear              */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Clear              */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPSTATUSCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104        /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
-#define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
-
-#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
-#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
-#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
-#define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
-#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSCLR) Current Bank Clear */
-#define USB_DEVICE_EPSTATUSCLR_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
-#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
-#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
-#define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
-#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
-#define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
-#define USB_DEVICE_EPSTATUSCLR_MASK _U_(0xF7)    /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
-
-/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W  8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle clear                  */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  CURBK:1;          /*!< bit:      2  Curren Bank clear                  */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Clear                  */
-    uint8_t  :1;               /*!< bit:      5  Reserved                           */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Clear                 */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Clear                 */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PSTATUSCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PSTATUSCLR_OFFSET  0x104        /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
-#define USB_HOST_PSTATUSCLR_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
-
-#define USB_HOST_PSTATUSCLR_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
-#define USB_HOST_PSTATUSCLR_DTGL    (_U_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos)
-#define USB_HOST_PSTATUSCLR_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
-#define USB_HOST_PSTATUSCLR_CURBK   (_U_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos)
-#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
-#define USB_HOST_PSTATUSCLR_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
-#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
-#define USB_HOST_PSTATUSCLR_BK0RDY  (_U_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
-#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
-#define USB_HOST_PSTATUSCLR_BK1RDY  (_U_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
-#define USB_HOST_PSTATUSCLR_MASK    _U_(0xD5)    /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
-
-/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W  8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle OUT Set                */
-    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle IN Set                 */
-    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request Set                */
-    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request Set                */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request Set                */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPSTATUSSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105        /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
-#define USB_DEVICE_EPSTATUSSET_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
-
-#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
-#define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
-#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
-#define USB_DEVICE_EPSTATUSSET_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
-#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
-#define USB_DEVICE_EPSTATUSSET_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
-#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
-#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
-#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
-#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
-#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
-#define USB_DEVICE_EPSTATUSSET_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
-#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
-#define USB_DEVICE_EPSTATUSSET_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
-#define USB_DEVICE_EPSTATUSSET_MASK _U_(0xF7)    /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
-
-/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W  8) HOST HOST_PIPE End Point Pipe Status Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle Set                    */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank Set                   */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze Set                    */
-    uint8_t  :1;               /*!< bit:      5  Reserved                           */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 Ready Set                   */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 Ready Set                   */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PSTATUSSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PSTATUSSET_OFFSET  0x105        /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
-#define USB_HOST_PSTATUSSET_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
-
-#define USB_HOST_PSTATUSSET_DTGL_Pos 0            /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
-#define USB_HOST_PSTATUSSET_DTGL    (_U_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos)
-#define USB_HOST_PSTATUSSET_CURBK_Pos 2            /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
-#define USB_HOST_PSTATUSSET_CURBK   (_U_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos)
-#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
-#define USB_HOST_PSTATUSSET_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos)
-#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
-#define USB_HOST_PSTATUSSET_BK0RDY  (_U_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos)
-#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
-#define USB_HOST_PSTATUSSET_BK1RDY  (_U_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos)
-#define USB_HOST_PSTATUSSET_MASK    _U_(0xD5)    /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
-
-/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/   8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGLOUT:1;        /*!< bit:      0  Data Toggle Out                    */
-    uint8_t  DTGLIN:1;         /*!< bit:      1  Data Toggle In                     */
-    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  STALLRQ0:1;       /*!< bit:      4  Stall 0 Request                    */
-    uint8_t  STALLRQ1:1;       /*!< bit:      5  Stall 1 Request                    */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  :4;               /*!< bit:  0.. 3  Reserved                           */
-    uint8_t  STALLRQ:2;        /*!< bit:  4.. 5  Stall x Request                    */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPSTATUS_OFFSET  0x106        /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
-#define USB_DEVICE_EPSTATUS_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
-
-#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
-#define USB_DEVICE_EPSTATUS_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
-#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1            /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
-#define USB_DEVICE_EPSTATUS_DTGLIN  (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
-#define USB_DEVICE_EPSTATUS_CURBK_Pos 2            /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
-#define USB_DEVICE_EPSTATUS_CURBK   (_U_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
-#define USB_DEVICE_EPSTATUS_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5            /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
-#define USB_DEVICE_EPSTATUS_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4            /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
-#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
-#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
-#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6            /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
-#define USB_DEVICE_EPSTATUS_BK0RDY  (_U_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
-#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7            /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
-#define USB_DEVICE_EPSTATUS_BK1RDY  (_U_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
-#define USB_DEVICE_EPSTATUS_MASK    _U_(0xF7)    /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
-
-/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/   8) HOST HOST_PIPE End Point Pipe Status -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  DTGL:1;           /*!< bit:      0  Data Toggle                        */
-    uint8_t  :1;               /*!< bit:      1  Reserved                           */
-    uint8_t  CURBK:1;          /*!< bit:      2  Current Bank                       */
-    uint8_t  :1;               /*!< bit:      3  Reserved                           */
-    uint8_t  PFREEZE:1;        /*!< bit:      4  Pipe Freeze                        */
-    uint8_t  :1;               /*!< bit:      5  Reserved                           */
-    uint8_t  BK0RDY:1;         /*!< bit:      6  Bank 0 ready                       */
-    uint8_t  BK1RDY:1;         /*!< bit:      7  Bank 1 ready                       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PSTATUS_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PSTATUS_OFFSET     0x106        /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
-#define USB_HOST_PSTATUS_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
-
-#define USB_HOST_PSTATUS_DTGL_Pos   0            /**< \brief (USB_HOST_PSTATUS) Data Toggle */
-#define USB_HOST_PSTATUS_DTGL       (_U_(0x1) << USB_HOST_PSTATUS_DTGL_Pos)
-#define USB_HOST_PSTATUS_CURBK_Pos  2            /**< \brief (USB_HOST_PSTATUS) Current Bank */
-#define USB_HOST_PSTATUS_CURBK      (_U_(0x1) << USB_HOST_PSTATUS_CURBK_Pos)
-#define USB_HOST_PSTATUS_PFREEZE_Pos 4            /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
-#define USB_HOST_PSTATUS_PFREEZE    (_U_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos)
-#define USB_HOST_PSTATUS_BK0RDY_Pos 6            /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
-#define USB_HOST_PSTATUS_BK0RDY     (_U_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos)
-#define USB_HOST_PSTATUS_BK1RDY_Pos 7            /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
-#define USB_HOST_PSTATUS_BK1RDY     (_U_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos)
-#define USB_HOST_PSTATUS_MASK       _U_(0xD5)    /**< \brief (USB_HOST_PSTATUS) MASK Register */
-
-/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0                */
-    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1                */
-    __I uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0                       */
-    __I uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1                       */
-    __I uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup                     */
-    __I uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out                     */
-    __I uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out                     */
-    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x                */
-    __I uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x                       */
-    __I uint8_t  :1;               /*!< bit:      4  Reserved                           */
-    __I uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out                     */
-    __I uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTFLAG_OFFSET 0x107        /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
-#define USB_DEVICE_EPINTFLAG_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
-
-#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
-#define USB_DEVICE_EPINTFLAG_TRCPT0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
-#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
-#define USB_DEVICE_EPINTFLAG_TRCPT1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
-#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
-#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
-#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
-#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
-#define USB_DEVICE_EPINTFLAG_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
-#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
-#define USB_DEVICE_EPINTFLAG_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
-#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
-#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
-#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
-#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
-#define USB_DEVICE_EPINTFLAG_RXSTP  (_U_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
-#define USB_DEVICE_EPINTFLAG_STALL0 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL0_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
-#define USB_DEVICE_EPINTFLAG_STALL1 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL1_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
-#define USB_DEVICE_EPINTFLAG_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos)
-#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
-#define USB_DEVICE_EPINTFLAG_MASK   _U_(0x7F)    /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
-
-/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Flag */
-    __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Flag */
-    __I uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Flag          */
-    __I uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Flag          */
-    __I uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Flag     */
-    __I uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Flag               */
-    __I uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    __I uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Flag */
-    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PINTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTFLAG_OFFSET    0x107        /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
-#define USB_HOST_PINTFLAG_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
-
-#define USB_HOST_PINTFLAG_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRCPT0    (_U_(1) << USB_HOST_PINTFLAG_TRCPT0_Pos)
-#define USB_HOST_PINTFLAG_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRCPT1    (_U_(1) << USB_HOST_PINTFLAG_TRCPT1_Pos)
-#define USB_HOST_PINTFLAG_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos)
-#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
-#define USB_HOST_PINTFLAG_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
-#define USB_HOST_PINTFLAG_TRFAIL    (_U_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos)
-#define USB_HOST_PINTFLAG_PERR_Pos  3            /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
-#define USB_HOST_PINTFLAG_PERR      (_U_(0x1) << USB_HOST_PINTFLAG_PERR_Pos)
-#define USB_HOST_PINTFLAG_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTFLAG) Transmit  Setup Interrupt Flag */
-#define USB_HOST_PINTFLAG_TXSTP     (_U_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos)
-#define USB_HOST_PINTFLAG_STALL_Pos 5            /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
-#define USB_HOST_PINTFLAG_STALL     (_U_(0x1) << USB_HOST_PINTFLAG_STALL_Pos)
-#define USB_HOST_PINTFLAG_MASK      _U_(0x3F)    /**< \brief (USB_HOST_PINTFLAG) MASK Register */
-
-/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Disable */
-    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Disable */
-    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Disable     */
-    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Disable     */
-    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Disable   */
-    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/Out Interrupt Disable   */
-    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/Out Interrupt Disable   */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Disable */
-    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Disable     */
-    uint8_t  :1;               /*!< bit:      4  Reserved                           */
-    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/Out Interrupt Disable   */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTENCLR_OFFSET 0x108        /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
-#define USB_DEVICE_EPINTENCLR_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
-
-#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
-#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
-#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
-#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
-#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
-#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
-#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
-#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
-#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_STALL0 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL0_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_STALL1 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL1_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
-#define USB_DEVICE_EPINTENCLR_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos)
-#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
-#define USB_DEVICE_EPINTENCLR_MASK  _U_(0x7F)    /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
-
-/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Disable        */
-    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Disable        */
-    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Disable       */
-    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Disable       */
-    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit Setup Interrupt Disable   */
-    uint8_t  STALL:1;          /*!< bit:      5  Stall Inetrrupt Disable            */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Disable        */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PINTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTENCLR_OFFSET   0x108        /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
-#define USB_HOST_PINTENCLR_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
-
-#define USB_HOST_PINTENCLR_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
-#define USB_HOST_PINTENCLR_TRCPT0   (_U_(1) << USB_HOST_PINTENCLR_TRCPT0_Pos)
-#define USB_HOST_PINTENCLR_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
-#define USB_HOST_PINTENCLR_TRCPT1   (_U_(1) << USB_HOST_PINTENCLR_TRCPT1_Pos)
-#define USB_HOST_PINTENCLR_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
-#define USB_HOST_PINTENCLR_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos)
-#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
-#define USB_HOST_PINTENCLR_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
-#define USB_HOST_PINTENCLR_TRFAIL   (_U_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos)
-#define USB_HOST_PINTENCLR_PERR_Pos 3            /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
-#define USB_HOST_PINTENCLR_PERR     (_U_(0x1) << USB_HOST_PINTENCLR_PERR_Pos)
-#define USB_HOST_PINTENCLR_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
-#define USB_HOST_PINTENCLR_TXSTP    (_U_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos)
-#define USB_HOST_PINTENCLR_STALL_Pos 5            /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
-#define USB_HOST_PINTENCLR_STALL    (_U_(0x1) << USB_HOST_PINTENCLR_STALL_Pos)
-#define USB_HOST_PINTENCLR_MASK     _U_(0x3F)    /**< \brief (USB_HOST_PINTENCLR) MASK Register */
-
-/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
-    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
-    uint8_t  TRFAIL0:1;        /*!< bit:      2  Error Flow 0 Interrupt Enable      */
-    uint8_t  TRFAIL1:1;        /*!< bit:      3  Error Flow 1 Interrupt Enable      */
-    uint8_t  RXSTP:1;          /*!< bit:      4  Received Setup Interrupt Enable    */
-    uint8_t  STALL0:1;         /*!< bit:      5  Stall 0 In/out Interrupt enable    */
-    uint8_t  STALL1:1;         /*!< bit:      6  Stall 1 In/out Interrupt enable    */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
-    uint8_t  TRFAIL:2;         /*!< bit:  2.. 3  Error Flow x Interrupt Enable      */
-    uint8_t  :1;               /*!< bit:      4  Reserved                           */
-    uint8_t  STALL:2;          /*!< bit:  5.. 6  Stall x In/out Interrupt enable    */
-    uint8_t  :1;               /*!< bit:      7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_EPINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EPINTENSET_OFFSET 0x109        /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
-#define USB_DEVICE_EPINTENSET_RESETVALUE _U_(0x00)    /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
-
-#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
-#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
-#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0            /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos)
-#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
-#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
-#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
-#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2            /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
-#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
-#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4            /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
-#define USB_DEVICE_EPINTENSET_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos)
-#define USB_DEVICE_EPINTENSET_STALL0_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
-#define USB_DEVICE_EPINTENSET_STALL0 (_U_(1) << USB_DEVICE_EPINTENSET_STALL0_Pos)
-#define USB_DEVICE_EPINTENSET_STALL1_Pos 6            /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
-#define USB_DEVICE_EPINTENSET_STALL1 (_U_(1) << USB_DEVICE_EPINTENSET_STALL1_Pos)
-#define USB_DEVICE_EPINTENSET_STALL_Pos 5            /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
-#define USB_DEVICE_EPINTENSET_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos)
-#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
-#define USB_DEVICE_EPINTENSET_MASK  _U_(0x7F)    /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
-
-/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Enable */
-    uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Enable */
-    uint8_t  TRFAIL:1;         /*!< bit:      2  Error Flow Interrupt Enable        */
-    uint8_t  PERR:1;           /*!< bit:      3  Pipe Error Interrupt Enable        */
-    uint8_t  TXSTP:1;          /*!< bit:      4  Transmit  Setup Interrupt Enable   */
-    uint8_t  STALL:1;          /*!< bit:      5  Stall Interrupt Enable             */
-    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  struct {
-    uint8_t  TRCPT:2;          /*!< bit:  0.. 1  Transfer Complete x Interrupt Enable */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } vec;                       /*!< Structure used for vec  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_PINTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PINTENSET_OFFSET   0x109        /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
-#define USB_HOST_PINTENSET_RESETVALUE _U_(0x00)    /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
-
-#define USB_HOST_PINTENSET_TRCPT0_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
-#define USB_HOST_PINTENSET_TRCPT0   (_U_(1) << USB_HOST_PINTENSET_TRCPT0_Pos)
-#define USB_HOST_PINTENSET_TRCPT1_Pos 1            /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
-#define USB_HOST_PINTENSET_TRCPT1   (_U_(1) << USB_HOST_PINTENSET_TRCPT1_Pos)
-#define USB_HOST_PINTENSET_TRCPT_Pos 0            /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
-#define USB_HOST_PINTENSET_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos)
-#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
-#define USB_HOST_PINTENSET_TRFAIL_Pos 2            /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
-#define USB_HOST_PINTENSET_TRFAIL   (_U_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos)
-#define USB_HOST_PINTENSET_PERR_Pos 3            /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
-#define USB_HOST_PINTENSET_PERR     (_U_(0x1) << USB_HOST_PINTENSET_PERR_Pos)
-#define USB_HOST_PINTENSET_TXSTP_Pos 4            /**< \brief (USB_HOST_PINTENSET) Transmit  Setup Interrupt Enable */
-#define USB_HOST_PINTENSET_TXSTP    (_U_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos)
-#define USB_HOST_PINTENSET_STALL_Pos 5            /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
-#define USB_HOST_PINTENSET_STALL    (_U_(0x1) << USB_HOST_PINTENSET_STALL_Pos)
-#define USB_HOST_PINTENSET_MASK     _U_(0x3F)    /**< \brief (USB_HOST_PINTENSET) MASK Register */
-
-/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_ADDR_OFFSET      0x000        /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
-
-#define USB_DEVICE_ADDR_ADDR_Pos    0            /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
-#define USB_DEVICE_ADDR_ADDR_Msk    (_U_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos)
-#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
-#define USB_DEVICE_ADDR_MASK        _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_ADDR) MASK Register */
-
-/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t ADDR:32;          /*!< bit:  0..31  Adress of data buffer              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_HOST_ADDR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_ADDR_OFFSET        0x000        /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
-
-#define USB_HOST_ADDR_ADDR_Pos      0            /**< \brief (USB_HOST_ADDR) Adress of data buffer */
-#define USB_HOST_ADDR_ADDR_Msk      (_U_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos)
-#define USB_HOST_ADDR_ADDR(value)   (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
-#define USB_HOST_ADDR_MASK          _U_(0xFFFFFFFF) /**< \brief (USB_HOST_ADDR) MASK Register */
-
-/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
-    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
-    uint32_t SIZE:3;           /*!< bit: 28..30  Enpoint size                       */
-    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_PCKSIZE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_PCKSIZE_OFFSET   0x004        /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
-
-#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
-#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
-#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
-#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
-#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
-#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
-#define USB_DEVICE_PCKSIZE_SIZE_Pos 28           /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
-#define USB_DEVICE_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos)
-#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
-#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
-#define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
-#define USB_DEVICE_PCKSIZE_MASK     _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
-
-/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t BYTE_COUNT:14;    /*!< bit:  0..13  Byte Count                         */
-    uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27  Multi Packet In or Out size        */
-    uint32_t SIZE:3;           /*!< bit: 28..30  Pipe size                          */
-    uint32_t AUTO_ZLP:1;       /*!< bit:     31  Automatic Zero Length Packet       */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} USB_HOST_PCKSIZE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_PCKSIZE_OFFSET     0x004        /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
-
-#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0            /**< \brief (USB_HOST_PCKSIZE) Byte Count */
-#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
-#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
-#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14           /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
-#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
-#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
-#define USB_HOST_PCKSIZE_SIZE_Pos   28           /**< \brief (USB_HOST_PCKSIZE) Pipe size */
-#define USB_HOST_PCKSIZE_SIZE_Msk   (_U_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos)
-#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
-#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31           /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
-#define USB_HOST_PCKSIZE_AUTO_ZLP   (_U_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
-#define USB_HOST_PCKSIZE_MASK       _U_(0xFFFFFFFF) /**< \brief (USB_HOST_PCKSIZE) MASK Register */
-
-/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
-    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_DEVICE_EXTREG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_EXTREG_OFFSET    0x008        /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
-
-#define USB_DEVICE_EXTREG_SUBPID_Pos 0            /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
-#define USB_DEVICE_EXTREG_SUBPID_Msk (_U_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos)
-#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
-#define USB_DEVICE_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
-#define USB_DEVICE_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos)
-#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
-#define USB_DEVICE_EXTREG_MASK      _U_(0x7FFF)  /**< \brief (USB_DEVICE_EXTREG) MASK Register */
-
-/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t SUBPID:4;         /*!< bit:  0.. 3  SUBPID field send with extended token */
-    uint16_t VARIABLE:11;      /*!< bit:  4..14  Variable field send with extended token */
-    uint16_t :1;               /*!< bit:     15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_EXTREG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_EXTREG_OFFSET      0x008        /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
-
-#define USB_HOST_EXTREG_SUBPID_Pos  0            /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
-#define USB_HOST_EXTREG_SUBPID_Msk  (_U_(0xF) << USB_HOST_EXTREG_SUBPID_Pos)
-#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
-#define USB_HOST_EXTREG_VARIABLE_Pos 4            /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
-#define USB_HOST_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos)
-#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
-#define USB_HOST_EXTREG_MASK        _U_(0x7FFF)  /**< \brief (USB_HOST_EXTREG) MASK Register */
-
-/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W  8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
-    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_DEVICE_STATUS_BK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_DEVICE_STATUS_BK_OFFSET 0x00A        /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
-
-#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
-#define USB_DEVICE_STATUS_BK_CRCERR (_U_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos)
-#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
-#define USB_DEVICE_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
-#define USB_DEVICE_STATUS_BK_MASK   _U_(0x03)    /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
-
-/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W  8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CRCERR:1;         /*!< bit:      0  CRC Error Status                   */
-    uint8_t  ERRORFLOW:1;      /*!< bit:      1  Error Flow Status                  */
-    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} USB_HOST_STATUS_BK_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_STATUS_BK_OFFSET   0x00A        /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
-
-#define USB_HOST_STATUS_BK_CRCERR_Pos 0            /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
-#define USB_HOST_STATUS_BK_CRCERR   (_U_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos)
-#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1            /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
-#define USB_HOST_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
-#define USB_HOST_STATUS_BK_MASK     _U_(0x03)    /**< \brief (USB_HOST_STATUS_BK) MASK Register */
-
-/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t PDADDR:7;         /*!< bit:  0.. 6  Pipe Device Adress                 */
-    uint16_t :1;               /*!< bit:      7  Reserved                           */
-    uint16_t PEPNUM:4;         /*!< bit:  8..11  Pipe Endpoint Number               */
-    uint16_t PERMAX:4;         /*!< bit: 12..15  Pipe Error Max Number              */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_CTRL_PIPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_CTRL_PIPE_OFFSET   0x00C        /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
-#define USB_HOST_CTRL_PIPE_RESETVALUE _U_(0x0000)  /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
-
-#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
-#define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos)
-#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
-#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8            /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
-#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
-#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
-#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12           /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
-#define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos)
-#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
-#define USB_HOST_CTRL_PIPE_MASK     _U_(0xFF7F)  /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
-
-/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint16_t DTGLER:1;         /*!< bit:      0  Data Toggle Error                  */
-    uint16_t DAPIDER:1;        /*!< bit:      1  Data PID Error                     */
-    uint16_t PIDER:1;          /*!< bit:      2  PID Error                          */
-    uint16_t TOUTER:1;         /*!< bit:      3  Time Out Error                     */
-    uint16_t CRC16ER:1;        /*!< bit:      4  CRC16 Error                        */
-    uint16_t ERCNT:3;          /*!< bit:  5.. 7  Pipe Error Count                   */
-    uint16_t :8;               /*!< bit:  8..15  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint16_t reg;                /*!< Type      used for register access              */
-} USB_HOST_STATUS_PIPE_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define USB_HOST_STATUS_PIPE_OFFSET 0x00E        /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
-
-#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0            /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
-#define USB_HOST_STATUS_PIPE_DTGLER (_U_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos)
-#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1            /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
-#define USB_HOST_STATUS_PIPE_DAPIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
-#define USB_HOST_STATUS_PIPE_PIDER_Pos 2            /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
-#define USB_HOST_STATUS_PIPE_PIDER  (_U_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos)
-#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3            /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
-#define USB_HOST_STATUS_PIPE_TOUTER (_U_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos)
-#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4            /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
-#define USB_HOST_STATUS_PIPE_CRC16ER (_U_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
-#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5            /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
-#define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos)
-#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
-#define USB_HOST_STATUS_PIPE_MASK   _U_(0x00FF)  /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
-
-/** \brief UsbDeviceDescBank SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO USB_DEVICE_ADDR_Type      ADDR;        /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
-  __IO USB_DEVICE_PCKSIZE_Type   PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
-  __IO USB_DEVICE_EXTREG_Type    EXTREG;      /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
-  __IO USB_DEVICE_STATUS_BK_Type STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
-       RoReg8                    Reserved1[0x5];
-} UsbDeviceDescBank;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief UsbHostDescBank SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO USB_HOST_ADDR_Type        ADDR;        /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
-  __IO USB_HOST_PCKSIZE_Type     PCKSIZE;     /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
-  __IO USB_HOST_EXTREG_Type      EXTREG;      /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
-  __IO USB_HOST_STATUS_BK_Type   STATUS_BK;   /**< \brief Offset: 0x00A (R/W  8) HOST_DESC_BANK Host Bank, Status of Bank */
-       RoReg8                    Reserved1[0x1];
-  __IO USB_HOST_CTRL_PIPE_Type   CTRL_PIPE;   /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
-  __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
-} UsbHostDescBank;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief UsbDeviceEndpoint hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO USB_DEVICE_EPCFG_Type     EPCFG;       /**< \brief Offset: 0x000 (R/W  8) DEVICE_ENDPOINT End Point Configuration */
-       RoReg8                    Reserved1[0x3];
-  __O  USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Clear */
-  __O  USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W  8) DEVICE_ENDPOINT End Point Pipe Status Set */
-  __I  USB_DEVICE_EPSTATUS_Type  EPSTATUS;    /**< \brief Offset: 0x006 (R/   8) DEVICE_ENDPOINT End Point Pipe Status */
-  __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG;   /**< \brief Offset: 0x007 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Flag */
-  __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR;  /**< \brief Offset: 0x008 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
-  __IO USB_DEVICE_EPINTENSET_Type EPINTENSET;  /**< \brief Offset: 0x009 (R/W  8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
-       RoReg8                    Reserved2[0x16];
-} UsbDeviceEndpoint;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief UsbHostPipe hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO USB_HOST_PCFG_Type        PCFG;        /**< \brief Offset: 0x000 (R/W  8) HOST_PIPE End Point Configuration */
-       RoReg8                    Reserved1[0x2];
-  __IO USB_HOST_BINTERVAL_Type   BINTERVAL;   /**< \brief Offset: 0x003 (R/W  8) HOST_PIPE Bus Access Period of Pipe */
-  __O  USB_HOST_PSTATUSCLR_Type  PSTATUSCLR;  /**< \brief Offset: 0x004 ( /W  8) HOST_PIPE End Point Pipe Status Clear */
-  __O  USB_HOST_PSTATUSSET_Type  PSTATUSSET;  /**< \brief Offset: 0x005 ( /W  8) HOST_PIPE End Point Pipe Status Set */
-  __I  USB_HOST_PSTATUS_Type     PSTATUS;     /**< \brief Offset: 0x006 (R/   8) HOST_PIPE End Point Pipe Status */
-  __IO USB_HOST_PINTFLAG_Type    PINTFLAG;    /**< \brief Offset: 0x007 (R/W  8) HOST_PIPE Pipe Interrupt Flag */
-  __IO USB_HOST_PINTENCLR_Type   PINTENCLR;   /**< \brief Offset: 0x008 (R/W  8) HOST_PIPE Pipe Interrupt Flag Clear */
-  __IO USB_HOST_PINTENSET_Type   PINTENSET;   /**< \brief Offset: 0x009 (R/W  8) HOST_PIPE Pipe Interrupt Flag Set */
-       RoReg8                    Reserved2[0x16];
-} UsbHostPipe;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_DEVICE APB hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Device */
-  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
-       RoReg8                    Reserved1[0x1];
-  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
-  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
-       RoReg8                    Reserved2[0x4];
-  __IO USB_DEVICE_CTRLB_Type     CTRLB;       /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
-  __IO USB_DEVICE_DADD_Type      DADD;        /**< \brief Offset: 0x00A (R/W  8) DEVICE Device Address */
-       RoReg8                    Reserved3[0x1];
-  __I  USB_DEVICE_STATUS_Type    STATUS;      /**< \brief Offset: 0x00C (R/   8) DEVICE Status */
-  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
-       RoReg8                    Reserved4[0x2];
-  __I  USB_DEVICE_FNUM_Type      FNUM;        /**< \brief Offset: 0x010 (R/  16) DEVICE Device Frame Number */
-       RoReg8                    Reserved5[0x2];
-  __IO USB_DEVICE_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
-       RoReg8                    Reserved6[0x2];
-  __IO USB_DEVICE_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
-       RoReg8                    Reserved7[0x2];
-  __IO USB_DEVICE_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
-       RoReg8                    Reserved8[0x2];
-  __I  USB_DEVICE_EPINTSMRY_Type EPINTSMRY;   /**< \brief Offset: 0x020 (R/  16) DEVICE End Point Interrupt Summary */
-       RoReg8                    Reserved9[0x2];
-  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
-  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
-       RoReg8                    Reserved10[0xD6];
-       UsbDeviceEndpoint         DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
-} UsbDevice;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_HOST hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Host */
-  __IO USB_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x000 (R/W  8) Control A */
-       RoReg8                    Reserved1[0x1];
-  __I  USB_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x002 (R/   8) Synchronization Busy */
-  __IO USB_QOSCTRL_Type          QOSCTRL;     /**< \brief Offset: 0x003 (R/W  8) USB Quality Of Service */
-       RoReg8                    Reserved2[0x4];
-  __IO USB_HOST_CTRLB_Type       CTRLB;       /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
-  __IO USB_HOST_HSOFC_Type       HSOFC;       /**< \brief Offset: 0x00A (R/W  8) HOST Host Start Of Frame Control */
-       RoReg8                    Reserved3[0x1];
-  __IO USB_HOST_STATUS_Type      STATUS;      /**< \brief Offset: 0x00C (R/W  8) HOST Status */
-  __I  USB_FSMSTATUS_Type        FSMSTATUS;   /**< \brief Offset: 0x00D (R/   8) Finite State Machine Status */
-       RoReg8                    Reserved4[0x2];
-  __IO USB_HOST_FNUM_Type        FNUM;        /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
-  __I  USB_HOST_FLENHIGH_Type    FLENHIGH;    /**< \brief Offset: 0x012 (R/   8) HOST Host Frame Length */
-       RoReg8                    Reserved5[0x1];
-  __IO USB_HOST_INTENCLR_Type    INTENCLR;    /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
-       RoReg8                    Reserved6[0x2];
-  __IO USB_HOST_INTENSET_Type    INTENSET;    /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
-       RoReg8                    Reserved7[0x2];
-  __IO USB_HOST_INTFLAG_Type     INTFLAG;     /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
-       RoReg8                    Reserved8[0x2];
-  __I  USB_HOST_PINTSMRY_Type    PINTSMRY;    /**< \brief Offset: 0x020 (R/  16) HOST Pipe Interrupt Summary */
-       RoReg8                    Reserved9[0x2];
-  __IO USB_DESCADD_Type          DESCADD;     /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
-  __IO USB_PADCAL_Type           PADCAL;      /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
-       RoReg8                    Reserved10[0xD6];
-       UsbHostPipe               HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [PIPE_NUM*HOST_IMPLEMENTED] */
-} UsbHost;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_DEVICE Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Device */
-       UsbDeviceDescBank         DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
-} UsbDeviceDescriptor;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/** \brief USB_HOST Descriptor SRAM registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct { /* USB is Host */
-       UsbHostDescBank           HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
-} UsbHostDescriptor;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define SECTION_USB_DESCRIPTOR
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-       UsbDevice                 DEVICE;      /**< \brief Offset: 0x000 USB is Device */
-       UsbHost                   HOST;        /**< \brief Offset: 0x000 USB is Host */
-} Usb;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_USB_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/wdt.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/wdt.h
deleted file mode 100644
index ce1947dcca..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/wdt.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/**
- * \file
- *
- * \brief Component description for WDT
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_WDT_COMPONENT_
-#define _SAMD51_WDT_COMPONENT_
-
-/* ========================================================================== */
-/**  SOFTWARE API DEFINITION FOR WDT */
-/* ========================================================================== */
-/** \addtogroup SAMD51_WDT Watchdog Timer */
-/*@{*/
-
-#define WDT_U2251
-#define REV_WDT                     0x110
-
-/* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W  8) Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  :1;               /*!< bit:      0  Reserved                           */
-    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
-    uint8_t  WEN:1;            /*!< bit:      2  Watchdog Timer Window Mode Enable  */
-    uint8_t  :4;               /*!< bit:  3.. 6  Reserved                           */
-    uint8_t  ALWAYSON:1;       /*!< bit:      7  Always-On                          */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_CTRLA_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_CTRLA_OFFSET            0x0          /**< \brief (WDT_CTRLA offset) Control */
-#define WDT_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (WDT_CTRLA reset_value) Control */
-
-#define WDT_CTRLA_ENABLE_Pos        1            /**< \brief (WDT_CTRLA) Enable */
-#define WDT_CTRLA_ENABLE            (_U_(0x1) << WDT_CTRLA_ENABLE_Pos)
-#define WDT_CTRLA_WEN_Pos           2            /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */
-#define WDT_CTRLA_WEN               (_U_(0x1) << WDT_CTRLA_WEN_Pos)
-#define WDT_CTRLA_ALWAYSON_Pos      7            /**< \brief (WDT_CTRLA) Always-On */
-#define WDT_CTRLA_ALWAYSON          (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos)
-#define WDT_CTRLA_MASK              _U_(0x86)    /**< \brief (WDT_CTRLA) MASK Register */
-
-/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W  8) Configuration -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  PER:4;            /*!< bit:  0.. 3  Time-Out Period                    */
-    uint8_t  WINDOW:4;         /*!< bit:  4.. 7  Window Mode Time-Out Period        */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_CONFIG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_CONFIG_OFFSET           0x1          /**< \brief (WDT_CONFIG offset) Configuration */
-#define WDT_CONFIG_RESETVALUE       _U_(0xBB)    /**< \brief (WDT_CONFIG reset_value) Configuration */
-
-#define WDT_CONFIG_PER_Pos          0            /**< \brief (WDT_CONFIG) Time-Out Period */
-#define WDT_CONFIG_PER_Msk          (_U_(0xF) << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER(value)       (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
-#define   WDT_CONFIG_PER_CYC8_Val         _U_(0x0)   /**< \brief (WDT_CONFIG) 8 clock cycles */
-#define   WDT_CONFIG_PER_CYC16_Val        _U_(0x1)   /**< \brief (WDT_CONFIG) 16 clock cycles */
-#define   WDT_CONFIG_PER_CYC32_Val        _U_(0x2)   /**< \brief (WDT_CONFIG) 32 clock cycles */
-#define   WDT_CONFIG_PER_CYC64_Val        _U_(0x3)   /**< \brief (WDT_CONFIG) 64 clock cycles */
-#define   WDT_CONFIG_PER_CYC128_Val       _U_(0x4)   /**< \brief (WDT_CONFIG) 128 clock cycles */
-#define   WDT_CONFIG_PER_CYC256_Val       _U_(0x5)   /**< \brief (WDT_CONFIG) 256 clock cycles */
-#define   WDT_CONFIG_PER_CYC512_Val       _U_(0x6)   /**< \brief (WDT_CONFIG) 512 clock cycles */
-#define   WDT_CONFIG_PER_CYC1024_Val      _U_(0x7)   /**< \brief (WDT_CONFIG) 1024 clock cycles */
-#define   WDT_CONFIG_PER_CYC2048_Val      _U_(0x8)   /**< \brief (WDT_CONFIG) 2048 clock cycles */
-#define   WDT_CONFIG_PER_CYC4096_Val      _U_(0x9)   /**< \brief (WDT_CONFIG) 4096 clock cycles */
-#define   WDT_CONFIG_PER_CYC8192_Val      _U_(0xA)   /**< \brief (WDT_CONFIG) 8192 clock cycles */
-#define   WDT_CONFIG_PER_CYC16384_Val     _U_(0xB)   /**< \brief (WDT_CONFIG) 16384 clock cycles */
-#define WDT_CONFIG_PER_CYC8         (WDT_CONFIG_PER_CYC8_Val       << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC16        (WDT_CONFIG_PER_CYC16_Val      << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC32        (WDT_CONFIG_PER_CYC32_Val      << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC64        (WDT_CONFIG_PER_CYC64_Val      << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC128       (WDT_CONFIG_PER_CYC128_Val     << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC256       (WDT_CONFIG_PER_CYC256_Val     << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC512       (WDT_CONFIG_PER_CYC512_Val     << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC1024      (WDT_CONFIG_PER_CYC1024_Val    << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC2048      (WDT_CONFIG_PER_CYC2048_Val    << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC4096      (WDT_CONFIG_PER_CYC4096_Val    << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC8192      (WDT_CONFIG_PER_CYC8192_Val    << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_PER_CYC16384     (WDT_CONFIG_PER_CYC16384_Val   << WDT_CONFIG_PER_Pos)
-#define WDT_CONFIG_WINDOW_Pos       4            /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
-#define WDT_CONFIG_WINDOW_Msk       (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW(value)    (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
-#define   WDT_CONFIG_WINDOW_CYC8_Val      _U_(0x0)   /**< \brief (WDT_CONFIG) 8 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC16_Val     _U_(0x1)   /**< \brief (WDT_CONFIG) 16 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC32_Val     _U_(0x2)   /**< \brief (WDT_CONFIG) 32 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC64_Val     _U_(0x3)   /**< \brief (WDT_CONFIG) 64 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC128_Val    _U_(0x4)   /**< \brief (WDT_CONFIG) 128 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC256_Val    _U_(0x5)   /**< \brief (WDT_CONFIG) 256 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC512_Val    _U_(0x6)   /**< \brief (WDT_CONFIG) 512 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC1024_Val   _U_(0x7)   /**< \brief (WDT_CONFIG) 1024 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC2048_Val   _U_(0x8)   /**< \brief (WDT_CONFIG) 2048 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC4096_Val   _U_(0x9)   /**< \brief (WDT_CONFIG) 4096 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC8192_Val   _U_(0xA)   /**< \brief (WDT_CONFIG) 8192 clock cycles */
-#define   WDT_CONFIG_WINDOW_CYC16384_Val  _U_(0xB)   /**< \brief (WDT_CONFIG) 16384 clock cycles */
-#define WDT_CONFIG_WINDOW_CYC8      (WDT_CONFIG_WINDOW_CYC8_Val    << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC16     (WDT_CONFIG_WINDOW_CYC16_Val   << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC32     (WDT_CONFIG_WINDOW_CYC32_Val   << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC64     (WDT_CONFIG_WINDOW_CYC64_Val   << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC128    (WDT_CONFIG_WINDOW_CYC128_Val  << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC256    (WDT_CONFIG_WINDOW_CYC256_Val  << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC512    (WDT_CONFIG_WINDOW_CYC512_Val  << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC1024   (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC2048   (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC4096   (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC8192   (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_WINDOW_CYC16384  (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos)
-#define WDT_CONFIG_MASK             _U_(0xFF)    /**< \brief (WDT_CONFIG) MASK Register */
-
-/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W  8) Early Warning Interrupt Control -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EWOFFSET:4;       /*!< bit:  0.. 3  Early Warning Interrupt Time Offset */
-    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_EWCTRL_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_EWCTRL_OFFSET           0x2          /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
-#define WDT_EWCTRL_RESETVALUE       _U_(0x0B)    /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
-
-#define WDT_EWCTRL_EWOFFSET_Pos     0            /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
-#define WDT_EWCTRL_EWOFFSET_Msk     (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET(value)  (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
-#define   WDT_EWCTRL_EWOFFSET_CYC8_Val    _U_(0x0)   /**< \brief (WDT_EWCTRL) 8 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC16_Val   _U_(0x1)   /**< \brief (WDT_EWCTRL) 16 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC32_Val   _U_(0x2)   /**< \brief (WDT_EWCTRL) 32 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC64_Val   _U_(0x3)   /**< \brief (WDT_EWCTRL) 64 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC128_Val  _U_(0x4)   /**< \brief (WDT_EWCTRL) 128 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC256_Val  _U_(0x5)   /**< \brief (WDT_EWCTRL) 256 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC512_Val  _U_(0x6)   /**< \brief (WDT_EWCTRL) 512 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7)   /**< \brief (WDT_EWCTRL) 1024 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8)   /**< \brief (WDT_EWCTRL) 2048 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9)   /**< \brief (WDT_EWCTRL) 4096 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA)   /**< \brief (WDT_EWCTRL) 8192 clock cycles */
-#define   WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB)   /**< \brief (WDT_EWCTRL) 16384 clock cycles */
-#define WDT_EWCTRL_EWOFFSET_CYC8    (WDT_EWCTRL_EWOFFSET_CYC8_Val  << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC16   (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC32   (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC64   (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC128  (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC256  (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC512  (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos)
-#define WDT_EWCTRL_MASK             _U_(0x0F)    /**< \brief (WDT_EWCTRL) MASK Register */
-
-/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W  8) Interrupt Enable Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_INTENCLR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_INTENCLR_OFFSET         0x4          /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
-#define WDT_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
-
-#define WDT_INTENCLR_EW_Pos         0            /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
-#define WDT_INTENCLR_EW             (_U_(0x1) << WDT_INTENCLR_EW_Pos)
-#define WDT_INTENCLR_MASK           _U_(0x01)    /**< \brief (WDT_INTENCLR) MASK Register */
-
-/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W  8) Interrupt Enable Set -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  EW:1;             /*!< bit:      0  Early Warning Interrupt Enable     */
-    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_INTENSET_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_INTENSET_OFFSET         0x5          /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
-#define WDT_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
-
-#define WDT_INTENSET_EW_Pos         0            /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
-#define WDT_INTENSET_EW             (_U_(0x1) << WDT_INTENSET_EW_Pos)
-#define WDT_INTENSET_MASK           _U_(0x01)    /**< \brief (WDT_INTENSET) MASK Register */
-
-/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
-  struct {
-    __I uint8_t  EW:1;             /*!< bit:      0  Early Warning                      */
-    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_INTFLAG_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_INTFLAG_OFFSET          0x6          /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
-#define WDT_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
-
-#define WDT_INTFLAG_EW_Pos          0            /**< \brief (WDT_INTFLAG) Early Warning */
-#define WDT_INTFLAG_EW              (_U_(0x1) << WDT_INTFLAG_EW_Pos)
-#define WDT_INTFLAG_MASK            _U_(0x01)    /**< \brief (WDT_INTFLAG) MASK Register */
-
-/* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/  32) Synchronization Busy -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint32_t :1;               /*!< bit:      0  Reserved                           */
-    uint32_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
-    uint32_t WEN:1;            /*!< bit:      2  Window Enable Synchronization Busy */
-    uint32_t ALWAYSON:1;       /*!< bit:      3  Always-On Synchronization Busy     */
-    uint32_t CLEAR:1;          /*!< bit:      4  Clear Synchronization Busy         */
-    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint32_t reg;                /*!< Type      used for register access              */
-} WDT_SYNCBUSY_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_SYNCBUSY_OFFSET         0x8          /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */
-#define WDT_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */
-
-#define WDT_SYNCBUSY_ENABLE_Pos     1            /**< \brief (WDT_SYNCBUSY) Enable Synchronization Busy */
-#define WDT_SYNCBUSY_ENABLE         (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)
-#define WDT_SYNCBUSY_WEN_Pos        2            /**< \brief (WDT_SYNCBUSY) Window Enable Synchronization Busy */
-#define WDT_SYNCBUSY_WEN            (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos)
-#define WDT_SYNCBUSY_ALWAYSON_Pos   3            /**< \brief (WDT_SYNCBUSY) Always-On Synchronization Busy */
-#define WDT_SYNCBUSY_ALWAYSON       (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)
-#define WDT_SYNCBUSY_CLEAR_Pos      4            /**< \brief (WDT_SYNCBUSY) Clear Synchronization Busy */
-#define WDT_SYNCBUSY_CLEAR          (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)
-#define WDT_SYNCBUSY_MASK           _U_(0x0000001E) /**< \brief (WDT_SYNCBUSY) MASK Register */
-
-/* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W  8) Clear -------- */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union {
-  struct {
-    uint8_t  CLEAR:8;          /*!< bit:  0.. 7  Watchdog Clear                     */
-  } bit;                       /*!< Structure used for bit  access                  */
-  uint8_t reg;                 /*!< Type      used for register access              */
-} WDT_CLEAR_Type;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#define WDT_CLEAR_OFFSET            0xC          /**< \brief (WDT_CLEAR offset) Clear */
-#define WDT_CLEAR_RESETVALUE        _U_(0x00)    /**< \brief (WDT_CLEAR reset_value) Clear */
-
-#define WDT_CLEAR_CLEAR_Pos         0            /**< \brief (WDT_CLEAR) Watchdog Clear */
-#define WDT_CLEAR_CLEAR_Msk         (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
-#define WDT_CLEAR_CLEAR(value)      (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
-#define   WDT_CLEAR_CLEAR_KEY_Val         _U_(0xA5)   /**< \brief (WDT_CLEAR) Clear Key */
-#define WDT_CLEAR_CLEAR_KEY         (WDT_CLEAR_CLEAR_KEY_Val       << WDT_CLEAR_CLEAR_Pos)
-#define WDT_CLEAR_MASK              _U_(0xFF)    /**< \brief (WDT_CLEAR) MASK Register */
-
-/** \brief WDT hardware registers */
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef struct {
-  __IO WDT_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x0 (R/W  8) Control */
-  __IO WDT_CONFIG_Type           CONFIG;      /**< \brief Offset: 0x1 (R/W  8) Configuration */
-  __IO WDT_EWCTRL_Type           EWCTRL;      /**< \brief Offset: 0x2 (R/W  8) Early Warning Interrupt Control */
-       RoReg8                    Reserved1[0x1];
-  __IO WDT_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x4 (R/W  8) Interrupt Enable Clear */
-  __IO WDT_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x5 (R/W  8) Interrupt Enable Set */
-  __IO WDT_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x6 (R/W  8) Interrupt Flag Status and Clear */
-       RoReg8                    Reserved2[0x1];
-  __I  WDT_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x8 (R/  32) Synchronization Busy */
-  __O  WDT_CLEAR_Type            CLEAR;       /**< \brief Offset: 0xC ( /W  8) Clear */
-} Wdt;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/*@}*/
-
-#endif /* _SAMD51_WDT_COMPONENT_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/ac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/ac.h
deleted file mode 100644
index bc5bd05e91..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/ac.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for AC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_AC_INSTANCE_
-#define _SAMD51_AC_INSTANCE_
-
-/* ========== Register definition for AC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_AC_CTRLA               (0x42002000) /**< \brief (AC) Control A */
-#define REG_AC_CTRLB               (0x42002001) /**< \brief (AC) Control B */
-#define REG_AC_EVCTRL              (0x42002002) /**< \brief (AC) Event Control */
-#define REG_AC_INTENCLR            (0x42002004) /**< \brief (AC) Interrupt Enable Clear */
-#define REG_AC_INTENSET            (0x42002005) /**< \brief (AC) Interrupt Enable Set */
-#define REG_AC_INTFLAG             (0x42002006) /**< \brief (AC) Interrupt Flag Status and Clear */
-#define REG_AC_STATUSA             (0x42002007) /**< \brief (AC) Status A */
-#define REG_AC_STATUSB             (0x42002008) /**< \brief (AC) Status B */
-#define REG_AC_DBGCTRL             (0x42002009) /**< \brief (AC) Debug Control */
-#define REG_AC_WINCTRL             (0x4200200A) /**< \brief (AC) Window Control */
-#define REG_AC_SCALER0             (0x4200200C) /**< \brief (AC) Scaler 0 */
-#define REG_AC_SCALER1             (0x4200200D) /**< \brief (AC) Scaler 1 */
-#define REG_AC_COMPCTRL0           (0x42002010) /**< \brief (AC) Comparator Control 0 */
-#define REG_AC_COMPCTRL1           (0x42002014) /**< \brief (AC) Comparator Control 1 */
-#define REG_AC_SYNCBUSY            (0x42002020) /**< \brief (AC) Synchronization Busy */
-#define REG_AC_CALIB               (0x42002024) /**< \brief (AC) Calibration */
-#else
-#define REG_AC_CTRLA               (*(RwReg8 *)0x42002000UL) /**< \brief (AC) Control A */
-#define REG_AC_CTRLB               (*(WoReg8 *)0x42002001UL) /**< \brief (AC) Control B */
-#define REG_AC_EVCTRL              (*(RwReg16*)0x42002002UL) /**< \brief (AC) Event Control */
-#define REG_AC_INTENCLR            (*(RwReg8 *)0x42002004UL) /**< \brief (AC) Interrupt Enable Clear */
-#define REG_AC_INTENSET            (*(RwReg8 *)0x42002005UL) /**< \brief (AC) Interrupt Enable Set */
-#define REG_AC_INTFLAG             (*(RwReg8 *)0x42002006UL) /**< \brief (AC) Interrupt Flag Status and Clear */
-#define REG_AC_STATUSA             (*(RoReg8 *)0x42002007UL) /**< \brief (AC) Status A */
-#define REG_AC_STATUSB             (*(RoReg8 *)0x42002008UL) /**< \brief (AC) Status B */
-#define REG_AC_DBGCTRL             (*(RwReg8 *)0x42002009UL) /**< \brief (AC) Debug Control */
-#define REG_AC_WINCTRL             (*(RwReg8 *)0x4200200AUL) /**< \brief (AC) Window Control */
-#define REG_AC_SCALER0             (*(RwReg8 *)0x4200200CUL) /**< \brief (AC) Scaler 0 */
-#define REG_AC_SCALER1             (*(RwReg8 *)0x4200200DUL) /**< \brief (AC) Scaler 1 */
-#define REG_AC_COMPCTRL0           (*(RwReg  *)0x42002010UL) /**< \brief (AC) Comparator Control 0 */
-#define REG_AC_COMPCTRL1           (*(RwReg  *)0x42002014UL) /**< \brief (AC) Comparator Control 1 */
-#define REG_AC_SYNCBUSY            (*(RoReg  *)0x42002020UL) /**< \brief (AC) Synchronization Busy */
-#define REG_AC_CALIB               (*(RwReg16*)0x42002024UL) /**< \brief (AC) Calibration */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for AC peripheral ========== */
-#define AC_COMPCTRL_MUXNEG_OPAMP    7        // OPAMP selection for MUXNEG
-#define AC_FUSES_BIAS1                       // PAIR1 Bias Calibration
-#define AC_GCLK_ID                  32       // Index of Generic Clock
-#define AC_IMPLEMENTS_VDBLR         0        // VDoubler implemented ?
-#define AC_NUM_CMP                  2        // Number of comparators
-#define AC_PAIRS                    1        // Number of pairs of comparators
-#define AC_SPEED_LEVELS             2        // Number of speed values
-
-#endif /* _SAMD51_AC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/adc0.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/adc0.h
deleted file mode 100644
index 6808fff9da..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/adc0.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for ADC0
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_ADC0_INSTANCE_
-#define _SAMD51_ADC0_INSTANCE_
-
-/* ========== Register definition for ADC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_ADC0_CTRLA             (0x43001C00) /**< \brief (ADC0) Control A */
-#define REG_ADC0_EVCTRL            (0x43001C02) /**< \brief (ADC0) Event Control */
-#define REG_ADC0_DBGCTRL           (0x43001C03) /**< \brief (ADC0) Debug Control */
-#define REG_ADC0_INPUTCTRL         (0x43001C04) /**< \brief (ADC0) Input Control */
-#define REG_ADC0_CTRLB             (0x43001C06) /**< \brief (ADC0) Control B */
-#define REG_ADC0_REFCTRL           (0x43001C08) /**< \brief (ADC0) Reference Control */
-#define REG_ADC0_AVGCTRL           (0x43001C0A) /**< \brief (ADC0) Average Control */
-#define REG_ADC0_SAMPCTRL          (0x43001C0B) /**< \brief (ADC0) Sample Time Control */
-#define REG_ADC0_WINLT             (0x43001C0C) /**< \brief (ADC0) Window Monitor Lower Threshold */
-#define REG_ADC0_WINUT             (0x43001C0E) /**< \brief (ADC0) Window Monitor Upper Threshold */
-#define REG_ADC0_GAINCORR          (0x43001C10) /**< \brief (ADC0) Gain Correction */
-#define REG_ADC0_OFFSETCORR        (0x43001C12) /**< \brief (ADC0) Offset Correction */
-#define REG_ADC0_SWTRIG            (0x43001C14) /**< \brief (ADC0) Software Trigger */
-#define REG_ADC0_INTENCLR          (0x43001C2C) /**< \brief (ADC0) Interrupt Enable Clear */
-#define REG_ADC0_INTENSET          (0x43001C2D) /**< \brief (ADC0) Interrupt Enable Set */
-#define REG_ADC0_INTFLAG           (0x43001C2E) /**< \brief (ADC0) Interrupt Flag Status and Clear */
-#define REG_ADC0_STATUS            (0x43001C2F) /**< \brief (ADC0) Status */
-#define REG_ADC0_SYNCBUSY          (0x43001C30) /**< \brief (ADC0) Synchronization Busy */
-#define REG_ADC0_DSEQDATA          (0x43001C34) /**< \brief (ADC0) DMA Sequencial Data */
-#define REG_ADC0_DSEQCTRL          (0x43001C38) /**< \brief (ADC0) DMA Sequential Control */
-#define REG_ADC0_DSEQSTAT          (0x43001C3C) /**< \brief (ADC0) DMA Sequencial Status */
-#define REG_ADC0_RESULT            (0x43001C40) /**< \brief (ADC0) Result Conversion Value */
-#define REG_ADC0_RESS              (0x43001C44) /**< \brief (ADC0) Last Sample Result */
-#define REG_ADC0_CALIB             (0x43001C48) /**< \brief (ADC0) Calibration */
-#else
-#define REG_ADC0_CTRLA             (*(RwReg16*)0x43001C00UL) /**< \brief (ADC0) Control A */
-#define REG_ADC0_EVCTRL            (*(RwReg8 *)0x43001C02UL) /**< \brief (ADC0) Event Control */
-#define REG_ADC0_DBGCTRL           (*(RwReg8 *)0x43001C03UL) /**< \brief (ADC0) Debug Control */
-#define REG_ADC0_INPUTCTRL         (*(RwReg16*)0x43001C04UL) /**< \brief (ADC0) Input Control */
-#define REG_ADC0_CTRLB             (*(RwReg16*)0x43001C06UL) /**< \brief (ADC0) Control B */
-#define REG_ADC0_REFCTRL           (*(RwReg8 *)0x43001C08UL) /**< \brief (ADC0) Reference Control */
-#define REG_ADC0_AVGCTRL           (*(RwReg8 *)0x43001C0AUL) /**< \brief (ADC0) Average Control */
-#define REG_ADC0_SAMPCTRL          (*(RwReg8 *)0x43001C0BUL) /**< \brief (ADC0) Sample Time Control */
-#define REG_ADC0_WINLT             (*(RwReg16*)0x43001C0CUL) /**< \brief (ADC0) Window Monitor Lower Threshold */
-#define REG_ADC0_WINUT             (*(RwReg16*)0x43001C0EUL) /**< \brief (ADC0) Window Monitor Upper Threshold */
-#define REG_ADC0_GAINCORR          (*(RwReg16*)0x43001C10UL) /**< \brief (ADC0) Gain Correction */
-#define REG_ADC0_OFFSETCORR        (*(RwReg16*)0x43001C12UL) /**< \brief (ADC0) Offset Correction */
-#define REG_ADC0_SWTRIG            (*(RwReg8 *)0x43001C14UL) /**< \brief (ADC0) Software Trigger */
-#define REG_ADC0_INTENCLR          (*(RwReg8 *)0x43001C2CUL) /**< \brief (ADC0) Interrupt Enable Clear */
-#define REG_ADC0_INTENSET          (*(RwReg8 *)0x43001C2DUL) /**< \brief (ADC0) Interrupt Enable Set */
-#define REG_ADC0_INTFLAG           (*(RwReg8 *)0x43001C2EUL) /**< \brief (ADC0) Interrupt Flag Status and Clear */
-#define REG_ADC0_STATUS            (*(RoReg8 *)0x43001C2FUL) /**< \brief (ADC0) Status */
-#define REG_ADC0_SYNCBUSY          (*(RoReg  *)0x43001C30UL) /**< \brief (ADC0) Synchronization Busy */
-#define REG_ADC0_DSEQDATA          (*(WoReg  *)0x43001C34UL) /**< \brief (ADC0) DMA Sequencial Data */
-#define REG_ADC0_DSEQCTRL          (*(RwReg  *)0x43001C38UL) /**< \brief (ADC0) DMA Sequential Control */
-#define REG_ADC0_DSEQSTAT          (*(RoReg  *)0x43001C3CUL) /**< \brief (ADC0) DMA Sequencial Status */
-#define REG_ADC0_RESULT            (*(RoReg16*)0x43001C40UL) /**< \brief (ADC0) Result Conversion Value */
-#define REG_ADC0_RESS              (*(RoReg16*)0x43001C44UL) /**< \brief (ADC0) Last Sample Result */
-#define REG_ADC0_CALIB             (*(RwReg16*)0x43001C48UL) /**< \brief (ADC0) Calibration */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for ADC0 peripheral ========== */
-#define ADC0_BANDGAP                27       // MUXPOS value to select BANDGAP
-#define ADC0_CTAT                   29       // MUXPOS value to select CTAT
-#define ADC0_DMAC_ID_RESRDY         68       // index of DMA RESRDY trigger
-#define ADC0_DMAC_ID_SEQ            69       // Index of DMA SEQ trigger
-#define ADC0_EXTCHANNEL_MSB         15       // Number of external channels
-#define ADC0_GCLK_ID                40       // index of Generic Clock
-#define ADC0_MASTER_SLAVE_MODE      1        // ADC Master/Slave Mode
-#define ADC0_OPAMP2                 0        // MUXPOS value to select OPAMP2
-#define ADC0_OPAMP01                0        // MUXPOS value to select OPAMP01
-#define ADC0_PTAT                   28       // MUXPOS value to select PTAT
-#define ADC0_TOUCH_IMPLEMENTED      1        // TOUCH implemented or not
-
-#endif /* _SAMD51_ADC0_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/adc1.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/adc1.h
deleted file mode 100644
index af572c0560..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/adc1.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for ADC1
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_ADC1_INSTANCE_
-#define _SAMD51_ADC1_INSTANCE_
-
-/* ========== Register definition for ADC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_ADC1_CTRLA             (0x43002000) /**< \brief (ADC1) Control A */
-#define REG_ADC1_EVCTRL            (0x43002002) /**< \brief (ADC1) Event Control */
-#define REG_ADC1_DBGCTRL           (0x43002003) /**< \brief (ADC1) Debug Control */
-#define REG_ADC1_INPUTCTRL         (0x43002004) /**< \brief (ADC1) Input Control */
-#define REG_ADC1_CTRLB             (0x43002006) /**< \brief (ADC1) Control B */
-#define REG_ADC1_REFCTRL           (0x43002008) /**< \brief (ADC1) Reference Control */
-#define REG_ADC1_AVGCTRL           (0x4300200A) /**< \brief (ADC1) Average Control */
-#define REG_ADC1_SAMPCTRL          (0x4300200B) /**< \brief (ADC1) Sample Time Control */
-#define REG_ADC1_WINLT             (0x4300200C) /**< \brief (ADC1) Window Monitor Lower Threshold */
-#define REG_ADC1_WINUT             (0x4300200E) /**< \brief (ADC1) Window Monitor Upper Threshold */
-#define REG_ADC1_GAINCORR          (0x43002010) /**< \brief (ADC1) Gain Correction */
-#define REG_ADC1_OFFSETCORR        (0x43002012) /**< \brief (ADC1) Offset Correction */
-#define REG_ADC1_SWTRIG            (0x43002014) /**< \brief (ADC1) Software Trigger */
-#define REG_ADC1_INTENCLR          (0x4300202C) /**< \brief (ADC1) Interrupt Enable Clear */
-#define REG_ADC1_INTENSET          (0x4300202D) /**< \brief (ADC1) Interrupt Enable Set */
-#define REG_ADC1_INTFLAG           (0x4300202E) /**< \brief (ADC1) Interrupt Flag Status and Clear */
-#define REG_ADC1_STATUS            (0x4300202F) /**< \brief (ADC1) Status */
-#define REG_ADC1_SYNCBUSY          (0x43002030) /**< \brief (ADC1) Synchronization Busy */
-#define REG_ADC1_DSEQDATA          (0x43002034) /**< \brief (ADC1) DMA Sequencial Data */
-#define REG_ADC1_DSEQCTRL          (0x43002038) /**< \brief (ADC1) DMA Sequential Control */
-#define REG_ADC1_DSEQSTAT          (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */
-#define REG_ADC1_RESULT            (0x43002040) /**< \brief (ADC1) Result Conversion Value */
-#define REG_ADC1_RESS              (0x43002044) /**< \brief (ADC1) Last Sample Result */
-#define REG_ADC1_CALIB             (0x43002048) /**< \brief (ADC1) Calibration */
-#else
-#define REG_ADC1_CTRLA             (*(RwReg16*)0x43002000UL) /**< \brief (ADC1) Control A */
-#define REG_ADC1_EVCTRL            (*(RwReg8 *)0x43002002UL) /**< \brief (ADC1) Event Control */
-#define REG_ADC1_DBGCTRL           (*(RwReg8 *)0x43002003UL) /**< \brief (ADC1) Debug Control */
-#define REG_ADC1_INPUTCTRL         (*(RwReg16*)0x43002004UL) /**< \brief (ADC1) Input Control */
-#define REG_ADC1_CTRLB             (*(RwReg16*)0x43002006UL) /**< \brief (ADC1) Control B */
-#define REG_ADC1_REFCTRL           (*(RwReg8 *)0x43002008UL) /**< \brief (ADC1) Reference Control */
-#define REG_ADC1_AVGCTRL           (*(RwReg8 *)0x4300200AUL) /**< \brief (ADC1) Average Control */
-#define REG_ADC1_SAMPCTRL          (*(RwReg8 *)0x4300200BUL) /**< \brief (ADC1) Sample Time Control */
-#define REG_ADC1_WINLT             (*(RwReg16*)0x4300200CUL) /**< \brief (ADC1) Window Monitor Lower Threshold */
-#define REG_ADC1_WINUT             (*(RwReg16*)0x4300200EUL) /**< \brief (ADC1) Window Monitor Upper Threshold */
-#define REG_ADC1_GAINCORR          (*(RwReg16*)0x43002010UL) /**< \brief (ADC1) Gain Correction */
-#define REG_ADC1_OFFSETCORR        (*(RwReg16*)0x43002012UL) /**< \brief (ADC1) Offset Correction */
-#define REG_ADC1_SWTRIG            (*(RwReg8 *)0x43002014UL) /**< \brief (ADC1) Software Trigger */
-#define REG_ADC1_INTENCLR          (*(RwReg8 *)0x4300202CUL) /**< \brief (ADC1) Interrupt Enable Clear */
-#define REG_ADC1_INTENSET          (*(RwReg8 *)0x4300202DUL) /**< \brief (ADC1) Interrupt Enable Set */
-#define REG_ADC1_INTFLAG           (*(RwReg8 *)0x4300202EUL) /**< \brief (ADC1) Interrupt Flag Status and Clear */
-#define REG_ADC1_STATUS            (*(RoReg8 *)0x4300202FUL) /**< \brief (ADC1) Status */
-#define REG_ADC1_SYNCBUSY          (*(RoReg  *)0x43002030UL) /**< \brief (ADC1) Synchronization Busy */
-#define REG_ADC1_DSEQDATA          (*(WoReg  *)0x43002034UL) /**< \brief (ADC1) DMA Sequencial Data */
-#define REG_ADC1_DSEQCTRL          (*(RwReg  *)0x43002038UL) /**< \brief (ADC1) DMA Sequential Control */
-#define REG_ADC1_DSEQSTAT          (*(RoReg  *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Status */
-#define REG_ADC1_RESULT            (*(RoReg16*)0x43002040UL) /**< \brief (ADC1) Result Conversion Value */
-#define REG_ADC1_RESS              (*(RoReg16*)0x43002044UL) /**< \brief (ADC1) Last Sample Result */
-#define REG_ADC1_CALIB             (*(RwReg16*)0x43002048UL) /**< \brief (ADC1) Calibration */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for ADC1 peripheral ========== */
-#define ADC1_BANDGAP                27       // MUXPOS value to select BANDGAP
-#define ADC1_CTAT                   29       // MUXPOS value to select CTAT
-#define ADC1_DMAC_ID_RESRDY         70       // Index of DMA RESRDY trigger
-#define ADC1_DMAC_ID_SEQ            71       // Index of DMA SEQ trigger
-#define ADC1_EXTCHANNEL_MSB         15       // Number of external channels
-#define ADC1_GCLK_ID                41       // Index of Generic Clock
-#define ADC1_MASTER_SLAVE_MODE      2        // ADC Master/Slave Mode
-#define ADC1_OPAMP2                 0        // MUXPOS value to select OPAMP2
-#define ADC1_OPAMP01                0        // MUXPOS value to select OPAMP01
-#define ADC1_PTAT                   28       // MUXPOS value to select PTAT
-#define ADC1_TOUCH_IMPLEMENTED      0        // TOUCH implemented or not
-#define ADC1_TOUCH_LINES_NUM        1        // Number of touch lines
-
-#endif /* _SAMD51_ADC1_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/aes.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/aes.h
deleted file mode 100644
index 5ce5cb3373..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/aes.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for AES
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_AES_INSTANCE_
-#define _SAMD51_AES_INSTANCE_
-
-/* ========== Register definition for AES peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_AES_CTRLA              (0x42002400) /**< \brief (AES) Control A */
-#define REG_AES_CTRLB              (0x42002404) /**< \brief (AES) Control B */
-#define REG_AES_INTENCLR           (0x42002405) /**< \brief (AES) Interrupt Enable Clear */
-#define REG_AES_INTENSET           (0x42002406) /**< \brief (AES) Interrupt Enable Set */
-#define REG_AES_INTFLAG            (0x42002407) /**< \brief (AES) Interrupt Flag Status */
-#define REG_AES_DATABUFPTR         (0x42002408) /**< \brief (AES) Data buffer pointer */
-#define REG_AES_DBGCTRL            (0x42002409) /**< \brief (AES) Debug control */
-#define REG_AES_KEYWORD0           (0x4200240C) /**< \brief (AES) Keyword 0 */
-#define REG_AES_KEYWORD1           (0x42002410) /**< \brief (AES) Keyword 1 */
-#define REG_AES_KEYWORD2           (0x42002414) /**< \brief (AES) Keyword 2 */
-#define REG_AES_KEYWORD3           (0x42002418) /**< \brief (AES) Keyword 3 */
-#define REG_AES_KEYWORD4           (0x4200241C) /**< \brief (AES) Keyword 4 */
-#define REG_AES_KEYWORD5           (0x42002420) /**< \brief (AES) Keyword 5 */
-#define REG_AES_KEYWORD6           (0x42002424) /**< \brief (AES) Keyword 6 */
-#define REG_AES_KEYWORD7           (0x42002428) /**< \brief (AES) Keyword 7 */
-#define REG_AES_INDATA             (0x42002438) /**< \brief (AES) Indata */
-#define REG_AES_INTVECTV0          (0x4200243C) /**< \brief (AES) Initialisation Vector 0 */
-#define REG_AES_INTVECTV1          (0x42002440) /**< \brief (AES) Initialisation Vector 1 */
-#define REG_AES_INTVECTV2          (0x42002444) /**< \brief (AES) Initialisation Vector 2 */
-#define REG_AES_INTVECTV3          (0x42002448) /**< \brief (AES) Initialisation Vector 3 */
-#define REG_AES_HASHKEY0           (0x4200245C) /**< \brief (AES) Hash key 0 */
-#define REG_AES_HASHKEY1           (0x42002460) /**< \brief (AES) Hash key 1 */
-#define REG_AES_HASHKEY2           (0x42002464) /**< \brief (AES) Hash key 2 */
-#define REG_AES_HASHKEY3           (0x42002468) /**< \brief (AES) Hash key 3 */
-#define REG_AES_GHASH0             (0x4200246C) /**< \brief (AES) Galois Hash 0 */
-#define REG_AES_GHASH1             (0x42002470) /**< \brief (AES) Galois Hash 1 */
-#define REG_AES_GHASH2             (0x42002474) /**< \brief (AES) Galois Hash 2 */
-#define REG_AES_GHASH3             (0x42002478) /**< \brief (AES) Galois Hash 3 */
-#define REG_AES_CIPLEN             (0x42002480) /**< \brief (AES) Cipher Length */
-#define REG_AES_RANDSEED           (0x42002484) /**< \brief (AES) Random Seed */
-#else
-#define REG_AES_CTRLA              (*(RwReg  *)0x42002400UL) /**< \brief (AES) Control A */
-#define REG_AES_CTRLB              (*(RwReg8 *)0x42002404UL) /**< \brief (AES) Control B */
-#define REG_AES_INTENCLR           (*(RwReg8 *)0x42002405UL) /**< \brief (AES) Interrupt Enable Clear */
-#define REG_AES_INTENSET           (*(RwReg8 *)0x42002406UL) /**< \brief (AES) Interrupt Enable Set */
-#define REG_AES_INTFLAG            (*(RwReg8 *)0x42002407UL) /**< \brief (AES) Interrupt Flag Status */
-#define REG_AES_DATABUFPTR         (*(RwReg8 *)0x42002408UL) /**< \brief (AES) Data buffer pointer */
-#define REG_AES_DBGCTRL            (*(RwReg8 *)0x42002409UL) /**< \brief (AES) Debug control */
-#define REG_AES_KEYWORD0           (*(WoReg  *)0x4200240CUL) /**< \brief (AES) Keyword 0 */
-#define REG_AES_KEYWORD1           (*(WoReg  *)0x42002410UL) /**< \brief (AES) Keyword 1 */
-#define REG_AES_KEYWORD2           (*(WoReg  *)0x42002414UL) /**< \brief (AES) Keyword 2 */
-#define REG_AES_KEYWORD3           (*(WoReg  *)0x42002418UL) /**< \brief (AES) Keyword 3 */
-#define REG_AES_KEYWORD4           (*(WoReg  *)0x4200241CUL) /**< \brief (AES) Keyword 4 */
-#define REG_AES_KEYWORD5           (*(WoReg  *)0x42002420UL) /**< \brief (AES) Keyword 5 */
-#define REG_AES_KEYWORD6           (*(WoReg  *)0x42002424UL) /**< \brief (AES) Keyword 6 */
-#define REG_AES_KEYWORD7           (*(WoReg  *)0x42002428UL) /**< \brief (AES) Keyword 7 */
-#define REG_AES_INDATA             (*(RwReg  *)0x42002438UL) /**< \brief (AES) Indata */
-#define REG_AES_INTVECTV0          (*(WoReg  *)0x4200243CUL) /**< \brief (AES) Initialisation Vector 0 */
-#define REG_AES_INTVECTV1          (*(WoReg  *)0x42002440UL) /**< \brief (AES) Initialisation Vector 1 */
-#define REG_AES_INTVECTV2          (*(WoReg  *)0x42002444UL) /**< \brief (AES) Initialisation Vector 2 */
-#define REG_AES_INTVECTV3          (*(WoReg  *)0x42002448UL) /**< \brief (AES) Initialisation Vector 3 */
-#define REG_AES_HASHKEY0           (*(RwReg  *)0x4200245CUL) /**< \brief (AES) Hash key 0 */
-#define REG_AES_HASHKEY1           (*(RwReg  *)0x42002460UL) /**< \brief (AES) Hash key 1 */
-#define REG_AES_HASHKEY2           (*(RwReg  *)0x42002464UL) /**< \brief (AES) Hash key 2 */
-#define REG_AES_HASHKEY3           (*(RwReg  *)0x42002468UL) /**< \brief (AES) Hash key 3 */
-#define REG_AES_GHASH0             (*(RwReg  *)0x4200246CUL) /**< \brief (AES) Galois Hash 0 */
-#define REG_AES_GHASH1             (*(RwReg  *)0x42002470UL) /**< \brief (AES) Galois Hash 1 */
-#define REG_AES_GHASH2             (*(RwReg  *)0x42002474UL) /**< \brief (AES) Galois Hash 2 */
-#define REG_AES_GHASH3             (*(RwReg  *)0x42002478UL) /**< \brief (AES) Galois Hash 3 */
-#define REG_AES_CIPLEN             (*(RwReg  *)0x42002480UL) /**< \brief (AES) Cipher Length */
-#define REG_AES_RANDSEED           (*(RwReg  *)0x42002484UL) /**< \brief (AES) Random Seed */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for AES peripheral ========== */
-#define AES_DMAC_ID_RD              82       // DMA DATA Read trigger
-#define AES_DMAC_ID_WR              81       // DMA DATA Write trigger
-#define AES_FOUR_BYTE_OPERATION     1        // Byte Operation
-#define AES_GCM                     1        // GCM
-#define AES_KEYLEN                  2        // Key Length
-
-#endif /* _SAMD51_AES_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/can0.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/can0.h
deleted file mode 100644
index 6b78b33e34..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/can0.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for CAN0
- *
- * Copyright (c) 2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- *    Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CAN0_INSTANCE_
-#define _SAMD51_CAN0_INSTANCE_
-
-/* ========== Register definition for CAN0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_CAN0_CREL              (0x42000000U) /**< \brief (CAN0) Core Release */
-#define REG_CAN0_ENDN              (0x42000004U) /**< \brief (CAN0) Endian */
-#define REG_CAN0_MRCFG             (0x42000008U) /**< \brief (CAN0) Message RAM Configuration */
-#define REG_CAN0_DBTP              (0x4200000CU) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
-#define REG_CAN0_TEST              (0x42000010U) /**< \brief (CAN0) Test */
-#define REG_CAN0_RWD               (0x42000014U) /**< \brief (CAN0) RAM Watchdog */
-#define REG_CAN0_CCCR              (0x42000018U) /**< \brief (CAN0) CC Control */
-#define REG_CAN0_NBTP              (0x4200001CU) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
-#define REG_CAN0_TSCC              (0x42000020U) /**< \brief (CAN0) Timestamp Counter Configuration */
-#define REG_CAN0_TSCV              (0x42000024U) /**< \brief (CAN0) Timestamp Counter Value */
-#define REG_CAN0_TOCC              (0x42000028U) /**< \brief (CAN0) Timeout Counter Configuration */
-#define REG_CAN0_TOCV              (0x4200002CU) /**< \brief (CAN0) Timeout Counter Value */
-#define REG_CAN0_ECR               (0x42000040U) /**< \brief (CAN0) Error Counter */
-#define REG_CAN0_PSR               (0x42000044U) /**< \brief (CAN0) Protocol Status */
-#define REG_CAN0_TDCR              (0x42000048U) /**< \brief (CAN0) Extended ID Filter Configuration */
-#define REG_CAN0_IR                (0x42000050U) /**< \brief (CAN0) Interrupt */
-#define REG_CAN0_IE                (0x42000054U) /**< \brief (CAN0) Interrupt Enable */
-#define REG_CAN0_ILS               (0x42000058U) /**< \brief (CAN0) Interrupt Line Select */
-#define REG_CAN0_ILE               (0x4200005CU) /**< \brief (CAN0) Interrupt Line Enable */
-#define REG_CAN0_GFC               (0x42000080U) /**< \brief (CAN0) Global Filter Configuration */
-#define REG_CAN0_SIDFC             (0x42000084U) /**< \brief (CAN0) Standard ID Filter Configuration */
-#define REG_CAN0_XIDFC             (0x42000088U) /**< \brief (CAN0) Extended ID Filter Configuration */
-#define REG_CAN0_XIDAM             (0x42000090U) /**< \brief (CAN0) Extended ID AND Mask */
-#define REG_CAN0_HPMS              (0x42000094U) /**< \brief (CAN0) High Priority Message Status */
-#define REG_CAN0_NDAT1             (0x42000098U) /**< \brief (CAN0) New Data 1 */
-#define REG_CAN0_NDAT2             (0x4200009CU) /**< \brief (CAN0) New Data 2 */
-#define REG_CAN0_RXF0C             (0x420000A0U) /**< \brief (CAN0) Rx FIFO 0 Configuration */
-#define REG_CAN0_RXF0S             (0x420000A4U) /**< \brief (CAN0) Rx FIFO 0 Status */
-#define REG_CAN0_RXF0A             (0x420000A8U) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
-#define REG_CAN0_RXBC              (0x420000ACU) /**< \brief (CAN0) Rx Buffer Configuration */
-#define REG_CAN0_RXF1C             (0x420000B0U) /**< \brief (CAN0) Rx FIFO 1 Configuration */
-#define REG_CAN0_RXF1S             (0x420000B4U) /**< \brief (CAN0) Rx FIFO 1 Status */
-#define REG_CAN0_RXF1A             (0x420000B8U) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
-#define REG_CAN0_RXESC             (0x420000BCU) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
-#define REG_CAN0_TXBC              (0x420000C0U) /**< \brief (CAN0) Tx Buffer Configuration */
-#define REG_CAN0_TXFQS             (0x420000C4U) /**< \brief (CAN0) Tx FIFO / Queue Status */
-#define REG_CAN0_TXESC             (0x420000C8U) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
-#define REG_CAN0_TXBRP             (0x420000CCU) /**< \brief (CAN0) Tx Buffer Request Pending */
-#define REG_CAN0_TXBAR             (0x420000D0U) /**< \brief (CAN0) Tx Buffer Add Request */
-#define REG_CAN0_TXBCR             (0x420000D4U) /**< \brief (CAN0) Tx Buffer Cancellation Request */
-#define REG_CAN0_TXBTO             (0x420000D8U) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
-#define REG_CAN0_TXBCF             (0x420000DCU) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
-#define REG_CAN0_TXBTIE            (0x420000E0U) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
-#define REG_CAN0_TXBCIE            (0x420000E4U) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
-#define REG_CAN0_TXEFC             (0x420000F0U) /**< \brief (CAN0) Tx Event FIFO Configuration */
-#define REG_CAN0_TXEFS             (0x420000F4U) /**< \brief (CAN0) Tx Event FIFO Status */
-#define REG_CAN0_TXEFA             (0x420000F8U) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
-#else
-#define REG_CAN0_CREL              (*(RoReg  *)0x42000000U) /**< \brief (CAN0) Core Release */
-#define REG_CAN0_ENDN              (*(RoReg  *)0x42000004U) /**< \brief (CAN0) Endian */
-#define REG_CAN0_MRCFG             (*(RwReg  *)0x42000008U) /**< \brief (CAN0) Message RAM Configuration */
-#define REG_CAN0_DBTP              (*(RwReg  *)0x4200000CU) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
-#define REG_CAN0_TEST              (*(RwReg  *)0x42000010U) /**< \brief (CAN0) Test */
-#define REG_CAN0_RWD               (*(RwReg  *)0x42000014U) /**< \brief (CAN0) RAM Watchdog */
-#define REG_CAN0_CCCR              (*(RwReg  *)0x42000018U) /**< \brief (CAN0) CC Control */
-#define REG_CAN0_NBTP              (*(RwReg  *)0x4200001CU) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
-#define REG_CAN0_TSCC              (*(RwReg  *)0x42000020U) /**< \brief (CAN0) Timestamp Counter Configuration */
-#define REG_CAN0_TSCV              (*(RoReg  *)0x42000024U) /**< \brief (CAN0) Timestamp Counter Value */
-#define REG_CAN0_TOCC              (*(RwReg  *)0x42000028U) /**< \brief (CAN0) Timeout Counter Configuration */
-#define REG_CAN0_TOCV              (*(RwReg  *)0x4200002CU) /**< \brief (CAN0) Timeout Counter Value */
-#define REG_CAN0_ECR               (*(RoReg  *)0x42000040U) /**< \brief (CAN0) Error Counter */
-#define REG_CAN0_PSR               (*(RoReg  *)0x42000044U) /**< \brief (CAN0) Protocol Status */
-#define REG_CAN0_TDCR              (*(RwReg  *)0x42000048U) /**< \brief (CAN0) Extended ID Filter Configuration */
-#define REG_CAN0_IR                (*(RwReg  *)0x42000050U) /**< \brief (CAN0) Interrupt */
-#define REG_CAN0_IE                (*(RwReg  *)0x42000054U) /**< \brief (CAN0) Interrupt Enable */
-#define REG_CAN0_ILS               (*(RwReg  *)0x42000058U) /**< \brief (CAN0) Interrupt Line Select */
-#define REG_CAN0_ILE               (*(RwReg  *)0x4200005CU) /**< \brief (CAN0) Interrupt Line Enable */
-#define REG_CAN0_GFC               (*(RwReg  *)0x42000080U) /**< \brief (CAN0) Global Filter Configuration */
-#define REG_CAN0_SIDFC             (*(RwReg  *)0x42000084U) /**< \brief (CAN0) Standard ID Filter Configuration */
-#define REG_CAN0_XIDFC             (*(RwReg  *)0x42000088U) /**< \brief (CAN0) Extended ID Filter Configuration */
-#define REG_CAN0_XIDAM             (*(RwReg  *)0x42000090U) /**< \brief (CAN0) Extended ID AND Mask */
-#define REG_CAN0_HPMS              (*(RoReg  *)0x42000094U) /**< \brief (CAN0) High Priority Message Status */
-#define REG_CAN0_NDAT1             (*(RwReg  *)0x42000098U) /**< \brief (CAN0) New Data 1 */
-#define REG_CAN0_NDAT2             (*(RwReg  *)0x4200009CU) /**< \brief (CAN0) New Data 2 */
-#define REG_CAN0_RXF0C             (*(RwReg  *)0x420000A0U) /**< \brief (CAN0) Rx FIFO 0 Configuration */
-#define REG_CAN0_RXF0S             (*(RoReg  *)0x420000A4U) /**< \brief (CAN0) Rx FIFO 0 Status */
-#define REG_CAN0_RXF0A             (*(RwReg  *)0x420000A8U) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
-#define REG_CAN0_RXBC              (*(RwReg  *)0x420000ACU) /**< \brief (CAN0) Rx Buffer Configuration */
-#define REG_CAN0_RXF1C             (*(RwReg  *)0x420000B0U) /**< \brief (CAN0) Rx FIFO 1 Configuration */
-#define REG_CAN0_RXF1S             (*(RoReg  *)0x420000B4U) /**< \brief (CAN0) Rx FIFO 1 Status */
-#define REG_CAN0_RXF1A             (*(RwReg  *)0x420000B8U) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
-#define REG_CAN0_RXESC             (*(RwReg  *)0x420000BCU) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
-#define REG_CAN0_TXBC              (*(RwReg  *)0x420000C0U) /**< \brief (CAN0) Tx Buffer Configuration */
-#define REG_CAN0_TXFQS             (*(RoReg  *)0x420000C4U) /**< \brief (CAN0) Tx FIFO / Queue Status */
-#define REG_CAN0_TXESC             (*(RwReg  *)0x420000C8U) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
-#define REG_CAN0_TXBRP             (*(RoReg  *)0x420000CCU) /**< \brief (CAN0) Tx Buffer Request Pending */
-#define REG_CAN0_TXBAR             (*(RwReg  *)0x420000D0U) /**< \brief (CAN0) Tx Buffer Add Request */
-#define REG_CAN0_TXBCR             (*(RwReg  *)0x420000D4U) /**< \brief (CAN0) Tx Buffer Cancellation Request */
-#define REG_CAN0_TXBTO             (*(RoReg  *)0x420000D8U) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
-#define REG_CAN0_TXBCF             (*(RoReg  *)0x420000DCU) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
-#define REG_CAN0_TXBTIE            (*(RwReg  *)0x420000E0U) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
-#define REG_CAN0_TXBCIE            (*(RwReg  *)0x420000E4U) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
-#define REG_CAN0_TXEFC             (*(RwReg  *)0x420000F0U) /**< \brief (CAN0) Tx Event FIFO Configuration */
-#define REG_CAN0_TXEFS             (*(RoReg  *)0x420000F4U) /**< \brief (CAN0) Tx Event FIFO Status */
-#define REG_CAN0_TXEFA             (*(RwReg  *)0x420000F8U) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for CAN0 peripheral ========== */
-#define CAN0_CLK_AHB_ID             17       // Index of AHB clock
-#define CAN0_DMAC_ID_DEBUG          20       // DMA CAN Debug Req
-#define CAN0_GCLK_ID                27       // Index of Generic Clock
-#define CAN0_MSG_RAM_ADDR           0x20000000
-#define CAN0_QOS_RESET_VAL          1        // QOS reset value
-
-#endif /* _SAMD51_CAN0_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/can1.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/can1.h
deleted file mode 100644
index 973487da9d..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/can1.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for CAN1
- *
- * Copyright (c) 2014 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- *    Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CAN1_INSTANCE_
-#define _SAMD51_CAN1_INSTANCE_
-
-/* ========== Register definition for CAN1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_CAN1_CREL              (0x42003800U) /**< \brief (CAN1) Core Release */
-#define REG_CAN1_ENDN              (0x42003804U) /**< \brief (CAN1) Endian */
-#define REG_CAN1_MRCFG             (0x42003808U) /**< \brief (CAN1) Message RAM Configuration */
-#define REG_CAN1_DBTP              (0x4200380CU) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
-#define REG_CAN1_TEST              (0x42003810U) /**< \brief (CAN1) Test */
-#define REG_CAN1_RWD               (0x42003814U) /**< \brief (CAN1) RAM Watchdog */
-#define REG_CAN1_CCCR              (0x42003818U) /**< \brief (CAN1) CC Control */
-#define REG_CAN1_NBTP              (0x4200381CU) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
-#define REG_CAN1_TSCC              (0x42003820U) /**< \brief (CAN1) Timestamp Counter Configuration */
-#define REG_CAN1_TSCV              (0x42003824U) /**< \brief (CAN1) Timestamp Counter Value */
-#define REG_CAN1_TOCC              (0x42003828U) /**< \brief (CAN1) Timeout Counter Configuration */
-#define REG_CAN1_TOCV              (0x4200382CU) /**< \brief (CAN1) Timeout Counter Value */
-#define REG_CAN1_ECR               (0x42003840U) /**< \brief (CAN1) Error Counter */
-#define REG_CAN1_PSR               (0x42003844U) /**< \brief (CAN1) Protocol Status */
-#define REG_CAN1_TDCR              (0x42003848U) /**< \brief (CAN1) Extended ID Filter Configuration */
-#define REG_CAN1_IR                (0x42003850U) /**< \brief (CAN1) Interrupt */
-#define REG_CAN1_IE                (0x42003854U) /**< \brief (CAN1) Interrupt Enable */
-#define REG_CAN1_ILS               (0x42003858U) /**< \brief (CAN1) Interrupt Line Select */
-#define REG_CAN1_ILE               (0x4200385CU) /**< \brief (CAN1) Interrupt Line Enable */
-#define REG_CAN1_GFC               (0x42003880U) /**< \brief (CAN1) Global Filter Configuration */
-#define REG_CAN1_SIDFC             (0x42003884U) /**< \brief (CAN1) Standard ID Filter Configuration */
-#define REG_CAN1_XIDFC             (0x42003888U) /**< \brief (CAN1) Extended ID Filter Configuration */
-#define REG_CAN1_XIDAM             (0x42003890U) /**< \brief (CAN1) Extended ID AND Mask */
-#define REG_CAN1_HPMS              (0x42003894U) /**< \brief (CAN1) High Priority Message Status */
-#define REG_CAN1_NDAT1             (0x42003898U) /**< \brief (CAN1) New Data 1 */
-#define REG_CAN1_NDAT2             (0x4200389CU) /**< \brief (CAN1) New Data 2 */
-#define REG_CAN1_RXF0C             (0x420038A0U) /**< \brief (CAN1) Rx FIFO 0 Configuration */
-#define REG_CAN1_RXF0S             (0x420038A4U) /**< \brief (CAN1) Rx FIFO 0 Status */
-#define REG_CAN1_RXF0A             (0x420038A8U) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
-#define REG_CAN1_RXBC              (0x420038ACU) /**< \brief (CAN1) Rx Buffer Configuration */
-#define REG_CAN1_RXF1C             (0x420038B0U) /**< \brief (CAN1) Rx FIFO 1 Configuration */
-#define REG_CAN1_RXF1S             (0x420038B4U) /**< \brief (CAN1) Rx FIFO 1 Status */
-#define REG_CAN1_RXF1A             (0x420038B8U) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
-#define REG_CAN1_RXESC             (0x420038BCU) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
-#define REG_CAN1_TXBC              (0x420038C0U) /**< \brief (CAN1) Tx Buffer Configuration */
-#define REG_CAN1_TXFQS             (0x420038C4U) /**< \brief (CAN1) Tx FIFO / Queue Status */
-#define REG_CAN1_TXESC             (0x420038C8U) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
-#define REG_CAN1_TXBRP             (0x420038CCU) /**< \brief (CAN1) Tx Buffer Request Pending */
-#define REG_CAN1_TXBAR             (0x420038D0U) /**< \brief (CAN1) Tx Buffer Add Request */
-#define REG_CAN1_TXBCR             (0x420038D4U) /**< \brief (CAN1) Tx Buffer Cancellation Request */
-#define REG_CAN1_TXBTO             (0x420038D8U) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
-#define REG_CAN1_TXBCF             (0x420038DCU) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
-#define REG_CAN1_TXBTIE            (0x420038E0U) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
-#define REG_CAN1_TXBCIE            (0x420038E4U) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
-#define REG_CAN1_TXEFC             (0x420038F0U) /**< \brief (CAN1) Tx Event FIFO Configuration */
-#define REG_CAN1_TXEFS             (0x420038F4U) /**< \brief (CAN1) Tx Event FIFO Status */
-#define REG_CAN1_TXEFA             (0x420038F8U) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
-#else
-#define REG_CAN1_CREL              (*(RoReg  *)0x42003800U) /**< \brief (CAN1) Core Release */
-#define REG_CAN1_ENDN              (*(RoReg  *)0x42003804U) /**< \brief (CAN1) Endian */
-#define REG_CAN1_MRCFG             (*(RwReg  *)0x42003808U) /**< \brief (CAN1) Message RAM Configuration */
-#define REG_CAN1_DBTP              (*(RwReg  *)0x4200380CU) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
-#define REG_CAN1_TEST              (*(RwReg  *)0x42003810U) /**< \brief (CAN1) Test */
-#define REG_CAN1_RWD               (*(RwReg  *)0x42003814U) /**< \brief (CAN1) RAM Watchdog */
-#define REG_CAN1_CCCR              (*(RwReg  *)0x42003818U) /**< \brief (CAN1) CC Control */
-#define REG_CAN1_NBTP              (*(RwReg  *)0x4200381CU) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
-#define REG_CAN1_TSCC              (*(RwReg  *)0x42003820U) /**< \brief (CAN1) Timestamp Counter Configuration */
-#define REG_CAN1_TSCV              (*(RoReg  *)0x42003824U) /**< \brief (CAN1) Timestamp Counter Value */
-#define REG_CAN1_TOCC              (*(RwReg  *)0x42003828U) /**< \brief (CAN1) Timeout Counter Configuration */
-#define REG_CAN1_TOCV              (*(RwReg  *)0x4200382CU) /**< \brief (CAN1) Timeout Counter Value */
-#define REG_CAN1_ECR               (*(RoReg  *)0x42003840U) /**< \brief (CAN1) Error Counter */
-#define REG_CAN1_PSR               (*(RoReg  *)0x42003844U) /**< \brief (CAN1) Protocol Status */
-#define REG_CAN1_TDCR              (*(RwReg  *)0x42003848U) /**< \brief (CAN1) Extended ID Filter Configuration */
-#define REG_CAN1_IR                (*(RwReg  *)0x42003850U) /**< \brief (CAN1) Interrupt */
-#define REG_CAN1_IE                (*(RwReg  *)0x42003854U) /**< \brief (CAN1) Interrupt Enable */
-#define REG_CAN1_ILS               (*(RwReg  *)0x42003858U) /**< \brief (CAN1) Interrupt Line Select */
-#define REG_CAN1_ILE               (*(RwReg  *)0x4200385CU) /**< \brief (CAN1) Interrupt Line Enable */
-#define REG_CAN1_GFC               (*(RwReg  *)0x42003880U) /**< \brief (CAN1) Global Filter Configuration */
-#define REG_CAN1_SIDFC             (*(RwReg  *)0x42003884U) /**< \brief (CAN1) Standard ID Filter Configuration */
-#define REG_CAN1_XIDFC             (*(RwReg  *)0x42003888U) /**< \brief (CAN1) Extended ID Filter Configuration */
-#define REG_CAN1_XIDAM             (*(RwReg  *)0x42003890U) /**< \brief (CAN1) Extended ID AND Mask */
-#define REG_CAN1_HPMS              (*(RoReg  *)0x42003894U) /**< \brief (CAN1) High Priority Message Status */
-#define REG_CAN1_NDAT1             (*(RwReg  *)0x42003898U) /**< \brief (CAN1) New Data 1 */
-#define REG_CAN1_NDAT2             (*(RwReg  *)0x4200389CU) /**< \brief (CAN1) New Data 2 */
-#define REG_CAN1_RXF0C             (*(RwReg  *)0x420038A0U) /**< \brief (CAN1) Rx FIFO 0 Configuration */
-#define REG_CAN1_RXF0S             (*(RoReg  *)0x420038A4U) /**< \brief (CAN1) Rx FIFO 0 Status */
-#define REG_CAN1_RXF0A             (*(RwReg  *)0x420038A8U) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
-#define REG_CAN1_RXBC              (*(RwReg  *)0x420038ACU) /**< \brief (CAN1) Rx Buffer Configuration */
-#define REG_CAN1_RXF1C             (*(RwReg  *)0x420038B0U) /**< \brief (CAN1) Rx FIFO 1 Configuration */
-#define REG_CAN1_RXF1S             (*(RoReg  *)0x420038B4U) /**< \brief (CAN1) Rx FIFO 1 Status */
-#define REG_CAN1_RXF1A             (*(RwReg  *)0x420038B8U) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
-#define REG_CAN1_RXESC             (*(RwReg  *)0x420038BCU) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
-#define REG_CAN1_TXBC              (*(RwReg  *)0x420038C0U) /**< \brief (CAN1) Tx Buffer Configuration */
-#define REG_CAN1_TXFQS             (*(RoReg  *)0x420038C4U) /**< \brief (CAN1) Tx FIFO / Queue Status */
-#define REG_CAN1_TXESC             (*(RwReg  *)0x420038C8U) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
-#define REG_CAN1_TXBRP             (*(RoReg  *)0x420038CCU) /**< \brief (CAN1) Tx Buffer Request Pending */
-#define REG_CAN1_TXBAR             (*(RwReg  *)0x420038D0U) /**< \brief (CAN1) Tx Buffer Add Request */
-#define REG_CAN1_TXBCR             (*(RwReg  *)0x420038D4U) /**< \brief (CAN1) Tx Buffer Cancellation Request */
-#define REG_CAN1_TXBTO             (*(RoReg  *)0x420038D8U) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
-#define REG_CAN1_TXBCF             (*(RoReg  *)0x420038DCU) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
-#define REG_CAN1_TXBTIE            (*(RwReg  *)0x420038E0U) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
-#define REG_CAN1_TXBCIE            (*(RwReg  *)0x420038E4U) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
-#define REG_CAN1_TXEFC             (*(RwReg  *)0x420038F0U) /**< \brief (CAN1) Tx Event FIFO Configuration */
-#define REG_CAN1_TXEFS             (*(RoReg  *)0x420038F4U) /**< \brief (CAN1) Tx Event FIFO Status */
-#define REG_CAN1_TXEFA             (*(RwReg  *)0x420038F8U) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for CAN1 peripheral ========== */
-#define CAN1_CLK_AHB_ID             22       // Index of AHB clock
-#define CAN1_DMAC_ID_DEBUG          38       // DMA CAN Debug Req
-#define CAN1_GCLK_ID                36       // Index of Generic Clock
-
-#endif /* _SAMD51_CAN1_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/ccl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/ccl.h
deleted file mode 100644
index 5f76d1ae31..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/ccl.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for CCL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CCL_INSTANCE_
-#define _SAMD51_CCL_INSTANCE_
-
-/* ========== Register definition for CCL peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_CCL_CTRL               (0x42003800) /**< \brief (CCL) Control */
-#define REG_CCL_SEQCTRL0           (0x42003804) /**< \brief (CCL) SEQ Control x 0 */
-#define REG_CCL_SEQCTRL1           (0x42003805) /**< \brief (CCL) SEQ Control x 1 */
-#define REG_CCL_LUTCTRL0           (0x42003808) /**< \brief (CCL) LUT Control x 0 */
-#define REG_CCL_LUTCTRL1           (0x4200380C) /**< \brief (CCL) LUT Control x 1 */
-#define REG_CCL_LUTCTRL2           (0x42003810) /**< \brief (CCL) LUT Control x 2 */
-#define REG_CCL_LUTCTRL3           (0x42003814) /**< \brief (CCL) LUT Control x 3 */
-#else
-#define REG_CCL_CTRL               (*(RwReg8 *)0x42003800UL) /**< \brief (CCL) Control */
-#define REG_CCL_SEQCTRL0           (*(RwReg8 *)0x42003804UL) /**< \brief (CCL) SEQ Control x 0 */
-#define REG_CCL_SEQCTRL1           (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */
-#define REG_CCL_LUTCTRL0           (*(RwReg  *)0x42003808UL) /**< \brief (CCL) LUT Control x 0 */
-#define REG_CCL_LUTCTRL1           (*(RwReg  *)0x4200380CUL) /**< \brief (CCL) LUT Control x 1 */
-#define REG_CCL_LUTCTRL2           (*(RwReg  *)0x42003810UL) /**< \brief (CCL) LUT Control x 2 */
-#define REG_CCL_LUTCTRL3           (*(RwReg  *)0x42003814UL) /**< \brief (CCL) LUT Control x 3 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for CCL peripheral ========== */
-#define CCL_GCLK_ID                 33       // GCLK index for CCL
-#define CCL_LUT_NUM                 4        // Number of LUT in a CCL
-#define CCL_SEQ_NUM                 2        // Number of SEQ in a CCL
-
-#endif /* _SAMD51_CCL_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/cmcc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/cmcc.h
deleted file mode 100644
index 6744e27f86..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/cmcc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for CMCC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_CMCC_INSTANCE_
-#define _SAMD51_CMCC_INSTANCE_
-
-/* ========== Register definition for CMCC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_CMCC_TYPE              (0x41006000) /**< \brief (CMCC) Cache Type Register */
-#define REG_CMCC_CFG               (0x41006004) /**< \brief (CMCC) Cache Configuration Register */
-#define REG_CMCC_CTRL              (0x41006008) /**< \brief (CMCC) Cache Control Register */
-#define REG_CMCC_SR                (0x4100600C) /**< \brief (CMCC) Cache Status Register */
-#define REG_CMCC_LCKWAY            (0x41006010) /**< \brief (CMCC) Cache Lock per Way Register */
-#define REG_CMCC_MAINT0            (0x41006020) /**< \brief (CMCC) Cache Maintenance Register 0 */
-#define REG_CMCC_MAINT1            (0x41006024) /**< \brief (CMCC) Cache Maintenance Register 1 */
-#define REG_CMCC_MCFG              (0x41006028) /**< \brief (CMCC) Cache Monitor Configuration Register */
-#define REG_CMCC_MEN               (0x4100602C) /**< \brief (CMCC) Cache Monitor Enable Register */
-#define REG_CMCC_MCTRL             (0x41006030) /**< \brief (CMCC) Cache Monitor Control Register */
-#define REG_CMCC_MSR               (0x41006034) /**< \brief (CMCC) Cache Monitor Status Register */
-#else
-#define REG_CMCC_TYPE              (*(RoReg  *)0x41006000UL) /**< \brief (CMCC) Cache Type Register */
-#define REG_CMCC_CFG               (*(RwReg  *)0x41006004UL) /**< \brief (CMCC) Cache Configuration Register */
-#define REG_CMCC_CTRL              (*(WoReg  *)0x41006008UL) /**< \brief (CMCC) Cache Control Register */
-#define REG_CMCC_SR                (*(RoReg  *)0x4100600CUL) /**< \brief (CMCC) Cache Status Register */
-#define REG_CMCC_LCKWAY            (*(RwReg  *)0x41006010UL) /**< \brief (CMCC) Cache Lock per Way Register */
-#define REG_CMCC_MAINT0            (*(WoReg  *)0x41006020UL) /**< \brief (CMCC) Cache Maintenance Register 0 */
-#define REG_CMCC_MAINT1            (*(WoReg  *)0x41006024UL) /**< \brief (CMCC) Cache Maintenance Register 1 */
-#define REG_CMCC_MCFG              (*(RwReg  *)0x41006028UL) /**< \brief (CMCC) Cache Monitor Configuration Register */
-#define REG_CMCC_MEN               (*(RwReg  *)0x4100602CUL) /**< \brief (CMCC) Cache Monitor Enable Register */
-#define REG_CMCC_MCTRL             (*(WoReg  *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Control Register */
-#define REG_CMCC_MSR               (*(RoReg  *)0x41006034UL) /**< \brief (CMCC) Cache Monitor Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-
-#endif /* _SAMD51_CMCC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/dac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/dac.h
deleted file mode 100644
index 15a7af4ab8..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/dac.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for DAC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_DAC_INSTANCE_
-#define _SAMD51_DAC_INSTANCE_
-
-/* ========== Register definition for DAC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_DAC_CTRLA              (0x43002400) /**< \brief (DAC) Control A */
-#define REG_DAC_CTRLB              (0x43002401) /**< \brief (DAC) Control B */
-#define REG_DAC_EVCTRL             (0x43002402) /**< \brief (DAC) Event Control */
-#define REG_DAC_INTENCLR           (0x43002404) /**< \brief (DAC) Interrupt Enable Clear */
-#define REG_DAC_INTENSET           (0x43002405) /**< \brief (DAC) Interrupt Enable Set */
-#define REG_DAC_INTFLAG            (0x43002406) /**< \brief (DAC) Interrupt Flag Status and Clear */
-#define REG_DAC_STATUS             (0x43002407) /**< \brief (DAC) Status */
-#define REG_DAC_SYNCBUSY           (0x43002408) /**< \brief (DAC) Synchronization Busy */
-#define REG_DAC_DACCTRL0           (0x4300240C) /**< \brief (DAC) DAC 0 Control */
-#define REG_DAC_DACCTRL1           (0x4300240E) /**< \brief (DAC) DAC 1 Control */
-#define REG_DAC_DATA0              (0x43002410) /**< \brief (DAC) DAC 0 Data */
-#define REG_DAC_DATA1              (0x43002412) /**< \brief (DAC) DAC 1 Data */
-#define REG_DAC_DATABUF0           (0x43002414) /**< \brief (DAC) DAC 0 Data Buffer */
-#define REG_DAC_DATABUF1           (0x43002416) /**< \brief (DAC) DAC 1 Data Buffer */
-#define REG_DAC_DBGCTRL            (0x43002418) /**< \brief (DAC) Debug Control */
-#define REG_DAC_RESULT0            (0x4300241C) /**< \brief (DAC) Filter Result 0 */
-#define REG_DAC_RESULT1            (0x4300241E) /**< \brief (DAC) Filter Result 1 */
-#else
-#define REG_DAC_CTRLA              (*(RwReg8 *)0x43002400UL) /**< \brief (DAC) Control A */
-#define REG_DAC_CTRLB              (*(RwReg8 *)0x43002401UL) /**< \brief (DAC) Control B */
-#define REG_DAC_EVCTRL             (*(RwReg8 *)0x43002402UL) /**< \brief (DAC) Event Control */
-#define REG_DAC_INTENCLR           (*(RwReg8 *)0x43002404UL) /**< \brief (DAC) Interrupt Enable Clear */
-#define REG_DAC_INTENSET           (*(RwReg8 *)0x43002405UL) /**< \brief (DAC) Interrupt Enable Set */
-#define REG_DAC_INTFLAG            (*(RwReg8 *)0x43002406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
-#define REG_DAC_STATUS             (*(RoReg8 *)0x43002407UL) /**< \brief (DAC) Status */
-#define REG_DAC_SYNCBUSY           (*(RoReg  *)0x43002408UL) /**< \brief (DAC) Synchronization Busy */
-#define REG_DAC_DACCTRL0           (*(RwReg16*)0x4300240CUL) /**< \brief (DAC) DAC 0 Control */
-#define REG_DAC_DACCTRL1           (*(RwReg16*)0x4300240EUL) /**< \brief (DAC) DAC 1 Control */
-#define REG_DAC_DATA0              (*(WoReg16*)0x43002410UL) /**< \brief (DAC) DAC 0 Data */
-#define REG_DAC_DATA1              (*(WoReg16*)0x43002412UL) /**< \brief (DAC) DAC 1 Data */
-#define REG_DAC_DATABUF0           (*(WoReg16*)0x43002414UL) /**< \brief (DAC) DAC 0 Data Buffer */
-#define REG_DAC_DATABUF1           (*(WoReg16*)0x43002416UL) /**< \brief (DAC) DAC 1 Data Buffer */
-#define REG_DAC_DBGCTRL            (*(RwReg8 *)0x43002418UL) /**< \brief (DAC) Debug Control */
-#define REG_DAC_RESULT0            (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
-#define REG_DAC_RESULT1            (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for DAC peripheral ========== */
-#define DAC_CHANNEL_SIZE            2        // Number of DACs
-#define DAC_DATA_SIZE               12       // Number of bits in data
-#define DAC_DMAC_ID_EMPTY_0         72
-#define DAC_DMAC_ID_EMPTY_1         73
-#define DAC_DMAC_ID_EMPTY_LSB       72
-#define DAC_DMAC_ID_EMPTY_MSB       73
-#define DAC_DMAC_ID_EMPTY_SIZE      2
-#define DAC_DMAC_ID_RESRDY_0        74
-#define DAC_DMAC_ID_RESRDY_1        75
-#define DAC_DMAC_ID_RESRDY_LSB      74
-#define DAC_DMAC_ID_RESRDY_MSB      75
-#define DAC_DMAC_ID_RESRDY_SIZE     2
-#define DAC_GCLK_ID                 42       // Index of Generic Clock
-#define DAC_STEP                    7        // Number of steps to reach full scale
-
-#endif /* _SAMD51_DAC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/dmac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/dmac.h
deleted file mode 100644
index 078ebfb022..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/dmac.h
+++ /dev/null
@@ -1,596 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for DMAC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_DMAC_INSTANCE_
-#define _SAMD51_DMAC_INSTANCE_
-
-/* ========== Register definition for DMAC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_DMAC_CTRL              (0x4100A000) /**< \brief (DMAC) Control */
-#define REG_DMAC_CRCCTRL           (0x4100A002) /**< \brief (DMAC) CRC Control */
-#define REG_DMAC_CRCDATAIN         (0x4100A004) /**< \brief (DMAC) CRC Data Input */
-#define REG_DMAC_CRCCHKSUM         (0x4100A008) /**< \brief (DMAC) CRC Checksum */
-#define REG_DMAC_CRCSTATUS         (0x4100A00C) /**< \brief (DMAC) CRC Status */
-#define REG_DMAC_DBGCTRL           (0x4100A00D) /**< \brief (DMAC) Debug Control */
-#define REG_DMAC_SWTRIGCTRL        (0x4100A010) /**< \brief (DMAC) Software Trigger Control */
-#define REG_DMAC_PRICTRL0          (0x4100A014) /**< \brief (DMAC) Priority Control 0 */
-#define REG_DMAC_INTPEND           (0x4100A020) /**< \brief (DMAC) Interrupt Pending */
-#define REG_DMAC_INTSTATUS         (0x4100A024) /**< \brief (DMAC) Interrupt Status */
-#define REG_DMAC_BUSYCH            (0x4100A028) /**< \brief (DMAC) Busy Channels */
-#define REG_DMAC_PENDCH            (0x4100A02C) /**< \brief (DMAC) Pending Channels */
-#define REG_DMAC_ACTIVE            (0x4100A030) /**< \brief (DMAC) Active Channel and Levels */
-#define REG_DMAC_BASEADDR          (0x4100A034) /**< \brief (DMAC) Descriptor Memory Section Base Address */
-#define REG_DMAC_WRBADDR           (0x4100A038) /**< \brief (DMAC) Write-Back Memory Section Base Address */
-#define REG_DMAC_CHCTRLA0          (0x4100A040) /**< \brief (DMAC) Channel 0 Control A */
-#define REG_DMAC_CHCTRLB0          (0x4100A044) /**< \brief (DMAC) Channel 0 Control B */
-#define REG_DMAC_CHPRILVL0         (0x4100A045) /**< \brief (DMAC) Channel 0 Priority Level */
-#define REG_DMAC_CHEVCTRL0         (0x4100A046) /**< \brief (DMAC) Channel 0 Event Control */
-#define REG_DMAC_CHINTENCLR0       (0x4100A04C) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET0       (0x4100A04D) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG0        (0x4100A04E) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS0         (0x4100A04F) /**< \brief (DMAC) Channel 0 Status */
-#define REG_DMAC_CHCTRLA1          (0x4100A050) /**< \brief (DMAC) Channel 1 Control A */
-#define REG_DMAC_CHCTRLB1          (0x4100A054) /**< \brief (DMAC) Channel 1 Control B */
-#define REG_DMAC_CHPRILVL1         (0x4100A055) /**< \brief (DMAC) Channel 1 Priority Level */
-#define REG_DMAC_CHEVCTRL1         (0x4100A056) /**< \brief (DMAC) Channel 1 Event Control */
-#define REG_DMAC_CHINTENCLR1       (0x4100A05C) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET1       (0x4100A05D) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG1        (0x4100A05E) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS1         (0x4100A05F) /**< \brief (DMAC) Channel 1 Status */
-#define REG_DMAC_CHCTRLA2          (0x4100A060) /**< \brief (DMAC) Channel 2 Control A */
-#define REG_DMAC_CHCTRLB2          (0x4100A064) /**< \brief (DMAC) Channel 2 Control B */
-#define REG_DMAC_CHPRILVL2         (0x4100A065) /**< \brief (DMAC) Channel 2 Priority Level */
-#define REG_DMAC_CHEVCTRL2         (0x4100A066) /**< \brief (DMAC) Channel 2 Event Control */
-#define REG_DMAC_CHINTENCLR2       (0x4100A06C) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET2       (0x4100A06D) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG2        (0x4100A06E) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS2         (0x4100A06F) /**< \brief (DMAC) Channel 2 Status */
-#define REG_DMAC_CHCTRLA3          (0x4100A070) /**< \brief (DMAC) Channel 3 Control A */
-#define REG_DMAC_CHCTRLB3          (0x4100A074) /**< \brief (DMAC) Channel 3 Control B */
-#define REG_DMAC_CHPRILVL3         (0x4100A075) /**< \brief (DMAC) Channel 3 Priority Level */
-#define REG_DMAC_CHEVCTRL3         (0x4100A076) /**< \brief (DMAC) Channel 3 Event Control */
-#define REG_DMAC_CHINTENCLR3       (0x4100A07C) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET3       (0x4100A07D) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG3        (0x4100A07E) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS3         (0x4100A07F) /**< \brief (DMAC) Channel 3 Status */
-#define REG_DMAC_CHCTRLA4          (0x4100A080) /**< \brief (DMAC) Channel 4 Control A */
-#define REG_DMAC_CHCTRLB4          (0x4100A084) /**< \brief (DMAC) Channel 4 Control B */
-#define REG_DMAC_CHPRILVL4         (0x4100A085) /**< \brief (DMAC) Channel 4 Priority Level */
-#define REG_DMAC_CHEVCTRL4         (0x4100A086) /**< \brief (DMAC) Channel 4 Event Control */
-#define REG_DMAC_CHINTENCLR4       (0x4100A08C) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET4       (0x4100A08D) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG4        (0x4100A08E) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS4         (0x4100A08F) /**< \brief (DMAC) Channel 4 Status */
-#define REG_DMAC_CHCTRLA5          (0x4100A090) /**< \brief (DMAC) Channel 5 Control A */
-#define REG_DMAC_CHCTRLB5          (0x4100A094) /**< \brief (DMAC) Channel 5 Control B */
-#define REG_DMAC_CHPRILVL5         (0x4100A095) /**< \brief (DMAC) Channel 5 Priority Level */
-#define REG_DMAC_CHEVCTRL5         (0x4100A096) /**< \brief (DMAC) Channel 5 Event Control */
-#define REG_DMAC_CHINTENCLR5       (0x4100A09C) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET5       (0x4100A09D) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG5        (0x4100A09E) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS5         (0x4100A09F) /**< \brief (DMAC) Channel 5 Status */
-#define REG_DMAC_CHCTRLA6          (0x4100A0A0) /**< \brief (DMAC) Channel 6 Control A */
-#define REG_DMAC_CHCTRLB6          (0x4100A0A4) /**< \brief (DMAC) Channel 6 Control B */
-#define REG_DMAC_CHPRILVL6         (0x4100A0A5) /**< \brief (DMAC) Channel 6 Priority Level */
-#define REG_DMAC_CHEVCTRL6         (0x4100A0A6) /**< \brief (DMAC) Channel 6 Event Control */
-#define REG_DMAC_CHINTENCLR6       (0x4100A0AC) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET6       (0x4100A0AD) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG6        (0x4100A0AE) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS6         (0x4100A0AF) /**< \brief (DMAC) Channel 6 Status */
-#define REG_DMAC_CHCTRLA7          (0x4100A0B0) /**< \brief (DMAC) Channel 7 Control A */
-#define REG_DMAC_CHCTRLB7          (0x4100A0B4) /**< \brief (DMAC) Channel 7 Control B */
-#define REG_DMAC_CHPRILVL7         (0x4100A0B5) /**< \brief (DMAC) Channel 7 Priority Level */
-#define REG_DMAC_CHEVCTRL7         (0x4100A0B6) /**< \brief (DMAC) Channel 7 Event Control */
-#define REG_DMAC_CHINTENCLR7       (0x4100A0BC) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET7       (0x4100A0BD) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG7        (0x4100A0BE) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS7         (0x4100A0BF) /**< \brief (DMAC) Channel 7 Status */
-#define REG_DMAC_CHCTRLA8          (0x4100A0C0) /**< \brief (DMAC) Channel 8 Control A */
-#define REG_DMAC_CHCTRLB8          (0x4100A0C4) /**< \brief (DMAC) Channel 8 Control B */
-#define REG_DMAC_CHPRILVL8         (0x4100A0C5) /**< \brief (DMAC) Channel 8 Priority Level */
-#define REG_DMAC_CHEVCTRL8         (0x4100A0C6) /**< \brief (DMAC) Channel 8 Event Control */
-#define REG_DMAC_CHINTENCLR8       (0x4100A0CC) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET8       (0x4100A0CD) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG8        (0x4100A0CE) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS8         (0x4100A0CF) /**< \brief (DMAC) Channel 8 Status */
-#define REG_DMAC_CHCTRLA9          (0x4100A0D0) /**< \brief (DMAC) Channel 9 Control A */
-#define REG_DMAC_CHCTRLB9          (0x4100A0D4) /**< \brief (DMAC) Channel 9 Control B */
-#define REG_DMAC_CHPRILVL9         (0x4100A0D5) /**< \brief (DMAC) Channel 9 Priority Level */
-#define REG_DMAC_CHEVCTRL9         (0x4100A0D6) /**< \brief (DMAC) Channel 9 Event Control */
-#define REG_DMAC_CHINTENCLR9       (0x4100A0DC) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET9       (0x4100A0DD) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG9        (0x4100A0DE) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS9         (0x4100A0DF) /**< \brief (DMAC) Channel 9 Status */
-#define REG_DMAC_CHCTRLA10         (0x4100A0E0) /**< \brief (DMAC) Channel 10 Control A */
-#define REG_DMAC_CHCTRLB10         (0x4100A0E4) /**< \brief (DMAC) Channel 10 Control B */
-#define REG_DMAC_CHPRILVL10        (0x4100A0E5) /**< \brief (DMAC) Channel 10 Priority Level */
-#define REG_DMAC_CHEVCTRL10        (0x4100A0E6) /**< \brief (DMAC) Channel 10 Event Control */
-#define REG_DMAC_CHINTENCLR10      (0x4100A0EC) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET10      (0x4100A0ED) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG10       (0x4100A0EE) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS10        (0x4100A0EF) /**< \brief (DMAC) Channel 10 Status */
-#define REG_DMAC_CHCTRLA11         (0x4100A0F0) /**< \brief (DMAC) Channel 11 Control A */
-#define REG_DMAC_CHCTRLB11         (0x4100A0F4) /**< \brief (DMAC) Channel 11 Control B */
-#define REG_DMAC_CHPRILVL11        (0x4100A0F5) /**< \brief (DMAC) Channel 11 Priority Level */
-#define REG_DMAC_CHEVCTRL11        (0x4100A0F6) /**< \brief (DMAC) Channel 11 Event Control */
-#define REG_DMAC_CHINTENCLR11      (0x4100A0FC) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET11      (0x4100A0FD) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG11       (0x4100A0FE) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS11        (0x4100A0FF) /**< \brief (DMAC) Channel 11 Status */
-#define REG_DMAC_CHCTRLA12         (0x4100A100) /**< \brief (DMAC) Channel 12 Control A */
-#define REG_DMAC_CHCTRLB12         (0x4100A104) /**< \brief (DMAC) Channel 12 Control B */
-#define REG_DMAC_CHPRILVL12        (0x4100A105) /**< \brief (DMAC) Channel 12 Priority Level */
-#define REG_DMAC_CHEVCTRL12        (0x4100A106) /**< \brief (DMAC) Channel 12 Event Control */
-#define REG_DMAC_CHINTENCLR12      (0x4100A10C) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET12      (0x4100A10D) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG12       (0x4100A10E) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS12        (0x4100A10F) /**< \brief (DMAC) Channel 12 Status */
-#define REG_DMAC_CHCTRLA13         (0x4100A110) /**< \brief (DMAC) Channel 13 Control A */
-#define REG_DMAC_CHCTRLB13         (0x4100A114) /**< \brief (DMAC) Channel 13 Control B */
-#define REG_DMAC_CHPRILVL13        (0x4100A115) /**< \brief (DMAC) Channel 13 Priority Level */
-#define REG_DMAC_CHEVCTRL13        (0x4100A116) /**< \brief (DMAC) Channel 13 Event Control */
-#define REG_DMAC_CHINTENCLR13      (0x4100A11C) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET13      (0x4100A11D) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG13       (0x4100A11E) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS13        (0x4100A11F) /**< \brief (DMAC) Channel 13 Status */
-#define REG_DMAC_CHCTRLA14         (0x4100A120) /**< \brief (DMAC) Channel 14 Control A */
-#define REG_DMAC_CHCTRLB14         (0x4100A124) /**< \brief (DMAC) Channel 14 Control B */
-#define REG_DMAC_CHPRILVL14        (0x4100A125) /**< \brief (DMAC) Channel 14 Priority Level */
-#define REG_DMAC_CHEVCTRL14        (0x4100A126) /**< \brief (DMAC) Channel 14 Event Control */
-#define REG_DMAC_CHINTENCLR14      (0x4100A12C) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET14      (0x4100A12D) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG14       (0x4100A12E) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS14        (0x4100A12F) /**< \brief (DMAC) Channel 14 Status */
-#define REG_DMAC_CHCTRLA15         (0x4100A130) /**< \brief (DMAC) Channel 15 Control A */
-#define REG_DMAC_CHCTRLB15         (0x4100A134) /**< \brief (DMAC) Channel 15 Control B */
-#define REG_DMAC_CHPRILVL15        (0x4100A135) /**< \brief (DMAC) Channel 15 Priority Level */
-#define REG_DMAC_CHEVCTRL15        (0x4100A136) /**< \brief (DMAC) Channel 15 Event Control */
-#define REG_DMAC_CHINTENCLR15      (0x4100A13C) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET15      (0x4100A13D) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG15       (0x4100A13E) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS15        (0x4100A13F) /**< \brief (DMAC) Channel 15 Status */
-#define REG_DMAC_CHCTRLA16         (0x4100A140) /**< \brief (DMAC) Channel 16 Control A */
-#define REG_DMAC_CHCTRLB16         (0x4100A144) /**< \brief (DMAC) Channel 16 Control B */
-#define REG_DMAC_CHPRILVL16        (0x4100A145) /**< \brief (DMAC) Channel 16 Priority Level */
-#define REG_DMAC_CHEVCTRL16        (0x4100A146) /**< \brief (DMAC) Channel 16 Event Control */
-#define REG_DMAC_CHINTENCLR16      (0x4100A14C) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET16      (0x4100A14D) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG16       (0x4100A14E) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS16        (0x4100A14F) /**< \brief (DMAC) Channel 16 Status */
-#define REG_DMAC_CHCTRLA17         (0x4100A150) /**< \brief (DMAC) Channel 17 Control A */
-#define REG_DMAC_CHCTRLB17         (0x4100A154) /**< \brief (DMAC) Channel 17 Control B */
-#define REG_DMAC_CHPRILVL17        (0x4100A155) /**< \brief (DMAC) Channel 17 Priority Level */
-#define REG_DMAC_CHEVCTRL17        (0x4100A156) /**< \brief (DMAC) Channel 17 Event Control */
-#define REG_DMAC_CHINTENCLR17      (0x4100A15C) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET17      (0x4100A15D) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG17       (0x4100A15E) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS17        (0x4100A15F) /**< \brief (DMAC) Channel 17 Status */
-#define REG_DMAC_CHCTRLA18         (0x4100A160) /**< \brief (DMAC) Channel 18 Control A */
-#define REG_DMAC_CHCTRLB18         (0x4100A164) /**< \brief (DMAC) Channel 18 Control B */
-#define REG_DMAC_CHPRILVL18        (0x4100A165) /**< \brief (DMAC) Channel 18 Priority Level */
-#define REG_DMAC_CHEVCTRL18        (0x4100A166) /**< \brief (DMAC) Channel 18 Event Control */
-#define REG_DMAC_CHINTENCLR18      (0x4100A16C) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET18      (0x4100A16D) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG18       (0x4100A16E) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS18        (0x4100A16F) /**< \brief (DMAC) Channel 18 Status */
-#define REG_DMAC_CHCTRLA19         (0x4100A170) /**< \brief (DMAC) Channel 19 Control A */
-#define REG_DMAC_CHCTRLB19         (0x4100A174) /**< \brief (DMAC) Channel 19 Control B */
-#define REG_DMAC_CHPRILVL19        (0x4100A175) /**< \brief (DMAC) Channel 19 Priority Level */
-#define REG_DMAC_CHEVCTRL19        (0x4100A176) /**< \brief (DMAC) Channel 19 Event Control */
-#define REG_DMAC_CHINTENCLR19      (0x4100A17C) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET19      (0x4100A17D) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG19       (0x4100A17E) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS19        (0x4100A17F) /**< \brief (DMAC) Channel 19 Status */
-#define REG_DMAC_CHCTRLA20         (0x4100A180) /**< \brief (DMAC) Channel 20 Control A */
-#define REG_DMAC_CHCTRLB20         (0x4100A184) /**< \brief (DMAC) Channel 20 Control B */
-#define REG_DMAC_CHPRILVL20        (0x4100A185) /**< \brief (DMAC) Channel 20 Priority Level */
-#define REG_DMAC_CHEVCTRL20        (0x4100A186) /**< \brief (DMAC) Channel 20 Event Control */
-#define REG_DMAC_CHINTENCLR20      (0x4100A18C) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET20      (0x4100A18D) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG20       (0x4100A18E) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS20        (0x4100A18F) /**< \brief (DMAC) Channel 20 Status */
-#define REG_DMAC_CHCTRLA21         (0x4100A190) /**< \brief (DMAC) Channel 21 Control A */
-#define REG_DMAC_CHCTRLB21         (0x4100A194) /**< \brief (DMAC) Channel 21 Control B */
-#define REG_DMAC_CHPRILVL21        (0x4100A195) /**< \brief (DMAC) Channel 21 Priority Level */
-#define REG_DMAC_CHEVCTRL21        (0x4100A196) /**< \brief (DMAC) Channel 21 Event Control */
-#define REG_DMAC_CHINTENCLR21      (0x4100A19C) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET21      (0x4100A19D) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG21       (0x4100A19E) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS21        (0x4100A19F) /**< \brief (DMAC) Channel 21 Status */
-#define REG_DMAC_CHCTRLA22         (0x4100A1A0) /**< \brief (DMAC) Channel 22 Control A */
-#define REG_DMAC_CHCTRLB22         (0x4100A1A4) /**< \brief (DMAC) Channel 22 Control B */
-#define REG_DMAC_CHPRILVL22        (0x4100A1A5) /**< \brief (DMAC) Channel 22 Priority Level */
-#define REG_DMAC_CHEVCTRL22        (0x4100A1A6) /**< \brief (DMAC) Channel 22 Event Control */
-#define REG_DMAC_CHINTENCLR22      (0x4100A1AC) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET22      (0x4100A1AD) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG22       (0x4100A1AE) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS22        (0x4100A1AF) /**< \brief (DMAC) Channel 22 Status */
-#define REG_DMAC_CHCTRLA23         (0x4100A1B0) /**< \brief (DMAC) Channel 23 Control A */
-#define REG_DMAC_CHCTRLB23         (0x4100A1B4) /**< \brief (DMAC) Channel 23 Control B */
-#define REG_DMAC_CHPRILVL23        (0x4100A1B5) /**< \brief (DMAC) Channel 23 Priority Level */
-#define REG_DMAC_CHEVCTRL23        (0x4100A1B6) /**< \brief (DMAC) Channel 23 Event Control */
-#define REG_DMAC_CHINTENCLR23      (0x4100A1BC) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET23      (0x4100A1BD) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG23       (0x4100A1BE) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS23        (0x4100A1BF) /**< \brief (DMAC) Channel 23 Status */
-#define REG_DMAC_CHCTRLA24         (0x4100A1C0) /**< \brief (DMAC) Channel 24 Control A */
-#define REG_DMAC_CHCTRLB24         (0x4100A1C4) /**< \brief (DMAC) Channel 24 Control B */
-#define REG_DMAC_CHPRILVL24        (0x4100A1C5) /**< \brief (DMAC) Channel 24 Priority Level */
-#define REG_DMAC_CHEVCTRL24        (0x4100A1C6) /**< \brief (DMAC) Channel 24 Event Control */
-#define REG_DMAC_CHINTENCLR24      (0x4100A1CC) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET24      (0x4100A1CD) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG24       (0x4100A1CE) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS24        (0x4100A1CF) /**< \brief (DMAC) Channel 24 Status */
-#define REG_DMAC_CHCTRLA25         (0x4100A1D0) /**< \brief (DMAC) Channel 25 Control A */
-#define REG_DMAC_CHCTRLB25         (0x4100A1D4) /**< \brief (DMAC) Channel 25 Control B */
-#define REG_DMAC_CHPRILVL25        (0x4100A1D5) /**< \brief (DMAC) Channel 25 Priority Level */
-#define REG_DMAC_CHEVCTRL25        (0x4100A1D6) /**< \brief (DMAC) Channel 25 Event Control */
-#define REG_DMAC_CHINTENCLR25      (0x4100A1DC) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET25      (0x4100A1DD) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG25       (0x4100A1DE) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS25        (0x4100A1DF) /**< \brief (DMAC) Channel 25 Status */
-#define REG_DMAC_CHCTRLA26         (0x4100A1E0) /**< \brief (DMAC) Channel 26 Control A */
-#define REG_DMAC_CHCTRLB26         (0x4100A1E4) /**< \brief (DMAC) Channel 26 Control B */
-#define REG_DMAC_CHPRILVL26        (0x4100A1E5) /**< \brief (DMAC) Channel 26 Priority Level */
-#define REG_DMAC_CHEVCTRL26        (0x4100A1E6) /**< \brief (DMAC) Channel 26 Event Control */
-#define REG_DMAC_CHINTENCLR26      (0x4100A1EC) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET26      (0x4100A1ED) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG26       (0x4100A1EE) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS26        (0x4100A1EF) /**< \brief (DMAC) Channel 26 Status */
-#define REG_DMAC_CHCTRLA27         (0x4100A1F0) /**< \brief (DMAC) Channel 27 Control A */
-#define REG_DMAC_CHCTRLB27         (0x4100A1F4) /**< \brief (DMAC) Channel 27 Control B */
-#define REG_DMAC_CHPRILVL27        (0x4100A1F5) /**< \brief (DMAC) Channel 27 Priority Level */
-#define REG_DMAC_CHEVCTRL27        (0x4100A1F6) /**< \brief (DMAC) Channel 27 Event Control */
-#define REG_DMAC_CHINTENCLR27      (0x4100A1FC) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET27      (0x4100A1FD) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG27       (0x4100A1FE) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS27        (0x4100A1FF) /**< \brief (DMAC) Channel 27 Status */
-#define REG_DMAC_CHCTRLA28         (0x4100A200) /**< \brief (DMAC) Channel 28 Control A */
-#define REG_DMAC_CHCTRLB28         (0x4100A204) /**< \brief (DMAC) Channel 28 Control B */
-#define REG_DMAC_CHPRILVL28        (0x4100A205) /**< \brief (DMAC) Channel 28 Priority Level */
-#define REG_DMAC_CHEVCTRL28        (0x4100A206) /**< \brief (DMAC) Channel 28 Event Control */
-#define REG_DMAC_CHINTENCLR28      (0x4100A20C) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET28      (0x4100A20D) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG28       (0x4100A20E) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS28        (0x4100A20F) /**< \brief (DMAC) Channel 28 Status */
-#define REG_DMAC_CHCTRLA29         (0x4100A210) /**< \brief (DMAC) Channel 29 Control A */
-#define REG_DMAC_CHCTRLB29         (0x4100A214) /**< \brief (DMAC) Channel 29 Control B */
-#define REG_DMAC_CHPRILVL29        (0x4100A215) /**< \brief (DMAC) Channel 29 Priority Level */
-#define REG_DMAC_CHEVCTRL29        (0x4100A216) /**< \brief (DMAC) Channel 29 Event Control */
-#define REG_DMAC_CHINTENCLR29      (0x4100A21C) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET29      (0x4100A21D) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG29       (0x4100A21E) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS29        (0x4100A21F) /**< \brief (DMAC) Channel 29 Status */
-#define REG_DMAC_CHCTRLA30         (0x4100A220) /**< \brief (DMAC) Channel 30 Control A */
-#define REG_DMAC_CHCTRLB30         (0x4100A224) /**< \brief (DMAC) Channel 30 Control B */
-#define REG_DMAC_CHPRILVL30        (0x4100A225) /**< \brief (DMAC) Channel 30 Priority Level */
-#define REG_DMAC_CHEVCTRL30        (0x4100A226) /**< \brief (DMAC) Channel 30 Event Control */
-#define REG_DMAC_CHINTENCLR30      (0x4100A22C) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET30      (0x4100A22D) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG30       (0x4100A22E) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS30        (0x4100A22F) /**< \brief (DMAC) Channel 30 Status */
-#define REG_DMAC_CHCTRLA31         (0x4100A230) /**< \brief (DMAC) Channel 31 Control A */
-#define REG_DMAC_CHCTRLB31         (0x4100A234) /**< \brief (DMAC) Channel 31 Control B */
-#define REG_DMAC_CHPRILVL31        (0x4100A235) /**< \brief (DMAC) Channel 31 Priority Level */
-#define REG_DMAC_CHEVCTRL31        (0x4100A236) /**< \brief (DMAC) Channel 31 Event Control */
-#define REG_DMAC_CHINTENCLR31      (0x4100A23C) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET31      (0x4100A23D) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG31       (0x4100A23E) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS31        (0x4100A23F) /**< \brief (DMAC) Channel 31 Status */
-#else
-#define REG_DMAC_CTRL              (*(RwReg16*)0x4100A000UL) /**< \brief (DMAC) Control */
-#define REG_DMAC_CRCCTRL           (*(RwReg16*)0x4100A002UL) /**< \brief (DMAC) CRC Control */
-#define REG_DMAC_CRCDATAIN         (*(RwReg  *)0x4100A004UL) /**< \brief (DMAC) CRC Data Input */
-#define REG_DMAC_CRCCHKSUM         (*(RwReg  *)0x4100A008UL) /**< \brief (DMAC) CRC Checksum */
-#define REG_DMAC_CRCSTATUS         (*(RwReg8 *)0x4100A00CUL) /**< \brief (DMAC) CRC Status */
-#define REG_DMAC_DBGCTRL           (*(RwReg8 *)0x4100A00DUL) /**< \brief (DMAC) Debug Control */
-#define REG_DMAC_SWTRIGCTRL        (*(RwReg  *)0x4100A010UL) /**< \brief (DMAC) Software Trigger Control */
-#define REG_DMAC_PRICTRL0          (*(RwReg  *)0x4100A014UL) /**< \brief (DMAC) Priority Control 0 */
-#define REG_DMAC_INTPEND           (*(RwReg16*)0x4100A020UL) /**< \brief (DMAC) Interrupt Pending */
-#define REG_DMAC_INTSTATUS         (*(RoReg  *)0x4100A024UL) /**< \brief (DMAC) Interrupt Status */
-#define REG_DMAC_BUSYCH            (*(RoReg  *)0x4100A028UL) /**< \brief (DMAC) Busy Channels */
-#define REG_DMAC_PENDCH            (*(RoReg  *)0x4100A02CUL) /**< \brief (DMAC) Pending Channels */
-#define REG_DMAC_ACTIVE            (*(RoReg  *)0x4100A030UL) /**< \brief (DMAC) Active Channel and Levels */
-#define REG_DMAC_BASEADDR          (*(RwReg  *)0x4100A034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
-#define REG_DMAC_WRBADDR           (*(RwReg  *)0x4100A038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
-#define REG_DMAC_CHCTRLA0          (*(RwReg  *)0x4100A040UL) /**< \brief (DMAC) Channel 0 Control A */
-#define REG_DMAC_CHCTRLB0          (*(RwReg  *)0x4100A044UL) /**< \brief (DMAC) Channel 0 Control B */
-#define REG_DMAC_CHPRILVL0         (*(RwReg  *)0x4100A045UL) /**< \brief (DMAC) Channel 0 Priority Level */
-#define REG_DMAC_CHEVCTRL0         (*(RwReg  *)0x4100A046UL) /**< \brief (DMAC) Channel 0 Event Control */
-#define REG_DMAC_CHINTENCLR0       (*(RwReg  *)0x4100A04CUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET0       (*(RwReg  *)0x4100A04DUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG0        (*(RwReg  *)0x4100A04EUL) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS0         (*(RwReg  *)0x4100A04FUL) /**< \brief (DMAC) Channel 0 Status */
-#define REG_DMAC_CHCTRLA1          (*(RwReg  *)0x4100A050UL) /**< \brief (DMAC) Channel 1 Control A */
-#define REG_DMAC_CHCTRLB1          (*(RwReg  *)0x4100A054UL) /**< \brief (DMAC) Channel 1 Control B */
-#define REG_DMAC_CHPRILVL1         (*(RwReg  *)0x4100A055UL) /**< \brief (DMAC) Channel 1 Priority Level */
-#define REG_DMAC_CHEVCTRL1         (*(RwReg  *)0x4100A056UL) /**< \brief (DMAC) Channel 1 Event Control */
-#define REG_DMAC_CHINTENCLR1       (*(RwReg  *)0x4100A05CUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET1       (*(RwReg  *)0x4100A05DUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG1        (*(RwReg  *)0x4100A05EUL) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS1         (*(RwReg  *)0x4100A05FUL) /**< \brief (DMAC) Channel 1 Status */
-#define REG_DMAC_CHCTRLA2          (*(RwReg  *)0x4100A060UL) /**< \brief (DMAC) Channel 2 Control A */
-#define REG_DMAC_CHCTRLB2          (*(RwReg  *)0x4100A064UL) /**< \brief (DMAC) Channel 2 Control B */
-#define REG_DMAC_CHPRILVL2         (*(RwReg  *)0x4100A065UL) /**< \brief (DMAC) Channel 2 Priority Level */
-#define REG_DMAC_CHEVCTRL2         (*(RwReg  *)0x4100A066UL) /**< \brief (DMAC) Channel 2 Event Control */
-#define REG_DMAC_CHINTENCLR2       (*(RwReg  *)0x4100A06CUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET2       (*(RwReg  *)0x4100A06DUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG2        (*(RwReg  *)0x4100A06EUL) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS2         (*(RwReg  *)0x4100A06FUL) /**< \brief (DMAC) Channel 2 Status */
-#define REG_DMAC_CHCTRLA3          (*(RwReg  *)0x4100A070UL) /**< \brief (DMAC) Channel 3 Control A */
-#define REG_DMAC_CHCTRLB3          (*(RwReg  *)0x4100A074UL) /**< \brief (DMAC) Channel 3 Control B */
-#define REG_DMAC_CHPRILVL3         (*(RwReg  *)0x4100A075UL) /**< \brief (DMAC) Channel 3 Priority Level */
-#define REG_DMAC_CHEVCTRL3         (*(RwReg  *)0x4100A076UL) /**< \brief (DMAC) Channel 3 Event Control */
-#define REG_DMAC_CHINTENCLR3       (*(RwReg  *)0x4100A07CUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET3       (*(RwReg  *)0x4100A07DUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG3        (*(RwReg  *)0x4100A07EUL) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS3         (*(RwReg  *)0x4100A07FUL) /**< \brief (DMAC) Channel 3 Status */
-#define REG_DMAC_CHCTRLA4          (*(RwReg  *)0x4100A080UL) /**< \brief (DMAC) Channel 4 Control A */
-#define REG_DMAC_CHCTRLB4          (*(RwReg  *)0x4100A084UL) /**< \brief (DMAC) Channel 4 Control B */
-#define REG_DMAC_CHPRILVL4         (*(RwReg  *)0x4100A085UL) /**< \brief (DMAC) Channel 4 Priority Level */
-#define REG_DMAC_CHEVCTRL4         (*(RwReg  *)0x4100A086UL) /**< \brief (DMAC) Channel 4 Event Control */
-#define REG_DMAC_CHINTENCLR4       (*(RwReg  *)0x4100A08CUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET4       (*(RwReg  *)0x4100A08DUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG4        (*(RwReg  *)0x4100A08EUL) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS4         (*(RwReg  *)0x4100A08FUL) /**< \brief (DMAC) Channel 4 Status */
-#define REG_DMAC_CHCTRLA5          (*(RwReg  *)0x4100A090UL) /**< \brief (DMAC) Channel 5 Control A */
-#define REG_DMAC_CHCTRLB5          (*(RwReg  *)0x4100A094UL) /**< \brief (DMAC) Channel 5 Control B */
-#define REG_DMAC_CHPRILVL5         (*(RwReg  *)0x4100A095UL) /**< \brief (DMAC) Channel 5 Priority Level */
-#define REG_DMAC_CHEVCTRL5         (*(RwReg  *)0x4100A096UL) /**< \brief (DMAC) Channel 5 Event Control */
-#define REG_DMAC_CHINTENCLR5       (*(RwReg  *)0x4100A09CUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET5       (*(RwReg  *)0x4100A09DUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG5        (*(RwReg  *)0x4100A09EUL) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS5         (*(RwReg  *)0x4100A09FUL) /**< \brief (DMAC) Channel 5 Status */
-#define REG_DMAC_CHCTRLA6          (*(RwReg  *)0x4100A0A0UL) /**< \brief (DMAC) Channel 6 Control A */
-#define REG_DMAC_CHCTRLB6          (*(RwReg  *)0x4100A0A4UL) /**< \brief (DMAC) Channel 6 Control B */
-#define REG_DMAC_CHPRILVL6         (*(RwReg  *)0x4100A0A5UL) /**< \brief (DMAC) Channel 6 Priority Level */
-#define REG_DMAC_CHEVCTRL6         (*(RwReg  *)0x4100A0A6UL) /**< \brief (DMAC) Channel 6 Event Control */
-#define REG_DMAC_CHINTENCLR6       (*(RwReg  *)0x4100A0ACUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET6       (*(RwReg  *)0x4100A0ADUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG6        (*(RwReg  *)0x4100A0AEUL) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS6         (*(RwReg  *)0x4100A0AFUL) /**< \brief (DMAC) Channel 6 Status */
-#define REG_DMAC_CHCTRLA7          (*(RwReg  *)0x4100A0B0UL) /**< \brief (DMAC) Channel 7 Control A */
-#define REG_DMAC_CHCTRLB7          (*(RwReg  *)0x4100A0B4UL) /**< \brief (DMAC) Channel 7 Control B */
-#define REG_DMAC_CHPRILVL7         (*(RwReg  *)0x4100A0B5UL) /**< \brief (DMAC) Channel 7 Priority Level */
-#define REG_DMAC_CHEVCTRL7         (*(RwReg  *)0x4100A0B6UL) /**< \brief (DMAC) Channel 7 Event Control */
-#define REG_DMAC_CHINTENCLR7       (*(RwReg  *)0x4100A0BCUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET7       (*(RwReg  *)0x4100A0BDUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG7        (*(RwReg  *)0x4100A0BEUL) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS7         (*(RwReg  *)0x4100A0BFUL) /**< \brief (DMAC) Channel 7 Status */
-#define REG_DMAC_CHCTRLA8          (*(RwReg  *)0x4100A0C0UL) /**< \brief (DMAC) Channel 8 Control A */
-#define REG_DMAC_CHCTRLB8          (*(RwReg  *)0x4100A0C4UL) /**< \brief (DMAC) Channel 8 Control B */
-#define REG_DMAC_CHPRILVL8         (*(RwReg  *)0x4100A0C5UL) /**< \brief (DMAC) Channel 8 Priority Level */
-#define REG_DMAC_CHEVCTRL8         (*(RwReg  *)0x4100A0C6UL) /**< \brief (DMAC) Channel 8 Event Control */
-#define REG_DMAC_CHINTENCLR8       (*(RwReg  *)0x4100A0CCUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET8       (*(RwReg  *)0x4100A0CDUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG8        (*(RwReg  *)0x4100A0CEUL) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS8         (*(RwReg  *)0x4100A0CFUL) /**< \brief (DMAC) Channel 8 Status */
-#define REG_DMAC_CHCTRLA9          (*(RwReg  *)0x4100A0D0UL) /**< \brief (DMAC) Channel 9 Control A */
-#define REG_DMAC_CHCTRLB9          (*(RwReg  *)0x4100A0D4UL) /**< \brief (DMAC) Channel 9 Control B */
-#define REG_DMAC_CHPRILVL9         (*(RwReg  *)0x4100A0D5UL) /**< \brief (DMAC) Channel 9 Priority Level */
-#define REG_DMAC_CHEVCTRL9         (*(RwReg  *)0x4100A0D6UL) /**< \brief (DMAC) Channel 9 Event Control */
-#define REG_DMAC_CHINTENCLR9       (*(RwReg  *)0x4100A0DCUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET9       (*(RwReg  *)0x4100A0DDUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG9        (*(RwReg  *)0x4100A0DEUL) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS9         (*(RwReg  *)0x4100A0DFUL) /**< \brief (DMAC) Channel 9 Status */
-#define REG_DMAC_CHCTRLA10         (*(RwReg  *)0x4100A0E0UL) /**< \brief (DMAC) Channel 10 Control A */
-#define REG_DMAC_CHCTRLB10         (*(RwReg  *)0x4100A0E4UL) /**< \brief (DMAC) Channel 10 Control B */
-#define REG_DMAC_CHPRILVL10        (*(RwReg  *)0x4100A0E5UL) /**< \brief (DMAC) Channel 10 Priority Level */
-#define REG_DMAC_CHEVCTRL10        (*(RwReg  *)0x4100A0E6UL) /**< \brief (DMAC) Channel 10 Event Control */
-#define REG_DMAC_CHINTENCLR10      (*(RwReg  *)0x4100A0ECUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET10      (*(RwReg  *)0x4100A0EDUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG10       (*(RwReg  *)0x4100A0EEUL) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS10        (*(RwReg  *)0x4100A0EFUL) /**< \brief (DMAC) Channel 10 Status */
-#define REG_DMAC_CHCTRLA11         (*(RwReg  *)0x4100A0F0UL) /**< \brief (DMAC) Channel 11 Control A */
-#define REG_DMAC_CHCTRLB11         (*(RwReg  *)0x4100A0F4UL) /**< \brief (DMAC) Channel 11 Control B */
-#define REG_DMAC_CHPRILVL11        (*(RwReg  *)0x4100A0F5UL) /**< \brief (DMAC) Channel 11 Priority Level */
-#define REG_DMAC_CHEVCTRL11        (*(RwReg  *)0x4100A0F6UL) /**< \brief (DMAC) Channel 11 Event Control */
-#define REG_DMAC_CHINTENCLR11      (*(RwReg  *)0x4100A0FCUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET11      (*(RwReg  *)0x4100A0FDUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG11       (*(RwReg  *)0x4100A0FEUL) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS11        (*(RwReg  *)0x4100A0FFUL) /**< \brief (DMAC) Channel 11 Status */
-#define REG_DMAC_CHCTRLA12         (*(RwReg  *)0x4100A100UL) /**< \brief (DMAC) Channel 12 Control A */
-#define REG_DMAC_CHCTRLB12         (*(RwReg  *)0x4100A104UL) /**< \brief (DMAC) Channel 12 Control B */
-#define REG_DMAC_CHPRILVL12        (*(RwReg  *)0x4100A105UL) /**< \brief (DMAC) Channel 12 Priority Level */
-#define REG_DMAC_CHEVCTRL12        (*(RwReg  *)0x4100A106UL) /**< \brief (DMAC) Channel 12 Event Control */
-#define REG_DMAC_CHINTENCLR12      (*(RwReg  *)0x4100A10CUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET12      (*(RwReg  *)0x4100A10DUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG12       (*(RwReg  *)0x4100A10EUL) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS12        (*(RwReg  *)0x4100A10FUL) /**< \brief (DMAC) Channel 12 Status */
-#define REG_DMAC_CHCTRLA13         (*(RwReg  *)0x4100A110UL) /**< \brief (DMAC) Channel 13 Control A */
-#define REG_DMAC_CHCTRLB13         (*(RwReg  *)0x4100A114UL) /**< \brief (DMAC) Channel 13 Control B */
-#define REG_DMAC_CHPRILVL13        (*(RwReg  *)0x4100A115UL) /**< \brief (DMAC) Channel 13 Priority Level */
-#define REG_DMAC_CHEVCTRL13        (*(RwReg  *)0x4100A116UL) /**< \brief (DMAC) Channel 13 Event Control */
-#define REG_DMAC_CHINTENCLR13      (*(RwReg  *)0x4100A11CUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET13      (*(RwReg  *)0x4100A11DUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG13       (*(RwReg  *)0x4100A11EUL) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS13        (*(RwReg  *)0x4100A11FUL) /**< \brief (DMAC) Channel 13 Status */
-#define REG_DMAC_CHCTRLA14         (*(RwReg  *)0x4100A120UL) /**< \brief (DMAC) Channel 14 Control A */
-#define REG_DMAC_CHCTRLB14         (*(RwReg  *)0x4100A124UL) /**< \brief (DMAC) Channel 14 Control B */
-#define REG_DMAC_CHPRILVL14        (*(RwReg  *)0x4100A125UL) /**< \brief (DMAC) Channel 14 Priority Level */
-#define REG_DMAC_CHEVCTRL14        (*(RwReg  *)0x4100A126UL) /**< \brief (DMAC) Channel 14 Event Control */
-#define REG_DMAC_CHINTENCLR14      (*(RwReg  *)0x4100A12CUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET14      (*(RwReg  *)0x4100A12DUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG14       (*(RwReg  *)0x4100A12EUL) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS14        (*(RwReg  *)0x4100A12FUL) /**< \brief (DMAC) Channel 14 Status */
-#define REG_DMAC_CHCTRLA15         (*(RwReg  *)0x4100A130UL) /**< \brief (DMAC) Channel 15 Control A */
-#define REG_DMAC_CHCTRLB15         (*(RwReg  *)0x4100A134UL) /**< \brief (DMAC) Channel 15 Control B */
-#define REG_DMAC_CHPRILVL15        (*(RwReg  *)0x4100A135UL) /**< \brief (DMAC) Channel 15 Priority Level */
-#define REG_DMAC_CHEVCTRL15        (*(RwReg  *)0x4100A136UL) /**< \brief (DMAC) Channel 15 Event Control */
-#define REG_DMAC_CHINTENCLR15      (*(RwReg  *)0x4100A13CUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET15      (*(RwReg  *)0x4100A13DUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG15       (*(RwReg  *)0x4100A13EUL) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS15        (*(RwReg  *)0x4100A13FUL) /**< \brief (DMAC) Channel 15 Status */
-#define REG_DMAC_CHCTRLA16         (*(RwReg  *)0x4100A140UL) /**< \brief (DMAC) Channel 16 Control A */
-#define REG_DMAC_CHCTRLB16         (*(RwReg  *)0x4100A144UL) /**< \brief (DMAC) Channel 16 Control B */
-#define REG_DMAC_CHPRILVL16        (*(RwReg  *)0x4100A145UL) /**< \brief (DMAC) Channel 16 Priority Level */
-#define REG_DMAC_CHEVCTRL16        (*(RwReg  *)0x4100A146UL) /**< \brief (DMAC) Channel 16 Event Control */
-#define REG_DMAC_CHINTENCLR16      (*(RwReg  *)0x4100A14CUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET16      (*(RwReg  *)0x4100A14DUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG16       (*(RwReg  *)0x4100A14EUL) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS16        (*(RwReg  *)0x4100A14FUL) /**< \brief (DMAC) Channel 16 Status */
-#define REG_DMAC_CHCTRLA17         (*(RwReg  *)0x4100A150UL) /**< \brief (DMAC) Channel 17 Control A */
-#define REG_DMAC_CHCTRLB17         (*(RwReg  *)0x4100A154UL) /**< \brief (DMAC) Channel 17 Control B */
-#define REG_DMAC_CHPRILVL17        (*(RwReg  *)0x4100A155UL) /**< \brief (DMAC) Channel 17 Priority Level */
-#define REG_DMAC_CHEVCTRL17        (*(RwReg  *)0x4100A156UL) /**< \brief (DMAC) Channel 17 Event Control */
-#define REG_DMAC_CHINTENCLR17      (*(RwReg  *)0x4100A15CUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET17      (*(RwReg  *)0x4100A15DUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG17       (*(RwReg  *)0x4100A15EUL) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS17        (*(RwReg  *)0x4100A15FUL) /**< \brief (DMAC) Channel 17 Status */
-#define REG_DMAC_CHCTRLA18         (*(RwReg  *)0x4100A160UL) /**< \brief (DMAC) Channel 18 Control A */
-#define REG_DMAC_CHCTRLB18         (*(RwReg  *)0x4100A164UL) /**< \brief (DMAC) Channel 18 Control B */
-#define REG_DMAC_CHPRILVL18        (*(RwReg  *)0x4100A165UL) /**< \brief (DMAC) Channel 18 Priority Level */
-#define REG_DMAC_CHEVCTRL18        (*(RwReg  *)0x4100A166UL) /**< \brief (DMAC) Channel 18 Event Control */
-#define REG_DMAC_CHINTENCLR18      (*(RwReg  *)0x4100A16CUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET18      (*(RwReg  *)0x4100A16DUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG18       (*(RwReg  *)0x4100A16EUL) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS18        (*(RwReg  *)0x4100A16FUL) /**< \brief (DMAC) Channel 18 Status */
-#define REG_DMAC_CHCTRLA19         (*(RwReg  *)0x4100A170UL) /**< \brief (DMAC) Channel 19 Control A */
-#define REG_DMAC_CHCTRLB19         (*(RwReg  *)0x4100A174UL) /**< \brief (DMAC) Channel 19 Control B */
-#define REG_DMAC_CHPRILVL19        (*(RwReg  *)0x4100A175UL) /**< \brief (DMAC) Channel 19 Priority Level */
-#define REG_DMAC_CHEVCTRL19        (*(RwReg  *)0x4100A176UL) /**< \brief (DMAC) Channel 19 Event Control */
-#define REG_DMAC_CHINTENCLR19      (*(RwReg  *)0x4100A17CUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET19      (*(RwReg  *)0x4100A17DUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG19       (*(RwReg  *)0x4100A17EUL) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS19        (*(RwReg  *)0x4100A17FUL) /**< \brief (DMAC) Channel 19 Status */
-#define REG_DMAC_CHCTRLA20         (*(RwReg  *)0x4100A180UL) /**< \brief (DMAC) Channel 20 Control A */
-#define REG_DMAC_CHCTRLB20         (*(RwReg  *)0x4100A184UL) /**< \brief (DMAC) Channel 20 Control B */
-#define REG_DMAC_CHPRILVL20        (*(RwReg  *)0x4100A185UL) /**< \brief (DMAC) Channel 20 Priority Level */
-#define REG_DMAC_CHEVCTRL20        (*(RwReg  *)0x4100A186UL) /**< \brief (DMAC) Channel 20 Event Control */
-#define REG_DMAC_CHINTENCLR20      (*(RwReg  *)0x4100A18CUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET20      (*(RwReg  *)0x4100A18DUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG20       (*(RwReg  *)0x4100A18EUL) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS20        (*(RwReg  *)0x4100A18FUL) /**< \brief (DMAC) Channel 20 Status */
-#define REG_DMAC_CHCTRLA21         (*(RwReg  *)0x4100A190UL) /**< \brief (DMAC) Channel 21 Control A */
-#define REG_DMAC_CHCTRLB21         (*(RwReg  *)0x4100A194UL) /**< \brief (DMAC) Channel 21 Control B */
-#define REG_DMAC_CHPRILVL21        (*(RwReg  *)0x4100A195UL) /**< \brief (DMAC) Channel 21 Priority Level */
-#define REG_DMAC_CHEVCTRL21        (*(RwReg  *)0x4100A196UL) /**< \brief (DMAC) Channel 21 Event Control */
-#define REG_DMAC_CHINTENCLR21      (*(RwReg  *)0x4100A19CUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET21      (*(RwReg  *)0x4100A19DUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG21       (*(RwReg  *)0x4100A19EUL) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS21        (*(RwReg  *)0x4100A19FUL) /**< \brief (DMAC) Channel 21 Status */
-#define REG_DMAC_CHCTRLA22         (*(RwReg  *)0x4100A1A0UL) /**< \brief (DMAC) Channel 22 Control A */
-#define REG_DMAC_CHCTRLB22         (*(RwReg  *)0x4100A1A4UL) /**< \brief (DMAC) Channel 22 Control B */
-#define REG_DMAC_CHPRILVL22        (*(RwReg  *)0x4100A1A5UL) /**< \brief (DMAC) Channel 22 Priority Level */
-#define REG_DMAC_CHEVCTRL22        (*(RwReg  *)0x4100A1A6UL) /**< \brief (DMAC) Channel 22 Event Control */
-#define REG_DMAC_CHINTENCLR22      (*(RwReg  *)0x4100A1ACUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET22      (*(RwReg  *)0x4100A1ADUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG22       (*(RwReg  *)0x4100A1AEUL) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS22        (*(RwReg  *)0x4100A1AFUL) /**< \brief (DMAC) Channel 22 Status */
-#define REG_DMAC_CHCTRLA23         (*(RwReg  *)0x4100A1B0UL) /**< \brief (DMAC) Channel 23 Control A */
-#define REG_DMAC_CHCTRLB23         (*(RwReg  *)0x4100A1B4UL) /**< \brief (DMAC) Channel 23 Control B */
-#define REG_DMAC_CHPRILVL23        (*(RwReg  *)0x4100A1B5UL) /**< \brief (DMAC) Channel 23 Priority Level */
-#define REG_DMAC_CHEVCTRL23        (*(RwReg  *)0x4100A1B6UL) /**< \brief (DMAC) Channel 23 Event Control */
-#define REG_DMAC_CHINTENCLR23      (*(RwReg  *)0x4100A1BCUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET23      (*(RwReg  *)0x4100A1BDUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG23       (*(RwReg  *)0x4100A1BEUL) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS23        (*(RwReg  *)0x4100A1BFUL) /**< \brief (DMAC) Channel 23 Status */
-#define REG_DMAC_CHCTRLA24         (*(RwReg  *)0x4100A1C0UL) /**< \brief (DMAC) Channel 24 Control A */
-#define REG_DMAC_CHCTRLB24         (*(RwReg  *)0x4100A1C4UL) /**< \brief (DMAC) Channel 24 Control B */
-#define REG_DMAC_CHPRILVL24        (*(RwReg  *)0x4100A1C5UL) /**< \brief (DMAC) Channel 24 Priority Level */
-#define REG_DMAC_CHEVCTRL24        (*(RwReg  *)0x4100A1C6UL) /**< \brief (DMAC) Channel 24 Event Control */
-#define REG_DMAC_CHINTENCLR24      (*(RwReg  *)0x4100A1CCUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET24      (*(RwReg  *)0x4100A1CDUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG24       (*(RwReg  *)0x4100A1CEUL) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS24        (*(RwReg  *)0x4100A1CFUL) /**< \brief (DMAC) Channel 24 Status */
-#define REG_DMAC_CHCTRLA25         (*(RwReg  *)0x4100A1D0UL) /**< \brief (DMAC) Channel 25 Control A */
-#define REG_DMAC_CHCTRLB25         (*(RwReg  *)0x4100A1D4UL) /**< \brief (DMAC) Channel 25 Control B */
-#define REG_DMAC_CHPRILVL25        (*(RwReg  *)0x4100A1D5UL) /**< \brief (DMAC) Channel 25 Priority Level */
-#define REG_DMAC_CHEVCTRL25        (*(RwReg  *)0x4100A1D6UL) /**< \brief (DMAC) Channel 25 Event Control */
-#define REG_DMAC_CHINTENCLR25      (*(RwReg  *)0x4100A1DCUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET25      (*(RwReg  *)0x4100A1DDUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG25       (*(RwReg  *)0x4100A1DEUL) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS25        (*(RwReg  *)0x4100A1DFUL) /**< \brief (DMAC) Channel 25 Status */
-#define REG_DMAC_CHCTRLA26         (*(RwReg  *)0x4100A1E0UL) /**< \brief (DMAC) Channel 26 Control A */
-#define REG_DMAC_CHCTRLB26         (*(RwReg  *)0x4100A1E4UL) /**< \brief (DMAC) Channel 26 Control B */
-#define REG_DMAC_CHPRILVL26        (*(RwReg  *)0x4100A1E5UL) /**< \brief (DMAC) Channel 26 Priority Level */
-#define REG_DMAC_CHEVCTRL26        (*(RwReg  *)0x4100A1E6UL) /**< \brief (DMAC) Channel 26 Event Control */
-#define REG_DMAC_CHINTENCLR26      (*(RwReg  *)0x4100A1ECUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET26      (*(RwReg  *)0x4100A1EDUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG26       (*(RwReg  *)0x4100A1EEUL) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS26        (*(RwReg  *)0x4100A1EFUL) /**< \brief (DMAC) Channel 26 Status */
-#define REG_DMAC_CHCTRLA27         (*(RwReg  *)0x4100A1F0UL) /**< \brief (DMAC) Channel 27 Control A */
-#define REG_DMAC_CHCTRLB27         (*(RwReg  *)0x4100A1F4UL) /**< \brief (DMAC) Channel 27 Control B */
-#define REG_DMAC_CHPRILVL27        (*(RwReg  *)0x4100A1F5UL) /**< \brief (DMAC) Channel 27 Priority Level */
-#define REG_DMAC_CHEVCTRL27        (*(RwReg  *)0x4100A1F6UL) /**< \brief (DMAC) Channel 27 Event Control */
-#define REG_DMAC_CHINTENCLR27      (*(RwReg  *)0x4100A1FCUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET27      (*(RwReg  *)0x4100A1FDUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG27       (*(RwReg  *)0x4100A1FEUL) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS27        (*(RwReg  *)0x4100A1FFUL) /**< \brief (DMAC) Channel 27 Status */
-#define REG_DMAC_CHCTRLA28         (*(RwReg  *)0x4100A200UL) /**< \brief (DMAC) Channel 28 Control A */
-#define REG_DMAC_CHCTRLB28         (*(RwReg  *)0x4100A204UL) /**< \brief (DMAC) Channel 28 Control B */
-#define REG_DMAC_CHPRILVL28        (*(RwReg  *)0x4100A205UL) /**< \brief (DMAC) Channel 28 Priority Level */
-#define REG_DMAC_CHEVCTRL28        (*(RwReg  *)0x4100A206UL) /**< \brief (DMAC) Channel 28 Event Control */
-#define REG_DMAC_CHINTENCLR28      (*(RwReg  *)0x4100A20CUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET28      (*(RwReg  *)0x4100A20DUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG28       (*(RwReg  *)0x4100A20EUL) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS28        (*(RwReg  *)0x4100A20FUL) /**< \brief (DMAC) Channel 28 Status */
-#define REG_DMAC_CHCTRLA29         (*(RwReg  *)0x4100A210UL) /**< \brief (DMAC) Channel 29 Control A */
-#define REG_DMAC_CHCTRLB29         (*(RwReg  *)0x4100A214UL) /**< \brief (DMAC) Channel 29 Control B */
-#define REG_DMAC_CHPRILVL29        (*(RwReg  *)0x4100A215UL) /**< \brief (DMAC) Channel 29 Priority Level */
-#define REG_DMAC_CHEVCTRL29        (*(RwReg  *)0x4100A216UL) /**< \brief (DMAC) Channel 29 Event Control */
-#define REG_DMAC_CHINTENCLR29      (*(RwReg  *)0x4100A21CUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET29      (*(RwReg  *)0x4100A21DUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG29       (*(RwReg  *)0x4100A21EUL) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS29        (*(RwReg  *)0x4100A21FUL) /**< \brief (DMAC) Channel 29 Status */
-#define REG_DMAC_CHCTRLA30         (*(RwReg  *)0x4100A220UL) /**< \brief (DMAC) Channel 30 Control A */
-#define REG_DMAC_CHCTRLB30         (*(RwReg  *)0x4100A224UL) /**< \brief (DMAC) Channel 30 Control B */
-#define REG_DMAC_CHPRILVL30        (*(RwReg  *)0x4100A225UL) /**< \brief (DMAC) Channel 30 Priority Level */
-#define REG_DMAC_CHEVCTRL30        (*(RwReg  *)0x4100A226UL) /**< \brief (DMAC) Channel 30 Event Control */
-#define REG_DMAC_CHINTENCLR30      (*(RwReg  *)0x4100A22CUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET30      (*(RwReg  *)0x4100A22DUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG30       (*(RwReg  *)0x4100A22EUL) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS30        (*(RwReg  *)0x4100A22FUL) /**< \brief (DMAC) Channel 30 Status */
-#define REG_DMAC_CHCTRLA31         (*(RwReg  *)0x4100A230UL) /**< \brief (DMAC) Channel 31 Control A */
-#define REG_DMAC_CHCTRLB31         (*(RwReg  *)0x4100A234UL) /**< \brief (DMAC) Channel 31 Control B */
-#define REG_DMAC_CHPRILVL31        (*(RwReg  *)0x4100A235UL) /**< \brief (DMAC) Channel 31 Priority Level */
-#define REG_DMAC_CHEVCTRL31        (*(RwReg  *)0x4100A236UL) /**< \brief (DMAC) Channel 31 Event Control */
-#define REG_DMAC_CHINTENCLR31      (*(RwReg  *)0x4100A23CUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
-#define REG_DMAC_CHINTENSET31      (*(RwReg  *)0x4100A23DUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
-#define REG_DMAC_CHINTFLAG31       (*(RwReg  *)0x4100A23EUL) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
-#define REG_DMAC_CHSTATUS31        (*(RwReg  *)0x4100A23FUL) /**< \brief (DMAC) Channel 31 Status */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for DMAC peripheral ========== */
-#define DMAC_BURST                  1        // 0: no burst support; 1: burst support
-#define DMAC_CH_BITS                5        // Number of bits to select channel
-#define DMAC_CH_NUM                 32       // Number of channels
-#define DMAC_CLK_AHB_ID             9        // AHB clock index
-#define DMAC_EVIN_NUM               8        // Number of input events
-#define DMAC_EVOUT_NUM              4        // Number of output events
-#define DMAC_FIFO_SIZE              16       // FIFO size for burst mode.
-#define DMAC_LVL_BITS               2        // Number of bits to select level priority
-#define DMAC_LVL_NUM                4        // Enable priority level number
-#define DMAC_QOSCTRL_D_RESETVALUE   2        // QOS dmac ahb interface reset value
-#define DMAC_QOSCTRL_F_RESETVALUE   2        // QOS dmac fetch interface reset value
-#define DMAC_QOSCTRL_WRB_RESETVALUE 2        // QOS dmac write back interface reset value
-#define DMAC_TRIG_BITS              7        // Number of bits to select trigger source
-#define DMAC_TRIG_NUM               85       // Number of peripheral triggers
-
-#endif /* _SAMD51_DMAC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/dsu.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/dsu.h
deleted file mode 100644
index dc0c3d2e63..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/dsu.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for DSU
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_DSU_INSTANCE_
-#define _SAMD51_DSU_INSTANCE_
-
-/* ========== Register definition for DSU peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_DSU_CTRL               (0x41002000) /**< \brief (DSU) Control */
-#define REG_DSU_STATUSA            (0x41002001) /**< \brief (DSU) Status A */
-#define REG_DSU_STATUSB            (0x41002002) /**< \brief (DSU) Status B */
-#define REG_DSU_ADDR               (0x41002004) /**< \brief (DSU) Address */
-#define REG_DSU_LENGTH             (0x41002008) /**< \brief (DSU) Length */
-#define REG_DSU_DATA               (0x4100200C) /**< \brief (DSU) Data */
-#define REG_DSU_DCC0               (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
-#define REG_DSU_DCC1               (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
-#define REG_DSU_DID                (0x41002018) /**< \brief (DSU) Device Identification */
-#define REG_DSU_CFG                (0x4100201C) /**< \brief (DSU) Configuration */
-#define REG_DSU_MBCTRL             (0x41002040) /**< \brief (DSU) MBIST Control */
-#define REG_DSU_MBCONFIG           (0x41002044) /**< \brief (DSU) MBIST Configuration */
-#define REG_DSU_MBWORD             (0x41002048) /**< \brief (DSU) MBIST Background Word */
-#define REG_DSU_MBGSTAT            (0x4100204C) /**< \brief (DSU) MBIST Global Status */
-#define REG_DSU_MBDFAIL            (0x41002050) /**< \brief (DSU) MBIST Fail Data */
-#define REG_DSU_MBDEXP             (0x41002054) /**< \brief (DSU) MBIST Expected Data */
-#define REG_DSU_MBAFAIL            (0x41002058) /**< \brief (DSU) MBIST Fail Address */
-#define REG_DSU_MBCONTEXT          (0x4100205C) /**< \brief (DSU) MBIST Fail Context */
-#define REG_DSU_MBENABLE0          (0x41002060) /**< \brief (DSU) MBIST Memory Enable 0 */
-#define REG_DSU_MBBUSY0            (0x41002068) /**< \brief (DSU) MBIST Memory Busy 0 */
-#define REG_DSU_MBSTATUS0          (0x41002070) /**< \brief (DSU) MBIST Memory Status 0 */
-#define REG_DSU_DCFG0              (0x410020F0) /**< \brief (DSU) Device Configuration 0 */
-#define REG_DSU_DCFG1              (0x410020F4) /**< \brief (DSU) Device Configuration 1 */
-#define REG_DSU_ENTRY0             (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
-#define REG_DSU_ENTRY1             (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
-#define REG_DSU_END                (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
-#define REG_DSU_MEMTYPE            (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */
-#define REG_DSU_PID4               (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
-#define REG_DSU_PID5               (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */
-#define REG_DSU_PID6               (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */
-#define REG_DSU_PID7               (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */
-#define REG_DSU_PID0               (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
-#define REG_DSU_PID1               (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
-#define REG_DSU_PID2               (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
-#define REG_DSU_PID3               (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
-#define REG_DSU_CID0               (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
-#define REG_DSU_CID1               (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
-#define REG_DSU_CID2               (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
-#define REG_DSU_CID3               (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
-#else
-#define REG_DSU_CTRL               (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
-#define REG_DSU_STATUSA            (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
-#define REG_DSU_STATUSB            (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
-#define REG_DSU_ADDR               (*(RwReg  *)0x41002004UL) /**< \brief (DSU) Address */
-#define REG_DSU_LENGTH             (*(RwReg  *)0x41002008UL) /**< \brief (DSU) Length */
-#define REG_DSU_DATA               (*(RwReg  *)0x4100200CUL) /**< \brief (DSU) Data */
-#define REG_DSU_DCC0               (*(RwReg  *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
-#define REG_DSU_DCC1               (*(RwReg  *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
-#define REG_DSU_DID                (*(RoReg  *)0x41002018UL) /**< \brief (DSU) Device Identification */
-#define REG_DSU_CFG                (*(RwReg  *)0x4100201CUL) /**< \brief (DSU) Configuration */
-#define REG_DSU_MBCTRL             (*(RwReg  *)0x41002040UL) /**< \brief (DSU) MBIST Control */
-#define REG_DSU_MBCONFIG           (*(RwReg  *)0x41002044UL) /**< \brief (DSU) MBIST Configuration */
-#define REG_DSU_MBWORD             (*(RwReg  *)0x41002048UL) /**< \brief (DSU) MBIST Background Word */
-#define REG_DSU_MBGSTAT            (*(RwReg  *)0x4100204CUL) /**< \brief (DSU) MBIST Global Status */
-#define REG_DSU_MBDFAIL            (*(RoReg  *)0x41002050UL) /**< \brief (DSU) MBIST Fail Data */
-#define REG_DSU_MBDEXP             (*(RoReg  *)0x41002054UL) /**< \brief (DSU) MBIST Expected Data */
-#define REG_DSU_MBAFAIL            (*(RoReg  *)0x41002058UL) /**< \brief (DSU) MBIST Fail Address */
-#define REG_DSU_MBCONTEXT          (*(RoReg  *)0x4100205CUL) /**< \brief (DSU) MBIST Fail Context */
-#define REG_DSU_MBENABLE0          (*(RwReg  *)0x41002060UL) /**< \brief (DSU) MBIST Memory Enable 0 */
-#define REG_DSU_MBBUSY0            (*(RoReg  *)0x41002068UL) /**< \brief (DSU) MBIST Memory Busy 0 */
-#define REG_DSU_MBSTATUS0          (*(RwReg  *)0x41002070UL) /**< \brief (DSU) MBIST Memory Status 0 */
-#define REG_DSU_DCFG0              (*(RwReg  *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */
-#define REG_DSU_DCFG1              (*(RwReg  *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */
-#define REG_DSU_ENTRY0             (*(RoReg  *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
-#define REG_DSU_ENTRY1             (*(RoReg  *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
-#define REG_DSU_END                (*(RoReg  *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
-#define REG_DSU_MEMTYPE            (*(RoReg  *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */
-#define REG_DSU_PID4               (*(RoReg  *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
-#define REG_DSU_PID5               (*(RoReg  *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */
-#define REG_DSU_PID6               (*(RoReg  *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */
-#define REG_DSU_PID7               (*(RoReg  *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */
-#define REG_DSU_PID0               (*(RoReg  *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
-#define REG_DSU_PID1               (*(RoReg  *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
-#define REG_DSU_PID2               (*(RoReg  *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
-#define REG_DSU_PID3               (*(RoReg  *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
-#define REG_DSU_CID0               (*(RoReg  *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
-#define REG_DSU_CID1               (*(RoReg  *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
-#define REG_DSU_CID2               (*(RoReg  *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
-#define REG_DSU_CID3               (*(RoReg  *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for DSU peripheral ========== */
-#define DSU_CLK_AHB_ID              4       
-#define DSU_DMAC_ID_DCC0            2        // DMAC ID for DCC0 register
-#define DSU_DMAC_ID_DCC1            3        // DMAC ID for DCC1 register
-
-#endif /* _SAMD51_DSU_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/eic.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/eic.h
deleted file mode 100644
index d4d6d3eb42..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/eic.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for EIC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_EIC_INSTANCE_
-#define _SAMD51_EIC_INSTANCE_
-
-/* ========== Register definition for EIC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_EIC_CTRLA              (0x40002800) /**< \brief (EIC) Control A */
-#define REG_EIC_NMICTRL            (0x40002801) /**< \brief (EIC) Non-Maskable Interrupt Control */
-#define REG_EIC_NMIFLAG            (0x40002802) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
-#define REG_EIC_SYNCBUSY           (0x40002804) /**< \brief (EIC) Synchronization Busy */
-#define REG_EIC_EVCTRL             (0x40002808) /**< \brief (EIC) Event Control */
-#define REG_EIC_INTENCLR           (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */
-#define REG_EIC_INTENSET           (0x40002810) /**< \brief (EIC) Interrupt Enable Set */
-#define REG_EIC_INTFLAG            (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */
-#define REG_EIC_ASYNCH             (0x40002818) /**< \brief (EIC) External Interrupt Asynchronous Mode */
-#define REG_EIC_CONFIG0            (0x4000281C) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
-#define REG_EIC_CONFIG1            (0x40002820) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
-#define REG_EIC_DEBOUNCEN          (0x40002830) /**< \brief (EIC) Debouncer Enable */
-#define REG_EIC_DPRESCALER         (0x40002834) /**< \brief (EIC) Debouncer Prescaler */
-#define REG_EIC_PINSTATE           (0x40002838) /**< \brief (EIC) Pin State */
-#else
-#define REG_EIC_CTRLA              (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control A */
-#define REG_EIC_NMICTRL            (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) Non-Maskable Interrupt Control */
-#define REG_EIC_NMIFLAG            (*(RwReg16*)0x40002802UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
-#define REG_EIC_SYNCBUSY           (*(RoReg  *)0x40002804UL) /**< \brief (EIC) Synchronization Busy */
-#define REG_EIC_EVCTRL             (*(RwReg  *)0x40002808UL) /**< \brief (EIC) Event Control */
-#define REG_EIC_INTENCLR           (*(RwReg  *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */
-#define REG_EIC_INTENSET           (*(RwReg  *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */
-#define REG_EIC_INTFLAG            (*(RwReg  *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
-#define REG_EIC_ASYNCH             (*(RwReg  *)0x40002818UL) /**< \brief (EIC) External Interrupt Asynchronous Mode */
-#define REG_EIC_CONFIG0            (*(RwReg  *)0x4000281CUL) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
-#define REG_EIC_CONFIG1            (*(RwReg  *)0x40002820UL) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
-#define REG_EIC_DEBOUNCEN          (*(RwReg  *)0x40002830UL) /**< \brief (EIC) Debouncer Enable */
-#define REG_EIC_DPRESCALER         (*(RwReg  *)0x40002834UL) /**< \brief (EIC) Debouncer Prescaler */
-#define REG_EIC_PINSTATE           (*(RoReg  *)0x40002838UL) /**< \brief (EIC) Pin State */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for EIC peripheral ========== */
-#define EIC_EXTINT_NUM              16       // Number of external interrupts
-#define EIC_GCLK_ID                 4        // Generic Clock index
-#define EIC_NUMBER_OF_CONFIG_REGS   2        // Number of CONFIG registers
-#define EIC_NUMBER_OF_DPRESCALER_REGS 2        // Number of DPRESCALER pin groups
-#define EIC_NUMBER_OF_INTERRUPTS    16       // Number of external interrupts (obsolete)
-
-#endif /* _SAMD51_EIC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/evsys.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/evsys.h
deleted file mode 100644
index 59c14905b5..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/evsys.h
+++ /dev/null
@@ -1,722 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for EVSYS
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_EVSYS_INSTANCE_
-#define _SAMD51_EVSYS_INSTANCE_
-
-/* ========== Register definition for EVSYS peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_EVSYS_CTRLA            (0x4100E000) /**< \brief (EVSYS) Control */
-#define REG_EVSYS_SWEVT            (0x4100E004) /**< \brief (EVSYS) Software Event */
-#define REG_EVSYS_PRICTRL          (0x4100E008) /**< \brief (EVSYS) Priority Control */
-#define REG_EVSYS_INTPEND          (0x4100E010) /**< \brief (EVSYS) Channel Pending Interrupt */
-#define REG_EVSYS_INTSTATUS        (0x4100E014) /**< \brief (EVSYS) Interrupt Status */
-#define REG_EVSYS_BUSYCH           (0x4100E018) /**< \brief (EVSYS) Busy Channels */
-#define REG_EVSYS_READYUSR         (0x4100E01C) /**< \brief (EVSYS) Ready Users */
-#define REG_EVSYS_CHANNEL0         (0x4100E020) /**< \brief (EVSYS) Channel 0 Control */
-#define REG_EVSYS_CHINTENCLR0      (0x4100E024) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET0      (0x4100E025) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG0       (0x4100E026) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS0        (0x4100E027) /**< \brief (EVSYS) Channel 0 Status */
-#define REG_EVSYS_CHANNEL1         (0x4100E028) /**< \brief (EVSYS) Channel 1 Control */
-#define REG_EVSYS_CHINTENCLR1      (0x4100E02C) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET1      (0x4100E02D) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG1       (0x4100E02E) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS1        (0x4100E02F) /**< \brief (EVSYS) Channel 1 Status */
-#define REG_EVSYS_CHANNEL2         (0x4100E030) /**< \brief (EVSYS) Channel 2 Control */
-#define REG_EVSYS_CHINTENCLR2      (0x4100E034) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET2      (0x4100E035) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG2       (0x4100E036) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS2        (0x4100E037) /**< \brief (EVSYS) Channel 2 Status */
-#define REG_EVSYS_CHANNEL3         (0x4100E038) /**< \brief (EVSYS) Channel 3 Control */
-#define REG_EVSYS_CHINTENCLR3      (0x4100E03C) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET3      (0x4100E03D) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG3       (0x4100E03E) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS3        (0x4100E03F) /**< \brief (EVSYS) Channel 3 Status */
-#define REG_EVSYS_CHANNEL4         (0x4100E040) /**< \brief (EVSYS) Channel 4 Control */
-#define REG_EVSYS_CHINTENCLR4      (0x4100E044) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET4      (0x4100E045) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG4       (0x4100E046) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS4        (0x4100E047) /**< \brief (EVSYS) Channel 4 Status */
-#define REG_EVSYS_CHANNEL5         (0x4100E048) /**< \brief (EVSYS) Channel 5 Control */
-#define REG_EVSYS_CHINTENCLR5      (0x4100E04C) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET5      (0x4100E04D) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG5       (0x4100E04E) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS5        (0x4100E04F) /**< \brief (EVSYS) Channel 5 Status */
-#define REG_EVSYS_CHANNEL6         (0x4100E050) /**< \brief (EVSYS) Channel 6 Control */
-#define REG_EVSYS_CHINTENCLR6      (0x4100E054) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET6      (0x4100E055) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG6       (0x4100E056) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS6        (0x4100E057) /**< \brief (EVSYS) Channel 6 Status */
-#define REG_EVSYS_CHANNEL7         (0x4100E058) /**< \brief (EVSYS) Channel 7 Control */
-#define REG_EVSYS_CHINTENCLR7      (0x4100E05C) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET7      (0x4100E05D) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG7       (0x4100E05E) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS7        (0x4100E05F) /**< \brief (EVSYS) Channel 7 Status */
-#define REG_EVSYS_CHANNEL8         (0x4100E060) /**< \brief (EVSYS) Channel 8 Control */
-#define REG_EVSYS_CHINTENCLR8      (0x4100E064) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET8      (0x4100E065) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG8       (0x4100E066) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS8        (0x4100E067) /**< \brief (EVSYS) Channel 8 Status */
-#define REG_EVSYS_CHANNEL9         (0x4100E068) /**< \brief (EVSYS) Channel 9 Control */
-#define REG_EVSYS_CHINTENCLR9      (0x4100E06C) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET9      (0x4100E06D) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG9       (0x4100E06E) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS9        (0x4100E06F) /**< \brief (EVSYS) Channel 9 Status */
-#define REG_EVSYS_CHANNEL10        (0x4100E070) /**< \brief (EVSYS) Channel 10 Control */
-#define REG_EVSYS_CHINTENCLR10     (0x4100E074) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET10     (0x4100E075) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG10      (0x4100E076) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS10       (0x4100E077) /**< \brief (EVSYS) Channel 10 Status */
-#define REG_EVSYS_CHANNEL11        (0x4100E078) /**< \brief (EVSYS) Channel 11 Control */
-#define REG_EVSYS_CHINTENCLR11     (0x4100E07C) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET11     (0x4100E07D) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG11      (0x4100E07E) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS11       (0x4100E07F) /**< \brief (EVSYS) Channel 11 Status */
-#define REG_EVSYS_CHANNEL12        (0x4100E080) /**< \brief (EVSYS) Channel 12 Control */
-#define REG_EVSYS_CHINTENCLR12     (0x4100E084) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET12     (0x4100E085) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG12      (0x4100E086) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS12       (0x4100E087) /**< \brief (EVSYS) Channel 12 Status */
-#define REG_EVSYS_CHANNEL13        (0x4100E088) /**< \brief (EVSYS) Channel 13 Control */
-#define REG_EVSYS_CHINTENCLR13     (0x4100E08C) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET13     (0x4100E08D) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG13      (0x4100E08E) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS13       (0x4100E08F) /**< \brief (EVSYS) Channel 13 Status */
-#define REG_EVSYS_CHANNEL14        (0x4100E090) /**< \brief (EVSYS) Channel 14 Control */
-#define REG_EVSYS_CHINTENCLR14     (0x4100E094) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET14     (0x4100E095) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG14      (0x4100E096) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS14       (0x4100E097) /**< \brief (EVSYS) Channel 14 Status */
-#define REG_EVSYS_CHANNEL15        (0x4100E098) /**< \brief (EVSYS) Channel 15 Control */
-#define REG_EVSYS_CHINTENCLR15     (0x4100E09C) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET15     (0x4100E09D) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG15      (0x4100E09E) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS15       (0x4100E09F) /**< \brief (EVSYS) Channel 15 Status */
-#define REG_EVSYS_CHANNEL16        (0x4100E0A0) /**< \brief (EVSYS) Channel 16 Control */
-#define REG_EVSYS_CHINTENCLR16     (0x4100E0A4) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET16     (0x4100E0A5) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG16      (0x4100E0A6) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS16       (0x4100E0A7) /**< \brief (EVSYS) Channel 16 Status */
-#define REG_EVSYS_CHANNEL17        (0x4100E0A8) /**< \brief (EVSYS) Channel 17 Control */
-#define REG_EVSYS_CHINTENCLR17     (0x4100E0AC) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET17     (0x4100E0AD) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG17      (0x4100E0AE) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS17       (0x4100E0AF) /**< \brief (EVSYS) Channel 17 Status */
-#define REG_EVSYS_CHANNEL18        (0x4100E0B0) /**< \brief (EVSYS) Channel 18 Control */
-#define REG_EVSYS_CHINTENCLR18     (0x4100E0B4) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET18     (0x4100E0B5) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG18      (0x4100E0B6) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS18       (0x4100E0B7) /**< \brief (EVSYS) Channel 18 Status */
-#define REG_EVSYS_CHANNEL19        (0x4100E0B8) /**< \brief (EVSYS) Channel 19 Control */
-#define REG_EVSYS_CHINTENCLR19     (0x4100E0BC) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET19     (0x4100E0BD) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG19      (0x4100E0BE) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS19       (0x4100E0BF) /**< \brief (EVSYS) Channel 19 Status */
-#define REG_EVSYS_CHANNEL20        (0x4100E0C0) /**< \brief (EVSYS) Channel 20 Control */
-#define REG_EVSYS_CHINTENCLR20     (0x4100E0C4) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET20     (0x4100E0C5) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG20      (0x4100E0C6) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS20       (0x4100E0C7) /**< \brief (EVSYS) Channel 20 Status */
-#define REG_EVSYS_CHANNEL21        (0x4100E0C8) /**< \brief (EVSYS) Channel 21 Control */
-#define REG_EVSYS_CHINTENCLR21     (0x4100E0CC) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET21     (0x4100E0CD) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG21      (0x4100E0CE) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS21       (0x4100E0CF) /**< \brief (EVSYS) Channel 21 Status */
-#define REG_EVSYS_CHANNEL22        (0x4100E0D0) /**< \brief (EVSYS) Channel 22 Control */
-#define REG_EVSYS_CHINTENCLR22     (0x4100E0D4) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET22     (0x4100E0D5) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG22      (0x4100E0D6) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS22       (0x4100E0D7) /**< \brief (EVSYS) Channel 22 Status */
-#define REG_EVSYS_CHANNEL23        (0x4100E0D8) /**< \brief (EVSYS) Channel 23 Control */
-#define REG_EVSYS_CHINTENCLR23     (0x4100E0DC) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET23     (0x4100E0DD) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG23      (0x4100E0DE) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS23       (0x4100E0DF) /**< \brief (EVSYS) Channel 23 Status */
-#define REG_EVSYS_CHANNEL24        (0x4100E0E0) /**< \brief (EVSYS) Channel 24 Control */
-#define REG_EVSYS_CHINTENCLR24     (0x4100E0E4) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET24     (0x4100E0E5) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG24      (0x4100E0E6) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS24       (0x4100E0E7) /**< \brief (EVSYS) Channel 24 Status */
-#define REG_EVSYS_CHANNEL25        (0x4100E0E8) /**< \brief (EVSYS) Channel 25 Control */
-#define REG_EVSYS_CHINTENCLR25     (0x4100E0EC) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET25     (0x4100E0ED) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG25      (0x4100E0EE) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS25       (0x4100E0EF) /**< \brief (EVSYS) Channel 25 Status */
-#define REG_EVSYS_CHANNEL26        (0x4100E0F0) /**< \brief (EVSYS) Channel 26 Control */
-#define REG_EVSYS_CHINTENCLR26     (0x4100E0F4) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET26     (0x4100E0F5) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG26      (0x4100E0F6) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS26       (0x4100E0F7) /**< \brief (EVSYS) Channel 26 Status */
-#define REG_EVSYS_CHANNEL27        (0x4100E0F8) /**< \brief (EVSYS) Channel 27 Control */
-#define REG_EVSYS_CHINTENCLR27     (0x4100E0FC) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET27     (0x4100E0FD) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG27      (0x4100E0FE) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS27       (0x4100E0FF) /**< \brief (EVSYS) Channel 27 Status */
-#define REG_EVSYS_CHANNEL28        (0x4100E100) /**< \brief (EVSYS) Channel 28 Control */
-#define REG_EVSYS_CHINTENCLR28     (0x4100E104) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET28     (0x4100E105) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG28      (0x4100E106) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS28       (0x4100E107) /**< \brief (EVSYS) Channel 28 Status */
-#define REG_EVSYS_CHANNEL29        (0x4100E108) /**< \brief (EVSYS) Channel 29 Control */
-#define REG_EVSYS_CHINTENCLR29     (0x4100E10C) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET29     (0x4100E10D) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG29      (0x4100E10E) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS29       (0x4100E10F) /**< \brief (EVSYS) Channel 29 Status */
-#define REG_EVSYS_CHANNEL30        (0x4100E110) /**< \brief (EVSYS) Channel 30 Control */
-#define REG_EVSYS_CHINTENCLR30     (0x4100E114) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET30     (0x4100E115) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG30      (0x4100E116) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS30       (0x4100E117) /**< \brief (EVSYS) Channel 30 Status */
-#define REG_EVSYS_CHANNEL31        (0x4100E118) /**< \brief (EVSYS) Channel 31 Control */
-#define REG_EVSYS_CHINTENCLR31     (0x4100E11C) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET31     (0x4100E11D) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG31      (0x4100E11E) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS31       (0x4100E11F) /**< \brief (EVSYS) Channel 31 Status */
-#define REG_EVSYS_USER0            (0x4100E120) /**< \brief (EVSYS) User Multiplexer 0 */
-#define REG_EVSYS_USER1            (0x4100E124) /**< \brief (EVSYS) User Multiplexer 1 */
-#define REG_EVSYS_USER2            (0x4100E128) /**< \brief (EVSYS) User Multiplexer 2 */
-#define REG_EVSYS_USER3            (0x4100E12C) /**< \brief (EVSYS) User Multiplexer 3 */
-#define REG_EVSYS_USER4            (0x4100E130) /**< \brief (EVSYS) User Multiplexer 4 */
-#define REG_EVSYS_USER5            (0x4100E134) /**< \brief (EVSYS) User Multiplexer 5 */
-#define REG_EVSYS_USER6            (0x4100E138) /**< \brief (EVSYS) User Multiplexer 6 */
-#define REG_EVSYS_USER7            (0x4100E13C) /**< \brief (EVSYS) User Multiplexer 7 */
-#define REG_EVSYS_USER8            (0x4100E140) /**< \brief (EVSYS) User Multiplexer 8 */
-#define REG_EVSYS_USER9            (0x4100E144) /**< \brief (EVSYS) User Multiplexer 9 */
-#define REG_EVSYS_USER10           (0x4100E148) /**< \brief (EVSYS) User Multiplexer 10 */
-#define REG_EVSYS_USER11           (0x4100E14C) /**< \brief (EVSYS) User Multiplexer 11 */
-#define REG_EVSYS_USER12           (0x4100E150) /**< \brief (EVSYS) User Multiplexer 12 */
-#define REG_EVSYS_USER13           (0x4100E154) /**< \brief (EVSYS) User Multiplexer 13 */
-#define REG_EVSYS_USER14           (0x4100E158) /**< \brief (EVSYS) User Multiplexer 14 */
-#define REG_EVSYS_USER15           (0x4100E15C) /**< \brief (EVSYS) User Multiplexer 15 */
-#define REG_EVSYS_USER16           (0x4100E160) /**< \brief (EVSYS) User Multiplexer 16 */
-#define REG_EVSYS_USER17           (0x4100E164) /**< \brief (EVSYS) User Multiplexer 17 */
-#define REG_EVSYS_USER18           (0x4100E168) /**< \brief (EVSYS) User Multiplexer 18 */
-#define REG_EVSYS_USER19           (0x4100E16C) /**< \brief (EVSYS) User Multiplexer 19 */
-#define REG_EVSYS_USER20           (0x4100E170) /**< \brief (EVSYS) User Multiplexer 20 */
-#define REG_EVSYS_USER21           (0x4100E174) /**< \brief (EVSYS) User Multiplexer 21 */
-#define REG_EVSYS_USER22           (0x4100E178) /**< \brief (EVSYS) User Multiplexer 22 */
-#define REG_EVSYS_USER23           (0x4100E17C) /**< \brief (EVSYS) User Multiplexer 23 */
-#define REG_EVSYS_USER24           (0x4100E180) /**< \brief (EVSYS) User Multiplexer 24 */
-#define REG_EVSYS_USER25           (0x4100E184) /**< \brief (EVSYS) User Multiplexer 25 */
-#define REG_EVSYS_USER26           (0x4100E188) /**< \brief (EVSYS) User Multiplexer 26 */
-#define REG_EVSYS_USER27           (0x4100E18C) /**< \brief (EVSYS) User Multiplexer 27 */
-#define REG_EVSYS_USER28           (0x4100E190) /**< \brief (EVSYS) User Multiplexer 28 */
-#define REG_EVSYS_USER29           (0x4100E194) /**< \brief (EVSYS) User Multiplexer 29 */
-#define REG_EVSYS_USER30           (0x4100E198) /**< \brief (EVSYS) User Multiplexer 30 */
-#define REG_EVSYS_USER31           (0x4100E19C) /**< \brief (EVSYS) User Multiplexer 31 */
-#define REG_EVSYS_USER32           (0x4100E1A0) /**< \brief (EVSYS) User Multiplexer 32 */
-#define REG_EVSYS_USER33           (0x4100E1A4) /**< \brief (EVSYS) User Multiplexer 33 */
-#define REG_EVSYS_USER34           (0x4100E1A8) /**< \brief (EVSYS) User Multiplexer 34 */
-#define REG_EVSYS_USER35           (0x4100E1AC) /**< \brief (EVSYS) User Multiplexer 35 */
-#define REG_EVSYS_USER36           (0x4100E1B0) /**< \brief (EVSYS) User Multiplexer 36 */
-#define REG_EVSYS_USER37           (0x4100E1B4) /**< \brief (EVSYS) User Multiplexer 37 */
-#define REG_EVSYS_USER38           (0x4100E1B8) /**< \brief (EVSYS) User Multiplexer 38 */
-#define REG_EVSYS_USER39           (0x4100E1BC) /**< \brief (EVSYS) User Multiplexer 39 */
-#define REG_EVSYS_USER40           (0x4100E1C0) /**< \brief (EVSYS) User Multiplexer 40 */
-#define REG_EVSYS_USER41           (0x4100E1C4) /**< \brief (EVSYS) User Multiplexer 41 */
-#define REG_EVSYS_USER42           (0x4100E1C8) /**< \brief (EVSYS) User Multiplexer 42 */
-#define REG_EVSYS_USER43           (0x4100E1CC) /**< \brief (EVSYS) User Multiplexer 43 */
-#define REG_EVSYS_USER44           (0x4100E1D0) /**< \brief (EVSYS) User Multiplexer 44 */
-#define REG_EVSYS_USER45           (0x4100E1D4) /**< \brief (EVSYS) User Multiplexer 45 */
-#define REG_EVSYS_USER46           (0x4100E1D8) /**< \brief (EVSYS) User Multiplexer 46 */
-#define REG_EVSYS_USER47           (0x4100E1DC) /**< \brief (EVSYS) User Multiplexer 47 */
-#define REG_EVSYS_USER48           (0x4100E1E0) /**< \brief (EVSYS) User Multiplexer 48 */
-#define REG_EVSYS_USER49           (0x4100E1E4) /**< \brief (EVSYS) User Multiplexer 49 */
-#define REG_EVSYS_USER50           (0x4100E1E8) /**< \brief (EVSYS) User Multiplexer 50 */
-#define REG_EVSYS_USER51           (0x4100E1EC) /**< \brief (EVSYS) User Multiplexer 51 */
-#define REG_EVSYS_USER52           (0x4100E1F0) /**< \brief (EVSYS) User Multiplexer 52 */
-#define REG_EVSYS_USER53           (0x4100E1F4) /**< \brief (EVSYS) User Multiplexer 53 */
-#define REG_EVSYS_USER54           (0x4100E1F8) /**< \brief (EVSYS) User Multiplexer 54 */
-#define REG_EVSYS_USER55           (0x4100E1FC) /**< \brief (EVSYS) User Multiplexer 55 */
-#define REG_EVSYS_USER56           (0x4100E200) /**< \brief (EVSYS) User Multiplexer 56 */
-#define REG_EVSYS_USER57           (0x4100E204) /**< \brief (EVSYS) User Multiplexer 57 */
-#define REG_EVSYS_USER58           (0x4100E208) /**< \brief (EVSYS) User Multiplexer 58 */
-#define REG_EVSYS_USER59           (0x4100E20C) /**< \brief (EVSYS) User Multiplexer 59 */
-#define REG_EVSYS_USER60           (0x4100E210) /**< \brief (EVSYS) User Multiplexer 60 */
-#define REG_EVSYS_USER61           (0x4100E214) /**< \brief (EVSYS) User Multiplexer 61 */
-#define REG_EVSYS_USER62           (0x4100E218) /**< \brief (EVSYS) User Multiplexer 62 */
-#define REG_EVSYS_USER63           (0x4100E21C) /**< \brief (EVSYS) User Multiplexer 63 */
-#define REG_EVSYS_USER64           (0x4100E220) /**< \brief (EVSYS) User Multiplexer 64 */
-#define REG_EVSYS_USER65           (0x4100E224) /**< \brief (EVSYS) User Multiplexer 65 */
-#define REG_EVSYS_USER66           (0x4100E228) /**< \brief (EVSYS) User Multiplexer 66 */
-#else
-#define REG_EVSYS_CTRLA            (*(RwReg8 *)0x4100E000UL) /**< \brief (EVSYS) Control */
-#define REG_EVSYS_SWEVT            (*(WoReg  *)0x4100E004UL) /**< \brief (EVSYS) Software Event */
-#define REG_EVSYS_PRICTRL          (*(RwReg8 *)0x4100E008UL) /**< \brief (EVSYS) Priority Control */
-#define REG_EVSYS_INTPEND          (*(RwReg16*)0x4100E010UL) /**< \brief (EVSYS) Channel Pending Interrupt */
-#define REG_EVSYS_INTSTATUS        (*(RoReg  *)0x4100E014UL) /**< \brief (EVSYS) Interrupt Status */
-#define REG_EVSYS_BUSYCH           (*(RoReg  *)0x4100E018UL) /**< \brief (EVSYS) Busy Channels */
-#define REG_EVSYS_READYUSR         (*(RoReg  *)0x4100E01CUL) /**< \brief (EVSYS) Ready Users */
-#define REG_EVSYS_CHANNEL0         (*(RwReg  *)0x4100E020UL) /**< \brief (EVSYS) Channel 0 Control */
-#define REG_EVSYS_CHINTENCLR0      (*(RwReg  *)0x4100E024UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET0      (*(RwReg  *)0x4100E025UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG0       (*(RwReg  *)0x4100E026UL) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS0        (*(RoReg  *)0x4100E027UL) /**< \brief (EVSYS) Channel 0 Status */
-#define REG_EVSYS_CHANNEL1         (*(RwReg  *)0x4100E028UL) /**< \brief (EVSYS) Channel 1 Control */
-#define REG_EVSYS_CHINTENCLR1      (*(RwReg  *)0x4100E02CUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET1      (*(RwReg  *)0x4100E02DUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG1       (*(RwReg  *)0x4100E02EUL) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS1        (*(RoReg  *)0x4100E02FUL) /**< \brief (EVSYS) Channel 1 Status */
-#define REG_EVSYS_CHANNEL2         (*(RwReg  *)0x4100E030UL) /**< \brief (EVSYS) Channel 2 Control */
-#define REG_EVSYS_CHINTENCLR2      (*(RwReg  *)0x4100E034UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET2      (*(RwReg  *)0x4100E035UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG2       (*(RwReg  *)0x4100E036UL) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS2        (*(RoReg  *)0x4100E037UL) /**< \brief (EVSYS) Channel 2 Status */
-#define REG_EVSYS_CHANNEL3         (*(RwReg  *)0x4100E038UL) /**< \brief (EVSYS) Channel 3 Control */
-#define REG_EVSYS_CHINTENCLR3      (*(RwReg  *)0x4100E03CUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET3      (*(RwReg  *)0x4100E03DUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG3       (*(RwReg  *)0x4100E03EUL) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS3        (*(RoReg  *)0x4100E03FUL) /**< \brief (EVSYS) Channel 3 Status */
-#define REG_EVSYS_CHANNEL4         (*(RwReg  *)0x4100E040UL) /**< \brief (EVSYS) Channel 4 Control */
-#define REG_EVSYS_CHINTENCLR4      (*(RwReg  *)0x4100E044UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET4      (*(RwReg  *)0x4100E045UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG4       (*(RwReg  *)0x4100E046UL) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS4        (*(RoReg  *)0x4100E047UL) /**< \brief (EVSYS) Channel 4 Status */
-#define REG_EVSYS_CHANNEL5         (*(RwReg  *)0x4100E048UL) /**< \brief (EVSYS) Channel 5 Control */
-#define REG_EVSYS_CHINTENCLR5      (*(RwReg  *)0x4100E04CUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET5      (*(RwReg  *)0x4100E04DUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG5       (*(RwReg  *)0x4100E04EUL) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS5        (*(RoReg  *)0x4100E04FUL) /**< \brief (EVSYS) Channel 5 Status */
-#define REG_EVSYS_CHANNEL6         (*(RwReg  *)0x4100E050UL) /**< \brief (EVSYS) Channel 6 Control */
-#define REG_EVSYS_CHINTENCLR6      (*(RwReg  *)0x4100E054UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET6      (*(RwReg  *)0x4100E055UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG6       (*(RwReg  *)0x4100E056UL) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS6        (*(RoReg  *)0x4100E057UL) /**< \brief (EVSYS) Channel 6 Status */
-#define REG_EVSYS_CHANNEL7         (*(RwReg  *)0x4100E058UL) /**< \brief (EVSYS) Channel 7 Control */
-#define REG_EVSYS_CHINTENCLR7      (*(RwReg  *)0x4100E05CUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET7      (*(RwReg  *)0x4100E05DUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG7       (*(RwReg  *)0x4100E05EUL) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS7        (*(RoReg  *)0x4100E05FUL) /**< \brief (EVSYS) Channel 7 Status */
-#define REG_EVSYS_CHANNEL8         (*(RwReg  *)0x4100E060UL) /**< \brief (EVSYS) Channel 8 Control */
-#define REG_EVSYS_CHINTENCLR8      (*(RwReg  *)0x4100E064UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET8      (*(RwReg  *)0x4100E065UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG8       (*(RwReg  *)0x4100E066UL) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS8        (*(RoReg  *)0x4100E067UL) /**< \brief (EVSYS) Channel 8 Status */
-#define REG_EVSYS_CHANNEL9         (*(RwReg  *)0x4100E068UL) /**< \brief (EVSYS) Channel 9 Control */
-#define REG_EVSYS_CHINTENCLR9      (*(RwReg  *)0x4100E06CUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET9      (*(RwReg  *)0x4100E06DUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG9       (*(RwReg  *)0x4100E06EUL) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS9        (*(RoReg  *)0x4100E06FUL) /**< \brief (EVSYS) Channel 9 Status */
-#define REG_EVSYS_CHANNEL10        (*(RwReg  *)0x4100E070UL) /**< \brief (EVSYS) Channel 10 Control */
-#define REG_EVSYS_CHINTENCLR10     (*(RwReg  *)0x4100E074UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET10     (*(RwReg  *)0x4100E075UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG10      (*(RwReg  *)0x4100E076UL) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS10       (*(RoReg  *)0x4100E077UL) /**< \brief (EVSYS) Channel 10 Status */
-#define REG_EVSYS_CHANNEL11        (*(RwReg  *)0x4100E078UL) /**< \brief (EVSYS) Channel 11 Control */
-#define REG_EVSYS_CHINTENCLR11     (*(RwReg  *)0x4100E07CUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET11     (*(RwReg  *)0x4100E07DUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG11      (*(RwReg  *)0x4100E07EUL) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS11       (*(RoReg  *)0x4100E07FUL) /**< \brief (EVSYS) Channel 11 Status */
-#define REG_EVSYS_CHANNEL12        (*(RwReg  *)0x4100E080UL) /**< \brief (EVSYS) Channel 12 Control */
-#define REG_EVSYS_CHINTENCLR12     (*(RwReg  *)0x4100E084UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET12     (*(RwReg  *)0x4100E085UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG12      (*(RwReg  *)0x4100E086UL) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS12       (*(RoReg  *)0x4100E087UL) /**< \brief (EVSYS) Channel 12 Status */
-#define REG_EVSYS_CHANNEL13        (*(RwReg  *)0x4100E088UL) /**< \brief (EVSYS) Channel 13 Control */
-#define REG_EVSYS_CHINTENCLR13     (*(RwReg  *)0x4100E08CUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET13     (*(RwReg  *)0x4100E08DUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG13      (*(RwReg  *)0x4100E08EUL) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS13       (*(RoReg  *)0x4100E08FUL) /**< \brief (EVSYS) Channel 13 Status */
-#define REG_EVSYS_CHANNEL14        (*(RwReg  *)0x4100E090UL) /**< \brief (EVSYS) Channel 14 Control */
-#define REG_EVSYS_CHINTENCLR14     (*(RwReg  *)0x4100E094UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET14     (*(RwReg  *)0x4100E095UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG14      (*(RwReg  *)0x4100E096UL) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS14       (*(RoReg  *)0x4100E097UL) /**< \brief (EVSYS) Channel 14 Status */
-#define REG_EVSYS_CHANNEL15        (*(RwReg  *)0x4100E098UL) /**< \brief (EVSYS) Channel 15 Control */
-#define REG_EVSYS_CHINTENCLR15     (*(RwReg  *)0x4100E09CUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET15     (*(RwReg  *)0x4100E09DUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG15      (*(RwReg  *)0x4100E09EUL) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS15       (*(RoReg  *)0x4100E09FUL) /**< \brief (EVSYS) Channel 15 Status */
-#define REG_EVSYS_CHANNEL16        (*(RwReg  *)0x4100E0A0UL) /**< \brief (EVSYS) Channel 16 Control */
-#define REG_EVSYS_CHINTENCLR16     (*(RwReg  *)0x4100E0A4UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET16     (*(RwReg  *)0x4100E0A5UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG16      (*(RwReg  *)0x4100E0A6UL) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS16       (*(RoReg  *)0x4100E0A7UL) /**< \brief (EVSYS) Channel 16 Status */
-#define REG_EVSYS_CHANNEL17        (*(RwReg  *)0x4100E0A8UL) /**< \brief (EVSYS) Channel 17 Control */
-#define REG_EVSYS_CHINTENCLR17     (*(RwReg  *)0x4100E0ACUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET17     (*(RwReg  *)0x4100E0ADUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG17      (*(RwReg  *)0x4100E0AEUL) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS17       (*(RoReg  *)0x4100E0AFUL) /**< \brief (EVSYS) Channel 17 Status */
-#define REG_EVSYS_CHANNEL18        (*(RwReg  *)0x4100E0B0UL) /**< \brief (EVSYS) Channel 18 Control */
-#define REG_EVSYS_CHINTENCLR18     (*(RwReg  *)0x4100E0B4UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET18     (*(RwReg  *)0x4100E0B5UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG18      (*(RwReg  *)0x4100E0B6UL) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS18       (*(RoReg  *)0x4100E0B7UL) /**< \brief (EVSYS) Channel 18 Status */
-#define REG_EVSYS_CHANNEL19        (*(RwReg  *)0x4100E0B8UL) /**< \brief (EVSYS) Channel 19 Control */
-#define REG_EVSYS_CHINTENCLR19     (*(RwReg  *)0x4100E0BCUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET19     (*(RwReg  *)0x4100E0BDUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG19      (*(RwReg  *)0x4100E0BEUL) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS19       (*(RoReg  *)0x4100E0BFUL) /**< \brief (EVSYS) Channel 19 Status */
-#define REG_EVSYS_CHANNEL20        (*(RwReg  *)0x4100E0C0UL) /**< \brief (EVSYS) Channel 20 Control */
-#define REG_EVSYS_CHINTENCLR20     (*(RwReg  *)0x4100E0C4UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET20     (*(RwReg  *)0x4100E0C5UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG20      (*(RwReg  *)0x4100E0C6UL) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS20       (*(RoReg  *)0x4100E0C7UL) /**< \brief (EVSYS) Channel 20 Status */
-#define REG_EVSYS_CHANNEL21        (*(RwReg  *)0x4100E0C8UL) /**< \brief (EVSYS) Channel 21 Control */
-#define REG_EVSYS_CHINTENCLR21     (*(RwReg  *)0x4100E0CCUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET21     (*(RwReg  *)0x4100E0CDUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG21      (*(RwReg  *)0x4100E0CEUL) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS21       (*(RoReg  *)0x4100E0CFUL) /**< \brief (EVSYS) Channel 21 Status */
-#define REG_EVSYS_CHANNEL22        (*(RwReg  *)0x4100E0D0UL) /**< \brief (EVSYS) Channel 22 Control */
-#define REG_EVSYS_CHINTENCLR22     (*(RwReg  *)0x4100E0D4UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET22     (*(RwReg  *)0x4100E0D5UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG22      (*(RwReg  *)0x4100E0D6UL) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS22       (*(RoReg  *)0x4100E0D7UL) /**< \brief (EVSYS) Channel 22 Status */
-#define REG_EVSYS_CHANNEL23        (*(RwReg  *)0x4100E0D8UL) /**< \brief (EVSYS) Channel 23 Control */
-#define REG_EVSYS_CHINTENCLR23     (*(RwReg  *)0x4100E0DCUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET23     (*(RwReg  *)0x4100E0DDUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG23      (*(RwReg  *)0x4100E0DEUL) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS23       (*(RoReg  *)0x4100E0DFUL) /**< \brief (EVSYS) Channel 23 Status */
-#define REG_EVSYS_CHANNEL24        (*(RwReg  *)0x4100E0E0UL) /**< \brief (EVSYS) Channel 24 Control */
-#define REG_EVSYS_CHINTENCLR24     (*(RwReg  *)0x4100E0E4UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET24     (*(RwReg  *)0x4100E0E5UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG24      (*(RwReg  *)0x4100E0E6UL) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS24       (*(RoReg  *)0x4100E0E7UL) /**< \brief (EVSYS) Channel 24 Status */
-#define REG_EVSYS_CHANNEL25        (*(RwReg  *)0x4100E0E8UL) /**< \brief (EVSYS) Channel 25 Control */
-#define REG_EVSYS_CHINTENCLR25     (*(RwReg  *)0x4100E0ECUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET25     (*(RwReg  *)0x4100E0EDUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG25      (*(RwReg  *)0x4100E0EEUL) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS25       (*(RoReg  *)0x4100E0EFUL) /**< \brief (EVSYS) Channel 25 Status */
-#define REG_EVSYS_CHANNEL26        (*(RwReg  *)0x4100E0F0UL) /**< \brief (EVSYS) Channel 26 Control */
-#define REG_EVSYS_CHINTENCLR26     (*(RwReg  *)0x4100E0F4UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET26     (*(RwReg  *)0x4100E0F5UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG26      (*(RwReg  *)0x4100E0F6UL) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS26       (*(RoReg  *)0x4100E0F7UL) /**< \brief (EVSYS) Channel 26 Status */
-#define REG_EVSYS_CHANNEL27        (*(RwReg  *)0x4100E0F8UL) /**< \brief (EVSYS) Channel 27 Control */
-#define REG_EVSYS_CHINTENCLR27     (*(RwReg  *)0x4100E0FCUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET27     (*(RwReg  *)0x4100E0FDUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG27      (*(RwReg  *)0x4100E0FEUL) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS27       (*(RoReg  *)0x4100E0FFUL) /**< \brief (EVSYS) Channel 27 Status */
-#define REG_EVSYS_CHANNEL28        (*(RwReg  *)0x4100E100UL) /**< \brief (EVSYS) Channel 28 Control */
-#define REG_EVSYS_CHINTENCLR28     (*(RwReg  *)0x4100E104UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET28     (*(RwReg  *)0x4100E105UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG28      (*(RwReg  *)0x4100E106UL) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS28       (*(RoReg  *)0x4100E107UL) /**< \brief (EVSYS) Channel 28 Status */
-#define REG_EVSYS_CHANNEL29        (*(RwReg  *)0x4100E108UL) /**< \brief (EVSYS) Channel 29 Control */
-#define REG_EVSYS_CHINTENCLR29     (*(RwReg  *)0x4100E10CUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET29     (*(RwReg  *)0x4100E10DUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG29      (*(RwReg  *)0x4100E10EUL) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS29       (*(RoReg  *)0x4100E10FUL) /**< \brief (EVSYS) Channel 29 Status */
-#define REG_EVSYS_CHANNEL30        (*(RwReg  *)0x4100E110UL) /**< \brief (EVSYS) Channel 30 Control */
-#define REG_EVSYS_CHINTENCLR30     (*(RwReg  *)0x4100E114UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET30     (*(RwReg  *)0x4100E115UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG30      (*(RwReg  *)0x4100E116UL) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS30       (*(RoReg  *)0x4100E117UL) /**< \brief (EVSYS) Channel 30 Status */
-#define REG_EVSYS_CHANNEL31        (*(RwReg  *)0x4100E118UL) /**< \brief (EVSYS) Channel 31 Control */
-#define REG_EVSYS_CHINTENCLR31     (*(RwReg  *)0x4100E11CUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */
-#define REG_EVSYS_CHINTENSET31     (*(RwReg  *)0x4100E11DUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */
-#define REG_EVSYS_CHINTFLAG31      (*(RwReg  *)0x4100E11EUL) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */
-#define REG_EVSYS_CHSTATUS31       (*(RoReg  *)0x4100E11FUL) /**< \brief (EVSYS) Channel 31 Status */
-#define REG_EVSYS_USER0            (*(RwReg  *)0x4100E120UL) /**< \brief (EVSYS) User Multiplexer 0 */
-#define REG_EVSYS_USER1            (*(RwReg  *)0x4100E124UL) /**< \brief (EVSYS) User Multiplexer 1 */
-#define REG_EVSYS_USER2            (*(RwReg  *)0x4100E128UL) /**< \brief (EVSYS) User Multiplexer 2 */
-#define REG_EVSYS_USER3            (*(RwReg  *)0x4100E12CUL) /**< \brief (EVSYS) User Multiplexer 3 */
-#define REG_EVSYS_USER4            (*(RwReg  *)0x4100E130UL) /**< \brief (EVSYS) User Multiplexer 4 */
-#define REG_EVSYS_USER5            (*(RwReg  *)0x4100E134UL) /**< \brief (EVSYS) User Multiplexer 5 */
-#define REG_EVSYS_USER6            (*(RwReg  *)0x4100E138UL) /**< \brief (EVSYS) User Multiplexer 6 */
-#define REG_EVSYS_USER7            (*(RwReg  *)0x4100E13CUL) /**< \brief (EVSYS) User Multiplexer 7 */
-#define REG_EVSYS_USER8            (*(RwReg  *)0x4100E140UL) /**< \brief (EVSYS) User Multiplexer 8 */
-#define REG_EVSYS_USER9            (*(RwReg  *)0x4100E144UL) /**< \brief (EVSYS) User Multiplexer 9 */
-#define REG_EVSYS_USER10           (*(RwReg  *)0x4100E148UL) /**< \brief (EVSYS) User Multiplexer 10 */
-#define REG_EVSYS_USER11           (*(RwReg  *)0x4100E14CUL) /**< \brief (EVSYS) User Multiplexer 11 */
-#define REG_EVSYS_USER12           (*(RwReg  *)0x4100E150UL) /**< \brief (EVSYS) User Multiplexer 12 */
-#define REG_EVSYS_USER13           (*(RwReg  *)0x4100E154UL) /**< \brief (EVSYS) User Multiplexer 13 */
-#define REG_EVSYS_USER14           (*(RwReg  *)0x4100E158UL) /**< \brief (EVSYS) User Multiplexer 14 */
-#define REG_EVSYS_USER15           (*(RwReg  *)0x4100E15CUL) /**< \brief (EVSYS) User Multiplexer 15 */
-#define REG_EVSYS_USER16           (*(RwReg  *)0x4100E160UL) /**< \brief (EVSYS) User Multiplexer 16 */
-#define REG_EVSYS_USER17           (*(RwReg  *)0x4100E164UL) /**< \brief (EVSYS) User Multiplexer 17 */
-#define REG_EVSYS_USER18           (*(RwReg  *)0x4100E168UL) /**< \brief (EVSYS) User Multiplexer 18 */
-#define REG_EVSYS_USER19           (*(RwReg  *)0x4100E16CUL) /**< \brief (EVSYS) User Multiplexer 19 */
-#define REG_EVSYS_USER20           (*(RwReg  *)0x4100E170UL) /**< \brief (EVSYS) User Multiplexer 20 */
-#define REG_EVSYS_USER21           (*(RwReg  *)0x4100E174UL) /**< \brief (EVSYS) User Multiplexer 21 */
-#define REG_EVSYS_USER22           (*(RwReg  *)0x4100E178UL) /**< \brief (EVSYS) User Multiplexer 22 */
-#define REG_EVSYS_USER23           (*(RwReg  *)0x4100E17CUL) /**< \brief (EVSYS) User Multiplexer 23 */
-#define REG_EVSYS_USER24           (*(RwReg  *)0x4100E180UL) /**< \brief (EVSYS) User Multiplexer 24 */
-#define REG_EVSYS_USER25           (*(RwReg  *)0x4100E184UL) /**< \brief (EVSYS) User Multiplexer 25 */
-#define REG_EVSYS_USER26           (*(RwReg  *)0x4100E188UL) /**< \brief (EVSYS) User Multiplexer 26 */
-#define REG_EVSYS_USER27           (*(RwReg  *)0x4100E18CUL) /**< \brief (EVSYS) User Multiplexer 27 */
-#define REG_EVSYS_USER28           (*(RwReg  *)0x4100E190UL) /**< \brief (EVSYS) User Multiplexer 28 */
-#define REG_EVSYS_USER29           (*(RwReg  *)0x4100E194UL) /**< \brief (EVSYS) User Multiplexer 29 */
-#define REG_EVSYS_USER30           (*(RwReg  *)0x4100E198UL) /**< \brief (EVSYS) User Multiplexer 30 */
-#define REG_EVSYS_USER31           (*(RwReg  *)0x4100E19CUL) /**< \brief (EVSYS) User Multiplexer 31 */
-#define REG_EVSYS_USER32           (*(RwReg  *)0x4100E1A0UL) /**< \brief (EVSYS) User Multiplexer 32 */
-#define REG_EVSYS_USER33           (*(RwReg  *)0x4100E1A4UL) /**< \brief (EVSYS) User Multiplexer 33 */
-#define REG_EVSYS_USER34           (*(RwReg  *)0x4100E1A8UL) /**< \brief (EVSYS) User Multiplexer 34 */
-#define REG_EVSYS_USER35           (*(RwReg  *)0x4100E1ACUL) /**< \brief (EVSYS) User Multiplexer 35 */
-#define REG_EVSYS_USER36           (*(RwReg  *)0x4100E1B0UL) /**< \brief (EVSYS) User Multiplexer 36 */
-#define REG_EVSYS_USER37           (*(RwReg  *)0x4100E1B4UL) /**< \brief (EVSYS) User Multiplexer 37 */
-#define REG_EVSYS_USER38           (*(RwReg  *)0x4100E1B8UL) /**< \brief (EVSYS) User Multiplexer 38 */
-#define REG_EVSYS_USER39           (*(RwReg  *)0x4100E1BCUL) /**< \brief (EVSYS) User Multiplexer 39 */
-#define REG_EVSYS_USER40           (*(RwReg  *)0x4100E1C0UL) /**< \brief (EVSYS) User Multiplexer 40 */
-#define REG_EVSYS_USER41           (*(RwReg  *)0x4100E1C4UL) /**< \brief (EVSYS) User Multiplexer 41 */
-#define REG_EVSYS_USER42           (*(RwReg  *)0x4100E1C8UL) /**< \brief (EVSYS) User Multiplexer 42 */
-#define REG_EVSYS_USER43           (*(RwReg  *)0x4100E1CCUL) /**< \brief (EVSYS) User Multiplexer 43 */
-#define REG_EVSYS_USER44           (*(RwReg  *)0x4100E1D0UL) /**< \brief (EVSYS) User Multiplexer 44 */
-#define REG_EVSYS_USER45           (*(RwReg  *)0x4100E1D4UL) /**< \brief (EVSYS) User Multiplexer 45 */
-#define REG_EVSYS_USER46           (*(RwReg  *)0x4100E1D8UL) /**< \brief (EVSYS) User Multiplexer 46 */
-#define REG_EVSYS_USER47           (*(RwReg  *)0x4100E1DCUL) /**< \brief (EVSYS) User Multiplexer 47 */
-#define REG_EVSYS_USER48           (*(RwReg  *)0x4100E1E0UL) /**< \brief (EVSYS) User Multiplexer 48 */
-#define REG_EVSYS_USER49           (*(RwReg  *)0x4100E1E4UL) /**< \brief (EVSYS) User Multiplexer 49 */
-#define REG_EVSYS_USER50           (*(RwReg  *)0x4100E1E8UL) /**< \brief (EVSYS) User Multiplexer 50 */
-#define REG_EVSYS_USER51           (*(RwReg  *)0x4100E1ECUL) /**< \brief (EVSYS) User Multiplexer 51 */
-#define REG_EVSYS_USER52           (*(RwReg  *)0x4100E1F0UL) /**< \brief (EVSYS) User Multiplexer 52 */
-#define REG_EVSYS_USER53           (*(RwReg  *)0x4100E1F4UL) /**< \brief (EVSYS) User Multiplexer 53 */
-#define REG_EVSYS_USER54           (*(RwReg  *)0x4100E1F8UL) /**< \brief (EVSYS) User Multiplexer 54 */
-#define REG_EVSYS_USER55           (*(RwReg  *)0x4100E1FCUL) /**< \brief (EVSYS) User Multiplexer 55 */
-#define REG_EVSYS_USER56           (*(RwReg  *)0x4100E200UL) /**< \brief (EVSYS) User Multiplexer 56 */
-#define REG_EVSYS_USER57           (*(RwReg  *)0x4100E204UL) /**< \brief (EVSYS) User Multiplexer 57 */
-#define REG_EVSYS_USER58           (*(RwReg  *)0x4100E208UL) /**< \brief (EVSYS) User Multiplexer 58 */
-#define REG_EVSYS_USER59           (*(RwReg  *)0x4100E20CUL) /**< \brief (EVSYS) User Multiplexer 59 */
-#define REG_EVSYS_USER60           (*(RwReg  *)0x4100E210UL) /**< \brief (EVSYS) User Multiplexer 60 */
-#define REG_EVSYS_USER61           (*(RwReg  *)0x4100E214UL) /**< \brief (EVSYS) User Multiplexer 61 */
-#define REG_EVSYS_USER62           (*(RwReg  *)0x4100E218UL) /**< \brief (EVSYS) User Multiplexer 62 */
-#define REG_EVSYS_USER63           (*(RwReg  *)0x4100E21CUL) /**< \brief (EVSYS) User Multiplexer 63 */
-#define REG_EVSYS_USER64           (*(RwReg  *)0x4100E220UL) /**< \brief (EVSYS) User Multiplexer 64 */
-#define REG_EVSYS_USER65           (*(RwReg  *)0x4100E224UL) /**< \brief (EVSYS) User Multiplexer 65 */
-#define REG_EVSYS_USER66           (*(RwReg  *)0x4100E228UL) /**< \brief (EVSYS) User Multiplexer 66 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for EVSYS peripheral ========== */
-#define EVSYS_ASYNCHRONOUS_CHANNELS 0xFFFFF000 // Mask of Only Asynchronous Channels
-#define EVSYS_CHANNELS              32       // Total Number of Channels
-#define EVSYS_CHANNELS_BITS         5        // Number of bits to select Channel
-#define EVSYS_EXTEVT_NUM            0        // Number of External Event Generators
-#define EVSYS_GCLK_ID_0             11
-#define EVSYS_GCLK_ID_1             12
-#define EVSYS_GCLK_ID_2             13
-#define EVSYS_GCLK_ID_3             14
-#define EVSYS_GCLK_ID_4             15
-#define EVSYS_GCLK_ID_5             16
-#define EVSYS_GCLK_ID_6             17
-#define EVSYS_GCLK_ID_7             18
-#define EVSYS_GCLK_ID_8             19
-#define EVSYS_GCLK_ID_9             20
-#define EVSYS_GCLK_ID_10            21
-#define EVSYS_GCLK_ID_11            22
-#define EVSYS_GCLK_ID_LSB           11
-#define EVSYS_GCLK_ID_MSB           22
-#define EVSYS_GCLK_ID_SIZE          12
-#define EVSYS_GENERATORS            119      // Total Number of Event Generators
-#define EVSYS_GENERATORS_BITS       7        // Number of bits to select Event Generator
-#define EVSYS_SYNCH_NUM             12       // Number of Synchronous Channels
-#define EVSYS_SYNCH_NUM_BITS        4        // Number of bits to select Synchronous Channels
-#define EVSYS_USERS                 67       // Total Number of Event Users
-#define EVSYS_USERS_BITS            7        // Number of bits to select Event User
-
-// GENERATORS
-#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_0 1
-#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_1 2
-#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3
-#define EVSYS_ID_GEN_RTC_PER_0      4
-#define EVSYS_ID_GEN_RTC_PER_1      5
-#define EVSYS_ID_GEN_RTC_PER_2      6
-#define EVSYS_ID_GEN_RTC_PER_3      7
-#define EVSYS_ID_GEN_RTC_PER_4      8
-#define EVSYS_ID_GEN_RTC_PER_5      9
-#define EVSYS_ID_GEN_RTC_PER_6      10
-#define EVSYS_ID_GEN_RTC_PER_7      11
-#define EVSYS_ID_GEN_RTC_CMP_0      12
-#define EVSYS_ID_GEN_RTC_CMP_1      13
-#define EVSYS_ID_GEN_RTC_CMP_2      14
-#define EVSYS_ID_GEN_RTC_CMP_3      15
-#define EVSYS_ID_GEN_RTC_TAMPER     16
-#define EVSYS_ID_GEN_RTC_OVF        17
-#define EVSYS_ID_GEN_EIC_EXTINT_0   18
-#define EVSYS_ID_GEN_EIC_EXTINT_1   19
-#define EVSYS_ID_GEN_EIC_EXTINT_2   20
-#define EVSYS_ID_GEN_EIC_EXTINT_3   21
-#define EVSYS_ID_GEN_EIC_EXTINT_4   22
-#define EVSYS_ID_GEN_EIC_EXTINT_5   23
-#define EVSYS_ID_GEN_EIC_EXTINT_6   24
-#define EVSYS_ID_GEN_EIC_EXTINT_7   25
-#define EVSYS_ID_GEN_EIC_EXTINT_8   26
-#define EVSYS_ID_GEN_EIC_EXTINT_9   27
-#define EVSYS_ID_GEN_EIC_EXTINT_10  28
-#define EVSYS_ID_GEN_EIC_EXTINT_11  29
-#define EVSYS_ID_GEN_EIC_EXTINT_12  30
-#define EVSYS_ID_GEN_EIC_EXTINT_13  31
-#define EVSYS_ID_GEN_EIC_EXTINT_14  32
-#define EVSYS_ID_GEN_EIC_EXTINT_15  33
-#define EVSYS_ID_GEN_DMAC_CH_0      34
-#define EVSYS_ID_GEN_DMAC_CH_1      35
-#define EVSYS_ID_GEN_DMAC_CH_2      36
-#define EVSYS_ID_GEN_DMAC_CH_3      37
-#define EVSYS_ID_GEN_PAC_ACCERR     38
-#define EVSYS_ID_GEN_TAL_BRK        39
-#define EVSYS_ID_GEN_TAL_IRQMON_0   40
-#define EVSYS_ID_GEN_TCC0_OVF       41
-#define EVSYS_ID_GEN_TCC0_TRG       42
-#define EVSYS_ID_GEN_TCC0_CNT       43
-#define EVSYS_ID_GEN_TCC0_MCX_0     44
-#define EVSYS_ID_GEN_TCC0_MCX_1     45
-#define EVSYS_ID_GEN_TCC0_MCX_2     46
-#define EVSYS_ID_GEN_TCC0_MCX_3     47
-#define EVSYS_ID_GEN_TCC0_MCX_4     48
-#define EVSYS_ID_GEN_TCC0_MCX_5     49
-#define EVSYS_ID_GEN_TCC1_OVF       50
-#define EVSYS_ID_GEN_TCC1_TRG       51
-#define EVSYS_ID_GEN_TCC1_CNT       52
-#define EVSYS_ID_GEN_TCC1_MCX_0     53
-#define EVSYS_ID_GEN_TCC1_MCX_1     54
-#define EVSYS_ID_GEN_TCC1_MCX_2     55
-#define EVSYS_ID_GEN_TCC1_MCX_3     56
-#define EVSYS_ID_GEN_TCC2_OVF       57
-#define EVSYS_ID_GEN_TCC2_TRG       58
-#define EVSYS_ID_GEN_TCC2_CNT       59
-#define EVSYS_ID_GEN_TCC2_MCX_0     60
-#define EVSYS_ID_GEN_TCC2_MCX_1     61
-#define EVSYS_ID_GEN_TCC2_MCX_2     62
-#define EVSYS_ID_GEN_TCC3_OVF       63
-#define EVSYS_ID_GEN_TCC3_TRG       64
-#define EVSYS_ID_GEN_TCC3_CNT       65
-#define EVSYS_ID_GEN_TCC3_MCX_0     66
-#define EVSYS_ID_GEN_TCC3_MCX_1     67
-#define EVSYS_ID_GEN_TCC4_OVF       68
-#define EVSYS_ID_GEN_TCC4_TRG       69
-#define EVSYS_ID_GEN_TCC4_CNT       70
-#define EVSYS_ID_GEN_TCC4_MCX_0     71
-#define EVSYS_ID_GEN_TCC4_MCX_1     72
-#define EVSYS_ID_GEN_TC0_OVF        73
-#define EVSYS_ID_GEN_TC0_MCX_0      74
-#define EVSYS_ID_GEN_TC0_MCX_1      75
-#define EVSYS_ID_GEN_TC1_OVF        76
-#define EVSYS_ID_GEN_TC1_MCX_0      77
-#define EVSYS_ID_GEN_TC1_MCX_1      78
-#define EVSYS_ID_GEN_TC2_OVF        79
-#define EVSYS_ID_GEN_TC2_MCX_0      80
-#define EVSYS_ID_GEN_TC2_MCX_1      81
-#define EVSYS_ID_GEN_TC3_OVF        82
-#define EVSYS_ID_GEN_TC3_MCX_0      83
-#define EVSYS_ID_GEN_TC3_MCX_1      84
-#define EVSYS_ID_GEN_TC4_OVF        85
-#define EVSYS_ID_GEN_TC4_MCX_0      86
-#define EVSYS_ID_GEN_TC4_MCX_1      87
-#define EVSYS_ID_GEN_TC5_OVF        88
-#define EVSYS_ID_GEN_TC5_MCX_0      89
-#define EVSYS_ID_GEN_TC5_MCX_1      90
-#define EVSYS_ID_GEN_TC6_OVF        91
-#define EVSYS_ID_GEN_TC6_MCX_0      92
-#define EVSYS_ID_GEN_TC6_MCX_1      93
-#define EVSYS_ID_GEN_TC7_OVF        94
-#define EVSYS_ID_GEN_TC7_MCX_0      95
-#define EVSYS_ID_GEN_TC7_MCX_1      96
-#define EVSYS_ID_GEN_PDEC_OVF       97
-#define EVSYS_ID_GEN_PDEC_ERR       98
-#define EVSYS_ID_GEN_PDEC_DIR       99
-#define EVSYS_ID_GEN_PDEC_VLC       100
-#define EVSYS_ID_GEN_PDEC_MCX_0     101
-#define EVSYS_ID_GEN_PDEC_MCX_1     102
-#define EVSYS_ID_GEN_ADC0_RESRDY    103
-#define EVSYS_ID_GEN_ADC0_WINMON    104
-#define EVSYS_ID_GEN_ADC1_RESRDY    105
-#define EVSYS_ID_GEN_ADC1_WINMON    106
-#define EVSYS_ID_GEN_AC_COMP_0      107
-#define EVSYS_ID_GEN_AC_COMP_1      108
-#define EVSYS_ID_GEN_AC_WIN_0       109
-#define EVSYS_ID_GEN_DAC_EMPTY_0    110
-#define EVSYS_ID_GEN_DAC_EMPTY_1    111
-#define EVSYS_ID_GEN_DAC_RESRDY_0   112
-#define EVSYS_ID_GEN_DAC_RESRDY_1   113
-#define EVSYS_ID_GEN_TRNG_READY     115
-#define EVSYS_ID_GEN_CCL_LUTOUT_0   116
-#define EVSYS_ID_GEN_CCL_LUTOUT_1   117
-#define EVSYS_ID_GEN_CCL_LUTOUT_2   118
-#define EVSYS_ID_GEN_CCL_LUTOUT_3   119
-
-// USERS
-#define EVSYS_ID_USER_RTC_TAMPER    0
-#define EVSYS_ID_USER_PORT_EV_0     1
-#define EVSYS_ID_USER_PORT_EV_1     2
-#define EVSYS_ID_USER_PORT_EV_2     3
-#define EVSYS_ID_USER_PORT_EV_3     4
-#define EVSYS_ID_USER_DMAC_CH_0     5
-#define EVSYS_ID_USER_DMAC_CH_1     6
-#define EVSYS_ID_USER_DMAC_CH_2     7
-#define EVSYS_ID_USER_DMAC_CH_3     8
-#define EVSYS_ID_USER_DMAC_CH_4     9
-#define EVSYS_ID_USER_DMAC_CH_5     10
-#define EVSYS_ID_USER_DMAC_CH_6     11
-#define EVSYS_ID_USER_DMAC_CH_7     12
-#define EVSYS_ID_USER_TAL_BRK       13
-#define EVSYS_ID_USER_CM4_TRACE_START 14
-#define EVSYS_ID_USER_CM4_TRACE_STOP 15
-#define EVSYS_ID_USER_CM4_TRACE_TRIG 16
-#define EVSYS_ID_USER_TCC0_EV_0     17
-#define EVSYS_ID_USER_TCC0_EV_1     18
-#define EVSYS_ID_USER_TCC0_MC_0     19
-#define EVSYS_ID_USER_TCC0_MC_1     20
-#define EVSYS_ID_USER_TCC0_MC_2     21
-#define EVSYS_ID_USER_TCC0_MC_3     22
-#define EVSYS_ID_USER_TCC0_MC_4     23
-#define EVSYS_ID_USER_TCC0_MC_5     24
-#define EVSYS_ID_USER_TCC1_EV_0     25
-#define EVSYS_ID_USER_TCC1_EV_1     26
-#define EVSYS_ID_USER_TCC1_MC_0     27
-#define EVSYS_ID_USER_TCC1_MC_1     28
-#define EVSYS_ID_USER_TCC1_MC_2     29
-#define EVSYS_ID_USER_TCC1_MC_3     30
-#define EVSYS_ID_USER_TCC2_EV_0     31
-#define EVSYS_ID_USER_TCC2_EV_1     32
-#define EVSYS_ID_USER_TCC2_MC_0     33
-#define EVSYS_ID_USER_TCC2_MC_1     34
-#define EVSYS_ID_USER_TCC2_MC_2     35
-#define EVSYS_ID_USER_TCC3_EV_0     36
-#define EVSYS_ID_USER_TCC3_EV_1     37
-#define EVSYS_ID_USER_TCC3_MC_0     38
-#define EVSYS_ID_USER_TCC3_MC_1     39
-#define EVSYS_ID_USER_TCC4_EV_0     40
-#define EVSYS_ID_USER_TCC4_EV_1     41
-#define EVSYS_ID_USER_TCC4_MC_0     42
-#define EVSYS_ID_USER_TCC4_MC_1     43
-#define EVSYS_ID_USER_TC0_EVU       44
-#define EVSYS_ID_USER_TC1_EVU       45
-#define EVSYS_ID_USER_TC2_EVU       46
-#define EVSYS_ID_USER_TC3_EVU       47
-#define EVSYS_ID_USER_TC4_EVU       48
-#define EVSYS_ID_USER_TC5_EVU       49
-#define EVSYS_ID_USER_TC6_EVU       50
-#define EVSYS_ID_USER_TC7_EVU       51
-#define EVSYS_ID_USER_PDEC_EVU_0    52
-#define EVSYS_ID_USER_PDEC_EVU_1    53
-#define EVSYS_ID_USER_PDEC_EVU_2    54
-#define EVSYS_ID_USER_ADC0_START    55
-#define EVSYS_ID_USER_ADC0_SYNC     56
-#define EVSYS_ID_USER_ADC1_START    57
-#define EVSYS_ID_USER_ADC1_SYNC     58
-#define EVSYS_ID_USER_AC_SOC_0      59
-#define EVSYS_ID_USER_AC_SOC_1      60
-#define EVSYS_ID_USER_DAC_START_0   61
-#define EVSYS_ID_USER_DAC_START_1   62
-#define EVSYS_ID_USER_CCL_LUTIN_0   63
-#define EVSYS_ID_USER_CCL_LUTIN_1   64
-#define EVSYS_ID_USER_CCL_LUTIN_2   65
-#define EVSYS_ID_USER_CCL_LUTIN_3   66
-
-#endif /* _SAMD51_EVSYS_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/freqm.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/freqm.h
deleted file mode 100644
index 0a94593175..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/freqm.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for FREQM
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_FREQM_INSTANCE_
-#define _SAMD51_FREQM_INSTANCE_
-
-/* ========== Register definition for FREQM peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_FREQM_CTRLA            (0x40002C00) /**< \brief (FREQM) Control A Register */
-#define REG_FREQM_CTRLB            (0x40002C01) /**< \brief (FREQM) Control B Register */
-#define REG_FREQM_CFGA             (0x40002C02) /**< \brief (FREQM) Config A register */
-#define REG_FREQM_INTENCLR         (0x40002C08) /**< \brief (FREQM) Interrupt Enable Clear Register */
-#define REG_FREQM_INTENSET         (0x40002C09) /**< \brief (FREQM) Interrupt Enable Set Register */
-#define REG_FREQM_INTFLAG          (0x40002C0A) /**< \brief (FREQM) Interrupt Flag Register */
-#define REG_FREQM_STATUS           (0x40002C0B) /**< \brief (FREQM) Status Register */
-#define REG_FREQM_SYNCBUSY         (0x40002C0C) /**< \brief (FREQM) Synchronization Busy Register */
-#define REG_FREQM_VALUE            (0x40002C10) /**< \brief (FREQM) Count Value Register */
-#else
-#define REG_FREQM_CTRLA            (*(RwReg8 *)0x40002C00UL) /**< \brief (FREQM) Control A Register */
-#define REG_FREQM_CTRLB            (*(WoReg8 *)0x40002C01UL) /**< \brief (FREQM) Control B Register */
-#define REG_FREQM_CFGA             (*(RwReg16*)0x40002C02UL) /**< \brief (FREQM) Config A register */
-#define REG_FREQM_INTENCLR         (*(RwReg8 *)0x40002C08UL) /**< \brief (FREQM) Interrupt Enable Clear Register */
-#define REG_FREQM_INTENSET         (*(RwReg8 *)0x40002C09UL) /**< \brief (FREQM) Interrupt Enable Set Register */
-#define REG_FREQM_INTFLAG          (*(RwReg8 *)0x40002C0AUL) /**< \brief (FREQM) Interrupt Flag Register */
-#define REG_FREQM_STATUS           (*(RwReg8 *)0x40002C0BUL) /**< \brief (FREQM) Status Register */
-#define REG_FREQM_SYNCBUSY         (*(RoReg  *)0x40002C0CUL) /**< \brief (FREQM) Synchronization Busy Register */
-#define REG_FREQM_VALUE            (*(RoReg  *)0x40002C10UL) /**< \brief (FREQM) Count Value Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for FREQM peripheral ========== */
-#define FREQM_GCLK_ID_MSR           5        // Index of measure generic clock
-
-#endif /* _SAMD51_FREQM_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/gclk.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/gclk.h
deleted file mode 100644
index c04e384022..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/gclk.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for GCLK
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_GCLK_INSTANCE_
-#define _SAMD51_GCLK_INSTANCE_
-
-/* ========== Register definition for GCLK peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_GCLK_CTRLA             (0x40001C00) /**< \brief (GCLK) Control */
-#define REG_GCLK_SYNCBUSY          (0x40001C04) /**< \brief (GCLK) Synchronization Busy */
-#define REG_GCLK_GENCTRL0          (0x40001C20) /**< \brief (GCLK) Generic Clock Generator Control 0 */
-#define REG_GCLK_GENCTRL1          (0x40001C24) /**< \brief (GCLK) Generic Clock Generator Control 1 */
-#define REG_GCLK_GENCTRL2          (0x40001C28) /**< \brief (GCLK) Generic Clock Generator Control 2 */
-#define REG_GCLK_GENCTRL3          (0x40001C2C) /**< \brief (GCLK) Generic Clock Generator Control 3 */
-#define REG_GCLK_GENCTRL4          (0x40001C30) /**< \brief (GCLK) Generic Clock Generator Control 4 */
-#define REG_GCLK_GENCTRL5          (0x40001C34) /**< \brief (GCLK) Generic Clock Generator Control 5 */
-#define REG_GCLK_GENCTRL6          (0x40001C38) /**< \brief (GCLK) Generic Clock Generator Control 6 */
-#define REG_GCLK_GENCTRL7          (0x40001C3C) /**< \brief (GCLK) Generic Clock Generator Control 7 */
-#define REG_GCLK_GENCTRL8          (0x40001C40) /**< \brief (GCLK) Generic Clock Generator Control 8 */
-#define REG_GCLK_GENCTRL9          (0x40001C44) /**< \brief (GCLK) Generic Clock Generator Control 9 */
-#define REG_GCLK_GENCTRL10         (0x40001C48) /**< \brief (GCLK) Generic Clock Generator Control 10 */
-#define REG_GCLK_GENCTRL11         (0x40001C4C) /**< \brief (GCLK) Generic Clock Generator Control 11 */
-#define REG_GCLK_PCHCTRL0          (0x40001C80) /**< \brief (GCLK) Peripheral Clock Control 0 */
-#define REG_GCLK_PCHCTRL1          (0x40001C84) /**< \brief (GCLK) Peripheral Clock Control 1 */
-#define REG_GCLK_PCHCTRL2          (0x40001C88) /**< \brief (GCLK) Peripheral Clock Control 2 */
-#define REG_GCLK_PCHCTRL3          (0x40001C8C) /**< \brief (GCLK) Peripheral Clock Control 3 */
-#define REG_GCLK_PCHCTRL4          (0x40001C90) /**< \brief (GCLK) Peripheral Clock Control 4 */
-#define REG_GCLK_PCHCTRL5          (0x40001C94) /**< \brief (GCLK) Peripheral Clock Control 5 */
-#define REG_GCLK_PCHCTRL6          (0x40001C98) /**< \brief (GCLK) Peripheral Clock Control 6 */
-#define REG_GCLK_PCHCTRL7          (0x40001C9C) /**< \brief (GCLK) Peripheral Clock Control 7 */
-#define REG_GCLK_PCHCTRL8          (0x40001CA0) /**< \brief (GCLK) Peripheral Clock Control 8 */
-#define REG_GCLK_PCHCTRL9          (0x40001CA4) /**< \brief (GCLK) Peripheral Clock Control 9 */
-#define REG_GCLK_PCHCTRL10         (0x40001CA8) /**< \brief (GCLK) Peripheral Clock Control 10 */
-#define REG_GCLK_PCHCTRL11         (0x40001CAC) /**< \brief (GCLK) Peripheral Clock Control 11 */
-#define REG_GCLK_PCHCTRL12         (0x40001CB0) /**< \brief (GCLK) Peripheral Clock Control 12 */
-#define REG_GCLK_PCHCTRL13         (0x40001CB4) /**< \brief (GCLK) Peripheral Clock Control 13 */
-#define REG_GCLK_PCHCTRL14         (0x40001CB8) /**< \brief (GCLK) Peripheral Clock Control 14 */
-#define REG_GCLK_PCHCTRL15         (0x40001CBC) /**< \brief (GCLK) Peripheral Clock Control 15 */
-#define REG_GCLK_PCHCTRL16         (0x40001CC0) /**< \brief (GCLK) Peripheral Clock Control 16 */
-#define REG_GCLK_PCHCTRL17         (0x40001CC4) /**< \brief (GCLK) Peripheral Clock Control 17 */
-#define REG_GCLK_PCHCTRL18         (0x40001CC8) /**< \brief (GCLK) Peripheral Clock Control 18 */
-#define REG_GCLK_PCHCTRL19         (0x40001CCC) /**< \brief (GCLK) Peripheral Clock Control 19 */
-#define REG_GCLK_PCHCTRL20         (0x40001CD0) /**< \brief (GCLK) Peripheral Clock Control 20 */
-#define REG_GCLK_PCHCTRL21         (0x40001CD4) /**< \brief (GCLK) Peripheral Clock Control 21 */
-#define REG_GCLK_PCHCTRL22         (0x40001CD8) /**< \brief (GCLK) Peripheral Clock Control 22 */
-#define REG_GCLK_PCHCTRL23         (0x40001CDC) /**< \brief (GCLK) Peripheral Clock Control 23 */
-#define REG_GCLK_PCHCTRL24         (0x40001CE0) /**< \brief (GCLK) Peripheral Clock Control 24 */
-#define REG_GCLK_PCHCTRL25         (0x40001CE4) /**< \brief (GCLK) Peripheral Clock Control 25 */
-#define REG_GCLK_PCHCTRL26         (0x40001CE8) /**< \brief (GCLK) Peripheral Clock Control 26 */
-#define REG_GCLK_PCHCTRL27         (0x40001CEC) /**< \brief (GCLK) Peripheral Clock Control 27 */
-#define REG_GCLK_PCHCTRL28         (0x40001CF0) /**< \brief (GCLK) Peripheral Clock Control 28 */
-#define REG_GCLK_PCHCTRL29         (0x40001CF4) /**< \brief (GCLK) Peripheral Clock Control 29 */
-#define REG_GCLK_PCHCTRL30         (0x40001CF8) /**< \brief (GCLK) Peripheral Clock Control 30 */
-#define REG_GCLK_PCHCTRL31         (0x40001CFC) /**< \brief (GCLK) Peripheral Clock Control 31 */
-#define REG_GCLK_PCHCTRL32         (0x40001D00) /**< \brief (GCLK) Peripheral Clock Control 32 */
-#define REG_GCLK_PCHCTRL33         (0x40001D04) /**< \brief (GCLK) Peripheral Clock Control 33 */
-#define REG_GCLK_PCHCTRL34         (0x40001D08) /**< \brief (GCLK) Peripheral Clock Control 34 */
-#define REG_GCLK_PCHCTRL35         (0x40001D0C) /**< \brief (GCLK) Peripheral Clock Control 35 */
-#define REG_GCLK_PCHCTRL36         (0x40001D10) /**< \brief (GCLK) Peripheral Clock Control 36 */
-#define REG_GCLK_PCHCTRL37         (0x40001D14) /**< \brief (GCLK) Peripheral Clock Control 37 */
-#define REG_GCLK_PCHCTRL38         (0x40001D18) /**< \brief (GCLK) Peripheral Clock Control 38 */
-#define REG_GCLK_PCHCTRL39         (0x40001D1C) /**< \brief (GCLK) Peripheral Clock Control 39 */
-#define REG_GCLK_PCHCTRL40         (0x40001D20) /**< \brief (GCLK) Peripheral Clock Control 40 */
-#define REG_GCLK_PCHCTRL41         (0x40001D24) /**< \brief (GCLK) Peripheral Clock Control 41 */
-#define REG_GCLK_PCHCTRL42         (0x40001D28) /**< \brief (GCLK) Peripheral Clock Control 42 */
-#define REG_GCLK_PCHCTRL43         (0x40001D2C) /**< \brief (GCLK) Peripheral Clock Control 43 */
-#define REG_GCLK_PCHCTRL44         (0x40001D30) /**< \brief (GCLK) Peripheral Clock Control 44 */
-#define REG_GCLK_PCHCTRL45         (0x40001D34) /**< \brief (GCLK) Peripheral Clock Control 45 */
-#define REG_GCLK_PCHCTRL46         (0x40001D38) /**< \brief (GCLK) Peripheral Clock Control 46 */
-#define REG_GCLK_PCHCTRL47         (0x40001D3C) /**< \brief (GCLK) Peripheral Clock Control 47 */
-#else
-#define REG_GCLK_CTRLA             (*(RwReg8 *)0x40001C00UL) /**< \brief (GCLK) Control */
-#define REG_GCLK_SYNCBUSY          (*(RoReg  *)0x40001C04UL) /**< \brief (GCLK) Synchronization Busy */
-#define REG_GCLK_GENCTRL0          (*(RwReg  *)0x40001C20UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */
-#define REG_GCLK_GENCTRL1          (*(RwReg  *)0x40001C24UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */
-#define REG_GCLK_GENCTRL2          (*(RwReg  *)0x40001C28UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */
-#define REG_GCLK_GENCTRL3          (*(RwReg  *)0x40001C2CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */
-#define REG_GCLK_GENCTRL4          (*(RwReg  *)0x40001C30UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */
-#define REG_GCLK_GENCTRL5          (*(RwReg  *)0x40001C34UL) /**< \brief (GCLK) Generic Clock Generator Control 5 */
-#define REG_GCLK_GENCTRL6          (*(RwReg  *)0x40001C38UL) /**< \brief (GCLK) Generic Clock Generator Control 6 */
-#define REG_GCLK_GENCTRL7          (*(RwReg  *)0x40001C3CUL) /**< \brief (GCLK) Generic Clock Generator Control 7 */
-#define REG_GCLK_GENCTRL8          (*(RwReg  *)0x40001C40UL) /**< \brief (GCLK) Generic Clock Generator Control 8 */
-#define REG_GCLK_GENCTRL9          (*(RwReg  *)0x40001C44UL) /**< \brief (GCLK) Generic Clock Generator Control 9 */
-#define REG_GCLK_GENCTRL10         (*(RwReg  *)0x40001C48UL) /**< \brief (GCLK) Generic Clock Generator Control 10 */
-#define REG_GCLK_GENCTRL11         (*(RwReg  *)0x40001C4CUL) /**< \brief (GCLK) Generic Clock Generator Control 11 */
-#define REG_GCLK_PCHCTRL0          (*(RwReg  *)0x40001C80UL) /**< \brief (GCLK) Peripheral Clock Control 0 */
-#define REG_GCLK_PCHCTRL1          (*(RwReg  *)0x40001C84UL) /**< \brief (GCLK) Peripheral Clock Control 1 */
-#define REG_GCLK_PCHCTRL2          (*(RwReg  *)0x40001C88UL) /**< \brief (GCLK) Peripheral Clock Control 2 */
-#define REG_GCLK_PCHCTRL3          (*(RwReg  *)0x40001C8CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */
-#define REG_GCLK_PCHCTRL4          (*(RwReg  *)0x40001C90UL) /**< \brief (GCLK) Peripheral Clock Control 4 */
-#define REG_GCLK_PCHCTRL5          (*(RwReg  *)0x40001C94UL) /**< \brief (GCLK) Peripheral Clock Control 5 */
-#define REG_GCLK_PCHCTRL6          (*(RwReg  *)0x40001C98UL) /**< \brief (GCLK) Peripheral Clock Control 6 */
-#define REG_GCLK_PCHCTRL7          (*(RwReg  *)0x40001C9CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */
-#define REG_GCLK_PCHCTRL8          (*(RwReg  *)0x40001CA0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */
-#define REG_GCLK_PCHCTRL9          (*(RwReg  *)0x40001CA4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */
-#define REG_GCLK_PCHCTRL10         (*(RwReg  *)0x40001CA8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */
-#define REG_GCLK_PCHCTRL11         (*(RwReg  *)0x40001CACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */
-#define REG_GCLK_PCHCTRL12         (*(RwReg  *)0x40001CB0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */
-#define REG_GCLK_PCHCTRL13         (*(RwReg  *)0x40001CB4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */
-#define REG_GCLK_PCHCTRL14         (*(RwReg  *)0x40001CB8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */
-#define REG_GCLK_PCHCTRL15         (*(RwReg  *)0x40001CBCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */
-#define REG_GCLK_PCHCTRL16         (*(RwReg  *)0x40001CC0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */
-#define REG_GCLK_PCHCTRL17         (*(RwReg  *)0x40001CC4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */
-#define REG_GCLK_PCHCTRL18         (*(RwReg  *)0x40001CC8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */
-#define REG_GCLK_PCHCTRL19         (*(RwReg  *)0x40001CCCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */
-#define REG_GCLK_PCHCTRL20         (*(RwReg  *)0x40001CD0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */
-#define REG_GCLK_PCHCTRL21         (*(RwReg  *)0x40001CD4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */
-#define REG_GCLK_PCHCTRL22         (*(RwReg  *)0x40001CD8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */
-#define REG_GCLK_PCHCTRL23         (*(RwReg  *)0x40001CDCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */
-#define REG_GCLK_PCHCTRL24         (*(RwReg  *)0x40001CE0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */
-#define REG_GCLK_PCHCTRL25         (*(RwReg  *)0x40001CE4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */
-#define REG_GCLK_PCHCTRL26         (*(RwReg  *)0x40001CE8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */
-#define REG_GCLK_PCHCTRL27         (*(RwReg  *)0x40001CECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */
-#define REG_GCLK_PCHCTRL28         (*(RwReg  *)0x40001CF0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */
-#define REG_GCLK_PCHCTRL29         (*(RwReg  *)0x40001CF4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */
-#define REG_GCLK_PCHCTRL30         (*(RwReg  *)0x40001CF8UL) /**< \brief (GCLK) Peripheral Clock Control 30 */
-#define REG_GCLK_PCHCTRL31         (*(RwReg  *)0x40001CFCUL) /**< \brief (GCLK) Peripheral Clock Control 31 */
-#define REG_GCLK_PCHCTRL32         (*(RwReg  *)0x40001D00UL) /**< \brief (GCLK) Peripheral Clock Control 32 */
-#define REG_GCLK_PCHCTRL33         (*(RwReg  *)0x40001D04UL) /**< \brief (GCLK) Peripheral Clock Control 33 */
-#define REG_GCLK_PCHCTRL34         (*(RwReg  *)0x40001D08UL) /**< \brief (GCLK) Peripheral Clock Control 34 */
-#define REG_GCLK_PCHCTRL35         (*(RwReg  *)0x40001D0CUL) /**< \brief (GCLK) Peripheral Clock Control 35 */
-#define REG_GCLK_PCHCTRL36         (*(RwReg  *)0x40001D10UL) /**< \brief (GCLK) Peripheral Clock Control 36 */
-#define REG_GCLK_PCHCTRL37         (*(RwReg  *)0x40001D14UL) /**< \brief (GCLK) Peripheral Clock Control 37 */
-#define REG_GCLK_PCHCTRL38         (*(RwReg  *)0x40001D18UL) /**< \brief (GCLK) Peripheral Clock Control 38 */
-#define REG_GCLK_PCHCTRL39         (*(RwReg  *)0x40001D1CUL) /**< \brief (GCLK) Peripheral Clock Control 39 */
-#define REG_GCLK_PCHCTRL40         (*(RwReg  *)0x40001D20UL) /**< \brief (GCLK) Peripheral Clock Control 40 */
-#define REG_GCLK_PCHCTRL41         (*(RwReg  *)0x40001D24UL) /**< \brief (GCLK) Peripheral Clock Control 41 */
-#define REG_GCLK_PCHCTRL42         (*(RwReg  *)0x40001D28UL) /**< \brief (GCLK) Peripheral Clock Control 42 */
-#define REG_GCLK_PCHCTRL43         (*(RwReg  *)0x40001D2CUL) /**< \brief (GCLK) Peripheral Clock Control 43 */
-#define REG_GCLK_PCHCTRL44         (*(RwReg  *)0x40001D30UL) /**< \brief (GCLK) Peripheral Clock Control 44 */
-#define REG_GCLK_PCHCTRL45         (*(RwReg  *)0x40001D34UL) /**< \brief (GCLK) Peripheral Clock Control 45 */
-#define REG_GCLK_PCHCTRL46         (*(RwReg  *)0x40001D38UL) /**< \brief (GCLK) Peripheral Clock Control 46 */
-#define REG_GCLK_PCHCTRL47         (*(RwReg  *)0x40001D3CUL) /**< \brief (GCLK) Peripheral Clock Control 47 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for GCLK peripheral ========== */
-#define GCLK_GENCTRL0_RESETVALUE    106      // Default specific reset value for generator 0
-#define GCLK_GENDIV_BITS            16      
-#define GCLK_GEN_BITS               4       
-#define GCLK_GEN_NUM                12       // Number of Generic Clock Generators
-#define GCLK_GEN_NUM_MSB            11       // Number of Generic Clock Generators - 1
-#define GCLK_GEN_SOURCE_NUM_MSB     8        // Number of Generic Clock Sources - 1
-#define GCLK_IO_NUM                 8        // Number of Generic Clock I/Os
-#define GCLK_NUM                    48       // Number of Generic Clock Users
-#define GCLK_SOURCE_BITS            4       
-#define GCLK_SOURCE_NUM             9        // Number of Generic Clock Sources
-#define GCLK_SOURCE_XOSC0           0        // Crystal Oscillator 0
-#define GCLK_SOURCE_XOSC            0        //   Alias to GCLK_SOURCE_XOSC0
-#define GCLK_SOURCE_XOSC1           1        // Crystal Oscillator 1
-#define GCLK_SOURCE_GCLKIN          2        // Input Pin of Corresponding GCLK Generator
-#define GCLK_SOURCE_GCLKGEN1        3        // GCLK Generator 1 output
-#define GCLK_SOURCE_OSCULP32K       4        // Ultra-low-power 32kHz Oscillator
-#define GCLK_SOURCE_XOSC32K         5        // 32kHz Crystal Oscillator
-#define GCLK_SOURCE_DFLL            6        // Digital FLL
-#define GCLK_SOURCE_DFLL48M         6        //   Alias to GCLK_SOURCE_DFLL
-#define GCLK_SOURCE_OSC16M          6        //   Alias to GCLK_SOURCE_DFLL
-#define GCLK_SOURCE_OSC48M          6        //   Alias to GCLK_SOURCE_DFLL
-#define GCLK_SOURCE_DPLL0           7        // Digital PLL 0
-#define GCLK_SOURCE_FDPLL           7        //   Alias to GCLK_SOURCE_DPLL0
-#define GCLK_SOURCE_FDPLL0          7        //   Alias to GCLK_SOURCE_DPLL0
-#define GCLK_SOURCE_DPLL1           8        // Digital PLL 1
-#define GCLK_SOURCE_FDPLL1          8        //   Alias to GCLK_SOURCE_DPLL1
-#define GCLK_GEN_DIV_BITS           { 8, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8 }
-
-#endif /* _SAMD51_GCLK_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/hmatrix.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/hmatrix.h
deleted file mode 100644
index 9333d859ed..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/hmatrix.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for HMATRIX
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_HMATRIX_INSTANCE_
-#define _SAMD51_HMATRIX_INSTANCE_
-
-/* ========== Register definition for HMATRIX peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_HMATRIX_PRAS0          (0x4100C080) /**< \brief (HMATRIX) Priority A for Slave 0 */
-#define REG_HMATRIX_PRBS0          (0x4100C084) /**< \brief (HMATRIX) Priority B for Slave 0 */
-#define REG_HMATRIX_PRAS1          (0x4100C088) /**< \brief (HMATRIX) Priority A for Slave 1 */
-#define REG_HMATRIX_PRBS1          (0x4100C08C) /**< \brief (HMATRIX) Priority B for Slave 1 */
-#define REG_HMATRIX_PRAS2          (0x4100C090) /**< \brief (HMATRIX) Priority A for Slave 2 */
-#define REG_HMATRIX_PRBS2          (0x4100C094) /**< \brief (HMATRIX) Priority B for Slave 2 */
-#define REG_HMATRIX_PRAS3          (0x4100C098) /**< \brief (HMATRIX) Priority A for Slave 3 */
-#define REG_HMATRIX_PRBS3          (0x4100C09C) /**< \brief (HMATRIX) Priority B for Slave 3 */
-#define REG_HMATRIX_PRAS4          (0x4100C0A0) /**< \brief (HMATRIX) Priority A for Slave 4 */
-#define REG_HMATRIX_PRBS4          (0x4100C0A4) /**< \brief (HMATRIX) Priority B for Slave 4 */
-#define REG_HMATRIX_PRAS5          (0x4100C0A8) /**< \brief (HMATRIX) Priority A for Slave 5 */
-#define REG_HMATRIX_PRBS5          (0x4100C0AC) /**< \brief (HMATRIX) Priority B for Slave 5 */
-#define REG_HMATRIX_PRAS6          (0x4100C0B0) /**< \brief (HMATRIX) Priority A for Slave 6 */
-#define REG_HMATRIX_PRBS6          (0x4100C0B4) /**< \brief (HMATRIX) Priority B for Slave 6 */
-#define REG_HMATRIX_PRAS7          (0x4100C0B8) /**< \brief (HMATRIX) Priority A for Slave 7 */
-#define REG_HMATRIX_PRBS7          (0x4100C0BC) /**< \brief (HMATRIX) Priority B for Slave 7 */
-#define REG_HMATRIX_PRAS8          (0x4100C0C0) /**< \brief (HMATRIX) Priority A for Slave 8 */
-#define REG_HMATRIX_PRBS8          (0x4100C0C4) /**< \brief (HMATRIX) Priority B for Slave 8 */
-#define REG_HMATRIX_PRAS9          (0x4100C0C8) /**< \brief (HMATRIX) Priority A for Slave 9 */
-#define REG_HMATRIX_PRBS9          (0x4100C0CC) /**< \brief (HMATRIX) Priority B for Slave 9 */
-#define REG_HMATRIX_PRAS10         (0x4100C0D0) /**< \brief (HMATRIX) Priority A for Slave 10 */
-#define REG_HMATRIX_PRBS10         (0x4100C0D4) /**< \brief (HMATRIX) Priority B for Slave 10 */
-#define REG_HMATRIX_PRAS11         (0x4100C0D8) /**< \brief (HMATRIX) Priority A for Slave 11 */
-#define REG_HMATRIX_PRBS11         (0x4100C0DC) /**< \brief (HMATRIX) Priority B for Slave 11 */
-#define REG_HMATRIX_PRAS12         (0x4100C0E0) /**< \brief (HMATRIX) Priority A for Slave 12 */
-#define REG_HMATRIX_PRBS12         (0x4100C0E4) /**< \brief (HMATRIX) Priority B for Slave 12 */
-#define REG_HMATRIX_PRAS13         (0x4100C0E8) /**< \brief (HMATRIX) Priority A for Slave 13 */
-#define REG_HMATRIX_PRBS13         (0x4100C0EC) /**< \brief (HMATRIX) Priority B for Slave 13 */
-#define REG_HMATRIX_PRAS14         (0x4100C0F0) /**< \brief (HMATRIX) Priority A for Slave 14 */
-#define REG_HMATRIX_PRBS14         (0x4100C0F4) /**< \brief (HMATRIX) Priority B for Slave 14 */
-#define REG_HMATRIX_PRAS15         (0x4100C0F8) /**< \brief (HMATRIX) Priority A for Slave 15 */
-#define REG_HMATRIX_PRBS15         (0x4100C0FC) /**< \brief (HMATRIX) Priority B for Slave 15 */
-#else
-#define REG_HMATRIX_PRAS0          (*(RwReg  *)0x4100C080UL) /**< \brief (HMATRIX) Priority A for Slave 0 */
-#define REG_HMATRIX_PRBS0          (*(RwReg  *)0x4100C084UL) /**< \brief (HMATRIX) Priority B for Slave 0 */
-#define REG_HMATRIX_PRAS1          (*(RwReg  *)0x4100C088UL) /**< \brief (HMATRIX) Priority A for Slave 1 */
-#define REG_HMATRIX_PRBS1          (*(RwReg  *)0x4100C08CUL) /**< \brief (HMATRIX) Priority B for Slave 1 */
-#define REG_HMATRIX_PRAS2          (*(RwReg  *)0x4100C090UL) /**< \brief (HMATRIX) Priority A for Slave 2 */
-#define REG_HMATRIX_PRBS2          (*(RwReg  *)0x4100C094UL) /**< \brief (HMATRIX) Priority B for Slave 2 */
-#define REG_HMATRIX_PRAS3          (*(RwReg  *)0x4100C098UL) /**< \brief (HMATRIX) Priority A for Slave 3 */
-#define REG_HMATRIX_PRBS3          (*(RwReg  *)0x4100C09CUL) /**< \brief (HMATRIX) Priority B for Slave 3 */
-#define REG_HMATRIX_PRAS4          (*(RwReg  *)0x4100C0A0UL) /**< \brief (HMATRIX) Priority A for Slave 4 */
-#define REG_HMATRIX_PRBS4          (*(RwReg  *)0x4100C0A4UL) /**< \brief (HMATRIX) Priority B for Slave 4 */
-#define REG_HMATRIX_PRAS5          (*(RwReg  *)0x4100C0A8UL) /**< \brief (HMATRIX) Priority A for Slave 5 */
-#define REG_HMATRIX_PRBS5          (*(RwReg  *)0x4100C0ACUL) /**< \brief (HMATRIX) Priority B for Slave 5 */
-#define REG_HMATRIX_PRAS6          (*(RwReg  *)0x4100C0B0UL) /**< \brief (HMATRIX) Priority A for Slave 6 */
-#define REG_HMATRIX_PRBS6          (*(RwReg  *)0x4100C0B4UL) /**< \brief (HMATRIX) Priority B for Slave 6 */
-#define REG_HMATRIX_PRAS7          (*(RwReg  *)0x4100C0B8UL) /**< \brief (HMATRIX) Priority A for Slave 7 */
-#define REG_HMATRIX_PRBS7          (*(RwReg  *)0x4100C0BCUL) /**< \brief (HMATRIX) Priority B for Slave 7 */
-#define REG_HMATRIX_PRAS8          (*(RwReg  *)0x4100C0C0UL) /**< \brief (HMATRIX) Priority A for Slave 8 */
-#define REG_HMATRIX_PRBS8          (*(RwReg  *)0x4100C0C4UL) /**< \brief (HMATRIX) Priority B for Slave 8 */
-#define REG_HMATRIX_PRAS9          (*(RwReg  *)0x4100C0C8UL) /**< \brief (HMATRIX) Priority A for Slave 9 */
-#define REG_HMATRIX_PRBS9          (*(RwReg  *)0x4100C0CCUL) /**< \brief (HMATRIX) Priority B for Slave 9 */
-#define REG_HMATRIX_PRAS10         (*(RwReg  *)0x4100C0D0UL) /**< \brief (HMATRIX) Priority A for Slave 10 */
-#define REG_HMATRIX_PRBS10         (*(RwReg  *)0x4100C0D4UL) /**< \brief (HMATRIX) Priority B for Slave 10 */
-#define REG_HMATRIX_PRAS11         (*(RwReg  *)0x4100C0D8UL) /**< \brief (HMATRIX) Priority A for Slave 11 */
-#define REG_HMATRIX_PRBS11         (*(RwReg  *)0x4100C0DCUL) /**< \brief (HMATRIX) Priority B for Slave 11 */
-#define REG_HMATRIX_PRAS12         (*(RwReg  *)0x4100C0E0UL) /**< \brief (HMATRIX) Priority A for Slave 12 */
-#define REG_HMATRIX_PRBS12         (*(RwReg  *)0x4100C0E4UL) /**< \brief (HMATRIX) Priority B for Slave 12 */
-#define REG_HMATRIX_PRAS13         (*(RwReg  *)0x4100C0E8UL) /**< \brief (HMATRIX) Priority A for Slave 13 */
-#define REG_HMATRIX_PRBS13         (*(RwReg  *)0x4100C0ECUL) /**< \brief (HMATRIX) Priority B for Slave 13 */
-#define REG_HMATRIX_PRAS14         (*(RwReg  *)0x4100C0F0UL) /**< \brief (HMATRIX) Priority A for Slave 14 */
-#define REG_HMATRIX_PRBS14         (*(RwReg  *)0x4100C0F4UL) /**< \brief (HMATRIX) Priority B for Slave 14 */
-#define REG_HMATRIX_PRAS15         (*(RwReg  *)0x4100C0F8UL) /**< \brief (HMATRIX) Priority A for Slave 15 */
-#define REG_HMATRIX_PRBS15         (*(RwReg  *)0x4100C0FCUL) /**< \brief (HMATRIX) Priority B for Slave 15 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for HMATRIX peripheral ========== */
-#define HMATRIX_CLK_AHB_ID          5        // Index of AHB Clock in MCLK.AHBMASK register (MASK may be tied to 1 depending on chip integration)
-#define HMATRIX_DEFINED                     
-/* ========== Instance parameters for HMATRIX ========== */
-#define HMATRIX_SLAVE_FLASH         0
-#define HMATRIX_SLAVE_FLASH_ALT     1
-#define HMATRIX_SLAVE_SEEPROM       2
-#define HMATRIX_SLAVE_RAMCM4S       3
-#define HMATRIX_SLAVE_RAMPPPDSU     4
-#define HMATRIX_SLAVE_RAMDMAWR      5
-#define HMATRIX_SLAVE_RAMDMACICM    6
-#define HMATRIX_SLAVE_HPB0          7
-#define HMATRIX_SLAVE_HPB1          8
-#define HMATRIX_SLAVE_HPB2          9
-#define HMATRIX_SLAVE_HPB3          10
-#define HMATRIX_SLAVE_SDHC0         12
-#define HMATRIX_SLAVE_SDHC1         13
-#define HMATRIX_SLAVE_QSPI          14
-#define HMATRIX_SLAVE_BKUPRAM       15
-#define HMATRIX_SLAVE_NUM           16
-
-#define HMATRIX_MASTER_CM4_S        0
-#define HMATRIX_MASTER_CMCC         1
-#define HMATRIX_MASTER_PICOP_MEM    2
-#define HMATRIX_MASTER_PICOP_IO     3
-#define HMATRIX_MASTER_DMAC_DTWR    4
-#define HMATRIX_MASTER_DMAC_DTRD    5
-#define HMATRIX_MASTER_ICM          6
-#define HMATRIX_MASTER_DSU          7
-#define HMATRIX_MASTER_NUM          8
-
-#endif /* _SAMD51_HMATRIX_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/i2s.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/i2s.h
deleted file mode 100644
index 833a2b101b..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/i2s.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for I2S
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_I2S_INSTANCE_
-#define _SAMD51_I2S_INSTANCE_
-
-/* ========== Register definition for I2S peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_I2S_CTRLA              (0x43002800) /**< \brief (I2S) Control A */
-#define REG_I2S_CLKCTRL0           (0x43002804) /**< \brief (I2S) Clock Unit 0 Control */
-#define REG_I2S_CLKCTRL1           (0x43002808) /**< \brief (I2S) Clock Unit 1 Control */
-#define REG_I2S_INTENCLR           (0x4300280C) /**< \brief (I2S) Interrupt Enable Clear */
-#define REG_I2S_INTENSET           (0x43002810) /**< \brief (I2S) Interrupt Enable Set */
-#define REG_I2S_INTFLAG            (0x43002814) /**< \brief (I2S) Interrupt Flag Status and Clear */
-#define REG_I2S_SYNCBUSY           (0x43002818) /**< \brief (I2S) Synchronization Status */
-#define REG_I2S_TXCTRL             (0x43002820) /**< \brief (I2S) Tx Serializer Control */
-#define REG_I2S_RXCTRL             (0x43002824) /**< \brief (I2S) Rx Serializer Control */
-#define REG_I2S_TXDATA             (0x43002830) /**< \brief (I2S) Tx Data */
-#define REG_I2S_RXDATA             (0x43002834) /**< \brief (I2S) Rx Data */
-#else
-#define REG_I2S_CTRLA              (*(RwReg8 *)0x43002800UL) /**< \brief (I2S) Control A */
-#define REG_I2S_CLKCTRL0           (*(RwReg  *)0x43002804UL) /**< \brief (I2S) Clock Unit 0 Control */
-#define REG_I2S_CLKCTRL1           (*(RwReg  *)0x43002808UL) /**< \brief (I2S) Clock Unit 1 Control */
-#define REG_I2S_INTENCLR           (*(RwReg16*)0x4300280CUL) /**< \brief (I2S) Interrupt Enable Clear */
-#define REG_I2S_INTENSET           (*(RwReg16*)0x43002810UL) /**< \brief (I2S) Interrupt Enable Set */
-#define REG_I2S_INTFLAG            (*(RwReg16*)0x43002814UL) /**< \brief (I2S) Interrupt Flag Status and Clear */
-#define REG_I2S_SYNCBUSY           (*(RoReg16*)0x43002818UL) /**< \brief (I2S) Synchronization Status */
-#define REG_I2S_TXCTRL             (*(RwReg  *)0x43002820UL) /**< \brief (I2S) Tx Serializer Control */
-#define REG_I2S_RXCTRL             (*(RwReg  *)0x43002824UL) /**< \brief (I2S) Rx Serializer Control */
-#define REG_I2S_TXDATA             (*(WoReg  *)0x43002830UL) /**< \brief (I2S) Tx Data */
-#define REG_I2S_RXDATA             (*(RoReg  *)0x43002834UL) /**< \brief (I2S) Rx Data */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for I2S peripheral ========== */
-#define I2S_CLK_NUM                 2        // Number of clock units
-#define I2S_DMAC_ID_RX_0            76
-#define I2S_DMAC_ID_RX_1            77
-#define I2S_DMAC_ID_RX_LSB          76
-#define I2S_DMAC_ID_RX_MSB          77
-#define I2S_DMAC_ID_RX_SIZE         2
-#define I2S_DMAC_ID_TX_0            78
-#define I2S_DMAC_ID_TX_1            79
-#define I2S_DMAC_ID_TX_LSB          78
-#define I2S_DMAC_ID_TX_MSB          79
-#define I2S_DMAC_ID_TX_SIZE         2
-#define I2S_GCLK_ID_0               43
-#define I2S_GCLK_ID_1               44
-#define I2S_GCLK_ID_LSB             43
-#define I2S_GCLK_ID_MSB             44
-#define I2S_GCLK_ID_SIZE            2
-#define I2S_MAX_SLOTS               8        // Max number of data slots in frame
-#define I2S_MAX_WL_BITS             32       // Max number of bits in data samples
-#define I2S_SER_NUM                 2        // Number of serializers
-
-#endif /* _SAMD51_I2S_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/icm.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/icm.h
deleted file mode 100644
index 08a8e8c01e..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/icm.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for ICM
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_ICM_INSTANCE_
-#define _SAMD51_ICM_INSTANCE_
-
-/* ========== Register definition for ICM peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_ICM_CFG                (0x42002C00) /**< \brief (ICM) Configuration */
-#define REG_ICM_CTRL               (0x42002C04) /**< \brief (ICM) Control */
-#define REG_ICM_SR                 (0x42002C08) /**< \brief (ICM) Status */
-#define REG_ICM_IER                (0x42002C10) /**< \brief (ICM) Interrupt Enable */
-#define REG_ICM_IDR                (0x42002C14) /**< \brief (ICM) Interrupt Disable */
-#define REG_ICM_IMR                (0x42002C18) /**< \brief (ICM) Interrupt Mask */
-#define REG_ICM_ISR                (0x42002C1C) /**< \brief (ICM) Interrupt Status */
-#define REG_ICM_UASR               (0x42002C20) /**< \brief (ICM) Undefined Access Status */
-#define REG_ICM_DSCR               (0x42002C30) /**< \brief (ICM) Region Descriptor Area Start Address */
-#define REG_ICM_HASH               (0x42002C34) /**< \brief (ICM) Region Hash Area Start Address */
-#define REG_ICM_UIHVAL0            (0x42002C38) /**< \brief (ICM) User Initial Hash Value 0 */
-#define REG_ICM_UIHVAL1            (0x42002C3C) /**< \brief (ICM) User Initial Hash Value 1 */
-#define REG_ICM_UIHVAL2            (0x42002C40) /**< \brief (ICM) User Initial Hash Value 2 */
-#define REG_ICM_UIHVAL3            (0x42002C44) /**< \brief (ICM) User Initial Hash Value 3 */
-#define REG_ICM_UIHVAL4            (0x42002C48) /**< \brief (ICM) User Initial Hash Value 4 */
-#define REG_ICM_UIHVAL5            (0x42002C4C) /**< \brief (ICM) User Initial Hash Value 5 */
-#define REG_ICM_UIHVAL6            (0x42002C50) /**< \brief (ICM) User Initial Hash Value 6 */
-#define REG_ICM_UIHVAL7            (0x42002C54) /**< \brief (ICM) User Initial Hash Value 7 */
-#else
-#define REG_ICM_CFG                (*(RwReg  *)0x42002C00UL) /**< \brief (ICM) Configuration */
-#define REG_ICM_CTRL               (*(WoReg  *)0x42002C04UL) /**< \brief (ICM) Control */
-#define REG_ICM_SR                 (*(RoReg  *)0x42002C08UL) /**< \brief (ICM) Status */
-#define REG_ICM_IER                (*(WoReg  *)0x42002C10UL) /**< \brief (ICM) Interrupt Enable */
-#define REG_ICM_IDR                (*(WoReg  *)0x42002C14UL) /**< \brief (ICM) Interrupt Disable */
-#define REG_ICM_IMR                (*(RoReg  *)0x42002C18UL) /**< \brief (ICM) Interrupt Mask */
-#define REG_ICM_ISR                (*(RoReg  *)0x42002C1CUL) /**< \brief (ICM) Interrupt Status */
-#define REG_ICM_UASR               (*(RoReg  *)0x42002C20UL) /**< \brief (ICM) Undefined Access Status */
-#define REG_ICM_DSCR               (*(RwReg  *)0x42002C30UL) /**< \brief (ICM) Region Descriptor Area Start Address */
-#define REG_ICM_HASH               (*(RwReg  *)0x42002C34UL) /**< \brief (ICM) Region Hash Area Start Address */
-#define REG_ICM_UIHVAL0            (*(WoReg  *)0x42002C38UL) /**< \brief (ICM) User Initial Hash Value 0 */
-#define REG_ICM_UIHVAL1            (*(WoReg  *)0x42002C3CUL) /**< \brief (ICM) User Initial Hash Value 1 */
-#define REG_ICM_UIHVAL2            (*(WoReg  *)0x42002C40UL) /**< \brief (ICM) User Initial Hash Value 2 */
-#define REG_ICM_UIHVAL3            (*(WoReg  *)0x42002C44UL) /**< \brief (ICM) User Initial Hash Value 3 */
-#define REG_ICM_UIHVAL4            (*(WoReg  *)0x42002C48UL) /**< \brief (ICM) User Initial Hash Value 4 */
-#define REG_ICM_UIHVAL5            (*(WoReg  *)0x42002C4CUL) /**< \brief (ICM) User Initial Hash Value 5 */
-#define REG_ICM_UIHVAL6            (*(WoReg  *)0x42002C50UL) /**< \brief (ICM) User Initial Hash Value 6 */
-#define REG_ICM_UIHVAL7            (*(WoReg  *)0x42002C54UL) /**< \brief (ICM) User Initial Hash Value 7 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for ICM peripheral ========== */
-#define ICM_CLK_AHB_ID              19      
-
-#endif /* _SAMD51_ICM_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/mclk.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/mclk.h
deleted file mode 100644
index 65e68bcf79..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/mclk.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for MCLK
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_MCLK_INSTANCE_
-#define _SAMD51_MCLK_INSTANCE_
-
-/* ========== Register definition for MCLK peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_MCLK_INTENCLR          (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */
-#define REG_MCLK_INTENSET          (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */
-#define REG_MCLK_INTFLAG           (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */
-#define REG_MCLK_HSDIV             (0x40000804) /**< \brief (MCLK) HS Clock Division */
-#define REG_MCLK_CPUDIV            (0x40000805) /**< \brief (MCLK) CPU Clock Division */
-#define REG_MCLK_AHBMASK           (0x40000810) /**< \brief (MCLK) AHB Mask */
-#define REG_MCLK_APBAMASK          (0x40000814) /**< \brief (MCLK) APBA Mask */
-#define REG_MCLK_APBBMASK          (0x40000818) /**< \brief (MCLK) APBB Mask */
-#define REG_MCLK_APBCMASK          (0x4000081C) /**< \brief (MCLK) APBC Mask */
-#define REG_MCLK_APBDMASK          (0x40000820) /**< \brief (MCLK) APBD Mask */
-#else
-#define REG_MCLK_INTENCLR          (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */
-#define REG_MCLK_INTENSET          (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */
-#define REG_MCLK_INTFLAG           (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */
-#define REG_MCLK_HSDIV             (*(RoReg8 *)0x40000804UL) /**< \brief (MCLK) HS Clock Division */
-#define REG_MCLK_CPUDIV            (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division */
-#define REG_MCLK_AHBMASK           (*(RwReg  *)0x40000810UL) /**< \brief (MCLK) AHB Mask */
-#define REG_MCLK_APBAMASK          (*(RwReg  *)0x40000814UL) /**< \brief (MCLK) APBA Mask */
-#define REG_MCLK_APBBMASK          (*(RwReg  *)0x40000818UL) /**< \brief (MCLK) APBB Mask */
-#define REG_MCLK_APBCMASK          (*(RwReg  *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */
-#define REG_MCLK_APBDMASK          (*(RwReg  *)0x40000820UL) /**< \brief (MCLK) APBD Mask */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for MCLK peripheral ========== */
-#define MCLK_SYSTEM_CLOCK           48000000 // System Clock Frequency at Reset
-
-#endif /* _SAMD51_MCLK_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/nvmctrl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/nvmctrl.h
deleted file mode 100644
index efd120920b..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/nvmctrl.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for NVMCTRL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_NVMCTRL_INSTANCE_
-#define _SAMD51_NVMCTRL_INSTANCE_
-
-/* ========== Register definition for NVMCTRL peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_NVMCTRL_CTRLA          (0x41004000) /**< \brief (NVMCTRL) Control A */
-#define REG_NVMCTRL_CTRLB          (0x41004004) /**< \brief (NVMCTRL) Control B */
-#define REG_NVMCTRL_PARAM          (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
-#define REG_NVMCTRL_INTENCLR       (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
-#define REG_NVMCTRL_INTENSET       (0x4100400E) /**< \brief (NVMCTRL) Interrupt Enable Set */
-#define REG_NVMCTRL_INTFLAG        (0x41004010) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
-#define REG_NVMCTRL_STATUS         (0x41004012) /**< \brief (NVMCTRL) Status */
-#define REG_NVMCTRL_ADDR           (0x41004014) /**< \brief (NVMCTRL) Address */
-#define REG_NVMCTRL_RUNLOCK        (0x41004018) /**< \brief (NVMCTRL) Lock Section */
-#define REG_NVMCTRL_PBLDATA0       (0x4100401C) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */
-#define REG_NVMCTRL_PBLDATA1       (0x41004020) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */
-#define REG_NVMCTRL_ECCERR         (0x41004024) /**< \brief (NVMCTRL) ECC Error Status Register */
-#define REG_NVMCTRL_DBGCTRL        (0x41004028) /**< \brief (NVMCTRL) Debug Control */
-#define REG_NVMCTRL_SEECFG         (0x4100402A) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */
-#define REG_NVMCTRL_SEESTAT        (0x4100402C) /**< \brief (NVMCTRL) SmartEEPROM Status Register */
-#else
-#define REG_NVMCTRL_CTRLA          (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
-#define REG_NVMCTRL_CTRLB          (*(WoReg16*)0x41004004UL) /**< \brief (NVMCTRL) Control B */
-#define REG_NVMCTRL_PARAM          (*(RoReg  *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
-#define REG_NVMCTRL_INTENCLR       (*(RwReg16*)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
-#define REG_NVMCTRL_INTENSET       (*(RwReg16*)0x4100400EUL) /**< \brief (NVMCTRL) Interrupt Enable Set */
-#define REG_NVMCTRL_INTFLAG        (*(RwReg16*)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
-#define REG_NVMCTRL_STATUS         (*(RoReg16*)0x41004012UL) /**< \brief (NVMCTRL) Status */
-#define REG_NVMCTRL_ADDR           (*(RwReg  *)0x41004014UL) /**< \brief (NVMCTRL) Address */
-#define REG_NVMCTRL_RUNLOCK        (*(RoReg  *)0x41004018UL) /**< \brief (NVMCTRL) Lock Section */
-#define REG_NVMCTRL_PBLDATA0       (*(RoReg  *)0x4100401CUL) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */
-#define REG_NVMCTRL_PBLDATA1       (*(RoReg  *)0x41004020UL) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */
-#define REG_NVMCTRL_ECCERR         (*(RoReg  *)0x41004024UL) /**< \brief (NVMCTRL) ECC Error Status Register */
-#define REG_NVMCTRL_DBGCTRL        (*(RwReg8 *)0x41004028UL) /**< \brief (NVMCTRL) Debug Control */
-#define REG_NVMCTRL_SEECFG         (*(RwReg8 *)0x4100402AUL) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */
-#define REG_NVMCTRL_SEESTAT        (*(RoReg  *)0x4100402CUL) /**< \brief (NVMCTRL) SmartEEPROM Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for NVMCTRL peripheral ========== */
-#define NVMCTRL_BLOCK_SIZE          8192     // Size Of Block (Bytes, Smallest Granularity for Erase Operation)
-#define NVMCTRL_CLK_AHB_ID          6        // Index of AHB Clock in PM.AHBMASK register
-#define NVMCTRL_CLK_AHB_ID_CACHE    23       // Index of AHB Clock in PM.AHBMASK register for NVMCTRL CACHE lines
-#define NVMCTRL_CLK_AHB_ID_SMEEPROM 22       // Index of AHB Clock in PM.AHBMASK register for SMEE submodule
-#define NVMCTRL_PAGE_SIZE           512      // Size Of Page (Bytes, Smallest Granularity for Write Operation In Main Array)
-
-#endif /* _SAMD51_NVMCTRL_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/osc32kctrl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/osc32kctrl.h
deleted file mode 100644
index 1313a0c67d..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/osc32kctrl.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for OSC32KCTRL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_OSC32KCTRL_INSTANCE_
-#define _SAMD51_OSC32KCTRL_INSTANCE_
-
-/* ========== Register definition for OSC32KCTRL peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_OSC32KCTRL_INTENCLR    (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
-#define REG_OSC32KCTRL_INTENSET    (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
-#define REG_OSC32KCTRL_INTFLAG     (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
-#define REG_OSC32KCTRL_STATUS      (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */
-#define REG_OSC32KCTRL_RTCCTRL     (0x40001410) /**< \brief (OSC32KCTRL) RTC Clock Selection */
-#define REG_OSC32KCTRL_XOSC32K     (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
-#define REG_OSC32KCTRL_CFDCTRL     (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
-#define REG_OSC32KCTRL_EVCTRL      (0x40001417) /**< \brief (OSC32KCTRL) Event Control */
-#define REG_OSC32KCTRL_OSCULP32K   (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-#else
-#define REG_OSC32KCTRL_INTENCLR    (*(RwReg  *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
-#define REG_OSC32KCTRL_INTENSET    (*(RwReg  *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
-#define REG_OSC32KCTRL_INTFLAG     (*(RwReg  *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
-#define REG_OSC32KCTRL_STATUS      (*(RoReg  *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */
-#define REG_OSC32KCTRL_RTCCTRL     (*(RwReg8 *)0x40001410UL) /**< \brief (OSC32KCTRL) RTC Clock Selection */
-#define REG_OSC32KCTRL_XOSC32K     (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
-#define REG_OSC32KCTRL_CFDCTRL     (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
-#define REG_OSC32KCTRL_EVCTRL      (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */
-#define REG_OSC32KCTRL_OSCULP32K   (*(RwReg  *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
-#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 0        // OSC32K coarse calibration size
-
-#endif /* _SAMD51_OSC32KCTRL_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/oscctrl.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/oscctrl.h
deleted file mode 100644
index 5e8d00066b..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/oscctrl.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for OSCCTRL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_OSCCTRL_INSTANCE_
-#define _SAMD51_OSCCTRL_INSTANCE_
-
-/* ========== Register definition for OSCCTRL peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_OSCCTRL_EVCTRL         (0x40001000) /**< \brief (OSCCTRL) Event Control */
-#define REG_OSCCTRL_INTENCLR       (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Clear */
-#define REG_OSCCTRL_INTENSET       (0x40001008) /**< \brief (OSCCTRL) Interrupt Enable Set */
-#define REG_OSCCTRL_INTFLAG        (0x4000100C) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
-#define REG_OSCCTRL_STATUS         (0x40001010) /**< \brief (OSCCTRL) Status */
-#define REG_OSCCTRL_XOSCCTRL0      (0x40001014) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
-#define REG_OSCCTRL_XOSCCTRL1      (0x40001018) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
-#define REG_OSCCTRL_DFLLCTRLA      (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Control A */
-#define REG_OSCCTRL_DFLLCTRLB      (0x40001020) /**< \brief (OSCCTRL) DFLL48M Control B */
-#define REG_OSCCTRL_DFLLVAL        (0x40001024) /**< \brief (OSCCTRL) DFLL48M Value */
-#define REG_OSCCTRL_DFLLMUL        (0x40001028) /**< \brief (OSCCTRL) DFLL48M Multiplier */
-#define REG_OSCCTRL_DFLLSYNC       (0x4000102C) /**< \brief (OSCCTRL) DFLL48M Synchronization */
-#define REG_OSCCTRL_DPLLCTRLA0     (0x40001030) /**< \brief (OSCCTRL) DPLL Control A 0 */
-#define REG_OSCCTRL_DPLLRATIO0     (0x40001034) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
-#define REG_OSCCTRL_DPLLCTRLB0     (0x40001038) /**< \brief (OSCCTRL) DPLL Control B 0 */
-#define REG_OSCCTRL_DPLLSYNCBUSY0  (0x4000103C) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
-#define REG_OSCCTRL_DPLLSTATUS0    (0x40001040) /**< \brief (OSCCTRL) DPLL Status 0 */
-#define REG_OSCCTRL_DPLLCTRLA1     (0x40001044) /**< \brief (OSCCTRL) DPLL Control A 1 */
-#define REG_OSCCTRL_DPLLRATIO1     (0x40001048) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
-#define REG_OSCCTRL_DPLLCTRLB1     (0x4000104C) /**< \brief (OSCCTRL) DPLL Control B 1 */
-#define REG_OSCCTRL_DPLLSYNCBUSY1  (0x40001050) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
-#define REG_OSCCTRL_DPLLSTATUS1    (0x40001054) /**< \brief (OSCCTRL) DPLL Status 1 */
-#else
-#define REG_OSCCTRL_EVCTRL         (*(RwReg8 *)0x40001000UL) /**< \brief (OSCCTRL) Event Control */
-#define REG_OSCCTRL_INTENCLR       (*(RwReg  *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
-#define REG_OSCCTRL_INTENSET       (*(RwReg  *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
-#define REG_OSCCTRL_INTFLAG        (*(RwReg  *)0x4000100CUL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
-#define REG_OSCCTRL_STATUS         (*(RoReg  *)0x40001010UL) /**< \brief (OSCCTRL) Status */
-#define REG_OSCCTRL_XOSCCTRL0      (*(RwReg  *)0x40001014UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
-#define REG_OSCCTRL_XOSCCTRL1      (*(RwReg  *)0x40001018UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
-#define REG_OSCCTRL_DFLLCTRLA      (*(RwReg8 *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Control A */
-#define REG_OSCCTRL_DFLLCTRLB      (*(RwReg8 *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Control B */
-#define REG_OSCCTRL_DFLLVAL        (*(RwReg  *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Value */
-#define REG_OSCCTRL_DFLLMUL        (*(RwReg  *)0x40001028UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */
-#define REG_OSCCTRL_DFLLSYNC       (*(RwReg8 *)0x4000102CUL) /**< \brief (OSCCTRL) DFLL48M Synchronization */
-#define REG_OSCCTRL_DPLLCTRLA0     (*(RwReg8 *)0x40001030UL) /**< \brief (OSCCTRL) DPLL Control A 0 */
-#define REG_OSCCTRL_DPLLRATIO0     (*(RwReg8 *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
-#define REG_OSCCTRL_DPLLCTRLB0     (*(RwReg8 *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Control B 0 */
-#define REG_OSCCTRL_DPLLSYNCBUSY0  (*(RoReg8 *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
-#define REG_OSCCTRL_DPLLSTATUS0    (*(RoReg8 *)0x40001040UL) /**< \brief (OSCCTRL) DPLL Status 0 */
-#define REG_OSCCTRL_DPLLCTRLA1     (*(RwReg8 *)0x40001044UL) /**< \brief (OSCCTRL) DPLL Control A 1 */
-#define REG_OSCCTRL_DPLLRATIO1     (*(RwReg8 *)0x40001048UL) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
-#define REG_OSCCTRL_DPLLCTRLB1     (*(RwReg8 *)0x4000104CUL) /**< \brief (OSCCTRL) DPLL Control B 1 */
-#define REG_OSCCTRL_DPLLSYNCBUSY1  (*(RoReg8 *)0x40001050UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
-#define REG_OSCCTRL_DPLLSTATUS1    (*(RoReg8 *)0x40001054UL) /**< \brief (OSCCTRL) DPLL Status 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for OSCCTRL peripheral ========== */
-#define OSCCTRL_DFLLS_NUM           1        // Number of DFLLs
-#define OSCCTRL_DFLL_IMPLEMENTED    1        // DFLL implemented
-#define OSCCTRL_DFLL48M_BIASTESTPT_IMPLEMENTED 0        // DFLL48M bias test mode implemented
-#define OSCCTRL_DFLL48M_CDACSTEPSIZE_SIZE 2        // Size COARSE DAC STEP
-#define OSCCTRL_DFLL48M_COARSE_RESET_VALUE 32       // DFLL48M Frequency Coarse Reset Value (Before Calibration)
-#define OSCCTRL_DFLL48M_COARSE_SIZE 6        // Size COARSE CALIBRATION
-#define OSCCTRL_DFLL48M_ENABLE_RESET_VALUE 1        // Run oscillator at reset
-#define OSCCTRL_DFLL48M_FDACSTEPSIZE_SIZE 2        // Size FINE DAC STEP
-#define OSCCTRL_DFLL48M_FINE_RESET_VALUE 128      // DFLL48M Frequency Fine Reset Value (Before Calibration)
-#define OSCCTRL_DFLL48M_FINE_SIZE   8        // Size FINE CALIBRATION
-#define OSCCTRL_DFLL48M_ONDEMAND_RESET_VALUE 1        // Run oscillator always or only when requested
-#define OSCCTRL_DFLL48M_RUNSTDBY_RESET_VALUE 0        // Run oscillator even if standby mode
-#define OSCCTRL_DFLL48M_TCAL_SIZE   4        // Size TEMP CALIBRATION
-#define OSCCTRL_DFLL48M_TCBIAS_SIZE 2        // Size TC BIAS CALIBRATION
-#define OSCCTRL_DFLL48M_TESTPTSEL_SIZE 3        // Size TEST POINT SELECTOR
-#define OSCCTRL_DFLL48M_WAITLOCK_ACTIVE 1        // Enable Wait Lock Feature
-#define OSCCTRL_DPLLS_NUM           2        // Number of DPLLs
-#define OSCCTRL_DPLL0_IMPLEMENTED   1        // DPLL0 implemented
-#define OSCCTRL_DPLL0_I12ND_I12NDFRAC_PAD_CONTROL 0        // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
-#define OSCCTRL_DPLL0_OCC_IMPLEMENTED 1        // DPLL0 OCC Implemented
-#define OSCCTRL_DPLL1_IMPLEMENTED   1        // DPLL1 implemented
-#define OSCCTRL_DPLL1_I12ND_I12NDFRAC_PAD_CONTROL 0        // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
-#define OSCCTRL_DPLL1_OCC_IMPLEMENTED 0        // DPLL1 OCC Implemented
-#define OSCCTRL_GCLK_ID_DFLL48      0        // Index of Generic Clock for DFLL48
-#define OSCCTRL_GCLK_ID_FDPLL0      1        // Index of Generic Clock for DPLL0
-#define OSCCTRL_GCLK_ID_FDPLL1      2        // Index of Generic Clock for DPLL1
-#define OSCCTRL_GCLK_ID_FDPLL032K   3        // Index of Generic Clock for DPLL0 32K
-#define OSCCTRL_GCLK_ID_FDPLL132K   3        // Index of Generic Clock for DPLL1 32K
-#define OSCCTRL_OSC16M_IMPLEMENTED  0        // OSC16M implemented
-#define OSCCTRL_OSC48M_IMPLEMENTED  0        // OSC48M implemented
-#define OSCCTRL_OSC48M_NUM          1       
-#define OSCCTRL_RCOSCS_NUM          1        // Number of RCOSCs (min 1)
-#define OSCCTRL_XOSCS_NUM           2        // Number of XOSCs
-#define OSCCTRL_XOSC0_CFD_CLK_SELECT_SIZE 4        // Clock fail prescaler size
-#define OSCCTRL_XOSC0_CFD_IMPLEMENTED 1        // Clock fail detected for xosc implemented
-#define OSCCTRL_XOSC0_IMPLEMENTED   1        // XOSC0 implemented
-#define OSCCTRL_XOSC0_ONDEMAND_RESET_VALUE 1        // Run oscillator always or only when requested
-#define OSCCTRL_XOSC0_RUNSTDBY_RESET_VALUE 0        // Run oscillator even if standby mode
-#define OSCCTRL_XOSC1_CFD_CLK_SELECT_SIZE 4        // Clock fail prescaler size
-#define OSCCTRL_XOSC1_CFD_IMPLEMENTED 1        // Clock fail detected for xosc implemented
-#define OSCCTRL_XOSC1_IMPLEMENTED   1        // XOSC1 implemented
-#define OSCCTRL_XOSC1_ONDEMAND_RESET_VALUE 1        // Run oscillator always or only when requested
-#define OSCCTRL_XOSC1_RUNSTDBY_RESET_VALUE 0        // Run oscillator even if standby mode
-#define OSCCTRL_DFLL48M_VERSION     0x100   
-#define OSCCTRL_FDPLL_VERSION       0x100   
-#define OSCCTRL_XOSC_VERSION        0x100   
-
-#endif /* _SAMD51_OSCCTRL_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pac.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pac.h
deleted file mode 100644
index 3d35951e74..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pac.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for PAC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PAC_INSTANCE_
-#define _SAMD51_PAC_INSTANCE_
-
-/* ========== Register definition for PAC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PAC_WRCTRL             (0x40000000) /**< \brief (PAC) Write control */
-#define REG_PAC_EVCTRL             (0x40000004) /**< \brief (PAC) Event control */
-#define REG_PAC_INTENCLR           (0x40000008) /**< \brief (PAC) Interrupt enable clear */
-#define REG_PAC_INTENSET           (0x40000009) /**< \brief (PAC) Interrupt enable set */
-#define REG_PAC_INTFLAGAHB         (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */
-#define REG_PAC_INTFLAGA           (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
-#define REG_PAC_INTFLAGB           (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
-#define REG_PAC_INTFLAGC           (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
-#define REG_PAC_INTFLAGD           (0x40000020) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
-#define REG_PAC_STATUSA            (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */
-#define REG_PAC_STATUSB            (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */
-#define REG_PAC_STATUSC            (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */
-#define REG_PAC_STATUSD            (0x40000040) /**< \brief (PAC) Peripheral write protection status - Bridge D */
-#else
-#define REG_PAC_WRCTRL             (*(RwReg  *)0x40000000UL) /**< \brief (PAC) Write control */
-#define REG_PAC_EVCTRL             (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */
-#define REG_PAC_INTENCLR           (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */
-#define REG_PAC_INTENSET           (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */
-#define REG_PAC_INTFLAGAHB         (*(RwReg  *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */
-#define REG_PAC_INTFLAGA           (*(RwReg  *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
-#define REG_PAC_INTFLAGB           (*(RwReg  *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
-#define REG_PAC_INTFLAGC           (*(RwReg  *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
-#define REG_PAC_INTFLAGD           (*(RwReg  *)0x40000020UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
-#define REG_PAC_STATUSA            (*(RoReg  *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */
-#define REG_PAC_STATUSB            (*(RoReg  *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */
-#define REG_PAC_STATUSC            (*(RoReg  *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */
-#define REG_PAC_STATUSD            (*(RoReg  *)0x40000040UL) /**< \brief (PAC) Peripheral write protection status - Bridge D */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PAC peripheral ========== */
-#define PAC_CLK_AHB_DOMAIN                   // Clock domain of AHB clock
-#define PAC_CLK_AHB_ID              12       // AHB clock index
-#define PAC_HPB_NUM                 4        // Number of bridges AHB/APB
-
-#endif /* _SAMD51_PAC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pcc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pcc.h
deleted file mode 100644
index 1148237444..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pcc.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for PCC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PCC_INSTANCE_
-#define _SAMD51_PCC_INSTANCE_
-
-/* ========== Register definition for PCC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PCC_MR                 (0x43002C00) /**< \brief (PCC) Mode Register */
-#define REG_PCC_IER                (0x43002C04) /**< \brief (PCC) Interrupt Enable Register */
-#define REG_PCC_IDR                (0x43002C08) /**< \brief (PCC) Interrupt Disable Register */
-#define REG_PCC_IMR                (0x43002C0C) /**< \brief (PCC) Interrupt Mask Register */
-#define REG_PCC_ISR                (0x43002C10) /**< \brief (PCC) Interrupt Status Register */
-#define REG_PCC_RHR                (0x43002C14) /**< \brief (PCC) Reception Holding Register */
-#define REG_PCC_WPMR               (0x43002CE0) /**< \brief (PCC) Write Protection Mode Register */
-#define REG_PCC_WPSR               (0x43002CE4) /**< \brief (PCC) Write Protection Status Register */
-#else
-#define REG_PCC_MR                 (*(RwReg  *)0x43002C00UL) /**< \brief (PCC) Mode Register */
-#define REG_PCC_IER                (*(WoReg  *)0x43002C04UL) /**< \brief (PCC) Interrupt Enable Register */
-#define REG_PCC_IDR                (*(WoReg  *)0x43002C08UL) /**< \brief (PCC) Interrupt Disable Register */
-#define REG_PCC_IMR                (*(RoReg  *)0x43002C0CUL) /**< \brief (PCC) Interrupt Mask Register */
-#define REG_PCC_ISR                (*(RoReg  *)0x43002C10UL) /**< \brief (PCC) Interrupt Status Register */
-#define REG_PCC_RHR                (*(RoReg  *)0x43002C14UL) /**< \brief (PCC) Reception Holding Register */
-#define REG_PCC_WPMR               (*(RwReg  *)0x43002CE0UL) /**< \brief (PCC) Write Protection Mode Register */
-#define REG_PCC_WPSR               (*(RoReg  *)0x43002CE4UL) /**< \brief (PCC) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PCC peripheral ========== */
-#define PCC_DATA_SIZE               14      
-#define PCC_DMAC_ID_RX              80      
-
-#endif /* _SAMD51_PCC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pdec.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pdec.h
deleted file mode 100644
index 0b207a2204..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pdec.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for PDEC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PDEC_INSTANCE_
-#define _SAMD51_PDEC_INSTANCE_
-
-/* ========== Register definition for PDEC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PDEC_CTRLA             (0x42001C00) /**< \brief (PDEC) Control A */
-#define REG_PDEC_CTRLBCLR          (0x42001C04) /**< \brief (PDEC) Control B Clear */
-#define REG_PDEC_CTRLBSET          (0x42001C05) /**< \brief (PDEC) Control B Set */
-#define REG_PDEC_EVCTRL            (0x42001C06) /**< \brief (PDEC) Event Control */
-#define REG_PDEC_INTENCLR          (0x42001C08) /**< \brief (PDEC) Interrupt Enable Clear */
-#define REG_PDEC_INTENSET          (0x42001C09) /**< \brief (PDEC) Interrupt Enable Set */
-#define REG_PDEC_INTFLAG           (0x42001C0A) /**< \brief (PDEC) Interrupt Flag Status and Clear */
-#define REG_PDEC_STATUS            (0x42001C0C) /**< \brief (PDEC) Status */
-#define REG_PDEC_DBGCTRL           (0x42001C0F) /**< \brief (PDEC) Debug Control */
-#define REG_PDEC_SYNCBUSY          (0x42001C10) /**< \brief (PDEC) Synchronization Status */
-#define REG_PDEC_PRESC             (0x42001C14) /**< \brief (PDEC) Prescaler Value */
-#define REG_PDEC_FILTER            (0x42001C15) /**< \brief (PDEC) Filter Value */
-#define REG_PDEC_PRESCBUF          (0x42001C18) /**< \brief (PDEC) Prescaler Buffer Value */
-#define REG_PDEC_FILTERBUF         (0x42001C19) /**< \brief (PDEC) Filter Buffer Value */
-#define REG_PDEC_COUNT             (0x42001C1C) /**< \brief (PDEC) Counter Value */
-#define REG_PDEC_CC0               (0x42001C20) /**< \brief (PDEC) Channel 0 Compare Value */
-#define REG_PDEC_CC1               (0x42001C24) /**< \brief (PDEC) Channel 1 Compare Value */
-#define REG_PDEC_CCBUF0            (0x42001C30) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
-#define REG_PDEC_CCBUF1            (0x42001C34) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
-#else
-#define REG_PDEC_CTRLA             (*(RwReg  *)0x42001C00UL) /**< \brief (PDEC) Control A */
-#define REG_PDEC_CTRLBCLR          (*(RwReg8 *)0x42001C04UL) /**< \brief (PDEC) Control B Clear */
-#define REG_PDEC_CTRLBSET          (*(RwReg8 *)0x42001C05UL) /**< \brief (PDEC) Control B Set */
-#define REG_PDEC_EVCTRL            (*(RwReg16*)0x42001C06UL) /**< \brief (PDEC) Event Control */
-#define REG_PDEC_INTENCLR          (*(RwReg8 *)0x42001C08UL) /**< \brief (PDEC) Interrupt Enable Clear */
-#define REG_PDEC_INTENSET          (*(RwReg8 *)0x42001C09UL) /**< \brief (PDEC) Interrupt Enable Set */
-#define REG_PDEC_INTFLAG           (*(RwReg8 *)0x42001C0AUL) /**< \brief (PDEC) Interrupt Flag Status and Clear */
-#define REG_PDEC_STATUS            (*(RwReg16*)0x42001C0CUL) /**< \brief (PDEC) Status */
-#define REG_PDEC_DBGCTRL           (*(RwReg8 *)0x42001C0FUL) /**< \brief (PDEC) Debug Control */
-#define REG_PDEC_SYNCBUSY          (*(RoReg  *)0x42001C10UL) /**< \brief (PDEC) Synchronization Status */
-#define REG_PDEC_PRESC             (*(RwReg8 *)0x42001C14UL) /**< \brief (PDEC) Prescaler Value */
-#define REG_PDEC_FILTER            (*(RwReg8 *)0x42001C15UL) /**< \brief (PDEC) Filter Value */
-#define REG_PDEC_PRESCBUF          (*(RwReg8 *)0x42001C18UL) /**< \brief (PDEC) Prescaler Buffer Value */
-#define REG_PDEC_FILTERBUF         (*(RwReg8 *)0x42001C19UL) /**< \brief (PDEC) Filter Buffer Value */
-#define REG_PDEC_COUNT             (*(RwReg  *)0x42001C1CUL) /**< \brief (PDEC) Counter Value */
-#define REG_PDEC_CC0               (*(RwReg  *)0x42001C20UL) /**< \brief (PDEC) Channel 0 Compare Value */
-#define REG_PDEC_CC1               (*(RwReg  *)0x42001C24UL) /**< \brief (PDEC) Channel 1 Compare Value */
-#define REG_PDEC_CCBUF0            (*(RwReg  *)0x42001C30UL) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
-#define REG_PDEC_CCBUF1            (*(RwReg  *)0x42001C34UL) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PDEC peripheral ========== */
-#define PDEC_CC_NUM                 2        // Number of Compare Channels units
-#define PDEC_GCLK_ID                31      
-
-#endif /* _SAMD51_PDEC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pm.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pm.h
deleted file mode 100644
index 534aee29f8..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pm.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for PM
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PM_INSTANCE_
-#define _SAMD51_PM_INSTANCE_
-
-/* ========== Register definition for PM peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PM_CTRLA               (0x40000400) /**< \brief (PM) Control A */
-#define REG_PM_SLEEPCFG            (0x40000401) /**< \brief (PM) Sleep Configuration */
-#define REG_PM_INTENCLR            (0x40000404) /**< \brief (PM) Interrupt Enable Clear */
-#define REG_PM_INTENSET            (0x40000405) /**< \brief (PM) Interrupt Enable Set */
-#define REG_PM_INTFLAG             (0x40000406) /**< \brief (PM) Interrupt Flag Status and Clear */
-#define REG_PM_STDBYCFG            (0x40000408) /**< \brief (PM) Standby Configuration */
-#define REG_PM_HIBCFG              (0x40000409) /**< \brief (PM) Hibernate Configuration */
-#define REG_PM_BKUPCFG             (0x4000040A) /**< \brief (PM) Backup Configuration */
-#define REG_PM_PWSAKDLY            (0x40000412) /**< \brief (PM) Power Switch Acknowledge Delay */
-#else
-#define REG_PM_CTRLA               (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control A */
-#define REG_PM_SLEEPCFG            (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */
-#define REG_PM_INTENCLR            (*(RwReg8 *)0x40000404UL) /**< \brief (PM) Interrupt Enable Clear */
-#define REG_PM_INTENSET            (*(RwReg8 *)0x40000405UL) /**< \brief (PM) Interrupt Enable Set */
-#define REG_PM_INTFLAG             (*(RwReg8 *)0x40000406UL) /**< \brief (PM) Interrupt Flag Status and Clear */
-#define REG_PM_STDBYCFG            (*(RwReg8 *)0x40000408UL) /**< \brief (PM) Standby Configuration */
-#define REG_PM_HIBCFG              (*(RwReg8 *)0x40000409UL) /**< \brief (PM) Hibernate Configuration */
-#define REG_PM_BKUPCFG             (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) Backup Configuration */
-#define REG_PM_PWSAKDLY            (*(RwReg8 *)0x40000412UL) /**< \brief (PM) Power Switch Acknowledge Delay */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PM peripheral ========== */
-#define PM_PD_NUM                   0        // Number of switchable Power Domains
-
-#endif /* _SAMD51_PM_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/port.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/port.h
deleted file mode 100644
index 85c913108a..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/port.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for PORT
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PORT_INSTANCE_
-#define _SAMD51_PORT_INSTANCE_
-
-/* ========== Register definition for PORT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_PORT_DIR0              (0x41008000) /**< \brief (PORT) Data Direction 0 */
-#define REG_PORT_DIRCLR0           (0x41008004) /**< \brief (PORT) Data Direction Clear 0 */
-#define REG_PORT_DIRSET0           (0x41008008) /**< \brief (PORT) Data Direction Set 0 */
-#define REG_PORT_DIRTGL0           (0x4100800C) /**< \brief (PORT) Data Direction Toggle 0 */
-#define REG_PORT_OUT0              (0x41008010) /**< \brief (PORT) Data Output Value 0 */
-#define REG_PORT_OUTCLR0           (0x41008014) /**< \brief (PORT) Data Output Value Clear 0 */
-#define REG_PORT_OUTSET0           (0x41008018) /**< \brief (PORT) Data Output Value Set 0 */
-#define REG_PORT_OUTTGL0           (0x4100801C) /**< \brief (PORT) Data Output Value Toggle 0 */
-#define REG_PORT_IN0               (0x41008020) /**< \brief (PORT) Data Input Value 0 */
-#define REG_PORT_CTRL0             (0x41008024) /**< \brief (PORT) Control 0 */
-#define REG_PORT_WRCONFIG0         (0x41008028) /**< \brief (PORT) Write Configuration 0 */
-#define REG_PORT_EVCTRL0           (0x4100802C) /**< \brief (PORT) Event Input Control 0 */
-#define REG_PORT_PMUX0             (0x41008030) /**< \brief (PORT) Peripheral Multiplexing 0 */
-#define REG_PORT_PINCFG0           (0x41008040) /**< \brief (PORT) Pin Configuration 0 */
-#define REG_PORT_DIR1              (0x41008080) /**< \brief (PORT) Data Direction 1 */
-#define REG_PORT_DIRCLR1           (0x41008084) /**< \brief (PORT) Data Direction Clear 1 */
-#define REG_PORT_DIRSET1           (0x41008088) /**< \brief (PORT) Data Direction Set 1 */
-#define REG_PORT_DIRTGL1           (0x4100808C) /**< \brief (PORT) Data Direction Toggle 1 */
-#define REG_PORT_OUT1              (0x41008090) /**< \brief (PORT) Data Output Value 1 */
-#define REG_PORT_OUTCLR1           (0x41008094) /**< \brief (PORT) Data Output Value Clear 1 */
-#define REG_PORT_OUTSET1           (0x41008098) /**< \brief (PORT) Data Output Value Set 1 */
-#define REG_PORT_OUTTGL1           (0x4100809C) /**< \brief (PORT) Data Output Value Toggle 1 */
-#define REG_PORT_IN1               (0x410080A0) /**< \brief (PORT) Data Input Value 1 */
-#define REG_PORT_CTRL1             (0x410080A4) /**< \brief (PORT) Control 1 */
-#define REG_PORT_WRCONFIG1         (0x410080A8) /**< \brief (PORT) Write Configuration 1 */
-#define REG_PORT_EVCTRL1           (0x410080AC) /**< \brief (PORT) Event Input Control 1 */
-#define REG_PORT_PMUX1             (0x410080B0) /**< \brief (PORT) Peripheral Multiplexing 1 */
-#define REG_PORT_PINCFG1           (0x410080C0) /**< \brief (PORT) Pin Configuration 1 */
-#define REG_PORT_DIR2              (0x41008100) /**< \brief (PORT) Data Direction 2 */
-#define REG_PORT_DIRCLR2           (0x41008104) /**< \brief (PORT) Data Direction Clear 2 */
-#define REG_PORT_DIRSET2           (0x41008108) /**< \brief (PORT) Data Direction Set 2 */
-#define REG_PORT_DIRTGL2           (0x4100810C) /**< \brief (PORT) Data Direction Toggle 2 */
-#define REG_PORT_OUT2              (0x41008110) /**< \brief (PORT) Data Output Value 2 */
-#define REG_PORT_OUTCLR2           (0x41008114) /**< \brief (PORT) Data Output Value Clear 2 */
-#define REG_PORT_OUTSET2           (0x41008118) /**< \brief (PORT) Data Output Value Set 2 */
-#define REG_PORT_OUTTGL2           (0x4100811C) /**< \brief (PORT) Data Output Value Toggle 2 */
-#define REG_PORT_IN2               (0x41008120) /**< \brief (PORT) Data Input Value 2 */
-#define REG_PORT_CTRL2             (0x41008124) /**< \brief (PORT) Control 2 */
-#define REG_PORT_WRCONFIG2         (0x41008128) /**< \brief (PORT) Write Configuration 2 */
-#define REG_PORT_EVCTRL2           (0x4100812C) /**< \brief (PORT) Event Input Control 2 */
-#define REG_PORT_PMUX2             (0x41008130) /**< \brief (PORT) Peripheral Multiplexing 2 */
-#define REG_PORT_PINCFG2           (0x41008140) /**< \brief (PORT) Pin Configuration 2 */
-#define REG_PORT_DIR3              (0x41008180) /**< \brief (PORT) Data Direction 3 */
-#define REG_PORT_DIRCLR3           (0x41008184) /**< \brief (PORT) Data Direction Clear 3 */
-#define REG_PORT_DIRSET3           (0x41008188) /**< \brief (PORT) Data Direction Set 3 */
-#define REG_PORT_DIRTGL3           (0x4100818C) /**< \brief (PORT) Data Direction Toggle 3 */
-#define REG_PORT_OUT3              (0x41008190) /**< \brief (PORT) Data Output Value 3 */
-#define REG_PORT_OUTCLR3           (0x41008194) /**< \brief (PORT) Data Output Value Clear 3 */
-#define REG_PORT_OUTSET3           (0x41008198) /**< \brief (PORT) Data Output Value Set 3 */
-#define REG_PORT_OUTTGL3           (0x4100819C) /**< \brief (PORT) Data Output Value Toggle 3 */
-#define REG_PORT_IN3               (0x410081A0) /**< \brief (PORT) Data Input Value 3 */
-#define REG_PORT_CTRL3             (0x410081A4) /**< \brief (PORT) Control 3 */
-#define REG_PORT_WRCONFIG3         (0x410081A8) /**< \brief (PORT) Write Configuration 3 */
-#define REG_PORT_EVCTRL3           (0x410081AC) /**< \brief (PORT) Event Input Control 3 */
-#define REG_PORT_PMUX3             (0x410081B0) /**< \brief (PORT) Peripheral Multiplexing 3 */
-#define REG_PORT_PINCFG3           (0x410081C0) /**< \brief (PORT) Pin Configuration 3 */
-#else
-#define REG_PORT_DIR0              (*(RwReg  *)0x41008000UL) /**< \brief (PORT) Data Direction 0 */
-#define REG_PORT_DIRCLR0           (*(RwReg  *)0x41008004UL) /**< \brief (PORT) Data Direction Clear 0 */
-#define REG_PORT_DIRSET0           (*(RwReg  *)0x41008008UL) /**< \brief (PORT) Data Direction Set 0 */
-#define REG_PORT_DIRTGL0           (*(RwReg  *)0x4100800CUL) /**< \brief (PORT) Data Direction Toggle 0 */
-#define REG_PORT_OUT0              (*(RwReg  *)0x41008010UL) /**< \brief (PORT) Data Output Value 0 */
-#define REG_PORT_OUTCLR0           (*(RwReg  *)0x41008014UL) /**< \brief (PORT) Data Output Value Clear 0 */
-#define REG_PORT_OUTSET0           (*(RwReg  *)0x41008018UL) /**< \brief (PORT) Data Output Value Set 0 */
-#define REG_PORT_OUTTGL0           (*(RwReg  *)0x4100801CUL) /**< \brief (PORT) Data Output Value Toggle 0 */
-#define REG_PORT_IN0               (*(RoReg  *)0x41008020UL) /**< \brief (PORT) Data Input Value 0 */
-#define REG_PORT_CTRL0             (*(RwReg  *)0x41008024UL) /**< \brief (PORT) Control 0 */
-#define REG_PORT_WRCONFIG0         (*(WoReg  *)0x41008028UL) /**< \brief (PORT) Write Configuration 0 */
-#define REG_PORT_EVCTRL0           (*(RwReg  *)0x4100802CUL) /**< \brief (PORT) Event Input Control 0 */
-#define REG_PORT_PMUX0             (*(RwReg  *)0x41008030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */
-#define REG_PORT_PINCFG0           (*(RwReg  *)0x41008040UL) /**< \brief (PORT) Pin Configuration 0 */
-#define REG_PORT_DIR1              (*(RwReg  *)0x41008080UL) /**< \brief (PORT) Data Direction 1 */
-#define REG_PORT_DIRCLR1           (*(RwReg  *)0x41008084UL) /**< \brief (PORT) Data Direction Clear 1 */
-#define REG_PORT_DIRSET1           (*(RwReg  *)0x41008088UL) /**< \brief (PORT) Data Direction Set 1 */
-#define REG_PORT_DIRTGL1           (*(RwReg  *)0x4100808CUL) /**< \brief (PORT) Data Direction Toggle 1 */
-#define REG_PORT_OUT1              (*(RwReg  *)0x41008090UL) /**< \brief (PORT) Data Output Value 1 */
-#define REG_PORT_OUTCLR1           (*(RwReg  *)0x41008094UL) /**< \brief (PORT) Data Output Value Clear 1 */
-#define REG_PORT_OUTSET1           (*(RwReg  *)0x41008098UL) /**< \brief (PORT) Data Output Value Set 1 */
-#define REG_PORT_OUTTGL1           (*(RwReg  *)0x4100809CUL) /**< \brief (PORT) Data Output Value Toggle 1 */
-#define REG_PORT_IN1               (*(RoReg  *)0x410080A0UL) /**< \brief (PORT) Data Input Value 1 */
-#define REG_PORT_CTRL1             (*(RwReg  *)0x410080A4UL) /**< \brief (PORT) Control 1 */
-#define REG_PORT_WRCONFIG1         (*(WoReg  *)0x410080A8UL) /**< \brief (PORT) Write Configuration 1 */
-#define REG_PORT_EVCTRL1           (*(RwReg  *)0x410080ACUL) /**< \brief (PORT) Event Input Control 1 */
-#define REG_PORT_PMUX1             (*(RwReg  *)0x410080B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */
-#define REG_PORT_PINCFG1           (*(RwReg  *)0x410080C0UL) /**< \brief (PORT) Pin Configuration 1 */
-#define REG_PORT_DIR2              (*(RwReg  *)0x41008100UL) /**< \brief (PORT) Data Direction 2 */
-#define REG_PORT_DIRCLR2           (*(RwReg  *)0x41008104UL) /**< \brief (PORT) Data Direction Clear 2 */
-#define REG_PORT_DIRSET2           (*(RwReg  *)0x41008108UL) /**< \brief (PORT) Data Direction Set 2 */
-#define REG_PORT_DIRTGL2           (*(RwReg  *)0x4100810CUL) /**< \brief (PORT) Data Direction Toggle 2 */
-#define REG_PORT_OUT2              (*(RwReg  *)0x41008110UL) /**< \brief (PORT) Data Output Value 2 */
-#define REG_PORT_OUTCLR2           (*(RwReg  *)0x41008114UL) /**< \brief (PORT) Data Output Value Clear 2 */
-#define REG_PORT_OUTSET2           (*(RwReg  *)0x41008118UL) /**< \brief (PORT) Data Output Value Set 2 */
-#define REG_PORT_OUTTGL2           (*(RwReg  *)0x4100811CUL) /**< \brief (PORT) Data Output Value Toggle 2 */
-#define REG_PORT_IN2               (*(RoReg  *)0x41008120UL) /**< \brief (PORT) Data Input Value 2 */
-#define REG_PORT_CTRL2             (*(RwReg  *)0x41008124UL) /**< \brief (PORT) Control 2 */
-#define REG_PORT_WRCONFIG2         (*(WoReg  *)0x41008128UL) /**< \brief (PORT) Write Configuration 2 */
-#define REG_PORT_EVCTRL2           (*(RwReg  *)0x4100812CUL) /**< \brief (PORT) Event Input Control 2 */
-#define REG_PORT_PMUX2             (*(RwReg  *)0x41008130UL) /**< \brief (PORT) Peripheral Multiplexing 2 */
-#define REG_PORT_PINCFG2           (*(RwReg  *)0x41008140UL) /**< \brief (PORT) Pin Configuration 2 */
-#define REG_PORT_DIR3              (*(RwReg  *)0x41008180UL) /**< \brief (PORT) Data Direction 3 */
-#define REG_PORT_DIRCLR3           (*(RwReg  *)0x41008184UL) /**< \brief (PORT) Data Direction Clear 3 */
-#define REG_PORT_DIRSET3           (*(RwReg  *)0x41008188UL) /**< \brief (PORT) Data Direction Set 3 */
-#define REG_PORT_DIRTGL3           (*(RwReg  *)0x4100818CUL) /**< \brief (PORT) Data Direction Toggle 3 */
-#define REG_PORT_OUT3              (*(RwReg  *)0x41008190UL) /**< \brief (PORT) Data Output Value 3 */
-#define REG_PORT_OUTCLR3           (*(RwReg  *)0x41008194UL) /**< \brief (PORT) Data Output Value Clear 3 */
-#define REG_PORT_OUTSET3           (*(RwReg  *)0x41008198UL) /**< \brief (PORT) Data Output Value Set 3 */
-#define REG_PORT_OUTTGL3           (*(RwReg  *)0x4100819CUL) /**< \brief (PORT) Data Output Value Toggle 3 */
-#define REG_PORT_IN3               (*(RoReg  *)0x410081A0UL) /**< \brief (PORT) Data Input Value 3 */
-#define REG_PORT_CTRL3             (*(RwReg  *)0x410081A4UL) /**< \brief (PORT) Control 3 */
-#define REG_PORT_WRCONFIG3         (*(WoReg  *)0x410081A8UL) /**< \brief (PORT) Write Configuration 3 */
-#define REG_PORT_EVCTRL3           (*(RwReg  *)0x410081ACUL) /**< \brief (PORT) Event Input Control 3 */
-#define REG_PORT_PMUX3             (*(RwReg  *)0x410081B0UL) /**< \brief (PORT) Peripheral Multiplexing 3 */
-#define REG_PORT_PINCFG3           (*(RwReg  *)0x410081C0UL) /**< \brief (PORT) Pin Configuration 3 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PORT peripheral ========== */
-#define PORT_BITS                   118     
-#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_DIR_IMPLEMENTED        { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
-#define PORT_DRVSTR                 1        // DRVSTR supported
-#define PORT_DRVSTR_DEFAULT_VAL     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_DRVSTR_IMPLEMENTED     { 0xC8FFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
-#define PORT_EVENT_IMPLEMENTED      { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
-#define PORT_EV_NUM                 4       
-#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_INEN_IMPLEMENTED       { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
-#define PORT_ODRAIN                 0        // ODRAIN supported
-#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_OUT_IMPLEMENTED        { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
-#define PORT_PIN_IMPLEMENTED        { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
-#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_PMUXBIT0_IMPLEMENTED   { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFC1F, 0x00301F03 }
-#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_PMUXBIT1_IMPLEMENTED   { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFCF0, 0x00300F00 }
-#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_PMUXBIT2_IMPLEMENTED   { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFC10, 0x00301F00 }
-#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_PMUXBIT3_IMPLEMENTED   { 0xCBFFFFF8, 0x33FFFFFF, 0x18FFF8C0, 0x00300000 }
-#define PORT_PMUXEN_DEFAULT_VAL     { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_PMUXEN_IMPLEMENTED     { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
-#define PORT_PPP_IMPLEMENTED        { 0x00000001 } // IOBUS2 implemented?
-#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_PULLEN_IMPLEMENTED     { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
-#define PORT_SLEWLIM                0        // SLEWLIM supported
-#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
-
-#endif /* _SAMD51_PORT_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pukcc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pukcc.h
deleted file mode 100644
index 2ee05d85e7..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/pukcc.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for PUKCC
- *
- * Copyright (c) 2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- *    Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_PUKCC_INSTANCE_
-#define _SAMD51_PUKCC_INSTANCE_
-
-/* ========== Register definition for PUKCC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#else
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for PUKCC peripheral ========== */
-#define PUKCC_CLK_AHB_ID            20      
-#define PUKCC_RAM_ADDR_SIZE         12      
-#define PUKCC_ROM_ADDR_SIZE         16      
-
-#endif /* _SAMD51_PUKCC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/qspi.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/qspi.h
deleted file mode 100644
index a85bf3bfa7..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/qspi.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for QSPI
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_QSPI_INSTANCE_
-#define _SAMD51_QSPI_INSTANCE_
-
-/* ========== Register definition for QSPI peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_QSPI_CTRLA             (0x42003400) /**< \brief (QSPI) Control A */
-#define REG_QSPI_CTRLB             (0x42003404) /**< \brief (QSPI) Control B */
-#define REG_QSPI_BAUD              (0x42003408) /**< \brief (QSPI) Baud Rate */
-#define REG_QSPI_RXDATA            (0x4200340C) /**< \brief (QSPI) Receive Data */
-#define REG_QSPI_TXDATA            (0x42003410) /**< \brief (QSPI) Transmit Data */
-#define REG_QSPI_INTENCLR          (0x42003414) /**< \brief (QSPI) Interrupt Enable Clear */
-#define REG_QSPI_INTENSET          (0x42003418) /**< \brief (QSPI) Interrupt Enable Set */
-#define REG_QSPI_INTFLAG           (0x4200341C) /**< \brief (QSPI) Interrupt Flag Status and Clear */
-#define REG_QSPI_STATUS            (0x42003420) /**< \brief (QSPI) Status Register */
-#define REG_QSPI_INSTRADDR         (0x42003430) /**< \brief (QSPI) Instruction Address */
-#define REG_QSPI_INSTRCTRL         (0x42003434) /**< \brief (QSPI) Instruction Code */
-#define REG_QSPI_INSTRFRAME        (0x42003438) /**< \brief (QSPI) Instruction Frame */
-#define REG_QSPI_SCRAMBCTRL        (0x42003440) /**< \brief (QSPI) Scrambling Mode */
-#define REG_QSPI_SCRAMBKEY         (0x42003444) /**< \brief (QSPI) Scrambling Key */
-#else
-#define REG_QSPI_CTRLA             (*(RwReg  *)0x42003400UL) /**< \brief (QSPI) Control A */
-#define REG_QSPI_CTRLB             (*(RwReg  *)0x42003404UL) /**< \brief (QSPI) Control B */
-#define REG_QSPI_BAUD              (*(RwReg  *)0x42003408UL) /**< \brief (QSPI) Baud Rate */
-#define REG_QSPI_RXDATA            (*(RoReg  *)0x4200340CUL) /**< \brief (QSPI) Receive Data */
-#define REG_QSPI_TXDATA            (*(WoReg  *)0x42003410UL) /**< \brief (QSPI) Transmit Data */
-#define REG_QSPI_INTENCLR          (*(RwReg  *)0x42003414UL) /**< \brief (QSPI) Interrupt Enable Clear */
-#define REG_QSPI_INTENSET          (*(RwReg  *)0x42003418UL) /**< \brief (QSPI) Interrupt Enable Set */
-#define REG_QSPI_INTFLAG           (*(RwReg  *)0x4200341CUL) /**< \brief (QSPI) Interrupt Flag Status and Clear */
-#define REG_QSPI_STATUS            (*(RoReg  *)0x42003420UL) /**< \brief (QSPI) Status Register */
-#define REG_QSPI_INSTRADDR         (*(RwReg  *)0x42003430UL) /**< \brief (QSPI) Instruction Address */
-#define REG_QSPI_INSTRCTRL         (*(RwReg  *)0x42003434UL) /**< \brief (QSPI) Instruction Code */
-#define REG_QSPI_INSTRFRAME        (*(RwReg  *)0x42003438UL) /**< \brief (QSPI) Instruction Frame */
-#define REG_QSPI_SCRAMBCTRL        (*(RwReg  *)0x42003440UL) /**< \brief (QSPI) Scrambling Mode */
-#define REG_QSPI_SCRAMBKEY         (*(WoReg  *)0x42003444UL) /**< \brief (QSPI) Scrambling Key */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for QSPI peripheral ========== */
-#define QSPI_DMAC_ID_RX             83      
-#define QSPI_DMAC_ID_TX             84      
-#define QSPI_HADDR_MSB              23      
-#define QSPI_OCMS                   1       
-
-#endif /* _SAMD51_QSPI_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/ramecc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/ramecc.h
deleted file mode 100644
index c162e1e8d1..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/ramecc.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for RAMECC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_RAMECC_INSTANCE_
-#define _SAMD51_RAMECC_INSTANCE_
-
-/* ========== Register definition for RAMECC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_RAMECC_INTENCLR        (0x41020000) /**< \brief (RAMECC) Interrupt Enable Clear */
-#define REG_RAMECC_INTENSET        (0x41020001) /**< \brief (RAMECC) Interrupt Enable Set */
-#define REG_RAMECC_INTFLAG         (0x41020002) /**< \brief (RAMECC) Interrupt Flag */
-#define REG_RAMECC_STATUS          (0x41020003) /**< \brief (RAMECC) Status */
-#define REG_RAMECC_ERRADDR         (0x41020004) /**< \brief (RAMECC) Error Address */
-#define REG_RAMECC_DBGCTRL         (0x4102000F) /**< \brief (RAMECC) Debug Control */
-#else
-#define REG_RAMECC_INTENCLR        (*(RwReg8 *)0x41020000UL) /**< \brief (RAMECC) Interrupt Enable Clear */
-#define REG_RAMECC_INTENSET        (*(RwReg8 *)0x41020001UL) /**< \brief (RAMECC) Interrupt Enable Set */
-#define REG_RAMECC_INTFLAG         (*(RwReg8 *)0x41020002UL) /**< \brief (RAMECC) Interrupt Flag */
-#define REG_RAMECC_STATUS          (*(RoReg8 *)0x41020003UL) /**< \brief (RAMECC) Status */
-#define REG_RAMECC_ERRADDR         (*(RoReg  *)0x41020004UL) /**< \brief (RAMECC) Error Address */
-#define REG_RAMECC_DBGCTRL         (*(RwReg8 *)0x4102000FUL) /**< \brief (RAMECC) Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for RAMECC peripheral ========== */
-#define RAMECC_RAMADDR_BITS         13       // Number of RAM address bits
-#define RAMECC_RAMBANK_NUM          4        // Number of RAM banks
-
-#endif /* _SAMD51_RAMECC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/rstc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/rstc.h
deleted file mode 100644
index f1e5d7db78..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/rstc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for RSTC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_RSTC_INSTANCE_
-#define _SAMD51_RSTC_INSTANCE_
-
-/* ========== Register definition for RSTC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_RSTC_RCAUSE            (0x40000C00) /**< \brief (RSTC) Reset Cause */
-#define REG_RSTC_BKUPEXIT          (0x40000C02) /**< \brief (RSTC) Backup Exit Source */
-#else
-#define REG_RSTC_RCAUSE            (*(RoReg8 *)0x40000C00UL) /**< \brief (RSTC) Reset Cause */
-#define REG_RSTC_BKUPEXIT          (*(RoReg8 *)0x40000C02UL) /**< \brief (RSTC) Backup Exit Source */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for RSTC peripheral ========== */
-#define RSTC_BACKUP_IMPLEMENTED     1       
-#define RSTC_HIB_IMPLEMENTED        1       
-#define RSTC_NUMBER_OF_EXTWAKE      0        // number of external wakeup line
-#define RSTC_NVMRST_IMPLEMENTED     1       
-
-#endif /* _SAMD51_RSTC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/rtc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/rtc.h
deleted file mode 100644
index c31c674528..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/rtc.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for RTC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_RTC_INSTANCE_
-#define _SAMD51_RTC_INSTANCE_
-
-/* ========== Register definition for RTC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_RTC_DBGCTRL            (0x4000240E) /**< \brief (RTC) Debug Control */
-#define REG_RTC_FREQCORR           (0x40002414) /**< \brief (RTC) Frequency Correction */
-#define REG_RTC_GP0                (0x40002440) /**< \brief (RTC) General Purpose 0 */
-#define REG_RTC_GP1                (0x40002444) /**< \brief (RTC) General Purpose 1 */
-#define REG_RTC_GP2                (0x40002448) /**< \brief (RTC) General Purpose 2 */
-#define REG_RTC_GP3                (0x4000244C) /**< \brief (RTC) General Purpose 3 */
-#define REG_RTC_TAMPCTRL           (0x40002460) /**< \brief (RTC) Tamper Control */
-#define REG_RTC_TAMPID             (0x40002468) /**< \brief (RTC) Tamper ID */
-#define REG_RTC_BKUP0              (0x40002480) /**< \brief (RTC) Backup 0 */
-#define REG_RTC_BKUP1              (0x40002484) /**< \brief (RTC) Backup 1 */
-#define REG_RTC_BKUP2              (0x40002488) /**< \brief (RTC) Backup 2 */
-#define REG_RTC_BKUP3              (0x4000248C) /**< \brief (RTC) Backup 3 */
-#define REG_RTC_BKUP4              (0x40002490) /**< \brief (RTC) Backup 4 */
-#define REG_RTC_BKUP5              (0x40002494) /**< \brief (RTC) Backup 5 */
-#define REG_RTC_BKUP6              (0x40002498) /**< \brief (RTC) Backup 6 */
-#define REG_RTC_BKUP7              (0x4000249C) /**< \brief (RTC) Backup 7 */
-#define REG_RTC_MODE0_CTRLA        (0x40002400) /**< \brief (RTC) MODE0 Control A */
-#define REG_RTC_MODE0_CTRLB        (0x40002402) /**< \brief (RTC) MODE0 Control B */
-#define REG_RTC_MODE0_EVCTRL       (0x40002404) /**< \brief (RTC) MODE0 Event Control */
-#define REG_RTC_MODE0_INTENCLR     (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
-#define REG_RTC_MODE0_INTENSET     (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */
-#define REG_RTC_MODE0_INTFLAG      (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE0_SYNCBUSY     (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */
-#define REG_RTC_MODE0_COUNT        (0x40002418) /**< \brief (RTC) MODE0 Counter Value */
-#define REG_RTC_MODE0_COMP0        (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */
-#define REG_RTC_MODE0_COMP1        (0x40002424) /**< \brief (RTC) MODE0 Compare 1 Value */
-#define REG_RTC_MODE0_TIMESTAMP    (0x40002464) /**< \brief (RTC) MODE0 Timestamp */
-#define REG_RTC_MODE1_CTRLA        (0x40002400) /**< \brief (RTC) MODE1 Control A */
-#define REG_RTC_MODE1_CTRLB        (0x40002402) /**< \brief (RTC) MODE1 Control B */
-#define REG_RTC_MODE1_EVCTRL       (0x40002404) /**< \brief (RTC) MODE1 Event Control */
-#define REG_RTC_MODE1_INTENCLR     (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
-#define REG_RTC_MODE1_INTENSET     (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */
-#define REG_RTC_MODE1_INTFLAG      (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE1_SYNCBUSY     (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */
-#define REG_RTC_MODE1_COUNT        (0x40002418) /**< \brief (RTC) MODE1 Counter Value */
-#define REG_RTC_MODE1_PER          (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */
-#define REG_RTC_MODE1_COMP0        (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */
-#define REG_RTC_MODE1_COMP1        (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */
-#define REG_RTC_MODE1_COMP2        (0x40002424) /**< \brief (RTC) MODE1 Compare 2 Value */
-#define REG_RTC_MODE1_COMP3        (0x40002426) /**< \brief (RTC) MODE1 Compare 3 Value */
-#define REG_RTC_MODE1_TIMESTAMP    (0x40002464) /**< \brief (RTC) MODE1 Timestamp */
-#define REG_RTC_MODE2_CTRLA        (0x40002400) /**< \brief (RTC) MODE2 Control A */
-#define REG_RTC_MODE2_CTRLB        (0x40002402) /**< \brief (RTC) MODE2 Control B */
-#define REG_RTC_MODE2_EVCTRL       (0x40002404) /**< \brief (RTC) MODE2 Event Control */
-#define REG_RTC_MODE2_INTENCLR     (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
-#define REG_RTC_MODE2_INTENSET     (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */
-#define REG_RTC_MODE2_INTFLAG      (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE2_SYNCBUSY     (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */
-#define REG_RTC_MODE2_CLOCK        (0x40002418) /**< \brief (RTC) MODE2 Clock Value */
-#define REG_RTC_MODE2_TIMESTAMP    (0x40002464) /**< \brief (RTC) MODE2 Timestamp */
-#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
-#define REG_RTC_MODE2_ALARM_MASK0  (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
-#define REG_RTC_MODE2_ALARM_ALARM1 (0x40002428) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
-#define REG_RTC_MODE2_ALARM_MASK1  (0x4000242C) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
-#else
-#define REG_RTC_DBGCTRL            (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */
-#define REG_RTC_FREQCORR           (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */
-#define REG_RTC_GP0                (*(RwReg  *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */
-#define REG_RTC_GP1                (*(RwReg  *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */
-#define REG_RTC_GP2                (*(RwReg  *)0x40002448UL) /**< \brief (RTC) General Purpose 2 */
-#define REG_RTC_GP3                (*(RwReg  *)0x4000244CUL) /**< \brief (RTC) General Purpose 3 */
-#define REG_RTC_TAMPCTRL           (*(RwReg  *)0x40002460UL) /**< \brief (RTC) Tamper Control */
-#define REG_RTC_TAMPID             (*(RwReg  *)0x40002468UL) /**< \brief (RTC) Tamper ID */
-#define REG_RTC_BKUP0              (*(RwReg  *)0x40002480UL) /**< \brief (RTC) Backup 0 */
-#define REG_RTC_BKUP1              (*(RwReg  *)0x40002484UL) /**< \brief (RTC) Backup 1 */
-#define REG_RTC_BKUP2              (*(RwReg  *)0x40002488UL) /**< \brief (RTC) Backup 2 */
-#define REG_RTC_BKUP3              (*(RwReg  *)0x4000248CUL) /**< \brief (RTC) Backup 3 */
-#define REG_RTC_BKUP4              (*(RwReg  *)0x40002490UL) /**< \brief (RTC) Backup 4 */
-#define REG_RTC_BKUP5              (*(RwReg  *)0x40002494UL) /**< \brief (RTC) Backup 5 */
-#define REG_RTC_BKUP6              (*(RwReg  *)0x40002498UL) /**< \brief (RTC) Backup 6 */
-#define REG_RTC_BKUP7              (*(RwReg  *)0x4000249CUL) /**< \brief (RTC) Backup 7 */
-#define REG_RTC_MODE0_CTRLA        (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */
-#define REG_RTC_MODE0_CTRLB        (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */
-#define REG_RTC_MODE0_EVCTRL       (*(RwReg  *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */
-#define REG_RTC_MODE0_INTENCLR     (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
-#define REG_RTC_MODE0_INTENSET     (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
-#define REG_RTC_MODE0_INTFLAG      (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE0_SYNCBUSY     (*(RoReg  *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */
-#define REG_RTC_MODE0_COUNT        (*(RwReg  *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */
-#define REG_RTC_MODE0_COMP0        (*(RwReg  *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */
-#define REG_RTC_MODE0_COMP1        (*(RwReg  *)0x40002424UL) /**< \brief (RTC) MODE0 Compare 1 Value */
-#define REG_RTC_MODE0_TIMESTAMP    (*(RoReg  *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */
-#define REG_RTC_MODE1_CTRLA        (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */
-#define REG_RTC_MODE1_CTRLB        (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */
-#define REG_RTC_MODE1_EVCTRL       (*(RwReg  *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */
-#define REG_RTC_MODE1_INTENCLR     (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
-#define REG_RTC_MODE1_INTENSET     (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
-#define REG_RTC_MODE1_INTFLAG      (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE1_SYNCBUSY     (*(RoReg  *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */
-#define REG_RTC_MODE1_COUNT        (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */
-#define REG_RTC_MODE1_PER          (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */
-#define REG_RTC_MODE1_COMP0        (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */
-#define REG_RTC_MODE1_COMP1        (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */
-#define REG_RTC_MODE1_COMP2        (*(RwReg16*)0x40002424UL) /**< \brief (RTC) MODE1 Compare 2 Value */
-#define REG_RTC_MODE1_COMP3        (*(RwReg16*)0x40002426UL) /**< \brief (RTC) MODE1 Compare 3 Value */
-#define REG_RTC_MODE1_TIMESTAMP    (*(RoReg  *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */
-#define REG_RTC_MODE2_CTRLA        (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */
-#define REG_RTC_MODE2_CTRLB        (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */
-#define REG_RTC_MODE2_EVCTRL       (*(RwReg  *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */
-#define REG_RTC_MODE2_INTENCLR     (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
-#define REG_RTC_MODE2_INTENSET     (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
-#define REG_RTC_MODE2_INTFLAG      (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
-#define REG_RTC_MODE2_SYNCBUSY     (*(RoReg  *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */
-#define REG_RTC_MODE2_CLOCK        (*(RwReg  *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */
-#define REG_RTC_MODE2_TIMESTAMP    (*(RoReg  *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */
-#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg  *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
-#define REG_RTC_MODE2_ALARM_MASK0  (*(RwReg  *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
-#define REG_RTC_MODE2_ALARM_ALARM1 (*(RwReg  *)0x40002428UL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
-#define REG_RTC_MODE2_ALARM_MASK1  (*(RwReg  *)0x4000242CUL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for RTC peripheral ========== */
-#define RTC_DMAC_ID_TIMESTAMP       1        // DMA RTC timestamp trigger
-#define RTC_GPR_NUM                 4        // Number of General-Purpose Registers
-#define RTC_NUM_OF_ALARMS           2        // Number of Alarms
-#define RTC_NUM_OF_BKREGS           8        // Number of Backup Registers
-#define RTC_NUM_OF_COMP16           4        // Number of 16-bit Comparators
-#define RTC_NUM_OF_COMP32           2        // Number of 32-bit Comparators
-#define RTC_NUM_OF_TAMPERS          5        // Number of Tamper Inputs
-#define RTC_PER_NUM                 8        // Number of Periodic Intervals
-
-#endif /* _SAMD51_RTC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sdhc0.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sdhc0.h
deleted file mode 100644
index c7f723da5c..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sdhc0.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SDHC0
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SDHC0_INSTANCE_
-#define _SAMD51_SDHC0_INSTANCE_
-
-/* ========== Register definition for SDHC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SDHC0_SSAR             (0x45000000) /**< \brief (SDHC0) SDMA System Address / Argument 2 */
-#define REG_SDHC0_BSR              (0x45000004) /**< \brief (SDHC0) Block Size */
-#define REG_SDHC0_BCR              (0x45000006) /**< \brief (SDHC0) Block Count */
-#define REG_SDHC0_ARG1R            (0x45000008) /**< \brief (SDHC0) Argument 1 */
-#define REG_SDHC0_TMR              (0x4500000C) /**< \brief (SDHC0) Transfer Mode */
-#define REG_SDHC0_CR               (0x4500000E) /**< \brief (SDHC0) Command */
-#define REG_SDHC0_RR0              (0x45000010) /**< \brief (SDHC0) Response 0 */
-#define REG_SDHC0_RR1              (0x45000014) /**< \brief (SDHC0) Response 1 */
-#define REG_SDHC0_RR2              (0x45000018) /**< \brief (SDHC0) Response 2 */
-#define REG_SDHC0_RR3              (0x4500001C) /**< \brief (SDHC0) Response 3 */
-#define REG_SDHC0_BDPR             (0x45000020) /**< \brief (SDHC0) Buffer Data Port */
-#define REG_SDHC0_PSR              (0x45000024) /**< \brief (SDHC0) Present State */
-#define REG_SDHC0_HC1R             (0x45000028) /**< \brief (SDHC0) Host Control 1 */
-#define REG_SDHC0_PCR              (0x45000029) /**< \brief (SDHC0) Power Control */
-#define REG_SDHC0_BGCR             (0x4500002A) /**< \brief (SDHC0) Block Gap Control */
-#define REG_SDHC0_WCR              (0x4500002B) /**< \brief (SDHC0) Wakeup Control */
-#define REG_SDHC0_CCR              (0x4500002C) /**< \brief (SDHC0) Clock Control */
-#define REG_SDHC0_TCR              (0x4500002E) /**< \brief (SDHC0) Timeout Control */
-#define REG_SDHC0_SRR              (0x4500002F) /**< \brief (SDHC0) Software Reset */
-#define REG_SDHC0_NISTR            (0x45000030) /**< \brief (SDHC0) Normal Interrupt Status */
-#define REG_SDHC0_EISTR            (0x45000032) /**< \brief (SDHC0) Error Interrupt Status */
-#define REG_SDHC0_NISTER           (0x45000034) /**< \brief (SDHC0) Normal Interrupt Status Enable */
-#define REG_SDHC0_EISTER           (0x45000036) /**< \brief (SDHC0) Error Interrupt Status Enable */
-#define REG_SDHC0_NISIER           (0x45000038) /**< \brief (SDHC0) Normal Interrupt Signal Enable */
-#define REG_SDHC0_EISIER           (0x4500003A) /**< \brief (SDHC0) Error Interrupt Signal Enable */
-#define REG_SDHC0_ACESR            (0x4500003C) /**< \brief (SDHC0) Auto CMD Error Status */
-#define REG_SDHC0_HC2R             (0x4500003E) /**< \brief (SDHC0) Host Control 2 */
-#define REG_SDHC0_CA0R             (0x45000040) /**< \brief (SDHC0) Capabilities 0 */
-#define REG_SDHC0_CA1R             (0x45000044) /**< \brief (SDHC0) Capabilities 1 */
-#define REG_SDHC0_MCCAR            (0x45000048) /**< \brief (SDHC0) Maximum Current Capabilities */
-#define REG_SDHC0_FERACES          (0x45000050) /**< \brief (SDHC0) Force Event for Auto CMD Error Status */
-#define REG_SDHC0_FEREIS           (0x45000052) /**< \brief (SDHC0) Force Event for Error Interrupt Status */
-#define REG_SDHC0_AESR             (0x45000054) /**< \brief (SDHC0) ADMA Error Status */
-#define REG_SDHC0_ASAR0            (0x45000058) /**< \brief (SDHC0) ADMA System Address 0 */
-#define REG_SDHC0_PVR0             (0x45000060) /**< \brief (SDHC0) Preset Value 0 */
-#define REG_SDHC0_PVR1             (0x45000062) /**< \brief (SDHC0) Preset Value 1 */
-#define REG_SDHC0_PVR2             (0x45000064) /**< \brief (SDHC0) Preset Value 2 */
-#define REG_SDHC0_PVR3             (0x45000066) /**< \brief (SDHC0) Preset Value 3 */
-#define REG_SDHC0_PVR4             (0x45000068) /**< \brief (SDHC0) Preset Value 4 */
-#define REG_SDHC0_PVR5             (0x4500006A) /**< \brief (SDHC0) Preset Value 5 */
-#define REG_SDHC0_PVR6             (0x4500006C) /**< \brief (SDHC0) Preset Value 6 */
-#define REG_SDHC0_PVR7             (0x4500006E) /**< \brief (SDHC0) Preset Value 7 */
-#define REG_SDHC0_SISR             (0x450000FC) /**< \brief (SDHC0) Slot Interrupt Status */
-#define REG_SDHC0_HCVR             (0x450000FE) /**< \brief (SDHC0) Host Controller Version */
-#define REG_SDHC0_MC1R             (0x45000204) /**< \brief (SDHC0) MMC Control 1 */
-#define REG_SDHC0_MC2R             (0x45000205) /**< \brief (SDHC0) MMC Control 2 */
-#define REG_SDHC0_ACR              (0x45000208) /**< \brief (SDHC0) AHB Control */
-#define REG_SDHC0_CC2R             (0x4500020C) /**< \brief (SDHC0) Clock Control 2 */
-#define REG_SDHC0_CACR             (0x45000230) /**< \brief (SDHC0) Capabilities Control */
-#define REG_SDHC0_DBGR             (0x45000234) /**< \brief (SDHC0) Debug */
-#else
-#define REG_SDHC0_SSAR             (*(RwReg  *)0x45000000UL) /**< \brief (SDHC0) SDMA System Address / Argument 2 */
-#define REG_SDHC0_BSR              (*(RwReg16*)0x45000004UL) /**< \brief (SDHC0) Block Size */
-#define REG_SDHC0_BCR              (*(RwReg16*)0x45000006UL) /**< \brief (SDHC0) Block Count */
-#define REG_SDHC0_ARG1R            (*(RwReg  *)0x45000008UL) /**< \brief (SDHC0) Argument 1 */
-#define REG_SDHC0_TMR              (*(RwReg16*)0x4500000CUL) /**< \brief (SDHC0) Transfer Mode */
-#define REG_SDHC0_CR               (*(RwReg16*)0x4500000EUL) /**< \brief (SDHC0) Command */
-#define REG_SDHC0_RR0              (*(RoReg  *)0x45000010UL) /**< \brief (SDHC0) Response 0 */
-#define REG_SDHC0_RR1              (*(RoReg  *)0x45000014UL) /**< \brief (SDHC0) Response 1 */
-#define REG_SDHC0_RR2              (*(RoReg  *)0x45000018UL) /**< \brief (SDHC0) Response 2 */
-#define REG_SDHC0_RR3              (*(RoReg  *)0x4500001CUL) /**< \brief (SDHC0) Response 3 */
-#define REG_SDHC0_BDPR             (*(RwReg  *)0x45000020UL) /**< \brief (SDHC0) Buffer Data Port */
-#define REG_SDHC0_PSR              (*(RoReg  *)0x45000024UL) /**< \brief (SDHC0) Present State */
-#define REG_SDHC0_HC1R             (*(RwReg8 *)0x45000028UL) /**< \brief (SDHC0) Host Control 1 */
-#define REG_SDHC0_PCR              (*(RwReg8 *)0x45000029UL) /**< \brief (SDHC0) Power Control */
-#define REG_SDHC0_BGCR             (*(RwReg8 *)0x4500002AUL) /**< \brief (SDHC0) Block Gap Control */
-#define REG_SDHC0_WCR              (*(RwReg8 *)0x4500002BUL) /**< \brief (SDHC0) Wakeup Control */
-#define REG_SDHC0_CCR              (*(RwReg16*)0x4500002CUL) /**< \brief (SDHC0) Clock Control */
-#define REG_SDHC0_TCR              (*(RwReg8 *)0x4500002EUL) /**< \brief (SDHC0) Timeout Control */
-#define REG_SDHC0_SRR              (*(RwReg8 *)0x4500002FUL) /**< \brief (SDHC0) Software Reset */
-#define REG_SDHC0_NISTR            (*(RwReg16*)0x45000030UL) /**< \brief (SDHC0) Normal Interrupt Status */
-#define REG_SDHC0_EISTR            (*(RwReg16*)0x45000032UL) /**< \brief (SDHC0) Error Interrupt Status */
-#define REG_SDHC0_NISTER           (*(RwReg16*)0x45000034UL) /**< \brief (SDHC0) Normal Interrupt Status Enable */
-#define REG_SDHC0_EISTER           (*(RwReg16*)0x45000036UL) /**< \brief (SDHC0) Error Interrupt Status Enable */
-#define REG_SDHC0_NISIER           (*(RwReg16*)0x45000038UL) /**< \brief (SDHC0) Normal Interrupt Signal Enable */
-#define REG_SDHC0_EISIER           (*(RwReg16*)0x4500003AUL) /**< \brief (SDHC0) Error Interrupt Signal Enable */
-#define REG_SDHC0_ACESR            (*(RoReg16*)0x4500003CUL) /**< \brief (SDHC0) Auto CMD Error Status */
-#define REG_SDHC0_HC2R             (*(RwReg16*)0x4500003EUL) /**< \brief (SDHC0) Host Control 2 */
-#define REG_SDHC0_CA0R             (*(RoReg  *)0x45000040UL) /**< \brief (SDHC0) Capabilities 0 */
-#define REG_SDHC0_CA1R             (*(RoReg  *)0x45000044UL) /**< \brief (SDHC0) Capabilities 1 */
-#define REG_SDHC0_MCCAR            (*(RoReg  *)0x45000048UL) /**< \brief (SDHC0) Maximum Current Capabilities */
-#define REG_SDHC0_FERACES          (*(WoReg16*)0x45000050UL) /**< \brief (SDHC0) Force Event for Auto CMD Error Status */
-#define REG_SDHC0_FEREIS           (*(WoReg16*)0x45000052UL) /**< \brief (SDHC0) Force Event for Error Interrupt Status */
-#define REG_SDHC0_AESR             (*(RoReg8 *)0x45000054UL) /**< \brief (SDHC0) ADMA Error Status */
-#define REG_SDHC0_ASAR0            (*(RwReg  *)0x45000058UL) /**< \brief (SDHC0) ADMA System Address 0 */
-#define REG_SDHC0_PVR0             (*(RwReg16*)0x45000060UL) /**< \brief (SDHC0) Preset Value 0 */
-#define REG_SDHC0_PVR1             (*(RwReg16*)0x45000062UL) /**< \brief (SDHC0) Preset Value 1 */
-#define REG_SDHC0_PVR2             (*(RwReg16*)0x45000064UL) /**< \brief (SDHC0) Preset Value 2 */
-#define REG_SDHC0_PVR3             (*(RwReg16*)0x45000066UL) /**< \brief (SDHC0) Preset Value 3 */
-#define REG_SDHC0_PVR4             (*(RwReg16*)0x45000068UL) /**< \brief (SDHC0) Preset Value 4 */
-#define REG_SDHC0_PVR5             (*(RwReg16*)0x4500006AUL) /**< \brief (SDHC0) Preset Value 5 */
-#define REG_SDHC0_PVR6             (*(RwReg16*)0x4500006CUL) /**< \brief (SDHC0) Preset Value 6 */
-#define REG_SDHC0_PVR7             (*(RwReg16*)0x4500006EUL) /**< \brief (SDHC0) Preset Value 7 */
-#define REG_SDHC0_SISR             (*(RoReg16*)0x450000FCUL) /**< \brief (SDHC0) Slot Interrupt Status */
-#define REG_SDHC0_HCVR             (*(RoReg16*)0x450000FEUL) /**< \brief (SDHC0) Host Controller Version */
-#define REG_SDHC0_MC1R             (*(RwReg8 *)0x45000204UL) /**< \brief (SDHC0) MMC Control 1 */
-#define REG_SDHC0_MC2R             (*(WoReg8 *)0x45000205UL) /**< \brief (SDHC0) MMC Control 2 */
-#define REG_SDHC0_ACR              (*(RwReg  *)0x45000208UL) /**< \brief (SDHC0) AHB Control */
-#define REG_SDHC0_CC2R             (*(RwReg  *)0x4500020CUL) /**< \brief (SDHC0) Clock Control 2 */
-#define REG_SDHC0_CACR             (*(RwReg  *)0x45000230UL) /**< \brief (SDHC0) Capabilities Control */
-#define REG_SDHC0_DBGR             (*(RwReg8 *)0x45000234UL) /**< \brief (SDHC0) Debug */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SDHC0 peripheral ========== */
-#define SDHC0_CARD_DATA_SIZE        4       
-#define SDHC0_CLK_AHB_ID            15      
-#define SDHC0_GCLK_ID               45      
-#define SDHC0_GCLK_ID_SLOW          3       
-#define SDHC0_NB_OF_DEVICES         1       
-#define SDHC0_NB_REG_PVR            8       
-#define SDHC0_NB_REG_RR             4       
-
-#endif /* _SAMD51_SDHC0_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sdhc1.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sdhc1.h
deleted file mode 100644
index 94eeaaab2c..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sdhc1.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SDHC1
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SDHC1_INSTANCE_
-#define _SAMD51_SDHC1_INSTANCE_
-
-/* ========== Register definition for SDHC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SDHC1_SSAR             (0x46000000) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
-#define REG_SDHC1_BSR              (0x46000004) /**< \brief (SDHC1) Block Size */
-#define REG_SDHC1_BCR              (0x46000006) /**< \brief (SDHC1) Block Count */
-#define REG_SDHC1_ARG1R            (0x46000008) /**< \brief (SDHC1) Argument 1 */
-#define REG_SDHC1_TMR              (0x4600000C) /**< \brief (SDHC1) Transfer Mode */
-#define REG_SDHC1_CR               (0x4600000E) /**< \brief (SDHC1) Command */
-#define REG_SDHC1_RR0              (0x46000010) /**< \brief (SDHC1) Response 0 */
-#define REG_SDHC1_RR1              (0x46000014) /**< \brief (SDHC1) Response 1 */
-#define REG_SDHC1_RR2              (0x46000018) /**< \brief (SDHC1) Response 2 */
-#define REG_SDHC1_RR3              (0x4600001C) /**< \brief (SDHC1) Response 3 */
-#define REG_SDHC1_BDPR             (0x46000020) /**< \brief (SDHC1) Buffer Data Port */
-#define REG_SDHC1_PSR              (0x46000024) /**< \brief (SDHC1) Present State */
-#define REG_SDHC1_HC1R             (0x46000028) /**< \brief (SDHC1) Host Control 1 */
-#define REG_SDHC1_PCR              (0x46000029) /**< \brief (SDHC1) Power Control */
-#define REG_SDHC1_BGCR             (0x4600002A) /**< \brief (SDHC1) Block Gap Control */
-#define REG_SDHC1_WCR              (0x4600002B) /**< \brief (SDHC1) Wakeup Control */
-#define REG_SDHC1_CCR              (0x4600002C) /**< \brief (SDHC1) Clock Control */
-#define REG_SDHC1_TCR              (0x4600002E) /**< \brief (SDHC1) Timeout Control */
-#define REG_SDHC1_SRR              (0x4600002F) /**< \brief (SDHC1) Software Reset */
-#define REG_SDHC1_NISTR            (0x46000030) /**< \brief (SDHC1) Normal Interrupt Status */
-#define REG_SDHC1_EISTR            (0x46000032) /**< \brief (SDHC1) Error Interrupt Status */
-#define REG_SDHC1_NISTER           (0x46000034) /**< \brief (SDHC1) Normal Interrupt Status Enable */
-#define REG_SDHC1_EISTER           (0x46000036) /**< \brief (SDHC1) Error Interrupt Status Enable */
-#define REG_SDHC1_NISIER           (0x46000038) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
-#define REG_SDHC1_EISIER           (0x4600003A) /**< \brief (SDHC1) Error Interrupt Signal Enable */
-#define REG_SDHC1_ACESR            (0x4600003C) /**< \brief (SDHC1) Auto CMD Error Status */
-#define REG_SDHC1_HC2R             (0x4600003E) /**< \brief (SDHC1) Host Control 2 */
-#define REG_SDHC1_CA0R             (0x46000040) /**< \brief (SDHC1) Capabilities 0 */
-#define REG_SDHC1_CA1R             (0x46000044) /**< \brief (SDHC1) Capabilities 1 */
-#define REG_SDHC1_MCCAR            (0x46000048) /**< \brief (SDHC1) Maximum Current Capabilities */
-#define REG_SDHC1_FERACES          (0x46000050) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
-#define REG_SDHC1_FEREIS           (0x46000052) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
-#define REG_SDHC1_AESR             (0x46000054) /**< \brief (SDHC1) ADMA Error Status */
-#define REG_SDHC1_ASAR0            (0x46000058) /**< \brief (SDHC1) ADMA System Address 0 */
-#define REG_SDHC1_PVR0             (0x46000060) /**< \brief (SDHC1) Preset Value 0 */
-#define REG_SDHC1_PVR1             (0x46000062) /**< \brief (SDHC1) Preset Value 1 */
-#define REG_SDHC1_PVR2             (0x46000064) /**< \brief (SDHC1) Preset Value 2 */
-#define REG_SDHC1_PVR3             (0x46000066) /**< \brief (SDHC1) Preset Value 3 */
-#define REG_SDHC1_PVR4             (0x46000068) /**< \brief (SDHC1) Preset Value 4 */
-#define REG_SDHC1_PVR5             (0x4600006A) /**< \brief (SDHC1) Preset Value 5 */
-#define REG_SDHC1_PVR6             (0x4600006C) /**< \brief (SDHC1) Preset Value 6 */
-#define REG_SDHC1_PVR7             (0x4600006E) /**< \brief (SDHC1) Preset Value 7 */
-#define REG_SDHC1_SISR             (0x460000FC) /**< \brief (SDHC1) Slot Interrupt Status */
-#define REG_SDHC1_HCVR             (0x460000FE) /**< \brief (SDHC1) Host Controller Version */
-#define REG_SDHC1_MC1R             (0x46000204) /**< \brief (SDHC1) MMC Control 1 */
-#define REG_SDHC1_MC2R             (0x46000205) /**< \brief (SDHC1) MMC Control 2 */
-#define REG_SDHC1_ACR              (0x46000208) /**< \brief (SDHC1) AHB Control */
-#define REG_SDHC1_CC2R             (0x4600020C) /**< \brief (SDHC1) Clock Control 2 */
-#define REG_SDHC1_CACR             (0x46000230) /**< \brief (SDHC1) Capabilities Control */
-#define REG_SDHC1_DBGR             (0x46000234) /**< \brief (SDHC1) Debug */
-#else
-#define REG_SDHC1_SSAR             (*(RwReg  *)0x46000000UL) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
-#define REG_SDHC1_BSR              (*(RwReg16*)0x46000004UL) /**< \brief (SDHC1) Block Size */
-#define REG_SDHC1_BCR              (*(RwReg16*)0x46000006UL) /**< \brief (SDHC1) Block Count */
-#define REG_SDHC1_ARG1R            (*(RwReg  *)0x46000008UL) /**< \brief (SDHC1) Argument 1 */
-#define REG_SDHC1_TMR              (*(RwReg16*)0x4600000CUL) /**< \brief (SDHC1) Transfer Mode */
-#define REG_SDHC1_CR               (*(RwReg16*)0x4600000EUL) /**< \brief (SDHC1) Command */
-#define REG_SDHC1_RR0              (*(RoReg  *)0x46000010UL) /**< \brief (SDHC1) Response 0 */
-#define REG_SDHC1_RR1              (*(RoReg  *)0x46000014UL) /**< \brief (SDHC1) Response 1 */
-#define REG_SDHC1_RR2              (*(RoReg  *)0x46000018UL) /**< \brief (SDHC1) Response 2 */
-#define REG_SDHC1_RR3              (*(RoReg  *)0x4600001CUL) /**< \brief (SDHC1) Response 3 */
-#define REG_SDHC1_BDPR             (*(RwReg  *)0x46000020UL) /**< \brief (SDHC1) Buffer Data Port */
-#define REG_SDHC1_PSR              (*(RoReg  *)0x46000024UL) /**< \brief (SDHC1) Present State */
-#define REG_SDHC1_HC1R             (*(RwReg8 *)0x46000028UL) /**< \brief (SDHC1) Host Control 1 */
-#define REG_SDHC1_PCR              (*(RwReg8 *)0x46000029UL) /**< \brief (SDHC1) Power Control */
-#define REG_SDHC1_BGCR             (*(RwReg8 *)0x4600002AUL) /**< \brief (SDHC1) Block Gap Control */
-#define REG_SDHC1_WCR              (*(RwReg8 *)0x4600002BUL) /**< \brief (SDHC1) Wakeup Control */
-#define REG_SDHC1_CCR              (*(RwReg16*)0x4600002CUL) /**< \brief (SDHC1) Clock Control */
-#define REG_SDHC1_TCR              (*(RwReg8 *)0x4600002EUL) /**< \brief (SDHC1) Timeout Control */
-#define REG_SDHC1_SRR              (*(RwReg8 *)0x4600002FUL) /**< \brief (SDHC1) Software Reset */
-#define REG_SDHC1_NISTR            (*(RwReg16*)0x46000030UL) /**< \brief (SDHC1) Normal Interrupt Status */
-#define REG_SDHC1_EISTR            (*(RwReg16*)0x46000032UL) /**< \brief (SDHC1) Error Interrupt Status */
-#define REG_SDHC1_NISTER           (*(RwReg16*)0x46000034UL) /**< \brief (SDHC1) Normal Interrupt Status Enable */
-#define REG_SDHC1_EISTER           (*(RwReg16*)0x46000036UL) /**< \brief (SDHC1) Error Interrupt Status Enable */
-#define REG_SDHC1_NISIER           (*(RwReg16*)0x46000038UL) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
-#define REG_SDHC1_EISIER           (*(RwReg16*)0x4600003AUL) /**< \brief (SDHC1) Error Interrupt Signal Enable */
-#define REG_SDHC1_ACESR            (*(RoReg16*)0x4600003CUL) /**< \brief (SDHC1) Auto CMD Error Status */
-#define REG_SDHC1_HC2R             (*(RwReg16*)0x4600003EUL) /**< \brief (SDHC1) Host Control 2 */
-#define REG_SDHC1_CA0R             (*(RoReg  *)0x46000040UL) /**< \brief (SDHC1) Capabilities 0 */
-#define REG_SDHC1_CA1R             (*(RoReg  *)0x46000044UL) /**< \brief (SDHC1) Capabilities 1 */
-#define REG_SDHC1_MCCAR            (*(RoReg  *)0x46000048UL) /**< \brief (SDHC1) Maximum Current Capabilities */
-#define REG_SDHC1_FERACES          (*(WoReg16*)0x46000050UL) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
-#define REG_SDHC1_FEREIS           (*(WoReg16*)0x46000052UL) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
-#define REG_SDHC1_AESR             (*(RoReg8 *)0x46000054UL) /**< \brief (SDHC1) ADMA Error Status */
-#define REG_SDHC1_ASAR0            (*(RwReg  *)0x46000058UL) /**< \brief (SDHC1) ADMA System Address 0 */
-#define REG_SDHC1_PVR0             (*(RwReg16*)0x46000060UL) /**< \brief (SDHC1) Preset Value 0 */
-#define REG_SDHC1_PVR1             (*(RwReg16*)0x46000062UL) /**< \brief (SDHC1) Preset Value 1 */
-#define REG_SDHC1_PVR2             (*(RwReg16*)0x46000064UL) /**< \brief (SDHC1) Preset Value 2 */
-#define REG_SDHC1_PVR3             (*(RwReg16*)0x46000066UL) /**< \brief (SDHC1) Preset Value 3 */
-#define REG_SDHC1_PVR4             (*(RwReg16*)0x46000068UL) /**< \brief (SDHC1) Preset Value 4 */
-#define REG_SDHC1_PVR5             (*(RwReg16*)0x4600006AUL) /**< \brief (SDHC1) Preset Value 5 */
-#define REG_SDHC1_PVR6             (*(RwReg16*)0x4600006CUL) /**< \brief (SDHC1) Preset Value 6 */
-#define REG_SDHC1_PVR7             (*(RwReg16*)0x4600006EUL) /**< \brief (SDHC1) Preset Value 7 */
-#define REG_SDHC1_SISR             (*(RoReg16*)0x460000FCUL) /**< \brief (SDHC1) Slot Interrupt Status */
-#define REG_SDHC1_HCVR             (*(RoReg16*)0x460000FEUL) /**< \brief (SDHC1) Host Controller Version */
-#define REG_SDHC1_MC1R             (*(RwReg8 *)0x46000204UL) /**< \brief (SDHC1) MMC Control 1 */
-#define REG_SDHC1_MC2R             (*(WoReg8 *)0x46000205UL) /**< \brief (SDHC1) MMC Control 2 */
-#define REG_SDHC1_ACR              (*(RwReg  *)0x46000208UL) /**< \brief (SDHC1) AHB Control */
-#define REG_SDHC1_CC2R             (*(RwReg  *)0x4600020CUL) /**< \brief (SDHC1) Clock Control 2 */
-#define REG_SDHC1_CACR             (*(RwReg  *)0x46000230UL) /**< \brief (SDHC1) Capabilities Control */
-#define REG_SDHC1_DBGR             (*(RwReg8 *)0x46000234UL) /**< \brief (SDHC1) Debug */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SDHC1 peripheral ========== */
-#define SDHC1_CARD_DATA_SIZE        4       
-#define SDHC1_CLK_AHB_ID            16      
-#define SDHC1_GCLK_ID               46      
-#define SDHC1_GCLK_ID_SLOW          3       
-#define SDHC1_NB_OF_DEVICES         1       
-#define SDHC1_NB_REG_PVR            8       
-#define SDHC1_NB_REG_RR             4       
-
-#endif /* _SAMD51_SDHC1_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom0.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom0.h
deleted file mode 100644
index cd440c5648..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom0.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM0
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SERCOM0_INSTANCE_
-#define _SAMD51_SERCOM0_INSTANCE_
-
-/* ========== Register definition for SERCOM0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM0_I2CM_CTRLA     (0x40003000) /**< \brief (SERCOM0) I2CM Control A */
-#define REG_SERCOM0_I2CM_CTRLB     (0x40003004) /**< \brief (SERCOM0) I2CM Control B */
-#define REG_SERCOM0_I2CM_CTRLC     (0x40003008) /**< \brief (SERCOM0) I2CM Control C */
-#define REG_SERCOM0_I2CM_BAUD      (0x4000300C) /**< \brief (SERCOM0) I2CM Baud Rate */
-#define REG_SERCOM0_I2CM_INTENCLR  (0x40003014) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
-#define REG_SERCOM0_I2CM_INTENSET  (0x40003016) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
-#define REG_SERCOM0_I2CM_INTFLAG   (0x40003018) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM0_I2CM_STATUS    (0x4000301A) /**< \brief (SERCOM0) I2CM Status */
-#define REG_SERCOM0_I2CM_SYNCBUSY  (0x4000301C) /**< \brief (SERCOM0) I2CM Synchronization Busy */
-#define REG_SERCOM0_I2CM_ADDR      (0x40003024) /**< \brief (SERCOM0) I2CM Address */
-#define REG_SERCOM0_I2CM_DATA      (0x40003028) /**< \brief (SERCOM0) I2CM Data */
-#define REG_SERCOM0_I2CM_DBGCTRL   (0x40003030) /**< \brief (SERCOM0) I2CM Debug Control */
-#define REG_SERCOM0_I2CS_CTRLA     (0x40003000) /**< \brief (SERCOM0) I2CS Control A */
-#define REG_SERCOM0_I2CS_CTRLB     (0x40003004) /**< \brief (SERCOM0) I2CS Control B */
-#define REG_SERCOM0_I2CS_CTRLC     (0x40003008) /**< \brief (SERCOM0) I2CS Control C */
-#define REG_SERCOM0_I2CS_INTENCLR  (0x40003014) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
-#define REG_SERCOM0_I2CS_INTENSET  (0x40003016) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
-#define REG_SERCOM0_I2CS_INTFLAG   (0x40003018) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM0_I2CS_STATUS    (0x4000301A) /**< \brief (SERCOM0) I2CS Status */
-#define REG_SERCOM0_I2CS_SYNCBUSY  (0x4000301C) /**< \brief (SERCOM0) I2CS Synchronization Busy */
-#define REG_SERCOM0_I2CS_LENGTH    (0x40003022) /**< \brief (SERCOM0) I2CS Length */
-#define REG_SERCOM0_I2CS_ADDR      (0x40003024) /**< \brief (SERCOM0) I2CS Address */
-#define REG_SERCOM0_I2CS_DATA      (0x40003028) /**< \brief (SERCOM0) I2CS Data */
-#define REG_SERCOM0_SPI_CTRLA      (0x40003000) /**< \brief (SERCOM0) SPI Control A */
-#define REG_SERCOM0_SPI_CTRLB      (0x40003004) /**< \brief (SERCOM0) SPI Control B */
-#define REG_SERCOM0_SPI_CTRLC      (0x40003008) /**< \brief (SERCOM0) SPI Control C */
-#define REG_SERCOM0_SPI_BAUD       (0x4000300C) /**< \brief (SERCOM0) SPI Baud Rate */
-#define REG_SERCOM0_SPI_INTENCLR   (0x40003014) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
-#define REG_SERCOM0_SPI_INTENSET   (0x40003016) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
-#define REG_SERCOM0_SPI_INTFLAG    (0x40003018) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM0_SPI_STATUS     (0x4000301A) /**< \brief (SERCOM0) SPI Status */
-#define REG_SERCOM0_SPI_SYNCBUSY   (0x4000301C) /**< \brief (SERCOM0) SPI Synchronization Busy */
-#define REG_SERCOM0_SPI_LENGTH     (0x40003022) /**< \brief (SERCOM0) SPI Length */
-#define REG_SERCOM0_SPI_ADDR       (0x40003024) /**< \brief (SERCOM0) SPI Address */
-#define REG_SERCOM0_SPI_DATA       (0x40003028) /**< \brief (SERCOM0) SPI Data */
-#define REG_SERCOM0_SPI_DBGCTRL    (0x40003030) /**< \brief (SERCOM0) SPI Debug Control */
-#define REG_SERCOM0_USART_CTRLA    (0x40003000) /**< \brief (SERCOM0) USART Control A */
-#define REG_SERCOM0_USART_CTRLB    (0x40003004) /**< \brief (SERCOM0) USART Control B */
-#define REG_SERCOM0_USART_CTRLC    (0x40003008) /**< \brief (SERCOM0) USART Control C */
-#define REG_SERCOM0_USART_BAUD     (0x4000300C) /**< \brief (SERCOM0) USART Baud Rate */
-#define REG_SERCOM0_USART_RXPL     (0x4000300E) /**< \brief (SERCOM0) USART Receive Pulse Length */
-#define REG_SERCOM0_USART_INTENCLR (0x40003014) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
-#define REG_SERCOM0_USART_INTENSET (0x40003016) /**< \brief (SERCOM0) USART Interrupt Enable Set */
-#define REG_SERCOM0_USART_INTFLAG  (0x40003018) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM0_USART_STATUS   (0x4000301A) /**< \brief (SERCOM0) USART Status */
-#define REG_SERCOM0_USART_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) USART Synchronization Busy */
-#define REG_SERCOM0_USART_RXERRCNT (0x40003020) /**< \brief (SERCOM0) USART Receive Error Count */
-#define REG_SERCOM0_USART_LENGTH   (0x40003022) /**< \brief (SERCOM0) USART Length */
-#define REG_SERCOM0_USART_DATA     (0x40003028) /**< \brief (SERCOM0) USART Data */
-#define REG_SERCOM0_USART_DBGCTRL  (0x40003030) /**< \brief (SERCOM0) USART Debug Control */
-#else
-#define REG_SERCOM0_I2CM_CTRLA     (*(RwReg  *)0x40003000UL) /**< \brief (SERCOM0) I2CM Control A */
-#define REG_SERCOM0_I2CM_CTRLB     (*(RwReg  *)0x40003004UL) /**< \brief (SERCOM0) I2CM Control B */
-#define REG_SERCOM0_I2CM_CTRLC     (*(RwReg  *)0x40003008UL) /**< \brief (SERCOM0) I2CM Control C */
-#define REG_SERCOM0_I2CM_BAUD      (*(RwReg  *)0x4000300CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
-#define REG_SERCOM0_I2CM_INTENCLR  (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
-#define REG_SERCOM0_I2CM_INTENSET  (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
-#define REG_SERCOM0_I2CM_INTFLAG   (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM0_I2CM_STATUS    (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CM Status */
-#define REG_SERCOM0_I2CM_SYNCBUSY  (*(RoReg  *)0x4000301CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */
-#define REG_SERCOM0_I2CM_ADDR      (*(RwReg  *)0x40003024UL) /**< \brief (SERCOM0) I2CM Address */
-#define REG_SERCOM0_I2CM_DATA      (*(RwReg  *)0x40003028UL) /**< \brief (SERCOM0) I2CM Data */
-#define REG_SERCOM0_I2CM_DBGCTRL   (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) I2CM Debug Control */
-#define REG_SERCOM0_I2CS_CTRLA     (*(RwReg  *)0x40003000UL) /**< \brief (SERCOM0) I2CS Control A */
-#define REG_SERCOM0_I2CS_CTRLB     (*(RwReg  *)0x40003004UL) /**< \brief (SERCOM0) I2CS Control B */
-#define REG_SERCOM0_I2CS_CTRLC     (*(RwReg  *)0x40003008UL) /**< \brief (SERCOM0) I2CS Control C */
-#define REG_SERCOM0_I2CS_INTENCLR  (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
-#define REG_SERCOM0_I2CS_INTENSET  (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
-#define REG_SERCOM0_I2CS_INTFLAG   (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM0_I2CS_STATUS    (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CS Status */
-#define REG_SERCOM0_I2CS_SYNCBUSY  (*(RoReg  *)0x4000301CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */
-#define REG_SERCOM0_I2CS_LENGTH    (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) I2CS Length */
-#define REG_SERCOM0_I2CS_ADDR      (*(RwReg  *)0x40003024UL) /**< \brief (SERCOM0) I2CS Address */
-#define REG_SERCOM0_I2CS_DATA      (*(RwReg  *)0x40003028UL) /**< \brief (SERCOM0) I2CS Data */
-#define REG_SERCOM0_SPI_CTRLA      (*(RwReg  *)0x40003000UL) /**< \brief (SERCOM0) SPI Control A */
-#define REG_SERCOM0_SPI_CTRLB      (*(RwReg  *)0x40003004UL) /**< \brief (SERCOM0) SPI Control B */
-#define REG_SERCOM0_SPI_CTRLC      (*(RwReg  *)0x40003008UL) /**< \brief (SERCOM0) SPI Control C */
-#define REG_SERCOM0_SPI_BAUD       (*(RwReg8 *)0x4000300CUL) /**< \brief (SERCOM0) SPI Baud Rate */
-#define REG_SERCOM0_SPI_INTENCLR   (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
-#define REG_SERCOM0_SPI_INTENSET   (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
-#define REG_SERCOM0_SPI_INTFLAG    (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM0_SPI_STATUS     (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) SPI Status */
-#define REG_SERCOM0_SPI_SYNCBUSY   (*(RoReg  *)0x4000301CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */
-#define REG_SERCOM0_SPI_LENGTH     (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) SPI Length */
-#define REG_SERCOM0_SPI_ADDR       (*(RwReg  *)0x40003024UL) /**< \brief (SERCOM0) SPI Address */
-#define REG_SERCOM0_SPI_DATA       (*(RwReg  *)0x40003028UL) /**< \brief (SERCOM0) SPI Data */
-#define REG_SERCOM0_SPI_DBGCTRL    (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) SPI Debug Control */
-#define REG_SERCOM0_USART_CTRLA    (*(RwReg  *)0x40003000UL) /**< \brief (SERCOM0) USART Control A */
-#define REG_SERCOM0_USART_CTRLB    (*(RwReg  *)0x40003004UL) /**< \brief (SERCOM0) USART Control B */
-#define REG_SERCOM0_USART_CTRLC    (*(RwReg  *)0x40003008UL) /**< \brief (SERCOM0) USART Control C */
-#define REG_SERCOM0_USART_BAUD     (*(RwReg16*)0x4000300CUL) /**< \brief (SERCOM0) USART Baud Rate */
-#define REG_SERCOM0_USART_RXPL     (*(RwReg8 *)0x4000300EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
-#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
-#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
-#define REG_SERCOM0_USART_INTFLAG  (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM0_USART_STATUS   (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) USART Status */
-#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg  *)0x4000301CUL) /**< \brief (SERCOM0) USART Synchronization Busy */
-#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x40003020UL) /**< \brief (SERCOM0) USART Receive Error Count */
-#define REG_SERCOM0_USART_LENGTH   (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) USART Length */
-#define REG_SERCOM0_USART_DATA     (*(RwReg  *)0x40003028UL) /**< \brief (SERCOM0) USART Data */
-#define REG_SERCOM0_USART_DBGCTRL  (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM0 peripheral ========== */
-#define SERCOM0_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
-#define SERCOM0_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
-#define SERCOM0_DMA                 1        // DMA support implemented?
-#define SERCOM0_DMAC_ID_RX          4        // Index of DMA RX trigger
-#define SERCOM0_DMAC_ID_TX          5        // Index of DMA TX trigger
-#define SERCOM0_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
-#define SERCOM0_GCLK_ID_CORE        7       
-#define SERCOM0_GCLK_ID_SLOW        3       
-#define SERCOM0_INT_MSB             6       
-#define SERCOM0_PMSB                3       
-#define SERCOM0_RETENTION_SUPPORT   0        // Retention supported?
-#define SERCOM0_SE_CNT              1        // SE counter included?
-#define SERCOM0_SPI                 1        // SPI mode implemented?
-#define SERCOM0_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
-#define SERCOM0_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
-#define SERCOM0_SPI_OZMO            0        // OZMO features implemented?
-#define SERCOM0_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
-#define SERCOM0_TTBIT_EXTENSION     1        // 32-bit extension implemented?
-#define SERCOM0_TWIM                1        // TWI Master mode implemented?
-#define SERCOM0_TWIS                1        // TWI Slave mode implemented?
-#define SERCOM0_TWIS_AUTO_ACK       1        // TWI slave automatic acknowledge implemented?
-#define SERCOM0_TWIS_GROUP_CMD      1        // TWI slave group command implemented?
-#define SERCOM0_TWIS_SDASETUP_CNT_SIZE 8        // TWIS sda setup count size
-#define SERCOM0_TWIS_SDASETUP_SIZE  4        // TWIS sda setup size
-#define SERCOM0_TWIS_SUDAT          1        // TWI slave SDA setup implemented?
-#define SERCOM0_TWI_FASTMP          1        // TWI fast mode plus implemented?
-#define SERCOM0_TWI_HSMODE          1        // USART mode implemented?
-#define SERCOM0_TWI_SCLSM_MODE      1        // TWI SCL clock stretch mode implemented?
-#define SERCOM0_TWI_SMB_TIMEOUTS    1        // TWI SMBus timeouts implemented?
-#define SERCOM0_TWI_TENBIT_ADR      1        // TWI ten bit enabled?
-#define SERCOM0_USART               1        // USART mode implemented?
-#define SERCOM0_USART_AUTOBAUD      1        // USART autobaud implemented?
-#define SERCOM0_USART_COLDET        1        // USART collision detection implemented?
-#define SERCOM0_USART_FLOW_CTRL     1        // USART flow control implemented?
-#define SERCOM0_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
-#define SERCOM0_USART_IRDA          1        // USART IrDA implemented?
-#define SERCOM0_USART_ISO7816       1        // USART ISO7816 mode implemented?
-#define SERCOM0_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
-#define SERCOM0_USART_RS485         1        // USART RS485 mode implemented?
-#define SERCOM0_USART_SAMPA_EXT     1        // USART sample adjust implemented?
-#define SERCOM0_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
-
-#endif /* _SAMD51_SERCOM0_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom1.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom1.h
deleted file mode 100644
index ebf29a0fa6..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom1.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM1
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SERCOM1_INSTANCE_
-#define _SAMD51_SERCOM1_INSTANCE_
-
-/* ========== Register definition for SERCOM1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM1_I2CM_CTRLA     (0x40003400) /**< \brief (SERCOM1) I2CM Control A */
-#define REG_SERCOM1_I2CM_CTRLB     (0x40003404) /**< \brief (SERCOM1) I2CM Control B */
-#define REG_SERCOM1_I2CM_CTRLC     (0x40003408) /**< \brief (SERCOM1) I2CM Control C */
-#define REG_SERCOM1_I2CM_BAUD      (0x4000340C) /**< \brief (SERCOM1) I2CM Baud Rate */
-#define REG_SERCOM1_I2CM_INTENCLR  (0x40003414) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
-#define REG_SERCOM1_I2CM_INTENSET  (0x40003416) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
-#define REG_SERCOM1_I2CM_INTFLAG   (0x40003418) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM1_I2CM_STATUS    (0x4000341A) /**< \brief (SERCOM1) I2CM Status */
-#define REG_SERCOM1_I2CM_SYNCBUSY  (0x4000341C) /**< \brief (SERCOM1) I2CM Synchronization Busy */
-#define REG_SERCOM1_I2CM_ADDR      (0x40003424) /**< \brief (SERCOM1) I2CM Address */
-#define REG_SERCOM1_I2CM_DATA      (0x40003428) /**< \brief (SERCOM1) I2CM Data */
-#define REG_SERCOM1_I2CM_DBGCTRL   (0x40003430) /**< \brief (SERCOM1) I2CM Debug Control */
-#define REG_SERCOM1_I2CS_CTRLA     (0x40003400) /**< \brief (SERCOM1) I2CS Control A */
-#define REG_SERCOM1_I2CS_CTRLB     (0x40003404) /**< \brief (SERCOM1) I2CS Control B */
-#define REG_SERCOM1_I2CS_CTRLC     (0x40003408) /**< \brief (SERCOM1) I2CS Control C */
-#define REG_SERCOM1_I2CS_INTENCLR  (0x40003414) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
-#define REG_SERCOM1_I2CS_INTENSET  (0x40003416) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
-#define REG_SERCOM1_I2CS_INTFLAG   (0x40003418) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM1_I2CS_STATUS    (0x4000341A) /**< \brief (SERCOM1) I2CS Status */
-#define REG_SERCOM1_I2CS_SYNCBUSY  (0x4000341C) /**< \brief (SERCOM1) I2CS Synchronization Busy */
-#define REG_SERCOM1_I2CS_LENGTH    (0x40003422) /**< \brief (SERCOM1) I2CS Length */
-#define REG_SERCOM1_I2CS_ADDR      (0x40003424) /**< \brief (SERCOM1) I2CS Address */
-#define REG_SERCOM1_I2CS_DATA      (0x40003428) /**< \brief (SERCOM1) I2CS Data */
-#define REG_SERCOM1_SPI_CTRLA      (0x40003400) /**< \brief (SERCOM1) SPI Control A */
-#define REG_SERCOM1_SPI_CTRLB      (0x40003404) /**< \brief (SERCOM1) SPI Control B */
-#define REG_SERCOM1_SPI_CTRLC      (0x40003408) /**< \brief (SERCOM1) SPI Control C */
-#define REG_SERCOM1_SPI_BAUD       (0x4000340C) /**< \brief (SERCOM1) SPI Baud Rate */
-#define REG_SERCOM1_SPI_INTENCLR   (0x40003414) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
-#define REG_SERCOM1_SPI_INTENSET   (0x40003416) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
-#define REG_SERCOM1_SPI_INTFLAG    (0x40003418) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM1_SPI_STATUS     (0x4000341A) /**< \brief (SERCOM1) SPI Status */
-#define REG_SERCOM1_SPI_SYNCBUSY   (0x4000341C) /**< \brief (SERCOM1) SPI Synchronization Busy */
-#define REG_SERCOM1_SPI_LENGTH     (0x40003422) /**< \brief (SERCOM1) SPI Length */
-#define REG_SERCOM1_SPI_ADDR       (0x40003424) /**< \brief (SERCOM1) SPI Address */
-#define REG_SERCOM1_SPI_DATA       (0x40003428) /**< \brief (SERCOM1) SPI Data */
-#define REG_SERCOM1_SPI_DBGCTRL    (0x40003430) /**< \brief (SERCOM1) SPI Debug Control */
-#define REG_SERCOM1_USART_CTRLA    (0x40003400) /**< \brief (SERCOM1) USART Control A */
-#define REG_SERCOM1_USART_CTRLB    (0x40003404) /**< \brief (SERCOM1) USART Control B */
-#define REG_SERCOM1_USART_CTRLC    (0x40003408) /**< \brief (SERCOM1) USART Control C */
-#define REG_SERCOM1_USART_BAUD     (0x4000340C) /**< \brief (SERCOM1) USART Baud Rate */
-#define REG_SERCOM1_USART_RXPL     (0x4000340E) /**< \brief (SERCOM1) USART Receive Pulse Length */
-#define REG_SERCOM1_USART_INTENCLR (0x40003414) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
-#define REG_SERCOM1_USART_INTENSET (0x40003416) /**< \brief (SERCOM1) USART Interrupt Enable Set */
-#define REG_SERCOM1_USART_INTFLAG  (0x40003418) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM1_USART_STATUS   (0x4000341A) /**< \brief (SERCOM1) USART Status */
-#define REG_SERCOM1_USART_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) USART Synchronization Busy */
-#define REG_SERCOM1_USART_RXERRCNT (0x40003420) /**< \brief (SERCOM1) USART Receive Error Count */
-#define REG_SERCOM1_USART_LENGTH   (0x40003422) /**< \brief (SERCOM1) USART Length */
-#define REG_SERCOM1_USART_DATA     (0x40003428) /**< \brief (SERCOM1) USART Data */
-#define REG_SERCOM1_USART_DBGCTRL  (0x40003430) /**< \brief (SERCOM1) USART Debug Control */
-#else
-#define REG_SERCOM1_I2CM_CTRLA     (*(RwReg  *)0x40003400UL) /**< \brief (SERCOM1) I2CM Control A */
-#define REG_SERCOM1_I2CM_CTRLB     (*(RwReg  *)0x40003404UL) /**< \brief (SERCOM1) I2CM Control B */
-#define REG_SERCOM1_I2CM_CTRLC     (*(RwReg  *)0x40003408UL) /**< \brief (SERCOM1) I2CM Control C */
-#define REG_SERCOM1_I2CM_BAUD      (*(RwReg  *)0x4000340CUL) /**< \brief (SERCOM1) I2CM Baud Rate */
-#define REG_SERCOM1_I2CM_INTENCLR  (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
-#define REG_SERCOM1_I2CM_INTENSET  (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
-#define REG_SERCOM1_I2CM_INTFLAG   (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM1_I2CM_STATUS    (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CM Status */
-#define REG_SERCOM1_I2CM_SYNCBUSY  (*(RoReg  *)0x4000341CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */
-#define REG_SERCOM1_I2CM_ADDR      (*(RwReg  *)0x40003424UL) /**< \brief (SERCOM1) I2CM Address */
-#define REG_SERCOM1_I2CM_DATA      (*(RwReg  *)0x40003428UL) /**< \brief (SERCOM1) I2CM Data */
-#define REG_SERCOM1_I2CM_DBGCTRL   (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) I2CM Debug Control */
-#define REG_SERCOM1_I2CS_CTRLA     (*(RwReg  *)0x40003400UL) /**< \brief (SERCOM1) I2CS Control A */
-#define REG_SERCOM1_I2CS_CTRLB     (*(RwReg  *)0x40003404UL) /**< \brief (SERCOM1) I2CS Control B */
-#define REG_SERCOM1_I2CS_CTRLC     (*(RwReg  *)0x40003408UL) /**< \brief (SERCOM1) I2CS Control C */
-#define REG_SERCOM1_I2CS_INTENCLR  (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
-#define REG_SERCOM1_I2CS_INTENSET  (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
-#define REG_SERCOM1_I2CS_INTFLAG   (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM1_I2CS_STATUS    (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CS Status */
-#define REG_SERCOM1_I2CS_SYNCBUSY  (*(RoReg  *)0x4000341CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */
-#define REG_SERCOM1_I2CS_LENGTH    (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) I2CS Length */
-#define REG_SERCOM1_I2CS_ADDR      (*(RwReg  *)0x40003424UL) /**< \brief (SERCOM1) I2CS Address */
-#define REG_SERCOM1_I2CS_DATA      (*(RwReg  *)0x40003428UL) /**< \brief (SERCOM1) I2CS Data */
-#define REG_SERCOM1_SPI_CTRLA      (*(RwReg  *)0x40003400UL) /**< \brief (SERCOM1) SPI Control A */
-#define REG_SERCOM1_SPI_CTRLB      (*(RwReg  *)0x40003404UL) /**< \brief (SERCOM1) SPI Control B */
-#define REG_SERCOM1_SPI_CTRLC      (*(RwReg  *)0x40003408UL) /**< \brief (SERCOM1) SPI Control C */
-#define REG_SERCOM1_SPI_BAUD       (*(RwReg8 *)0x4000340CUL) /**< \brief (SERCOM1) SPI Baud Rate */
-#define REG_SERCOM1_SPI_INTENCLR   (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
-#define REG_SERCOM1_SPI_INTENSET   (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
-#define REG_SERCOM1_SPI_INTFLAG    (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM1_SPI_STATUS     (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) SPI Status */
-#define REG_SERCOM1_SPI_SYNCBUSY   (*(RoReg  *)0x4000341CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */
-#define REG_SERCOM1_SPI_LENGTH     (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) SPI Length */
-#define REG_SERCOM1_SPI_ADDR       (*(RwReg  *)0x40003424UL) /**< \brief (SERCOM1) SPI Address */
-#define REG_SERCOM1_SPI_DATA       (*(RwReg  *)0x40003428UL) /**< \brief (SERCOM1) SPI Data */
-#define REG_SERCOM1_SPI_DBGCTRL    (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) SPI Debug Control */
-#define REG_SERCOM1_USART_CTRLA    (*(RwReg  *)0x40003400UL) /**< \brief (SERCOM1) USART Control A */
-#define REG_SERCOM1_USART_CTRLB    (*(RwReg  *)0x40003404UL) /**< \brief (SERCOM1) USART Control B */
-#define REG_SERCOM1_USART_CTRLC    (*(RwReg  *)0x40003408UL) /**< \brief (SERCOM1) USART Control C */
-#define REG_SERCOM1_USART_BAUD     (*(RwReg16*)0x4000340CUL) /**< \brief (SERCOM1) USART Baud Rate */
-#define REG_SERCOM1_USART_RXPL     (*(RwReg8 *)0x4000340EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */
-#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
-#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */
-#define REG_SERCOM1_USART_INTFLAG  (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM1_USART_STATUS   (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) USART Status */
-#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg  *)0x4000341CUL) /**< \brief (SERCOM1) USART Synchronization Busy */
-#define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x40003420UL) /**< \brief (SERCOM1) USART Receive Error Count */
-#define REG_SERCOM1_USART_LENGTH   (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) USART Length */
-#define REG_SERCOM1_USART_DATA     (*(RwReg  *)0x40003428UL) /**< \brief (SERCOM1) USART Data */
-#define REG_SERCOM1_USART_DBGCTRL  (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM1 peripheral ========== */
-#define SERCOM1_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
-#define SERCOM1_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
-#define SERCOM1_DMA                 1        // DMA support implemented?
-#define SERCOM1_DMAC_ID_RX          6        // Index of DMA RX trigger
-#define SERCOM1_DMAC_ID_TX          7        // Index of DMA TX trigger
-#define SERCOM1_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
-#define SERCOM1_GCLK_ID_CORE        8       
-#define SERCOM1_GCLK_ID_SLOW        3       
-#define SERCOM1_INT_MSB             6       
-#define SERCOM1_PMSB                3       
-#define SERCOM1_RETENTION_SUPPORT   0        // Retention supported?
-#define SERCOM1_SE_CNT              1        // SE counter included?
-#define SERCOM1_SPI                 1        // SPI mode implemented?
-#define SERCOM1_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
-#define SERCOM1_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
-#define SERCOM1_SPI_OZMO            0        // OZMO features implemented?
-#define SERCOM1_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
-#define SERCOM1_TTBIT_EXTENSION     1        // 32-bit extension implemented?
-#define SERCOM1_TWIM                1        // TWI Master mode implemented?
-#define SERCOM1_TWIS                1        // TWI Slave mode implemented?
-#define SERCOM1_TWIS_AUTO_ACK       1        // TWI slave automatic acknowledge implemented?
-#define SERCOM1_TWIS_GROUP_CMD      1        // TWI slave group command implemented?
-#define SERCOM1_TWIS_SDASETUP_CNT_SIZE 8        // TWIS sda setup count size
-#define SERCOM1_TWIS_SDASETUP_SIZE  4        // TWIS sda setup size
-#define SERCOM1_TWIS_SUDAT          1        // TWI slave SDA setup implemented?
-#define SERCOM1_TWI_FASTMP          1        // TWI fast mode plus implemented?
-#define SERCOM1_TWI_HSMODE          1        // USART mode implemented?
-#define SERCOM1_TWI_SCLSM_MODE      1        // TWI SCL clock stretch mode implemented?
-#define SERCOM1_TWI_SMB_TIMEOUTS    1        // TWI SMBus timeouts implemented?
-#define SERCOM1_TWI_TENBIT_ADR      1        // TWI ten bit enabled?
-#define SERCOM1_USART               1        // USART mode implemented?
-#define SERCOM1_USART_AUTOBAUD      1        // USART autobaud implemented?
-#define SERCOM1_USART_COLDET        1        // USART collision detection implemented?
-#define SERCOM1_USART_FLOW_CTRL     1        // USART flow control implemented?
-#define SERCOM1_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
-#define SERCOM1_USART_IRDA          1        // USART IrDA implemented?
-#define SERCOM1_USART_ISO7816       1        // USART ISO7816 mode implemented?
-#define SERCOM1_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
-#define SERCOM1_USART_RS485         1        // USART RS485 mode implemented?
-#define SERCOM1_USART_SAMPA_EXT     1        // USART sample adjust implemented?
-#define SERCOM1_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
-
-#endif /* _SAMD51_SERCOM1_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom2.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom2.h
deleted file mode 100644
index 674e63b700..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom2.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM2
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SERCOM2_INSTANCE_
-#define _SAMD51_SERCOM2_INSTANCE_
-
-/* ========== Register definition for SERCOM2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM2_I2CM_CTRLA     (0x41012000) /**< \brief (SERCOM2) I2CM Control A */
-#define REG_SERCOM2_I2CM_CTRLB     (0x41012004) /**< \brief (SERCOM2) I2CM Control B */
-#define REG_SERCOM2_I2CM_CTRLC     (0x41012008) /**< \brief (SERCOM2) I2CM Control C */
-#define REG_SERCOM2_I2CM_BAUD      (0x4101200C) /**< \brief (SERCOM2) I2CM Baud Rate */
-#define REG_SERCOM2_I2CM_INTENCLR  (0x41012014) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
-#define REG_SERCOM2_I2CM_INTENSET  (0x41012016) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
-#define REG_SERCOM2_I2CM_INTFLAG   (0x41012018) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CM_STATUS    (0x4101201A) /**< \brief (SERCOM2) I2CM Status */
-#define REG_SERCOM2_I2CM_SYNCBUSY  (0x4101201C) /**< \brief (SERCOM2) I2CM Synchronization Busy */
-#define REG_SERCOM2_I2CM_ADDR      (0x41012024) /**< \brief (SERCOM2) I2CM Address */
-#define REG_SERCOM2_I2CM_DATA      (0x41012028) /**< \brief (SERCOM2) I2CM Data */
-#define REG_SERCOM2_I2CM_DBGCTRL   (0x41012030) /**< \brief (SERCOM2) I2CM Debug Control */
-#define REG_SERCOM2_I2CS_CTRLA     (0x41012000) /**< \brief (SERCOM2) I2CS Control A */
-#define REG_SERCOM2_I2CS_CTRLB     (0x41012004) /**< \brief (SERCOM2) I2CS Control B */
-#define REG_SERCOM2_I2CS_CTRLC     (0x41012008) /**< \brief (SERCOM2) I2CS Control C */
-#define REG_SERCOM2_I2CS_INTENCLR  (0x41012014) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
-#define REG_SERCOM2_I2CS_INTENSET  (0x41012016) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
-#define REG_SERCOM2_I2CS_INTFLAG   (0x41012018) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CS_STATUS    (0x4101201A) /**< \brief (SERCOM2) I2CS Status */
-#define REG_SERCOM2_I2CS_SYNCBUSY  (0x4101201C) /**< \brief (SERCOM2) I2CS Synchronization Busy */
-#define REG_SERCOM2_I2CS_LENGTH    (0x41012022) /**< \brief (SERCOM2) I2CS Length */
-#define REG_SERCOM2_I2CS_ADDR      (0x41012024) /**< \brief (SERCOM2) I2CS Address */
-#define REG_SERCOM2_I2CS_DATA      (0x41012028) /**< \brief (SERCOM2) I2CS Data */
-#define REG_SERCOM2_SPI_CTRLA      (0x41012000) /**< \brief (SERCOM2) SPI Control A */
-#define REG_SERCOM2_SPI_CTRLB      (0x41012004) /**< \brief (SERCOM2) SPI Control B */
-#define REG_SERCOM2_SPI_CTRLC      (0x41012008) /**< \brief (SERCOM2) SPI Control C */
-#define REG_SERCOM2_SPI_BAUD       (0x4101200C) /**< \brief (SERCOM2) SPI Baud Rate */
-#define REG_SERCOM2_SPI_INTENCLR   (0x41012014) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
-#define REG_SERCOM2_SPI_INTENSET   (0x41012016) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
-#define REG_SERCOM2_SPI_INTFLAG    (0x41012018) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM2_SPI_STATUS     (0x4101201A) /**< \brief (SERCOM2) SPI Status */
-#define REG_SERCOM2_SPI_SYNCBUSY   (0x4101201C) /**< \brief (SERCOM2) SPI Synchronization Busy */
-#define REG_SERCOM2_SPI_LENGTH     (0x41012022) /**< \brief (SERCOM2) SPI Length */
-#define REG_SERCOM2_SPI_ADDR       (0x41012024) /**< \brief (SERCOM2) SPI Address */
-#define REG_SERCOM2_SPI_DATA       (0x41012028) /**< \brief (SERCOM2) SPI Data */
-#define REG_SERCOM2_SPI_DBGCTRL    (0x41012030) /**< \brief (SERCOM2) SPI Debug Control */
-#define REG_SERCOM2_USART_CTRLA    (0x41012000) /**< \brief (SERCOM2) USART Control A */
-#define REG_SERCOM2_USART_CTRLB    (0x41012004) /**< \brief (SERCOM2) USART Control B */
-#define REG_SERCOM2_USART_CTRLC    (0x41012008) /**< \brief (SERCOM2) USART Control C */
-#define REG_SERCOM2_USART_BAUD     (0x4101200C) /**< \brief (SERCOM2) USART Baud Rate */
-#define REG_SERCOM2_USART_RXPL     (0x4101200E) /**< \brief (SERCOM2) USART Receive Pulse Length */
-#define REG_SERCOM2_USART_INTENCLR (0x41012014) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
-#define REG_SERCOM2_USART_INTENSET (0x41012016) /**< \brief (SERCOM2) USART Interrupt Enable Set */
-#define REG_SERCOM2_USART_INTFLAG  (0x41012018) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM2_USART_STATUS   (0x4101201A) /**< \brief (SERCOM2) USART Status */
-#define REG_SERCOM2_USART_SYNCBUSY (0x4101201C) /**< \brief (SERCOM2) USART Synchronization Busy */
-#define REG_SERCOM2_USART_RXERRCNT (0x41012020) /**< \brief (SERCOM2) USART Receive Error Count */
-#define REG_SERCOM2_USART_LENGTH   (0x41012022) /**< \brief (SERCOM2) USART Length */
-#define REG_SERCOM2_USART_DATA     (0x41012028) /**< \brief (SERCOM2) USART Data */
-#define REG_SERCOM2_USART_DBGCTRL  (0x41012030) /**< \brief (SERCOM2) USART Debug Control */
-#else
-#define REG_SERCOM2_I2CM_CTRLA     (*(RwReg  *)0x41012000UL) /**< \brief (SERCOM2) I2CM Control A */
-#define REG_SERCOM2_I2CM_CTRLB     (*(RwReg  *)0x41012004UL) /**< \brief (SERCOM2) I2CM Control B */
-#define REG_SERCOM2_I2CM_CTRLC     (*(RwReg  *)0x41012008UL) /**< \brief (SERCOM2) I2CM Control C */
-#define REG_SERCOM2_I2CM_BAUD      (*(RwReg  *)0x4101200CUL) /**< \brief (SERCOM2) I2CM Baud Rate */
-#define REG_SERCOM2_I2CM_INTENCLR  (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
-#define REG_SERCOM2_I2CM_INTENSET  (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
-#define REG_SERCOM2_I2CM_INTFLAG   (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CM_STATUS    (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) I2CM Status */
-#define REG_SERCOM2_I2CM_SYNCBUSY  (*(RoReg  *)0x4101201CUL) /**< \brief (SERCOM2) I2CM Synchronization Busy */
-#define REG_SERCOM2_I2CM_ADDR      (*(RwReg  *)0x41012024UL) /**< \brief (SERCOM2) I2CM Address */
-#define REG_SERCOM2_I2CM_DATA      (*(RwReg  *)0x41012028UL) /**< \brief (SERCOM2) I2CM Data */
-#define REG_SERCOM2_I2CM_DBGCTRL   (*(RwReg8 *)0x41012030UL) /**< \brief (SERCOM2) I2CM Debug Control */
-#define REG_SERCOM2_I2CS_CTRLA     (*(RwReg  *)0x41012000UL) /**< \brief (SERCOM2) I2CS Control A */
-#define REG_SERCOM2_I2CS_CTRLB     (*(RwReg  *)0x41012004UL) /**< \brief (SERCOM2) I2CS Control B */
-#define REG_SERCOM2_I2CS_CTRLC     (*(RwReg  *)0x41012008UL) /**< \brief (SERCOM2) I2CS Control C */
-#define REG_SERCOM2_I2CS_INTENCLR  (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
-#define REG_SERCOM2_I2CS_INTENSET  (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
-#define REG_SERCOM2_I2CS_INTFLAG   (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM2_I2CS_STATUS    (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) I2CS Status */
-#define REG_SERCOM2_I2CS_SYNCBUSY  (*(RoReg  *)0x4101201CUL) /**< \brief (SERCOM2) I2CS Synchronization Busy */
-#define REG_SERCOM2_I2CS_LENGTH    (*(RwReg16*)0x41012022UL) /**< \brief (SERCOM2) I2CS Length */
-#define REG_SERCOM2_I2CS_ADDR      (*(RwReg  *)0x41012024UL) /**< \brief (SERCOM2) I2CS Address */
-#define REG_SERCOM2_I2CS_DATA      (*(RwReg  *)0x41012028UL) /**< \brief (SERCOM2) I2CS Data */
-#define REG_SERCOM2_SPI_CTRLA      (*(RwReg  *)0x41012000UL) /**< \brief (SERCOM2) SPI Control A */
-#define REG_SERCOM2_SPI_CTRLB      (*(RwReg  *)0x41012004UL) /**< \brief (SERCOM2) SPI Control B */
-#define REG_SERCOM2_SPI_CTRLC      (*(RwReg  *)0x41012008UL) /**< \brief (SERCOM2) SPI Control C */
-#define REG_SERCOM2_SPI_BAUD       (*(RwReg8 *)0x4101200CUL) /**< \brief (SERCOM2) SPI Baud Rate */
-#define REG_SERCOM2_SPI_INTENCLR   (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
-#define REG_SERCOM2_SPI_INTENSET   (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
-#define REG_SERCOM2_SPI_INTFLAG    (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM2_SPI_STATUS     (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) SPI Status */
-#define REG_SERCOM2_SPI_SYNCBUSY   (*(RoReg  *)0x4101201CUL) /**< \brief (SERCOM2) SPI Synchronization Busy */
-#define REG_SERCOM2_SPI_LENGTH     (*(RwReg16*)0x41012022UL) /**< \brief (SERCOM2) SPI Length */
-#define REG_SERCOM2_SPI_ADDR       (*(RwReg  *)0x41012024UL) /**< \brief (SERCOM2) SPI Address */
-#define REG_SERCOM2_SPI_DATA       (*(RwReg  *)0x41012028UL) /**< \brief (SERCOM2) SPI Data */
-#define REG_SERCOM2_SPI_DBGCTRL    (*(RwReg8 *)0x41012030UL) /**< \brief (SERCOM2) SPI Debug Control */
-#define REG_SERCOM2_USART_CTRLA    (*(RwReg  *)0x41012000UL) /**< \brief (SERCOM2) USART Control A */
-#define REG_SERCOM2_USART_CTRLB    (*(RwReg  *)0x41012004UL) /**< \brief (SERCOM2) USART Control B */
-#define REG_SERCOM2_USART_CTRLC    (*(RwReg  *)0x41012008UL) /**< \brief (SERCOM2) USART Control C */
-#define REG_SERCOM2_USART_BAUD     (*(RwReg16*)0x4101200CUL) /**< \brief (SERCOM2) USART Baud Rate */
-#define REG_SERCOM2_USART_RXPL     (*(RwReg8 *)0x4101200EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */
-#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x41012014UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
-#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x41012016UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */
-#define REG_SERCOM2_USART_INTFLAG  (*(RwReg8 *)0x41012018UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM2_USART_STATUS   (*(RwReg16*)0x4101201AUL) /**< \brief (SERCOM2) USART Status */
-#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg  *)0x4101201CUL) /**< \brief (SERCOM2) USART Synchronization Busy */
-#define REG_SERCOM2_USART_RXERRCNT (*(RoReg8 *)0x41012020UL) /**< \brief (SERCOM2) USART Receive Error Count */
-#define REG_SERCOM2_USART_LENGTH   (*(RwReg16*)0x41012022UL) /**< \brief (SERCOM2) USART Length */
-#define REG_SERCOM2_USART_DATA     (*(RwReg  *)0x41012028UL) /**< \brief (SERCOM2) USART Data */
-#define REG_SERCOM2_USART_DBGCTRL  (*(RwReg8 *)0x41012030UL) /**< \brief (SERCOM2) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM2 peripheral ========== */
-#define SERCOM2_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
-#define SERCOM2_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
-#define SERCOM2_DMA                 1        // DMA support implemented?
-#define SERCOM2_DMAC_ID_RX          8        // Index of DMA RX trigger
-#define SERCOM2_DMAC_ID_TX          9        // Index of DMA TX trigger
-#define SERCOM2_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
-#define SERCOM2_GCLK_ID_CORE        23      
-#define SERCOM2_GCLK_ID_SLOW        3       
-#define SERCOM2_INT_MSB             6       
-#define SERCOM2_PMSB                3       
-#define SERCOM2_RETENTION_SUPPORT   0        // Retention supported?
-#define SERCOM2_SE_CNT              1        // SE counter included?
-#define SERCOM2_SPI                 1        // SPI mode implemented?
-#define SERCOM2_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
-#define SERCOM2_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
-#define SERCOM2_SPI_OZMO            0        // OZMO features implemented?
-#define SERCOM2_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
-#define SERCOM2_TTBIT_EXTENSION     1        // 32-bit extension implemented?
-#define SERCOM2_TWIM                1        // TWI Master mode implemented?
-#define SERCOM2_TWIS                1        // TWI Slave mode implemented?
-#define SERCOM2_TWIS_AUTO_ACK       1        // TWI slave automatic acknowledge implemented?
-#define SERCOM2_TWIS_GROUP_CMD      1        // TWI slave group command implemented?
-#define SERCOM2_TWIS_SDASETUP_CNT_SIZE 8        // TWIS sda setup count size
-#define SERCOM2_TWIS_SDASETUP_SIZE  4        // TWIS sda setup size
-#define SERCOM2_TWIS_SUDAT          1        // TWI slave SDA setup implemented?
-#define SERCOM2_TWI_FASTMP          1        // TWI fast mode plus implemented?
-#define SERCOM2_TWI_HSMODE          1        // USART mode implemented?
-#define SERCOM2_TWI_SCLSM_MODE      1        // TWI SCL clock stretch mode implemented?
-#define SERCOM2_TWI_SMB_TIMEOUTS    1        // TWI SMBus timeouts implemented?
-#define SERCOM2_TWI_TENBIT_ADR      1        // TWI ten bit enabled?
-#define SERCOM2_USART               1        // USART mode implemented?
-#define SERCOM2_USART_AUTOBAUD      1        // USART autobaud implemented?
-#define SERCOM2_USART_COLDET        1        // USART collision detection implemented?
-#define SERCOM2_USART_FLOW_CTRL     1        // USART flow control implemented?
-#define SERCOM2_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
-#define SERCOM2_USART_IRDA          1        // USART IrDA implemented?
-#define SERCOM2_USART_ISO7816       1        // USART ISO7816 mode implemented?
-#define SERCOM2_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
-#define SERCOM2_USART_RS485         1        // USART RS485 mode implemented?
-#define SERCOM2_USART_SAMPA_EXT     1        // USART sample adjust implemented?
-#define SERCOM2_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
-
-#endif /* _SAMD51_SERCOM2_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom3.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom3.h
deleted file mode 100644
index 9edd4e9242..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom3.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM3
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SERCOM3_INSTANCE_
-#define _SAMD51_SERCOM3_INSTANCE_
-
-/* ========== Register definition for SERCOM3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM3_I2CM_CTRLA     (0x41014000) /**< \brief (SERCOM3) I2CM Control A */
-#define REG_SERCOM3_I2CM_CTRLB     (0x41014004) /**< \brief (SERCOM3) I2CM Control B */
-#define REG_SERCOM3_I2CM_CTRLC     (0x41014008) /**< \brief (SERCOM3) I2CM Control C */
-#define REG_SERCOM3_I2CM_BAUD      (0x4101400C) /**< \brief (SERCOM3) I2CM Baud Rate */
-#define REG_SERCOM3_I2CM_INTENCLR  (0x41014014) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
-#define REG_SERCOM3_I2CM_INTENSET  (0x41014016) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
-#define REG_SERCOM3_I2CM_INTFLAG   (0x41014018) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CM_STATUS    (0x4101401A) /**< \brief (SERCOM3) I2CM Status */
-#define REG_SERCOM3_I2CM_SYNCBUSY  (0x4101401C) /**< \brief (SERCOM3) I2CM Synchronization Busy */
-#define REG_SERCOM3_I2CM_ADDR      (0x41014024) /**< \brief (SERCOM3) I2CM Address */
-#define REG_SERCOM3_I2CM_DATA      (0x41014028) /**< \brief (SERCOM3) I2CM Data */
-#define REG_SERCOM3_I2CM_DBGCTRL   (0x41014030) /**< \brief (SERCOM3) I2CM Debug Control */
-#define REG_SERCOM3_I2CS_CTRLA     (0x41014000) /**< \brief (SERCOM3) I2CS Control A */
-#define REG_SERCOM3_I2CS_CTRLB     (0x41014004) /**< \brief (SERCOM3) I2CS Control B */
-#define REG_SERCOM3_I2CS_CTRLC     (0x41014008) /**< \brief (SERCOM3) I2CS Control C */
-#define REG_SERCOM3_I2CS_INTENCLR  (0x41014014) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
-#define REG_SERCOM3_I2CS_INTENSET  (0x41014016) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
-#define REG_SERCOM3_I2CS_INTFLAG   (0x41014018) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CS_STATUS    (0x4101401A) /**< \brief (SERCOM3) I2CS Status */
-#define REG_SERCOM3_I2CS_SYNCBUSY  (0x4101401C) /**< \brief (SERCOM3) I2CS Synchronization Busy */
-#define REG_SERCOM3_I2CS_LENGTH    (0x41014022) /**< \brief (SERCOM3) I2CS Length */
-#define REG_SERCOM3_I2CS_ADDR      (0x41014024) /**< \brief (SERCOM3) I2CS Address */
-#define REG_SERCOM3_I2CS_DATA      (0x41014028) /**< \brief (SERCOM3) I2CS Data */
-#define REG_SERCOM3_SPI_CTRLA      (0x41014000) /**< \brief (SERCOM3) SPI Control A */
-#define REG_SERCOM3_SPI_CTRLB      (0x41014004) /**< \brief (SERCOM3) SPI Control B */
-#define REG_SERCOM3_SPI_CTRLC      (0x41014008) /**< \brief (SERCOM3) SPI Control C */
-#define REG_SERCOM3_SPI_BAUD       (0x4101400C) /**< \brief (SERCOM3) SPI Baud Rate */
-#define REG_SERCOM3_SPI_INTENCLR   (0x41014014) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
-#define REG_SERCOM3_SPI_INTENSET   (0x41014016) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
-#define REG_SERCOM3_SPI_INTFLAG    (0x41014018) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM3_SPI_STATUS     (0x4101401A) /**< \brief (SERCOM3) SPI Status */
-#define REG_SERCOM3_SPI_SYNCBUSY   (0x4101401C) /**< \brief (SERCOM3) SPI Synchronization Busy */
-#define REG_SERCOM3_SPI_LENGTH     (0x41014022) /**< \brief (SERCOM3) SPI Length */
-#define REG_SERCOM3_SPI_ADDR       (0x41014024) /**< \brief (SERCOM3) SPI Address */
-#define REG_SERCOM3_SPI_DATA       (0x41014028) /**< \brief (SERCOM3) SPI Data */
-#define REG_SERCOM3_SPI_DBGCTRL    (0x41014030) /**< \brief (SERCOM3) SPI Debug Control */
-#define REG_SERCOM3_USART_CTRLA    (0x41014000) /**< \brief (SERCOM3) USART Control A */
-#define REG_SERCOM3_USART_CTRLB    (0x41014004) /**< \brief (SERCOM3) USART Control B */
-#define REG_SERCOM3_USART_CTRLC    (0x41014008) /**< \brief (SERCOM3) USART Control C */
-#define REG_SERCOM3_USART_BAUD     (0x4101400C) /**< \brief (SERCOM3) USART Baud Rate */
-#define REG_SERCOM3_USART_RXPL     (0x4101400E) /**< \brief (SERCOM3) USART Receive Pulse Length */
-#define REG_SERCOM3_USART_INTENCLR (0x41014014) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
-#define REG_SERCOM3_USART_INTENSET (0x41014016) /**< \brief (SERCOM3) USART Interrupt Enable Set */
-#define REG_SERCOM3_USART_INTFLAG  (0x41014018) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM3_USART_STATUS   (0x4101401A) /**< \brief (SERCOM3) USART Status */
-#define REG_SERCOM3_USART_SYNCBUSY (0x4101401C) /**< \brief (SERCOM3) USART Synchronization Busy */
-#define REG_SERCOM3_USART_RXERRCNT (0x41014020) /**< \brief (SERCOM3) USART Receive Error Count */
-#define REG_SERCOM3_USART_LENGTH   (0x41014022) /**< \brief (SERCOM3) USART Length */
-#define REG_SERCOM3_USART_DATA     (0x41014028) /**< \brief (SERCOM3) USART Data */
-#define REG_SERCOM3_USART_DBGCTRL  (0x41014030) /**< \brief (SERCOM3) USART Debug Control */
-#else
-#define REG_SERCOM3_I2CM_CTRLA     (*(RwReg  *)0x41014000UL) /**< \brief (SERCOM3) I2CM Control A */
-#define REG_SERCOM3_I2CM_CTRLB     (*(RwReg  *)0x41014004UL) /**< \brief (SERCOM3) I2CM Control B */
-#define REG_SERCOM3_I2CM_CTRLC     (*(RwReg  *)0x41014008UL) /**< \brief (SERCOM3) I2CM Control C */
-#define REG_SERCOM3_I2CM_BAUD      (*(RwReg  *)0x4101400CUL) /**< \brief (SERCOM3) I2CM Baud Rate */
-#define REG_SERCOM3_I2CM_INTENCLR  (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
-#define REG_SERCOM3_I2CM_INTENSET  (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
-#define REG_SERCOM3_I2CM_INTFLAG   (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CM_STATUS    (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) I2CM Status */
-#define REG_SERCOM3_I2CM_SYNCBUSY  (*(RoReg  *)0x4101401CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */
-#define REG_SERCOM3_I2CM_ADDR      (*(RwReg  *)0x41014024UL) /**< \brief (SERCOM3) I2CM Address */
-#define REG_SERCOM3_I2CM_DATA      (*(RwReg  *)0x41014028UL) /**< \brief (SERCOM3) I2CM Data */
-#define REG_SERCOM3_I2CM_DBGCTRL   (*(RwReg8 *)0x41014030UL) /**< \brief (SERCOM3) I2CM Debug Control */
-#define REG_SERCOM3_I2CS_CTRLA     (*(RwReg  *)0x41014000UL) /**< \brief (SERCOM3) I2CS Control A */
-#define REG_SERCOM3_I2CS_CTRLB     (*(RwReg  *)0x41014004UL) /**< \brief (SERCOM3) I2CS Control B */
-#define REG_SERCOM3_I2CS_CTRLC     (*(RwReg  *)0x41014008UL) /**< \brief (SERCOM3) I2CS Control C */
-#define REG_SERCOM3_I2CS_INTENCLR  (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
-#define REG_SERCOM3_I2CS_INTENSET  (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
-#define REG_SERCOM3_I2CS_INTFLAG   (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM3_I2CS_STATUS    (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) I2CS Status */
-#define REG_SERCOM3_I2CS_SYNCBUSY  (*(RoReg  *)0x4101401CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */
-#define REG_SERCOM3_I2CS_LENGTH    (*(RwReg16*)0x41014022UL) /**< \brief (SERCOM3) I2CS Length */
-#define REG_SERCOM3_I2CS_ADDR      (*(RwReg  *)0x41014024UL) /**< \brief (SERCOM3) I2CS Address */
-#define REG_SERCOM3_I2CS_DATA      (*(RwReg  *)0x41014028UL) /**< \brief (SERCOM3) I2CS Data */
-#define REG_SERCOM3_SPI_CTRLA      (*(RwReg  *)0x41014000UL) /**< \brief (SERCOM3) SPI Control A */
-#define REG_SERCOM3_SPI_CTRLB      (*(RwReg  *)0x41014004UL) /**< \brief (SERCOM3) SPI Control B */
-#define REG_SERCOM3_SPI_CTRLC      (*(RwReg  *)0x41014008UL) /**< \brief (SERCOM3) SPI Control C */
-#define REG_SERCOM3_SPI_BAUD       (*(RwReg8 *)0x4101400CUL) /**< \brief (SERCOM3) SPI Baud Rate */
-#define REG_SERCOM3_SPI_INTENCLR   (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
-#define REG_SERCOM3_SPI_INTENSET   (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
-#define REG_SERCOM3_SPI_INTFLAG    (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM3_SPI_STATUS     (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) SPI Status */
-#define REG_SERCOM3_SPI_SYNCBUSY   (*(RoReg  *)0x4101401CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */
-#define REG_SERCOM3_SPI_LENGTH     (*(RwReg16*)0x41014022UL) /**< \brief (SERCOM3) SPI Length */
-#define REG_SERCOM3_SPI_ADDR       (*(RwReg  *)0x41014024UL) /**< \brief (SERCOM3) SPI Address */
-#define REG_SERCOM3_SPI_DATA       (*(RwReg  *)0x41014028UL) /**< \brief (SERCOM3) SPI Data */
-#define REG_SERCOM3_SPI_DBGCTRL    (*(RwReg8 *)0x41014030UL) /**< \brief (SERCOM3) SPI Debug Control */
-#define REG_SERCOM3_USART_CTRLA    (*(RwReg  *)0x41014000UL) /**< \brief (SERCOM3) USART Control A */
-#define REG_SERCOM3_USART_CTRLB    (*(RwReg  *)0x41014004UL) /**< \brief (SERCOM3) USART Control B */
-#define REG_SERCOM3_USART_CTRLC    (*(RwReg  *)0x41014008UL) /**< \brief (SERCOM3) USART Control C */
-#define REG_SERCOM3_USART_BAUD     (*(RwReg16*)0x4101400CUL) /**< \brief (SERCOM3) USART Baud Rate */
-#define REG_SERCOM3_USART_RXPL     (*(RwReg8 *)0x4101400EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */
-#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x41014014UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
-#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x41014016UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */
-#define REG_SERCOM3_USART_INTFLAG  (*(RwReg8 *)0x41014018UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM3_USART_STATUS   (*(RwReg16*)0x4101401AUL) /**< \brief (SERCOM3) USART Status */
-#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg  *)0x4101401CUL) /**< \brief (SERCOM3) USART Synchronization Busy */
-#define REG_SERCOM3_USART_RXERRCNT (*(RoReg8 *)0x41014020UL) /**< \brief (SERCOM3) USART Receive Error Count */
-#define REG_SERCOM3_USART_LENGTH   (*(RwReg16*)0x41014022UL) /**< \brief (SERCOM3) USART Length */
-#define REG_SERCOM3_USART_DATA     (*(RwReg  *)0x41014028UL) /**< \brief (SERCOM3) USART Data */
-#define REG_SERCOM3_USART_DBGCTRL  (*(RwReg8 *)0x41014030UL) /**< \brief (SERCOM3) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM3 peripheral ========== */
-#define SERCOM3_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
-#define SERCOM3_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
-#define SERCOM3_DMA                 1        // DMA support implemented?
-#define SERCOM3_DMAC_ID_RX          10       // Index of DMA RX trigger
-#define SERCOM3_DMAC_ID_TX          11       // Index of DMA TX trigger
-#define SERCOM3_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
-#define SERCOM3_GCLK_ID_CORE        24      
-#define SERCOM3_GCLK_ID_SLOW        3       
-#define SERCOM3_INT_MSB             6       
-#define SERCOM3_PMSB                3       
-#define SERCOM3_RETENTION_SUPPORT   0        // Retention supported?
-#define SERCOM3_SE_CNT              1        // SE counter included?
-#define SERCOM3_SPI                 1        // SPI mode implemented?
-#define SERCOM3_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
-#define SERCOM3_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
-#define SERCOM3_SPI_OZMO            0        // OZMO features implemented?
-#define SERCOM3_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
-#define SERCOM3_TTBIT_EXTENSION     1        // 32-bit extension implemented?
-#define SERCOM3_TWIM                1        // TWI Master mode implemented?
-#define SERCOM3_TWIS                1        // TWI Slave mode implemented?
-#define SERCOM3_TWIS_AUTO_ACK       1        // TWI slave automatic acknowledge implemented?
-#define SERCOM3_TWIS_GROUP_CMD      1        // TWI slave group command implemented?
-#define SERCOM3_TWIS_SDASETUP_CNT_SIZE 8        // TWIS sda setup count size
-#define SERCOM3_TWIS_SDASETUP_SIZE  4        // TWIS sda setup size
-#define SERCOM3_TWIS_SUDAT          1        // TWI slave SDA setup implemented?
-#define SERCOM3_TWI_FASTMP          1        // TWI fast mode plus implemented?
-#define SERCOM3_TWI_HSMODE          1        // USART mode implemented?
-#define SERCOM3_TWI_SCLSM_MODE      1        // TWI SCL clock stretch mode implemented?
-#define SERCOM3_TWI_SMB_TIMEOUTS    1        // TWI SMBus timeouts implemented?
-#define SERCOM3_TWI_TENBIT_ADR      1        // TWI ten bit enabled?
-#define SERCOM3_USART               1        // USART mode implemented?
-#define SERCOM3_USART_AUTOBAUD      1        // USART autobaud implemented?
-#define SERCOM3_USART_COLDET        1        // USART collision detection implemented?
-#define SERCOM3_USART_FLOW_CTRL     1        // USART flow control implemented?
-#define SERCOM3_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
-#define SERCOM3_USART_IRDA          1        // USART IrDA implemented?
-#define SERCOM3_USART_ISO7816       1        // USART ISO7816 mode implemented?
-#define SERCOM3_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
-#define SERCOM3_USART_RS485         1        // USART RS485 mode implemented?
-#define SERCOM3_USART_SAMPA_EXT     1        // USART sample adjust implemented?
-#define SERCOM3_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
-
-#endif /* _SAMD51_SERCOM3_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom4.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom4.h
deleted file mode 100644
index 20665abba0..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom4.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM4
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SERCOM4_INSTANCE_
-#define _SAMD51_SERCOM4_INSTANCE_
-
-/* ========== Register definition for SERCOM4 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM4_I2CM_CTRLA     (0x43000000) /**< \brief (SERCOM4) I2CM Control A */
-#define REG_SERCOM4_I2CM_CTRLB     (0x43000004) /**< \brief (SERCOM4) I2CM Control B */
-#define REG_SERCOM4_I2CM_CTRLC     (0x43000008) /**< \brief (SERCOM4) I2CM Control C */
-#define REG_SERCOM4_I2CM_BAUD      (0x4300000C) /**< \brief (SERCOM4) I2CM Baud Rate */
-#define REG_SERCOM4_I2CM_INTENCLR  (0x43000014) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
-#define REG_SERCOM4_I2CM_INTENSET  (0x43000016) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
-#define REG_SERCOM4_I2CM_INTFLAG   (0x43000018) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CM_STATUS    (0x4300001A) /**< \brief (SERCOM4) I2CM Status */
-#define REG_SERCOM4_I2CM_SYNCBUSY  (0x4300001C) /**< \brief (SERCOM4) I2CM Synchronization Busy */
-#define REG_SERCOM4_I2CM_ADDR      (0x43000024) /**< \brief (SERCOM4) I2CM Address */
-#define REG_SERCOM4_I2CM_DATA      (0x43000028) /**< \brief (SERCOM4) I2CM Data */
-#define REG_SERCOM4_I2CM_DBGCTRL   (0x43000030) /**< \brief (SERCOM4) I2CM Debug Control */
-#define REG_SERCOM4_I2CS_CTRLA     (0x43000000) /**< \brief (SERCOM4) I2CS Control A */
-#define REG_SERCOM4_I2CS_CTRLB     (0x43000004) /**< \brief (SERCOM4) I2CS Control B */
-#define REG_SERCOM4_I2CS_CTRLC     (0x43000008) /**< \brief (SERCOM4) I2CS Control C */
-#define REG_SERCOM4_I2CS_INTENCLR  (0x43000014) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
-#define REG_SERCOM4_I2CS_INTENSET  (0x43000016) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
-#define REG_SERCOM4_I2CS_INTFLAG   (0x43000018) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CS_STATUS    (0x4300001A) /**< \brief (SERCOM4) I2CS Status */
-#define REG_SERCOM4_I2CS_SYNCBUSY  (0x4300001C) /**< \brief (SERCOM4) I2CS Synchronization Busy */
-#define REG_SERCOM4_I2CS_LENGTH    (0x43000022) /**< \brief (SERCOM4) I2CS Length */
-#define REG_SERCOM4_I2CS_ADDR      (0x43000024) /**< \brief (SERCOM4) I2CS Address */
-#define REG_SERCOM4_I2CS_DATA      (0x43000028) /**< \brief (SERCOM4) I2CS Data */
-#define REG_SERCOM4_SPI_CTRLA      (0x43000000) /**< \brief (SERCOM4) SPI Control A */
-#define REG_SERCOM4_SPI_CTRLB      (0x43000004) /**< \brief (SERCOM4) SPI Control B */
-#define REG_SERCOM4_SPI_CTRLC      (0x43000008) /**< \brief (SERCOM4) SPI Control C */
-#define REG_SERCOM4_SPI_BAUD       (0x4300000C) /**< \brief (SERCOM4) SPI Baud Rate */
-#define REG_SERCOM4_SPI_INTENCLR   (0x43000014) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
-#define REG_SERCOM4_SPI_INTENSET   (0x43000016) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
-#define REG_SERCOM4_SPI_INTFLAG    (0x43000018) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM4_SPI_STATUS     (0x4300001A) /**< \brief (SERCOM4) SPI Status */
-#define REG_SERCOM4_SPI_SYNCBUSY   (0x4300001C) /**< \brief (SERCOM4) SPI Synchronization Busy */
-#define REG_SERCOM4_SPI_LENGTH     (0x43000022) /**< \brief (SERCOM4) SPI Length */
-#define REG_SERCOM4_SPI_ADDR       (0x43000024) /**< \brief (SERCOM4) SPI Address */
-#define REG_SERCOM4_SPI_DATA       (0x43000028) /**< \brief (SERCOM4) SPI Data */
-#define REG_SERCOM4_SPI_DBGCTRL    (0x43000030) /**< \brief (SERCOM4) SPI Debug Control */
-#define REG_SERCOM4_USART_CTRLA    (0x43000000) /**< \brief (SERCOM4) USART Control A */
-#define REG_SERCOM4_USART_CTRLB    (0x43000004) /**< \brief (SERCOM4) USART Control B */
-#define REG_SERCOM4_USART_CTRLC    (0x43000008) /**< \brief (SERCOM4) USART Control C */
-#define REG_SERCOM4_USART_BAUD     (0x4300000C) /**< \brief (SERCOM4) USART Baud Rate */
-#define REG_SERCOM4_USART_RXPL     (0x4300000E) /**< \brief (SERCOM4) USART Receive Pulse Length */
-#define REG_SERCOM4_USART_INTENCLR (0x43000014) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
-#define REG_SERCOM4_USART_INTENSET (0x43000016) /**< \brief (SERCOM4) USART Interrupt Enable Set */
-#define REG_SERCOM4_USART_INTFLAG  (0x43000018) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM4_USART_STATUS   (0x4300001A) /**< \brief (SERCOM4) USART Status */
-#define REG_SERCOM4_USART_SYNCBUSY (0x4300001C) /**< \brief (SERCOM4) USART Synchronization Busy */
-#define REG_SERCOM4_USART_RXERRCNT (0x43000020) /**< \brief (SERCOM4) USART Receive Error Count */
-#define REG_SERCOM4_USART_LENGTH   (0x43000022) /**< \brief (SERCOM4) USART Length */
-#define REG_SERCOM4_USART_DATA     (0x43000028) /**< \brief (SERCOM4) USART Data */
-#define REG_SERCOM4_USART_DBGCTRL  (0x43000030) /**< \brief (SERCOM4) USART Debug Control */
-#else
-#define REG_SERCOM4_I2CM_CTRLA     (*(RwReg  *)0x43000000UL) /**< \brief (SERCOM4) I2CM Control A */
-#define REG_SERCOM4_I2CM_CTRLB     (*(RwReg  *)0x43000004UL) /**< \brief (SERCOM4) I2CM Control B */
-#define REG_SERCOM4_I2CM_CTRLC     (*(RwReg  *)0x43000008UL) /**< \brief (SERCOM4) I2CM Control C */
-#define REG_SERCOM4_I2CM_BAUD      (*(RwReg  *)0x4300000CUL) /**< \brief (SERCOM4) I2CM Baud Rate */
-#define REG_SERCOM4_I2CM_INTENCLR  (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
-#define REG_SERCOM4_I2CM_INTENSET  (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
-#define REG_SERCOM4_I2CM_INTFLAG   (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CM_STATUS    (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) I2CM Status */
-#define REG_SERCOM4_I2CM_SYNCBUSY  (*(RoReg  *)0x4300001CUL) /**< \brief (SERCOM4) I2CM Synchronization Busy */
-#define REG_SERCOM4_I2CM_ADDR      (*(RwReg  *)0x43000024UL) /**< \brief (SERCOM4) I2CM Address */
-#define REG_SERCOM4_I2CM_DATA      (*(RwReg  *)0x43000028UL) /**< \brief (SERCOM4) I2CM Data */
-#define REG_SERCOM4_I2CM_DBGCTRL   (*(RwReg8 *)0x43000030UL) /**< \brief (SERCOM4) I2CM Debug Control */
-#define REG_SERCOM4_I2CS_CTRLA     (*(RwReg  *)0x43000000UL) /**< \brief (SERCOM4) I2CS Control A */
-#define REG_SERCOM4_I2CS_CTRLB     (*(RwReg  *)0x43000004UL) /**< \brief (SERCOM4) I2CS Control B */
-#define REG_SERCOM4_I2CS_CTRLC     (*(RwReg  *)0x43000008UL) /**< \brief (SERCOM4) I2CS Control C */
-#define REG_SERCOM4_I2CS_INTENCLR  (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
-#define REG_SERCOM4_I2CS_INTENSET  (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
-#define REG_SERCOM4_I2CS_INTFLAG   (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM4_I2CS_STATUS    (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) I2CS Status */
-#define REG_SERCOM4_I2CS_SYNCBUSY  (*(RoReg  *)0x4300001CUL) /**< \brief (SERCOM4) I2CS Synchronization Busy */
-#define REG_SERCOM4_I2CS_LENGTH    (*(RwReg16*)0x43000022UL) /**< \brief (SERCOM4) I2CS Length */
-#define REG_SERCOM4_I2CS_ADDR      (*(RwReg  *)0x43000024UL) /**< \brief (SERCOM4) I2CS Address */
-#define REG_SERCOM4_I2CS_DATA      (*(RwReg  *)0x43000028UL) /**< \brief (SERCOM4) I2CS Data */
-#define REG_SERCOM4_SPI_CTRLA      (*(RwReg  *)0x43000000UL) /**< \brief (SERCOM4) SPI Control A */
-#define REG_SERCOM4_SPI_CTRLB      (*(RwReg  *)0x43000004UL) /**< \brief (SERCOM4) SPI Control B */
-#define REG_SERCOM4_SPI_CTRLC      (*(RwReg  *)0x43000008UL) /**< \brief (SERCOM4) SPI Control C */
-#define REG_SERCOM4_SPI_BAUD       (*(RwReg8 *)0x4300000CUL) /**< \brief (SERCOM4) SPI Baud Rate */
-#define REG_SERCOM4_SPI_INTENCLR   (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
-#define REG_SERCOM4_SPI_INTENSET   (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
-#define REG_SERCOM4_SPI_INTFLAG    (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM4_SPI_STATUS     (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) SPI Status */
-#define REG_SERCOM4_SPI_SYNCBUSY   (*(RoReg  *)0x4300001CUL) /**< \brief (SERCOM4) SPI Synchronization Busy */
-#define REG_SERCOM4_SPI_LENGTH     (*(RwReg16*)0x43000022UL) /**< \brief (SERCOM4) SPI Length */
-#define REG_SERCOM4_SPI_ADDR       (*(RwReg  *)0x43000024UL) /**< \brief (SERCOM4) SPI Address */
-#define REG_SERCOM4_SPI_DATA       (*(RwReg  *)0x43000028UL) /**< \brief (SERCOM4) SPI Data */
-#define REG_SERCOM4_SPI_DBGCTRL    (*(RwReg8 *)0x43000030UL) /**< \brief (SERCOM4) SPI Debug Control */
-#define REG_SERCOM4_USART_CTRLA    (*(RwReg  *)0x43000000UL) /**< \brief (SERCOM4) USART Control A */
-#define REG_SERCOM4_USART_CTRLB    (*(RwReg  *)0x43000004UL) /**< \brief (SERCOM4) USART Control B */
-#define REG_SERCOM4_USART_CTRLC    (*(RwReg  *)0x43000008UL) /**< \brief (SERCOM4) USART Control C */
-#define REG_SERCOM4_USART_BAUD     (*(RwReg16*)0x4300000CUL) /**< \brief (SERCOM4) USART Baud Rate */
-#define REG_SERCOM4_USART_RXPL     (*(RwReg8 *)0x4300000EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */
-#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x43000014UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
-#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x43000016UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */
-#define REG_SERCOM4_USART_INTFLAG  (*(RwReg8 *)0x43000018UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM4_USART_STATUS   (*(RwReg16*)0x4300001AUL) /**< \brief (SERCOM4) USART Status */
-#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg  *)0x4300001CUL) /**< \brief (SERCOM4) USART Synchronization Busy */
-#define REG_SERCOM4_USART_RXERRCNT (*(RoReg8 *)0x43000020UL) /**< \brief (SERCOM4) USART Receive Error Count */
-#define REG_SERCOM4_USART_LENGTH   (*(RwReg16*)0x43000022UL) /**< \brief (SERCOM4) USART Length */
-#define REG_SERCOM4_USART_DATA     (*(RwReg  *)0x43000028UL) /**< \brief (SERCOM4) USART Data */
-#define REG_SERCOM4_USART_DBGCTRL  (*(RwReg8 *)0x43000030UL) /**< \brief (SERCOM4) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM4 peripheral ========== */
-#define SERCOM4_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
-#define SERCOM4_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
-#define SERCOM4_DMA                 1        // DMA support implemented?
-#define SERCOM4_DMAC_ID_RX          12       // Index of DMA RX trigger
-#define SERCOM4_DMAC_ID_TX          13       // Index of DMA TX trigger
-#define SERCOM4_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
-#define SERCOM4_GCLK_ID_CORE        34      
-#define SERCOM4_GCLK_ID_SLOW        3       
-#define SERCOM4_INT_MSB             6       
-#define SERCOM4_PMSB                3       
-#define SERCOM4_RETENTION_SUPPORT   0        // Retention supported?
-#define SERCOM4_SE_CNT              1        // SE counter included?
-#define SERCOM4_SPI                 1        // SPI mode implemented?
-#define SERCOM4_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
-#define SERCOM4_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
-#define SERCOM4_SPI_OZMO            0        // OZMO features implemented?
-#define SERCOM4_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
-#define SERCOM4_TTBIT_EXTENSION     1        // 32-bit extension implemented?
-#define SERCOM4_TWIM                1        // TWI Master mode implemented?
-#define SERCOM4_TWIS                1        // TWI Slave mode implemented?
-#define SERCOM4_TWIS_AUTO_ACK       1        // TWI slave automatic acknowledge implemented?
-#define SERCOM4_TWIS_GROUP_CMD      1        // TWI slave group command implemented?
-#define SERCOM4_TWIS_SDASETUP_CNT_SIZE 8        // TWIS sda setup count size
-#define SERCOM4_TWIS_SDASETUP_SIZE  4        // TWIS sda setup size
-#define SERCOM4_TWIS_SUDAT          1        // TWI slave SDA setup implemented?
-#define SERCOM4_TWI_FASTMP          1        // TWI fast mode plus implemented?
-#define SERCOM4_TWI_HSMODE          1        // USART mode implemented?
-#define SERCOM4_TWI_SCLSM_MODE      1        // TWI SCL clock stretch mode implemented?
-#define SERCOM4_TWI_SMB_TIMEOUTS    1        // TWI SMBus timeouts implemented?
-#define SERCOM4_TWI_TENBIT_ADR      1        // TWI ten bit enabled?
-#define SERCOM4_USART               1        // USART mode implemented?
-#define SERCOM4_USART_AUTOBAUD      1        // USART autobaud implemented?
-#define SERCOM4_USART_COLDET        1        // USART collision detection implemented?
-#define SERCOM4_USART_FLOW_CTRL     1        // USART flow control implemented?
-#define SERCOM4_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
-#define SERCOM4_USART_IRDA          1        // USART IrDA implemented?
-#define SERCOM4_USART_ISO7816       1        // USART ISO7816 mode implemented?
-#define SERCOM4_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
-#define SERCOM4_USART_RS485         1        // USART RS485 mode implemented?
-#define SERCOM4_USART_SAMPA_EXT     1        // USART sample adjust implemented?
-#define SERCOM4_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
-
-#endif /* _SAMD51_SERCOM4_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom5.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom5.h
deleted file mode 100644
index 7705b5f5ca..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom5.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM5
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SERCOM5_INSTANCE_
-#define _SAMD51_SERCOM5_INSTANCE_
-
-/* ========== Register definition for SERCOM5 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM5_I2CM_CTRLA     (0x43000400) /**< \brief (SERCOM5) I2CM Control A */
-#define REG_SERCOM5_I2CM_CTRLB     (0x43000404) /**< \brief (SERCOM5) I2CM Control B */
-#define REG_SERCOM5_I2CM_CTRLC     (0x43000408) /**< \brief (SERCOM5) I2CM Control C */
-#define REG_SERCOM5_I2CM_BAUD      (0x4300040C) /**< \brief (SERCOM5) I2CM Baud Rate */
-#define REG_SERCOM5_I2CM_INTENCLR  (0x43000414) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
-#define REG_SERCOM5_I2CM_INTENSET  (0x43000416) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
-#define REG_SERCOM5_I2CM_INTFLAG   (0x43000418) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CM_STATUS    (0x4300041A) /**< \brief (SERCOM5) I2CM Status */
-#define REG_SERCOM5_I2CM_SYNCBUSY  (0x4300041C) /**< \brief (SERCOM5) I2CM Synchronization Busy */
-#define REG_SERCOM5_I2CM_ADDR      (0x43000424) /**< \brief (SERCOM5) I2CM Address */
-#define REG_SERCOM5_I2CM_DATA      (0x43000428) /**< \brief (SERCOM5) I2CM Data */
-#define REG_SERCOM5_I2CM_DBGCTRL   (0x43000430) /**< \brief (SERCOM5) I2CM Debug Control */
-#define REG_SERCOM5_I2CS_CTRLA     (0x43000400) /**< \brief (SERCOM5) I2CS Control A */
-#define REG_SERCOM5_I2CS_CTRLB     (0x43000404) /**< \brief (SERCOM5) I2CS Control B */
-#define REG_SERCOM5_I2CS_CTRLC     (0x43000408) /**< \brief (SERCOM5) I2CS Control C */
-#define REG_SERCOM5_I2CS_INTENCLR  (0x43000414) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
-#define REG_SERCOM5_I2CS_INTENSET  (0x43000416) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
-#define REG_SERCOM5_I2CS_INTFLAG   (0x43000418) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CS_STATUS    (0x4300041A) /**< \brief (SERCOM5) I2CS Status */
-#define REG_SERCOM5_I2CS_SYNCBUSY  (0x4300041C) /**< \brief (SERCOM5) I2CS Synchronization Busy */
-#define REG_SERCOM5_I2CS_LENGTH    (0x43000422) /**< \brief (SERCOM5) I2CS Length */
-#define REG_SERCOM5_I2CS_ADDR      (0x43000424) /**< \brief (SERCOM5) I2CS Address */
-#define REG_SERCOM5_I2CS_DATA      (0x43000428) /**< \brief (SERCOM5) I2CS Data */
-#define REG_SERCOM5_SPI_CTRLA      (0x43000400) /**< \brief (SERCOM5) SPI Control A */
-#define REG_SERCOM5_SPI_CTRLB      (0x43000404) /**< \brief (SERCOM5) SPI Control B */
-#define REG_SERCOM5_SPI_CTRLC      (0x43000408) /**< \brief (SERCOM5) SPI Control C */
-#define REG_SERCOM5_SPI_BAUD       (0x4300040C) /**< \brief (SERCOM5) SPI Baud Rate */
-#define REG_SERCOM5_SPI_INTENCLR   (0x43000414) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
-#define REG_SERCOM5_SPI_INTENSET   (0x43000416) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
-#define REG_SERCOM5_SPI_INTFLAG    (0x43000418) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM5_SPI_STATUS     (0x4300041A) /**< \brief (SERCOM5) SPI Status */
-#define REG_SERCOM5_SPI_SYNCBUSY   (0x4300041C) /**< \brief (SERCOM5) SPI Synchronization Busy */
-#define REG_SERCOM5_SPI_LENGTH     (0x43000422) /**< \brief (SERCOM5) SPI Length */
-#define REG_SERCOM5_SPI_ADDR       (0x43000424) /**< \brief (SERCOM5) SPI Address */
-#define REG_SERCOM5_SPI_DATA       (0x43000428) /**< \brief (SERCOM5) SPI Data */
-#define REG_SERCOM5_SPI_DBGCTRL    (0x43000430) /**< \brief (SERCOM5) SPI Debug Control */
-#define REG_SERCOM5_USART_CTRLA    (0x43000400) /**< \brief (SERCOM5) USART Control A */
-#define REG_SERCOM5_USART_CTRLB    (0x43000404) /**< \brief (SERCOM5) USART Control B */
-#define REG_SERCOM5_USART_CTRLC    (0x43000408) /**< \brief (SERCOM5) USART Control C */
-#define REG_SERCOM5_USART_BAUD     (0x4300040C) /**< \brief (SERCOM5) USART Baud Rate */
-#define REG_SERCOM5_USART_RXPL     (0x4300040E) /**< \brief (SERCOM5) USART Receive Pulse Length */
-#define REG_SERCOM5_USART_INTENCLR (0x43000414) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
-#define REG_SERCOM5_USART_INTENSET (0x43000416) /**< \brief (SERCOM5) USART Interrupt Enable Set */
-#define REG_SERCOM5_USART_INTFLAG  (0x43000418) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM5_USART_STATUS   (0x4300041A) /**< \brief (SERCOM5) USART Status */
-#define REG_SERCOM5_USART_SYNCBUSY (0x4300041C) /**< \brief (SERCOM5) USART Synchronization Busy */
-#define REG_SERCOM5_USART_RXERRCNT (0x43000420) /**< \brief (SERCOM5) USART Receive Error Count */
-#define REG_SERCOM5_USART_LENGTH   (0x43000422) /**< \brief (SERCOM5) USART Length */
-#define REG_SERCOM5_USART_DATA     (0x43000428) /**< \brief (SERCOM5) USART Data */
-#define REG_SERCOM5_USART_DBGCTRL  (0x43000430) /**< \brief (SERCOM5) USART Debug Control */
-#else
-#define REG_SERCOM5_I2CM_CTRLA     (*(RwReg  *)0x43000400UL) /**< \brief (SERCOM5) I2CM Control A */
-#define REG_SERCOM5_I2CM_CTRLB     (*(RwReg  *)0x43000404UL) /**< \brief (SERCOM5) I2CM Control B */
-#define REG_SERCOM5_I2CM_CTRLC     (*(RwReg  *)0x43000408UL) /**< \brief (SERCOM5) I2CM Control C */
-#define REG_SERCOM5_I2CM_BAUD      (*(RwReg  *)0x4300040CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
-#define REG_SERCOM5_I2CM_INTENCLR  (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
-#define REG_SERCOM5_I2CM_INTENSET  (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
-#define REG_SERCOM5_I2CM_INTFLAG   (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CM_STATUS    (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) I2CM Status */
-#define REG_SERCOM5_I2CM_SYNCBUSY  (*(RoReg  *)0x4300041CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */
-#define REG_SERCOM5_I2CM_ADDR      (*(RwReg  *)0x43000424UL) /**< \brief (SERCOM5) I2CM Address */
-#define REG_SERCOM5_I2CM_DATA      (*(RwReg  *)0x43000428UL) /**< \brief (SERCOM5) I2CM Data */
-#define REG_SERCOM5_I2CM_DBGCTRL   (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) I2CM Debug Control */
-#define REG_SERCOM5_I2CS_CTRLA     (*(RwReg  *)0x43000400UL) /**< \brief (SERCOM5) I2CS Control A */
-#define REG_SERCOM5_I2CS_CTRLB     (*(RwReg  *)0x43000404UL) /**< \brief (SERCOM5) I2CS Control B */
-#define REG_SERCOM5_I2CS_CTRLC     (*(RwReg  *)0x43000408UL) /**< \brief (SERCOM5) I2CS Control C */
-#define REG_SERCOM5_I2CS_INTENCLR  (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
-#define REG_SERCOM5_I2CS_INTENSET  (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
-#define REG_SERCOM5_I2CS_INTFLAG   (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM5_I2CS_STATUS    (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) I2CS Status */
-#define REG_SERCOM5_I2CS_SYNCBUSY  (*(RoReg  *)0x4300041CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */
-#define REG_SERCOM5_I2CS_LENGTH    (*(RwReg16*)0x43000422UL) /**< \brief (SERCOM5) I2CS Length */
-#define REG_SERCOM5_I2CS_ADDR      (*(RwReg  *)0x43000424UL) /**< \brief (SERCOM5) I2CS Address */
-#define REG_SERCOM5_I2CS_DATA      (*(RwReg  *)0x43000428UL) /**< \brief (SERCOM5) I2CS Data */
-#define REG_SERCOM5_SPI_CTRLA      (*(RwReg  *)0x43000400UL) /**< \brief (SERCOM5) SPI Control A */
-#define REG_SERCOM5_SPI_CTRLB      (*(RwReg  *)0x43000404UL) /**< \brief (SERCOM5) SPI Control B */
-#define REG_SERCOM5_SPI_CTRLC      (*(RwReg  *)0x43000408UL) /**< \brief (SERCOM5) SPI Control C */
-#define REG_SERCOM5_SPI_BAUD       (*(RwReg8 *)0x4300040CUL) /**< \brief (SERCOM5) SPI Baud Rate */
-#define REG_SERCOM5_SPI_INTENCLR   (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
-#define REG_SERCOM5_SPI_INTENSET   (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
-#define REG_SERCOM5_SPI_INTFLAG    (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM5_SPI_STATUS     (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) SPI Status */
-#define REG_SERCOM5_SPI_SYNCBUSY   (*(RoReg  *)0x4300041CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */
-#define REG_SERCOM5_SPI_LENGTH     (*(RwReg16*)0x43000422UL) /**< \brief (SERCOM5) SPI Length */
-#define REG_SERCOM5_SPI_ADDR       (*(RwReg  *)0x43000424UL) /**< \brief (SERCOM5) SPI Address */
-#define REG_SERCOM5_SPI_DATA       (*(RwReg  *)0x43000428UL) /**< \brief (SERCOM5) SPI Data */
-#define REG_SERCOM5_SPI_DBGCTRL    (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) SPI Debug Control */
-#define REG_SERCOM5_USART_CTRLA    (*(RwReg  *)0x43000400UL) /**< \brief (SERCOM5) USART Control A */
-#define REG_SERCOM5_USART_CTRLB    (*(RwReg  *)0x43000404UL) /**< \brief (SERCOM5) USART Control B */
-#define REG_SERCOM5_USART_CTRLC    (*(RwReg  *)0x43000408UL) /**< \brief (SERCOM5) USART Control C */
-#define REG_SERCOM5_USART_BAUD     (*(RwReg16*)0x4300040CUL) /**< \brief (SERCOM5) USART Baud Rate */
-#define REG_SERCOM5_USART_RXPL     (*(RwReg8 *)0x4300040EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
-#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x43000414UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
-#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x43000416UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
-#define REG_SERCOM5_USART_INTFLAG  (*(RwReg8 *)0x43000418UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM5_USART_STATUS   (*(RwReg16*)0x4300041AUL) /**< \brief (SERCOM5) USART Status */
-#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg  *)0x4300041CUL) /**< \brief (SERCOM5) USART Synchronization Busy */
-#define REG_SERCOM5_USART_RXERRCNT (*(RoReg8 *)0x43000420UL) /**< \brief (SERCOM5) USART Receive Error Count */
-#define REG_SERCOM5_USART_LENGTH   (*(RwReg16*)0x43000422UL) /**< \brief (SERCOM5) USART Length */
-#define REG_SERCOM5_USART_DATA     (*(RwReg  *)0x43000428UL) /**< \brief (SERCOM5) USART Data */
-#define REG_SERCOM5_USART_DBGCTRL  (*(RwReg8 *)0x43000430UL) /**< \brief (SERCOM5) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM5 peripheral ========== */
-#define SERCOM5_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
-#define SERCOM5_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
-#define SERCOM5_DMA                 1        // DMA support implemented?
-#define SERCOM5_DMAC_ID_RX          14       // Index of DMA RX trigger
-#define SERCOM5_DMAC_ID_TX          15       // Index of DMA TX trigger
-#define SERCOM5_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
-#define SERCOM5_GCLK_ID_CORE        35      
-#define SERCOM5_GCLK_ID_SLOW        3       
-#define SERCOM5_INT_MSB             6       
-#define SERCOM5_PMSB                3       
-#define SERCOM5_RETENTION_SUPPORT   0        // Retention supported?
-#define SERCOM5_SE_CNT              1        // SE counter included?
-#define SERCOM5_SPI                 1        // SPI mode implemented?
-#define SERCOM5_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
-#define SERCOM5_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
-#define SERCOM5_SPI_OZMO            0        // OZMO features implemented?
-#define SERCOM5_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
-#define SERCOM5_TTBIT_EXTENSION     1        // 32-bit extension implemented?
-#define SERCOM5_TWIM                1        // TWI Master mode implemented?
-#define SERCOM5_TWIS                1        // TWI Slave mode implemented?
-#define SERCOM5_TWIS_AUTO_ACK       1        // TWI slave automatic acknowledge implemented?
-#define SERCOM5_TWIS_GROUP_CMD      1        // TWI slave group command implemented?
-#define SERCOM5_TWIS_SDASETUP_CNT_SIZE 8        // TWIS sda setup count size
-#define SERCOM5_TWIS_SDASETUP_SIZE  4        // TWIS sda setup size
-#define SERCOM5_TWIS_SUDAT          1        // TWI slave SDA setup implemented?
-#define SERCOM5_TWI_FASTMP          1        // TWI fast mode plus implemented?
-#define SERCOM5_TWI_HSMODE          1        // USART mode implemented?
-#define SERCOM5_TWI_SCLSM_MODE      1        // TWI SCL clock stretch mode implemented?
-#define SERCOM5_TWI_SMB_TIMEOUTS    1        // TWI SMBus timeouts implemented?
-#define SERCOM5_TWI_TENBIT_ADR      1        // TWI ten bit enabled?
-#define SERCOM5_USART               1        // USART mode implemented?
-#define SERCOM5_USART_AUTOBAUD      1        // USART autobaud implemented?
-#define SERCOM5_USART_COLDET        1        // USART collision detection implemented?
-#define SERCOM5_USART_FLOW_CTRL     1        // USART flow control implemented?
-#define SERCOM5_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
-#define SERCOM5_USART_IRDA          1        // USART IrDA implemented?
-#define SERCOM5_USART_ISO7816       1        // USART ISO7816 mode implemented?
-#define SERCOM5_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
-#define SERCOM5_USART_RS485         1        // USART RS485 mode implemented?
-#define SERCOM5_USART_SAMPA_EXT     1        // USART sample adjust implemented?
-#define SERCOM5_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
-
-#endif /* _SAMD51_SERCOM5_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom6.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom6.h
deleted file mode 100644
index 0d86569e86..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom6.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM6
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SERCOM6_INSTANCE_
-#define _SAMD51_SERCOM6_INSTANCE_
-
-/* ========== Register definition for SERCOM6 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM6_I2CM_CTRLA     (0x43000800) /**< \brief (SERCOM6) I2CM Control A */
-#define REG_SERCOM6_I2CM_CTRLB     (0x43000804) /**< \brief (SERCOM6) I2CM Control B */
-#define REG_SERCOM6_I2CM_CTRLC     (0x43000808) /**< \brief (SERCOM6) I2CM Control C */
-#define REG_SERCOM6_I2CM_BAUD      (0x4300080C) /**< \brief (SERCOM6) I2CM Baud Rate */
-#define REG_SERCOM6_I2CM_INTENCLR  (0x43000814) /**< \brief (SERCOM6) I2CM Interrupt Enable Clear */
-#define REG_SERCOM6_I2CM_INTENSET  (0x43000816) /**< \brief (SERCOM6) I2CM Interrupt Enable Set */
-#define REG_SERCOM6_I2CM_INTFLAG   (0x43000818) /**< \brief (SERCOM6) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM6_I2CM_STATUS    (0x4300081A) /**< \brief (SERCOM6) I2CM Status */
-#define REG_SERCOM6_I2CM_SYNCBUSY  (0x4300081C) /**< \brief (SERCOM6) I2CM Synchronization Busy */
-#define REG_SERCOM6_I2CM_ADDR      (0x43000824) /**< \brief (SERCOM6) I2CM Address */
-#define REG_SERCOM6_I2CM_DATA      (0x43000828) /**< \brief (SERCOM6) I2CM Data */
-#define REG_SERCOM6_I2CM_DBGCTRL   (0x43000830) /**< \brief (SERCOM6) I2CM Debug Control */
-#define REG_SERCOM6_I2CS_CTRLA     (0x43000800) /**< \brief (SERCOM6) I2CS Control A */
-#define REG_SERCOM6_I2CS_CTRLB     (0x43000804) /**< \brief (SERCOM6) I2CS Control B */
-#define REG_SERCOM6_I2CS_CTRLC     (0x43000808) /**< \brief (SERCOM6) I2CS Control C */
-#define REG_SERCOM6_I2CS_INTENCLR  (0x43000814) /**< \brief (SERCOM6) I2CS Interrupt Enable Clear */
-#define REG_SERCOM6_I2CS_INTENSET  (0x43000816) /**< \brief (SERCOM6) I2CS Interrupt Enable Set */
-#define REG_SERCOM6_I2CS_INTFLAG   (0x43000818) /**< \brief (SERCOM6) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM6_I2CS_STATUS    (0x4300081A) /**< \brief (SERCOM6) I2CS Status */
-#define REG_SERCOM6_I2CS_SYNCBUSY  (0x4300081C) /**< \brief (SERCOM6) I2CS Synchronization Busy */
-#define REG_SERCOM6_I2CS_LENGTH    (0x43000822) /**< \brief (SERCOM6) I2CS Length */
-#define REG_SERCOM6_I2CS_ADDR      (0x43000824) /**< \brief (SERCOM6) I2CS Address */
-#define REG_SERCOM6_I2CS_DATA      (0x43000828) /**< \brief (SERCOM6) I2CS Data */
-#define REG_SERCOM6_SPI_CTRLA      (0x43000800) /**< \brief (SERCOM6) SPI Control A */
-#define REG_SERCOM6_SPI_CTRLB      (0x43000804) /**< \brief (SERCOM6) SPI Control B */
-#define REG_SERCOM6_SPI_CTRLC      (0x43000808) /**< \brief (SERCOM6) SPI Control C */
-#define REG_SERCOM6_SPI_BAUD       (0x4300080C) /**< \brief (SERCOM6) SPI Baud Rate */
-#define REG_SERCOM6_SPI_INTENCLR   (0x43000814) /**< \brief (SERCOM6) SPI Interrupt Enable Clear */
-#define REG_SERCOM6_SPI_INTENSET   (0x43000816) /**< \brief (SERCOM6) SPI Interrupt Enable Set */
-#define REG_SERCOM6_SPI_INTFLAG    (0x43000818) /**< \brief (SERCOM6) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM6_SPI_STATUS     (0x4300081A) /**< \brief (SERCOM6) SPI Status */
-#define REG_SERCOM6_SPI_SYNCBUSY   (0x4300081C) /**< \brief (SERCOM6) SPI Synchronization Busy */
-#define REG_SERCOM6_SPI_LENGTH     (0x43000822) /**< \brief (SERCOM6) SPI Length */
-#define REG_SERCOM6_SPI_ADDR       (0x43000824) /**< \brief (SERCOM6) SPI Address */
-#define REG_SERCOM6_SPI_DATA       (0x43000828) /**< \brief (SERCOM6) SPI Data */
-#define REG_SERCOM6_SPI_DBGCTRL    (0x43000830) /**< \brief (SERCOM6) SPI Debug Control */
-#define REG_SERCOM6_USART_CTRLA    (0x43000800) /**< \brief (SERCOM6) USART Control A */
-#define REG_SERCOM6_USART_CTRLB    (0x43000804) /**< \brief (SERCOM6) USART Control B */
-#define REG_SERCOM6_USART_CTRLC    (0x43000808) /**< \brief (SERCOM6) USART Control C */
-#define REG_SERCOM6_USART_BAUD     (0x4300080C) /**< \brief (SERCOM6) USART Baud Rate */
-#define REG_SERCOM6_USART_RXPL     (0x4300080E) /**< \brief (SERCOM6) USART Receive Pulse Length */
-#define REG_SERCOM6_USART_INTENCLR (0x43000814) /**< \brief (SERCOM6) USART Interrupt Enable Clear */
-#define REG_SERCOM6_USART_INTENSET (0x43000816) /**< \brief (SERCOM6) USART Interrupt Enable Set */
-#define REG_SERCOM6_USART_INTFLAG  (0x43000818) /**< \brief (SERCOM6) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM6_USART_STATUS   (0x4300081A) /**< \brief (SERCOM6) USART Status */
-#define REG_SERCOM6_USART_SYNCBUSY (0x4300081C) /**< \brief (SERCOM6) USART Synchronization Busy */
-#define REG_SERCOM6_USART_RXERRCNT (0x43000820) /**< \brief (SERCOM6) USART Receive Error Count */
-#define REG_SERCOM6_USART_LENGTH   (0x43000822) /**< \brief (SERCOM6) USART Length */
-#define REG_SERCOM6_USART_DATA     (0x43000828) /**< \brief (SERCOM6) USART Data */
-#define REG_SERCOM6_USART_DBGCTRL  (0x43000830) /**< \brief (SERCOM6) USART Debug Control */
-#else
-#define REG_SERCOM6_I2CM_CTRLA     (*(RwReg  *)0x43000800UL) /**< \brief (SERCOM6) I2CM Control A */
-#define REG_SERCOM6_I2CM_CTRLB     (*(RwReg  *)0x43000804UL) /**< \brief (SERCOM6) I2CM Control B */
-#define REG_SERCOM6_I2CM_CTRLC     (*(RwReg  *)0x43000808UL) /**< \brief (SERCOM6) I2CM Control C */
-#define REG_SERCOM6_I2CM_BAUD      (*(RwReg  *)0x4300080CUL) /**< \brief (SERCOM6) I2CM Baud Rate */
-#define REG_SERCOM6_I2CM_INTENCLR  (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) I2CM Interrupt Enable Clear */
-#define REG_SERCOM6_I2CM_INTENSET  (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) I2CM Interrupt Enable Set */
-#define REG_SERCOM6_I2CM_INTFLAG   (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM6_I2CM_STATUS    (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) I2CM Status */
-#define REG_SERCOM6_I2CM_SYNCBUSY  (*(RoReg  *)0x4300081CUL) /**< \brief (SERCOM6) I2CM Synchronization Busy */
-#define REG_SERCOM6_I2CM_ADDR      (*(RwReg  *)0x43000824UL) /**< \brief (SERCOM6) I2CM Address */
-#define REG_SERCOM6_I2CM_DATA      (*(RwReg  *)0x43000828UL) /**< \brief (SERCOM6) I2CM Data */
-#define REG_SERCOM6_I2CM_DBGCTRL   (*(RwReg8 *)0x43000830UL) /**< \brief (SERCOM6) I2CM Debug Control */
-#define REG_SERCOM6_I2CS_CTRLA     (*(RwReg  *)0x43000800UL) /**< \brief (SERCOM6) I2CS Control A */
-#define REG_SERCOM6_I2CS_CTRLB     (*(RwReg  *)0x43000804UL) /**< \brief (SERCOM6) I2CS Control B */
-#define REG_SERCOM6_I2CS_CTRLC     (*(RwReg  *)0x43000808UL) /**< \brief (SERCOM6) I2CS Control C */
-#define REG_SERCOM6_I2CS_INTENCLR  (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) I2CS Interrupt Enable Clear */
-#define REG_SERCOM6_I2CS_INTENSET  (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) I2CS Interrupt Enable Set */
-#define REG_SERCOM6_I2CS_INTFLAG   (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM6_I2CS_STATUS    (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) I2CS Status */
-#define REG_SERCOM6_I2CS_SYNCBUSY  (*(RoReg  *)0x4300081CUL) /**< \brief (SERCOM6) I2CS Synchronization Busy */
-#define REG_SERCOM6_I2CS_LENGTH    (*(RwReg16*)0x43000822UL) /**< \brief (SERCOM6) I2CS Length */
-#define REG_SERCOM6_I2CS_ADDR      (*(RwReg  *)0x43000824UL) /**< \brief (SERCOM6) I2CS Address */
-#define REG_SERCOM6_I2CS_DATA      (*(RwReg  *)0x43000828UL) /**< \brief (SERCOM6) I2CS Data */
-#define REG_SERCOM6_SPI_CTRLA      (*(RwReg  *)0x43000800UL) /**< \brief (SERCOM6) SPI Control A */
-#define REG_SERCOM6_SPI_CTRLB      (*(RwReg  *)0x43000804UL) /**< \brief (SERCOM6) SPI Control B */
-#define REG_SERCOM6_SPI_CTRLC      (*(RwReg  *)0x43000808UL) /**< \brief (SERCOM6) SPI Control C */
-#define REG_SERCOM6_SPI_BAUD       (*(RwReg8 *)0x4300080CUL) /**< \brief (SERCOM6) SPI Baud Rate */
-#define REG_SERCOM6_SPI_INTENCLR   (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) SPI Interrupt Enable Clear */
-#define REG_SERCOM6_SPI_INTENSET   (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) SPI Interrupt Enable Set */
-#define REG_SERCOM6_SPI_INTFLAG    (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM6_SPI_STATUS     (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) SPI Status */
-#define REG_SERCOM6_SPI_SYNCBUSY   (*(RoReg  *)0x4300081CUL) /**< \brief (SERCOM6) SPI Synchronization Busy */
-#define REG_SERCOM6_SPI_LENGTH     (*(RwReg16*)0x43000822UL) /**< \brief (SERCOM6) SPI Length */
-#define REG_SERCOM6_SPI_ADDR       (*(RwReg  *)0x43000824UL) /**< \brief (SERCOM6) SPI Address */
-#define REG_SERCOM6_SPI_DATA       (*(RwReg  *)0x43000828UL) /**< \brief (SERCOM6) SPI Data */
-#define REG_SERCOM6_SPI_DBGCTRL    (*(RwReg8 *)0x43000830UL) /**< \brief (SERCOM6) SPI Debug Control */
-#define REG_SERCOM6_USART_CTRLA    (*(RwReg  *)0x43000800UL) /**< \brief (SERCOM6) USART Control A */
-#define REG_SERCOM6_USART_CTRLB    (*(RwReg  *)0x43000804UL) /**< \brief (SERCOM6) USART Control B */
-#define REG_SERCOM6_USART_CTRLC    (*(RwReg  *)0x43000808UL) /**< \brief (SERCOM6) USART Control C */
-#define REG_SERCOM6_USART_BAUD     (*(RwReg16*)0x4300080CUL) /**< \brief (SERCOM6) USART Baud Rate */
-#define REG_SERCOM6_USART_RXPL     (*(RwReg8 *)0x4300080EUL) /**< \brief (SERCOM6) USART Receive Pulse Length */
-#define REG_SERCOM6_USART_INTENCLR (*(RwReg8 *)0x43000814UL) /**< \brief (SERCOM6) USART Interrupt Enable Clear */
-#define REG_SERCOM6_USART_INTENSET (*(RwReg8 *)0x43000816UL) /**< \brief (SERCOM6) USART Interrupt Enable Set */
-#define REG_SERCOM6_USART_INTFLAG  (*(RwReg8 *)0x43000818UL) /**< \brief (SERCOM6) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM6_USART_STATUS   (*(RwReg16*)0x4300081AUL) /**< \brief (SERCOM6) USART Status */
-#define REG_SERCOM6_USART_SYNCBUSY (*(RoReg  *)0x4300081CUL) /**< \brief (SERCOM6) USART Synchronization Busy */
-#define REG_SERCOM6_USART_RXERRCNT (*(RoReg8 *)0x43000820UL) /**< \brief (SERCOM6) USART Receive Error Count */
-#define REG_SERCOM6_USART_LENGTH   (*(RwReg16*)0x43000822UL) /**< \brief (SERCOM6) USART Length */
-#define REG_SERCOM6_USART_DATA     (*(RwReg  *)0x43000828UL) /**< \brief (SERCOM6) USART Data */
-#define REG_SERCOM6_USART_DBGCTRL  (*(RwReg8 *)0x43000830UL) /**< \brief (SERCOM6) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM6 peripheral ========== */
-#define SERCOM6_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
-#define SERCOM6_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
-#define SERCOM6_DMA                 1        // DMA support implemented?
-#define SERCOM6_DMAC_ID_RX          16       // Index of DMA RX trigger
-#define SERCOM6_DMAC_ID_TX          17       // Index of DMA TX trigger
-#define SERCOM6_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
-#define SERCOM6_GCLK_ID_CORE        36      
-#define SERCOM6_GCLK_ID_SLOW        3       
-#define SERCOM6_INT_MSB             6       
-#define SERCOM6_PMSB                3       
-#define SERCOM6_RETENTION_SUPPORT   0        // Retention supported?
-#define SERCOM6_SE_CNT              1        // SE counter included?
-#define SERCOM6_SPI                 1        // SPI mode implemented?
-#define SERCOM6_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
-#define SERCOM6_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
-#define SERCOM6_SPI_OZMO            0        // OZMO features implemented?
-#define SERCOM6_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
-#define SERCOM6_TTBIT_EXTENSION     1        // 32-bit extension implemented?
-#define SERCOM6_TWIM                1        // TWI Master mode implemented?
-#define SERCOM6_TWIS                1        // TWI Slave mode implemented?
-#define SERCOM6_TWIS_AUTO_ACK       1        // TWI slave automatic acknowledge implemented?
-#define SERCOM6_TWIS_GROUP_CMD      1        // TWI slave group command implemented?
-#define SERCOM6_TWIS_SDASETUP_CNT_SIZE 8        // TWIS sda setup count size
-#define SERCOM6_TWIS_SDASETUP_SIZE  4        // TWIS sda setup size
-#define SERCOM6_TWIS_SUDAT          1        // TWI slave SDA setup implemented?
-#define SERCOM6_TWI_FASTMP          1        // TWI fast mode plus implemented?
-#define SERCOM6_TWI_HSMODE          1        // USART mode implemented?
-#define SERCOM6_TWI_SCLSM_MODE      1        // TWI SCL clock stretch mode implemented?
-#define SERCOM6_TWI_SMB_TIMEOUTS    1        // TWI SMBus timeouts implemented?
-#define SERCOM6_TWI_TENBIT_ADR      1        // TWI ten bit enabled?
-#define SERCOM6_USART               1        // USART mode implemented?
-#define SERCOM6_USART_AUTOBAUD      1        // USART autobaud implemented?
-#define SERCOM6_USART_COLDET        1        // USART collision detection implemented?
-#define SERCOM6_USART_FLOW_CTRL     1        // USART flow control implemented?
-#define SERCOM6_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
-#define SERCOM6_USART_IRDA          1        // USART IrDA implemented?
-#define SERCOM6_USART_ISO7816       1        // USART ISO7816 mode implemented?
-#define SERCOM6_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
-#define SERCOM6_USART_RS485         1        // USART RS485 mode implemented?
-#define SERCOM6_USART_SAMPA_EXT     1        // USART sample adjust implemented?
-#define SERCOM6_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
-
-#endif /* _SAMD51_SERCOM6_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom7.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom7.h
deleted file mode 100644
index 22bccde20d..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/sercom7.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SERCOM7
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SERCOM7_INSTANCE_
-#define _SAMD51_SERCOM7_INSTANCE_
-
-/* ========== Register definition for SERCOM7 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SERCOM7_I2CM_CTRLA     (0x43000C00) /**< \brief (SERCOM7) I2CM Control A */
-#define REG_SERCOM7_I2CM_CTRLB     (0x43000C04) /**< \brief (SERCOM7) I2CM Control B */
-#define REG_SERCOM7_I2CM_CTRLC     (0x43000C08) /**< \brief (SERCOM7) I2CM Control C */
-#define REG_SERCOM7_I2CM_BAUD      (0x43000C0C) /**< \brief (SERCOM7) I2CM Baud Rate */
-#define REG_SERCOM7_I2CM_INTENCLR  (0x43000C14) /**< \brief (SERCOM7) I2CM Interrupt Enable Clear */
-#define REG_SERCOM7_I2CM_INTENSET  (0x43000C16) /**< \brief (SERCOM7) I2CM Interrupt Enable Set */
-#define REG_SERCOM7_I2CM_INTFLAG   (0x43000C18) /**< \brief (SERCOM7) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM7_I2CM_STATUS    (0x43000C1A) /**< \brief (SERCOM7) I2CM Status */
-#define REG_SERCOM7_I2CM_SYNCBUSY  (0x43000C1C) /**< \brief (SERCOM7) I2CM Synchronization Busy */
-#define REG_SERCOM7_I2CM_ADDR      (0x43000C24) /**< \brief (SERCOM7) I2CM Address */
-#define REG_SERCOM7_I2CM_DATA      (0x43000C28) /**< \brief (SERCOM7) I2CM Data */
-#define REG_SERCOM7_I2CM_DBGCTRL   (0x43000C30) /**< \brief (SERCOM7) I2CM Debug Control */
-#define REG_SERCOM7_I2CS_CTRLA     (0x43000C00) /**< \brief (SERCOM7) I2CS Control A */
-#define REG_SERCOM7_I2CS_CTRLB     (0x43000C04) /**< \brief (SERCOM7) I2CS Control B */
-#define REG_SERCOM7_I2CS_CTRLC     (0x43000C08) /**< \brief (SERCOM7) I2CS Control C */
-#define REG_SERCOM7_I2CS_INTENCLR  (0x43000C14) /**< \brief (SERCOM7) I2CS Interrupt Enable Clear */
-#define REG_SERCOM7_I2CS_INTENSET  (0x43000C16) /**< \brief (SERCOM7) I2CS Interrupt Enable Set */
-#define REG_SERCOM7_I2CS_INTFLAG   (0x43000C18) /**< \brief (SERCOM7) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM7_I2CS_STATUS    (0x43000C1A) /**< \brief (SERCOM7) I2CS Status */
-#define REG_SERCOM7_I2CS_SYNCBUSY  (0x43000C1C) /**< \brief (SERCOM7) I2CS Synchronization Busy */
-#define REG_SERCOM7_I2CS_LENGTH    (0x43000C22) /**< \brief (SERCOM7) I2CS Length */
-#define REG_SERCOM7_I2CS_ADDR      (0x43000C24) /**< \brief (SERCOM7) I2CS Address */
-#define REG_SERCOM7_I2CS_DATA      (0x43000C28) /**< \brief (SERCOM7) I2CS Data */
-#define REG_SERCOM7_SPI_CTRLA      (0x43000C00) /**< \brief (SERCOM7) SPI Control A */
-#define REG_SERCOM7_SPI_CTRLB      (0x43000C04) /**< \brief (SERCOM7) SPI Control B */
-#define REG_SERCOM7_SPI_CTRLC      (0x43000C08) /**< \brief (SERCOM7) SPI Control C */
-#define REG_SERCOM7_SPI_BAUD       (0x43000C0C) /**< \brief (SERCOM7) SPI Baud Rate */
-#define REG_SERCOM7_SPI_INTENCLR   (0x43000C14) /**< \brief (SERCOM7) SPI Interrupt Enable Clear */
-#define REG_SERCOM7_SPI_INTENSET   (0x43000C16) /**< \brief (SERCOM7) SPI Interrupt Enable Set */
-#define REG_SERCOM7_SPI_INTFLAG    (0x43000C18) /**< \brief (SERCOM7) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM7_SPI_STATUS     (0x43000C1A) /**< \brief (SERCOM7) SPI Status */
-#define REG_SERCOM7_SPI_SYNCBUSY   (0x43000C1C) /**< \brief (SERCOM7) SPI Synchronization Busy */
-#define REG_SERCOM7_SPI_LENGTH     (0x43000C22) /**< \brief (SERCOM7) SPI Length */
-#define REG_SERCOM7_SPI_ADDR       (0x43000C24) /**< \brief (SERCOM7) SPI Address */
-#define REG_SERCOM7_SPI_DATA       (0x43000C28) /**< \brief (SERCOM7) SPI Data */
-#define REG_SERCOM7_SPI_DBGCTRL    (0x43000C30) /**< \brief (SERCOM7) SPI Debug Control */
-#define REG_SERCOM7_USART_CTRLA    (0x43000C00) /**< \brief (SERCOM7) USART Control A */
-#define REG_SERCOM7_USART_CTRLB    (0x43000C04) /**< \brief (SERCOM7) USART Control B */
-#define REG_SERCOM7_USART_CTRLC    (0x43000C08) /**< \brief (SERCOM7) USART Control C */
-#define REG_SERCOM7_USART_BAUD     (0x43000C0C) /**< \brief (SERCOM7) USART Baud Rate */
-#define REG_SERCOM7_USART_RXPL     (0x43000C0E) /**< \brief (SERCOM7) USART Receive Pulse Length */
-#define REG_SERCOM7_USART_INTENCLR (0x43000C14) /**< \brief (SERCOM7) USART Interrupt Enable Clear */
-#define REG_SERCOM7_USART_INTENSET (0x43000C16) /**< \brief (SERCOM7) USART Interrupt Enable Set */
-#define REG_SERCOM7_USART_INTFLAG  (0x43000C18) /**< \brief (SERCOM7) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM7_USART_STATUS   (0x43000C1A) /**< \brief (SERCOM7) USART Status */
-#define REG_SERCOM7_USART_SYNCBUSY (0x43000C1C) /**< \brief (SERCOM7) USART Synchronization Busy */
-#define REG_SERCOM7_USART_RXERRCNT (0x43000C20) /**< \brief (SERCOM7) USART Receive Error Count */
-#define REG_SERCOM7_USART_LENGTH   (0x43000C22) /**< \brief (SERCOM7) USART Length */
-#define REG_SERCOM7_USART_DATA     (0x43000C28) /**< \brief (SERCOM7) USART Data */
-#define REG_SERCOM7_USART_DBGCTRL  (0x43000C30) /**< \brief (SERCOM7) USART Debug Control */
-#else
-#define REG_SERCOM7_I2CM_CTRLA     (*(RwReg  *)0x43000C00UL) /**< \brief (SERCOM7) I2CM Control A */
-#define REG_SERCOM7_I2CM_CTRLB     (*(RwReg  *)0x43000C04UL) /**< \brief (SERCOM7) I2CM Control B */
-#define REG_SERCOM7_I2CM_CTRLC     (*(RwReg  *)0x43000C08UL) /**< \brief (SERCOM7) I2CM Control C */
-#define REG_SERCOM7_I2CM_BAUD      (*(RwReg  *)0x43000C0CUL) /**< \brief (SERCOM7) I2CM Baud Rate */
-#define REG_SERCOM7_I2CM_INTENCLR  (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) I2CM Interrupt Enable Clear */
-#define REG_SERCOM7_I2CM_INTENSET  (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) I2CM Interrupt Enable Set */
-#define REG_SERCOM7_I2CM_INTFLAG   (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) I2CM Interrupt Flag Status and Clear */
-#define REG_SERCOM7_I2CM_STATUS    (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) I2CM Status */
-#define REG_SERCOM7_I2CM_SYNCBUSY  (*(RoReg  *)0x43000C1CUL) /**< \brief (SERCOM7) I2CM Synchronization Busy */
-#define REG_SERCOM7_I2CM_ADDR      (*(RwReg  *)0x43000C24UL) /**< \brief (SERCOM7) I2CM Address */
-#define REG_SERCOM7_I2CM_DATA      (*(RwReg  *)0x43000C28UL) /**< \brief (SERCOM7) I2CM Data */
-#define REG_SERCOM7_I2CM_DBGCTRL   (*(RwReg8 *)0x43000C30UL) /**< \brief (SERCOM7) I2CM Debug Control */
-#define REG_SERCOM7_I2CS_CTRLA     (*(RwReg  *)0x43000C00UL) /**< \brief (SERCOM7) I2CS Control A */
-#define REG_SERCOM7_I2CS_CTRLB     (*(RwReg  *)0x43000C04UL) /**< \brief (SERCOM7) I2CS Control B */
-#define REG_SERCOM7_I2CS_CTRLC     (*(RwReg  *)0x43000C08UL) /**< \brief (SERCOM7) I2CS Control C */
-#define REG_SERCOM7_I2CS_INTENCLR  (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) I2CS Interrupt Enable Clear */
-#define REG_SERCOM7_I2CS_INTENSET  (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) I2CS Interrupt Enable Set */
-#define REG_SERCOM7_I2CS_INTFLAG   (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) I2CS Interrupt Flag Status and Clear */
-#define REG_SERCOM7_I2CS_STATUS    (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) I2CS Status */
-#define REG_SERCOM7_I2CS_SYNCBUSY  (*(RoReg  *)0x43000C1CUL) /**< \brief (SERCOM7) I2CS Synchronization Busy */
-#define REG_SERCOM7_I2CS_LENGTH    (*(RwReg16*)0x43000C22UL) /**< \brief (SERCOM7) I2CS Length */
-#define REG_SERCOM7_I2CS_ADDR      (*(RwReg  *)0x43000C24UL) /**< \brief (SERCOM7) I2CS Address */
-#define REG_SERCOM7_I2CS_DATA      (*(RwReg  *)0x43000C28UL) /**< \brief (SERCOM7) I2CS Data */
-#define REG_SERCOM7_SPI_CTRLA      (*(RwReg  *)0x43000C00UL) /**< \brief (SERCOM7) SPI Control A */
-#define REG_SERCOM7_SPI_CTRLB      (*(RwReg  *)0x43000C04UL) /**< \brief (SERCOM7) SPI Control B */
-#define REG_SERCOM7_SPI_CTRLC      (*(RwReg  *)0x43000C08UL) /**< \brief (SERCOM7) SPI Control C */
-#define REG_SERCOM7_SPI_BAUD       (*(RwReg8 *)0x43000C0CUL) /**< \brief (SERCOM7) SPI Baud Rate */
-#define REG_SERCOM7_SPI_INTENCLR   (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) SPI Interrupt Enable Clear */
-#define REG_SERCOM7_SPI_INTENSET   (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) SPI Interrupt Enable Set */
-#define REG_SERCOM7_SPI_INTFLAG    (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) SPI Interrupt Flag Status and Clear */
-#define REG_SERCOM7_SPI_STATUS     (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) SPI Status */
-#define REG_SERCOM7_SPI_SYNCBUSY   (*(RoReg  *)0x43000C1CUL) /**< \brief (SERCOM7) SPI Synchronization Busy */
-#define REG_SERCOM7_SPI_LENGTH     (*(RwReg16*)0x43000C22UL) /**< \brief (SERCOM7) SPI Length */
-#define REG_SERCOM7_SPI_ADDR       (*(RwReg  *)0x43000C24UL) /**< \brief (SERCOM7) SPI Address */
-#define REG_SERCOM7_SPI_DATA       (*(RwReg  *)0x43000C28UL) /**< \brief (SERCOM7) SPI Data */
-#define REG_SERCOM7_SPI_DBGCTRL    (*(RwReg8 *)0x43000C30UL) /**< \brief (SERCOM7) SPI Debug Control */
-#define REG_SERCOM7_USART_CTRLA    (*(RwReg  *)0x43000C00UL) /**< \brief (SERCOM7) USART Control A */
-#define REG_SERCOM7_USART_CTRLB    (*(RwReg  *)0x43000C04UL) /**< \brief (SERCOM7) USART Control B */
-#define REG_SERCOM7_USART_CTRLC    (*(RwReg  *)0x43000C08UL) /**< \brief (SERCOM7) USART Control C */
-#define REG_SERCOM7_USART_BAUD     (*(RwReg16*)0x43000C0CUL) /**< \brief (SERCOM7) USART Baud Rate */
-#define REG_SERCOM7_USART_RXPL     (*(RwReg8 *)0x43000C0EUL) /**< \brief (SERCOM7) USART Receive Pulse Length */
-#define REG_SERCOM7_USART_INTENCLR (*(RwReg8 *)0x43000C14UL) /**< \brief (SERCOM7) USART Interrupt Enable Clear */
-#define REG_SERCOM7_USART_INTENSET (*(RwReg8 *)0x43000C16UL) /**< \brief (SERCOM7) USART Interrupt Enable Set */
-#define REG_SERCOM7_USART_INTFLAG  (*(RwReg8 *)0x43000C18UL) /**< \brief (SERCOM7) USART Interrupt Flag Status and Clear */
-#define REG_SERCOM7_USART_STATUS   (*(RwReg16*)0x43000C1AUL) /**< \brief (SERCOM7) USART Status */
-#define REG_SERCOM7_USART_SYNCBUSY (*(RoReg  *)0x43000C1CUL) /**< \brief (SERCOM7) USART Synchronization Busy */
-#define REG_SERCOM7_USART_RXERRCNT (*(RoReg8 *)0x43000C20UL) /**< \brief (SERCOM7) USART Receive Error Count */
-#define REG_SERCOM7_USART_LENGTH   (*(RwReg16*)0x43000C22UL) /**< \brief (SERCOM7) USART Length */
-#define REG_SERCOM7_USART_DATA     (*(RwReg  *)0x43000C28UL) /**< \brief (SERCOM7) USART Data */
-#define REG_SERCOM7_USART_DBGCTRL  (*(RwReg8 *)0x43000C30UL) /**< \brief (SERCOM7) USART Debug Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SERCOM7 peripheral ========== */
-#define SERCOM7_CLK_REDUCTION       1        // Reduce clock options to pin 1 for SPI and USART
-#define SERCOM7_DLY_COMPENSATION    1        // Compensates for a fast DLY50 element. Assuming 20ns
-#define SERCOM7_DMA                 1        // DMA support implemented?
-#define SERCOM7_DMAC_ID_RX          18       // Index of DMA RX trigger
-#define SERCOM7_DMAC_ID_TX          19       // Index of DMA TX trigger
-#define SERCOM7_FIFO_DEPTH_POWER    1        // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
-#define SERCOM7_GCLK_ID_CORE        37      
-#define SERCOM7_GCLK_ID_SLOW        3       
-#define SERCOM7_INT_MSB             6       
-#define SERCOM7_PMSB                3       
-#define SERCOM7_RETENTION_SUPPORT   0        // Retention supported?
-#define SERCOM7_SE_CNT              1        // SE counter included?
-#define SERCOM7_SPI                 1        // SPI mode implemented?
-#define SERCOM7_SPI_HW_SS_CTRL      1        // Master _SS hardware control implemented?
-#define SERCOM7_SPI_ICSPACE_EXT     1        // SPI inter character space implemented?
-#define SERCOM7_SPI_OZMO            0        // OZMO features implemented?
-#define SERCOM7_SPI_WAKE_ON_SSL     1        // _SS low detect implemented?
-#define SERCOM7_TTBIT_EXTENSION     1        // 32-bit extension implemented?
-#define SERCOM7_TWIM                1        // TWI Master mode implemented?
-#define SERCOM7_TWIS                1        // TWI Slave mode implemented?
-#define SERCOM7_TWIS_AUTO_ACK       1        // TWI slave automatic acknowledge implemented?
-#define SERCOM7_TWIS_GROUP_CMD      1        // TWI slave group command implemented?
-#define SERCOM7_TWIS_SDASETUP_CNT_SIZE 8        // TWIS sda setup count size
-#define SERCOM7_TWIS_SDASETUP_SIZE  4        // TWIS sda setup size
-#define SERCOM7_TWIS_SUDAT          1        // TWI slave SDA setup implemented?
-#define SERCOM7_TWI_FASTMP          1        // TWI fast mode plus implemented?
-#define SERCOM7_TWI_HSMODE          1        // USART mode implemented?
-#define SERCOM7_TWI_SCLSM_MODE      1        // TWI SCL clock stretch mode implemented?
-#define SERCOM7_TWI_SMB_TIMEOUTS    1        // TWI SMBus timeouts implemented?
-#define SERCOM7_TWI_TENBIT_ADR      1        // TWI ten bit enabled?
-#define SERCOM7_USART               1        // USART mode implemented?
-#define SERCOM7_USART_AUTOBAUD      1        // USART autobaud implemented?
-#define SERCOM7_USART_COLDET        1        // USART collision detection implemented?
-#define SERCOM7_USART_FLOW_CTRL     1        // USART flow control implemented?
-#define SERCOM7_USART_FRAC_BAUD     1        // USART fractional BAUD implemented?
-#define SERCOM7_USART_IRDA          1        // USART IrDA implemented?
-#define SERCOM7_USART_ISO7816       1        // USART ISO7816 mode implemented?
-#define SERCOM7_USART_LIN_MASTER    1        // USART LIN Master mode implemented?
-#define SERCOM7_USART_RS485         1        // USART RS485 mode implemented?
-#define SERCOM7_USART_SAMPA_EXT     1        // USART sample adjust implemented?
-#define SERCOM7_USART_SAMPR_EXT     1        // USART oversampling adjustment implemented?
-
-#endif /* _SAMD51_SERCOM7_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/supc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/supc.h
deleted file mode 100644
index 495c6a3995..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/supc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for SUPC
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_SUPC_INSTANCE_
-#define _SAMD51_SUPC_INSTANCE_
-
-/* ========== Register definition for SUPC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_SUPC_INTENCLR          (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */
-#define REG_SUPC_INTENSET          (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */
-#define REG_SUPC_INTFLAG           (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */
-#define REG_SUPC_STATUS            (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */
-#define REG_SUPC_BOD33             (0x40001810) /**< \brief (SUPC) BOD33 Control */
-#define REG_SUPC_BOD12             (0x40001814) /**< \brief (SUPC) BOD12 Control */
-#define REG_SUPC_VREG              (0x40001818) /**< \brief (SUPC) VREG Control */
-#define REG_SUPC_VREF              (0x4000181C) /**< \brief (SUPC) VREF Control */
-#define REG_SUPC_BBPS              (0x40001820) /**< \brief (SUPC) Battery Backup Power Switch */
-#define REG_SUPC_BKOUT             (0x40001824) /**< \brief (SUPC) Backup Output Control */
-#define REG_SUPC_BKIN              (0x40001828) /**< \brief (SUPC) Backup Input Control */
-#else
-#define REG_SUPC_INTENCLR          (*(RwReg  *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */
-#define REG_SUPC_INTENSET          (*(RwReg  *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */
-#define REG_SUPC_INTFLAG           (*(RwReg  *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */
-#define REG_SUPC_STATUS            (*(RoReg  *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */
-#define REG_SUPC_BOD33             (*(RwReg  *)0x40001810UL) /**< \brief (SUPC) BOD33 Control */
-#define REG_SUPC_BOD12             (*(RwReg  *)0x40001814UL) /**< \brief (SUPC) BOD12 Control */
-#define REG_SUPC_VREG              (*(RwReg  *)0x40001818UL) /**< \brief (SUPC) VREG Control */
-#define REG_SUPC_VREF              (*(RwReg  *)0x4000181CUL) /**< \brief (SUPC) VREF Control */
-#define REG_SUPC_BBPS              (*(RwReg  *)0x40001820UL) /**< \brief (SUPC) Battery Backup Power Switch */
-#define REG_SUPC_BKOUT             (*(RwReg  *)0x40001824UL) /**< \brief (SUPC) Backup Output Control */
-#define REG_SUPC_BKIN              (*(RoReg  *)0x40001828UL) /**< \brief (SUPC) Backup Input Control */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for SUPC peripheral ========== */
-#define SUPC_BOD12_CALIB_MSB        5       
-#define SUPC_BOD33_CALIB_MSB        5       
-
-#endif /* _SAMD51_SUPC_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tal.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tal.h
deleted file mode 100644
index 9facace8e0..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tal.h
+++ /dev/null
@@ -1,541 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TAL
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TAL_INSTANCE_
-#define _SAMD51_TAL_INSTANCE_
-
-/* ========== Register definition for TAL peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TAL_CTRLA              (0x4101E000) /**< \brief (TAL) Control A */
-#define REG_TAL_EXTCTRL            (0x4101E001) /**< \brief (TAL) External Break Control */
-#define REG_TAL_EVCTRL             (0x4101E004) /**< \brief (TAL) Event Control */
-#define REG_TAL_INTENCLR           (0x4101E008) /**< \brief (TAL) Interrupt Enable Clear */
-#define REG_TAL_INTENSET           (0x4101E009) /**< \brief (TAL) Interrupt Enable Set */
-#define REG_TAL_INTFLAG            (0x4101E00A) /**< \brief (TAL) Interrupt Flag Status and Clear */
-#define REG_TAL_GLOBMASK           (0x4101E00B) /**< \brief (TAL) Global Break Requests Mask */
-#define REG_TAL_HALT               (0x4101E00C) /**< \brief (TAL) Debug Halt Request */
-#define REG_TAL_RESTART            (0x4101E00D) /**< \brief (TAL) Debug Restart Request */
-#define REG_TAL_BRKSTATUS          (0x4101E00E) /**< \brief (TAL) Break Request Status */
-#define REG_TAL_CTICTRLA0          (0x4101E010) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */
-#define REG_TAL_CTIMASK0           (0x4101E011) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */
-#define REG_TAL_CTICTRLA1          (0x4101E012) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */
-#define REG_TAL_CTIMASK1           (0x4101E013) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */
-#define REG_TAL_CTICTRLA2          (0x4101E014) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */
-#define REG_TAL_CTIMASK2           (0x4101E015) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */
-#define REG_TAL_CTICTRLA3          (0x4101E016) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */
-#define REG_TAL_CTIMASK3           (0x4101E017) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */
-#define REG_TAL_INTSTATUS0         (0x4101E020) /**< \brief (TAL) Interrupt 0 Status */
-#define REG_TAL_INTSTATUS1         (0x4101E021) /**< \brief (TAL) Interrupt 1 Status */
-#define REG_TAL_INTSTATUS2         (0x4101E022) /**< \brief (TAL) Interrupt 2 Status */
-#define REG_TAL_INTSTATUS3         (0x4101E023) /**< \brief (TAL) Interrupt 3 Status */
-#define REG_TAL_INTSTATUS4         (0x4101E024) /**< \brief (TAL) Interrupt 4 Status */
-#define REG_TAL_INTSTATUS5         (0x4101E025) /**< \brief (TAL) Interrupt 5 Status */
-#define REG_TAL_INTSTATUS6         (0x4101E026) /**< \brief (TAL) Interrupt 6 Status */
-#define REG_TAL_INTSTATUS7         (0x4101E027) /**< \brief (TAL) Interrupt 7 Status */
-#define REG_TAL_INTSTATUS8         (0x4101E028) /**< \brief (TAL) Interrupt 8 Status */
-#define REG_TAL_INTSTATUS9         (0x4101E029) /**< \brief (TAL) Interrupt 9 Status */
-#define REG_TAL_INTSTATUS10        (0x4101E02A) /**< \brief (TAL) Interrupt 10 Status */
-#define REG_TAL_INTSTATUS11        (0x4101E02B) /**< \brief (TAL) Interrupt 11 Status */
-#define REG_TAL_INTSTATUS12        (0x4101E02C) /**< \brief (TAL) Interrupt 12 Status */
-#define REG_TAL_INTSTATUS13        (0x4101E02D) /**< \brief (TAL) Interrupt 13 Status */
-#define REG_TAL_INTSTATUS14        (0x4101E02E) /**< \brief (TAL) Interrupt 14 Status */
-#define REG_TAL_INTSTATUS15        (0x4101E02F) /**< \brief (TAL) Interrupt 15 Status */
-#define REG_TAL_INTSTATUS16        (0x4101E030) /**< \brief (TAL) Interrupt 16 Status */
-#define REG_TAL_INTSTATUS17        (0x4101E031) /**< \brief (TAL) Interrupt 17 Status */
-#define REG_TAL_INTSTATUS18        (0x4101E032) /**< \brief (TAL) Interrupt 18 Status */
-#define REG_TAL_INTSTATUS19        (0x4101E033) /**< \brief (TAL) Interrupt 19 Status */
-#define REG_TAL_INTSTATUS20        (0x4101E034) /**< \brief (TAL) Interrupt 20 Status */
-#define REG_TAL_INTSTATUS21        (0x4101E035) /**< \brief (TAL) Interrupt 21 Status */
-#define REG_TAL_INTSTATUS22        (0x4101E036) /**< \brief (TAL) Interrupt 22 Status */
-#define REG_TAL_INTSTATUS23        (0x4101E037) /**< \brief (TAL) Interrupt 23 Status */
-#define REG_TAL_INTSTATUS24        (0x4101E038) /**< \brief (TAL) Interrupt 24 Status */
-#define REG_TAL_INTSTATUS25        (0x4101E039) /**< \brief (TAL) Interrupt 25 Status */
-#define REG_TAL_INTSTATUS26        (0x4101E03A) /**< \brief (TAL) Interrupt 26 Status */
-#define REG_TAL_INTSTATUS27        (0x4101E03B) /**< \brief (TAL) Interrupt 27 Status */
-#define REG_TAL_INTSTATUS28        (0x4101E03C) /**< \brief (TAL) Interrupt 28 Status */
-#define REG_TAL_INTSTATUS29        (0x4101E03D) /**< \brief (TAL) Interrupt 29 Status */
-#define REG_TAL_INTSTATUS30        (0x4101E03E) /**< \brief (TAL) Interrupt 30 Status */
-#define REG_TAL_INTSTATUS31        (0x4101E03F) /**< \brief (TAL) Interrupt 31 Status */
-#define REG_TAL_INTSTATUS32        (0x4101E040) /**< \brief (TAL) Interrupt 32 Status */
-#define REG_TAL_INTSTATUS33        (0x4101E041) /**< \brief (TAL) Interrupt 33 Status */
-#define REG_TAL_INTSTATUS34        (0x4101E042) /**< \brief (TAL) Interrupt 34 Status */
-#define REG_TAL_INTSTATUS35        (0x4101E043) /**< \brief (TAL) Interrupt 35 Status */
-#define REG_TAL_INTSTATUS36        (0x4101E044) /**< \brief (TAL) Interrupt 36 Status */
-#define REG_TAL_INTSTATUS37        (0x4101E045) /**< \brief (TAL) Interrupt 37 Status */
-#define REG_TAL_INTSTATUS38        (0x4101E046) /**< \brief (TAL) Interrupt 38 Status */
-#define REG_TAL_INTSTATUS39        (0x4101E047) /**< \brief (TAL) Interrupt 39 Status */
-#define REG_TAL_INTSTATUS40        (0x4101E048) /**< \brief (TAL) Interrupt 40 Status */
-#define REG_TAL_INTSTATUS41        (0x4101E049) /**< \brief (TAL) Interrupt 41 Status */
-#define REG_TAL_INTSTATUS42        (0x4101E04A) /**< \brief (TAL) Interrupt 42 Status */
-#define REG_TAL_INTSTATUS43        (0x4101E04B) /**< \brief (TAL) Interrupt 43 Status */
-#define REG_TAL_INTSTATUS44        (0x4101E04C) /**< \brief (TAL) Interrupt 44 Status */
-#define REG_TAL_INTSTATUS45        (0x4101E04D) /**< \brief (TAL) Interrupt 45 Status */
-#define REG_TAL_INTSTATUS46        (0x4101E04E) /**< \brief (TAL) Interrupt 46 Status */
-#define REG_TAL_INTSTATUS47        (0x4101E04F) /**< \brief (TAL) Interrupt 47 Status */
-#define REG_TAL_INTSTATUS48        (0x4101E050) /**< \brief (TAL) Interrupt 48 Status */
-#define REG_TAL_INTSTATUS49        (0x4101E051) /**< \brief (TAL) Interrupt 49 Status */
-#define REG_TAL_INTSTATUS50        (0x4101E052) /**< \brief (TAL) Interrupt 50 Status */
-#define REG_TAL_INTSTATUS51        (0x4101E053) /**< \brief (TAL) Interrupt 51 Status */
-#define REG_TAL_INTSTATUS52        (0x4101E054) /**< \brief (TAL) Interrupt 52 Status */
-#define REG_TAL_INTSTATUS53        (0x4101E055) /**< \brief (TAL) Interrupt 53 Status */
-#define REG_TAL_INTSTATUS54        (0x4101E056) /**< \brief (TAL) Interrupt 54 Status */
-#define REG_TAL_INTSTATUS55        (0x4101E057) /**< \brief (TAL) Interrupt 55 Status */
-#define REG_TAL_INTSTATUS56        (0x4101E058) /**< \brief (TAL) Interrupt 56 Status */
-#define REG_TAL_INTSTATUS57        (0x4101E059) /**< \brief (TAL) Interrupt 57 Status */
-#define REG_TAL_INTSTATUS58        (0x4101E05A) /**< \brief (TAL) Interrupt 58 Status */
-#define REG_TAL_INTSTATUS59        (0x4101E05B) /**< \brief (TAL) Interrupt 59 Status */
-#define REG_TAL_INTSTATUS60        (0x4101E05C) /**< \brief (TAL) Interrupt 60 Status */
-#define REG_TAL_INTSTATUS61        (0x4101E05D) /**< \brief (TAL) Interrupt 61 Status */
-#define REG_TAL_INTSTATUS62        (0x4101E05E) /**< \brief (TAL) Interrupt 62 Status */
-#define REG_TAL_INTSTATUS63        (0x4101E05F) /**< \brief (TAL) Interrupt 63 Status */
-#define REG_TAL_INTSTATUS64        (0x4101E060) /**< \brief (TAL) Interrupt 64 Status */
-#define REG_TAL_INTSTATUS65        (0x4101E061) /**< \brief (TAL) Interrupt 65 Status */
-#define REG_TAL_INTSTATUS66        (0x4101E062) /**< \brief (TAL) Interrupt 66 Status */
-#define REG_TAL_INTSTATUS67        (0x4101E063) /**< \brief (TAL) Interrupt 67 Status */
-#define REG_TAL_INTSTATUS68        (0x4101E064) /**< \brief (TAL) Interrupt 68 Status */
-#define REG_TAL_INTSTATUS69        (0x4101E065) /**< \brief (TAL) Interrupt 69 Status */
-#define REG_TAL_INTSTATUS70        (0x4101E066) /**< \brief (TAL) Interrupt 70 Status */
-#define REG_TAL_INTSTATUS71        (0x4101E067) /**< \brief (TAL) Interrupt 71 Status */
-#define REG_TAL_INTSTATUS72        (0x4101E068) /**< \brief (TAL) Interrupt 72 Status */
-#define REG_TAL_INTSTATUS73        (0x4101E069) /**< \brief (TAL) Interrupt 73 Status */
-#define REG_TAL_INTSTATUS74        (0x4101E06A) /**< \brief (TAL) Interrupt 74 Status */
-#define REG_TAL_INTSTATUS75        (0x4101E06B) /**< \brief (TAL) Interrupt 75 Status */
-#define REG_TAL_INTSTATUS76        (0x4101E06C) /**< \brief (TAL) Interrupt 76 Status */
-#define REG_TAL_INTSTATUS77        (0x4101E06D) /**< \brief (TAL) Interrupt 77 Status */
-#define REG_TAL_INTSTATUS78        (0x4101E06E) /**< \brief (TAL) Interrupt 78 Status */
-#define REG_TAL_INTSTATUS79        (0x4101E06F) /**< \brief (TAL) Interrupt 79 Status */
-#define REG_TAL_INTSTATUS80        (0x4101E070) /**< \brief (TAL) Interrupt 80 Status */
-#define REG_TAL_INTSTATUS81        (0x4101E071) /**< \brief (TAL) Interrupt 81 Status */
-#define REG_TAL_INTSTATUS82        (0x4101E072) /**< \brief (TAL) Interrupt 82 Status */
-#define REG_TAL_INTSTATUS83        (0x4101E073) /**< \brief (TAL) Interrupt 83 Status */
-#define REG_TAL_INTSTATUS84        (0x4101E074) /**< \brief (TAL) Interrupt 84 Status */
-#define REG_TAL_INTSTATUS85        (0x4101E075) /**< \brief (TAL) Interrupt 85 Status */
-#define REG_TAL_INTSTATUS86        (0x4101E076) /**< \brief (TAL) Interrupt 86 Status */
-#define REG_TAL_INTSTATUS87        (0x4101E077) /**< \brief (TAL) Interrupt 87 Status */
-#define REG_TAL_INTSTATUS88        (0x4101E078) /**< \brief (TAL) Interrupt 88 Status */
-#define REG_TAL_INTSTATUS89        (0x4101E079) /**< \brief (TAL) Interrupt 89 Status */
-#define REG_TAL_INTSTATUS90        (0x4101E07A) /**< \brief (TAL) Interrupt 90 Status */
-#define REG_TAL_INTSTATUS91        (0x4101E07B) /**< \brief (TAL) Interrupt 91 Status */
-#define REG_TAL_INTSTATUS92        (0x4101E07C) /**< \brief (TAL) Interrupt 92 Status */
-#define REG_TAL_INTSTATUS93        (0x4101E07D) /**< \brief (TAL) Interrupt 93 Status */
-#define REG_TAL_INTSTATUS94        (0x4101E07E) /**< \brief (TAL) Interrupt 94 Status */
-#define REG_TAL_INTSTATUS95        (0x4101E07F) /**< \brief (TAL) Interrupt 95 Status */
-#define REG_TAL_INTSTATUS96        (0x4101E080) /**< \brief (TAL) Interrupt 96 Status */
-#define REG_TAL_INTSTATUS97        (0x4101E081) /**< \brief (TAL) Interrupt 97 Status */
-#define REG_TAL_INTSTATUS98        (0x4101E082) /**< \brief (TAL) Interrupt 98 Status */
-#define REG_TAL_INTSTATUS99        (0x4101E083) /**< \brief (TAL) Interrupt 99 Status */
-#define REG_TAL_INTSTATUS100       (0x4101E084) /**< \brief (TAL) Interrupt 100 Status */
-#define REG_TAL_INTSTATUS101       (0x4101E085) /**< \brief (TAL) Interrupt 101 Status */
-#define REG_TAL_INTSTATUS102       (0x4101E086) /**< \brief (TAL) Interrupt 102 Status */
-#define REG_TAL_INTSTATUS103       (0x4101E087) /**< \brief (TAL) Interrupt 103 Status */
-#define REG_TAL_INTSTATUS104       (0x4101E088) /**< \brief (TAL) Interrupt 104 Status */
-#define REG_TAL_INTSTATUS105       (0x4101E089) /**< \brief (TAL) Interrupt 105 Status */
-#define REG_TAL_INTSTATUS106       (0x4101E08A) /**< \brief (TAL) Interrupt 106 Status */
-#define REG_TAL_INTSTATUS107       (0x4101E08B) /**< \brief (TAL) Interrupt 107 Status */
-#define REG_TAL_INTSTATUS108       (0x4101E08C) /**< \brief (TAL) Interrupt 108 Status */
-#define REG_TAL_INTSTATUS109       (0x4101E08D) /**< \brief (TAL) Interrupt 109 Status */
-#define REG_TAL_INTSTATUS110       (0x4101E08E) /**< \brief (TAL) Interrupt 110 Status */
-#define REG_TAL_INTSTATUS111       (0x4101E08F) /**< \brief (TAL) Interrupt 111 Status */
-#define REG_TAL_INTSTATUS112       (0x4101E090) /**< \brief (TAL) Interrupt 112 Status */
-#define REG_TAL_INTSTATUS113       (0x4101E091) /**< \brief (TAL) Interrupt 113 Status */
-#define REG_TAL_INTSTATUS114       (0x4101E092) /**< \brief (TAL) Interrupt 114 Status */
-#define REG_TAL_INTSTATUS115       (0x4101E093) /**< \brief (TAL) Interrupt 115 Status */
-#define REG_TAL_INTSTATUS116       (0x4101E094) /**< \brief (TAL) Interrupt 116 Status */
-#define REG_TAL_INTSTATUS117       (0x4101E095) /**< \brief (TAL) Interrupt 117 Status */
-#define REG_TAL_INTSTATUS118       (0x4101E096) /**< \brief (TAL) Interrupt 118 Status */
-#define REG_TAL_INTSTATUS119       (0x4101E097) /**< \brief (TAL) Interrupt 119 Status */
-#define REG_TAL_INTSTATUS120       (0x4101E098) /**< \brief (TAL) Interrupt 120 Status */
-#define REG_TAL_INTSTATUS121       (0x4101E099) /**< \brief (TAL) Interrupt 121 Status */
-#define REG_TAL_INTSTATUS122       (0x4101E09A) /**< \brief (TAL) Interrupt 122 Status */
-#define REG_TAL_INTSTATUS123       (0x4101E09B) /**< \brief (TAL) Interrupt 123 Status */
-#define REG_TAL_INTSTATUS124       (0x4101E09C) /**< \brief (TAL) Interrupt 124 Status */
-#define REG_TAL_INTSTATUS125       (0x4101E09D) /**< \brief (TAL) Interrupt 125 Status */
-#define REG_TAL_INTSTATUS126       (0x4101E09E) /**< \brief (TAL) Interrupt 126 Status */
-#define REG_TAL_INTSTATUS127       (0x4101E09F) /**< \brief (TAL) Interrupt 127 Status */
-#define REG_TAL_INTSTATUS128       (0x4101E0A0) /**< \brief (TAL) Interrupt 128 Status */
-#define REG_TAL_INTSTATUS129       (0x4101E0A1) /**< \brief (TAL) Interrupt 129 Status */
-#define REG_TAL_INTSTATUS130       (0x4101E0A2) /**< \brief (TAL) Interrupt 130 Status */
-#define REG_TAL_INTSTATUS131       (0x4101E0A3) /**< \brief (TAL) Interrupt 131 Status */
-#define REG_TAL_INTSTATUS132       (0x4101E0A4) /**< \brief (TAL) Interrupt 132 Status */
-#define REG_TAL_INTSTATUS133       (0x4101E0A5) /**< \brief (TAL) Interrupt 133 Status */
-#define REG_TAL_INTSTATUS134       (0x4101E0A6) /**< \brief (TAL) Interrupt 134 Status */
-#define REG_TAL_INTSTATUS135       (0x4101E0A7) /**< \brief (TAL) Interrupt 135 Status */
-#define REG_TAL_INTSTATUS136       (0x4101E0A8) /**< \brief (TAL) Interrupt 136 Status */
-#define REG_TAL_DMACPUSEL0         (0x4101E110) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */
-#define REG_TAL_DMACPUSEL1         (0x4101E114) /**< \brief (TAL) DMA Channel Interrupts CPU Select 1 */
-#define REG_TAL_EVCPUSEL0          (0x4101E118) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */
-#define REG_TAL_EICCPUSEL0         (0x4101E120) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */
-#define REG_TAL_INTCPUSEL0         (0x4101E128) /**< \brief (TAL) Interrupts CPU Select 0 */
-#define REG_TAL_INTCPUSEL1         (0x4101E12C) /**< \brief (TAL) Interrupts CPU Select 1 */
-#define REG_TAL_INTCPUSEL2         (0x4101E130) /**< \brief (TAL) Interrupts CPU Select 2 */
-#define REG_TAL_INTCPUSEL3         (0x4101E134) /**< \brief (TAL) Interrupts CPU Select 3 */
-#define REG_TAL_INTCPUSEL4         (0x4101E138) /**< \brief (TAL) Interrupts CPU Select 4 */
-#define REG_TAL_INTCPUSEL5         (0x4101E13C) /**< \brief (TAL) Interrupts CPU Select 5 */
-#define REG_TAL_INTCPUSEL6         (0x4101E140) /**< \brief (TAL) Interrupts CPU Select 6 */
-#define REG_TAL_INTCPUSEL7         (0x4101E144) /**< \brief (TAL) Interrupts CPU Select 7 */
-#define REG_TAL_INTCPUSEL8         (0x4101E148) /**< \brief (TAL) Interrupts CPU Select 8 */
-#define REG_TAL_IRQTRIG            (0x4101E164) /**< \brief (TAL) Interrupt Trigger */
-#define REG_TAL_IRQMON0            (0x4101E168) /**< \brief (TAL) Interrupt Monitor Select 0 */
-#define REG_TAL_CPUIRQS0           (0x4101E180) /**< \brief (TAL) Interrupt Status m for CPU 0 */
-#define REG_TAL_CPUIRQS1           (0x4101E1A0) /**< \brief (TAL) Interrupt Status m for CPU 1 */
-#define REG_TAL_SMASK0             (0x4101E200) /**< \brief (TAL) Inter-Process Signal Mask m for CPU 0 */
-#define REG_TAL_SMASK1             (0x4101E208) /**< \brief (TAL) Inter-Process Signal Mask m for CPU 1 */
-#define REG_TAL_SFLAGCLR0          (0x4101E220) /**< \brief (TAL) Inter-Process Signal Flag Clear 0 */
-#define REG_TAL_SFLAGCLR1          (0x4101E224) /**< \brief (TAL) Inter-Process Signal Flag Clear 1 */
-#define REG_TAL_SFLAGSET0          (0x4101E228) /**< \brief (TAL) Inter-Process Signal Flag Set 0 */
-#define REG_TAL_SFLAGSET1          (0x4101E22C) /**< \brief (TAL) Inter-Process Signal Flag Set 1 */
-#define REG_TAL_SFLAG0             (0x4101E230) /**< \brief (TAL) Inter-Process Signal Flag 0 */
-#define REG_TAL_SFLAG1             (0x4101E234) /**< \brief (TAL) Inter-Process Signal Flag 1 */
-#define REG_TAL_SFLAGCLRR0         (0x4101E300) /**< \brief (TAL) Inter-Process Signal Flag Bit 0 */
-#define REG_TAL_SFLAGCLRR1         (0x4101E301) /**< \brief (TAL) Inter-Process Signal Flag Bit 1 */
-#define REG_TAL_SFLAGCLRR2         (0x4101E302) /**< \brief (TAL) Inter-Process Signal Flag Bit 2 */
-#define REG_TAL_SFLAGCLRR3         (0x4101E303) /**< \brief (TAL) Inter-Process Signal Flag Bit 3 */
-#define REG_TAL_SFLAGCLRR4         (0x4101E304) /**< \brief (TAL) Inter-Process Signal Flag Bit 4 */
-#define REG_TAL_SFLAGCLRR5         (0x4101E305) /**< \brief (TAL) Inter-Process Signal Flag Bit 5 */
-#define REG_TAL_SFLAGCLRR6         (0x4101E306) /**< \brief (TAL) Inter-Process Signal Flag Bit 6 */
-#define REG_TAL_SFLAGCLRR7         (0x4101E307) /**< \brief (TAL) Inter-Process Signal Flag Bit 7 */
-#define REG_TAL_SFLAGCLRR8         (0x4101E308) /**< \brief (TAL) Inter-Process Signal Flag Bit 8 */
-#define REG_TAL_SFLAGCLRR9         (0x4101E309) /**< \brief (TAL) Inter-Process Signal Flag Bit 9 */
-#define REG_TAL_SFLAGCLRR10        (0x4101E30A) /**< \brief (TAL) Inter-Process Signal Flag Bit 10 */
-#define REG_TAL_SFLAGCLRR11        (0x4101E30B) /**< \brief (TAL) Inter-Process Signal Flag Bit 11 */
-#define REG_TAL_SFLAGCLRR12        (0x4101E30C) /**< \brief (TAL) Inter-Process Signal Flag Bit 12 */
-#define REG_TAL_SFLAGCLRR13        (0x4101E30D) /**< \brief (TAL) Inter-Process Signal Flag Bit 13 */
-#define REG_TAL_SFLAGCLRR14        (0x4101E30E) /**< \brief (TAL) Inter-Process Signal Flag Bit 14 */
-#define REG_TAL_SFLAGCLRR15        (0x4101E30F) /**< \brief (TAL) Inter-Process Signal Flag Bit 15 */
-#define REG_TAL_SFLAGCLRR16        (0x4101E310) /**< \brief (TAL) Inter-Process Signal Flag Bit 16 */
-#define REG_TAL_SFLAGCLRR17        (0x4101E311) /**< \brief (TAL) Inter-Process Signal Flag Bit 17 */
-#define REG_TAL_SFLAGCLRR18        (0x4101E312) /**< \brief (TAL) Inter-Process Signal Flag Bit 18 */
-#define REG_TAL_SFLAGCLRR19        (0x4101E313) /**< \brief (TAL) Inter-Process Signal Flag Bit 19 */
-#define REG_TAL_SFLAGCLRR20        (0x4101E314) /**< \brief (TAL) Inter-Process Signal Flag Bit 20 */
-#define REG_TAL_SFLAGCLRR21        (0x4101E315) /**< \brief (TAL) Inter-Process Signal Flag Bit 21 */
-#define REG_TAL_SFLAGCLRR22        (0x4101E316) /**< \brief (TAL) Inter-Process Signal Flag Bit 22 */
-#define REG_TAL_SFLAGCLRR23        (0x4101E317) /**< \brief (TAL) Inter-Process Signal Flag Bit 23 */
-#define REG_TAL_SFLAGCLRR24        (0x4101E318) /**< \brief (TAL) Inter-Process Signal Flag Bit 24 */
-#define REG_TAL_SFLAGCLRR25        (0x4101E319) /**< \brief (TAL) Inter-Process Signal Flag Bit 25 */
-#define REG_TAL_SFLAGCLRR26        (0x4101E31A) /**< \brief (TAL) Inter-Process Signal Flag Bit 26 */
-#define REG_TAL_SFLAGCLRR27        (0x4101E31B) /**< \brief (TAL) Inter-Process Signal Flag Bit 27 */
-#define REG_TAL_SFLAGCLRR28        (0x4101E31C) /**< \brief (TAL) Inter-Process Signal Flag Bit 28 */
-#define REG_TAL_SFLAGCLRR29        (0x4101E31D) /**< \brief (TAL) Inter-Process Signal Flag Bit 29 */
-#define REG_TAL_SFLAGCLRR30        (0x4101E31E) /**< \brief (TAL) Inter-Process Signal Flag Bit 30 */
-#define REG_TAL_SFLAGCLRR31        (0x4101E31F) /**< \brief (TAL) Inter-Process Signal Flag Bit 31 */
-#define REG_TAL_SFLAGCLRR32        (0x4101E320) /**< \brief (TAL) Inter-Process Signal Flag Bit 32 */
-#define REG_TAL_SFLAGCLRR33        (0x4101E321) /**< \brief (TAL) Inter-Process Signal Flag Bit 33 */
-#define REG_TAL_SFLAGCLRR34        (0x4101E322) /**< \brief (TAL) Inter-Process Signal Flag Bit 34 */
-#define REG_TAL_SFLAGCLRR35        (0x4101E323) /**< \brief (TAL) Inter-Process Signal Flag Bit 35 */
-#define REG_TAL_SFLAGCLRR36        (0x4101E324) /**< \brief (TAL) Inter-Process Signal Flag Bit 36 */
-#define REG_TAL_SFLAGCLRR37        (0x4101E325) /**< \brief (TAL) Inter-Process Signal Flag Bit 37 */
-#define REG_TAL_SFLAGCLRR38        (0x4101E326) /**< \brief (TAL) Inter-Process Signal Flag Bit 38 */
-#define REG_TAL_SFLAGCLRR39        (0x4101E327) /**< \brief (TAL) Inter-Process Signal Flag Bit 39 */
-#define REG_TAL_SFLAGCLRR40        (0x4101E328) /**< \brief (TAL) Inter-Process Signal Flag Bit 40 */
-#define REG_TAL_SFLAGCLRR41        (0x4101E329) /**< \brief (TAL) Inter-Process Signal Flag Bit 41 */
-#define REG_TAL_SFLAGCLRR42        (0x4101E32A) /**< \brief (TAL) Inter-Process Signal Flag Bit 42 */
-#define REG_TAL_SFLAGCLRR43        (0x4101E32B) /**< \brief (TAL) Inter-Process Signal Flag Bit 43 */
-#define REG_TAL_SFLAGCLRR44        (0x4101E32C) /**< \brief (TAL) Inter-Process Signal Flag Bit 44 */
-#define REG_TAL_SFLAGCLRR45        (0x4101E32D) /**< \brief (TAL) Inter-Process Signal Flag Bit 45 */
-#define REG_TAL_SFLAGCLRR46        (0x4101E32E) /**< \brief (TAL) Inter-Process Signal Flag Bit 46 */
-#define REG_TAL_SFLAGCLRR47        (0x4101E32F) /**< \brief (TAL) Inter-Process Signal Flag Bit 47 */
-#define REG_TAL_SFLAGCLRR48        (0x4101E330) /**< \brief (TAL) Inter-Process Signal Flag Bit 48 */
-#define REG_TAL_SFLAGCLRR49        (0x4101E331) /**< \brief (TAL) Inter-Process Signal Flag Bit 49 */
-#define REG_TAL_SFLAGCLRR50        (0x4101E332) /**< \brief (TAL) Inter-Process Signal Flag Bit 50 */
-#define REG_TAL_SFLAGCLRR51        (0x4101E333) /**< \brief (TAL) Inter-Process Signal Flag Bit 51 */
-#define REG_TAL_SFLAGCLRR52        (0x4101E334) /**< \brief (TAL) Inter-Process Signal Flag Bit 52 */
-#define REG_TAL_SFLAGCLRR53        (0x4101E335) /**< \brief (TAL) Inter-Process Signal Flag Bit 53 */
-#define REG_TAL_SFLAGCLRR54        (0x4101E336) /**< \brief (TAL) Inter-Process Signal Flag Bit 54 */
-#define REG_TAL_SFLAGCLRR55        (0x4101E337) /**< \brief (TAL) Inter-Process Signal Flag Bit 55 */
-#define REG_TAL_SFLAGCLRR56        (0x4101E338) /**< \brief (TAL) Inter-Process Signal Flag Bit 56 */
-#define REG_TAL_SFLAGCLRR57        (0x4101E339) /**< \brief (TAL) Inter-Process Signal Flag Bit 57 */
-#define REG_TAL_SFLAGCLRR58        (0x4101E33A) /**< \brief (TAL) Inter-Process Signal Flag Bit 58 */
-#define REG_TAL_SFLAGCLRR59        (0x4101E33B) /**< \brief (TAL) Inter-Process Signal Flag Bit 59 */
-#define REG_TAL_SFLAGCLRR60        (0x4101E33C) /**< \brief (TAL) Inter-Process Signal Flag Bit 60 */
-#define REG_TAL_SFLAGCLRR61        (0x4101E33D) /**< \brief (TAL) Inter-Process Signal Flag Bit 61 */
-#define REG_TAL_SFLAGCLRR62        (0x4101E33E) /**< \brief (TAL) Inter-Process Signal Flag Bit 62 */
-#define REG_TAL_SFLAGCLRR63        (0x4101E33F) /**< \brief (TAL) Inter-Process Signal Flag Bit 63 */
-#else
-#define REG_TAL_CTRLA              (*(RwReg8 *)0x4101E000UL) /**< \brief (TAL) Control A */
-#define REG_TAL_EXTCTRL            (*(RwReg8 *)0x4101E001UL) /**< \brief (TAL) External Break Control */
-#define REG_TAL_EVCTRL             (*(RwReg16*)0x4101E004UL) /**< \brief (TAL) Event Control */
-#define REG_TAL_INTENCLR           (*(RwReg8 *)0x4101E008UL) /**< \brief (TAL) Interrupt Enable Clear */
-#define REG_TAL_INTENSET           (*(RwReg8 *)0x4101E009UL) /**< \brief (TAL) Interrupt Enable Set */
-#define REG_TAL_INTFLAG            (*(RwReg8 *)0x4101E00AUL) /**< \brief (TAL) Interrupt Flag Status and Clear */
-#define REG_TAL_GLOBMASK           (*(RwReg8 *)0x4101E00BUL) /**< \brief (TAL) Global Break Requests Mask */
-#define REG_TAL_HALT               (*(WoReg8 *)0x4101E00CUL) /**< \brief (TAL) Debug Halt Request */
-#define REG_TAL_RESTART            (*(WoReg8 *)0x4101E00DUL) /**< \brief (TAL) Debug Restart Request */
-#define REG_TAL_BRKSTATUS          (*(RoReg16*)0x4101E00EUL) /**< \brief (TAL) Break Request Status */
-#define REG_TAL_CTICTRLA0          (*(RwReg8 *)0x4101E010UL) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */
-#define REG_TAL_CTIMASK0           (*(RwReg8 *)0x4101E011UL) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */
-#define REG_TAL_CTICTRLA1          (*(RwReg8 *)0x4101E012UL) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */
-#define REG_TAL_CTIMASK1           (*(RwReg8 *)0x4101E013UL) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */
-#define REG_TAL_CTICTRLA2          (*(RwReg8 *)0x4101E014UL) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */
-#define REG_TAL_CTIMASK2           (*(RwReg8 *)0x4101E015UL) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */
-#define REG_TAL_CTICTRLA3          (*(RwReg8 *)0x4101E016UL) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */
-#define REG_TAL_CTIMASK3           (*(RwReg8 *)0x4101E017UL) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */
-#define REG_TAL_INTSTATUS0         (*(RoReg8 *)0x4101E020UL) /**< \brief (TAL) Interrupt 0 Status */
-#define REG_TAL_INTSTATUS1         (*(RoReg8 *)0x4101E021UL) /**< \brief (TAL) Interrupt 1 Status */
-#define REG_TAL_INTSTATUS2         (*(RoReg8 *)0x4101E022UL) /**< \brief (TAL) Interrupt 2 Status */
-#define REG_TAL_INTSTATUS3         (*(RoReg8 *)0x4101E023UL) /**< \brief (TAL) Interrupt 3 Status */
-#define REG_TAL_INTSTATUS4         (*(RoReg8 *)0x4101E024UL) /**< \brief (TAL) Interrupt 4 Status */
-#define REG_TAL_INTSTATUS5         (*(RoReg8 *)0x4101E025UL) /**< \brief (TAL) Interrupt 5 Status */
-#define REG_TAL_INTSTATUS6         (*(RoReg8 *)0x4101E026UL) /**< \brief (TAL) Interrupt 6 Status */
-#define REG_TAL_INTSTATUS7         (*(RoReg8 *)0x4101E027UL) /**< \brief (TAL) Interrupt 7 Status */
-#define REG_TAL_INTSTATUS8         (*(RoReg8 *)0x4101E028UL) /**< \brief (TAL) Interrupt 8 Status */
-#define REG_TAL_INTSTATUS9         (*(RoReg8 *)0x4101E029UL) /**< \brief (TAL) Interrupt 9 Status */
-#define REG_TAL_INTSTATUS10        (*(RoReg8 *)0x4101E02AUL) /**< \brief (TAL) Interrupt 10 Status */
-#define REG_TAL_INTSTATUS11        (*(RoReg8 *)0x4101E02BUL) /**< \brief (TAL) Interrupt 11 Status */
-#define REG_TAL_INTSTATUS12        (*(RoReg8 *)0x4101E02CUL) /**< \brief (TAL) Interrupt 12 Status */
-#define REG_TAL_INTSTATUS13        (*(RoReg8 *)0x4101E02DUL) /**< \brief (TAL) Interrupt 13 Status */
-#define REG_TAL_INTSTATUS14        (*(RoReg8 *)0x4101E02EUL) /**< \brief (TAL) Interrupt 14 Status */
-#define REG_TAL_INTSTATUS15        (*(RoReg8 *)0x4101E02FUL) /**< \brief (TAL) Interrupt 15 Status */
-#define REG_TAL_INTSTATUS16        (*(RoReg8 *)0x4101E030UL) /**< \brief (TAL) Interrupt 16 Status */
-#define REG_TAL_INTSTATUS17        (*(RoReg8 *)0x4101E031UL) /**< \brief (TAL) Interrupt 17 Status */
-#define REG_TAL_INTSTATUS18        (*(RoReg8 *)0x4101E032UL) /**< \brief (TAL) Interrupt 18 Status */
-#define REG_TAL_INTSTATUS19        (*(RoReg8 *)0x4101E033UL) /**< \brief (TAL) Interrupt 19 Status */
-#define REG_TAL_INTSTATUS20        (*(RoReg8 *)0x4101E034UL) /**< \brief (TAL) Interrupt 20 Status */
-#define REG_TAL_INTSTATUS21        (*(RoReg8 *)0x4101E035UL) /**< \brief (TAL) Interrupt 21 Status */
-#define REG_TAL_INTSTATUS22        (*(RoReg8 *)0x4101E036UL) /**< \brief (TAL) Interrupt 22 Status */
-#define REG_TAL_INTSTATUS23        (*(RoReg8 *)0x4101E037UL) /**< \brief (TAL) Interrupt 23 Status */
-#define REG_TAL_INTSTATUS24        (*(RoReg8 *)0x4101E038UL) /**< \brief (TAL) Interrupt 24 Status */
-#define REG_TAL_INTSTATUS25        (*(RoReg8 *)0x4101E039UL) /**< \brief (TAL) Interrupt 25 Status */
-#define REG_TAL_INTSTATUS26        (*(RoReg8 *)0x4101E03AUL) /**< \brief (TAL) Interrupt 26 Status */
-#define REG_TAL_INTSTATUS27        (*(RoReg8 *)0x4101E03BUL) /**< \brief (TAL) Interrupt 27 Status */
-#define REG_TAL_INTSTATUS28        (*(RoReg8 *)0x4101E03CUL) /**< \brief (TAL) Interrupt 28 Status */
-#define REG_TAL_INTSTATUS29        (*(RoReg8 *)0x4101E03DUL) /**< \brief (TAL) Interrupt 29 Status */
-#define REG_TAL_INTSTATUS30        (*(RoReg8 *)0x4101E03EUL) /**< \brief (TAL) Interrupt 30 Status */
-#define REG_TAL_INTSTATUS31        (*(RoReg8 *)0x4101E03FUL) /**< \brief (TAL) Interrupt 31 Status */
-#define REG_TAL_INTSTATUS32        (*(RoReg8 *)0x4101E040UL) /**< \brief (TAL) Interrupt 32 Status */
-#define REG_TAL_INTSTATUS33        (*(RoReg8 *)0x4101E041UL) /**< \brief (TAL) Interrupt 33 Status */
-#define REG_TAL_INTSTATUS34        (*(RoReg8 *)0x4101E042UL) /**< \brief (TAL) Interrupt 34 Status */
-#define REG_TAL_INTSTATUS35        (*(RoReg8 *)0x4101E043UL) /**< \brief (TAL) Interrupt 35 Status */
-#define REG_TAL_INTSTATUS36        (*(RoReg8 *)0x4101E044UL) /**< \brief (TAL) Interrupt 36 Status */
-#define REG_TAL_INTSTATUS37        (*(RoReg8 *)0x4101E045UL) /**< \brief (TAL) Interrupt 37 Status */
-#define REG_TAL_INTSTATUS38        (*(RoReg8 *)0x4101E046UL) /**< \brief (TAL) Interrupt 38 Status */
-#define REG_TAL_INTSTATUS39        (*(RoReg8 *)0x4101E047UL) /**< \brief (TAL) Interrupt 39 Status */
-#define REG_TAL_INTSTATUS40        (*(RoReg8 *)0x4101E048UL) /**< \brief (TAL) Interrupt 40 Status */
-#define REG_TAL_INTSTATUS41        (*(RoReg8 *)0x4101E049UL) /**< \brief (TAL) Interrupt 41 Status */
-#define REG_TAL_INTSTATUS42        (*(RoReg8 *)0x4101E04AUL) /**< \brief (TAL) Interrupt 42 Status */
-#define REG_TAL_INTSTATUS43        (*(RoReg8 *)0x4101E04BUL) /**< \brief (TAL) Interrupt 43 Status */
-#define REG_TAL_INTSTATUS44        (*(RoReg8 *)0x4101E04CUL) /**< \brief (TAL) Interrupt 44 Status */
-#define REG_TAL_INTSTATUS45        (*(RoReg8 *)0x4101E04DUL) /**< \brief (TAL) Interrupt 45 Status */
-#define REG_TAL_INTSTATUS46        (*(RoReg8 *)0x4101E04EUL) /**< \brief (TAL) Interrupt 46 Status */
-#define REG_TAL_INTSTATUS47        (*(RoReg8 *)0x4101E04FUL) /**< \brief (TAL) Interrupt 47 Status */
-#define REG_TAL_INTSTATUS48        (*(RoReg8 *)0x4101E050UL) /**< \brief (TAL) Interrupt 48 Status */
-#define REG_TAL_INTSTATUS49        (*(RoReg8 *)0x4101E051UL) /**< \brief (TAL) Interrupt 49 Status */
-#define REG_TAL_INTSTATUS50        (*(RoReg8 *)0x4101E052UL) /**< \brief (TAL) Interrupt 50 Status */
-#define REG_TAL_INTSTATUS51        (*(RoReg8 *)0x4101E053UL) /**< \brief (TAL) Interrupt 51 Status */
-#define REG_TAL_INTSTATUS52        (*(RoReg8 *)0x4101E054UL) /**< \brief (TAL) Interrupt 52 Status */
-#define REG_TAL_INTSTATUS53        (*(RoReg8 *)0x4101E055UL) /**< \brief (TAL) Interrupt 53 Status */
-#define REG_TAL_INTSTATUS54        (*(RoReg8 *)0x4101E056UL) /**< \brief (TAL) Interrupt 54 Status */
-#define REG_TAL_INTSTATUS55        (*(RoReg8 *)0x4101E057UL) /**< \brief (TAL) Interrupt 55 Status */
-#define REG_TAL_INTSTATUS56        (*(RoReg8 *)0x4101E058UL) /**< \brief (TAL) Interrupt 56 Status */
-#define REG_TAL_INTSTATUS57        (*(RoReg8 *)0x4101E059UL) /**< \brief (TAL) Interrupt 57 Status */
-#define REG_TAL_INTSTATUS58        (*(RoReg8 *)0x4101E05AUL) /**< \brief (TAL) Interrupt 58 Status */
-#define REG_TAL_INTSTATUS59        (*(RoReg8 *)0x4101E05BUL) /**< \brief (TAL) Interrupt 59 Status */
-#define REG_TAL_INTSTATUS60        (*(RoReg8 *)0x4101E05CUL) /**< \brief (TAL) Interrupt 60 Status */
-#define REG_TAL_INTSTATUS61        (*(RoReg8 *)0x4101E05DUL) /**< \brief (TAL) Interrupt 61 Status */
-#define REG_TAL_INTSTATUS62        (*(RoReg8 *)0x4101E05EUL) /**< \brief (TAL) Interrupt 62 Status */
-#define REG_TAL_INTSTATUS63        (*(RoReg8 *)0x4101E05FUL) /**< \brief (TAL) Interrupt 63 Status */
-#define REG_TAL_INTSTATUS64        (*(RoReg8 *)0x4101E060UL) /**< \brief (TAL) Interrupt 64 Status */
-#define REG_TAL_INTSTATUS65        (*(RoReg8 *)0x4101E061UL) /**< \brief (TAL) Interrupt 65 Status */
-#define REG_TAL_INTSTATUS66        (*(RoReg8 *)0x4101E062UL) /**< \brief (TAL) Interrupt 66 Status */
-#define REG_TAL_INTSTATUS67        (*(RoReg8 *)0x4101E063UL) /**< \brief (TAL) Interrupt 67 Status */
-#define REG_TAL_INTSTATUS68        (*(RoReg8 *)0x4101E064UL) /**< \brief (TAL) Interrupt 68 Status */
-#define REG_TAL_INTSTATUS69        (*(RoReg8 *)0x4101E065UL) /**< \brief (TAL) Interrupt 69 Status */
-#define REG_TAL_INTSTATUS70        (*(RoReg8 *)0x4101E066UL) /**< \brief (TAL) Interrupt 70 Status */
-#define REG_TAL_INTSTATUS71        (*(RoReg8 *)0x4101E067UL) /**< \brief (TAL) Interrupt 71 Status */
-#define REG_TAL_INTSTATUS72        (*(RoReg8 *)0x4101E068UL) /**< \brief (TAL) Interrupt 72 Status */
-#define REG_TAL_INTSTATUS73        (*(RoReg8 *)0x4101E069UL) /**< \brief (TAL) Interrupt 73 Status */
-#define REG_TAL_INTSTATUS74        (*(RoReg8 *)0x4101E06AUL) /**< \brief (TAL) Interrupt 74 Status */
-#define REG_TAL_INTSTATUS75        (*(RoReg8 *)0x4101E06BUL) /**< \brief (TAL) Interrupt 75 Status */
-#define REG_TAL_INTSTATUS76        (*(RoReg8 *)0x4101E06CUL) /**< \brief (TAL) Interrupt 76 Status */
-#define REG_TAL_INTSTATUS77        (*(RoReg8 *)0x4101E06DUL) /**< \brief (TAL) Interrupt 77 Status */
-#define REG_TAL_INTSTATUS78        (*(RoReg8 *)0x4101E06EUL) /**< \brief (TAL) Interrupt 78 Status */
-#define REG_TAL_INTSTATUS79        (*(RoReg8 *)0x4101E06FUL) /**< \brief (TAL) Interrupt 79 Status */
-#define REG_TAL_INTSTATUS80        (*(RoReg8 *)0x4101E070UL) /**< \brief (TAL) Interrupt 80 Status */
-#define REG_TAL_INTSTATUS81        (*(RoReg8 *)0x4101E071UL) /**< \brief (TAL) Interrupt 81 Status */
-#define REG_TAL_INTSTATUS82        (*(RoReg8 *)0x4101E072UL) /**< \brief (TAL) Interrupt 82 Status */
-#define REG_TAL_INTSTATUS83        (*(RoReg8 *)0x4101E073UL) /**< \brief (TAL) Interrupt 83 Status */
-#define REG_TAL_INTSTATUS84        (*(RoReg8 *)0x4101E074UL) /**< \brief (TAL) Interrupt 84 Status */
-#define REG_TAL_INTSTATUS85        (*(RoReg8 *)0x4101E075UL) /**< \brief (TAL) Interrupt 85 Status */
-#define REG_TAL_INTSTATUS86        (*(RoReg8 *)0x4101E076UL) /**< \brief (TAL) Interrupt 86 Status */
-#define REG_TAL_INTSTATUS87        (*(RoReg8 *)0x4101E077UL) /**< \brief (TAL) Interrupt 87 Status */
-#define REG_TAL_INTSTATUS88        (*(RoReg8 *)0x4101E078UL) /**< \brief (TAL) Interrupt 88 Status */
-#define REG_TAL_INTSTATUS89        (*(RoReg8 *)0x4101E079UL) /**< \brief (TAL) Interrupt 89 Status */
-#define REG_TAL_INTSTATUS90        (*(RoReg8 *)0x4101E07AUL) /**< \brief (TAL) Interrupt 90 Status */
-#define REG_TAL_INTSTATUS91        (*(RoReg8 *)0x4101E07BUL) /**< \brief (TAL) Interrupt 91 Status */
-#define REG_TAL_INTSTATUS92        (*(RoReg8 *)0x4101E07CUL) /**< \brief (TAL) Interrupt 92 Status */
-#define REG_TAL_INTSTATUS93        (*(RoReg8 *)0x4101E07DUL) /**< \brief (TAL) Interrupt 93 Status */
-#define REG_TAL_INTSTATUS94        (*(RoReg8 *)0x4101E07EUL) /**< \brief (TAL) Interrupt 94 Status */
-#define REG_TAL_INTSTATUS95        (*(RoReg8 *)0x4101E07FUL) /**< \brief (TAL) Interrupt 95 Status */
-#define REG_TAL_INTSTATUS96        (*(RoReg8 *)0x4101E080UL) /**< \brief (TAL) Interrupt 96 Status */
-#define REG_TAL_INTSTATUS97        (*(RoReg8 *)0x4101E081UL) /**< \brief (TAL) Interrupt 97 Status */
-#define REG_TAL_INTSTATUS98        (*(RoReg8 *)0x4101E082UL) /**< \brief (TAL) Interrupt 98 Status */
-#define REG_TAL_INTSTATUS99        (*(RoReg8 *)0x4101E083UL) /**< \brief (TAL) Interrupt 99 Status */
-#define REG_TAL_INTSTATUS100       (*(RoReg8 *)0x4101E084UL) /**< \brief (TAL) Interrupt 100 Status */
-#define REG_TAL_INTSTATUS101       (*(RoReg8 *)0x4101E085UL) /**< \brief (TAL) Interrupt 101 Status */
-#define REG_TAL_INTSTATUS102       (*(RoReg8 *)0x4101E086UL) /**< \brief (TAL) Interrupt 102 Status */
-#define REG_TAL_INTSTATUS103       (*(RoReg8 *)0x4101E087UL) /**< \brief (TAL) Interrupt 103 Status */
-#define REG_TAL_INTSTATUS104       (*(RoReg8 *)0x4101E088UL) /**< \brief (TAL) Interrupt 104 Status */
-#define REG_TAL_INTSTATUS105       (*(RoReg8 *)0x4101E089UL) /**< \brief (TAL) Interrupt 105 Status */
-#define REG_TAL_INTSTATUS106       (*(RoReg8 *)0x4101E08AUL) /**< \brief (TAL) Interrupt 106 Status */
-#define REG_TAL_INTSTATUS107       (*(RoReg8 *)0x4101E08BUL) /**< \brief (TAL) Interrupt 107 Status */
-#define REG_TAL_INTSTATUS108       (*(RoReg8 *)0x4101E08CUL) /**< \brief (TAL) Interrupt 108 Status */
-#define REG_TAL_INTSTATUS109       (*(RoReg8 *)0x4101E08DUL) /**< \brief (TAL) Interrupt 109 Status */
-#define REG_TAL_INTSTATUS110       (*(RoReg8 *)0x4101E08EUL) /**< \brief (TAL) Interrupt 110 Status */
-#define REG_TAL_INTSTATUS111       (*(RoReg8 *)0x4101E08FUL) /**< \brief (TAL) Interrupt 111 Status */
-#define REG_TAL_INTSTATUS112       (*(RoReg8 *)0x4101E090UL) /**< \brief (TAL) Interrupt 112 Status */
-#define REG_TAL_INTSTATUS113       (*(RoReg8 *)0x4101E091UL) /**< \brief (TAL) Interrupt 113 Status */
-#define REG_TAL_INTSTATUS114       (*(RoReg8 *)0x4101E092UL) /**< \brief (TAL) Interrupt 114 Status */
-#define REG_TAL_INTSTATUS115       (*(RoReg8 *)0x4101E093UL) /**< \brief (TAL) Interrupt 115 Status */
-#define REG_TAL_INTSTATUS116       (*(RoReg8 *)0x4101E094UL) /**< \brief (TAL) Interrupt 116 Status */
-#define REG_TAL_INTSTATUS117       (*(RoReg8 *)0x4101E095UL) /**< \brief (TAL) Interrupt 117 Status */
-#define REG_TAL_INTSTATUS118       (*(RoReg8 *)0x4101E096UL) /**< \brief (TAL) Interrupt 118 Status */
-#define REG_TAL_INTSTATUS119       (*(RoReg8 *)0x4101E097UL) /**< \brief (TAL) Interrupt 119 Status */
-#define REG_TAL_INTSTATUS120       (*(RoReg8 *)0x4101E098UL) /**< \brief (TAL) Interrupt 120 Status */
-#define REG_TAL_INTSTATUS121       (*(RoReg8 *)0x4101E099UL) /**< \brief (TAL) Interrupt 121 Status */
-#define REG_TAL_INTSTATUS122       (*(RoReg8 *)0x4101E09AUL) /**< \brief (TAL) Interrupt 122 Status */
-#define REG_TAL_INTSTATUS123       (*(RoReg8 *)0x4101E09BUL) /**< \brief (TAL) Interrupt 123 Status */
-#define REG_TAL_INTSTATUS124       (*(RoReg8 *)0x4101E09CUL) /**< \brief (TAL) Interrupt 124 Status */
-#define REG_TAL_INTSTATUS125       (*(RoReg8 *)0x4101E09DUL) /**< \brief (TAL) Interrupt 125 Status */
-#define REG_TAL_INTSTATUS126       (*(RoReg8 *)0x4101E09EUL) /**< \brief (TAL) Interrupt 126 Status */
-#define REG_TAL_INTSTATUS127       (*(RoReg8 *)0x4101E09FUL) /**< \brief (TAL) Interrupt 127 Status */
-#define REG_TAL_INTSTATUS128       (*(RoReg8 *)0x4101E0A0UL) /**< \brief (TAL) Interrupt 128 Status */
-#define REG_TAL_INTSTATUS129       (*(RoReg8 *)0x4101E0A1UL) /**< \brief (TAL) Interrupt 129 Status */
-#define REG_TAL_INTSTATUS130       (*(RoReg8 *)0x4101E0A2UL) /**< \brief (TAL) Interrupt 130 Status */
-#define REG_TAL_INTSTATUS131       (*(RoReg8 *)0x4101E0A3UL) /**< \brief (TAL) Interrupt 131 Status */
-#define REG_TAL_INTSTATUS132       (*(RoReg8 *)0x4101E0A4UL) /**< \brief (TAL) Interrupt 132 Status */
-#define REG_TAL_INTSTATUS133       (*(RoReg8 *)0x4101E0A5UL) /**< \brief (TAL) Interrupt 133 Status */
-#define REG_TAL_INTSTATUS134       (*(RoReg8 *)0x4101E0A6UL) /**< \brief (TAL) Interrupt 134 Status */
-#define REG_TAL_INTSTATUS135       (*(RoReg8 *)0x4101E0A7UL) /**< \brief (TAL) Interrupt 135 Status */
-#define REG_TAL_INTSTATUS136       (*(RoReg8 *)0x4101E0A8UL) /**< \brief (TAL) Interrupt 136 Status */
-#define REG_TAL_DMACPUSEL0         (*(RwReg  *)0x4101E110UL) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */
-#define REG_TAL_DMACPUSEL1         (*(RwReg  *)0x4101E114UL) /**< \brief (TAL) DMA Channel Interrupts CPU Select 1 */
-#define REG_TAL_EVCPUSEL0          (*(RwReg  *)0x4101E118UL) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */
-#define REG_TAL_EICCPUSEL0         (*(RwReg  *)0x4101E120UL) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */
-#define REG_TAL_INTCPUSEL0         (*(RwReg  *)0x4101E128UL) /**< \brief (TAL) Interrupts CPU Select 0 */
-#define REG_TAL_INTCPUSEL1         (*(RwReg  *)0x4101E12CUL) /**< \brief (TAL) Interrupts CPU Select 1 */
-#define REG_TAL_INTCPUSEL2         (*(RwReg  *)0x4101E130UL) /**< \brief (TAL) Interrupts CPU Select 2 */
-#define REG_TAL_INTCPUSEL3         (*(RwReg  *)0x4101E134UL) /**< \brief (TAL) Interrupts CPU Select 3 */
-#define REG_TAL_INTCPUSEL4         (*(RwReg  *)0x4101E138UL) /**< \brief (TAL) Interrupts CPU Select 4 */
-#define REG_TAL_INTCPUSEL5         (*(RwReg  *)0x4101E13CUL) /**< \brief (TAL) Interrupts CPU Select 5 */
-#define REG_TAL_INTCPUSEL6         (*(RwReg  *)0x4101E140UL) /**< \brief (TAL) Interrupts CPU Select 6 */
-#define REG_TAL_INTCPUSEL7         (*(RwReg  *)0x4101E144UL) /**< \brief (TAL) Interrupts CPU Select 7 */
-#define REG_TAL_INTCPUSEL8         (*(RwReg  *)0x4101E148UL) /**< \brief (TAL) Interrupts CPU Select 8 */
-#define REG_TAL_IRQTRIG            (*(RwReg  *)0x4101E164UL) /**< \brief (TAL) Interrupt Trigger */
-#define REG_TAL_IRQMON0            (*(RwReg16*)0x4101E168UL) /**< \brief (TAL) Interrupt Monitor Select 0 */
-#define REG_TAL_CPUIRQS0           (*(RoReg  *)0x4101E180UL) /**< \brief (TAL) Interrupt Status m for CPU 0 */
-#define REG_TAL_CPUIRQS1           (*(RoReg  *)0x4101E1A0UL) /**< \brief (TAL) Interrupt Status m for CPU 1 */
-#define REG_TAL_SMASK0             (*(RwReg  *)0x4101E200UL) /**< \brief (TAL) Inter-Process Signal Mask m for CPU 0 */
-#define REG_TAL_SMASK1             (*(RwReg  *)0x4101E208UL) /**< \brief (TAL) Inter-Process Signal Mask m for CPU 1 */
-#define REG_TAL_SFLAGCLR0          (*(WoReg  *)0x4101E220UL) /**< \brief (TAL) Inter-Process Signal Flag Clear 0 */
-#define REG_TAL_SFLAGCLR1          (*(WoReg  *)0x4101E224UL) /**< \brief (TAL) Inter-Process Signal Flag Clear 1 */
-#define REG_TAL_SFLAGSET0          (*(WoReg  *)0x4101E228UL) /**< \brief (TAL) Inter-Process Signal Flag Set 0 */
-#define REG_TAL_SFLAGSET1          (*(WoReg  *)0x4101E22CUL) /**< \brief (TAL) Inter-Process Signal Flag Set 1 */
-#define REG_TAL_SFLAG0             (*(RoReg  *)0x4101E230UL) /**< \brief (TAL) Inter-Process Signal Flag 0 */
-#define REG_TAL_SFLAG1             (*(RoReg  *)0x4101E234UL) /**< \brief (TAL) Inter-Process Signal Flag 1 */
-#define REG_TAL_SFLAGCLRR0         (*(RwReg8 *)0x4101E300UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 0 */
-#define REG_TAL_SFLAGCLRR1         (*(RwReg8 *)0x4101E301UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 1 */
-#define REG_TAL_SFLAGCLRR2         (*(RwReg8 *)0x4101E302UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 2 */
-#define REG_TAL_SFLAGCLRR3         (*(RwReg8 *)0x4101E303UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 3 */
-#define REG_TAL_SFLAGCLRR4         (*(RwReg8 *)0x4101E304UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 4 */
-#define REG_TAL_SFLAGCLRR5         (*(RwReg8 *)0x4101E305UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 5 */
-#define REG_TAL_SFLAGCLRR6         (*(RwReg8 *)0x4101E306UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 6 */
-#define REG_TAL_SFLAGCLRR7         (*(RwReg8 *)0x4101E307UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 7 */
-#define REG_TAL_SFLAGCLRR8         (*(RwReg8 *)0x4101E308UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 8 */
-#define REG_TAL_SFLAGCLRR9         (*(RwReg8 *)0x4101E309UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 9 */
-#define REG_TAL_SFLAGCLRR10        (*(RwReg8 *)0x4101E30AUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 10 */
-#define REG_TAL_SFLAGCLRR11        (*(RwReg8 *)0x4101E30BUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 11 */
-#define REG_TAL_SFLAGCLRR12        (*(RwReg8 *)0x4101E30CUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 12 */
-#define REG_TAL_SFLAGCLRR13        (*(RwReg8 *)0x4101E30DUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 13 */
-#define REG_TAL_SFLAGCLRR14        (*(RwReg8 *)0x4101E30EUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 14 */
-#define REG_TAL_SFLAGCLRR15        (*(RwReg8 *)0x4101E30FUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 15 */
-#define REG_TAL_SFLAGCLRR16        (*(RwReg8 *)0x4101E310UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 16 */
-#define REG_TAL_SFLAGCLRR17        (*(RwReg8 *)0x4101E311UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 17 */
-#define REG_TAL_SFLAGCLRR18        (*(RwReg8 *)0x4101E312UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 18 */
-#define REG_TAL_SFLAGCLRR19        (*(RwReg8 *)0x4101E313UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 19 */
-#define REG_TAL_SFLAGCLRR20        (*(RwReg8 *)0x4101E314UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 20 */
-#define REG_TAL_SFLAGCLRR21        (*(RwReg8 *)0x4101E315UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 21 */
-#define REG_TAL_SFLAGCLRR22        (*(RwReg8 *)0x4101E316UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 22 */
-#define REG_TAL_SFLAGCLRR23        (*(RwReg8 *)0x4101E317UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 23 */
-#define REG_TAL_SFLAGCLRR24        (*(RwReg8 *)0x4101E318UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 24 */
-#define REG_TAL_SFLAGCLRR25        (*(RwReg8 *)0x4101E319UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 25 */
-#define REG_TAL_SFLAGCLRR26        (*(RwReg8 *)0x4101E31AUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 26 */
-#define REG_TAL_SFLAGCLRR27        (*(RwReg8 *)0x4101E31BUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 27 */
-#define REG_TAL_SFLAGCLRR28        (*(RwReg8 *)0x4101E31CUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 28 */
-#define REG_TAL_SFLAGCLRR29        (*(RwReg8 *)0x4101E31DUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 29 */
-#define REG_TAL_SFLAGCLRR30        (*(RwReg8 *)0x4101E31EUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 30 */
-#define REG_TAL_SFLAGCLRR31        (*(RwReg8 *)0x4101E31FUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 31 */
-#define REG_TAL_SFLAGCLRR32        (*(RwReg8 *)0x4101E320UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 32 */
-#define REG_TAL_SFLAGCLRR33        (*(RwReg8 *)0x4101E321UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 33 */
-#define REG_TAL_SFLAGCLRR34        (*(RwReg8 *)0x4101E322UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 34 */
-#define REG_TAL_SFLAGCLRR35        (*(RwReg8 *)0x4101E323UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 35 */
-#define REG_TAL_SFLAGCLRR36        (*(RwReg8 *)0x4101E324UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 36 */
-#define REG_TAL_SFLAGCLRR37        (*(RwReg8 *)0x4101E325UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 37 */
-#define REG_TAL_SFLAGCLRR38        (*(RwReg8 *)0x4101E326UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 38 */
-#define REG_TAL_SFLAGCLRR39        (*(RwReg8 *)0x4101E327UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 39 */
-#define REG_TAL_SFLAGCLRR40        (*(RwReg8 *)0x4101E328UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 40 */
-#define REG_TAL_SFLAGCLRR41        (*(RwReg8 *)0x4101E329UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 41 */
-#define REG_TAL_SFLAGCLRR42        (*(RwReg8 *)0x4101E32AUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 42 */
-#define REG_TAL_SFLAGCLRR43        (*(RwReg8 *)0x4101E32BUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 43 */
-#define REG_TAL_SFLAGCLRR44        (*(RwReg8 *)0x4101E32CUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 44 */
-#define REG_TAL_SFLAGCLRR45        (*(RwReg8 *)0x4101E32DUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 45 */
-#define REG_TAL_SFLAGCLRR46        (*(RwReg8 *)0x4101E32EUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 46 */
-#define REG_TAL_SFLAGCLRR47        (*(RwReg8 *)0x4101E32FUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 47 */
-#define REG_TAL_SFLAGCLRR48        (*(RwReg8 *)0x4101E330UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 48 */
-#define REG_TAL_SFLAGCLRR49        (*(RwReg8 *)0x4101E331UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 49 */
-#define REG_TAL_SFLAGCLRR50        (*(RwReg8 *)0x4101E332UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 50 */
-#define REG_TAL_SFLAGCLRR51        (*(RwReg8 *)0x4101E333UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 51 */
-#define REG_TAL_SFLAGCLRR52        (*(RwReg8 *)0x4101E334UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 52 */
-#define REG_TAL_SFLAGCLRR53        (*(RwReg8 *)0x4101E335UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 53 */
-#define REG_TAL_SFLAGCLRR54        (*(RwReg8 *)0x4101E336UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 54 */
-#define REG_TAL_SFLAGCLRR55        (*(RwReg8 *)0x4101E337UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 55 */
-#define REG_TAL_SFLAGCLRR56        (*(RwReg8 *)0x4101E338UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 56 */
-#define REG_TAL_SFLAGCLRR57        (*(RwReg8 *)0x4101E339UL) /**< \brief (TAL) Inter-Process Signal Flag Bit 57 */
-#define REG_TAL_SFLAGCLRR58        (*(RwReg8 *)0x4101E33AUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 58 */
-#define REG_TAL_SFLAGCLRR59        (*(RwReg8 *)0x4101E33BUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 59 */
-#define REG_TAL_SFLAGCLRR60        (*(RwReg8 *)0x4101E33CUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 60 */
-#define REG_TAL_SFLAGCLRR61        (*(RwReg8 *)0x4101E33DUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 61 */
-#define REG_TAL_SFLAGCLRR62        (*(RwReg8 *)0x4101E33EUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 62 */
-#define REG_TAL_SFLAGCLRR63        (*(RwReg8 *)0x4101E33FUL) /**< \brief (TAL) Inter-Process Signal Flag Bit 63 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TAL peripheral ========== */
-#define TAL_CPU_NUM                 2        // Number of CPUs
-#define TAL_CTI_NUM                 4        // Number of Cross-Trigger Interfaces
-#define TAL_DMA_CH_NUM              32       // Number of DMAC Channels
-#define TAL_EV_CH_NUM               12       // Number of EVSYS Channels
-#define TAL_EXTINT_NUM              16       // Number of EIC External Interrrupts
-#define TAL_ID_IN_INTCPUSEL         1        // Use ID of IP instances in INTCPUSEL registers
-#define TAL_ID_NUM                  130      // Number of IDs for IP instance numbers
-#define TAL_INT_GRP_NUM             5        // Number of 32-IRQ Groups
-#define TAL_INT_NUM                 137      // Number of Interrupt Requests
-#define TAL_INT_NUM_BITS            8        // Number of bits for INT_NUM
-#define TAL_IPS_GRP_NUM             2        // Number of 32-IPS Groups
-#define TAL_IPS_NUM                 64       // Number of Inter-Process Signals
-#define TAL_IRQMON_NUM              1        // Number of IRQ Monitors
-
-#endif /* _SAMD51_TAL_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc0.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc0.h
deleted file mode 100644
index 7b3d2b8594..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc0.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC0
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TC0_INSTANCE_
-#define _SAMD51_TC0_INSTANCE_
-
-/* ========== Register definition for TC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC0_CTRLA              (0x40003800) /**< \brief (TC0) Control A */
-#define REG_TC0_CTRLBCLR           (0x40003804) /**< \brief (TC0) Control B Clear */
-#define REG_TC0_CTRLBSET           (0x40003805) /**< \brief (TC0) Control B Set */
-#define REG_TC0_EVCTRL             (0x40003806) /**< \brief (TC0) Event Control */
-#define REG_TC0_INTENCLR           (0x40003808) /**< \brief (TC0) Interrupt Enable Clear */
-#define REG_TC0_INTENSET           (0x40003809) /**< \brief (TC0) Interrupt Enable Set */
-#define REG_TC0_INTFLAG            (0x4000380A) /**< \brief (TC0) Interrupt Flag Status and Clear */
-#define REG_TC0_STATUS             (0x4000380B) /**< \brief (TC0) Status */
-#define REG_TC0_WAVE               (0x4000380C) /**< \brief (TC0) Waveform Generation Control */
-#define REG_TC0_DRVCTRL            (0x4000380D) /**< \brief (TC0) Control C */
-#define REG_TC0_DBGCTRL            (0x4000380F) /**< \brief (TC0) Debug Control */
-#define REG_TC0_SYNCBUSY           (0x40003810) /**< \brief (TC0) Synchronization Status */
-#define REG_TC0_COUNT16_COUNT      (0x40003814) /**< \brief (TC0) COUNT16 Count */
-#define REG_TC0_COUNT16_CC0        (0x4000381C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
-#define REG_TC0_COUNT16_CC1        (0x4000381E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
-#define REG_TC0_COUNT16_CCBUF0     (0x40003830) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC0_COUNT16_CCBUF1     (0x40003832) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC0_COUNT32_COUNT      (0x40003814) /**< \brief (TC0) COUNT32 Count */
-#define REG_TC0_COUNT32_CC0        (0x4000381C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
-#define REG_TC0_COUNT32_CC1        (0x40003820) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
-#define REG_TC0_COUNT32_CCBUF0     (0x40003830) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC0_COUNT32_CCBUF1     (0x40003834) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC0_COUNT8_COUNT       (0x40003814) /**< \brief (TC0) COUNT8 Count */
-#define REG_TC0_COUNT8_PER         (0x4000381B) /**< \brief (TC0) COUNT8 Period */
-#define REG_TC0_COUNT8_CC0         (0x4000381C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
-#define REG_TC0_COUNT8_CC1         (0x4000381D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
-#define REG_TC0_COUNT8_PERBUF      (0x4000382F) /**< \brief (TC0) COUNT8 Period Buffer */
-#define REG_TC0_COUNT8_CCBUF0      (0x40003830) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC0_COUNT8_CCBUF1      (0x40003831) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
-#else
-#define REG_TC0_CTRLA              (*(RwReg  *)0x40003800UL) /**< \brief (TC0) Control A */
-#define REG_TC0_CTRLBCLR           (*(RwReg8 *)0x40003804UL) /**< \brief (TC0) Control B Clear */
-#define REG_TC0_CTRLBSET           (*(RwReg8 *)0x40003805UL) /**< \brief (TC0) Control B Set */
-#define REG_TC0_EVCTRL             (*(RwReg16*)0x40003806UL) /**< \brief (TC0) Event Control */
-#define REG_TC0_INTENCLR           (*(RwReg8 *)0x40003808UL) /**< \brief (TC0) Interrupt Enable Clear */
-#define REG_TC0_INTENSET           (*(RwReg8 *)0x40003809UL) /**< \brief (TC0) Interrupt Enable Set */
-#define REG_TC0_INTFLAG            (*(RwReg8 *)0x4000380AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */
-#define REG_TC0_STATUS             (*(RwReg8 *)0x4000380BUL) /**< \brief (TC0) Status */
-#define REG_TC0_WAVE               (*(RwReg8 *)0x4000380CUL) /**< \brief (TC0) Waveform Generation Control */
-#define REG_TC0_DRVCTRL            (*(RwReg8 *)0x4000380DUL) /**< \brief (TC0) Control C */
-#define REG_TC0_DBGCTRL            (*(RwReg8 *)0x4000380FUL) /**< \brief (TC0) Debug Control */
-#define REG_TC0_SYNCBUSY           (*(RoReg  *)0x40003810UL) /**< \brief (TC0) Synchronization Status */
-#define REG_TC0_COUNT16_COUNT      (*(RwReg16*)0x40003814UL) /**< \brief (TC0) COUNT16 Count */
-#define REG_TC0_COUNT16_CC0        (*(RwReg16*)0x4000381CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
-#define REG_TC0_COUNT16_CC1        (*(RwReg16*)0x4000381EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
-#define REG_TC0_COUNT16_CCBUF0     (*(RwReg16*)0x40003830UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC0_COUNT16_CCBUF1     (*(RwReg16*)0x40003832UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC0_COUNT32_COUNT      (*(RwReg  *)0x40003814UL) /**< \brief (TC0) COUNT32 Count */
-#define REG_TC0_COUNT32_CC0        (*(RwReg  *)0x4000381CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
-#define REG_TC0_COUNT32_CC1        (*(RwReg  *)0x40003820UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
-#define REG_TC0_COUNT32_CCBUF0     (*(RwReg  *)0x40003830UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC0_COUNT32_CCBUF1     (*(RwReg  *)0x40003834UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC0_COUNT8_COUNT       (*(RwReg8 *)0x40003814UL) /**< \brief (TC0) COUNT8 Count */
-#define REG_TC0_COUNT8_PER         (*(RwReg8 *)0x4000381BUL) /**< \brief (TC0) COUNT8 Period */
-#define REG_TC0_COUNT8_CC0         (*(RwReg8 *)0x4000381CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
-#define REG_TC0_COUNT8_CC1         (*(RwReg8 *)0x4000381DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
-#define REG_TC0_COUNT8_PERBUF      (*(RwReg8 *)0x4000382FUL) /**< \brief (TC0) COUNT8 Period Buffer */
-#define REG_TC0_COUNT8_CCBUF0      (*(RwReg8 *)0x40003830UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC0_COUNT8_CCBUF1      (*(RwReg8 *)0x40003831UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC0 peripheral ========== */
-#define TC0_CC_NUM                  2       
-#define TC0_DMAC_ID_MC_0            45
-#define TC0_DMAC_ID_MC_1            46
-#define TC0_DMAC_ID_MC_LSB          45
-#define TC0_DMAC_ID_MC_MSB          46
-#define TC0_DMAC_ID_MC_SIZE         2
-#define TC0_DMAC_ID_OVF             44       // Indexes of DMA Overflow trigger
-#define TC0_EXT                     0        // Coding of implemented extended features (keep 0 value)
-#define TC0_GCLK_ID                 9        // Index of Generic Clock
-#define TC0_MASTER_SLAVE_MODE       1        // TC type 0 : NA, 1 : Master, 2 : Slave
-#define TC0_OW_NUM                  2        // Number of Output Waveforms
-
-#endif /* _SAMD51_TC0_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc1.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc1.h
deleted file mode 100644
index 544a7055ae..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc1.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC1
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TC1_INSTANCE_
-#define _SAMD51_TC1_INSTANCE_
-
-/* ========== Register definition for TC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC1_CTRLA              (0x40003C00) /**< \brief (TC1) Control A */
-#define REG_TC1_CTRLBCLR           (0x40003C04) /**< \brief (TC1) Control B Clear */
-#define REG_TC1_CTRLBSET           (0x40003C05) /**< \brief (TC1) Control B Set */
-#define REG_TC1_EVCTRL             (0x40003C06) /**< \brief (TC1) Event Control */
-#define REG_TC1_INTENCLR           (0x40003C08) /**< \brief (TC1) Interrupt Enable Clear */
-#define REG_TC1_INTENSET           (0x40003C09) /**< \brief (TC1) Interrupt Enable Set */
-#define REG_TC1_INTFLAG            (0x40003C0A) /**< \brief (TC1) Interrupt Flag Status and Clear */
-#define REG_TC1_STATUS             (0x40003C0B) /**< \brief (TC1) Status */
-#define REG_TC1_WAVE               (0x40003C0C) /**< \brief (TC1) Waveform Generation Control */
-#define REG_TC1_DRVCTRL            (0x40003C0D) /**< \brief (TC1) Control C */
-#define REG_TC1_DBGCTRL            (0x40003C0F) /**< \brief (TC1) Debug Control */
-#define REG_TC1_SYNCBUSY           (0x40003C10) /**< \brief (TC1) Synchronization Status */
-#define REG_TC1_COUNT16_COUNT      (0x40003C14) /**< \brief (TC1) COUNT16 Count */
-#define REG_TC1_COUNT16_CC0        (0x40003C1C) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
-#define REG_TC1_COUNT16_CC1        (0x40003C1E) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
-#define REG_TC1_COUNT16_CCBUF0     (0x40003C30) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC1_COUNT16_CCBUF1     (0x40003C32) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC1_COUNT32_COUNT      (0x40003C14) /**< \brief (TC1) COUNT32 Count */
-#define REG_TC1_COUNT32_CC0        (0x40003C1C) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
-#define REG_TC1_COUNT32_CC1        (0x40003C20) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
-#define REG_TC1_COUNT32_CCBUF0     (0x40003C30) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC1_COUNT32_CCBUF1     (0x40003C34) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC1_COUNT8_COUNT       (0x40003C14) /**< \brief (TC1) COUNT8 Count */
-#define REG_TC1_COUNT8_PER         (0x40003C1B) /**< \brief (TC1) COUNT8 Period */
-#define REG_TC1_COUNT8_CC0         (0x40003C1C) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
-#define REG_TC1_COUNT8_CC1         (0x40003C1D) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
-#define REG_TC1_COUNT8_PERBUF      (0x40003C2F) /**< \brief (TC1) COUNT8 Period Buffer */
-#define REG_TC1_COUNT8_CCBUF0      (0x40003C30) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC1_COUNT8_CCBUF1      (0x40003C31) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
-#else
-#define REG_TC1_CTRLA              (*(RwReg  *)0x40003C00UL) /**< \brief (TC1) Control A */
-#define REG_TC1_CTRLBCLR           (*(RwReg8 *)0x40003C04UL) /**< \brief (TC1) Control B Clear */
-#define REG_TC1_CTRLBSET           (*(RwReg8 *)0x40003C05UL) /**< \brief (TC1) Control B Set */
-#define REG_TC1_EVCTRL             (*(RwReg16*)0x40003C06UL) /**< \brief (TC1) Event Control */
-#define REG_TC1_INTENCLR           (*(RwReg8 *)0x40003C08UL) /**< \brief (TC1) Interrupt Enable Clear */
-#define REG_TC1_INTENSET           (*(RwReg8 *)0x40003C09UL) /**< \brief (TC1) Interrupt Enable Set */
-#define REG_TC1_INTFLAG            (*(RwReg8 *)0x40003C0AUL) /**< \brief (TC1) Interrupt Flag Status and Clear */
-#define REG_TC1_STATUS             (*(RwReg8 *)0x40003C0BUL) /**< \brief (TC1) Status */
-#define REG_TC1_WAVE               (*(RwReg8 *)0x40003C0CUL) /**< \brief (TC1) Waveform Generation Control */
-#define REG_TC1_DRVCTRL            (*(RwReg8 *)0x40003C0DUL) /**< \brief (TC1) Control C */
-#define REG_TC1_DBGCTRL            (*(RwReg8 *)0x40003C0FUL) /**< \brief (TC1) Debug Control */
-#define REG_TC1_SYNCBUSY           (*(RoReg  *)0x40003C10UL) /**< \brief (TC1) Synchronization Status */
-#define REG_TC1_COUNT16_COUNT      (*(RwReg16*)0x40003C14UL) /**< \brief (TC1) COUNT16 Count */
-#define REG_TC1_COUNT16_CC0        (*(RwReg16*)0x40003C1CUL) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
-#define REG_TC1_COUNT16_CC1        (*(RwReg16*)0x40003C1EUL) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
-#define REG_TC1_COUNT16_CCBUF0     (*(RwReg16*)0x40003C30UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC1_COUNT16_CCBUF1     (*(RwReg16*)0x40003C32UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC1_COUNT32_COUNT      (*(RwReg  *)0x40003C14UL) /**< \brief (TC1) COUNT32 Count */
-#define REG_TC1_COUNT32_CC0        (*(RwReg  *)0x40003C1CUL) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
-#define REG_TC1_COUNT32_CC1        (*(RwReg  *)0x40003C20UL) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
-#define REG_TC1_COUNT32_CCBUF0     (*(RwReg  *)0x40003C30UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC1_COUNT32_CCBUF1     (*(RwReg  *)0x40003C34UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC1_COUNT8_COUNT       (*(RwReg8 *)0x40003C14UL) /**< \brief (TC1) COUNT8 Count */
-#define REG_TC1_COUNT8_PER         (*(RwReg8 *)0x40003C1BUL) /**< \brief (TC1) COUNT8 Period */
-#define REG_TC1_COUNT8_CC0         (*(RwReg8 *)0x40003C1CUL) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
-#define REG_TC1_COUNT8_CC1         (*(RwReg8 *)0x40003C1DUL) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
-#define REG_TC1_COUNT8_PERBUF      (*(RwReg8 *)0x40003C2FUL) /**< \brief (TC1) COUNT8 Period Buffer */
-#define REG_TC1_COUNT8_CCBUF0      (*(RwReg8 *)0x40003C30UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC1_COUNT8_CCBUF1      (*(RwReg8 *)0x40003C31UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC1 peripheral ========== */
-#define TC1_CC_NUM                  2       
-#define TC1_DMAC_ID_MC_0            48
-#define TC1_DMAC_ID_MC_1            49
-#define TC1_DMAC_ID_MC_LSB          48
-#define TC1_DMAC_ID_MC_MSB          49
-#define TC1_DMAC_ID_MC_SIZE         2
-#define TC1_DMAC_ID_OVF             47       // Indexes of DMA Overflow trigger
-#define TC1_EXT                     0        // Coding of implemented extended features (keep 0 value)
-#define TC1_GCLK_ID                 9        // Index of Generic Clock
-#define TC1_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave
-#define TC1_OW_NUM                  2        // Number of Output Waveforms
-
-#endif /* _SAMD51_TC1_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc2.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc2.h
deleted file mode 100644
index 2578fbfdb2..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc2.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC2
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TC2_INSTANCE_
-#define _SAMD51_TC2_INSTANCE_
-
-/* ========== Register definition for TC2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC2_CTRLA              (0x4101A000) /**< \brief (TC2) Control A */
-#define REG_TC2_CTRLBCLR           (0x4101A004) /**< \brief (TC2) Control B Clear */
-#define REG_TC2_CTRLBSET           (0x4101A005) /**< \brief (TC2) Control B Set */
-#define REG_TC2_EVCTRL             (0x4101A006) /**< \brief (TC2) Event Control */
-#define REG_TC2_INTENCLR           (0x4101A008) /**< \brief (TC2) Interrupt Enable Clear */
-#define REG_TC2_INTENSET           (0x4101A009) /**< \brief (TC2) Interrupt Enable Set */
-#define REG_TC2_INTFLAG            (0x4101A00A) /**< \brief (TC2) Interrupt Flag Status and Clear */
-#define REG_TC2_STATUS             (0x4101A00B) /**< \brief (TC2) Status */
-#define REG_TC2_WAVE               (0x4101A00C) /**< \brief (TC2) Waveform Generation Control */
-#define REG_TC2_DRVCTRL            (0x4101A00D) /**< \brief (TC2) Control C */
-#define REG_TC2_DBGCTRL            (0x4101A00F) /**< \brief (TC2) Debug Control */
-#define REG_TC2_SYNCBUSY           (0x4101A010) /**< \brief (TC2) Synchronization Status */
-#define REG_TC2_COUNT16_COUNT      (0x4101A014) /**< \brief (TC2) COUNT16 Count */
-#define REG_TC2_COUNT16_CC0        (0x4101A01C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
-#define REG_TC2_COUNT16_CC1        (0x4101A01E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
-#define REG_TC2_COUNT16_CCBUF0     (0x4101A030) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC2_COUNT16_CCBUF1     (0x4101A032) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC2_COUNT32_COUNT      (0x4101A014) /**< \brief (TC2) COUNT32 Count */
-#define REG_TC2_COUNT32_CC0        (0x4101A01C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
-#define REG_TC2_COUNT32_CC1        (0x4101A020) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
-#define REG_TC2_COUNT32_CCBUF0     (0x4101A030) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC2_COUNT32_CCBUF1     (0x4101A034) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC2_COUNT8_COUNT       (0x4101A014) /**< \brief (TC2) COUNT8 Count */
-#define REG_TC2_COUNT8_PER         (0x4101A01B) /**< \brief (TC2) COUNT8 Period */
-#define REG_TC2_COUNT8_CC0         (0x4101A01C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
-#define REG_TC2_COUNT8_CC1         (0x4101A01D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
-#define REG_TC2_COUNT8_PERBUF      (0x4101A02F) /**< \brief (TC2) COUNT8 Period Buffer */
-#define REG_TC2_COUNT8_CCBUF0      (0x4101A030) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC2_COUNT8_CCBUF1      (0x4101A031) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
-#else
-#define REG_TC2_CTRLA              (*(RwReg  *)0x4101A000UL) /**< \brief (TC2) Control A */
-#define REG_TC2_CTRLBCLR           (*(RwReg8 *)0x4101A004UL) /**< \brief (TC2) Control B Clear */
-#define REG_TC2_CTRLBSET           (*(RwReg8 *)0x4101A005UL) /**< \brief (TC2) Control B Set */
-#define REG_TC2_EVCTRL             (*(RwReg16*)0x4101A006UL) /**< \brief (TC2) Event Control */
-#define REG_TC2_INTENCLR           (*(RwReg8 *)0x4101A008UL) /**< \brief (TC2) Interrupt Enable Clear */
-#define REG_TC2_INTENSET           (*(RwReg8 *)0x4101A009UL) /**< \brief (TC2) Interrupt Enable Set */
-#define REG_TC2_INTFLAG            (*(RwReg8 *)0x4101A00AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */
-#define REG_TC2_STATUS             (*(RwReg8 *)0x4101A00BUL) /**< \brief (TC2) Status */
-#define REG_TC2_WAVE               (*(RwReg8 *)0x4101A00CUL) /**< \brief (TC2) Waveform Generation Control */
-#define REG_TC2_DRVCTRL            (*(RwReg8 *)0x4101A00DUL) /**< \brief (TC2) Control C */
-#define REG_TC2_DBGCTRL            (*(RwReg8 *)0x4101A00FUL) /**< \brief (TC2) Debug Control */
-#define REG_TC2_SYNCBUSY           (*(RoReg  *)0x4101A010UL) /**< \brief (TC2) Synchronization Status */
-#define REG_TC2_COUNT16_COUNT      (*(RwReg16*)0x4101A014UL) /**< \brief (TC2) COUNT16 Count */
-#define REG_TC2_COUNT16_CC0        (*(RwReg16*)0x4101A01CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
-#define REG_TC2_COUNT16_CC1        (*(RwReg16*)0x4101A01EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
-#define REG_TC2_COUNT16_CCBUF0     (*(RwReg16*)0x4101A030UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC2_COUNT16_CCBUF1     (*(RwReg16*)0x4101A032UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC2_COUNT32_COUNT      (*(RwReg  *)0x4101A014UL) /**< \brief (TC2) COUNT32 Count */
-#define REG_TC2_COUNT32_CC0        (*(RwReg  *)0x4101A01CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
-#define REG_TC2_COUNT32_CC1        (*(RwReg  *)0x4101A020UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
-#define REG_TC2_COUNT32_CCBUF0     (*(RwReg  *)0x4101A030UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC2_COUNT32_CCBUF1     (*(RwReg  *)0x4101A034UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC2_COUNT8_COUNT       (*(RwReg8 *)0x4101A014UL) /**< \brief (TC2) COUNT8 Count */
-#define REG_TC2_COUNT8_PER         (*(RwReg8 *)0x4101A01BUL) /**< \brief (TC2) COUNT8 Period */
-#define REG_TC2_COUNT8_CC0         (*(RwReg8 *)0x4101A01CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
-#define REG_TC2_COUNT8_CC1         (*(RwReg8 *)0x4101A01DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
-#define REG_TC2_COUNT8_PERBUF      (*(RwReg8 *)0x4101A02FUL) /**< \brief (TC2) COUNT8 Period Buffer */
-#define REG_TC2_COUNT8_CCBUF0      (*(RwReg8 *)0x4101A030UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC2_COUNT8_CCBUF1      (*(RwReg8 *)0x4101A031UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC2 peripheral ========== */
-#define TC2_CC_NUM                  2       
-#define TC2_DMAC_ID_MC_0            51
-#define TC2_DMAC_ID_MC_1            52
-#define TC2_DMAC_ID_MC_LSB          51
-#define TC2_DMAC_ID_MC_MSB          52
-#define TC2_DMAC_ID_MC_SIZE         2
-#define TC2_DMAC_ID_OVF             50       // Indexes of DMA Overflow trigger
-#define TC2_EXT                     0        // Coding of implemented extended features (keep 0 value)
-#define TC2_GCLK_ID                 26       // Index of Generic Clock
-#define TC2_MASTER_SLAVE_MODE       1        // TC type 0 : NA, 1 : Master, 2 : Slave
-#define TC2_OW_NUM                  2        // Number of Output Waveforms
-
-#endif /* _SAMD51_TC2_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc3.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc3.h
deleted file mode 100644
index 6ef2009d5d..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc3.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC3
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TC3_INSTANCE_
-#define _SAMD51_TC3_INSTANCE_
-
-/* ========== Register definition for TC3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC3_CTRLA              (0x4101C000) /**< \brief (TC3) Control A */
-#define REG_TC3_CTRLBCLR           (0x4101C004) /**< \brief (TC3) Control B Clear */
-#define REG_TC3_CTRLBSET           (0x4101C005) /**< \brief (TC3) Control B Set */
-#define REG_TC3_EVCTRL             (0x4101C006) /**< \brief (TC3) Event Control */
-#define REG_TC3_INTENCLR           (0x4101C008) /**< \brief (TC3) Interrupt Enable Clear */
-#define REG_TC3_INTENSET           (0x4101C009) /**< \brief (TC3) Interrupt Enable Set */
-#define REG_TC3_INTFLAG            (0x4101C00A) /**< \brief (TC3) Interrupt Flag Status and Clear */
-#define REG_TC3_STATUS             (0x4101C00B) /**< \brief (TC3) Status */
-#define REG_TC3_WAVE               (0x4101C00C) /**< \brief (TC3) Waveform Generation Control */
-#define REG_TC3_DRVCTRL            (0x4101C00D) /**< \brief (TC3) Control C */
-#define REG_TC3_DBGCTRL            (0x4101C00F) /**< \brief (TC3) Debug Control */
-#define REG_TC3_SYNCBUSY           (0x4101C010) /**< \brief (TC3) Synchronization Status */
-#define REG_TC3_COUNT16_COUNT      (0x4101C014) /**< \brief (TC3) COUNT16 Count */
-#define REG_TC3_COUNT16_CC0        (0x4101C01C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
-#define REG_TC3_COUNT16_CC1        (0x4101C01E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
-#define REG_TC3_COUNT16_CCBUF0     (0x4101C030) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT16_CCBUF1     (0x4101C032) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC3_COUNT32_COUNT      (0x4101C014) /**< \brief (TC3) COUNT32 Count */
-#define REG_TC3_COUNT32_CC0        (0x4101C01C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
-#define REG_TC3_COUNT32_CC1        (0x4101C020) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
-#define REG_TC3_COUNT32_CCBUF0     (0x4101C030) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT32_CCBUF1     (0x4101C034) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC3_COUNT8_COUNT       (0x4101C014) /**< \brief (TC3) COUNT8 Count */
-#define REG_TC3_COUNT8_PER         (0x4101C01B) /**< \brief (TC3) COUNT8 Period */
-#define REG_TC3_COUNT8_CC0         (0x4101C01C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
-#define REG_TC3_COUNT8_CC1         (0x4101C01D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
-#define REG_TC3_COUNT8_PERBUF      (0x4101C02F) /**< \brief (TC3) COUNT8 Period Buffer */
-#define REG_TC3_COUNT8_CCBUF0      (0x4101C030) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT8_CCBUF1      (0x4101C031) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
-#else
-#define REG_TC3_CTRLA              (*(RwReg  *)0x4101C000UL) /**< \brief (TC3) Control A */
-#define REG_TC3_CTRLBCLR           (*(RwReg8 *)0x4101C004UL) /**< \brief (TC3) Control B Clear */
-#define REG_TC3_CTRLBSET           (*(RwReg8 *)0x4101C005UL) /**< \brief (TC3) Control B Set */
-#define REG_TC3_EVCTRL             (*(RwReg16*)0x4101C006UL) /**< \brief (TC3) Event Control */
-#define REG_TC3_INTENCLR           (*(RwReg8 *)0x4101C008UL) /**< \brief (TC3) Interrupt Enable Clear */
-#define REG_TC3_INTENSET           (*(RwReg8 *)0x4101C009UL) /**< \brief (TC3) Interrupt Enable Set */
-#define REG_TC3_INTFLAG            (*(RwReg8 *)0x4101C00AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */
-#define REG_TC3_STATUS             (*(RwReg8 *)0x4101C00BUL) /**< \brief (TC3) Status */
-#define REG_TC3_WAVE               (*(RwReg8 *)0x4101C00CUL) /**< \brief (TC3) Waveform Generation Control */
-#define REG_TC3_DRVCTRL            (*(RwReg8 *)0x4101C00DUL) /**< \brief (TC3) Control C */
-#define REG_TC3_DBGCTRL            (*(RwReg8 *)0x4101C00FUL) /**< \brief (TC3) Debug Control */
-#define REG_TC3_SYNCBUSY           (*(RoReg  *)0x4101C010UL) /**< \brief (TC3) Synchronization Status */
-#define REG_TC3_COUNT16_COUNT      (*(RwReg16*)0x4101C014UL) /**< \brief (TC3) COUNT16 Count */
-#define REG_TC3_COUNT16_CC0        (*(RwReg16*)0x4101C01CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
-#define REG_TC3_COUNT16_CC1        (*(RwReg16*)0x4101C01EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
-#define REG_TC3_COUNT16_CCBUF0     (*(RwReg16*)0x4101C030UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT16_CCBUF1     (*(RwReg16*)0x4101C032UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC3_COUNT32_COUNT      (*(RwReg  *)0x4101C014UL) /**< \brief (TC3) COUNT32 Count */
-#define REG_TC3_COUNT32_CC0        (*(RwReg  *)0x4101C01CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
-#define REG_TC3_COUNT32_CC1        (*(RwReg  *)0x4101C020UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
-#define REG_TC3_COUNT32_CCBUF0     (*(RwReg  *)0x4101C030UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT32_CCBUF1     (*(RwReg  *)0x4101C034UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC3_COUNT8_COUNT       (*(RwReg8 *)0x4101C014UL) /**< \brief (TC3) COUNT8 Count */
-#define REG_TC3_COUNT8_PER         (*(RwReg8 *)0x4101C01BUL) /**< \brief (TC3) COUNT8 Period */
-#define REG_TC3_COUNT8_CC0         (*(RwReg8 *)0x4101C01CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
-#define REG_TC3_COUNT8_CC1         (*(RwReg8 *)0x4101C01DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
-#define REG_TC3_COUNT8_PERBUF      (*(RwReg8 *)0x4101C02FUL) /**< \brief (TC3) COUNT8 Period Buffer */
-#define REG_TC3_COUNT8_CCBUF0      (*(RwReg8 *)0x4101C030UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT8_CCBUF1      (*(RwReg8 *)0x4101C031UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC3 peripheral ========== */
-#define TC3_CC_NUM                  2       
-#define TC3_DMAC_ID_MC_0            54
-#define TC3_DMAC_ID_MC_1            55
-#define TC3_DMAC_ID_MC_LSB          54
-#define TC3_DMAC_ID_MC_MSB          55
-#define TC3_DMAC_ID_MC_SIZE         2
-#define TC3_DMAC_ID_OVF             53       // Indexes of DMA Overflow trigger
-#define TC3_EXT                     0        // Coding of implemented extended features (keep 0 value)
-#define TC3_GCLK_ID                 26       // Index of Generic Clock
-#define TC3_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave
-#define TC3_OW_NUM                  2        // Number of Output Waveforms
-
-#endif /* _SAMD51_TC3_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc4.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc4.h
deleted file mode 100644
index 392bc74abd..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc4.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC4
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TC4_INSTANCE_
-#define _SAMD51_TC4_INSTANCE_
-
-/* ========== Register definition for TC4 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC4_CTRLA              (0x42001400) /**< \brief (TC4) Control A */
-#define REG_TC4_CTRLBCLR           (0x42001404) /**< \brief (TC4) Control B Clear */
-#define REG_TC4_CTRLBSET           (0x42001405) /**< \brief (TC4) Control B Set */
-#define REG_TC4_EVCTRL             (0x42001406) /**< \brief (TC4) Event Control */
-#define REG_TC4_INTENCLR           (0x42001408) /**< \brief (TC4) Interrupt Enable Clear */
-#define REG_TC4_INTENSET           (0x42001409) /**< \brief (TC4) Interrupt Enable Set */
-#define REG_TC4_INTFLAG            (0x4200140A) /**< \brief (TC4) Interrupt Flag Status and Clear */
-#define REG_TC4_STATUS             (0x4200140B) /**< \brief (TC4) Status */
-#define REG_TC4_WAVE               (0x4200140C) /**< \brief (TC4) Waveform Generation Control */
-#define REG_TC4_DRVCTRL            (0x4200140D) /**< \brief (TC4) Control C */
-#define REG_TC4_DBGCTRL            (0x4200140F) /**< \brief (TC4) Debug Control */
-#define REG_TC4_SYNCBUSY           (0x42001410) /**< \brief (TC4) Synchronization Status */
-#define REG_TC4_COUNT16_COUNT      (0x42001414) /**< \brief (TC4) COUNT16 Count */
-#define REG_TC4_COUNT16_CC0        (0x4200141C) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
-#define REG_TC4_COUNT16_CC1        (0x4200141E) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
-#define REG_TC4_COUNT16_CCBUF0     (0x42001430) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC4_COUNT16_CCBUF1     (0x42001432) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC4_COUNT32_COUNT      (0x42001414) /**< \brief (TC4) COUNT32 Count */
-#define REG_TC4_COUNT32_CC0        (0x4200141C) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
-#define REG_TC4_COUNT32_CC1        (0x42001420) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
-#define REG_TC4_COUNT32_CCBUF0     (0x42001430) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC4_COUNT32_CCBUF1     (0x42001434) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC4_COUNT8_COUNT       (0x42001414) /**< \brief (TC4) COUNT8 Count */
-#define REG_TC4_COUNT8_PER         (0x4200141B) /**< \brief (TC4) COUNT8 Period */
-#define REG_TC4_COUNT8_CC0         (0x4200141C) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
-#define REG_TC4_COUNT8_CC1         (0x4200141D) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
-#define REG_TC4_COUNT8_PERBUF      (0x4200142F) /**< \brief (TC4) COUNT8 Period Buffer */
-#define REG_TC4_COUNT8_CCBUF0      (0x42001430) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC4_COUNT8_CCBUF1      (0x42001431) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
-#else
-#define REG_TC4_CTRLA              (*(RwReg  *)0x42001400UL) /**< \brief (TC4) Control A */
-#define REG_TC4_CTRLBCLR           (*(RwReg8 *)0x42001404UL) /**< \brief (TC4) Control B Clear */
-#define REG_TC4_CTRLBSET           (*(RwReg8 *)0x42001405UL) /**< \brief (TC4) Control B Set */
-#define REG_TC4_EVCTRL             (*(RwReg16*)0x42001406UL) /**< \brief (TC4) Event Control */
-#define REG_TC4_INTENCLR           (*(RwReg8 *)0x42001408UL) /**< \brief (TC4) Interrupt Enable Clear */
-#define REG_TC4_INTENSET           (*(RwReg8 *)0x42001409UL) /**< \brief (TC4) Interrupt Enable Set */
-#define REG_TC4_INTFLAG            (*(RwReg8 *)0x4200140AUL) /**< \brief (TC4) Interrupt Flag Status and Clear */
-#define REG_TC4_STATUS             (*(RwReg8 *)0x4200140BUL) /**< \brief (TC4) Status */
-#define REG_TC4_WAVE               (*(RwReg8 *)0x4200140CUL) /**< \brief (TC4) Waveform Generation Control */
-#define REG_TC4_DRVCTRL            (*(RwReg8 *)0x4200140DUL) /**< \brief (TC4) Control C */
-#define REG_TC4_DBGCTRL            (*(RwReg8 *)0x4200140FUL) /**< \brief (TC4) Debug Control */
-#define REG_TC4_SYNCBUSY           (*(RoReg  *)0x42001410UL) /**< \brief (TC4) Synchronization Status */
-#define REG_TC4_COUNT16_COUNT      (*(RwReg16*)0x42001414UL) /**< \brief (TC4) COUNT16 Count */
-#define REG_TC4_COUNT16_CC0        (*(RwReg16*)0x4200141CUL) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
-#define REG_TC4_COUNT16_CC1        (*(RwReg16*)0x4200141EUL) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
-#define REG_TC4_COUNT16_CCBUF0     (*(RwReg16*)0x42001430UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC4_COUNT16_CCBUF1     (*(RwReg16*)0x42001432UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC4_COUNT32_COUNT      (*(RwReg  *)0x42001414UL) /**< \brief (TC4) COUNT32 Count */
-#define REG_TC4_COUNT32_CC0        (*(RwReg  *)0x4200141CUL) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
-#define REG_TC4_COUNT32_CC1        (*(RwReg  *)0x42001420UL) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
-#define REG_TC4_COUNT32_CCBUF0     (*(RwReg  *)0x42001430UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC4_COUNT32_CCBUF1     (*(RwReg  *)0x42001434UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC4_COUNT8_COUNT       (*(RwReg8 *)0x42001414UL) /**< \brief (TC4) COUNT8 Count */
-#define REG_TC4_COUNT8_PER         (*(RwReg8 *)0x4200141BUL) /**< \brief (TC4) COUNT8 Period */
-#define REG_TC4_COUNT8_CC0         (*(RwReg8 *)0x4200141CUL) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
-#define REG_TC4_COUNT8_CC1         (*(RwReg8 *)0x4200141DUL) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
-#define REG_TC4_COUNT8_PERBUF      (*(RwReg8 *)0x4200142FUL) /**< \brief (TC4) COUNT8 Period Buffer */
-#define REG_TC4_COUNT8_CCBUF0      (*(RwReg8 *)0x42001430UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC4_COUNT8_CCBUF1      (*(RwReg8 *)0x42001431UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC4 peripheral ========== */
-#define TC4_CC_NUM                  2       
-#define TC4_DMAC_ID_MC_0            57
-#define TC4_DMAC_ID_MC_1            58
-#define TC4_DMAC_ID_MC_LSB          57
-#define TC4_DMAC_ID_MC_MSB          58
-#define TC4_DMAC_ID_MC_SIZE         2
-#define TC4_DMAC_ID_OVF             56       // Indexes of DMA Overflow trigger
-#define TC4_EXT                     0        // Coding of implemented extended features (keep 0 value)
-#define TC4_GCLK_ID                 30       // Index of Generic Clock
-#define TC4_MASTER_SLAVE_MODE       1        // TC type 0 : NA, 1 : Master, 2 : Slave
-#define TC4_OW_NUM                  2        // Number of Output Waveforms
-
-#endif /* _SAMD51_TC4_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc5.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc5.h
deleted file mode 100644
index 7e28247abb..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc5.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC5
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TC5_INSTANCE_
-#define _SAMD51_TC5_INSTANCE_
-
-/* ========== Register definition for TC5 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC5_CTRLA              (0x42001800) /**< \brief (TC5) Control A */
-#define REG_TC5_CTRLBCLR           (0x42001804) /**< \brief (TC5) Control B Clear */
-#define REG_TC5_CTRLBSET           (0x42001805) /**< \brief (TC5) Control B Set */
-#define REG_TC5_EVCTRL             (0x42001806) /**< \brief (TC5) Event Control */
-#define REG_TC5_INTENCLR           (0x42001808) /**< \brief (TC5) Interrupt Enable Clear */
-#define REG_TC5_INTENSET           (0x42001809) /**< \brief (TC5) Interrupt Enable Set */
-#define REG_TC5_INTFLAG            (0x4200180A) /**< \brief (TC5) Interrupt Flag Status and Clear */
-#define REG_TC5_STATUS             (0x4200180B) /**< \brief (TC5) Status */
-#define REG_TC5_WAVE               (0x4200180C) /**< \brief (TC5) Waveform Generation Control */
-#define REG_TC5_DRVCTRL            (0x4200180D) /**< \brief (TC5) Control C */
-#define REG_TC5_DBGCTRL            (0x4200180F) /**< \brief (TC5) Debug Control */
-#define REG_TC5_SYNCBUSY           (0x42001810) /**< \brief (TC5) Synchronization Status */
-#define REG_TC5_COUNT16_COUNT      (0x42001814) /**< \brief (TC5) COUNT16 Count */
-#define REG_TC5_COUNT16_CC0        (0x4200181C) /**< \brief (TC5) COUNT16 Compare and Capture 0 */
-#define REG_TC5_COUNT16_CC1        (0x4200181E) /**< \brief (TC5) COUNT16 Compare and Capture 1 */
-#define REG_TC5_COUNT16_CCBUF0     (0x42001830) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC5_COUNT16_CCBUF1     (0x42001832) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC5_COUNT32_COUNT      (0x42001814) /**< \brief (TC5) COUNT32 Count */
-#define REG_TC5_COUNT32_CC0        (0x4200181C) /**< \brief (TC5) COUNT32 Compare and Capture 0 */
-#define REG_TC5_COUNT32_CC1        (0x42001820) /**< \brief (TC5) COUNT32 Compare and Capture 1 */
-#define REG_TC5_COUNT32_CCBUF0     (0x42001830) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC5_COUNT32_CCBUF1     (0x42001834) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC5_COUNT8_COUNT       (0x42001814) /**< \brief (TC5) COUNT8 Count */
-#define REG_TC5_COUNT8_PER         (0x4200181B) /**< \brief (TC5) COUNT8 Period */
-#define REG_TC5_COUNT8_CC0         (0x4200181C) /**< \brief (TC5) COUNT8 Compare and Capture 0 */
-#define REG_TC5_COUNT8_CC1         (0x4200181D) /**< \brief (TC5) COUNT8 Compare and Capture 1 */
-#define REG_TC5_COUNT8_PERBUF      (0x4200182F) /**< \brief (TC5) COUNT8 Period Buffer */
-#define REG_TC5_COUNT8_CCBUF0      (0x42001830) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC5_COUNT8_CCBUF1      (0x42001831) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 1 */
-#else
-#define REG_TC5_CTRLA              (*(RwReg  *)0x42001800UL) /**< \brief (TC5) Control A */
-#define REG_TC5_CTRLBCLR           (*(RwReg8 *)0x42001804UL) /**< \brief (TC5) Control B Clear */
-#define REG_TC5_CTRLBSET           (*(RwReg8 *)0x42001805UL) /**< \brief (TC5) Control B Set */
-#define REG_TC5_EVCTRL             (*(RwReg16*)0x42001806UL) /**< \brief (TC5) Event Control */
-#define REG_TC5_INTENCLR           (*(RwReg8 *)0x42001808UL) /**< \brief (TC5) Interrupt Enable Clear */
-#define REG_TC5_INTENSET           (*(RwReg8 *)0x42001809UL) /**< \brief (TC5) Interrupt Enable Set */
-#define REG_TC5_INTFLAG            (*(RwReg8 *)0x4200180AUL) /**< \brief (TC5) Interrupt Flag Status and Clear */
-#define REG_TC5_STATUS             (*(RwReg8 *)0x4200180BUL) /**< \brief (TC5) Status */
-#define REG_TC5_WAVE               (*(RwReg8 *)0x4200180CUL) /**< \brief (TC5) Waveform Generation Control */
-#define REG_TC5_DRVCTRL            (*(RwReg8 *)0x4200180DUL) /**< \brief (TC5) Control C */
-#define REG_TC5_DBGCTRL            (*(RwReg8 *)0x4200180FUL) /**< \brief (TC5) Debug Control */
-#define REG_TC5_SYNCBUSY           (*(RoReg  *)0x42001810UL) /**< \brief (TC5) Synchronization Status */
-#define REG_TC5_COUNT16_COUNT      (*(RwReg16*)0x42001814UL) /**< \brief (TC5) COUNT16 Count */
-#define REG_TC5_COUNT16_CC0        (*(RwReg16*)0x4200181CUL) /**< \brief (TC5) COUNT16 Compare and Capture 0 */
-#define REG_TC5_COUNT16_CC1        (*(RwReg16*)0x4200181EUL) /**< \brief (TC5) COUNT16 Compare and Capture 1 */
-#define REG_TC5_COUNT16_CCBUF0     (*(RwReg16*)0x42001830UL) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC5_COUNT16_CCBUF1     (*(RwReg16*)0x42001832UL) /**< \brief (TC5) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC5_COUNT32_COUNT      (*(RwReg  *)0x42001814UL) /**< \brief (TC5) COUNT32 Count */
-#define REG_TC5_COUNT32_CC0        (*(RwReg  *)0x4200181CUL) /**< \brief (TC5) COUNT32 Compare and Capture 0 */
-#define REG_TC5_COUNT32_CC1        (*(RwReg  *)0x42001820UL) /**< \brief (TC5) COUNT32 Compare and Capture 1 */
-#define REG_TC5_COUNT32_CCBUF0     (*(RwReg  *)0x42001830UL) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC5_COUNT32_CCBUF1     (*(RwReg  *)0x42001834UL) /**< \brief (TC5) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC5_COUNT8_COUNT       (*(RwReg8 *)0x42001814UL) /**< \brief (TC5) COUNT8 Count */
-#define REG_TC5_COUNT8_PER         (*(RwReg8 *)0x4200181BUL) /**< \brief (TC5) COUNT8 Period */
-#define REG_TC5_COUNT8_CC0         (*(RwReg8 *)0x4200181CUL) /**< \brief (TC5) COUNT8 Compare and Capture 0 */
-#define REG_TC5_COUNT8_CC1         (*(RwReg8 *)0x4200181DUL) /**< \brief (TC5) COUNT8 Compare and Capture 1 */
-#define REG_TC5_COUNT8_PERBUF      (*(RwReg8 *)0x4200182FUL) /**< \brief (TC5) COUNT8 Period Buffer */
-#define REG_TC5_COUNT8_CCBUF0      (*(RwReg8 *)0x42001830UL) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC5_COUNT8_CCBUF1      (*(RwReg8 *)0x42001831UL) /**< \brief (TC5) COUNT8 Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC5 peripheral ========== */
-#define TC5_CC_NUM                  2       
-#define TC5_DMAC_ID_MC_0            60
-#define TC5_DMAC_ID_MC_1            61
-#define TC5_DMAC_ID_MC_LSB          60
-#define TC5_DMAC_ID_MC_MSB          61
-#define TC5_DMAC_ID_MC_SIZE         2
-#define TC5_DMAC_ID_OVF             59       // Indexes of DMA Overflow trigger
-#define TC5_EXT                     0        // Coding of implemented extended features (keep 0 value)
-#define TC5_GCLK_ID                 30       // Index of Generic Clock
-#define TC5_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave
-#define TC5_OW_NUM                  2        // Number of Output Waveforms
-
-#endif /* _SAMD51_TC5_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc6.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc6.h
deleted file mode 100644
index df6718fc82..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc6.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC6
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TC6_INSTANCE_
-#define _SAMD51_TC6_INSTANCE_
-
-/* ========== Register definition for TC6 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC6_CTRLA              (0x43001400) /**< \brief (TC6) Control A */
-#define REG_TC6_CTRLBCLR           (0x43001404) /**< \brief (TC6) Control B Clear */
-#define REG_TC6_CTRLBSET           (0x43001405) /**< \brief (TC6) Control B Set */
-#define REG_TC6_EVCTRL             (0x43001406) /**< \brief (TC6) Event Control */
-#define REG_TC6_INTENCLR           (0x43001408) /**< \brief (TC6) Interrupt Enable Clear */
-#define REG_TC6_INTENSET           (0x43001409) /**< \brief (TC6) Interrupt Enable Set */
-#define REG_TC6_INTFLAG            (0x4300140A) /**< \brief (TC6) Interrupt Flag Status and Clear */
-#define REG_TC6_STATUS             (0x4300140B) /**< \brief (TC6) Status */
-#define REG_TC6_WAVE               (0x4300140C) /**< \brief (TC6) Waveform Generation Control */
-#define REG_TC6_DRVCTRL            (0x4300140D) /**< \brief (TC6) Control C */
-#define REG_TC6_DBGCTRL            (0x4300140F) /**< \brief (TC6) Debug Control */
-#define REG_TC6_SYNCBUSY           (0x43001410) /**< \brief (TC6) Synchronization Status */
-#define REG_TC6_COUNT16_COUNT      (0x43001414) /**< \brief (TC6) COUNT16 Count */
-#define REG_TC6_COUNT16_CC0        (0x4300141C) /**< \brief (TC6) COUNT16 Compare and Capture 0 */
-#define REG_TC6_COUNT16_CC1        (0x4300141E) /**< \brief (TC6) COUNT16 Compare and Capture 1 */
-#define REG_TC6_COUNT16_CCBUF0     (0x43001430) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC6_COUNT16_CCBUF1     (0x43001432) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC6_COUNT32_COUNT      (0x43001414) /**< \brief (TC6) COUNT32 Count */
-#define REG_TC6_COUNT32_CC0        (0x4300141C) /**< \brief (TC6) COUNT32 Compare and Capture 0 */
-#define REG_TC6_COUNT32_CC1        (0x43001420) /**< \brief (TC6) COUNT32 Compare and Capture 1 */
-#define REG_TC6_COUNT32_CCBUF0     (0x43001430) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC6_COUNT32_CCBUF1     (0x43001434) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC6_COUNT8_COUNT       (0x43001414) /**< \brief (TC6) COUNT8 Count */
-#define REG_TC6_COUNT8_PER         (0x4300141B) /**< \brief (TC6) COUNT8 Period */
-#define REG_TC6_COUNT8_CC0         (0x4300141C) /**< \brief (TC6) COUNT8 Compare and Capture 0 */
-#define REG_TC6_COUNT8_CC1         (0x4300141D) /**< \brief (TC6) COUNT8 Compare and Capture 1 */
-#define REG_TC6_COUNT8_PERBUF      (0x4300142F) /**< \brief (TC6) COUNT8 Period Buffer */
-#define REG_TC6_COUNT8_CCBUF0      (0x43001430) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC6_COUNT8_CCBUF1      (0x43001431) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 1 */
-#else
-#define REG_TC6_CTRLA              (*(RwReg  *)0x43001400UL) /**< \brief (TC6) Control A */
-#define REG_TC6_CTRLBCLR           (*(RwReg8 *)0x43001404UL) /**< \brief (TC6) Control B Clear */
-#define REG_TC6_CTRLBSET           (*(RwReg8 *)0x43001405UL) /**< \brief (TC6) Control B Set */
-#define REG_TC6_EVCTRL             (*(RwReg16*)0x43001406UL) /**< \brief (TC6) Event Control */
-#define REG_TC6_INTENCLR           (*(RwReg8 *)0x43001408UL) /**< \brief (TC6) Interrupt Enable Clear */
-#define REG_TC6_INTENSET           (*(RwReg8 *)0x43001409UL) /**< \brief (TC6) Interrupt Enable Set */
-#define REG_TC6_INTFLAG            (*(RwReg8 *)0x4300140AUL) /**< \brief (TC6) Interrupt Flag Status and Clear */
-#define REG_TC6_STATUS             (*(RwReg8 *)0x4300140BUL) /**< \brief (TC6) Status */
-#define REG_TC6_WAVE               (*(RwReg8 *)0x4300140CUL) /**< \brief (TC6) Waveform Generation Control */
-#define REG_TC6_DRVCTRL            (*(RwReg8 *)0x4300140DUL) /**< \brief (TC6) Control C */
-#define REG_TC6_DBGCTRL            (*(RwReg8 *)0x4300140FUL) /**< \brief (TC6) Debug Control */
-#define REG_TC6_SYNCBUSY           (*(RoReg  *)0x43001410UL) /**< \brief (TC6) Synchronization Status */
-#define REG_TC6_COUNT16_COUNT      (*(RwReg16*)0x43001414UL) /**< \brief (TC6) COUNT16 Count */
-#define REG_TC6_COUNT16_CC0        (*(RwReg16*)0x4300141CUL) /**< \brief (TC6) COUNT16 Compare and Capture 0 */
-#define REG_TC6_COUNT16_CC1        (*(RwReg16*)0x4300141EUL) /**< \brief (TC6) COUNT16 Compare and Capture 1 */
-#define REG_TC6_COUNT16_CCBUF0     (*(RwReg16*)0x43001430UL) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC6_COUNT16_CCBUF1     (*(RwReg16*)0x43001432UL) /**< \brief (TC6) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC6_COUNT32_COUNT      (*(RwReg  *)0x43001414UL) /**< \brief (TC6) COUNT32 Count */
-#define REG_TC6_COUNT32_CC0        (*(RwReg  *)0x4300141CUL) /**< \brief (TC6) COUNT32 Compare and Capture 0 */
-#define REG_TC6_COUNT32_CC1        (*(RwReg  *)0x43001420UL) /**< \brief (TC6) COUNT32 Compare and Capture 1 */
-#define REG_TC6_COUNT32_CCBUF0     (*(RwReg  *)0x43001430UL) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC6_COUNT32_CCBUF1     (*(RwReg  *)0x43001434UL) /**< \brief (TC6) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC6_COUNT8_COUNT       (*(RwReg8 *)0x43001414UL) /**< \brief (TC6) COUNT8 Count */
-#define REG_TC6_COUNT8_PER         (*(RwReg8 *)0x4300141BUL) /**< \brief (TC6) COUNT8 Period */
-#define REG_TC6_COUNT8_CC0         (*(RwReg8 *)0x4300141CUL) /**< \brief (TC6) COUNT8 Compare and Capture 0 */
-#define REG_TC6_COUNT8_CC1         (*(RwReg8 *)0x4300141DUL) /**< \brief (TC6) COUNT8 Compare and Capture 1 */
-#define REG_TC6_COUNT8_PERBUF      (*(RwReg8 *)0x4300142FUL) /**< \brief (TC6) COUNT8 Period Buffer */
-#define REG_TC6_COUNT8_CCBUF0      (*(RwReg8 *)0x43001430UL) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC6_COUNT8_CCBUF1      (*(RwReg8 *)0x43001431UL) /**< \brief (TC6) COUNT8 Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC6 peripheral ========== */
-#define TC6_CC_NUM                  2       
-#define TC6_DMAC_ID_MC_0            63
-#define TC6_DMAC_ID_MC_1            64
-#define TC6_DMAC_ID_MC_LSB          63
-#define TC6_DMAC_ID_MC_MSB          64
-#define TC6_DMAC_ID_MC_SIZE         2
-#define TC6_DMAC_ID_OVF             62       // Indexes of DMA Overflow trigger
-#define TC6_EXT                     0        // Coding of implemented extended features (keep 0 value)
-#define TC6_GCLK_ID                 39       // Index of Generic Clock
-#define TC6_MASTER_SLAVE_MODE       1        // TC type 0 : NA, 1 : Master, 2 : Slave
-#define TC6_OW_NUM                  2        // Number of Output Waveforms
-
-#endif /* _SAMD51_TC6_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc7.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc7.h
deleted file mode 100644
index 3de53eeb5d..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tc7.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TC7
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TC7_INSTANCE_
-#define _SAMD51_TC7_INSTANCE_
-
-/* ========== Register definition for TC7 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC7_CTRLA              (0x43001800) /**< \brief (TC7) Control A */
-#define REG_TC7_CTRLBCLR           (0x43001804) /**< \brief (TC7) Control B Clear */
-#define REG_TC7_CTRLBSET           (0x43001805) /**< \brief (TC7) Control B Set */
-#define REG_TC7_EVCTRL             (0x43001806) /**< \brief (TC7) Event Control */
-#define REG_TC7_INTENCLR           (0x43001808) /**< \brief (TC7) Interrupt Enable Clear */
-#define REG_TC7_INTENSET           (0x43001809) /**< \brief (TC7) Interrupt Enable Set */
-#define REG_TC7_INTFLAG            (0x4300180A) /**< \brief (TC7) Interrupt Flag Status and Clear */
-#define REG_TC7_STATUS             (0x4300180B) /**< \brief (TC7) Status */
-#define REG_TC7_WAVE               (0x4300180C) /**< \brief (TC7) Waveform Generation Control */
-#define REG_TC7_DRVCTRL            (0x4300180D) /**< \brief (TC7) Control C */
-#define REG_TC7_DBGCTRL            (0x4300180F) /**< \brief (TC7) Debug Control */
-#define REG_TC7_SYNCBUSY           (0x43001810) /**< \brief (TC7) Synchronization Status */
-#define REG_TC7_COUNT16_COUNT      (0x43001814) /**< \brief (TC7) COUNT16 Count */
-#define REG_TC7_COUNT16_CC0        (0x4300181C) /**< \brief (TC7) COUNT16 Compare and Capture 0 */
-#define REG_TC7_COUNT16_CC1        (0x4300181E) /**< \brief (TC7) COUNT16 Compare and Capture 1 */
-#define REG_TC7_COUNT16_CCBUF0     (0x43001830) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC7_COUNT16_CCBUF1     (0x43001832) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC7_COUNT32_COUNT      (0x43001814) /**< \brief (TC7) COUNT32 Count */
-#define REG_TC7_COUNT32_CC0        (0x4300181C) /**< \brief (TC7) COUNT32 Compare and Capture 0 */
-#define REG_TC7_COUNT32_CC1        (0x43001820) /**< \brief (TC7) COUNT32 Compare and Capture 1 */
-#define REG_TC7_COUNT32_CCBUF0     (0x43001830) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC7_COUNT32_CCBUF1     (0x43001834) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC7_COUNT8_COUNT       (0x43001814) /**< \brief (TC7) COUNT8 Count */
-#define REG_TC7_COUNT8_PER         (0x4300181B) /**< \brief (TC7) COUNT8 Period */
-#define REG_TC7_COUNT8_CC0         (0x4300181C) /**< \brief (TC7) COUNT8 Compare and Capture 0 */
-#define REG_TC7_COUNT8_CC1         (0x4300181D) /**< \brief (TC7) COUNT8 Compare and Capture 1 */
-#define REG_TC7_COUNT8_PERBUF      (0x4300182F) /**< \brief (TC7) COUNT8 Period Buffer */
-#define REG_TC7_COUNT8_CCBUF0      (0x43001830) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC7_COUNT8_CCBUF1      (0x43001831) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 1 */
-#else
-#define REG_TC7_CTRLA              (*(RwReg  *)0x43001800UL) /**< \brief (TC7) Control A */
-#define REG_TC7_CTRLBCLR           (*(RwReg8 *)0x43001804UL) /**< \brief (TC7) Control B Clear */
-#define REG_TC7_CTRLBSET           (*(RwReg8 *)0x43001805UL) /**< \brief (TC7) Control B Set */
-#define REG_TC7_EVCTRL             (*(RwReg16*)0x43001806UL) /**< \brief (TC7) Event Control */
-#define REG_TC7_INTENCLR           (*(RwReg8 *)0x43001808UL) /**< \brief (TC7) Interrupt Enable Clear */
-#define REG_TC7_INTENSET           (*(RwReg8 *)0x43001809UL) /**< \brief (TC7) Interrupt Enable Set */
-#define REG_TC7_INTFLAG            (*(RwReg8 *)0x4300180AUL) /**< \brief (TC7) Interrupt Flag Status and Clear */
-#define REG_TC7_STATUS             (*(RwReg8 *)0x4300180BUL) /**< \brief (TC7) Status */
-#define REG_TC7_WAVE               (*(RwReg8 *)0x4300180CUL) /**< \brief (TC7) Waveform Generation Control */
-#define REG_TC7_DRVCTRL            (*(RwReg8 *)0x4300180DUL) /**< \brief (TC7) Control C */
-#define REG_TC7_DBGCTRL            (*(RwReg8 *)0x4300180FUL) /**< \brief (TC7) Debug Control */
-#define REG_TC7_SYNCBUSY           (*(RoReg  *)0x43001810UL) /**< \brief (TC7) Synchronization Status */
-#define REG_TC7_COUNT16_COUNT      (*(RwReg16*)0x43001814UL) /**< \brief (TC7) COUNT16 Count */
-#define REG_TC7_COUNT16_CC0        (*(RwReg16*)0x4300181CUL) /**< \brief (TC7) COUNT16 Compare and Capture 0 */
-#define REG_TC7_COUNT16_CC1        (*(RwReg16*)0x4300181EUL) /**< \brief (TC7) COUNT16 Compare and Capture 1 */
-#define REG_TC7_COUNT16_CCBUF0     (*(RwReg16*)0x43001830UL) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC7_COUNT16_CCBUF1     (*(RwReg16*)0x43001832UL) /**< \brief (TC7) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC7_COUNT32_COUNT      (*(RwReg  *)0x43001814UL) /**< \brief (TC7) COUNT32 Count */
-#define REG_TC7_COUNT32_CC0        (*(RwReg  *)0x4300181CUL) /**< \brief (TC7) COUNT32 Compare and Capture 0 */
-#define REG_TC7_COUNT32_CC1        (*(RwReg  *)0x43001820UL) /**< \brief (TC7) COUNT32 Compare and Capture 1 */
-#define REG_TC7_COUNT32_CCBUF0     (*(RwReg  *)0x43001830UL) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC7_COUNT32_CCBUF1     (*(RwReg  *)0x43001834UL) /**< \brief (TC7) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC7_COUNT8_COUNT       (*(RwReg8 *)0x43001814UL) /**< \brief (TC7) COUNT8 Count */
-#define REG_TC7_COUNT8_PER         (*(RwReg8 *)0x4300181BUL) /**< \brief (TC7) COUNT8 Period */
-#define REG_TC7_COUNT8_CC0         (*(RwReg8 *)0x4300181CUL) /**< \brief (TC7) COUNT8 Compare and Capture 0 */
-#define REG_TC7_COUNT8_CC1         (*(RwReg8 *)0x4300181DUL) /**< \brief (TC7) COUNT8 Compare and Capture 1 */
-#define REG_TC7_COUNT8_PERBUF      (*(RwReg8 *)0x4300182FUL) /**< \brief (TC7) COUNT8 Period Buffer */
-#define REG_TC7_COUNT8_CCBUF0      (*(RwReg8 *)0x43001830UL) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC7_COUNT8_CCBUF1      (*(RwReg8 *)0x43001831UL) /**< \brief (TC7) COUNT8 Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC7 peripheral ========== */
-#define TC7_CC_NUM                  2       
-#define TC7_DMAC_ID_MC_0            66
-#define TC7_DMAC_ID_MC_1            67
-#define TC7_DMAC_ID_MC_LSB          66
-#define TC7_DMAC_ID_MC_MSB          67
-#define TC7_DMAC_ID_MC_SIZE         2
-#define TC7_DMAC_ID_OVF             65       // Indexes of DMA Overflow trigger
-#define TC7_EXT                     0        // Coding of implemented extended features (keep 0 value)
-#define TC7_GCLK_ID                 39       // Index of Generic Clock
-#define TC7_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave
-#define TC7_OW_NUM                  2        // Number of Output Waveforms
-
-#endif /* _SAMD51_TC7_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc0.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc0.h
deleted file mode 100644
index edcfc368eb..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc0.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TCC0
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TCC0_INSTANCE_
-#define _SAMD51_TCC0_INSTANCE_
-
-/* ========== Register definition for TCC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TCC0_CTRLA             (0x41016000) /**< \brief (TCC0) Control A */
-#define REG_TCC0_CTRLBCLR          (0x41016004) /**< \brief (TCC0) Control B Clear */
-#define REG_TCC0_CTRLBSET          (0x41016005) /**< \brief (TCC0) Control B Set */
-#define REG_TCC0_SYNCBUSY          (0x41016008) /**< \brief (TCC0) Synchronization Busy */
-#define REG_TCC0_FCTRLA            (0x4101600C) /**< \brief (TCC0) Recoverable Fault A Configuration */
-#define REG_TCC0_FCTRLB            (0x41016010) /**< \brief (TCC0) Recoverable Fault B Configuration */
-#define REG_TCC0_WEXCTRL           (0x41016014) /**< \brief (TCC0) Waveform Extension Configuration */
-#define REG_TCC0_DRVCTRL           (0x41016018) /**< \brief (TCC0) Driver Control */
-#define REG_TCC0_DBGCTRL           (0x4101601E) /**< \brief (TCC0) Debug Control */
-#define REG_TCC0_EVCTRL            (0x41016020) /**< \brief (TCC0) Event Control */
-#define REG_TCC0_INTENCLR          (0x41016024) /**< \brief (TCC0) Interrupt Enable Clear */
-#define REG_TCC0_INTENSET          (0x41016028) /**< \brief (TCC0) Interrupt Enable Set */
-#define REG_TCC0_INTFLAG           (0x4101602C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
-#define REG_TCC0_STATUS            (0x41016030) /**< \brief (TCC0) Status */
-#define REG_TCC0_COUNT             (0x41016034) /**< \brief (TCC0) Count */
-#define REG_TCC0_PATT              (0x41016038) /**< \brief (TCC0) Pattern */
-#define REG_TCC0_WAVE              (0x4101603C) /**< \brief (TCC0) Waveform Control */
-#define REG_TCC0_PER               (0x41016040) /**< \brief (TCC0) Period */
-#define REG_TCC0_CC0               (0x41016044) /**< \brief (TCC0) Compare and Capture 0 */
-#define REG_TCC0_CC1               (0x41016048) /**< \brief (TCC0) Compare and Capture 1 */
-#define REG_TCC0_CC2               (0x4101604C) /**< \brief (TCC0) Compare and Capture 2 */
-#define REG_TCC0_CC3               (0x41016050) /**< \brief (TCC0) Compare and Capture 3 */
-#define REG_TCC0_CC4               (0x41016054) /**< \brief (TCC0) Compare and Capture 4 */
-#define REG_TCC0_CC5               (0x41016058) /**< \brief (TCC0) Compare and Capture 5 */
-#define REG_TCC0_PATTBUF           (0x41016064) /**< \brief (TCC0) Pattern Buffer */
-#define REG_TCC0_PERBUF            (0x4101606C) /**< \brief (TCC0) Period Buffer */
-#define REG_TCC0_CCBUF0            (0x41016070) /**< \brief (TCC0) Compare and Capture Buffer 0 */
-#define REG_TCC0_CCBUF1            (0x41016074) /**< \brief (TCC0) Compare and Capture Buffer 1 */
-#define REG_TCC0_CCBUF2            (0x41016078) /**< \brief (TCC0) Compare and Capture Buffer 2 */
-#define REG_TCC0_CCBUF3            (0x4101607C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
-#define REG_TCC0_CCBUF4            (0x41016080) /**< \brief (TCC0) Compare and Capture Buffer 4 */
-#define REG_TCC0_CCBUF5            (0x41016084) /**< \brief (TCC0) Compare and Capture Buffer 5 */
-#else
-#define REG_TCC0_CTRLA             (*(RwReg  *)0x41016000UL) /**< \brief (TCC0) Control A */
-#define REG_TCC0_CTRLBCLR          (*(RwReg8 *)0x41016004UL) /**< \brief (TCC0) Control B Clear */
-#define REG_TCC0_CTRLBSET          (*(RwReg8 *)0x41016005UL) /**< \brief (TCC0) Control B Set */
-#define REG_TCC0_SYNCBUSY          (*(RoReg  *)0x41016008UL) /**< \brief (TCC0) Synchronization Busy */
-#define REG_TCC0_FCTRLA            (*(RwReg  *)0x4101600CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
-#define REG_TCC0_FCTRLB            (*(RwReg  *)0x41016010UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
-#define REG_TCC0_WEXCTRL           (*(RwReg  *)0x41016014UL) /**< \brief (TCC0) Waveform Extension Configuration */
-#define REG_TCC0_DRVCTRL           (*(RwReg  *)0x41016018UL) /**< \brief (TCC0) Driver Control */
-#define REG_TCC0_DBGCTRL           (*(RwReg8 *)0x4101601EUL) /**< \brief (TCC0) Debug Control */
-#define REG_TCC0_EVCTRL            (*(RwReg  *)0x41016020UL) /**< \brief (TCC0) Event Control */
-#define REG_TCC0_INTENCLR          (*(RwReg  *)0x41016024UL) /**< \brief (TCC0) Interrupt Enable Clear */
-#define REG_TCC0_INTENSET          (*(RwReg  *)0x41016028UL) /**< \brief (TCC0) Interrupt Enable Set */
-#define REG_TCC0_INTFLAG           (*(RwReg  *)0x4101602CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
-#define REG_TCC0_STATUS            (*(RwReg  *)0x41016030UL) /**< \brief (TCC0) Status */
-#define REG_TCC0_COUNT             (*(RwReg  *)0x41016034UL) /**< \brief (TCC0) Count */
-#define REG_TCC0_PATT              (*(RwReg16*)0x41016038UL) /**< \brief (TCC0) Pattern */
-#define REG_TCC0_WAVE              (*(RwReg  *)0x4101603CUL) /**< \brief (TCC0) Waveform Control */
-#define REG_TCC0_PER               (*(RwReg  *)0x41016040UL) /**< \brief (TCC0) Period */
-#define REG_TCC0_CC0               (*(RwReg  *)0x41016044UL) /**< \brief (TCC0) Compare and Capture 0 */
-#define REG_TCC0_CC1               (*(RwReg  *)0x41016048UL) /**< \brief (TCC0) Compare and Capture 1 */
-#define REG_TCC0_CC2               (*(RwReg  *)0x4101604CUL) /**< \brief (TCC0) Compare and Capture 2 */
-#define REG_TCC0_CC3               (*(RwReg  *)0x41016050UL) /**< \brief (TCC0) Compare and Capture 3 */
-#define REG_TCC0_CC4               (*(RwReg  *)0x41016054UL) /**< \brief (TCC0) Compare and Capture 4 */
-#define REG_TCC0_CC5               (*(RwReg  *)0x41016058UL) /**< \brief (TCC0) Compare and Capture 5 */
-#define REG_TCC0_PATTBUF           (*(RwReg16*)0x41016064UL) /**< \brief (TCC0) Pattern Buffer */
-#define REG_TCC0_PERBUF            (*(RwReg  *)0x4101606CUL) /**< \brief (TCC0) Period Buffer */
-#define REG_TCC0_CCBUF0            (*(RwReg  *)0x41016070UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
-#define REG_TCC0_CCBUF1            (*(RwReg  *)0x41016074UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
-#define REG_TCC0_CCBUF2            (*(RwReg  *)0x41016078UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
-#define REG_TCC0_CCBUF3            (*(RwReg  *)0x4101607CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
-#define REG_TCC0_CCBUF4            (*(RwReg  *)0x41016080UL) /**< \brief (TCC0) Compare and Capture Buffer 4 */
-#define REG_TCC0_CCBUF5            (*(RwReg  *)0x41016084UL) /**< \brief (TCC0) Compare and Capture Buffer 5 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TCC0 peripheral ========== */
-#define TCC0_CC_NUM                 6        // Number of Compare/Capture units
-#define TCC0_DITHERING              1        // Dithering feature implemented
-#define TCC0_DMAC_ID_MC_0           23
-#define TCC0_DMAC_ID_MC_1           24
-#define TCC0_DMAC_ID_MC_2           25
-#define TCC0_DMAC_ID_MC_3           26
-#define TCC0_DMAC_ID_MC_4           27
-#define TCC0_DMAC_ID_MC_5           28
-#define TCC0_DMAC_ID_MC_LSB         23
-#define TCC0_DMAC_ID_MC_MSB         28
-#define TCC0_DMAC_ID_MC_SIZE        6
-#define TCC0_DMAC_ID_OVF            22       // DMA overflow/underflow/retrigger trigger
-#define TCC0_DTI                    1        // Dead-Time-Insertion feature implemented
-#define TCC0_EXT                    31       // Coding of implemented extended features
-#define TCC0_GCLK_ID                25       // Index of Generic Clock
-#define TCC0_MASTER_SLAVE_MODE      1        // TCC type 0 : NA, 1 : Master, 2 : Slave
-#define TCC0_OTMX                   1        // Output Matrix feature implemented
-#define TCC0_OW_NUM                 8        // Number of Output Waveforms
-#define TCC0_PG                     1        // Pattern Generation feature implemented
-#define TCC0_SIZE                   24      
-#define TCC0_SWAP                   1        // DTI outputs swap feature implemented
-
-#endif /* _SAMD51_TCC0_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc1.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc1.h
deleted file mode 100644
index 0c9ce3e881..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc1.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TCC1
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TCC1_INSTANCE_
-#define _SAMD51_TCC1_INSTANCE_
-
-/* ========== Register definition for TCC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TCC1_CTRLA             (0x41018000) /**< \brief (TCC1) Control A */
-#define REG_TCC1_CTRLBCLR          (0x41018004) /**< \brief (TCC1) Control B Clear */
-#define REG_TCC1_CTRLBSET          (0x41018005) /**< \brief (TCC1) Control B Set */
-#define REG_TCC1_SYNCBUSY          (0x41018008) /**< \brief (TCC1) Synchronization Busy */
-#define REG_TCC1_FCTRLA            (0x4101800C) /**< \brief (TCC1) Recoverable Fault A Configuration */
-#define REG_TCC1_FCTRLB            (0x41018010) /**< \brief (TCC1) Recoverable Fault B Configuration */
-#define REG_TCC1_WEXCTRL           (0x41018014) /**< \brief (TCC1) Waveform Extension Configuration */
-#define REG_TCC1_DRVCTRL           (0x41018018) /**< \brief (TCC1) Driver Control */
-#define REG_TCC1_DBGCTRL           (0x4101801E) /**< \brief (TCC1) Debug Control */
-#define REG_TCC1_EVCTRL            (0x41018020) /**< \brief (TCC1) Event Control */
-#define REG_TCC1_INTENCLR          (0x41018024) /**< \brief (TCC1) Interrupt Enable Clear */
-#define REG_TCC1_INTENSET          (0x41018028) /**< \brief (TCC1) Interrupt Enable Set */
-#define REG_TCC1_INTFLAG           (0x4101802C) /**< \brief (TCC1) Interrupt Flag Status and Clear */
-#define REG_TCC1_STATUS            (0x41018030) /**< \brief (TCC1) Status */
-#define REG_TCC1_COUNT             (0x41018034) /**< \brief (TCC1) Count */
-#define REG_TCC1_PATT              (0x41018038) /**< \brief (TCC1) Pattern */
-#define REG_TCC1_WAVE              (0x4101803C) /**< \brief (TCC1) Waveform Control */
-#define REG_TCC1_PER               (0x41018040) /**< \brief (TCC1) Period */
-#define REG_TCC1_CC0               (0x41018044) /**< \brief (TCC1) Compare and Capture 0 */
-#define REG_TCC1_CC1               (0x41018048) /**< \brief (TCC1) Compare and Capture 1 */
-#define REG_TCC1_CC2               (0x4101804C) /**< \brief (TCC1) Compare and Capture 2 */
-#define REG_TCC1_CC3               (0x41018050) /**< \brief (TCC1) Compare and Capture 3 */
-#define REG_TCC1_PATTBUF           (0x41018064) /**< \brief (TCC1) Pattern Buffer */
-#define REG_TCC1_PERBUF            (0x4101806C) /**< \brief (TCC1) Period Buffer */
-#define REG_TCC1_CCBUF0            (0x41018070) /**< \brief (TCC1) Compare and Capture Buffer 0 */
-#define REG_TCC1_CCBUF1            (0x41018074) /**< \brief (TCC1) Compare and Capture Buffer 1 */
-#define REG_TCC1_CCBUF2            (0x41018078) /**< \brief (TCC1) Compare and Capture Buffer 2 */
-#define REG_TCC1_CCBUF3            (0x4101807C) /**< \brief (TCC1) Compare and Capture Buffer 3 */
-#else
-#define REG_TCC1_CTRLA             (*(RwReg  *)0x41018000UL) /**< \brief (TCC1) Control A */
-#define REG_TCC1_CTRLBCLR          (*(RwReg8 *)0x41018004UL) /**< \brief (TCC1) Control B Clear */
-#define REG_TCC1_CTRLBSET          (*(RwReg8 *)0x41018005UL) /**< \brief (TCC1) Control B Set */
-#define REG_TCC1_SYNCBUSY          (*(RoReg  *)0x41018008UL) /**< \brief (TCC1) Synchronization Busy */
-#define REG_TCC1_FCTRLA            (*(RwReg  *)0x4101800CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */
-#define REG_TCC1_FCTRLB            (*(RwReg  *)0x41018010UL) /**< \brief (TCC1) Recoverable Fault B Configuration */
-#define REG_TCC1_WEXCTRL           (*(RwReg  *)0x41018014UL) /**< \brief (TCC1) Waveform Extension Configuration */
-#define REG_TCC1_DRVCTRL           (*(RwReg  *)0x41018018UL) /**< \brief (TCC1) Driver Control */
-#define REG_TCC1_DBGCTRL           (*(RwReg8 *)0x4101801EUL) /**< \brief (TCC1) Debug Control */
-#define REG_TCC1_EVCTRL            (*(RwReg  *)0x41018020UL) /**< \brief (TCC1) Event Control */
-#define REG_TCC1_INTENCLR          (*(RwReg  *)0x41018024UL) /**< \brief (TCC1) Interrupt Enable Clear */
-#define REG_TCC1_INTENSET          (*(RwReg  *)0x41018028UL) /**< \brief (TCC1) Interrupt Enable Set */
-#define REG_TCC1_INTFLAG           (*(RwReg  *)0x4101802CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */
-#define REG_TCC1_STATUS            (*(RwReg  *)0x41018030UL) /**< \brief (TCC1) Status */
-#define REG_TCC1_COUNT             (*(RwReg  *)0x41018034UL) /**< \brief (TCC1) Count */
-#define REG_TCC1_PATT              (*(RwReg16*)0x41018038UL) /**< \brief (TCC1) Pattern */
-#define REG_TCC1_WAVE              (*(RwReg  *)0x4101803CUL) /**< \brief (TCC1) Waveform Control */
-#define REG_TCC1_PER               (*(RwReg  *)0x41018040UL) /**< \brief (TCC1) Period */
-#define REG_TCC1_CC0               (*(RwReg  *)0x41018044UL) /**< \brief (TCC1) Compare and Capture 0 */
-#define REG_TCC1_CC1               (*(RwReg  *)0x41018048UL) /**< \brief (TCC1) Compare and Capture 1 */
-#define REG_TCC1_CC2               (*(RwReg  *)0x4101804CUL) /**< \brief (TCC1) Compare and Capture 2 */
-#define REG_TCC1_CC3               (*(RwReg  *)0x41018050UL) /**< \brief (TCC1) Compare and Capture 3 */
-#define REG_TCC1_PATTBUF           (*(RwReg16*)0x41018064UL) /**< \brief (TCC1) Pattern Buffer */
-#define REG_TCC1_PERBUF            (*(RwReg  *)0x4101806CUL) /**< \brief (TCC1) Period Buffer */
-#define REG_TCC1_CCBUF0            (*(RwReg  *)0x41018070UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */
-#define REG_TCC1_CCBUF1            (*(RwReg  *)0x41018074UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */
-#define REG_TCC1_CCBUF2            (*(RwReg  *)0x41018078UL) /**< \brief (TCC1) Compare and Capture Buffer 2 */
-#define REG_TCC1_CCBUF3            (*(RwReg  *)0x4101807CUL) /**< \brief (TCC1) Compare and Capture Buffer 3 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TCC1 peripheral ========== */
-#define TCC1_CC_NUM                 4        // Number of Compare/Capture units
-#define TCC1_DITHERING              1        // Dithering feature implemented
-#define TCC1_DMAC_ID_MC_0           30
-#define TCC1_DMAC_ID_MC_1           31
-#define TCC1_DMAC_ID_MC_2           32
-#define TCC1_DMAC_ID_MC_3           33
-#define TCC1_DMAC_ID_MC_LSB         30
-#define TCC1_DMAC_ID_MC_MSB         33
-#define TCC1_DMAC_ID_MC_SIZE        4
-#define TCC1_DMAC_ID_OVF            29       // DMA overflow/underflow/retrigger trigger
-#define TCC1_DTI                    1        // Dead-Time-Insertion feature implemented
-#define TCC1_EXT                    31       // Coding of implemented extended features
-#define TCC1_GCLK_ID                25       // Index of Generic Clock
-#define TCC1_MASTER_SLAVE_MODE      2        // TCC type 0 : NA, 1 : Master, 2 : Slave
-#define TCC1_OTMX                   1        // Output Matrix feature implemented
-#define TCC1_OW_NUM                 8        // Number of Output Waveforms
-#define TCC1_PG                     1        // Pattern Generation feature implemented
-#define TCC1_SIZE                   24      
-#define TCC1_SWAP                   1        // DTI outputs swap feature implemented
-
-#endif /* _SAMD51_TCC1_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc2.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc2.h
deleted file mode 100644
index 31f86e2de5..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc2.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TCC2
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TCC2_INSTANCE_
-#define _SAMD51_TCC2_INSTANCE_
-
-/* ========== Register definition for TCC2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TCC2_CTRLA             (0x42000C00) /**< \brief (TCC2) Control A */
-#define REG_TCC2_CTRLBCLR          (0x42000C04) /**< \brief (TCC2) Control B Clear */
-#define REG_TCC2_CTRLBSET          (0x42000C05) /**< \brief (TCC2) Control B Set */
-#define REG_TCC2_SYNCBUSY          (0x42000C08) /**< \brief (TCC2) Synchronization Busy */
-#define REG_TCC2_FCTRLA            (0x42000C0C) /**< \brief (TCC2) Recoverable Fault A Configuration */
-#define REG_TCC2_FCTRLB            (0x42000C10) /**< \brief (TCC2) Recoverable Fault B Configuration */
-#define REG_TCC2_WEXCTRL           (0x42000C14) /**< \brief (TCC2) Waveform Extension Configuration */
-#define REG_TCC2_DRVCTRL           (0x42000C18) /**< \brief (TCC2) Driver Control */
-#define REG_TCC2_DBGCTRL           (0x42000C1E) /**< \brief (TCC2) Debug Control */
-#define REG_TCC2_EVCTRL            (0x42000C20) /**< \brief (TCC2) Event Control */
-#define REG_TCC2_INTENCLR          (0x42000C24) /**< \brief (TCC2) Interrupt Enable Clear */
-#define REG_TCC2_INTENSET          (0x42000C28) /**< \brief (TCC2) Interrupt Enable Set */
-#define REG_TCC2_INTFLAG           (0x42000C2C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
-#define REG_TCC2_STATUS            (0x42000C30) /**< \brief (TCC2) Status */
-#define REG_TCC2_COUNT             (0x42000C34) /**< \brief (TCC2) Count */
-#define REG_TCC2_WAVE              (0x42000C3C) /**< \brief (TCC2) Waveform Control */
-#define REG_TCC2_PER               (0x42000C40) /**< \brief (TCC2) Period */
-#define REG_TCC2_CC0               (0x42000C44) /**< \brief (TCC2) Compare and Capture 0 */
-#define REG_TCC2_CC1               (0x42000C48) /**< \brief (TCC2) Compare and Capture 1 */
-#define REG_TCC2_CC2               (0x42000C4C) /**< \brief (TCC2) Compare and Capture 2 */
-#define REG_TCC2_PERBUF            (0x42000C6C) /**< \brief (TCC2) Period Buffer */
-#define REG_TCC2_CCBUF0            (0x42000C70) /**< \brief (TCC2) Compare and Capture Buffer 0 */
-#define REG_TCC2_CCBUF1            (0x42000C74) /**< \brief (TCC2) Compare and Capture Buffer 1 */
-#define REG_TCC2_CCBUF2            (0x42000C78) /**< \brief (TCC2) Compare and Capture Buffer 2 */
-#else
-#define REG_TCC2_CTRLA             (*(RwReg  *)0x42000C00UL) /**< \brief (TCC2) Control A */
-#define REG_TCC2_CTRLBCLR          (*(RwReg8 *)0x42000C04UL) /**< \brief (TCC2) Control B Clear */
-#define REG_TCC2_CTRLBSET          (*(RwReg8 *)0x42000C05UL) /**< \brief (TCC2) Control B Set */
-#define REG_TCC2_SYNCBUSY          (*(RoReg  *)0x42000C08UL) /**< \brief (TCC2) Synchronization Busy */
-#define REG_TCC2_FCTRLA            (*(RwReg  *)0x42000C0CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
-#define REG_TCC2_FCTRLB            (*(RwReg  *)0x42000C10UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
-#define REG_TCC2_WEXCTRL           (*(RwReg  *)0x42000C14UL) /**< \brief (TCC2) Waveform Extension Configuration */
-#define REG_TCC2_DRVCTRL           (*(RwReg  *)0x42000C18UL) /**< \brief (TCC2) Driver Control */
-#define REG_TCC2_DBGCTRL           (*(RwReg8 *)0x42000C1EUL) /**< \brief (TCC2) Debug Control */
-#define REG_TCC2_EVCTRL            (*(RwReg  *)0x42000C20UL) /**< \brief (TCC2) Event Control */
-#define REG_TCC2_INTENCLR          (*(RwReg  *)0x42000C24UL) /**< \brief (TCC2) Interrupt Enable Clear */
-#define REG_TCC2_INTENSET          (*(RwReg  *)0x42000C28UL) /**< \brief (TCC2) Interrupt Enable Set */
-#define REG_TCC2_INTFLAG           (*(RwReg  *)0x42000C2CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
-#define REG_TCC2_STATUS            (*(RwReg  *)0x42000C30UL) /**< \brief (TCC2) Status */
-#define REG_TCC2_COUNT             (*(RwReg  *)0x42000C34UL) /**< \brief (TCC2) Count */
-#define REG_TCC2_WAVE              (*(RwReg  *)0x42000C3CUL) /**< \brief (TCC2) Waveform Control */
-#define REG_TCC2_PER               (*(RwReg  *)0x42000C40UL) /**< \brief (TCC2) Period */
-#define REG_TCC2_CC0               (*(RwReg  *)0x42000C44UL) /**< \brief (TCC2) Compare and Capture 0 */
-#define REG_TCC2_CC1               (*(RwReg  *)0x42000C48UL) /**< \brief (TCC2) Compare and Capture 1 */
-#define REG_TCC2_CC2               (*(RwReg  *)0x42000C4CUL) /**< \brief (TCC2) Compare and Capture 2 */
-#define REG_TCC2_PERBUF            (*(RwReg  *)0x42000C6CUL) /**< \brief (TCC2) Period Buffer */
-#define REG_TCC2_CCBUF0            (*(RwReg  *)0x42000C70UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
-#define REG_TCC2_CCBUF1            (*(RwReg  *)0x42000C74UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
-#define REG_TCC2_CCBUF2            (*(RwReg  *)0x42000C78UL) /**< \brief (TCC2) Compare and Capture Buffer 2 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TCC2 peripheral ========== */
-#define TCC2_CC_NUM                 3        // Number of Compare/Capture units
-#define TCC2_DITHERING              0        // Dithering feature implemented
-#define TCC2_DMAC_ID_MC_0           35
-#define TCC2_DMAC_ID_MC_1           36
-#define TCC2_DMAC_ID_MC_2           37
-#define TCC2_DMAC_ID_MC_LSB         35
-#define TCC2_DMAC_ID_MC_MSB         37
-#define TCC2_DMAC_ID_MC_SIZE        3
-#define TCC2_DMAC_ID_OVF            34       // DMA overflow/underflow/retrigger trigger
-#define TCC2_DTI                    0        // Dead-Time-Insertion feature implemented
-#define TCC2_EXT                    1        // Coding of implemented extended features
-#define TCC2_GCLK_ID                29       // Index of Generic Clock
-#define TCC2_MASTER_SLAVE_MODE      0        // TCC type 0 : NA, 1 : Master, 2 : Slave
-#define TCC2_OTMX                   1        // Output Matrix feature implemented
-#define TCC2_OW_NUM                 3        // Number of Output Waveforms
-#define TCC2_PG                     0        // Pattern Generation feature implemented
-#define TCC2_SIZE                   16      
-#define TCC2_SWAP                   0        // DTI outputs swap feature implemented
-
-#endif /* _SAMD51_TCC2_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc3.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc3.h
deleted file mode 100644
index f492436f65..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc3.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TCC3
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TCC3_INSTANCE_
-#define _SAMD51_TCC3_INSTANCE_
-
-/* ========== Register definition for TCC3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TCC3_CTRLA             (0x42001000) /**< \brief (TCC3) Control A */
-#define REG_TCC3_CTRLBCLR          (0x42001004) /**< \brief (TCC3) Control B Clear */
-#define REG_TCC3_CTRLBSET          (0x42001005) /**< \brief (TCC3) Control B Set */
-#define REG_TCC3_SYNCBUSY          (0x42001008) /**< \brief (TCC3) Synchronization Busy */
-#define REG_TCC3_FCTRLA            (0x4200100C) /**< \brief (TCC3) Recoverable Fault A Configuration */
-#define REG_TCC3_FCTRLB            (0x42001010) /**< \brief (TCC3) Recoverable Fault B Configuration */
-#define REG_TCC3_DRVCTRL           (0x42001018) /**< \brief (TCC3) Driver Control */
-#define REG_TCC3_DBGCTRL           (0x4200101E) /**< \brief (TCC3) Debug Control */
-#define REG_TCC3_EVCTRL            (0x42001020) /**< \brief (TCC3) Event Control */
-#define REG_TCC3_INTENCLR          (0x42001024) /**< \brief (TCC3) Interrupt Enable Clear */
-#define REG_TCC3_INTENSET          (0x42001028) /**< \brief (TCC3) Interrupt Enable Set */
-#define REG_TCC3_INTFLAG           (0x4200102C) /**< \brief (TCC3) Interrupt Flag Status and Clear */
-#define REG_TCC3_STATUS            (0x42001030) /**< \brief (TCC3) Status */
-#define REG_TCC3_COUNT             (0x42001034) /**< \brief (TCC3) Count */
-#define REG_TCC3_WAVE              (0x4200103C) /**< \brief (TCC3) Waveform Control */
-#define REG_TCC3_PER               (0x42001040) /**< \brief (TCC3) Period */
-#define REG_TCC3_CC0               (0x42001044) /**< \brief (TCC3) Compare and Capture 0 */
-#define REG_TCC3_CC1               (0x42001048) /**< \brief (TCC3) Compare and Capture 1 */
-#define REG_TCC3_PERBUF            (0x4200106C) /**< \brief (TCC3) Period Buffer */
-#define REG_TCC3_CCBUF0            (0x42001070) /**< \brief (TCC3) Compare and Capture Buffer 0 */
-#define REG_TCC3_CCBUF1            (0x42001074) /**< \brief (TCC3) Compare and Capture Buffer 1 */
-#else
-#define REG_TCC3_CTRLA             (*(RwReg  *)0x42001000UL) /**< \brief (TCC3) Control A */
-#define REG_TCC3_CTRLBCLR          (*(RwReg8 *)0x42001004UL) /**< \brief (TCC3) Control B Clear */
-#define REG_TCC3_CTRLBSET          (*(RwReg8 *)0x42001005UL) /**< \brief (TCC3) Control B Set */
-#define REG_TCC3_SYNCBUSY          (*(RoReg  *)0x42001008UL) /**< \brief (TCC3) Synchronization Busy */
-#define REG_TCC3_FCTRLA            (*(RwReg  *)0x4200100CUL) /**< \brief (TCC3) Recoverable Fault A Configuration */
-#define REG_TCC3_FCTRLB            (*(RwReg  *)0x42001010UL) /**< \brief (TCC3) Recoverable Fault B Configuration */
-#define REG_TCC3_DRVCTRL           (*(RwReg  *)0x42001018UL) /**< \brief (TCC3) Driver Control */
-#define REG_TCC3_DBGCTRL           (*(RwReg8 *)0x4200101EUL) /**< \brief (TCC3) Debug Control */
-#define REG_TCC3_EVCTRL            (*(RwReg  *)0x42001020UL) /**< \brief (TCC3) Event Control */
-#define REG_TCC3_INTENCLR          (*(RwReg  *)0x42001024UL) /**< \brief (TCC3) Interrupt Enable Clear */
-#define REG_TCC3_INTENSET          (*(RwReg  *)0x42001028UL) /**< \brief (TCC3) Interrupt Enable Set */
-#define REG_TCC3_INTFLAG           (*(RwReg  *)0x4200102CUL) /**< \brief (TCC3) Interrupt Flag Status and Clear */
-#define REG_TCC3_STATUS            (*(RwReg  *)0x42001030UL) /**< \brief (TCC3) Status */
-#define REG_TCC3_COUNT             (*(RwReg  *)0x42001034UL) /**< \brief (TCC3) Count */
-#define REG_TCC3_WAVE              (*(RwReg  *)0x4200103CUL) /**< \brief (TCC3) Waveform Control */
-#define REG_TCC3_PER               (*(RwReg  *)0x42001040UL) /**< \brief (TCC3) Period */
-#define REG_TCC3_CC0               (*(RwReg  *)0x42001044UL) /**< \brief (TCC3) Compare and Capture 0 */
-#define REG_TCC3_CC1               (*(RwReg  *)0x42001048UL) /**< \brief (TCC3) Compare and Capture 1 */
-#define REG_TCC3_PERBUF            (*(RwReg  *)0x4200106CUL) /**< \brief (TCC3) Period Buffer */
-#define REG_TCC3_CCBUF0            (*(RwReg  *)0x42001070UL) /**< \brief (TCC3) Compare and Capture Buffer 0 */
-#define REG_TCC3_CCBUF1            (*(RwReg  *)0x42001074UL) /**< \brief (TCC3) Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TCC3 peripheral ========== */
-#define TCC3_CC_NUM                 2        // Number of Compare/Capture units
-#define TCC3_DITHERING              0        // Dithering feature implemented
-#define TCC3_DMAC_ID_MC_0           39
-#define TCC3_DMAC_ID_MC_1           40
-#define TCC3_DMAC_ID_MC_LSB         39
-#define TCC3_DMAC_ID_MC_MSB         40
-#define TCC3_DMAC_ID_MC_SIZE        2
-#define TCC3_DMAC_ID_OVF            38       // DMA overflow/underflow/retrigger trigger
-#define TCC3_DTI                    0        // Dead-Time-Insertion feature implemented
-#define TCC3_EXT                    0        // Coding of implemented extended features
-#define TCC3_GCLK_ID                29       // Index of Generic Clock
-#define TCC3_MASTER_SLAVE_MODE      0        // TCC type 0 : NA, 1 : Master, 2 : Slave
-#define TCC3_OTMX                   0        // Output Matrix feature implemented
-#define TCC3_OW_NUM                 2        // Number of Output Waveforms
-#define TCC3_PG                     0        // Pattern Generation feature implemented
-#define TCC3_SIZE                   16      
-#define TCC3_SWAP                   0        // DTI outputs swap feature implemented
-
-#endif /* _SAMD51_TCC3_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc4.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc4.h
deleted file mode 100644
index 84d55b8c90..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/tcc4.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TCC4
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TCC4_INSTANCE_
-#define _SAMD51_TCC4_INSTANCE_
-
-/* ========== Register definition for TCC4 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TCC4_CTRLA             (0x43001000) /**< \brief (TCC4) Control A */
-#define REG_TCC4_CTRLBCLR          (0x43001004) /**< \brief (TCC4) Control B Clear */
-#define REG_TCC4_CTRLBSET          (0x43001005) /**< \brief (TCC4) Control B Set */
-#define REG_TCC4_SYNCBUSY          (0x43001008) /**< \brief (TCC4) Synchronization Busy */
-#define REG_TCC4_FCTRLA            (0x4300100C) /**< \brief (TCC4) Recoverable Fault A Configuration */
-#define REG_TCC4_FCTRLB            (0x43001010) /**< \brief (TCC4) Recoverable Fault B Configuration */
-#define REG_TCC4_DRVCTRL           (0x43001018) /**< \brief (TCC4) Driver Control */
-#define REG_TCC4_DBGCTRL           (0x4300101E) /**< \brief (TCC4) Debug Control */
-#define REG_TCC4_EVCTRL            (0x43001020) /**< \brief (TCC4) Event Control */
-#define REG_TCC4_INTENCLR          (0x43001024) /**< \brief (TCC4) Interrupt Enable Clear */
-#define REG_TCC4_INTENSET          (0x43001028) /**< \brief (TCC4) Interrupt Enable Set */
-#define REG_TCC4_INTFLAG           (0x4300102C) /**< \brief (TCC4) Interrupt Flag Status and Clear */
-#define REG_TCC4_STATUS            (0x43001030) /**< \brief (TCC4) Status */
-#define REG_TCC4_COUNT             (0x43001034) /**< \brief (TCC4) Count */
-#define REG_TCC4_WAVE              (0x4300103C) /**< \brief (TCC4) Waveform Control */
-#define REG_TCC4_PER               (0x43001040) /**< \brief (TCC4) Period */
-#define REG_TCC4_CC0               (0x43001044) /**< \brief (TCC4) Compare and Capture 0 */
-#define REG_TCC4_CC1               (0x43001048) /**< \brief (TCC4) Compare and Capture 1 */
-#define REG_TCC4_PERBUF            (0x4300106C) /**< \brief (TCC4) Period Buffer */
-#define REG_TCC4_CCBUF0            (0x43001070) /**< \brief (TCC4) Compare and Capture Buffer 0 */
-#define REG_TCC4_CCBUF1            (0x43001074) /**< \brief (TCC4) Compare and Capture Buffer 1 */
-#else
-#define REG_TCC4_CTRLA             (*(RwReg  *)0x43001000UL) /**< \brief (TCC4) Control A */
-#define REG_TCC4_CTRLBCLR          (*(RwReg8 *)0x43001004UL) /**< \brief (TCC4) Control B Clear */
-#define REG_TCC4_CTRLBSET          (*(RwReg8 *)0x43001005UL) /**< \brief (TCC4) Control B Set */
-#define REG_TCC4_SYNCBUSY          (*(RoReg  *)0x43001008UL) /**< \brief (TCC4) Synchronization Busy */
-#define REG_TCC4_FCTRLA            (*(RwReg  *)0x4300100CUL) /**< \brief (TCC4) Recoverable Fault A Configuration */
-#define REG_TCC4_FCTRLB            (*(RwReg  *)0x43001010UL) /**< \brief (TCC4) Recoverable Fault B Configuration */
-#define REG_TCC4_DRVCTRL           (*(RwReg  *)0x43001018UL) /**< \brief (TCC4) Driver Control */
-#define REG_TCC4_DBGCTRL           (*(RwReg8 *)0x4300101EUL) /**< \brief (TCC4) Debug Control */
-#define REG_TCC4_EVCTRL            (*(RwReg  *)0x43001020UL) /**< \brief (TCC4) Event Control */
-#define REG_TCC4_INTENCLR          (*(RwReg  *)0x43001024UL) /**< \brief (TCC4) Interrupt Enable Clear */
-#define REG_TCC4_INTENSET          (*(RwReg  *)0x43001028UL) /**< \brief (TCC4) Interrupt Enable Set */
-#define REG_TCC4_INTFLAG           (*(RwReg  *)0x4300102CUL) /**< \brief (TCC4) Interrupt Flag Status and Clear */
-#define REG_TCC4_STATUS            (*(RwReg  *)0x43001030UL) /**< \brief (TCC4) Status */
-#define REG_TCC4_COUNT             (*(RwReg  *)0x43001034UL) /**< \brief (TCC4) Count */
-#define REG_TCC4_WAVE              (*(RwReg  *)0x4300103CUL) /**< \brief (TCC4) Waveform Control */
-#define REG_TCC4_PER               (*(RwReg  *)0x43001040UL) /**< \brief (TCC4) Period */
-#define REG_TCC4_CC0               (*(RwReg  *)0x43001044UL) /**< \brief (TCC4) Compare and Capture 0 */
-#define REG_TCC4_CC1               (*(RwReg  *)0x43001048UL) /**< \brief (TCC4) Compare and Capture 1 */
-#define REG_TCC4_PERBUF            (*(RwReg  *)0x4300106CUL) /**< \brief (TCC4) Period Buffer */
-#define REG_TCC4_CCBUF0            (*(RwReg  *)0x43001070UL) /**< \brief (TCC4) Compare and Capture Buffer 0 */
-#define REG_TCC4_CCBUF1            (*(RwReg  *)0x43001074UL) /**< \brief (TCC4) Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TCC4 peripheral ========== */
-#define TCC4_CC_NUM                 2        // Number of Compare/Capture units
-#define TCC4_DITHERING              0        // Dithering feature implemented
-#define TCC4_DMAC_ID_MC_0           42
-#define TCC4_DMAC_ID_MC_1           43
-#define TCC4_DMAC_ID_MC_LSB         42
-#define TCC4_DMAC_ID_MC_MSB         43
-#define TCC4_DMAC_ID_MC_SIZE        2
-#define TCC4_DMAC_ID_OVF            41       // DMA overflow/underflow/retrigger trigger
-#define TCC4_DTI                    0        // Dead-Time-Insertion feature implemented
-#define TCC4_EXT                    0        // Coding of implemented extended features
-#define TCC4_GCLK_ID                38       // Index of Generic Clock
-#define TCC4_MASTER_SLAVE_MODE      0        // TCC type 0 : NA, 1 : Master, 2 : Slave
-#define TCC4_OTMX                   0        // Output Matrix feature implemented
-#define TCC4_OW_NUM                 2        // Number of Output Waveforms
-#define TCC4_PG                     0        // Pattern Generation feature implemented
-#define TCC4_SIZE                   16      
-#define TCC4_SWAP                   0        // DTI outputs swap feature implemented
-
-#endif /* _SAMD51_TCC4_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/trng.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/trng.h
deleted file mode 100644
index 86008b962c..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/trng.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for TRNG
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_TRNG_INSTANCE_
-#define _SAMD51_TRNG_INSTANCE_
-
-/* ========== Register definition for TRNG peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TRNG_CTRLA             (0x42002800) /**< \brief (TRNG) Control A */
-#define REG_TRNG_EVCTRL            (0x42002804) /**< \brief (TRNG) Event Control */
-#define REG_TRNG_INTENCLR          (0x42002808) /**< \brief (TRNG) Interrupt Enable Clear */
-#define REG_TRNG_INTENSET          (0x42002809) /**< \brief (TRNG) Interrupt Enable Set */
-#define REG_TRNG_INTFLAG           (0x4200280A) /**< \brief (TRNG) Interrupt Flag Status and Clear */
-#define REG_TRNG_DATA              (0x42002820) /**< \brief (TRNG) Output Data */
-#else
-#define REG_TRNG_CTRLA             (*(RwReg8 *)0x42002800UL) /**< \brief (TRNG) Control A */
-#define REG_TRNG_EVCTRL            (*(RwReg8 *)0x42002804UL) /**< \brief (TRNG) Event Control */
-#define REG_TRNG_INTENCLR          (*(RwReg8 *)0x42002808UL) /**< \brief (TRNG) Interrupt Enable Clear */
-#define REG_TRNG_INTENSET          (*(RwReg8 *)0x42002809UL) /**< \brief (TRNG) Interrupt Enable Set */
-#define REG_TRNG_INTFLAG           (*(RwReg8 *)0x4200280AUL) /**< \brief (TRNG) Interrupt Flag Status and Clear */
-#define REG_TRNG_DATA              (*(RoReg  *)0x42002820UL) /**< \brief (TRNG) Output Data */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-
-#endif /* _SAMD51_TRNG_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/usb.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/usb.h
deleted file mode 100644
index 9776c79fc7..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/usb.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for USB
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_USB_INSTANCE_
-#define _SAMD51_USB_INSTANCE_
-
-/* ========== Register definition for USB peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_USB_CTRLA              (0x41000000) /**< \brief (USB) Control A */
-#define REG_USB_SYNCBUSY           (0x41000002) /**< \brief (USB) Synchronization Busy */
-#define REG_USB_QOSCTRL            (0x41000003) /**< \brief (USB) USB Quality Of Service */
-#define REG_USB_FSMSTATUS          (0x4100000D) /**< \brief (USB) Finite State Machine Status */
-#define REG_USB_DESCADD            (0x41000024) /**< \brief (USB) Descriptor Address */
-#define REG_USB_PADCAL             (0x41000028) /**< \brief (USB) USB PAD Calibration */
-#define REG_USB_DEVICE_CTRLB       (0x41000008) /**< \brief (USB) DEVICE Control B */
-#define REG_USB_DEVICE_DADD        (0x4100000A) /**< \brief (USB) DEVICE Device Address */
-#define REG_USB_DEVICE_STATUS      (0x4100000C) /**< \brief (USB) DEVICE Status */
-#define REG_USB_DEVICE_FNUM        (0x41000010) /**< \brief (USB) DEVICE Device Frame Number */
-#define REG_USB_DEVICE_INTENCLR    (0x41000014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
-#define REG_USB_DEVICE_INTENSET    (0x41000018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
-#define REG_USB_DEVICE_INTFLAG     (0x4100001C) /**< \brief (USB) DEVICE Device Interrupt Flag */
-#define REG_USB_DEVICE_EPINTSMRY   (0x41000020) /**< \brief (USB) DEVICE End Point Interrupt Summary */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
-#define REG_USB_HOST_CTRLB         (0x41000008) /**< \brief (USB) HOST Control B */
-#define REG_USB_HOST_HSOFC         (0x4100000A) /**< \brief (USB) HOST Host Start Of Frame Control */
-#define REG_USB_HOST_STATUS        (0x4100000C) /**< \brief (USB) HOST Status */
-#define REG_USB_HOST_FNUM          (0x41000010) /**< \brief (USB) HOST Host Frame Number */
-#define REG_USB_HOST_FLENHIGH      (0x41000012) /**< \brief (USB) HOST Host Frame Length */
-#define REG_USB_HOST_INTENCLR      (0x41000014) /**< \brief (USB) HOST Host Interrupt Enable Clear */
-#define REG_USB_HOST_INTENSET      (0x41000018) /**< \brief (USB) HOST Host Interrupt Enable Set */
-#define REG_USB_HOST_INTFLAG       (0x4100001C) /**< \brief (USB) HOST Host Interrupt Flag */
-#define REG_USB_HOST_PINTSMRY      (0x41000020) /**< \brief (USB) HOST Pipe Interrupt Summary */
-#define REG_USB_HOST_PIPE_PCFG0    (0x41000100) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
-#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41000103) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41000104) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
-#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41000105) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
-#define REG_USB_HOST_PIPE_PSTATUS0 (0x41000106) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
-#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41000107) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
-#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41000108) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
-#define REG_USB_HOST_PIPE_PINTENSET0 (0x41000109) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
-#define REG_USB_HOST_PIPE_PCFG1    (0x41000120) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
-#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41000123) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41000124) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
-#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41000125) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
-#define REG_USB_HOST_PIPE_PSTATUS1 (0x41000126) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
-#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41000127) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
-#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41000128) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
-#define REG_USB_HOST_PIPE_PINTENSET1 (0x41000129) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
-#define REG_USB_HOST_PIPE_PCFG2    (0x41000140) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
-#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41000143) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41000144) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
-#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41000145) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
-#define REG_USB_HOST_PIPE_PSTATUS2 (0x41000146) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
-#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41000147) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
-#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41000148) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
-#define REG_USB_HOST_PIPE_PINTENSET2 (0x41000149) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
-#define REG_USB_HOST_PIPE_PCFG3    (0x41000160) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
-#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41000163) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41000164) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
-#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41000165) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
-#define REG_USB_HOST_PIPE_PSTATUS3 (0x41000166) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
-#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41000167) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
-#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41000168) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
-#define REG_USB_HOST_PIPE_PINTENSET3 (0x41000169) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
-#define REG_USB_HOST_PIPE_PCFG4    (0x41000180) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
-#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41000183) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41000184) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
-#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41000185) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
-#define REG_USB_HOST_PIPE_PSTATUS4 (0x41000186) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
-#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41000187) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
-#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41000188) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
-#define REG_USB_HOST_PIPE_PINTENSET4 (0x41000189) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
-#define REG_USB_HOST_PIPE_PCFG5    (0x410001A0) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
-#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410001A3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410001A4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
-#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410001A5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
-#define REG_USB_HOST_PIPE_PSTATUS5 (0x410001A6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
-#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410001A7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
-#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410001A8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
-#define REG_USB_HOST_PIPE_PINTENSET5 (0x410001A9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
-#define REG_USB_HOST_PIPE_PCFG6    (0x410001C0) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
-#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410001C3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410001C4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
-#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410001C5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
-#define REG_USB_HOST_PIPE_PSTATUS6 (0x410001C6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
-#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410001C7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
-#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410001C8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
-#define REG_USB_HOST_PIPE_PINTENSET6 (0x410001C9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
-#define REG_USB_HOST_PIPE_PCFG7    (0x410001E0) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
-#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410001E3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410001E4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
-#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410001E5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
-#define REG_USB_HOST_PIPE_PSTATUS7 (0x410001E6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
-#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410001E7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
-#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410001E8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
-#define REG_USB_HOST_PIPE_PINTENSET7 (0x410001E9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
-#else
-#define REG_USB_CTRLA              (*(RwReg8 *)0x41000000UL) /**< \brief (USB) Control A */
-#define REG_USB_SYNCBUSY           (*(RoReg8 *)0x41000002UL) /**< \brief (USB) Synchronization Busy */
-#define REG_USB_QOSCTRL            (*(RwReg8 *)0x41000003UL) /**< \brief (USB) USB Quality Of Service */
-#define REG_USB_FSMSTATUS          (*(RoReg8 *)0x4100000DUL) /**< \brief (USB) Finite State Machine Status */
-#define REG_USB_DESCADD            (*(RwReg  *)0x41000024UL) /**< \brief (USB) Descriptor Address */
-#define REG_USB_PADCAL             (*(RwReg16*)0x41000028UL) /**< \brief (USB) USB PAD Calibration */
-#define REG_USB_DEVICE_CTRLB       (*(RwReg16*)0x41000008UL) /**< \brief (USB) DEVICE Control B */
-#define REG_USB_DEVICE_DADD        (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) DEVICE Device Address */
-#define REG_USB_DEVICE_STATUS      (*(RoReg8 *)0x4100000CUL) /**< \brief (USB) DEVICE Status */
-#define REG_USB_DEVICE_FNUM        (*(RoReg16*)0x41000010UL) /**< \brief (USB) DEVICE Device Frame Number */
-#define REG_USB_DEVICE_INTENCLR    (*(RwReg16*)0x41000014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
-#define REG_USB_DEVICE_INTENSET    (*(RwReg16*)0x41000018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
-#define REG_USB_DEVICE_INTFLAG     (*(RwReg16*)0x4100001CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */
-#define REG_USB_DEVICE_EPINTSMRY   (*(RoReg16*)0x41000020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
-#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
-#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
-#define REG_USB_HOST_CTRLB         (*(RwReg16*)0x41000008UL) /**< \brief (USB) HOST Control B */
-#define REG_USB_HOST_HSOFC         (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) HOST Host Start Of Frame Control */
-#define REG_USB_HOST_STATUS        (*(RwReg8 *)0x4100000CUL) /**< \brief (USB) HOST Status */
-#define REG_USB_HOST_FNUM          (*(RwReg16*)0x41000010UL) /**< \brief (USB) HOST Host Frame Number */
-#define REG_USB_HOST_FLENHIGH      (*(RoReg8 *)0x41000012UL) /**< \brief (USB) HOST Host Frame Length */
-#define REG_USB_HOST_INTENCLR      (*(RwReg16*)0x41000014UL) /**< \brief (USB) HOST Host Interrupt Enable Clear */
-#define REG_USB_HOST_INTENSET      (*(RwReg16*)0x41000018UL) /**< \brief (USB) HOST Host Interrupt Enable Set */
-#define REG_USB_HOST_INTFLAG       (*(RwReg16*)0x4100001CUL) /**< \brief (USB) HOST Host Interrupt Flag */
-#define REG_USB_HOST_PINTSMRY      (*(RoReg16*)0x41000020UL) /**< \brief (USB) HOST Pipe Interrupt Summary */
-#define REG_USB_HOST_PIPE_PCFG0    (*(RwReg8 *)0x41000100UL) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
-#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41000103UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
-#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
-#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
-#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
-#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
-#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
-#define REG_USB_HOST_PIPE_PCFG1    (*(RwReg8 *)0x41000120UL) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
-#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41000123UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
-#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
-#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
-#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
-#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
-#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
-#define REG_USB_HOST_PIPE_PCFG2    (*(RwReg8 *)0x41000140UL) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
-#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41000143UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
-#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
-#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
-#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
-#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
-#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
-#define REG_USB_HOST_PIPE_PCFG3    (*(RwReg8 *)0x41000160UL) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
-#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41000163UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
-#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
-#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
-#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
-#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
-#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
-#define REG_USB_HOST_PIPE_PCFG4    (*(RwReg8 *)0x41000180UL) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
-#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41000183UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
-#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
-#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
-#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
-#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
-#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
-#define REG_USB_HOST_PIPE_PCFG5    (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
-#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410001A3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
-#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
-#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
-#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
-#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
-#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
-#define REG_USB_HOST_PIPE_PCFG6    (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
-#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410001C3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
-#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
-#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
-#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
-#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
-#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
-#define REG_USB_HOST_PIPE_PCFG7    (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
-#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410001E3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
-#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
-#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
-#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
-#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
-#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
-#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for USB peripheral ========== */
-#define USB_AHB_2_USB_FIFO_DEPTH    4        // bytes number, should be at least 2, and 2^n (4,8,16 ...)
-#define USB_AHB_2_USB_RD_DATA_BITS  8        // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode
-#define USB_AHB_2_USB_WR_DATA_BITS  32       // 8, 16 or 32 : here, AHB transfer is made in word mode
-#define USB_AHB_2_USB_WR_THRESHOLD  2        // as soon as there are N bytes-free inside the fifo, ahb read transfer is requested
-#define USB_DATA_BUS_16_8           0        // UTMI/SIE data bus size : 0 -> 8 bits, 1 -> 16 bits
-#define USB_EPNUM                   8        // parameter for rtl : max of ENDPOINT and PIPE NUM
-#define USB_EPT_NUM                 8        // Number of USB end points
-#define USB_GCLK_ID                 10       // Index of Generic Clock
-#define USB_INITIAL_CONTROL_QOS     3        // CONTROL QOS RESET value
-#define USB_INITIAL_DATA_QOS        3        // DATA QOS RESET value
-#define USB_MISSING_SOF_DET_IMPLEMENTED 1        // 48 mHz xPLL feature implemented
-#define USB_PIPE_NUM                8        // Number of USB pipes
-#define USB_SYSTEM_CLOCK_IS_CKUSB   0        // Dual (1'b0) or Single (1'b1) clock system
-#define USB_USB_2_AHB_FIFO_DEPTH    4        // bytes number, should be at least 2, and 2^n (4,8,16 ...)
-#define USB_USB_2_AHB_RD_DATA_BITS  16       // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode
-#define USB_USB_2_AHB_RD_THRESHOLD  2        // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested
-#define USB_USB_2_AHB_WR_DATA_BITS  8        // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode
-
-#endif /* _SAMD51_USB_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h
deleted file mode 100644
index 98a2ca13d7..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/instance/wdt.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * \file
- *
- * \brief Instance description for WDT
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_WDT_INSTANCE_
-#define _SAMD51_WDT_INSTANCE_
-
-/* ========== Register definition for WDT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_WDT_CTRLA              (0x40002000) /**< \brief (WDT) Control */
-#define REG_WDT_CONFIG             (0x40002001) /**< \brief (WDT) Configuration */
-#define REG_WDT_EWCTRL             (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */
-#define REG_WDT_INTENCLR           (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */
-#define REG_WDT_INTENSET           (0x40002005) /**< \brief (WDT) Interrupt Enable Set */
-#define REG_WDT_INTFLAG            (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */
-#define REG_WDT_SYNCBUSY           (0x40002008) /**< \brief (WDT) Synchronization Busy */
-#define REG_WDT_CLEAR              (0x4000200C) /**< \brief (WDT) Clear */
-#else
-#define REG_WDT_CTRLA              (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */
-#define REG_WDT_CONFIG             (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */
-#define REG_WDT_EWCTRL             (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */
-#define REG_WDT_INTENCLR           (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */
-#define REG_WDT_INTENSET           (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */
-#define REG_WDT_INTFLAG            (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */
-#define REG_WDT_SYNCBUSY           (*(RoReg  *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */
-#define REG_WDT_CLEAR              (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-
-#endif /* _SAMD51_WDT_INSTANCE_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h
deleted file mode 100644
index d8fa56d5ba..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/pio/samd51j18a.h
+++ /dev/null
@@ -1,1863 +0,0 @@
-/**
- * \file
- *
- * \brief Peripheral I/O description for SAMD51J18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51J18A_PIO_
-#define _SAMD51J18A_PIO_
-
-#define PIN_PA00                            0  /**< \brief Pin Number for PA00 */
-#define PORT_PA00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PA00 */
-#define PIN_PA01                            1  /**< \brief Pin Number for PA01 */
-#define PORT_PA01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PA01 */
-#define PIN_PA02                            2  /**< \brief Pin Number for PA02 */
-#define PORT_PA02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PA02 */
-#define PIN_PA03                            3  /**< \brief Pin Number for PA03 */
-#define PORT_PA03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PA03 */
-#define PIN_PA04                            4  /**< \brief Pin Number for PA04 */
-#define PORT_PA04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PA04 */
-#define PIN_PA05                            5  /**< \brief Pin Number for PA05 */
-#define PORT_PA05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PA05 */
-#define PIN_PA06                            6  /**< \brief Pin Number for PA06 */
-#define PORT_PA06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PA06 */
-#define PIN_PA07                            7  /**< \brief Pin Number for PA07 */
-#define PORT_PA07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PA07 */
-#define PIN_PA08                            8  /**< \brief Pin Number for PA08 */
-#define PORT_PA08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PA08 */
-#define PIN_PA09                            9  /**< \brief Pin Number for PA09 */
-#define PORT_PA09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PA09 */
-#define PIN_PA10                           10  /**< \brief Pin Number for PA10 */
-#define PORT_PA10              (_UL_(1) << 10) /**< \brief PORT Mask  for PA10 */
-#define PIN_PA11                           11  /**< \brief Pin Number for PA11 */
-#define PORT_PA11              (_UL_(1) << 11) /**< \brief PORT Mask  for PA11 */
-#define PIN_PA12                           12  /**< \brief Pin Number for PA12 */
-#define PORT_PA12              (_UL_(1) << 12) /**< \brief PORT Mask  for PA12 */
-#define PIN_PA13                           13  /**< \brief Pin Number for PA13 */
-#define PORT_PA13              (_UL_(1) << 13) /**< \brief PORT Mask  for PA13 */
-#define PIN_PA14                           14  /**< \brief Pin Number for PA14 */
-#define PORT_PA14              (_UL_(1) << 14) /**< \brief PORT Mask  for PA14 */
-#define PIN_PA15                           15  /**< \brief Pin Number for PA15 */
-#define PORT_PA15              (_UL_(1) << 15) /**< \brief PORT Mask  for PA15 */
-#define PIN_PA16                           16  /**< \brief Pin Number for PA16 */
-#define PORT_PA16              (_UL_(1) << 16) /**< \brief PORT Mask  for PA16 */
-#define PIN_PA17                           17  /**< \brief Pin Number for PA17 */
-#define PORT_PA17              (_UL_(1) << 17) /**< \brief PORT Mask  for PA17 */
-#define PIN_PA18                           18  /**< \brief Pin Number for PA18 */
-#define PORT_PA18              (_UL_(1) << 18) /**< \brief PORT Mask  for PA18 */
-#define PIN_PA19                           19  /**< \brief Pin Number for PA19 */
-#define PORT_PA19              (_UL_(1) << 19) /**< \brief PORT Mask  for PA19 */
-#define PIN_PA20                           20  /**< \brief Pin Number for PA20 */
-#define PORT_PA20              (_UL_(1) << 20) /**< \brief PORT Mask  for PA20 */
-#define PIN_PA21                           21  /**< \brief Pin Number for PA21 */
-#define PORT_PA21              (_UL_(1) << 21) /**< \brief PORT Mask  for PA21 */
-#define PIN_PA22                           22  /**< \brief Pin Number for PA22 */
-#define PORT_PA22              (_UL_(1) << 22) /**< \brief PORT Mask  for PA22 */
-#define PIN_PA23                           23  /**< \brief Pin Number for PA23 */
-#define PORT_PA23              (_UL_(1) << 23) /**< \brief PORT Mask  for PA23 */
-#define PIN_PA24                           24  /**< \brief Pin Number for PA24 */
-#define PORT_PA24              (_UL_(1) << 24) /**< \brief PORT Mask  for PA24 */
-#define PIN_PA25                           25  /**< \brief Pin Number for PA25 */
-#define PORT_PA25              (_UL_(1) << 25) /**< \brief PORT Mask  for PA25 */
-#define PIN_PA27                           27  /**< \brief Pin Number for PA27 */
-#define PORT_PA27              (_UL_(1) << 27) /**< \brief PORT Mask  for PA27 */
-#define PIN_PA30                           30  /**< \brief Pin Number for PA30 */
-#define PORT_PA30              (_UL_(1) << 30) /**< \brief PORT Mask  for PA30 */
-#define PIN_PA31                           31  /**< \brief Pin Number for PA31 */
-#define PORT_PA31              (_UL_(1) << 31) /**< \brief PORT Mask  for PA31 */
-#define PIN_PB00                           32  /**< \brief Pin Number for PB00 */
-#define PORT_PB00              (_UL_(1) <<  0) /**< \brief PORT Mask  for PB00 */
-#define PIN_PB01                           33  /**< \brief Pin Number for PB01 */
-#define PORT_PB01              (_UL_(1) <<  1) /**< \brief PORT Mask  for PB01 */
-#define PIN_PB02                           34  /**< \brief Pin Number for PB02 */
-#define PORT_PB02              (_UL_(1) <<  2) /**< \brief PORT Mask  for PB02 */
-#define PIN_PB03                           35  /**< \brief Pin Number for PB03 */
-#define PORT_PB03              (_UL_(1) <<  3) /**< \brief PORT Mask  for PB03 */
-#define PIN_PB04                           36  /**< \brief Pin Number for PB04 */
-#define PORT_PB04              (_UL_(1) <<  4) /**< \brief PORT Mask  for PB04 */
-#define PIN_PB05                           37  /**< \brief Pin Number for PB05 */
-#define PORT_PB05              (_UL_(1) <<  5) /**< \brief PORT Mask  for PB05 */
-#define PIN_PB06                           38  /**< \brief Pin Number for PB06 */
-#define PORT_PB06              (_UL_(1) <<  6) /**< \brief PORT Mask  for PB06 */
-#define PIN_PB07                           39  /**< \brief Pin Number for PB07 */
-#define PORT_PB07              (_UL_(1) <<  7) /**< \brief PORT Mask  for PB07 */
-#define PIN_PB08                           40  /**< \brief Pin Number for PB08 */
-#define PORT_PB08              (_UL_(1) <<  8) /**< \brief PORT Mask  for PB08 */
-#define PIN_PB09                           41  /**< \brief Pin Number for PB09 */
-#define PORT_PB09              (_UL_(1) <<  9) /**< \brief PORT Mask  for PB09 */
-#define PIN_PB10                           42  /**< \brief Pin Number for PB10 */
-#define PORT_PB10              (_UL_(1) << 10) /**< \brief PORT Mask  for PB10 */
-#define PIN_PB11                           43  /**< \brief Pin Number for PB11 */
-#define PORT_PB11              (_UL_(1) << 11) /**< \brief PORT Mask  for PB11 */
-#define PIN_PB12                           44  /**< \brief Pin Number for PB12 */
-#define PORT_PB12              (_UL_(1) << 12) /**< \brief PORT Mask  for PB12 */
-#define PIN_PB13                           45  /**< \brief Pin Number for PB13 */
-#define PORT_PB13              (_UL_(1) << 13) /**< \brief PORT Mask  for PB13 */
-#define PIN_PB14                           46  /**< \brief Pin Number for PB14 */
-#define PORT_PB14              (_UL_(1) << 14) /**< \brief PORT Mask  for PB14 */
-#define PIN_PB15                           47  /**< \brief Pin Number for PB15 */
-#define PORT_PB15              (_UL_(1) << 15) /**< \brief PORT Mask  for PB15 */
-#define PIN_PB16                           48  /**< \brief Pin Number for PB16 */
-#define PORT_PB16              (_UL_(1) << 16) /**< \brief PORT Mask  for PB16 */
-#define PIN_PB17                           49  /**< \brief Pin Number for PB17 */
-#define PORT_PB17              (_UL_(1) << 17) /**< \brief PORT Mask  for PB17 */
-#define PIN_PB22                           54  /**< \brief Pin Number for PB22 */
-#define PORT_PB22              (_UL_(1) << 22) /**< \brief PORT Mask  for PB22 */
-#define PIN_PB23                           55  /**< \brief Pin Number for PB23 */
-#define PORT_PB23              (_UL_(1) << 23) /**< \brief PORT Mask  for PB23 */
-#define PIN_PB30                           62  /**< \brief Pin Number for PB30 */
-#define PORT_PB30              (_UL_(1) << 30) /**< \brief PORT Mask  for PB30 */
-#define PIN_PB31                           63  /**< \brief Pin Number for PB31 */
-#define PORT_PB31              (_UL_(1) << 31) /**< \brief PORT Mask  for PB31 */
-/* ========== PORT definition for CM4 peripheral ========== */
-#define PIN_PA30H_CM4_SWCLK            _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
-#define MUX_PA30H_CM4_SWCLK             _L_(7)
-#define PINMUX_PA30H_CM4_SWCLK     ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
-#define PORT_PA30H_CM4_SWCLK   (_UL_(1) << 30)
-#define PIN_PB30H_CM4_SWO              _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
-#define MUX_PB30H_CM4_SWO               _L_(7)
-#define PINMUX_PB30H_CM4_SWO       ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
-#define PORT_PB30H_CM4_SWO     (_UL_(1) << 30)
-/* ========== PORT definition for ANAREF peripheral ========== */
-#define PIN_PA03B_ANAREF_VREF0          _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
-#define MUX_PA03B_ANAREF_VREF0          _L_(1)
-#define PINMUX_PA03B_ANAREF_VREF0  ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
-#define PORT_PA03B_ANAREF_VREF0  (_UL_(1) <<  3)
-#define PIN_PA04B_ANAREF_VREF1          _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
-#define MUX_PA04B_ANAREF_VREF1          _L_(1)
-#define PINMUX_PA04B_ANAREF_VREF1  ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
-#define PORT_PA04B_ANAREF_VREF1  (_UL_(1) <<  4)
-#define PIN_PA06B_ANAREF_VREF2          _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
-#define MUX_PA06B_ANAREF_VREF2          _L_(1)
-#define PINMUX_PA06B_ANAREF_VREF2  ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
-#define PORT_PA06B_ANAREF_VREF2  (_UL_(1) <<  6)
-/* ========== PORT definition for GCLK peripheral ========== */
-#define PIN_PA30M_GCLK_IO0             _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
-#define MUX_PA30M_GCLK_IO0             _L_(12)
-#define PINMUX_PA30M_GCLK_IO0      ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
-#define PORT_PA30M_GCLK_IO0    (_UL_(1) << 30)
-#define PIN_PB14M_GCLK_IO0             _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
-#define MUX_PB14M_GCLK_IO0             _L_(12)
-#define PINMUX_PB14M_GCLK_IO0      ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
-#define PORT_PB14M_GCLK_IO0    (_UL_(1) << 14)
-#define PIN_PA14M_GCLK_IO0             _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
-#define MUX_PA14M_GCLK_IO0             _L_(12)
-#define PINMUX_PA14M_GCLK_IO0      ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
-#define PORT_PA14M_GCLK_IO0    (_UL_(1) << 14)
-#define PIN_PB22M_GCLK_IO0             _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
-#define MUX_PB22M_GCLK_IO0             _L_(12)
-#define PINMUX_PB22M_GCLK_IO0      ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
-#define PORT_PB22M_GCLK_IO0    (_UL_(1) << 22)
-#define PIN_PB15M_GCLK_IO1             _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
-#define MUX_PB15M_GCLK_IO1             _L_(12)
-#define PINMUX_PB15M_GCLK_IO1      ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
-#define PORT_PB15M_GCLK_IO1    (_UL_(1) << 15)
-#define PIN_PA15M_GCLK_IO1             _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
-#define MUX_PA15M_GCLK_IO1             _L_(12)
-#define PINMUX_PA15M_GCLK_IO1      ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
-#define PORT_PA15M_GCLK_IO1    (_UL_(1) << 15)
-#define PIN_PB23M_GCLK_IO1             _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
-#define MUX_PB23M_GCLK_IO1             _L_(12)
-#define PINMUX_PB23M_GCLK_IO1      ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
-#define PORT_PB23M_GCLK_IO1    (_UL_(1) << 23)
-#define PIN_PA27M_GCLK_IO1             _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
-#define MUX_PA27M_GCLK_IO1             _L_(12)
-#define PINMUX_PA27M_GCLK_IO1      ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
-#define PORT_PA27M_GCLK_IO1    (_UL_(1) << 27)
-#define PIN_PA16M_GCLK_IO2             _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
-#define MUX_PA16M_GCLK_IO2             _L_(12)
-#define PINMUX_PA16M_GCLK_IO2      ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
-#define PORT_PA16M_GCLK_IO2    (_UL_(1) << 16)
-#define PIN_PB16M_GCLK_IO2             _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
-#define MUX_PB16M_GCLK_IO2             _L_(12)
-#define PINMUX_PB16M_GCLK_IO2      ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
-#define PORT_PB16M_GCLK_IO2    (_UL_(1) << 16)
-#define PIN_PA17M_GCLK_IO3             _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
-#define MUX_PA17M_GCLK_IO3             _L_(12)
-#define PINMUX_PA17M_GCLK_IO3      ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
-#define PORT_PA17M_GCLK_IO3    (_UL_(1) << 17)
-#define PIN_PB17M_GCLK_IO3             _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
-#define MUX_PB17M_GCLK_IO3             _L_(12)
-#define PINMUX_PB17M_GCLK_IO3      ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
-#define PORT_PB17M_GCLK_IO3    (_UL_(1) << 17)
-#define PIN_PA10M_GCLK_IO4             _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
-#define MUX_PA10M_GCLK_IO4             _L_(12)
-#define PINMUX_PA10M_GCLK_IO4      ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
-#define PORT_PA10M_GCLK_IO4    (_UL_(1) << 10)
-#define PIN_PB10M_GCLK_IO4             _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
-#define MUX_PB10M_GCLK_IO4             _L_(12)
-#define PINMUX_PB10M_GCLK_IO4      ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
-#define PORT_PB10M_GCLK_IO4    (_UL_(1) << 10)
-#define PIN_PA11M_GCLK_IO5             _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
-#define MUX_PA11M_GCLK_IO5             _L_(12)
-#define PINMUX_PA11M_GCLK_IO5      ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
-#define PORT_PA11M_GCLK_IO5    (_UL_(1) << 11)
-#define PIN_PB11M_GCLK_IO5             _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
-#define MUX_PB11M_GCLK_IO5             _L_(12)
-#define PINMUX_PB11M_GCLK_IO5      ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
-#define PORT_PB11M_GCLK_IO5    (_UL_(1) << 11)
-#define PIN_PB12M_GCLK_IO6             _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
-#define MUX_PB12M_GCLK_IO6             _L_(12)
-#define PINMUX_PB12M_GCLK_IO6      ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
-#define PORT_PB12M_GCLK_IO6    (_UL_(1) << 12)
-#define PIN_PB13M_GCLK_IO7             _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
-#define MUX_PB13M_GCLK_IO7             _L_(12)
-#define PINMUX_PB13M_GCLK_IO7      ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
-#define PORT_PB13M_GCLK_IO7    (_UL_(1) << 13)
-/* ========== PORT definition for EIC peripheral ========== */
-#define PIN_PA00A_EIC_EXTINT0           _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
-#define MUX_PA00A_EIC_EXTINT0           _L_(0)
-#define PINMUX_PA00A_EIC_EXTINT0   ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
-#define PORT_PA00A_EIC_EXTINT0  (_UL_(1) <<  0)
-#define PIN_PA00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
-#define PIN_PA16A_EIC_EXTINT0          _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
-#define MUX_PA16A_EIC_EXTINT0           _L_(0)
-#define PINMUX_PA16A_EIC_EXTINT0   ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
-#define PORT_PA16A_EIC_EXTINT0  (_UL_(1) << 16)
-#define PIN_PA16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
-#define PIN_PB00A_EIC_EXTINT0          _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
-#define MUX_PB00A_EIC_EXTINT0           _L_(0)
-#define PINMUX_PB00A_EIC_EXTINT0   ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
-#define PORT_PB00A_EIC_EXTINT0  (_UL_(1) <<  0)
-#define PIN_PB00A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
-#define PIN_PB16A_EIC_EXTINT0          _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
-#define MUX_PB16A_EIC_EXTINT0           _L_(0)
-#define PINMUX_PB16A_EIC_EXTINT0   ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
-#define PORT_PB16A_EIC_EXTINT0  (_UL_(1) << 16)
-#define PIN_PB16A_EIC_EXTINT_NUM        _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
-#define PIN_PA01A_EIC_EXTINT1           _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
-#define MUX_PA01A_EIC_EXTINT1           _L_(0)
-#define PINMUX_PA01A_EIC_EXTINT1   ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
-#define PORT_PA01A_EIC_EXTINT1  (_UL_(1) <<  1)
-#define PIN_PA01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
-#define PIN_PA17A_EIC_EXTINT1          _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
-#define MUX_PA17A_EIC_EXTINT1           _L_(0)
-#define PINMUX_PA17A_EIC_EXTINT1   ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
-#define PORT_PA17A_EIC_EXTINT1  (_UL_(1) << 17)
-#define PIN_PA17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
-#define PIN_PB01A_EIC_EXTINT1          _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
-#define MUX_PB01A_EIC_EXTINT1           _L_(0)
-#define PINMUX_PB01A_EIC_EXTINT1   ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
-#define PORT_PB01A_EIC_EXTINT1  (_UL_(1) <<  1)
-#define PIN_PB01A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
-#define PIN_PB17A_EIC_EXTINT1          _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
-#define MUX_PB17A_EIC_EXTINT1           _L_(0)
-#define PINMUX_PB17A_EIC_EXTINT1   ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
-#define PORT_PB17A_EIC_EXTINT1  (_UL_(1) << 17)
-#define PIN_PB17A_EIC_EXTINT_NUM        _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
-#define PIN_PA02A_EIC_EXTINT2           _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
-#define MUX_PA02A_EIC_EXTINT2           _L_(0)
-#define PINMUX_PA02A_EIC_EXTINT2   ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
-#define PORT_PA02A_EIC_EXTINT2  (_UL_(1) <<  2)
-#define PIN_PA02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
-#define PIN_PA18A_EIC_EXTINT2          _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
-#define MUX_PA18A_EIC_EXTINT2           _L_(0)
-#define PINMUX_PA18A_EIC_EXTINT2   ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
-#define PORT_PA18A_EIC_EXTINT2  (_UL_(1) << 18)
-#define PIN_PA18A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
-#define PIN_PB02A_EIC_EXTINT2          _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
-#define MUX_PB02A_EIC_EXTINT2           _L_(0)
-#define PINMUX_PB02A_EIC_EXTINT2   ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
-#define PORT_PB02A_EIC_EXTINT2  (_UL_(1) <<  2)
-#define PIN_PB02A_EIC_EXTINT_NUM        _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
-#define PIN_PA03A_EIC_EXTINT3           _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
-#define MUX_PA03A_EIC_EXTINT3           _L_(0)
-#define PINMUX_PA03A_EIC_EXTINT3   ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
-#define PORT_PA03A_EIC_EXTINT3  (_UL_(1) <<  3)
-#define PIN_PA03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
-#define PIN_PA19A_EIC_EXTINT3          _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
-#define MUX_PA19A_EIC_EXTINT3           _L_(0)
-#define PINMUX_PA19A_EIC_EXTINT3   ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
-#define PORT_PA19A_EIC_EXTINT3  (_UL_(1) << 19)
-#define PIN_PA19A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
-#define PIN_PB03A_EIC_EXTINT3          _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
-#define MUX_PB03A_EIC_EXTINT3           _L_(0)
-#define PINMUX_PB03A_EIC_EXTINT3   ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
-#define PORT_PB03A_EIC_EXTINT3  (_UL_(1) <<  3)
-#define PIN_PB03A_EIC_EXTINT_NUM        _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
-#define PIN_PA04A_EIC_EXTINT4           _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
-#define MUX_PA04A_EIC_EXTINT4           _L_(0)
-#define PINMUX_PA04A_EIC_EXTINT4   ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
-#define PORT_PA04A_EIC_EXTINT4  (_UL_(1) <<  4)
-#define PIN_PA04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
-#define PIN_PA20A_EIC_EXTINT4          _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
-#define MUX_PA20A_EIC_EXTINT4           _L_(0)
-#define PINMUX_PA20A_EIC_EXTINT4   ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
-#define PORT_PA20A_EIC_EXTINT4  (_UL_(1) << 20)
-#define PIN_PA20A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
-#define PIN_PB04A_EIC_EXTINT4          _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
-#define MUX_PB04A_EIC_EXTINT4           _L_(0)
-#define PINMUX_PB04A_EIC_EXTINT4   ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
-#define PORT_PB04A_EIC_EXTINT4  (_UL_(1) <<  4)
-#define PIN_PB04A_EIC_EXTINT_NUM        _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
-#define PIN_PA05A_EIC_EXTINT5           _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
-#define MUX_PA05A_EIC_EXTINT5           _L_(0)
-#define PINMUX_PA05A_EIC_EXTINT5   ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
-#define PORT_PA05A_EIC_EXTINT5  (_UL_(1) <<  5)
-#define PIN_PA05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
-#define PIN_PA21A_EIC_EXTINT5          _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
-#define MUX_PA21A_EIC_EXTINT5           _L_(0)
-#define PINMUX_PA21A_EIC_EXTINT5   ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
-#define PORT_PA21A_EIC_EXTINT5  (_UL_(1) << 21)
-#define PIN_PA21A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
-#define PIN_PB05A_EIC_EXTINT5          _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
-#define MUX_PB05A_EIC_EXTINT5           _L_(0)
-#define PINMUX_PB05A_EIC_EXTINT5   ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
-#define PORT_PB05A_EIC_EXTINT5  (_UL_(1) <<  5)
-#define PIN_PB05A_EIC_EXTINT_NUM        _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
-#define PIN_PA06A_EIC_EXTINT6           _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
-#define MUX_PA06A_EIC_EXTINT6           _L_(0)
-#define PINMUX_PA06A_EIC_EXTINT6   ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
-#define PORT_PA06A_EIC_EXTINT6  (_UL_(1) <<  6)
-#define PIN_PA06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
-#define PIN_PA22A_EIC_EXTINT6          _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
-#define MUX_PA22A_EIC_EXTINT6           _L_(0)
-#define PINMUX_PA22A_EIC_EXTINT6   ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
-#define PORT_PA22A_EIC_EXTINT6  (_UL_(1) << 22)
-#define PIN_PA22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
-#define PIN_PB06A_EIC_EXTINT6          _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
-#define MUX_PB06A_EIC_EXTINT6           _L_(0)
-#define PINMUX_PB06A_EIC_EXTINT6   ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
-#define PORT_PB06A_EIC_EXTINT6  (_UL_(1) <<  6)
-#define PIN_PB06A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
-#define PIN_PB22A_EIC_EXTINT6          _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
-#define MUX_PB22A_EIC_EXTINT6           _L_(0)
-#define PINMUX_PB22A_EIC_EXTINT6   ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
-#define PORT_PB22A_EIC_EXTINT6  (_UL_(1) << 22)
-#define PIN_PB22A_EIC_EXTINT_NUM        _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
-#define PIN_PA07A_EIC_EXTINT7           _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
-#define MUX_PA07A_EIC_EXTINT7           _L_(0)
-#define PINMUX_PA07A_EIC_EXTINT7   ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
-#define PORT_PA07A_EIC_EXTINT7  (_UL_(1) <<  7)
-#define PIN_PA07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
-#define PIN_PA23A_EIC_EXTINT7          _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
-#define MUX_PA23A_EIC_EXTINT7           _L_(0)
-#define PINMUX_PA23A_EIC_EXTINT7   ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
-#define PORT_PA23A_EIC_EXTINT7  (_UL_(1) << 23)
-#define PIN_PA23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
-#define PIN_PB07A_EIC_EXTINT7          _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
-#define MUX_PB07A_EIC_EXTINT7           _L_(0)
-#define PINMUX_PB07A_EIC_EXTINT7   ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
-#define PORT_PB07A_EIC_EXTINT7  (_UL_(1) <<  7)
-#define PIN_PB07A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
-#define PIN_PB23A_EIC_EXTINT7          _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
-#define MUX_PB23A_EIC_EXTINT7           _L_(0)
-#define PINMUX_PB23A_EIC_EXTINT7   ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
-#define PORT_PB23A_EIC_EXTINT7  (_UL_(1) << 23)
-#define PIN_PB23A_EIC_EXTINT_NUM        _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
-#define PIN_PA24A_EIC_EXTINT8          _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
-#define MUX_PA24A_EIC_EXTINT8           _L_(0)
-#define PINMUX_PA24A_EIC_EXTINT8   ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
-#define PORT_PA24A_EIC_EXTINT8  (_UL_(1) << 24)
-#define PIN_PA24A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
-#define PIN_PB08A_EIC_EXTINT8          _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
-#define MUX_PB08A_EIC_EXTINT8           _L_(0)
-#define PINMUX_PB08A_EIC_EXTINT8   ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
-#define PORT_PB08A_EIC_EXTINT8  (_UL_(1) <<  8)
-#define PIN_PB08A_EIC_EXTINT_NUM        _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
-#define PIN_PA09A_EIC_EXTINT9           _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
-#define MUX_PA09A_EIC_EXTINT9           _L_(0)
-#define PINMUX_PA09A_EIC_EXTINT9   ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
-#define PORT_PA09A_EIC_EXTINT9  (_UL_(1) <<  9)
-#define PIN_PA09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
-#define PIN_PA25A_EIC_EXTINT9          _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
-#define MUX_PA25A_EIC_EXTINT9           _L_(0)
-#define PINMUX_PA25A_EIC_EXTINT9   ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
-#define PORT_PA25A_EIC_EXTINT9  (_UL_(1) << 25)
-#define PIN_PA25A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
-#define PIN_PB09A_EIC_EXTINT9          _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
-#define MUX_PB09A_EIC_EXTINT9           _L_(0)
-#define PINMUX_PB09A_EIC_EXTINT9   ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
-#define PORT_PB09A_EIC_EXTINT9  (_UL_(1) <<  9)
-#define PIN_PB09A_EIC_EXTINT_NUM        _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
-#define PIN_PA10A_EIC_EXTINT10         _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
-#define MUX_PA10A_EIC_EXTINT10          _L_(0)
-#define PINMUX_PA10A_EIC_EXTINT10  ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
-#define PORT_PA10A_EIC_EXTINT10  (_UL_(1) << 10)
-#define PIN_PA10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
-#define PIN_PB10A_EIC_EXTINT10         _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
-#define MUX_PB10A_EIC_EXTINT10          _L_(0)
-#define PINMUX_PB10A_EIC_EXTINT10  ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
-#define PORT_PB10A_EIC_EXTINT10  (_UL_(1) << 10)
-#define PIN_PB10A_EIC_EXTINT_NUM       _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
-#define PIN_PA11A_EIC_EXTINT11         _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
-#define MUX_PA11A_EIC_EXTINT11          _L_(0)
-#define PINMUX_PA11A_EIC_EXTINT11  ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
-#define PORT_PA11A_EIC_EXTINT11  (_UL_(1) << 11)
-#define PIN_PA11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
-#define PIN_PA27A_EIC_EXTINT11         _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
-#define MUX_PA27A_EIC_EXTINT11          _L_(0)
-#define PINMUX_PA27A_EIC_EXTINT11  ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
-#define PORT_PA27A_EIC_EXTINT11  (_UL_(1) << 27)
-#define PIN_PA27A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
-#define PIN_PB11A_EIC_EXTINT11         _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
-#define MUX_PB11A_EIC_EXTINT11          _L_(0)
-#define PINMUX_PB11A_EIC_EXTINT11  ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
-#define PORT_PB11A_EIC_EXTINT11  (_UL_(1) << 11)
-#define PIN_PB11A_EIC_EXTINT_NUM       _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
-#define PIN_PA12A_EIC_EXTINT12         _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
-#define MUX_PA12A_EIC_EXTINT12          _L_(0)
-#define PINMUX_PA12A_EIC_EXTINT12  ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
-#define PORT_PA12A_EIC_EXTINT12  (_UL_(1) << 12)
-#define PIN_PA12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
-#define PIN_PB12A_EIC_EXTINT12         _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
-#define MUX_PB12A_EIC_EXTINT12          _L_(0)
-#define PINMUX_PB12A_EIC_EXTINT12  ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
-#define PORT_PB12A_EIC_EXTINT12  (_UL_(1) << 12)
-#define PIN_PB12A_EIC_EXTINT_NUM       _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
-#define PIN_PA13A_EIC_EXTINT13         _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
-#define MUX_PA13A_EIC_EXTINT13          _L_(0)
-#define PINMUX_PA13A_EIC_EXTINT13  ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
-#define PORT_PA13A_EIC_EXTINT13  (_UL_(1) << 13)
-#define PIN_PA13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
-#define PIN_PB13A_EIC_EXTINT13         _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
-#define MUX_PB13A_EIC_EXTINT13          _L_(0)
-#define PINMUX_PB13A_EIC_EXTINT13  ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
-#define PORT_PB13A_EIC_EXTINT13  (_UL_(1) << 13)
-#define PIN_PB13A_EIC_EXTINT_NUM       _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
-#define PIN_PA30A_EIC_EXTINT14         _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
-#define MUX_PA30A_EIC_EXTINT14          _L_(0)
-#define PINMUX_PA30A_EIC_EXTINT14  ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
-#define PORT_PA30A_EIC_EXTINT14  (_UL_(1) << 30)
-#define PIN_PA30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
-#define PIN_PB14A_EIC_EXTINT14         _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
-#define MUX_PB14A_EIC_EXTINT14          _L_(0)
-#define PINMUX_PB14A_EIC_EXTINT14  ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
-#define PORT_PB14A_EIC_EXTINT14  (_UL_(1) << 14)
-#define PIN_PB14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
-#define PIN_PB30A_EIC_EXTINT14         _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
-#define MUX_PB30A_EIC_EXTINT14          _L_(0)
-#define PINMUX_PB30A_EIC_EXTINT14  ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
-#define PORT_PB30A_EIC_EXTINT14  (_UL_(1) << 30)
-#define PIN_PB30A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
-#define PIN_PA14A_EIC_EXTINT14         _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
-#define MUX_PA14A_EIC_EXTINT14          _L_(0)
-#define PINMUX_PA14A_EIC_EXTINT14  ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
-#define PORT_PA14A_EIC_EXTINT14  (_UL_(1) << 14)
-#define PIN_PA14A_EIC_EXTINT_NUM       _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
-#define PIN_PA15A_EIC_EXTINT15         _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
-#define MUX_PA15A_EIC_EXTINT15          _L_(0)
-#define PINMUX_PA15A_EIC_EXTINT15  ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
-#define PORT_PA15A_EIC_EXTINT15  (_UL_(1) << 15)
-#define PIN_PA15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
-#define PIN_PA31A_EIC_EXTINT15         _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
-#define MUX_PA31A_EIC_EXTINT15          _L_(0)
-#define PINMUX_PA31A_EIC_EXTINT15  ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
-#define PORT_PA31A_EIC_EXTINT15  (_UL_(1) << 31)
-#define PIN_PA31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
-#define PIN_PB15A_EIC_EXTINT15         _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
-#define MUX_PB15A_EIC_EXTINT15          _L_(0)
-#define PINMUX_PB15A_EIC_EXTINT15  ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
-#define PORT_PB15A_EIC_EXTINT15  (_UL_(1) << 15)
-#define PIN_PB15A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
-#define PIN_PB31A_EIC_EXTINT15         _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
-#define MUX_PB31A_EIC_EXTINT15          _L_(0)
-#define PINMUX_PB31A_EIC_EXTINT15  ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
-#define PORT_PB31A_EIC_EXTINT15  (_UL_(1) << 31)
-#define PIN_PB31A_EIC_EXTINT_NUM       _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
-#define PIN_PA08A_EIC_NMI               _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
-#define MUX_PA08A_EIC_NMI               _L_(0)
-#define PINMUX_PA08A_EIC_NMI       ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
-#define PORT_PA08A_EIC_NMI     (_UL_(1) <<  8)
-/* ========== PORT definition for SERCOM0 peripheral ========== */
-#define PIN_PA04D_SERCOM0_PAD0          _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
-#define MUX_PA04D_SERCOM0_PAD0          _L_(3)
-#define PINMUX_PA04D_SERCOM0_PAD0  ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
-#define PORT_PA04D_SERCOM0_PAD0  (_UL_(1) <<  4)
-#define PIN_PA08C_SERCOM0_PAD0          _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
-#define MUX_PA08C_SERCOM0_PAD0          _L_(2)
-#define PINMUX_PA08C_SERCOM0_PAD0  ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
-#define PORT_PA08C_SERCOM0_PAD0  (_UL_(1) <<  8)
-#define PIN_PA05D_SERCOM0_PAD1          _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
-#define MUX_PA05D_SERCOM0_PAD1          _L_(3)
-#define PINMUX_PA05D_SERCOM0_PAD1  ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
-#define PORT_PA05D_SERCOM0_PAD1  (_UL_(1) <<  5)
-#define PIN_PA09C_SERCOM0_PAD1          _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
-#define MUX_PA09C_SERCOM0_PAD1          _L_(2)
-#define PINMUX_PA09C_SERCOM0_PAD1  ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
-#define PORT_PA09C_SERCOM0_PAD1  (_UL_(1) <<  9)
-#define PIN_PA06D_SERCOM0_PAD2          _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
-#define MUX_PA06D_SERCOM0_PAD2          _L_(3)
-#define PINMUX_PA06D_SERCOM0_PAD2  ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
-#define PORT_PA06D_SERCOM0_PAD2  (_UL_(1) <<  6)
-#define PIN_PA10C_SERCOM0_PAD2         _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
-#define MUX_PA10C_SERCOM0_PAD2          _L_(2)
-#define PINMUX_PA10C_SERCOM0_PAD2  ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
-#define PORT_PA10C_SERCOM0_PAD2  (_UL_(1) << 10)
-#define PIN_PA07D_SERCOM0_PAD3          _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
-#define MUX_PA07D_SERCOM0_PAD3          _L_(3)
-#define PINMUX_PA07D_SERCOM0_PAD3  ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
-#define PORT_PA07D_SERCOM0_PAD3  (_UL_(1) <<  7)
-#define PIN_PA11C_SERCOM0_PAD3         _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
-#define MUX_PA11C_SERCOM0_PAD3          _L_(2)
-#define PINMUX_PA11C_SERCOM0_PAD3  ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
-#define PORT_PA11C_SERCOM0_PAD3  (_UL_(1) << 11)
-/* ========== PORT definition for SERCOM1 peripheral ========== */
-#define PIN_PA00D_SERCOM1_PAD0          _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
-#define MUX_PA00D_SERCOM1_PAD0          _L_(3)
-#define PINMUX_PA00D_SERCOM1_PAD0  ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
-#define PORT_PA00D_SERCOM1_PAD0  (_UL_(1) <<  0)
-#define PIN_PA16C_SERCOM1_PAD0         _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
-#define MUX_PA16C_SERCOM1_PAD0          _L_(2)
-#define PINMUX_PA16C_SERCOM1_PAD0  ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
-#define PORT_PA16C_SERCOM1_PAD0  (_UL_(1) << 16)
-#define PIN_PA01D_SERCOM1_PAD1          _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
-#define MUX_PA01D_SERCOM1_PAD1          _L_(3)
-#define PINMUX_PA01D_SERCOM1_PAD1  ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
-#define PORT_PA01D_SERCOM1_PAD1  (_UL_(1) <<  1)
-#define PIN_PA17C_SERCOM1_PAD1         _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
-#define MUX_PA17C_SERCOM1_PAD1          _L_(2)
-#define PINMUX_PA17C_SERCOM1_PAD1  ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
-#define PORT_PA17C_SERCOM1_PAD1  (_UL_(1) << 17)
-#define PIN_PA30D_SERCOM1_PAD2         _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
-#define MUX_PA30D_SERCOM1_PAD2          _L_(3)
-#define PINMUX_PA30D_SERCOM1_PAD2  ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
-#define PORT_PA30D_SERCOM1_PAD2  (_UL_(1) << 30)
-#define PIN_PA18C_SERCOM1_PAD2         _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
-#define MUX_PA18C_SERCOM1_PAD2          _L_(2)
-#define PINMUX_PA18C_SERCOM1_PAD2  ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
-#define PORT_PA18C_SERCOM1_PAD2  (_UL_(1) << 18)
-#define PIN_PB22C_SERCOM1_PAD2         _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
-#define MUX_PB22C_SERCOM1_PAD2          _L_(2)
-#define PINMUX_PB22C_SERCOM1_PAD2  ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
-#define PORT_PB22C_SERCOM1_PAD2  (_UL_(1) << 22)
-#define PIN_PA31D_SERCOM1_PAD3         _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
-#define MUX_PA31D_SERCOM1_PAD3          _L_(3)
-#define PINMUX_PA31D_SERCOM1_PAD3  ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
-#define PORT_PA31D_SERCOM1_PAD3  (_UL_(1) << 31)
-#define PIN_PA19C_SERCOM1_PAD3         _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
-#define MUX_PA19C_SERCOM1_PAD3          _L_(2)
-#define PINMUX_PA19C_SERCOM1_PAD3  ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
-#define PORT_PA19C_SERCOM1_PAD3  (_UL_(1) << 19)
-#define PIN_PB23C_SERCOM1_PAD3         _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
-#define MUX_PB23C_SERCOM1_PAD3          _L_(2)
-#define PINMUX_PB23C_SERCOM1_PAD3  ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
-#define PORT_PB23C_SERCOM1_PAD3  (_UL_(1) << 23)
-/* ========== PORT definition for TC0 peripheral ========== */
-#define PIN_PA04E_TC0_WO0               _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
-#define MUX_PA04E_TC0_WO0               _L_(4)
-#define PINMUX_PA04E_TC0_WO0       ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
-#define PORT_PA04E_TC0_WO0     (_UL_(1) <<  4)
-#define PIN_PA08E_TC0_WO0               _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
-#define MUX_PA08E_TC0_WO0               _L_(4)
-#define PINMUX_PA08E_TC0_WO0       ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
-#define PORT_PA08E_TC0_WO0     (_UL_(1) <<  8)
-#define PIN_PB30E_TC0_WO0              _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
-#define MUX_PB30E_TC0_WO0               _L_(4)
-#define PINMUX_PB30E_TC0_WO0       ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
-#define PORT_PB30E_TC0_WO0     (_UL_(1) << 30)
-#define PIN_PA05E_TC0_WO1               _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
-#define MUX_PA05E_TC0_WO1               _L_(4)
-#define PINMUX_PA05E_TC0_WO1       ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
-#define PORT_PA05E_TC0_WO1     (_UL_(1) <<  5)
-#define PIN_PA09E_TC0_WO1               _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
-#define MUX_PA09E_TC0_WO1               _L_(4)
-#define PINMUX_PA09E_TC0_WO1       ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
-#define PORT_PA09E_TC0_WO1     (_UL_(1) <<  9)
-#define PIN_PB31E_TC0_WO1              _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
-#define MUX_PB31E_TC0_WO1               _L_(4)
-#define PINMUX_PB31E_TC0_WO1       ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
-#define PORT_PB31E_TC0_WO1     (_UL_(1) << 31)
-/* ========== PORT definition for TC1 peripheral ========== */
-#define PIN_PA06E_TC1_WO0               _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
-#define MUX_PA06E_TC1_WO0               _L_(4)
-#define PINMUX_PA06E_TC1_WO0       ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
-#define PORT_PA06E_TC1_WO0     (_UL_(1) <<  6)
-#define PIN_PA10E_TC1_WO0              _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
-#define MUX_PA10E_TC1_WO0               _L_(4)
-#define PINMUX_PA10E_TC1_WO0       ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
-#define PORT_PA10E_TC1_WO0     (_UL_(1) << 10)
-#define PIN_PA07E_TC1_WO1               _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
-#define MUX_PA07E_TC1_WO1               _L_(4)
-#define PINMUX_PA07E_TC1_WO1       ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
-#define PORT_PA07E_TC1_WO1     (_UL_(1) <<  7)
-#define PIN_PA11E_TC1_WO1              _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
-#define MUX_PA11E_TC1_WO1               _L_(4)
-#define PINMUX_PA11E_TC1_WO1       ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
-#define PORT_PA11E_TC1_WO1     (_UL_(1) << 11)
-/* ========== PORT definition for USB peripheral ========== */
-#define PIN_PA24H_USB_DM               _L_(24) /**< \brief USB signal: DM on PA24 mux H */
-#define MUX_PA24H_USB_DM                _L_(7)
-#define PINMUX_PA24H_USB_DM        ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
-#define PORT_PA24H_USB_DM      (_UL_(1) << 24)
-#define PIN_PA25H_USB_DP               _L_(25) /**< \brief USB signal: DP on PA25 mux H */
-#define MUX_PA25H_USB_DP                _L_(7)
-#define PINMUX_PA25H_USB_DP        ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
-#define PORT_PA25H_USB_DP      (_UL_(1) << 25)
-#define PIN_PA23H_USB_SOF_1KHZ         _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
-#define MUX_PA23H_USB_SOF_1KHZ          _L_(7)
-#define PINMUX_PA23H_USB_SOF_1KHZ  ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
-#define PORT_PA23H_USB_SOF_1KHZ  (_UL_(1) << 23)
-#define PIN_PB22H_USB_SOF_1KHZ         _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
-#define MUX_PB22H_USB_SOF_1KHZ          _L_(7)
-#define PINMUX_PB22H_USB_SOF_1KHZ  ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
-#define PORT_PB22H_USB_SOF_1KHZ  (_UL_(1) << 22)
-/* ========== PORT definition for SERCOM2 peripheral ========== */
-#define PIN_PA09D_SERCOM2_PAD0          _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
-#define MUX_PA09D_SERCOM2_PAD0          _L_(3)
-#define PINMUX_PA09D_SERCOM2_PAD0  ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
-#define PORT_PA09D_SERCOM2_PAD0  (_UL_(1) <<  9)
-#define PIN_PA12C_SERCOM2_PAD0         _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
-#define MUX_PA12C_SERCOM2_PAD0          _L_(2)
-#define PINMUX_PA12C_SERCOM2_PAD0  ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
-#define PORT_PA12C_SERCOM2_PAD0  (_UL_(1) << 12)
-#define PIN_PA08D_SERCOM2_PAD1          _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
-#define MUX_PA08D_SERCOM2_PAD1          _L_(3)
-#define PINMUX_PA08D_SERCOM2_PAD1  ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
-#define PORT_PA08D_SERCOM2_PAD1  (_UL_(1) <<  8)
-#define PIN_PA13C_SERCOM2_PAD1         _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
-#define MUX_PA13C_SERCOM2_PAD1          _L_(2)
-#define PINMUX_PA13C_SERCOM2_PAD1  ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
-#define PORT_PA13C_SERCOM2_PAD1  (_UL_(1) << 13)
-#define PIN_PA10D_SERCOM2_PAD2         _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
-#define MUX_PA10D_SERCOM2_PAD2          _L_(3)
-#define PINMUX_PA10D_SERCOM2_PAD2  ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
-#define PORT_PA10D_SERCOM2_PAD2  (_UL_(1) << 10)
-#define PIN_PA14C_SERCOM2_PAD2         _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
-#define MUX_PA14C_SERCOM2_PAD2          _L_(2)
-#define PINMUX_PA14C_SERCOM2_PAD2  ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
-#define PORT_PA14C_SERCOM2_PAD2  (_UL_(1) << 14)
-#define PIN_PA11D_SERCOM2_PAD3         _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
-#define MUX_PA11D_SERCOM2_PAD3          _L_(3)
-#define PINMUX_PA11D_SERCOM2_PAD3  ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
-#define PORT_PA11D_SERCOM2_PAD3  (_UL_(1) << 11)
-#define PIN_PA15C_SERCOM2_PAD3         _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
-#define MUX_PA15C_SERCOM2_PAD3          _L_(2)
-#define PINMUX_PA15C_SERCOM2_PAD3  ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
-#define PORT_PA15C_SERCOM2_PAD3  (_UL_(1) << 15)
-/* ========== PORT definition for SERCOM3 peripheral ========== */
-#define PIN_PA17D_SERCOM3_PAD0         _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
-#define MUX_PA17D_SERCOM3_PAD0          _L_(3)
-#define PINMUX_PA17D_SERCOM3_PAD0  ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
-#define PORT_PA17D_SERCOM3_PAD0  (_UL_(1) << 17)
-#define PIN_PA22C_SERCOM3_PAD0         _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
-#define MUX_PA22C_SERCOM3_PAD0          _L_(2)
-#define PINMUX_PA22C_SERCOM3_PAD0  ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
-#define PORT_PA22C_SERCOM3_PAD0  (_UL_(1) << 22)
-#define PIN_PA16D_SERCOM3_PAD1         _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
-#define MUX_PA16D_SERCOM3_PAD1          _L_(3)
-#define PINMUX_PA16D_SERCOM3_PAD1  ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
-#define PORT_PA16D_SERCOM3_PAD1  (_UL_(1) << 16)
-#define PIN_PA23C_SERCOM3_PAD1         _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
-#define MUX_PA23C_SERCOM3_PAD1          _L_(2)
-#define PINMUX_PA23C_SERCOM3_PAD1  ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
-#define PORT_PA23C_SERCOM3_PAD1  (_UL_(1) << 23)
-#define PIN_PA18D_SERCOM3_PAD2         _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
-#define MUX_PA18D_SERCOM3_PAD2          _L_(3)
-#define PINMUX_PA18D_SERCOM3_PAD2  ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
-#define PORT_PA18D_SERCOM3_PAD2  (_UL_(1) << 18)
-#define PIN_PA20D_SERCOM3_PAD2         _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
-#define MUX_PA20D_SERCOM3_PAD2          _L_(3)
-#define PINMUX_PA20D_SERCOM3_PAD2  ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
-#define PORT_PA20D_SERCOM3_PAD2  (_UL_(1) << 20)
-#define PIN_PA24C_SERCOM3_PAD2         _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
-#define MUX_PA24C_SERCOM3_PAD2          _L_(2)
-#define PINMUX_PA24C_SERCOM3_PAD2  ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
-#define PORT_PA24C_SERCOM3_PAD2  (_UL_(1) << 24)
-#define PIN_PA19D_SERCOM3_PAD3         _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
-#define MUX_PA19D_SERCOM3_PAD3          _L_(3)
-#define PINMUX_PA19D_SERCOM3_PAD3  ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
-#define PORT_PA19D_SERCOM3_PAD3  (_UL_(1) << 19)
-#define PIN_PA21D_SERCOM3_PAD3         _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
-#define MUX_PA21D_SERCOM3_PAD3          _L_(3)
-#define PINMUX_PA21D_SERCOM3_PAD3  ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
-#define PORT_PA21D_SERCOM3_PAD3  (_UL_(1) << 21)
-#define PIN_PA25C_SERCOM3_PAD3         _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
-#define MUX_PA25C_SERCOM3_PAD3          _L_(2)
-#define PINMUX_PA25C_SERCOM3_PAD3  ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
-#define PORT_PA25C_SERCOM3_PAD3  (_UL_(1) << 25)
-/* ========== PORT definition for TCC0 peripheral ========== */
-#define PIN_PA20G_TCC0_WO0             _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
-#define MUX_PA20G_TCC0_WO0              _L_(6)
-#define PINMUX_PA20G_TCC0_WO0      ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
-#define PORT_PA20G_TCC0_WO0    (_UL_(1) << 20)
-#define PIN_PB12G_TCC0_WO0             _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
-#define MUX_PB12G_TCC0_WO0              _L_(6)
-#define PINMUX_PB12G_TCC0_WO0      ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
-#define PORT_PB12G_TCC0_WO0    (_UL_(1) << 12)
-#define PIN_PA08F_TCC0_WO0              _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
-#define MUX_PA08F_TCC0_WO0              _L_(5)
-#define PINMUX_PA08F_TCC0_WO0      ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
-#define PORT_PA08F_TCC0_WO0    (_UL_(1) <<  8)
-#define PIN_PA21G_TCC0_WO1             _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
-#define MUX_PA21G_TCC0_WO1              _L_(6)
-#define PINMUX_PA21G_TCC0_WO1      ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
-#define PORT_PA21G_TCC0_WO1    (_UL_(1) << 21)
-#define PIN_PB13G_TCC0_WO1             _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
-#define MUX_PB13G_TCC0_WO1              _L_(6)
-#define PINMUX_PB13G_TCC0_WO1      ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
-#define PORT_PB13G_TCC0_WO1    (_UL_(1) << 13)
-#define PIN_PA09F_TCC0_WO1              _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
-#define MUX_PA09F_TCC0_WO1              _L_(5)
-#define PINMUX_PA09F_TCC0_WO1      ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
-#define PORT_PA09F_TCC0_WO1    (_UL_(1) <<  9)
-#define PIN_PA22G_TCC0_WO2             _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
-#define MUX_PA22G_TCC0_WO2              _L_(6)
-#define PINMUX_PA22G_TCC0_WO2      ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
-#define PORT_PA22G_TCC0_WO2    (_UL_(1) << 22)
-#define PIN_PB14G_TCC0_WO2             _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
-#define MUX_PB14G_TCC0_WO2              _L_(6)
-#define PINMUX_PB14G_TCC0_WO2      ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
-#define PORT_PB14G_TCC0_WO2    (_UL_(1) << 14)
-#define PIN_PA10F_TCC0_WO2             _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
-#define MUX_PA10F_TCC0_WO2              _L_(5)
-#define PINMUX_PA10F_TCC0_WO2      ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
-#define PORT_PA10F_TCC0_WO2    (_UL_(1) << 10)
-#define PIN_PA23G_TCC0_WO3             _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
-#define MUX_PA23G_TCC0_WO3              _L_(6)
-#define PINMUX_PA23G_TCC0_WO3      ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
-#define PORT_PA23G_TCC0_WO3    (_UL_(1) << 23)
-#define PIN_PB15G_TCC0_WO3             _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
-#define MUX_PB15G_TCC0_WO3              _L_(6)
-#define PINMUX_PB15G_TCC0_WO3      ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
-#define PORT_PB15G_TCC0_WO3    (_UL_(1) << 15)
-#define PIN_PA11F_TCC0_WO3             _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
-#define MUX_PA11F_TCC0_WO3              _L_(5)
-#define PINMUX_PA11F_TCC0_WO3      ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
-#define PORT_PA11F_TCC0_WO3    (_UL_(1) << 11)
-#define PIN_PA16G_TCC0_WO4             _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
-#define MUX_PA16G_TCC0_WO4              _L_(6)
-#define PINMUX_PA16G_TCC0_WO4      ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
-#define PORT_PA16G_TCC0_WO4    (_UL_(1) << 16)
-#define PIN_PB16G_TCC0_WO4             _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
-#define MUX_PB16G_TCC0_WO4              _L_(6)
-#define PINMUX_PB16G_TCC0_WO4      ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
-#define PORT_PB16G_TCC0_WO4    (_UL_(1) << 16)
-#define PIN_PB10F_TCC0_WO4             _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
-#define MUX_PB10F_TCC0_WO4              _L_(5)
-#define PINMUX_PB10F_TCC0_WO4      ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
-#define PORT_PB10F_TCC0_WO4    (_UL_(1) << 10)
-#define PIN_PA17G_TCC0_WO5             _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
-#define MUX_PA17G_TCC0_WO5              _L_(6)
-#define PINMUX_PA17G_TCC0_WO5      ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
-#define PORT_PA17G_TCC0_WO5    (_UL_(1) << 17)
-#define PIN_PB17G_TCC0_WO5             _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
-#define MUX_PB17G_TCC0_WO5              _L_(6)
-#define PINMUX_PB17G_TCC0_WO5      ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
-#define PORT_PB17G_TCC0_WO5    (_UL_(1) << 17)
-#define PIN_PB11F_TCC0_WO5             _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
-#define MUX_PB11F_TCC0_WO5              _L_(5)
-#define PINMUX_PB11F_TCC0_WO5      ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
-#define PORT_PB11F_TCC0_WO5    (_UL_(1) << 11)
-#define PIN_PA18G_TCC0_WO6             _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
-#define MUX_PA18G_TCC0_WO6              _L_(6)
-#define PINMUX_PA18G_TCC0_WO6      ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
-#define PORT_PA18G_TCC0_WO6    (_UL_(1) << 18)
-#define PIN_PB30G_TCC0_WO6             _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
-#define MUX_PB30G_TCC0_WO6              _L_(6)
-#define PINMUX_PB30G_TCC0_WO6      ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
-#define PORT_PB30G_TCC0_WO6    (_UL_(1) << 30)
-#define PIN_PA12F_TCC0_WO6             _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
-#define MUX_PA12F_TCC0_WO6              _L_(5)
-#define PINMUX_PA12F_TCC0_WO6      ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
-#define PORT_PA12F_TCC0_WO6    (_UL_(1) << 12)
-#define PIN_PA19G_TCC0_WO7             _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
-#define MUX_PA19G_TCC0_WO7              _L_(6)
-#define PINMUX_PA19G_TCC0_WO7      ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
-#define PORT_PA19G_TCC0_WO7    (_UL_(1) << 19)
-#define PIN_PB31G_TCC0_WO7             _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
-#define MUX_PB31G_TCC0_WO7              _L_(6)
-#define PINMUX_PB31G_TCC0_WO7      ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
-#define PORT_PB31G_TCC0_WO7    (_UL_(1) << 31)
-#define PIN_PA13F_TCC0_WO7             _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
-#define MUX_PA13F_TCC0_WO7              _L_(5)
-#define PINMUX_PA13F_TCC0_WO7      ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
-#define PORT_PA13F_TCC0_WO7    (_UL_(1) << 13)
-/* ========== PORT definition for TCC1 peripheral ========== */
-#define PIN_PB10G_TCC1_WO0             _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
-#define MUX_PB10G_TCC1_WO0              _L_(6)
-#define PINMUX_PB10G_TCC1_WO0      ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
-#define PORT_PB10G_TCC1_WO0    (_UL_(1) << 10)
-#define PIN_PA16F_TCC1_WO0             _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
-#define MUX_PA16F_TCC1_WO0              _L_(5)
-#define PINMUX_PA16F_TCC1_WO0      ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
-#define PORT_PA16F_TCC1_WO0    (_UL_(1) << 16)
-#define PIN_PB11G_TCC1_WO1             _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
-#define MUX_PB11G_TCC1_WO1              _L_(6)
-#define PINMUX_PB11G_TCC1_WO1      ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
-#define PORT_PB11G_TCC1_WO1    (_UL_(1) << 11)
-#define PIN_PA17F_TCC1_WO1             _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
-#define MUX_PA17F_TCC1_WO1              _L_(5)
-#define PINMUX_PA17F_TCC1_WO1      ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
-#define PORT_PA17F_TCC1_WO1    (_UL_(1) << 17)
-#define PIN_PA12G_TCC1_WO2             _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
-#define MUX_PA12G_TCC1_WO2              _L_(6)
-#define PINMUX_PA12G_TCC1_WO2      ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
-#define PORT_PA12G_TCC1_WO2    (_UL_(1) << 12)
-#define PIN_PA14G_TCC1_WO2             _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
-#define MUX_PA14G_TCC1_WO2              _L_(6)
-#define PINMUX_PA14G_TCC1_WO2      ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
-#define PORT_PA14G_TCC1_WO2    (_UL_(1) << 14)
-#define PIN_PA18F_TCC1_WO2             _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
-#define MUX_PA18F_TCC1_WO2              _L_(5)
-#define PINMUX_PA18F_TCC1_WO2      ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
-#define PORT_PA18F_TCC1_WO2    (_UL_(1) << 18)
-#define PIN_PA13G_TCC1_WO3             _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
-#define MUX_PA13G_TCC1_WO3              _L_(6)
-#define PINMUX_PA13G_TCC1_WO3      ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
-#define PORT_PA13G_TCC1_WO3    (_UL_(1) << 13)
-#define PIN_PA15G_TCC1_WO3             _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
-#define MUX_PA15G_TCC1_WO3              _L_(6)
-#define PINMUX_PA15G_TCC1_WO3      ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
-#define PORT_PA15G_TCC1_WO3    (_UL_(1) << 15)
-#define PIN_PA19F_TCC1_WO3             _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
-#define MUX_PA19F_TCC1_WO3              _L_(5)
-#define PINMUX_PA19F_TCC1_WO3      ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
-#define PORT_PA19F_TCC1_WO3    (_UL_(1) << 19)
-#define PIN_PA08G_TCC1_WO4              _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
-#define MUX_PA08G_TCC1_WO4              _L_(6)
-#define PINMUX_PA08G_TCC1_WO4      ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
-#define PORT_PA08G_TCC1_WO4    (_UL_(1) <<  8)
-#define PIN_PA20F_TCC1_WO4             _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
-#define MUX_PA20F_TCC1_WO4              _L_(5)
-#define PINMUX_PA20F_TCC1_WO4      ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
-#define PORT_PA20F_TCC1_WO4    (_UL_(1) << 20)
-#define PIN_PA09G_TCC1_WO5              _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
-#define MUX_PA09G_TCC1_WO5              _L_(6)
-#define PINMUX_PA09G_TCC1_WO5      ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
-#define PORT_PA09G_TCC1_WO5    (_UL_(1) <<  9)
-#define PIN_PA21F_TCC1_WO5             _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
-#define MUX_PA21F_TCC1_WO5              _L_(5)
-#define PINMUX_PA21F_TCC1_WO5      ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
-#define PORT_PA21F_TCC1_WO5    (_UL_(1) << 21)
-#define PIN_PA10G_TCC1_WO6             _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
-#define MUX_PA10G_TCC1_WO6              _L_(6)
-#define PINMUX_PA10G_TCC1_WO6      ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
-#define PORT_PA10G_TCC1_WO6    (_UL_(1) << 10)
-#define PIN_PA22F_TCC1_WO6             _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
-#define MUX_PA22F_TCC1_WO6              _L_(5)
-#define PINMUX_PA22F_TCC1_WO6      ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
-#define PORT_PA22F_TCC1_WO6    (_UL_(1) << 22)
-#define PIN_PA11G_TCC1_WO7             _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
-#define MUX_PA11G_TCC1_WO7              _L_(6)
-#define PINMUX_PA11G_TCC1_WO7      ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
-#define PORT_PA11G_TCC1_WO7    (_UL_(1) << 11)
-#define PIN_PA23F_TCC1_WO7             _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
-#define MUX_PA23F_TCC1_WO7              _L_(5)
-#define PINMUX_PA23F_TCC1_WO7      ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
-#define PORT_PA23F_TCC1_WO7    (_UL_(1) << 23)
-/* ========== PORT definition for TC2 peripheral ========== */
-#define PIN_PA12E_TC2_WO0              _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
-#define MUX_PA12E_TC2_WO0               _L_(4)
-#define PINMUX_PA12E_TC2_WO0       ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
-#define PORT_PA12E_TC2_WO0     (_UL_(1) << 12)
-#define PIN_PA16E_TC2_WO0              _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
-#define MUX_PA16E_TC2_WO0               _L_(4)
-#define PINMUX_PA16E_TC2_WO0       ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
-#define PORT_PA16E_TC2_WO0     (_UL_(1) << 16)
-#define PIN_PA00E_TC2_WO0               _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
-#define MUX_PA00E_TC2_WO0               _L_(4)
-#define PINMUX_PA00E_TC2_WO0       ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
-#define PORT_PA00E_TC2_WO0     (_UL_(1) <<  0)
-#define PIN_PA01E_TC2_WO1               _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
-#define MUX_PA01E_TC2_WO1               _L_(4)
-#define PINMUX_PA01E_TC2_WO1       ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
-#define PORT_PA01E_TC2_WO1     (_UL_(1) <<  1)
-#define PIN_PA13E_TC2_WO1              _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
-#define MUX_PA13E_TC2_WO1               _L_(4)
-#define PINMUX_PA13E_TC2_WO1       ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
-#define PORT_PA13E_TC2_WO1     (_UL_(1) << 13)
-#define PIN_PA17E_TC2_WO1              _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
-#define MUX_PA17E_TC2_WO1               _L_(4)
-#define PINMUX_PA17E_TC2_WO1       ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
-#define PORT_PA17E_TC2_WO1     (_UL_(1) << 17)
-/* ========== PORT definition for TC3 peripheral ========== */
-#define PIN_PA18E_TC3_WO0              _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
-#define MUX_PA18E_TC3_WO0               _L_(4)
-#define PINMUX_PA18E_TC3_WO0       ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
-#define PORT_PA18E_TC3_WO0     (_UL_(1) << 18)
-#define PIN_PA14E_TC3_WO0              _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
-#define MUX_PA14E_TC3_WO0               _L_(4)
-#define PINMUX_PA14E_TC3_WO0       ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
-#define PORT_PA14E_TC3_WO0     (_UL_(1) << 14)
-#define PIN_PA15E_TC3_WO1              _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
-#define MUX_PA15E_TC3_WO1               _L_(4)
-#define PINMUX_PA15E_TC3_WO1       ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
-#define PORT_PA15E_TC3_WO1     (_UL_(1) << 15)
-#define PIN_PA19E_TC3_WO1              _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
-#define MUX_PA19E_TC3_WO1               _L_(4)
-#define PINMUX_PA19E_TC3_WO1       ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
-#define PORT_PA19E_TC3_WO1     (_UL_(1) << 19)
-/* ========== PORT definition for TAL peripheral ========== */
-#define PIN_PA27H_TAL_BRK              _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */
-#define MUX_PA27H_TAL_BRK               _L_(7)
-#define PINMUX_PA27H_TAL_BRK       ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK)
-#define PORT_PA27H_TAL_BRK     (_UL_(1) << 27)
-#define PIN_PB31H_TAL_BRK              _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */
-#define MUX_PB31H_TAL_BRK               _L_(7)
-#define PINMUX_PB31H_TAL_BRK       ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK)
-#define PORT_PB31H_TAL_BRK     (_UL_(1) << 31)
-/* ========== PORT definition for TCC2 peripheral ========== */
-#define PIN_PA14F_TCC2_WO0             _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
-#define MUX_PA14F_TCC2_WO0              _L_(5)
-#define PINMUX_PA14F_TCC2_WO0      ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
-#define PORT_PA14F_TCC2_WO0    (_UL_(1) << 14)
-#define PIN_PA30F_TCC2_WO0             _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
-#define MUX_PA30F_TCC2_WO0              _L_(5)
-#define PINMUX_PA30F_TCC2_WO0      ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
-#define PORT_PA30F_TCC2_WO0    (_UL_(1) << 30)
-#define PIN_PA15F_TCC2_WO1             _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
-#define MUX_PA15F_TCC2_WO1              _L_(5)
-#define PINMUX_PA15F_TCC2_WO1      ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
-#define PORT_PA15F_TCC2_WO1    (_UL_(1) << 15)
-#define PIN_PA31F_TCC2_WO1             _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
-#define MUX_PA31F_TCC2_WO1              _L_(5)
-#define PINMUX_PA31F_TCC2_WO1      ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
-#define PORT_PA31F_TCC2_WO1    (_UL_(1) << 31)
-#define PIN_PA24F_TCC2_WO2             _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
-#define MUX_PA24F_TCC2_WO2              _L_(5)
-#define PINMUX_PA24F_TCC2_WO2      ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
-#define PORT_PA24F_TCC2_WO2    (_UL_(1) << 24)
-#define PIN_PB02F_TCC2_WO2             _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
-#define MUX_PB02F_TCC2_WO2              _L_(5)
-#define PINMUX_PB02F_TCC2_WO2      ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
-#define PORT_PB02F_TCC2_WO2    (_UL_(1) <<  2)
-/* ========== PORT definition for TCC3 peripheral ========== */
-#define PIN_PB12F_TCC3_WO0             _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
-#define MUX_PB12F_TCC3_WO0              _L_(5)
-#define PINMUX_PB12F_TCC3_WO0      ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
-#define PORT_PB12F_TCC3_WO0    (_UL_(1) << 12)
-#define PIN_PB16F_TCC3_WO0             _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
-#define MUX_PB16F_TCC3_WO0              _L_(5)
-#define PINMUX_PB16F_TCC3_WO0      ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
-#define PORT_PB16F_TCC3_WO0    (_UL_(1) << 16)
-#define PIN_PB13F_TCC3_WO1             _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
-#define MUX_PB13F_TCC3_WO1              _L_(5)
-#define PINMUX_PB13F_TCC3_WO1      ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
-#define PORT_PB13F_TCC3_WO1    (_UL_(1) << 13)
-#define PIN_PB17F_TCC3_WO1             _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
-#define MUX_PB17F_TCC3_WO1              _L_(5)
-#define PINMUX_PB17F_TCC3_WO1      ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
-#define PORT_PB17F_TCC3_WO1    (_UL_(1) << 17)
-/* ========== PORT definition for TC4 peripheral ========== */
-#define PIN_PA22E_TC4_WO0              _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
-#define MUX_PA22E_TC4_WO0               _L_(4)
-#define PINMUX_PA22E_TC4_WO0       ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
-#define PORT_PA22E_TC4_WO0     (_UL_(1) << 22)
-#define PIN_PB08E_TC4_WO0              _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
-#define MUX_PB08E_TC4_WO0               _L_(4)
-#define PINMUX_PB08E_TC4_WO0       ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
-#define PORT_PB08E_TC4_WO0     (_UL_(1) <<  8)
-#define PIN_PB12E_TC4_WO0              _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
-#define MUX_PB12E_TC4_WO0               _L_(4)
-#define PINMUX_PB12E_TC4_WO0       ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
-#define PORT_PB12E_TC4_WO0     (_UL_(1) << 12)
-#define PIN_PA23E_TC4_WO1              _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
-#define MUX_PA23E_TC4_WO1               _L_(4)
-#define PINMUX_PA23E_TC4_WO1       ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
-#define PORT_PA23E_TC4_WO1     (_UL_(1) << 23)
-#define PIN_PB09E_TC4_WO1              _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
-#define MUX_PB09E_TC4_WO1               _L_(4)
-#define PINMUX_PB09E_TC4_WO1       ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
-#define PORT_PB09E_TC4_WO1     (_UL_(1) <<  9)
-#define PIN_PB13E_TC4_WO1              _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
-#define MUX_PB13E_TC4_WO1               _L_(4)
-#define PINMUX_PB13E_TC4_WO1       ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
-#define PORT_PB13E_TC4_WO1     (_UL_(1) << 13)
-/* ========== PORT definition for TC5 peripheral ========== */
-#define PIN_PA24E_TC5_WO0              _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
-#define MUX_PA24E_TC5_WO0               _L_(4)
-#define PINMUX_PA24E_TC5_WO0       ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
-#define PORT_PA24E_TC5_WO0     (_UL_(1) << 24)
-#define PIN_PB10E_TC5_WO0              _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
-#define MUX_PB10E_TC5_WO0               _L_(4)
-#define PINMUX_PB10E_TC5_WO0       ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
-#define PORT_PB10E_TC5_WO0     (_UL_(1) << 10)
-#define PIN_PB14E_TC5_WO0              _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
-#define MUX_PB14E_TC5_WO0               _L_(4)
-#define PINMUX_PB14E_TC5_WO0       ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
-#define PORT_PB14E_TC5_WO0     (_UL_(1) << 14)
-#define PIN_PA25E_TC5_WO1              _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
-#define MUX_PA25E_TC5_WO1               _L_(4)
-#define PINMUX_PA25E_TC5_WO1       ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
-#define PORT_PA25E_TC5_WO1     (_UL_(1) << 25)
-#define PIN_PB11E_TC5_WO1              _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
-#define MUX_PB11E_TC5_WO1               _L_(4)
-#define PINMUX_PB11E_TC5_WO1       ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
-#define PORT_PB11E_TC5_WO1     (_UL_(1) << 11)
-#define PIN_PB15E_TC5_WO1              _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
-#define MUX_PB15E_TC5_WO1               _L_(4)
-#define PINMUX_PB15E_TC5_WO1       ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
-#define PORT_PB15E_TC5_WO1     (_UL_(1) << 15)
-/* ========== PORT definition for PDEC peripheral ========== */
-#define PIN_PB23G_PDEC_QDI0            _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
-#define MUX_PB23G_PDEC_QDI0             _L_(6)
-#define PINMUX_PB23G_PDEC_QDI0     ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
-#define PORT_PB23G_PDEC_QDI0   (_UL_(1) << 23)
-#define PIN_PA24G_PDEC_QDI0            _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
-#define MUX_PA24G_PDEC_QDI0             _L_(6)
-#define PINMUX_PA24G_PDEC_QDI0     ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
-#define PORT_PA24G_PDEC_QDI0   (_UL_(1) << 24)
-#define PIN_PA25G_PDEC_QDI1            _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
-#define MUX_PA25G_PDEC_QDI1             _L_(6)
-#define PINMUX_PA25G_PDEC_QDI1     ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
-#define PORT_PA25G_PDEC_QDI1   (_UL_(1) << 25)
-#define PIN_PB22G_PDEC_QDI2            _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
-#define MUX_PB22G_PDEC_QDI2             _L_(6)
-#define PINMUX_PB22G_PDEC_QDI2     ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
-#define PORT_PB22G_PDEC_QDI2   (_UL_(1) << 22)
-/* ========== PORT definition for AC peripheral ========== */
-#define PIN_PA04B_AC_AIN0               _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
-#define MUX_PA04B_AC_AIN0               _L_(1)
-#define PINMUX_PA04B_AC_AIN0       ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
-#define PORT_PA04B_AC_AIN0     (_UL_(1) <<  4)
-#define PIN_PA05B_AC_AIN1               _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
-#define MUX_PA05B_AC_AIN1               _L_(1)
-#define PINMUX_PA05B_AC_AIN1       ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
-#define PORT_PA05B_AC_AIN1     (_UL_(1) <<  5)
-#define PIN_PA06B_AC_AIN2               _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
-#define MUX_PA06B_AC_AIN2               _L_(1)
-#define PINMUX_PA06B_AC_AIN2       ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
-#define PORT_PA06B_AC_AIN2     (_UL_(1) <<  6)
-#define PIN_PA07B_AC_AIN3               _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
-#define MUX_PA07B_AC_AIN3               _L_(1)
-#define PINMUX_PA07B_AC_AIN3       ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
-#define PORT_PA07B_AC_AIN3     (_UL_(1) <<  7)
-#define PIN_PA12M_AC_CMP0              _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
-#define MUX_PA12M_AC_CMP0              _L_(12)
-#define PINMUX_PA12M_AC_CMP0       ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
-#define PORT_PA12M_AC_CMP0     (_UL_(1) << 12)
-#define PIN_PA18M_AC_CMP0              _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
-#define MUX_PA18M_AC_CMP0              _L_(12)
-#define PINMUX_PA18M_AC_CMP0       ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
-#define PORT_PA18M_AC_CMP0     (_UL_(1) << 18)
-#define PIN_PA13M_AC_CMP1              _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
-#define MUX_PA13M_AC_CMP1              _L_(12)
-#define PINMUX_PA13M_AC_CMP1       ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
-#define PORT_PA13M_AC_CMP1     (_UL_(1) << 13)
-#define PIN_PA19M_AC_CMP1              _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
-#define MUX_PA19M_AC_CMP1              _L_(12)
-#define PINMUX_PA19M_AC_CMP1       ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
-#define PORT_PA19M_AC_CMP1     (_UL_(1) << 19)
-/* ========== PORT definition for QSPI peripheral ========== */
-#define PIN_PB11H_QSPI_CS              _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
-#define MUX_PB11H_QSPI_CS               _L_(7)
-#define PINMUX_PB11H_QSPI_CS       ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
-#define PORT_PB11H_QSPI_CS     (_UL_(1) << 11)
-#define PIN_PA08H_QSPI_DATA0            _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
-#define MUX_PA08H_QSPI_DATA0            _L_(7)
-#define PINMUX_PA08H_QSPI_DATA0    ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
-#define PORT_PA08H_QSPI_DATA0  (_UL_(1) <<  8)
-#define PIN_PA09H_QSPI_DATA1            _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
-#define MUX_PA09H_QSPI_DATA1            _L_(7)
-#define PINMUX_PA09H_QSPI_DATA1    ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
-#define PORT_PA09H_QSPI_DATA1  (_UL_(1) <<  9)
-#define PIN_PA10H_QSPI_DATA2           _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
-#define MUX_PA10H_QSPI_DATA2            _L_(7)
-#define PINMUX_PA10H_QSPI_DATA2    ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
-#define PORT_PA10H_QSPI_DATA2  (_UL_(1) << 10)
-#define PIN_PA11H_QSPI_DATA3           _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
-#define MUX_PA11H_QSPI_DATA3            _L_(7)
-#define PINMUX_PA11H_QSPI_DATA3    ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
-#define PORT_PA11H_QSPI_DATA3  (_UL_(1) << 11)
-#define PIN_PB10H_QSPI_SCK             _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
-#define MUX_PB10H_QSPI_SCK              _L_(7)
-#define PINMUX_PB10H_QSPI_SCK      ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
-#define PORT_PB10H_QSPI_SCK    (_UL_(1) << 10)
-/* ========== PORT definition for CCL peripheral ========== */
-#define PIN_PA04N_CCL_IN0               _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
-#define MUX_PA04N_CCL_IN0              _L_(13)
-#define PINMUX_PA04N_CCL_IN0       ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
-#define PORT_PA04N_CCL_IN0     (_UL_(1) <<  4)
-#define PIN_PA16N_CCL_IN0              _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
-#define MUX_PA16N_CCL_IN0              _L_(13)
-#define PINMUX_PA16N_CCL_IN0       ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
-#define PORT_PA16N_CCL_IN0     (_UL_(1) << 16)
-#define PIN_PB22N_CCL_IN0              _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
-#define MUX_PB22N_CCL_IN0              _L_(13)
-#define PINMUX_PB22N_CCL_IN0       ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
-#define PORT_PB22N_CCL_IN0     (_UL_(1) << 22)
-#define PIN_PA05N_CCL_IN1               _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
-#define MUX_PA05N_CCL_IN1              _L_(13)
-#define PINMUX_PA05N_CCL_IN1       ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
-#define PORT_PA05N_CCL_IN1     (_UL_(1) <<  5)
-#define PIN_PA17N_CCL_IN1              _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
-#define MUX_PA17N_CCL_IN1              _L_(13)
-#define PINMUX_PA17N_CCL_IN1       ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
-#define PORT_PA17N_CCL_IN1     (_UL_(1) << 17)
-#define PIN_PB00N_CCL_IN1              _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
-#define MUX_PB00N_CCL_IN1              _L_(13)
-#define PINMUX_PB00N_CCL_IN1       ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
-#define PORT_PB00N_CCL_IN1     (_UL_(1) <<  0)
-#define PIN_PA06N_CCL_IN2               _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
-#define MUX_PA06N_CCL_IN2              _L_(13)
-#define PINMUX_PA06N_CCL_IN2       ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
-#define PORT_PA06N_CCL_IN2     (_UL_(1) <<  6)
-#define PIN_PA18N_CCL_IN2              _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
-#define MUX_PA18N_CCL_IN2              _L_(13)
-#define PINMUX_PA18N_CCL_IN2       ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
-#define PORT_PA18N_CCL_IN2     (_UL_(1) << 18)
-#define PIN_PB01N_CCL_IN2              _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
-#define MUX_PB01N_CCL_IN2              _L_(13)
-#define PINMUX_PB01N_CCL_IN2       ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
-#define PORT_PB01N_CCL_IN2     (_UL_(1) <<  1)
-#define PIN_PA08N_CCL_IN3               _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
-#define MUX_PA08N_CCL_IN3              _L_(13)
-#define PINMUX_PA08N_CCL_IN3       ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
-#define PORT_PA08N_CCL_IN3     (_UL_(1) <<  8)
-#define PIN_PA30N_CCL_IN3              _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
-#define MUX_PA30N_CCL_IN3              _L_(13)
-#define PINMUX_PA30N_CCL_IN3       ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
-#define PORT_PA30N_CCL_IN3     (_UL_(1) << 30)
-#define PIN_PA09N_CCL_IN4               _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
-#define MUX_PA09N_CCL_IN4              _L_(13)
-#define PINMUX_PA09N_CCL_IN4       ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
-#define PORT_PA09N_CCL_IN4     (_UL_(1) <<  9)
-#define PIN_PA10N_CCL_IN5              _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
-#define MUX_PA10N_CCL_IN5              _L_(13)
-#define PINMUX_PA10N_CCL_IN5       ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
-#define PORT_PA10N_CCL_IN5     (_UL_(1) << 10)
-#define PIN_PA22N_CCL_IN6              _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
-#define MUX_PA22N_CCL_IN6              _L_(13)
-#define PINMUX_PA22N_CCL_IN6       ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
-#define PORT_PA22N_CCL_IN6     (_UL_(1) << 22)
-#define PIN_PB06N_CCL_IN6              _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
-#define MUX_PB06N_CCL_IN6              _L_(13)
-#define PINMUX_PB06N_CCL_IN6       ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
-#define PORT_PB06N_CCL_IN6     (_UL_(1) <<  6)
-#define PIN_PA23N_CCL_IN7              _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
-#define MUX_PA23N_CCL_IN7              _L_(13)
-#define PINMUX_PA23N_CCL_IN7       ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
-#define PORT_PA23N_CCL_IN7     (_UL_(1) << 23)
-#define PIN_PB07N_CCL_IN7              _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
-#define MUX_PB07N_CCL_IN7              _L_(13)
-#define PINMUX_PB07N_CCL_IN7       ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
-#define PORT_PB07N_CCL_IN7     (_UL_(1) <<  7)
-#define PIN_PA24N_CCL_IN8              _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
-#define MUX_PA24N_CCL_IN8              _L_(13)
-#define PINMUX_PA24N_CCL_IN8       ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
-#define PORT_PA24N_CCL_IN8     (_UL_(1) << 24)
-#define PIN_PB08N_CCL_IN8              _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
-#define MUX_PB08N_CCL_IN8              _L_(13)
-#define PINMUX_PB08N_CCL_IN8       ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
-#define PORT_PB08N_CCL_IN8     (_UL_(1) <<  8)
-#define PIN_PB14N_CCL_IN9              _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
-#define MUX_PB14N_CCL_IN9              _L_(13)
-#define PINMUX_PB14N_CCL_IN9       ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
-#define PORT_PB14N_CCL_IN9     (_UL_(1) << 14)
-#define PIN_PB15N_CCL_IN10             _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
-#define MUX_PB15N_CCL_IN10             _L_(13)
-#define PINMUX_PB15N_CCL_IN10      ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
-#define PORT_PB15N_CCL_IN10    (_UL_(1) << 15)
-#define PIN_PB10N_CCL_IN11             _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
-#define MUX_PB10N_CCL_IN11             _L_(13)
-#define PINMUX_PB10N_CCL_IN11      ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
-#define PORT_PB10N_CCL_IN11    (_UL_(1) << 10)
-#define PIN_PB16N_CCL_IN11             _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
-#define MUX_PB16N_CCL_IN11             _L_(13)
-#define PINMUX_PB16N_CCL_IN11      ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
-#define PORT_PB16N_CCL_IN11    (_UL_(1) << 16)
-#define PIN_PA07N_CCL_OUT0              _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
-#define MUX_PA07N_CCL_OUT0             _L_(13)
-#define PINMUX_PA07N_CCL_OUT0      ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
-#define PORT_PA07N_CCL_OUT0    (_UL_(1) <<  7)
-#define PIN_PA19N_CCL_OUT0             _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
-#define MUX_PA19N_CCL_OUT0             _L_(13)
-#define PINMUX_PA19N_CCL_OUT0      ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
-#define PORT_PA19N_CCL_OUT0    (_UL_(1) << 19)
-#define PIN_PB02N_CCL_OUT0             _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
-#define MUX_PB02N_CCL_OUT0             _L_(13)
-#define PINMUX_PB02N_CCL_OUT0      ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
-#define PORT_PB02N_CCL_OUT0    (_UL_(1) <<  2)
-#define PIN_PB23N_CCL_OUT0             _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
-#define MUX_PB23N_CCL_OUT0             _L_(13)
-#define PINMUX_PB23N_CCL_OUT0      ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
-#define PORT_PB23N_CCL_OUT0    (_UL_(1) << 23)
-#define PIN_PA11N_CCL_OUT1             _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
-#define MUX_PA11N_CCL_OUT1             _L_(13)
-#define PINMUX_PA11N_CCL_OUT1      ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
-#define PORT_PA11N_CCL_OUT1    (_UL_(1) << 11)
-#define PIN_PA31N_CCL_OUT1             _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
-#define MUX_PA31N_CCL_OUT1             _L_(13)
-#define PINMUX_PA31N_CCL_OUT1      ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
-#define PORT_PA31N_CCL_OUT1    (_UL_(1) << 31)
-#define PIN_PB11N_CCL_OUT1             _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
-#define MUX_PB11N_CCL_OUT1             _L_(13)
-#define PINMUX_PB11N_CCL_OUT1      ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
-#define PORT_PB11N_CCL_OUT1    (_UL_(1) << 11)
-#define PIN_PA25N_CCL_OUT2             _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
-#define MUX_PA25N_CCL_OUT2             _L_(13)
-#define PINMUX_PA25N_CCL_OUT2      ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
-#define PORT_PA25N_CCL_OUT2    (_UL_(1) << 25)
-#define PIN_PB09N_CCL_OUT2             _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
-#define MUX_PB09N_CCL_OUT2             _L_(13)
-#define PINMUX_PB09N_CCL_OUT2      ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
-#define PORT_PB09N_CCL_OUT2    (_UL_(1) <<  9)
-#define PIN_PB17N_CCL_OUT3             _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
-#define MUX_PB17N_CCL_OUT3             _L_(13)
-#define PINMUX_PB17N_CCL_OUT3      ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
-#define PORT_PB17N_CCL_OUT3    (_UL_(1) << 17)
-/* ========== PORT definition for SERCOM4 peripheral ========== */
-#define PIN_PA13D_SERCOM4_PAD0         _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
-#define MUX_PA13D_SERCOM4_PAD0          _L_(3)
-#define PINMUX_PA13D_SERCOM4_PAD0  ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
-#define PORT_PA13D_SERCOM4_PAD0  (_UL_(1) << 13)
-#define PIN_PB08D_SERCOM4_PAD0         _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
-#define MUX_PB08D_SERCOM4_PAD0          _L_(3)
-#define PINMUX_PB08D_SERCOM4_PAD0  ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
-#define PORT_PB08D_SERCOM4_PAD0  (_UL_(1) <<  8)
-#define PIN_PB12C_SERCOM4_PAD0         _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
-#define MUX_PB12C_SERCOM4_PAD0          _L_(2)
-#define PINMUX_PB12C_SERCOM4_PAD0  ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
-#define PORT_PB12C_SERCOM4_PAD0  (_UL_(1) << 12)
-#define PIN_PA12D_SERCOM4_PAD1         _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
-#define MUX_PA12D_SERCOM4_PAD1          _L_(3)
-#define PINMUX_PA12D_SERCOM4_PAD1  ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
-#define PORT_PA12D_SERCOM4_PAD1  (_UL_(1) << 12)
-#define PIN_PB09D_SERCOM4_PAD1         _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
-#define MUX_PB09D_SERCOM4_PAD1          _L_(3)
-#define PINMUX_PB09D_SERCOM4_PAD1  ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
-#define PORT_PB09D_SERCOM4_PAD1  (_UL_(1) <<  9)
-#define PIN_PB13C_SERCOM4_PAD1         _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
-#define MUX_PB13C_SERCOM4_PAD1          _L_(2)
-#define PINMUX_PB13C_SERCOM4_PAD1  ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
-#define PORT_PB13C_SERCOM4_PAD1  (_UL_(1) << 13)
-#define PIN_PA14D_SERCOM4_PAD2         _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
-#define MUX_PA14D_SERCOM4_PAD2          _L_(3)
-#define PINMUX_PA14D_SERCOM4_PAD2  ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
-#define PORT_PA14D_SERCOM4_PAD2  (_UL_(1) << 14)
-#define PIN_PB10D_SERCOM4_PAD2         _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
-#define MUX_PB10D_SERCOM4_PAD2          _L_(3)
-#define PINMUX_PB10D_SERCOM4_PAD2  ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
-#define PORT_PB10D_SERCOM4_PAD2  (_UL_(1) << 10)
-#define PIN_PB14C_SERCOM4_PAD2         _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
-#define MUX_PB14C_SERCOM4_PAD2          _L_(2)
-#define PINMUX_PB14C_SERCOM4_PAD2  ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
-#define PORT_PB14C_SERCOM4_PAD2  (_UL_(1) << 14)
-#define PIN_PB11D_SERCOM4_PAD3         _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
-#define MUX_PB11D_SERCOM4_PAD3          _L_(3)
-#define PINMUX_PB11D_SERCOM4_PAD3  ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
-#define PORT_PB11D_SERCOM4_PAD3  (_UL_(1) << 11)
-#define PIN_PA15D_SERCOM4_PAD3         _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
-#define MUX_PA15D_SERCOM4_PAD3          _L_(3)
-#define PINMUX_PA15D_SERCOM4_PAD3  ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
-#define PORT_PA15D_SERCOM4_PAD3  (_UL_(1) << 15)
-#define PIN_PB15C_SERCOM4_PAD3         _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
-#define MUX_PB15C_SERCOM4_PAD3          _L_(2)
-#define PINMUX_PB15C_SERCOM4_PAD3  ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
-#define PORT_PB15C_SERCOM4_PAD3  (_UL_(1) << 15)
-/* ========== PORT definition for SERCOM5 peripheral ========== */
-#define PIN_PA23D_SERCOM5_PAD0         _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
-#define MUX_PA23D_SERCOM5_PAD0          _L_(3)
-#define PINMUX_PA23D_SERCOM5_PAD0  ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
-#define PORT_PA23D_SERCOM5_PAD0  (_UL_(1) << 23)
-#define PIN_PB02D_SERCOM5_PAD0         _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
-#define MUX_PB02D_SERCOM5_PAD0          _L_(3)
-#define PINMUX_PB02D_SERCOM5_PAD0  ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
-#define PORT_PB02D_SERCOM5_PAD0  (_UL_(1) <<  2)
-#define PIN_PB31D_SERCOM5_PAD0         _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
-#define MUX_PB31D_SERCOM5_PAD0          _L_(3)
-#define PINMUX_PB31D_SERCOM5_PAD0  ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
-#define PORT_PB31D_SERCOM5_PAD0  (_UL_(1) << 31)
-#define PIN_PB16C_SERCOM5_PAD0         _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
-#define MUX_PB16C_SERCOM5_PAD0          _L_(2)
-#define PINMUX_PB16C_SERCOM5_PAD0  ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
-#define PORT_PB16C_SERCOM5_PAD0  (_UL_(1) << 16)
-#define PIN_PA22D_SERCOM5_PAD1         _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
-#define MUX_PA22D_SERCOM5_PAD1          _L_(3)
-#define PINMUX_PA22D_SERCOM5_PAD1  ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
-#define PORT_PA22D_SERCOM5_PAD1  (_UL_(1) << 22)
-#define PIN_PB03D_SERCOM5_PAD1         _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
-#define MUX_PB03D_SERCOM5_PAD1          _L_(3)
-#define PINMUX_PB03D_SERCOM5_PAD1  ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
-#define PORT_PB03D_SERCOM5_PAD1  (_UL_(1) <<  3)
-#define PIN_PB30D_SERCOM5_PAD1         _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
-#define MUX_PB30D_SERCOM5_PAD1          _L_(3)
-#define PINMUX_PB30D_SERCOM5_PAD1  ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
-#define PORT_PB30D_SERCOM5_PAD1  (_UL_(1) << 30)
-#define PIN_PB17C_SERCOM5_PAD1         _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
-#define MUX_PB17C_SERCOM5_PAD1          _L_(2)
-#define PINMUX_PB17C_SERCOM5_PAD1  ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
-#define PORT_PB17C_SERCOM5_PAD1  (_UL_(1) << 17)
-#define PIN_PA24D_SERCOM5_PAD2         _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
-#define MUX_PA24D_SERCOM5_PAD2          _L_(3)
-#define PINMUX_PA24D_SERCOM5_PAD2  ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
-#define PORT_PA24D_SERCOM5_PAD2  (_UL_(1) << 24)
-#define PIN_PB00D_SERCOM5_PAD2         _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
-#define MUX_PB00D_SERCOM5_PAD2          _L_(3)
-#define PINMUX_PB00D_SERCOM5_PAD2  ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
-#define PORT_PB00D_SERCOM5_PAD2  (_UL_(1) <<  0)
-#define PIN_PB22D_SERCOM5_PAD2         _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
-#define MUX_PB22D_SERCOM5_PAD2          _L_(3)
-#define PINMUX_PB22D_SERCOM5_PAD2  ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
-#define PORT_PB22D_SERCOM5_PAD2  (_UL_(1) << 22)
-#define PIN_PA20C_SERCOM5_PAD2         _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
-#define MUX_PA20C_SERCOM5_PAD2          _L_(2)
-#define PINMUX_PA20C_SERCOM5_PAD2  ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
-#define PORT_PA20C_SERCOM5_PAD2  (_UL_(1) << 20)
-#define PIN_PA25D_SERCOM5_PAD3         _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
-#define MUX_PA25D_SERCOM5_PAD3          _L_(3)
-#define PINMUX_PA25D_SERCOM5_PAD3  ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
-#define PORT_PA25D_SERCOM5_PAD3  (_UL_(1) << 25)
-#define PIN_PB01D_SERCOM5_PAD3         _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
-#define MUX_PB01D_SERCOM5_PAD3          _L_(3)
-#define PINMUX_PB01D_SERCOM5_PAD3  ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
-#define PORT_PB01D_SERCOM5_PAD3  (_UL_(1) <<  1)
-#define PIN_PB23D_SERCOM5_PAD3         _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
-#define MUX_PB23D_SERCOM5_PAD3          _L_(3)
-#define PINMUX_PB23D_SERCOM5_PAD3  ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
-#define PORT_PB23D_SERCOM5_PAD3  (_UL_(1) << 23)
-#define PIN_PA21C_SERCOM5_PAD3         _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
-#define MUX_PA21C_SERCOM5_PAD3          _L_(2)
-#define PINMUX_PA21C_SERCOM5_PAD3  ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
-#define PORT_PA21C_SERCOM5_PAD3  (_UL_(1) << 21)
-/* ========== PORT definition for TCC4 peripheral ========== */
-#define PIN_PB14F_TCC4_WO0             _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
-#define MUX_PB14F_TCC4_WO0              _L_(5)
-#define PINMUX_PB14F_TCC4_WO0      ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
-#define PORT_PB14F_TCC4_WO0    (_UL_(1) << 14)
-#define PIN_PB30F_TCC4_WO0             _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
-#define MUX_PB30F_TCC4_WO0              _L_(5)
-#define PINMUX_PB30F_TCC4_WO0      ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
-#define PORT_PB30F_TCC4_WO0    (_UL_(1) << 30)
-#define PIN_PB15F_TCC4_WO1             _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
-#define MUX_PB15F_TCC4_WO1              _L_(5)
-#define PINMUX_PB15F_TCC4_WO1      ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
-#define PORT_PB15F_TCC4_WO1    (_UL_(1) << 15)
-#define PIN_PB31F_TCC4_WO1             _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
-#define MUX_PB31F_TCC4_WO1              _L_(5)
-#define PINMUX_PB31F_TCC4_WO1      ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
-#define PORT_PB31F_TCC4_WO1    (_UL_(1) << 31)
-/* ========== PORT definition for ADC0 peripheral ========== */
-#define PIN_PA02B_ADC0_AIN0             _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
-#define MUX_PA02B_ADC0_AIN0             _L_(1)
-#define PINMUX_PA02B_ADC0_AIN0     ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
-#define PORT_PA02B_ADC0_AIN0   (_UL_(1) <<  2)
-#define PIN_PA03B_ADC0_AIN1             _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
-#define MUX_PA03B_ADC0_AIN1             _L_(1)
-#define PINMUX_PA03B_ADC0_AIN1     ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
-#define PORT_PA03B_ADC0_AIN1   (_UL_(1) <<  3)
-#define PIN_PB08B_ADC0_AIN2            _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
-#define MUX_PB08B_ADC0_AIN2             _L_(1)
-#define PINMUX_PB08B_ADC0_AIN2     ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
-#define PORT_PB08B_ADC0_AIN2   (_UL_(1) <<  8)
-#define PIN_PB09B_ADC0_AIN3            _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
-#define MUX_PB09B_ADC0_AIN3             _L_(1)
-#define PINMUX_PB09B_ADC0_AIN3     ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
-#define PORT_PB09B_ADC0_AIN3   (_UL_(1) <<  9)
-#define PIN_PA04B_ADC0_AIN4             _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
-#define MUX_PA04B_ADC0_AIN4             _L_(1)
-#define PINMUX_PA04B_ADC0_AIN4     ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
-#define PORT_PA04B_ADC0_AIN4   (_UL_(1) <<  4)
-#define PIN_PA05B_ADC0_AIN5             _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
-#define MUX_PA05B_ADC0_AIN5             _L_(1)
-#define PINMUX_PA05B_ADC0_AIN5     ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
-#define PORT_PA05B_ADC0_AIN5   (_UL_(1) <<  5)
-#define PIN_PA06B_ADC0_AIN6             _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
-#define MUX_PA06B_ADC0_AIN6             _L_(1)
-#define PINMUX_PA06B_ADC0_AIN6     ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
-#define PORT_PA06B_ADC0_AIN6   (_UL_(1) <<  6)
-#define PIN_PA07B_ADC0_AIN7             _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
-#define MUX_PA07B_ADC0_AIN7             _L_(1)
-#define PINMUX_PA07B_ADC0_AIN7     ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
-#define PORT_PA07B_ADC0_AIN7   (_UL_(1) <<  7)
-#define PIN_PA08B_ADC0_AIN8             _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
-#define MUX_PA08B_ADC0_AIN8             _L_(1)
-#define PINMUX_PA08B_ADC0_AIN8     ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
-#define PORT_PA08B_ADC0_AIN8   (_UL_(1) <<  8)
-#define PIN_PA09B_ADC0_AIN9             _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
-#define MUX_PA09B_ADC0_AIN9             _L_(1)
-#define PINMUX_PA09B_ADC0_AIN9     ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
-#define PORT_PA09B_ADC0_AIN9   (_UL_(1) <<  9)
-#define PIN_PA10B_ADC0_AIN10           _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
-#define MUX_PA10B_ADC0_AIN10            _L_(1)
-#define PINMUX_PA10B_ADC0_AIN10    ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
-#define PORT_PA10B_ADC0_AIN10  (_UL_(1) << 10)
-#define PIN_PA11B_ADC0_AIN11           _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
-#define MUX_PA11B_ADC0_AIN11            _L_(1)
-#define PINMUX_PA11B_ADC0_AIN11    ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
-#define PORT_PA11B_ADC0_AIN11  (_UL_(1) << 11)
-#define PIN_PB00B_ADC0_AIN12           _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
-#define MUX_PB00B_ADC0_AIN12            _L_(1)
-#define PINMUX_PB00B_ADC0_AIN12    ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
-#define PORT_PB00B_ADC0_AIN12  (_UL_(1) <<  0)
-#define PIN_PB01B_ADC0_AIN13           _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
-#define MUX_PB01B_ADC0_AIN13            _L_(1)
-#define PINMUX_PB01B_ADC0_AIN13    ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
-#define PORT_PB01B_ADC0_AIN13  (_UL_(1) <<  1)
-#define PIN_PB02B_ADC0_AIN14           _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
-#define MUX_PB02B_ADC0_AIN14            _L_(1)
-#define PINMUX_PB02B_ADC0_AIN14    ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
-#define PORT_PB02B_ADC0_AIN14  (_UL_(1) <<  2)
-#define PIN_PB03B_ADC0_AIN15           _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
-#define MUX_PB03B_ADC0_AIN15            _L_(1)
-#define PINMUX_PB03B_ADC0_AIN15    ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
-#define PORT_PB03B_ADC0_AIN15  (_UL_(1) <<  3)
-#define PIN_PA03O_ADC0_DRV0             _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
-#define MUX_PA03O_ADC0_DRV0            _L_(14)
-#define PINMUX_PA03O_ADC0_DRV0     ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
-#define PORT_PA03O_ADC0_DRV0   (_UL_(1) <<  3)
-#define PIN_PB08O_ADC0_DRV1            _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
-#define MUX_PB08O_ADC0_DRV1            _L_(14)
-#define PINMUX_PB08O_ADC0_DRV1     ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
-#define PORT_PB08O_ADC0_DRV1   (_UL_(1) <<  8)
-#define PIN_PB09O_ADC0_DRV2            _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
-#define MUX_PB09O_ADC0_DRV2            _L_(14)
-#define PINMUX_PB09O_ADC0_DRV2     ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
-#define PORT_PB09O_ADC0_DRV2   (_UL_(1) <<  9)
-#define PIN_PA04O_ADC0_DRV3             _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
-#define MUX_PA04O_ADC0_DRV3            _L_(14)
-#define PINMUX_PA04O_ADC0_DRV3     ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
-#define PORT_PA04O_ADC0_DRV3   (_UL_(1) <<  4)
-#define PIN_PA06O_ADC0_DRV4             _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
-#define MUX_PA06O_ADC0_DRV4            _L_(14)
-#define PINMUX_PA06O_ADC0_DRV4     ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
-#define PORT_PA06O_ADC0_DRV4   (_UL_(1) <<  6)
-#define PIN_PA07O_ADC0_DRV5             _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
-#define MUX_PA07O_ADC0_DRV5            _L_(14)
-#define PINMUX_PA07O_ADC0_DRV5     ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
-#define PORT_PA07O_ADC0_DRV5   (_UL_(1) <<  7)
-#define PIN_PA08O_ADC0_DRV6             _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
-#define MUX_PA08O_ADC0_DRV6            _L_(14)
-#define PINMUX_PA08O_ADC0_DRV6     ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
-#define PORT_PA08O_ADC0_DRV6   (_UL_(1) <<  8)
-#define PIN_PA09O_ADC0_DRV7             _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
-#define MUX_PA09O_ADC0_DRV7            _L_(14)
-#define PINMUX_PA09O_ADC0_DRV7     ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
-#define PORT_PA09O_ADC0_DRV7   (_UL_(1) <<  9)
-#define PIN_PA10O_ADC0_DRV8            _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
-#define MUX_PA10O_ADC0_DRV8            _L_(14)
-#define PINMUX_PA10O_ADC0_DRV8     ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
-#define PORT_PA10O_ADC0_DRV8   (_UL_(1) << 10)
-#define PIN_PA11O_ADC0_DRV9            _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
-#define MUX_PA11O_ADC0_DRV9            _L_(14)
-#define PINMUX_PA11O_ADC0_DRV9     ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
-#define PORT_PA11O_ADC0_DRV9   (_UL_(1) << 11)
-#define PIN_PA16O_ADC0_DRV10           _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
-#define MUX_PA16O_ADC0_DRV10           _L_(14)
-#define PINMUX_PA16O_ADC0_DRV10    ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
-#define PORT_PA16O_ADC0_DRV10  (_UL_(1) << 16)
-#define PIN_PA17O_ADC0_DRV11           _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
-#define MUX_PA17O_ADC0_DRV11           _L_(14)
-#define PINMUX_PA17O_ADC0_DRV11    ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
-#define PORT_PA17O_ADC0_DRV11  (_UL_(1) << 17)
-#define PIN_PA18O_ADC0_DRV12           _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
-#define MUX_PA18O_ADC0_DRV12           _L_(14)
-#define PINMUX_PA18O_ADC0_DRV12    ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
-#define PORT_PA18O_ADC0_DRV12  (_UL_(1) << 18)
-#define PIN_PA19O_ADC0_DRV13           _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
-#define MUX_PA19O_ADC0_DRV13           _L_(14)
-#define PINMUX_PA19O_ADC0_DRV13    ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
-#define PORT_PA19O_ADC0_DRV13  (_UL_(1) << 19)
-#define PIN_PA20O_ADC0_DRV14           _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
-#define MUX_PA20O_ADC0_DRV14           _L_(14)
-#define PINMUX_PA20O_ADC0_DRV14    ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
-#define PORT_PA20O_ADC0_DRV14  (_UL_(1) << 20)
-#define PIN_PA21O_ADC0_DRV15           _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
-#define MUX_PA21O_ADC0_DRV15           _L_(14)
-#define PINMUX_PA21O_ADC0_DRV15    ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
-#define PORT_PA21O_ADC0_DRV15  (_UL_(1) << 21)
-#define PIN_PA22O_ADC0_DRV16           _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
-#define MUX_PA22O_ADC0_DRV16           _L_(14)
-#define PINMUX_PA22O_ADC0_DRV16    ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
-#define PORT_PA22O_ADC0_DRV16  (_UL_(1) << 22)
-#define PIN_PA23O_ADC0_DRV17           _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
-#define MUX_PA23O_ADC0_DRV17           _L_(14)
-#define PINMUX_PA23O_ADC0_DRV17    ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
-#define PORT_PA23O_ADC0_DRV17  (_UL_(1) << 23)
-#define PIN_PA27O_ADC0_DRV18           _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
-#define MUX_PA27O_ADC0_DRV18           _L_(14)
-#define PINMUX_PA27O_ADC0_DRV18    ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
-#define PORT_PA27O_ADC0_DRV18  (_UL_(1) << 27)
-#define PIN_PA30O_ADC0_DRV19           _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
-#define MUX_PA30O_ADC0_DRV19           _L_(14)
-#define PINMUX_PA30O_ADC0_DRV19    ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
-#define PORT_PA30O_ADC0_DRV19  (_UL_(1) << 30)
-#define PIN_PB02O_ADC0_DRV20           _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
-#define MUX_PB02O_ADC0_DRV20           _L_(14)
-#define PINMUX_PB02O_ADC0_DRV20    ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
-#define PORT_PB02O_ADC0_DRV20  (_UL_(1) <<  2)
-#define PIN_PB03O_ADC0_DRV21           _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
-#define MUX_PB03O_ADC0_DRV21           _L_(14)
-#define PINMUX_PB03O_ADC0_DRV21    ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
-#define PORT_PB03O_ADC0_DRV21  (_UL_(1) <<  3)
-#define PIN_PB04O_ADC0_DRV22           _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
-#define MUX_PB04O_ADC0_DRV22           _L_(14)
-#define PINMUX_PB04O_ADC0_DRV22    ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
-#define PORT_PB04O_ADC0_DRV22  (_UL_(1) <<  4)
-#define PIN_PB05O_ADC0_DRV23           _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
-#define MUX_PB05O_ADC0_DRV23           _L_(14)
-#define PINMUX_PB05O_ADC0_DRV23    ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
-#define PORT_PB05O_ADC0_DRV23  (_UL_(1) <<  5)
-#define PIN_PB06O_ADC0_DRV24           _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
-#define MUX_PB06O_ADC0_DRV24           _L_(14)
-#define PINMUX_PB06O_ADC0_DRV24    ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
-#define PORT_PB06O_ADC0_DRV24  (_UL_(1) <<  6)
-#define PIN_PB07O_ADC0_DRV25           _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
-#define MUX_PB07O_ADC0_DRV25           _L_(14)
-#define PINMUX_PB07O_ADC0_DRV25    ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
-#define PORT_PB07O_ADC0_DRV25  (_UL_(1) <<  7)
-#define PIN_PB12O_ADC0_DRV26           _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
-#define MUX_PB12O_ADC0_DRV26           _L_(14)
-#define PINMUX_PB12O_ADC0_DRV26    ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
-#define PORT_PB12O_ADC0_DRV26  (_UL_(1) << 12)
-#define PIN_PB13O_ADC0_DRV27           _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
-#define MUX_PB13O_ADC0_DRV27           _L_(14)
-#define PINMUX_PB13O_ADC0_DRV27    ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
-#define PORT_PB13O_ADC0_DRV27  (_UL_(1) << 13)
-#define PIN_PB14O_ADC0_DRV28           _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
-#define MUX_PB14O_ADC0_DRV28           _L_(14)
-#define PINMUX_PB14O_ADC0_DRV28    ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
-#define PORT_PB14O_ADC0_DRV28  (_UL_(1) << 14)
-#define PIN_PB15O_ADC0_DRV29           _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
-#define MUX_PB15O_ADC0_DRV29           _L_(14)
-#define PINMUX_PB15O_ADC0_DRV29    ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
-#define PORT_PB15O_ADC0_DRV29  (_UL_(1) << 15)
-#define PIN_PB00O_ADC0_DRV30           _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
-#define MUX_PB00O_ADC0_DRV30           _L_(14)
-#define PINMUX_PB00O_ADC0_DRV30    ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
-#define PORT_PB00O_ADC0_DRV30  (_UL_(1) <<  0)
-#define PIN_PB01O_ADC0_DRV31           _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
-#define MUX_PB01O_ADC0_DRV31           _L_(14)
-#define PINMUX_PB01O_ADC0_DRV31    ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
-#define PORT_PB01O_ADC0_DRV31  (_UL_(1) <<  1)
-#define PIN_PA03B_ADC0_PTCXY0           _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
-#define MUX_PA03B_ADC0_PTCXY0           _L_(1)
-#define PINMUX_PA03B_ADC0_PTCXY0   ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
-#define PORT_PA03B_ADC0_PTCXY0  (_UL_(1) <<  3)
-#define PIN_PB08B_ADC0_PTCXY1          _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
-#define MUX_PB08B_ADC0_PTCXY1           _L_(1)
-#define PINMUX_PB08B_ADC0_PTCXY1   ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
-#define PORT_PB08B_ADC0_PTCXY1  (_UL_(1) <<  8)
-#define PIN_PB09B_ADC0_PTCXY2          _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
-#define MUX_PB09B_ADC0_PTCXY2           _L_(1)
-#define PINMUX_PB09B_ADC0_PTCXY2   ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
-#define PORT_PB09B_ADC0_PTCXY2  (_UL_(1) <<  9)
-#define PIN_PA04B_ADC0_PTCXY3           _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
-#define MUX_PA04B_ADC0_PTCXY3           _L_(1)
-#define PINMUX_PA04B_ADC0_PTCXY3   ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
-#define PORT_PA04B_ADC0_PTCXY3  (_UL_(1) <<  4)
-#define PIN_PA06B_ADC0_PTCXY4           _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
-#define MUX_PA06B_ADC0_PTCXY4           _L_(1)
-#define PINMUX_PA06B_ADC0_PTCXY4   ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
-#define PORT_PA06B_ADC0_PTCXY4  (_UL_(1) <<  6)
-#define PIN_PA07B_ADC0_PTCXY5           _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
-#define MUX_PA07B_ADC0_PTCXY5           _L_(1)
-#define PINMUX_PA07B_ADC0_PTCXY5   ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
-#define PORT_PA07B_ADC0_PTCXY5  (_UL_(1) <<  7)
-#define PIN_PA08B_ADC0_PTCXY6           _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
-#define MUX_PA08B_ADC0_PTCXY6           _L_(1)
-#define PINMUX_PA08B_ADC0_PTCXY6   ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
-#define PORT_PA08B_ADC0_PTCXY6  (_UL_(1) <<  8)
-#define PIN_PA09B_ADC0_PTCXY7           _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
-#define MUX_PA09B_ADC0_PTCXY7           _L_(1)
-#define PINMUX_PA09B_ADC0_PTCXY7   ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
-#define PORT_PA09B_ADC0_PTCXY7  (_UL_(1) <<  9)
-#define PIN_PA10B_ADC0_PTCXY8          _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
-#define MUX_PA10B_ADC0_PTCXY8           _L_(1)
-#define PINMUX_PA10B_ADC0_PTCXY8   ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
-#define PORT_PA10B_ADC0_PTCXY8  (_UL_(1) << 10)
-#define PIN_PA11B_ADC0_PTCXY9          _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
-#define MUX_PA11B_ADC0_PTCXY9           _L_(1)
-#define PINMUX_PA11B_ADC0_PTCXY9   ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
-#define PORT_PA11B_ADC0_PTCXY9  (_UL_(1) << 11)
-#define PIN_PA16B_ADC0_PTCXY10         _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
-#define MUX_PA16B_ADC0_PTCXY10          _L_(1)
-#define PINMUX_PA16B_ADC0_PTCXY10  ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
-#define PORT_PA16B_ADC0_PTCXY10  (_UL_(1) << 16)
-#define PIN_PA17B_ADC0_PTCXY11         _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
-#define MUX_PA17B_ADC0_PTCXY11          _L_(1)
-#define PINMUX_PA17B_ADC0_PTCXY11  ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
-#define PORT_PA17B_ADC0_PTCXY11  (_UL_(1) << 17)
-#define PIN_PA19B_ADC0_PTCXY13         _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
-#define MUX_PA19B_ADC0_PTCXY13          _L_(1)
-#define PINMUX_PA19B_ADC0_PTCXY13  ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
-#define PORT_PA19B_ADC0_PTCXY13  (_UL_(1) << 19)
-#define PIN_PA20B_ADC0_PTCXY14         _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
-#define MUX_PA20B_ADC0_PTCXY14          _L_(1)
-#define PINMUX_PA20B_ADC0_PTCXY14  ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
-#define PORT_PA20B_ADC0_PTCXY14  (_UL_(1) << 20)
-#define PIN_PA21B_ADC0_PTCXY15         _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
-#define MUX_PA21B_ADC0_PTCXY15          _L_(1)
-#define PINMUX_PA21B_ADC0_PTCXY15  ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
-#define PORT_PA21B_ADC0_PTCXY15  (_UL_(1) << 21)
-#define PIN_PA22B_ADC0_PTCXY16         _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
-#define MUX_PA22B_ADC0_PTCXY16          _L_(1)
-#define PINMUX_PA22B_ADC0_PTCXY16  ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
-#define PORT_PA22B_ADC0_PTCXY16  (_UL_(1) << 22)
-#define PIN_PA23B_ADC0_PTCXY17         _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
-#define MUX_PA23B_ADC0_PTCXY17          _L_(1)
-#define PINMUX_PA23B_ADC0_PTCXY17  ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
-#define PORT_PA23B_ADC0_PTCXY17  (_UL_(1) << 23)
-#define PIN_PA27B_ADC0_PTCXY18         _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
-#define MUX_PA27B_ADC0_PTCXY18          _L_(1)
-#define PINMUX_PA27B_ADC0_PTCXY18  ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
-#define PORT_PA27B_ADC0_PTCXY18  (_UL_(1) << 27)
-#define PIN_PA30B_ADC0_PTCXY19         _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
-#define MUX_PA30B_ADC0_PTCXY19          _L_(1)
-#define PINMUX_PA30B_ADC0_PTCXY19  ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
-#define PORT_PA30B_ADC0_PTCXY19  (_UL_(1) << 30)
-#define PIN_PB02B_ADC0_PTCXY20         _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
-#define MUX_PB02B_ADC0_PTCXY20          _L_(1)
-#define PINMUX_PB02B_ADC0_PTCXY20  ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
-#define PORT_PB02B_ADC0_PTCXY20  (_UL_(1) <<  2)
-#define PIN_PB03B_ADC0_PTCXY21         _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
-#define MUX_PB03B_ADC0_PTCXY21          _L_(1)
-#define PINMUX_PB03B_ADC0_PTCXY21  ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
-#define PORT_PB03B_ADC0_PTCXY21  (_UL_(1) <<  3)
-#define PIN_PB04B_ADC0_PTCXY22         _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
-#define MUX_PB04B_ADC0_PTCXY22          _L_(1)
-#define PINMUX_PB04B_ADC0_PTCXY22  ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
-#define PORT_PB04B_ADC0_PTCXY22  (_UL_(1) <<  4)
-#define PIN_PB05B_ADC0_PTCXY23         _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
-#define MUX_PB05B_ADC0_PTCXY23          _L_(1)
-#define PINMUX_PB05B_ADC0_PTCXY23  ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
-#define PORT_PB05B_ADC0_PTCXY23  (_UL_(1) <<  5)
-#define PIN_PB06B_ADC0_PTCXY24         _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
-#define MUX_PB06B_ADC0_PTCXY24          _L_(1)
-#define PINMUX_PB06B_ADC0_PTCXY24  ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
-#define PORT_PB06B_ADC0_PTCXY24  (_UL_(1) <<  6)
-#define PIN_PB07B_ADC0_PTCXY25         _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
-#define MUX_PB07B_ADC0_PTCXY25          _L_(1)
-#define PINMUX_PB07B_ADC0_PTCXY25  ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
-#define PORT_PB07B_ADC0_PTCXY25  (_UL_(1) <<  7)
-#define PIN_PB12B_ADC0_PTCXY26         _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
-#define MUX_PB12B_ADC0_PTCXY26          _L_(1)
-#define PINMUX_PB12B_ADC0_PTCXY26  ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
-#define PORT_PB12B_ADC0_PTCXY26  (_UL_(1) << 12)
-#define PIN_PB13B_ADC0_PTCXY27         _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
-#define MUX_PB13B_ADC0_PTCXY27          _L_(1)
-#define PINMUX_PB13B_ADC0_PTCXY27  ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
-#define PORT_PB13B_ADC0_PTCXY27  (_UL_(1) << 13)
-#define PIN_PB14B_ADC0_PTCXY28         _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
-#define MUX_PB14B_ADC0_PTCXY28          _L_(1)
-#define PINMUX_PB14B_ADC0_PTCXY28  ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
-#define PORT_PB14B_ADC0_PTCXY28  (_UL_(1) << 14)
-#define PIN_PB15B_ADC0_PTCXY29         _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
-#define MUX_PB15B_ADC0_PTCXY29          _L_(1)
-#define PINMUX_PB15B_ADC0_PTCXY29  ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
-#define PORT_PB15B_ADC0_PTCXY29  (_UL_(1) << 15)
-#define PIN_PB00B_ADC0_PTCXY30         _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
-#define MUX_PB00B_ADC0_PTCXY30          _L_(1)
-#define PINMUX_PB00B_ADC0_PTCXY30  ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
-#define PORT_PB00B_ADC0_PTCXY30  (_UL_(1) <<  0)
-#define PIN_PB01B_ADC0_PTCXY31         _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
-#define MUX_PB01B_ADC0_PTCXY31          _L_(1)
-#define PINMUX_PB01B_ADC0_PTCXY31  ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
-#define PORT_PB01B_ADC0_PTCXY31  (_UL_(1) <<  1)
-/* ========== PORT definition for ADC1 peripheral ========== */
-#define PIN_PB08B_ADC1_AIN0            _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
-#define MUX_PB08B_ADC1_AIN0             _L_(1)
-#define PINMUX_PB08B_ADC1_AIN0     ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
-#define PORT_PB08B_ADC1_AIN0   (_UL_(1) <<  8)
-#define PIN_PB09B_ADC1_AIN1            _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
-#define MUX_PB09B_ADC1_AIN1             _L_(1)
-#define PINMUX_PB09B_ADC1_AIN1     ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
-#define PORT_PB09B_ADC1_AIN1   (_UL_(1) <<  9)
-#define PIN_PA08B_ADC1_AIN2             _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
-#define MUX_PA08B_ADC1_AIN2             _L_(1)
-#define PINMUX_PA08B_ADC1_AIN2     ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
-#define PORT_PA08B_ADC1_AIN2   (_UL_(1) <<  8)
-#define PIN_PA09B_ADC1_AIN3             _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
-#define MUX_PA09B_ADC1_AIN3             _L_(1)
-#define PINMUX_PA09B_ADC1_AIN3     ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
-#define PORT_PA09B_ADC1_AIN3   (_UL_(1) <<  9)
-#define PIN_PB04B_ADC1_AIN6            _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
-#define MUX_PB04B_ADC1_AIN6             _L_(1)
-#define PINMUX_PB04B_ADC1_AIN6     ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
-#define PORT_PB04B_ADC1_AIN6   (_UL_(1) <<  4)
-#define PIN_PB05B_ADC1_AIN7            _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
-#define MUX_PB05B_ADC1_AIN7             _L_(1)
-#define PINMUX_PB05B_ADC1_AIN7     ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
-#define PORT_PB05B_ADC1_AIN7   (_UL_(1) <<  5)
-#define PIN_PB06B_ADC1_AIN8            _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
-#define MUX_PB06B_ADC1_AIN8             _L_(1)
-#define PINMUX_PB06B_ADC1_AIN8     ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
-#define PORT_PB06B_ADC1_AIN8   (_UL_(1) <<  6)
-#define PIN_PB07B_ADC1_AIN9            _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
-#define MUX_PB07B_ADC1_AIN9             _L_(1)
-#define PINMUX_PB07B_ADC1_AIN9     ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
-#define PORT_PB07B_ADC1_AIN9   (_UL_(1) <<  7)
-/* ========== PORT definition for DAC peripheral ========== */
-#define PIN_PA02B_DAC_VOUT0             _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
-#define MUX_PA02B_DAC_VOUT0             _L_(1)
-#define PINMUX_PA02B_DAC_VOUT0     ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
-#define PORT_PA02B_DAC_VOUT0   (_UL_(1) <<  2)
-#define PIN_PA05B_DAC_VOUT1             _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
-#define MUX_PA05B_DAC_VOUT1             _L_(1)
-#define PINMUX_PA05B_DAC_VOUT1     ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
-#define PORT_PA05B_DAC_VOUT1   (_UL_(1) <<  5)
-/* ========== PORT definition for I2S peripheral ========== */
-#define PIN_PA09J_I2S_FS0               _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
-#define MUX_PA09J_I2S_FS0               _L_(9)
-#define PINMUX_PA09J_I2S_FS0       ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
-#define PORT_PA09J_I2S_FS0     (_UL_(1) <<  9)
-#define PIN_PA20J_I2S_FS0              _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
-#define MUX_PA20J_I2S_FS0               _L_(9)
-#define PINMUX_PA20J_I2S_FS0       ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
-#define PORT_PA20J_I2S_FS0     (_UL_(1) << 20)
-#define PIN_PA23J_I2S_FS1              _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
-#define MUX_PA23J_I2S_FS1               _L_(9)
-#define PINMUX_PA23J_I2S_FS1       ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
-#define PORT_PA23J_I2S_FS1     (_UL_(1) << 23)
-#define PIN_PB11J_I2S_FS1              _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
-#define MUX_PB11J_I2S_FS1               _L_(9)
-#define PINMUX_PB11J_I2S_FS1       ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
-#define PORT_PB11J_I2S_FS1     (_UL_(1) << 11)
-#define PIN_PA08J_I2S_MCK0              _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
-#define MUX_PA08J_I2S_MCK0              _L_(9)
-#define PINMUX_PA08J_I2S_MCK0      ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
-#define PORT_PA08J_I2S_MCK0    (_UL_(1) <<  8)
-#define PIN_PB17J_I2S_MCK0             _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
-#define MUX_PB17J_I2S_MCK0              _L_(9)
-#define PINMUX_PB17J_I2S_MCK0      ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
-#define PORT_PB17J_I2S_MCK0    (_UL_(1) << 17)
-#define PIN_PB13J_I2S_MCK1             _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
-#define MUX_PB13J_I2S_MCK1              _L_(9)
-#define PINMUX_PB13J_I2S_MCK1      ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
-#define PORT_PB13J_I2S_MCK1    (_UL_(1) << 13)
-#define PIN_PA10J_I2S_SCK0             _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
-#define MUX_PA10J_I2S_SCK0              _L_(9)
-#define PINMUX_PA10J_I2S_SCK0      ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
-#define PORT_PA10J_I2S_SCK0    (_UL_(1) << 10)
-#define PIN_PB16J_I2S_SCK0             _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
-#define MUX_PB16J_I2S_SCK0              _L_(9)
-#define PINMUX_PB16J_I2S_SCK0      ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
-#define PORT_PB16J_I2S_SCK0    (_UL_(1) << 16)
-#define PIN_PB12J_I2S_SCK1             _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
-#define MUX_PB12J_I2S_SCK1              _L_(9)
-#define PINMUX_PB12J_I2S_SCK1      ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
-#define PORT_PB12J_I2S_SCK1    (_UL_(1) << 12)
-#define PIN_PA22J_I2S_SDI              _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
-#define MUX_PA22J_I2S_SDI               _L_(9)
-#define PINMUX_PA22J_I2S_SDI       ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
-#define PORT_PA22J_I2S_SDI     (_UL_(1) << 22)
-#define PIN_PB10J_I2S_SDI              _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
-#define MUX_PB10J_I2S_SDI               _L_(9)
-#define PINMUX_PB10J_I2S_SDI       ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
-#define PORT_PB10J_I2S_SDI     (_UL_(1) << 10)
-#define PIN_PA11J_I2S_SDO              _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
-#define MUX_PA11J_I2S_SDO               _L_(9)
-#define PINMUX_PA11J_I2S_SDO       ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
-#define PORT_PA11J_I2S_SDO     (_UL_(1) << 11)
-#define PIN_PA21J_I2S_SDO              _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
-#define MUX_PA21J_I2S_SDO               _L_(9)
-#define PINMUX_PA21J_I2S_SDO       ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
-#define PORT_PA21J_I2S_SDO     (_UL_(1) << 21)
-/* ========== PORT definition for PCC peripheral ========== */
-#define PIN_PA14K_PCC_CLK              _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
-#define MUX_PA14K_PCC_CLK              _L_(10)
-#define PINMUX_PA14K_PCC_CLK       ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
-#define PORT_PA14K_PCC_CLK     (_UL_(1) << 14)
-#define PIN_PA16K_PCC_DATA0            _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
-#define MUX_PA16K_PCC_DATA0            _L_(10)
-#define PINMUX_PA16K_PCC_DATA0     ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
-#define PORT_PA16K_PCC_DATA0   (_UL_(1) << 16)
-#define PIN_PA17K_PCC_DATA1            _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
-#define MUX_PA17K_PCC_DATA1            _L_(10)
-#define PINMUX_PA17K_PCC_DATA1     ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
-#define PORT_PA17K_PCC_DATA1   (_UL_(1) << 17)
-#define PIN_PA18K_PCC_DATA2            _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
-#define MUX_PA18K_PCC_DATA2            _L_(10)
-#define PINMUX_PA18K_PCC_DATA2     ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
-#define PORT_PA18K_PCC_DATA2   (_UL_(1) << 18)
-#define PIN_PA19K_PCC_DATA3            _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
-#define MUX_PA19K_PCC_DATA3            _L_(10)
-#define PINMUX_PA19K_PCC_DATA3     ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
-#define PORT_PA19K_PCC_DATA3   (_UL_(1) << 19)
-#define PIN_PA20K_PCC_DATA4            _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
-#define MUX_PA20K_PCC_DATA4            _L_(10)
-#define PINMUX_PA20K_PCC_DATA4     ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
-#define PORT_PA20K_PCC_DATA4   (_UL_(1) << 20)
-#define PIN_PA21K_PCC_DATA5            _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
-#define MUX_PA21K_PCC_DATA5            _L_(10)
-#define PINMUX_PA21K_PCC_DATA5     ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
-#define PORT_PA21K_PCC_DATA5   (_UL_(1) << 21)
-#define PIN_PA22K_PCC_DATA6            _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
-#define MUX_PA22K_PCC_DATA6            _L_(10)
-#define PINMUX_PA22K_PCC_DATA6     ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
-#define PORT_PA22K_PCC_DATA6   (_UL_(1) << 22)
-#define PIN_PA23K_PCC_DATA7            _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
-#define MUX_PA23K_PCC_DATA7            _L_(10)
-#define PINMUX_PA23K_PCC_DATA7     ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
-#define PORT_PA23K_PCC_DATA7   (_UL_(1) << 23)
-#define PIN_PB14K_PCC_DATA8            _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
-#define MUX_PB14K_PCC_DATA8            _L_(10)
-#define PINMUX_PB14K_PCC_DATA8     ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
-#define PORT_PB14K_PCC_DATA8   (_UL_(1) << 14)
-#define PIN_PB15K_PCC_DATA9            _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
-#define MUX_PB15K_PCC_DATA9            _L_(10)
-#define PINMUX_PB15K_PCC_DATA9     ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
-#define PORT_PB15K_PCC_DATA9   (_UL_(1) << 15)
-#define PIN_PA12K_PCC_DEN1             _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
-#define MUX_PA12K_PCC_DEN1             _L_(10)
-#define PINMUX_PA12K_PCC_DEN1      ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
-#define PORT_PA12K_PCC_DEN1    (_UL_(1) << 12)
-#define PIN_PA13K_PCC_DEN2             _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
-#define MUX_PA13K_PCC_DEN2             _L_(10)
-#define PINMUX_PA13K_PCC_DEN2      ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
-#define PORT_PA13K_PCC_DEN2    (_UL_(1) << 13)
-/* ========== PORT definition for SDHC0 peripheral ========== */
-#define PIN_PA06I_SDHC0_SDCD            _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
-#define MUX_PA06I_SDHC0_SDCD            _L_(8)
-#define PINMUX_PA06I_SDHC0_SDCD    ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
-#define PORT_PA06I_SDHC0_SDCD  (_UL_(1) <<  6)
-#define PIN_PA12I_SDHC0_SDCD           _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
-#define MUX_PA12I_SDHC0_SDCD            _L_(8)
-#define PINMUX_PA12I_SDHC0_SDCD    ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
-#define PORT_PA12I_SDHC0_SDCD  (_UL_(1) << 12)
-#define PIN_PB12I_SDHC0_SDCD           _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
-#define MUX_PB12I_SDHC0_SDCD            _L_(8)
-#define PINMUX_PB12I_SDHC0_SDCD    ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
-#define PORT_PB12I_SDHC0_SDCD  (_UL_(1) << 12)
-#define PIN_PB11I_SDHC0_SDCK           _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
-#define MUX_PB11I_SDHC0_SDCK            _L_(8)
-#define PINMUX_PB11I_SDHC0_SDCK    ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
-#define PORT_PB11I_SDHC0_SDCK  (_UL_(1) << 11)
-#define PIN_PA08I_SDHC0_SDCMD           _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
-#define MUX_PA08I_SDHC0_SDCMD           _L_(8)
-#define PINMUX_PA08I_SDHC0_SDCMD   ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
-#define PORT_PA08I_SDHC0_SDCMD  (_UL_(1) <<  8)
-#define PIN_PA09I_SDHC0_SDDAT0          _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
-#define MUX_PA09I_SDHC0_SDDAT0          _L_(8)
-#define PINMUX_PA09I_SDHC0_SDDAT0  ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
-#define PORT_PA09I_SDHC0_SDDAT0  (_UL_(1) <<  9)
-#define PIN_PA10I_SDHC0_SDDAT1         _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
-#define MUX_PA10I_SDHC0_SDDAT1          _L_(8)
-#define PINMUX_PA10I_SDHC0_SDDAT1  ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
-#define PORT_PA10I_SDHC0_SDDAT1  (_UL_(1) << 10)
-#define PIN_PA11I_SDHC0_SDDAT2         _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
-#define MUX_PA11I_SDHC0_SDDAT2          _L_(8)
-#define PINMUX_PA11I_SDHC0_SDDAT2  ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
-#define PORT_PA11I_SDHC0_SDDAT2  (_UL_(1) << 11)
-#define PIN_PB10I_SDHC0_SDDAT3         _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
-#define MUX_PB10I_SDHC0_SDDAT3          _L_(8)
-#define PINMUX_PB10I_SDHC0_SDDAT3  ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
-#define PORT_PB10I_SDHC0_SDDAT3  (_UL_(1) << 10)
-#define PIN_PA07I_SDHC0_SDWP            _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
-#define MUX_PA07I_SDHC0_SDWP            _L_(8)
-#define PINMUX_PA07I_SDHC0_SDWP    ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
-#define PORT_PA07I_SDHC0_SDWP  (_UL_(1) <<  7)
-#define PIN_PA13I_SDHC0_SDWP           _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
-#define MUX_PA13I_SDHC0_SDWP            _L_(8)
-#define PINMUX_PA13I_SDHC0_SDWP    ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
-#define PORT_PA13I_SDHC0_SDWP  (_UL_(1) << 13)
-#define PIN_PB13I_SDHC0_SDWP           _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
-#define MUX_PB13I_SDHC0_SDWP            _L_(8)
-#define PINMUX_PB13I_SDHC0_SDWP    ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
-#define PORT_PB13I_SDHC0_SDWP  (_UL_(1) << 13)
-
-#endif /* _SAMD51J18A_PIO_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h
deleted file mode 100644
index 9009b6d653..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/sam.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**
- * \file
- *
- * \brief Top level header file
- *
- * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
- *
- * \license_start
- *
- * \page License
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \license_stop
- *
- */
-
-#ifndef _SAM_
-#define _SAM_
-
-#if   defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__)
-  #include "samd51g18a.h"
-#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__)
-  #include "samd51g19a.h"
-#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__)
-  #include "samd51j18a.h"
-#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__)
-  #include "samd51j19a.h"
-#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__)
-  #include "samd51j20a.h"
-#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__)
-  #include "samd51n19a.h"
-#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__)
-  #include "samd51n20a.h"
-#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__)
-  #include "samd51p19a.h"
-#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__)
-  #include "samd51p20a.h"
-#else
-  #error Library does not support the specified device
-#endif
-
-#endif /* _SAM_ */
-
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h
deleted file mode 100644
index d08ac64cb8..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/**
- * \file
- *
- * \brief Top header file for SAMD51
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51_
-#define _SAMD51_
-
-/**
- * \defgroup SAMD51_definitions SAMD51 Device Definitions
- * \brief SAMD51 CMSIS Definitions.
- */
-
-#if   defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__)
-  #include "samd51g18a.h"
-#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__)
-  #include "samd51g19a.h"
-#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__)
-  #include "samd51j18a.h"
-#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__)
-  #include "samd51j19a.h"
-#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__)
-  #include "samd51j20a.h"
-#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__)
-  #include "samd51n19a.h"
-#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__)
-  #include "samd51n20a.h"
-#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__)
-  #include "samd51p19a.h"
-#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__)
-  #include "samd51p20a.h"
-#else
-  #error Library does not support the specified device.
-#endif
-
-#endif /* _SAMD51_ */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h
deleted file mode 100644
index 5cfccdfc84..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/samd51j18a.h
+++ /dev/null
@@ -1,1079 +0,0 @@
-/**
- * \file
- *
- * \brief Header file for SAMD51J18A
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAMD51J18A_
-#define _SAMD51J18A_
-
-/**
- * \ingroup SAMD51_definitions
- * \addtogroup SAMD51J18A_definitions SAMD51J18A definitions
- * This file defines all structures and symbols for SAMD51J18A:
- *   - registers and bitfields
- *   - peripheral base address
- *   - peripheral ID
- *   - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#ifndef __cplusplus
-typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#else
-typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
-typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
-typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
-#endif
-typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
-typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
-typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
-typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
-#endif
-
-#if !defined(SKIP_INTEGER_LITERALS)
-#if defined(_U_) || defined(_L_) || defined(_UL_)
-  #error "Integer Literals macros already defined elsewhere"
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
-#define _U_(x)         x ## U            /**< C code: Unsigned integer literal constant value */
-#define _L_(x)         x ## L            /**< C code: Long integer literal constant value */
-#define _UL_(x)        x ## UL           /**< C code: Unsigned Long integer literal constant value */
-#else /* Assembler */
-#define _U_(x)         x                 /**< Assembler: Unsigned integer literal constant value */
-#define _L_(x)         x                 /**< Assembler: Long integer literal constant value */
-#define _UL_(x)        x                 /**< Assembler: Unsigned Long integer literal constant value */
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-#endif /* SKIP_INTEGER_LITERALS */
-
-/* ************************************************************************** */
-/**  CMSIS DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_cmsis CMSIS Definitions */
-/*@{*/
-
-/** Interrupt Number Definition */
-typedef enum IRQn
-{
-  /******  Cortex-M4 Processor Exceptions Numbers ******************************/
-  NonMaskableInt_IRQn      = -14,/**<  2 Non Maskable Interrupt                */
-  HardFault_IRQn           = -13,/**<  3 Cortex-M4 Hard Fault Interrupt        */
-  MemoryManagement_IRQn    = -12,/**<  4 Cortex-M4 Memory Management Interrupt */
-  BusFault_IRQn            = -11,/**<  5 Cortex-M4 Bus Fault Interrupt         */
-  UsageFault_IRQn          = -10,/**<  6 Cortex-M4 Usage Fault Interrupt       */
-  SVCall_IRQn              = -5, /**< 11 Cortex-M4 SV Call Interrupt           */
-  DebugMonitor_IRQn        = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt     */
-  PendSV_IRQn              = -2, /**< 14 Cortex-M4 Pend SV Interrupt           */
-  SysTick_IRQn             = -1, /**< 15 Cortex-M4 System Tick Interrupt       */
-  /******  SAMD51J18A-specific Interrupt Numbers ***********************/
-  PM_IRQn                  =  0, /**<  0 SAMD51J18A Power Manager (PM) */
-  MCLK_IRQn                =  1, /**<  1 SAMD51J18A Main Clock (MCLK) */
-  OSCCTRL_0_IRQn           =  2, /**<  2 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */
-  OSCCTRL_1_IRQn           =  3, /**<  3 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */
-  OSCCTRL_2_IRQn           =  4, /**<  4 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */
-  OSCCTRL_3_IRQn           =  5, /**<  5 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */
-  OSCCTRL_4_IRQn           =  6, /**<  6 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */
-  OSC32KCTRL_IRQn          =  7, /**<  7 SAMD51J18A 32kHz Oscillators Control (OSC32KCTRL) */
-  SUPC_0_IRQn              =  8, /**<  8 SAMD51J18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */
-  SUPC_1_IRQn              =  9, /**<  9 SAMD51J18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */
-  WDT_IRQn                 = 10, /**< 10 SAMD51J18A Watchdog Timer (WDT) */
-  RTC_IRQn                 = 11, /**< 11 SAMD51J18A Real-Time Counter (RTC) */
-  EIC_0_IRQn               = 12, /**< 12 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_0 */
-  EIC_1_IRQn               = 13, /**< 13 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_1 */
-  EIC_2_IRQn               = 14, /**< 14 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_2 */
-  EIC_3_IRQn               = 15, /**< 15 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_3 */
-  EIC_4_IRQn               = 16, /**< 16 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_4 */
-  EIC_5_IRQn               = 17, /**< 17 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_5 */
-  EIC_6_IRQn               = 18, /**< 18 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_6 */
-  EIC_7_IRQn               = 19, /**< 19 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_7 */
-  EIC_8_IRQn               = 20, /**< 20 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_8 */
-  EIC_9_IRQn               = 21, /**< 21 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_9 */
-  EIC_10_IRQn              = 22, /**< 22 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_10 */
-  EIC_11_IRQn              = 23, /**< 23 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_11 */
-  EIC_12_IRQn              = 24, /**< 24 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_12 */
-  EIC_13_IRQn              = 25, /**< 25 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_13 */
-  EIC_14_IRQn              = 26, /**< 26 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_14 */
-  EIC_15_IRQn              = 27, /**< 27 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_15 */
-  FREQM_IRQn               = 28, /**< 28 SAMD51J18A Frequency Meter (FREQM) */
-  NVMCTRL_0_IRQn           = 29, /**< 29 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */
-  NVMCTRL_1_IRQn           = 30, /**< 30 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */
-  DMAC_0_IRQn              = 31, /**< 31 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */
-  DMAC_1_IRQn              = 32, /**< 32 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */
-  DMAC_2_IRQn              = 33, /**< 33 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */
-  DMAC_3_IRQn              = 34, /**< 34 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */
-  DMAC_4_IRQn              = 35, /**< 35 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */
-  EVSYS_0_IRQn             = 36, /**< 36 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */
-  EVSYS_1_IRQn             = 37, /**< 37 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */
-  EVSYS_2_IRQn             = 38, /**< 38 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */
-  EVSYS_3_IRQn             = 39, /**< 39 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */
-  EVSYS_4_IRQn             = 40, /**< 40 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */
-  PAC_IRQn                 = 41, /**< 41 SAMD51J18A Peripheral Access Controller (PAC) */
-  TAL_0_IRQn               = 42, /**< 42 SAMD51J18A Trigger Allocator (TAL): TAL_BRK */
-  TAL_1_IRQn               = 43, /**< 43 SAMD51J18A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */
-  RAMECC_IRQn              = 45, /**< 45 SAMD51J18A RAM ECC (RAMECC) */
-  SERCOM0_0_IRQn           = 46, /**< 46 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */
-  SERCOM0_1_IRQn           = 47, /**< 47 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */
-  SERCOM0_2_IRQn           = 48, /**< 48 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */
-  SERCOM0_3_IRQn           = 49, /**< 49 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */
-  SERCOM1_0_IRQn           = 50, /**< 50 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */
-  SERCOM1_1_IRQn           = 51, /**< 51 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */
-  SERCOM1_2_IRQn           = 52, /**< 52 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */
-  SERCOM1_3_IRQn           = 53, /**< 53 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */
-  SERCOM2_0_IRQn           = 54, /**< 54 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */
-  SERCOM2_1_IRQn           = 55, /**< 55 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */
-  SERCOM2_2_IRQn           = 56, /**< 56 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */
-  SERCOM2_3_IRQn           = 57, /**< 57 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */
-  SERCOM3_0_IRQn           = 58, /**< 58 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */
-  SERCOM3_1_IRQn           = 59, /**< 59 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */
-  SERCOM3_2_IRQn           = 60, /**< 60 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */
-  SERCOM3_3_IRQn           = 61, /**< 61 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */
-  SERCOM4_0_IRQn           = 62, /**< 62 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */
-  SERCOM4_1_IRQn           = 63, /**< 63 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */
-  SERCOM4_2_IRQn           = 64, /**< 64 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */
-  SERCOM4_3_IRQn           = 65, /**< 65 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */
-  SERCOM5_0_IRQn           = 66, /**< 66 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */
-  SERCOM5_1_IRQn           = 67, /**< 67 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */
-  SERCOM5_2_IRQn           = 68, /**< 68 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */
-  SERCOM5_3_IRQn           = 69, /**< 69 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */
-  USB_0_IRQn               = 80, /**< 80 SAMD51J18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */
-  USB_1_IRQn               = 81, /**< 81 SAMD51J18A Universal Serial Bus (USB): USB_SOF_HSOF */
-  USB_2_IRQn               = 82, /**< 82 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */
-  USB_3_IRQn               = 83, /**< 83 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */
-  TCC0_0_IRQn              = 85, /**< 85 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */
-  TCC0_1_IRQn              = 86, /**< 86 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */
-  TCC0_2_IRQn              = 87, /**< 87 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */
-  TCC0_3_IRQn              = 88, /**< 88 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */
-  TCC0_4_IRQn              = 89, /**< 89 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */
-  TCC0_5_IRQn              = 90, /**< 90 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */
-  TCC0_6_IRQn              = 91, /**< 91 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */
-  TCC1_0_IRQn              = 92, /**< 92 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */
-  TCC1_1_IRQn              = 93, /**< 93 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */
-  TCC1_2_IRQn              = 94, /**< 94 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */
-  TCC1_3_IRQn              = 95, /**< 95 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */
-  TCC1_4_IRQn              = 96, /**< 96 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */
-  TCC2_0_IRQn              = 97, /**< 97 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */
-  TCC2_1_IRQn              = 98, /**< 98 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */
-  TCC2_2_IRQn              = 99, /**< 99 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */
-  TCC2_3_IRQn              = 100, /**< 100 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */
-  TCC3_0_IRQn              = 101, /**< 101 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */
-  TCC3_1_IRQn              = 102, /**< 102 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_0 */
-  TCC3_2_IRQn              = 103, /**< 103 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_1 */
-  TCC4_0_IRQn              = 104, /**< 104 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */
-  TCC4_1_IRQn              = 105, /**< 105 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_0 */
-  TCC4_2_IRQn              = 106, /**< 106 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_1 */
-  TC0_IRQn                 = 107, /**< 107 SAMD51J18A Basic Timer Counter 0 (TC0) */
-  TC1_IRQn                 = 108, /**< 108 SAMD51J18A Basic Timer Counter 1 (TC1) */
-  TC2_IRQn                 = 109, /**< 109 SAMD51J18A Basic Timer Counter 2 (TC2) */
-  TC3_IRQn                 = 110, /**< 110 SAMD51J18A Basic Timer Counter 3 (TC3) */
-  TC4_IRQn                 = 111, /**< 111 SAMD51J18A Basic Timer Counter 4 (TC4) */
-  TC5_IRQn                 = 112, /**< 112 SAMD51J18A Basic Timer Counter 5 (TC5) */
-  PDEC_0_IRQn              = 115, /**< 115 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */
-  PDEC_1_IRQn              = 116, /**< 116 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_0 */
-  PDEC_2_IRQn              = 117, /**< 117 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_1 */
-  ADC0_0_IRQn              = 118, /**< 118 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */
-  ADC0_1_IRQn              = 119, /**< 119 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */
-  ADC1_0_IRQn              = 120, /**< 120 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */
-  ADC1_1_IRQn              = 121, /**< 121 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */
-  AC_IRQn                  = 122, /**< 122 SAMD51J18A Analog Comparators (AC) */
-  DAC_0_IRQn               = 123, /**< 123 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */
-  DAC_1_IRQn               = 124, /**< 124 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */
-  DAC_2_IRQn               = 125, /**< 125 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */
-  DAC_3_IRQn               = 126, /**< 126 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */
-  DAC_4_IRQn               = 127, /**< 127 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */
-  I2S_IRQn                 = 128, /**< 128 SAMD51J18A Inter-IC Sound Interface (I2S) */
-  PCC_IRQn                 = 129, /**< 129 SAMD51J18A Parallel Capture Controller (PCC) */
-  AES_IRQn                 = 130, /**< 130 SAMD51J18A Advanced Encryption Standard (AES) */
-  TRNG_IRQn                = 131, /**< 131 SAMD51J18A True Random Generator (TRNG) */
-  ICM_IRQn                 = 132, /**< 132 SAMD51J18A Integrity Check Monitor (ICM) */
-  PUKCC_IRQn               = 133, /**< 133 SAMD51J18A PUblic-Key Cryptography Controller (PUKCC) */
-  QSPI_IRQn                = 134, /**< 134 SAMD51J18A Quad SPI interface (QSPI) */
-  SDHC0_IRQn               = 135, /**< 135 SAMD51J18A SD/MMC Host Controller 0 (SDHC0) */
-
-  PERIPH_COUNT_IRQn        = 137  /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
-  /* Stack pointer */
-  void* pvStack;
-
-  /* Cortex-M handlers */
-  void* pfnReset_Handler;
-  void* pfnNMI_Handler;
-  void* pfnHardFault_Handler;
-  void* pfnMemManage_Handler;
-  void* pfnBusFault_Handler;
-  void* pfnUsageFault_Handler;
-  void* pvReservedM9;
-  void* pvReservedM8;
-  void* pvReservedM7;
-  void* pvReservedM6;
-  void* pfnSVC_Handler;
-  void* pfnDebugMon_Handler;
-  void* pvReservedM3;
-  void* pfnPendSV_Handler;
-  void* pfnSysTick_Handler;
-
-  /* Peripheral handlers */
-  void* pfnPM_Handler;                    /*  0 Power Manager */
-  void* pfnMCLK_Handler;                  /*  1 Main Clock */
-  void* pfnOSCCTRL_0_Handler;             /*  2 Oscillators Control IRQ 0 */
-  void* pfnOSCCTRL_1_Handler;             /*  3 Oscillators Control IRQ 1 */
-  void* pfnOSCCTRL_2_Handler;             /*  4 Oscillators Control IRQ 2 */
-  void* pfnOSCCTRL_3_Handler;             /*  5 Oscillators Control IRQ 3 */
-  void* pfnOSCCTRL_4_Handler;             /*  6 Oscillators Control IRQ 4 */
-  void* pfnOSC32KCTRL_Handler;            /*  7 32kHz Oscillators Control */
-  void* pfnSUPC_0_Handler;                /*  8 Supply Controller IRQ 0 */
-  void* pfnSUPC_1_Handler;                /*  9 Supply Controller IRQ 1 */
-  void* pfnWDT_Handler;                   /* 10 Watchdog Timer */
-  void* pfnRTC_Handler;                   /* 11 Real-Time Counter */
-  void* pfnEIC_0_Handler;                 /* 12 External Interrupt Controller IRQ 0 */
-  void* pfnEIC_1_Handler;                 /* 13 External Interrupt Controller IRQ 1 */
-  void* pfnEIC_2_Handler;                 /* 14 External Interrupt Controller IRQ 2 */
-  void* pfnEIC_3_Handler;                 /* 15 External Interrupt Controller IRQ 3 */
-  void* pfnEIC_4_Handler;                 /* 16 External Interrupt Controller IRQ 4 */
-  void* pfnEIC_5_Handler;                 /* 17 External Interrupt Controller IRQ 5 */
-  void* pfnEIC_6_Handler;                 /* 18 External Interrupt Controller IRQ 6 */
-  void* pfnEIC_7_Handler;                 /* 19 External Interrupt Controller IRQ 7 */
-  void* pfnEIC_8_Handler;                 /* 20 External Interrupt Controller IRQ 8 */
-  void* pfnEIC_9_Handler;                 /* 21 External Interrupt Controller IRQ 9 */
-  void* pfnEIC_10_Handler;                /* 22 External Interrupt Controller IRQ 10 */
-  void* pfnEIC_11_Handler;                /* 23 External Interrupt Controller IRQ 11 */
-  void* pfnEIC_12_Handler;                /* 24 External Interrupt Controller IRQ 12 */
-  void* pfnEIC_13_Handler;                /* 25 External Interrupt Controller IRQ 13 */
-  void* pfnEIC_14_Handler;                /* 26 External Interrupt Controller IRQ 14 */
-  void* pfnEIC_15_Handler;                /* 27 External Interrupt Controller IRQ 15 */
-  void* pfnFREQM_Handler;                 /* 28 Frequency Meter */
-  void* pfnNVMCTRL_0_Handler;             /* 29 Non-Volatile Memory Controller IRQ 0 */
-  void* pfnNVMCTRL_1_Handler;             /* 30 Non-Volatile Memory Controller IRQ 1 */
-  void* pfnDMAC_0_Handler;                /* 31 Direct Memory Access Controller IRQ 0 */
-  void* pfnDMAC_1_Handler;                /* 32 Direct Memory Access Controller IRQ 1 */
-  void* pfnDMAC_2_Handler;                /* 33 Direct Memory Access Controller IRQ 2 */
-  void* pfnDMAC_3_Handler;                /* 34 Direct Memory Access Controller IRQ 3 */
-  void* pfnDMAC_4_Handler;                /* 35 Direct Memory Access Controller IRQ 4 */
-  void* pfnEVSYS_0_Handler;               /* 36 Event System Interface IRQ 0 */
-  void* pfnEVSYS_1_Handler;               /* 37 Event System Interface IRQ 1 */
-  void* pfnEVSYS_2_Handler;               /* 38 Event System Interface IRQ 2 */
-  void* pfnEVSYS_3_Handler;               /* 39 Event System Interface IRQ 3 */
-  void* pfnEVSYS_4_Handler;               /* 40 Event System Interface IRQ 4 */
-  void* pfnPAC_Handler;                   /* 41 Peripheral Access Controller */
-  void* pfnTAL_0_Handler;                 /* 42 Trigger Allocator IRQ 0 */
-  void* pfnTAL_1_Handler;                 /* 43 Trigger Allocator IRQ 1 */
-  void* pvReserved44;
-  void* pfnRAMECC_Handler;                /* 45 RAM ECC */
-  void* pfnSERCOM0_0_Handler;             /* 46 Serial Communication Interface 0 IRQ 0 */
-  void* pfnSERCOM0_1_Handler;             /* 47 Serial Communication Interface 0 IRQ 1 */
-  void* pfnSERCOM0_2_Handler;             /* 48 Serial Communication Interface 0 IRQ 2 */
-  void* pfnSERCOM0_3_Handler;             /* 49 Serial Communication Interface 0 IRQ 3 */
-  void* pfnSERCOM1_0_Handler;             /* 50 Serial Communication Interface 1 IRQ 0 */
-  void* pfnSERCOM1_1_Handler;             /* 51 Serial Communication Interface 1 IRQ 1 */
-  void* pfnSERCOM1_2_Handler;             /* 52 Serial Communication Interface 1 IRQ 2 */
-  void* pfnSERCOM1_3_Handler;             /* 53 Serial Communication Interface 1 IRQ 3 */
-  void* pfnSERCOM2_0_Handler;             /* 54 Serial Communication Interface 2 IRQ 0 */
-  void* pfnSERCOM2_1_Handler;             /* 55 Serial Communication Interface 2 IRQ 1 */
-  void* pfnSERCOM2_2_Handler;             /* 56 Serial Communication Interface 2 IRQ 2 */
-  void* pfnSERCOM2_3_Handler;             /* 57 Serial Communication Interface 2 IRQ 3 */
-  void* pfnSERCOM3_0_Handler;             /* 58 Serial Communication Interface 3 IRQ 0 */
-  void* pfnSERCOM3_1_Handler;             /* 59 Serial Communication Interface 3 IRQ 1 */
-  void* pfnSERCOM3_2_Handler;             /* 60 Serial Communication Interface 3 IRQ 2 */
-  void* pfnSERCOM3_3_Handler;             /* 61 Serial Communication Interface 3 IRQ 3 */
-  void* pfnSERCOM4_0_Handler;             /* 62 Serial Communication Interface 4 IRQ 0 */
-  void* pfnSERCOM4_1_Handler;             /* 63 Serial Communication Interface 4 IRQ 1 */
-  void* pfnSERCOM4_2_Handler;             /* 64 Serial Communication Interface 4 IRQ 2 */
-  void* pfnSERCOM4_3_Handler;             /* 65 Serial Communication Interface 4 IRQ 3 */
-  void* pfnSERCOM5_0_Handler;             /* 66 Serial Communication Interface 5 IRQ 0 */
-  void* pfnSERCOM5_1_Handler;             /* 67 Serial Communication Interface 5 IRQ 1 */
-  void* pfnSERCOM5_2_Handler;             /* 68 Serial Communication Interface 5 IRQ 2 */
-  void* pfnSERCOM5_3_Handler;             /* 69 Serial Communication Interface 5 IRQ 3 */
-  void* pvReserved70;
-  void* pvReserved71;
-  void* pvReserved72;
-  void* pvReserved73;
-  void* pvReserved74;
-  void* pvReserved75;
-  void* pvReserved76;
-  void* pvReserved77;
-  void* pvReserved78;
-  void* pvReserved79;
-  void* pfnUSB_0_Handler;                 /* 80 Universal Serial Bus IRQ 0 */
-  void* pfnUSB_1_Handler;                 /* 81 Universal Serial Bus IRQ 1 */
-  void* pfnUSB_2_Handler;                 /* 82 Universal Serial Bus IRQ 2 */
-  void* pfnUSB_3_Handler;                 /* 83 Universal Serial Bus IRQ 3 */
-  void* pvReserved84;
-  void* pfnTCC0_0_Handler;                /* 85 Timer Counter Control 0 IRQ 0 */
-  void* pfnTCC0_1_Handler;                /* 86 Timer Counter Control 0 IRQ 1 */
-  void* pfnTCC0_2_Handler;                /* 87 Timer Counter Control 0 IRQ 2 */
-  void* pfnTCC0_3_Handler;                /* 88 Timer Counter Control 0 IRQ 3 */
-  void* pfnTCC0_4_Handler;                /* 89 Timer Counter Control 0 IRQ 4 */
-  void* pfnTCC0_5_Handler;                /* 90 Timer Counter Control 0 IRQ 5 */
-  void* pfnTCC0_6_Handler;                /* 91 Timer Counter Control 0 IRQ 6 */
-  void* pfnTCC1_0_Handler;                /* 92 Timer Counter Control 1 IRQ 0 */
-  void* pfnTCC1_1_Handler;                /* 93 Timer Counter Control 1 IRQ 1 */
-  void* pfnTCC1_2_Handler;                /* 94 Timer Counter Control 1 IRQ 2 */
-  void* pfnTCC1_3_Handler;                /* 95 Timer Counter Control 1 IRQ 3 */
-  void* pfnTCC1_4_Handler;                /* 96 Timer Counter Control 1 IRQ 4 */
-  void* pfnTCC2_0_Handler;                /* 97 Timer Counter Control 2 IRQ 0 */
-  void* pfnTCC2_1_Handler;                /* 98 Timer Counter Control 2 IRQ 1 */
-  void* pfnTCC2_2_Handler;                /* 99 Timer Counter Control 2 IRQ 2 */
-  void* pfnTCC2_3_Handler;                /* 100 Timer Counter Control 2 IRQ 3 */
-  void* pfnTCC3_0_Handler;                /* 101 Timer Counter Control 3 IRQ 0 */
-  void* pfnTCC3_1_Handler;                /* 102 Timer Counter Control 3 IRQ 1 */
-  void* pfnTCC3_2_Handler;                /* 103 Timer Counter Control 3 IRQ 2 */
-  void* pfnTCC4_0_Handler;                /* 104 Timer Counter Control 4 IRQ 0 */
-  void* pfnTCC4_1_Handler;                /* 105 Timer Counter Control 4 IRQ 1 */
-  void* pfnTCC4_2_Handler;                /* 106 Timer Counter Control 4 IRQ 2 */
-  void* pfnTC0_Handler;                   /* 107 Basic Timer Counter 0 */
-  void* pfnTC1_Handler;                   /* 108 Basic Timer Counter 1 */
-  void* pfnTC2_Handler;                   /* 109 Basic Timer Counter 2 */
-  void* pfnTC3_Handler;                   /* 110 Basic Timer Counter 3 */
-  void* pfnTC4_Handler;                   /* 111 Basic Timer Counter 4 */
-  void* pfnTC5_Handler;                   /* 112 Basic Timer Counter 5 */
-  void* pvReserved113;
-  void* pvReserved114;
-  void* pfnPDEC_0_Handler;                /* 115 Quadrature Decodeur IRQ 0 */
-  void* pfnPDEC_1_Handler;                /* 116 Quadrature Decodeur IRQ 1 */
-  void* pfnPDEC_2_Handler;                /* 117 Quadrature Decodeur IRQ 2 */
-  void* pfnADC0_0_Handler;                /* 118 Analog Digital Converter 0 IRQ 0 */
-  void* pfnADC0_1_Handler;                /* 119 Analog Digital Converter 0 IRQ 1 */
-  void* pfnADC1_0_Handler;                /* 120 Analog Digital Converter 1 IRQ 0 */
-  void* pfnADC1_1_Handler;                /* 121 Analog Digital Converter 1 IRQ 1 */
-  void* pfnAC_Handler;                    /* 122 Analog Comparators */
-  void* pfnDAC_0_Handler;                 /* 123 Digital-to-Analog Converter IRQ 0 */
-  void* pfnDAC_1_Handler;                 /* 124 Digital-to-Analog Converter IRQ 1 */
-  void* pfnDAC_2_Handler;                 /* 125 Digital-to-Analog Converter IRQ 2 */
-  void* pfnDAC_3_Handler;                 /* 126 Digital-to-Analog Converter IRQ 3 */
-  void* pfnDAC_4_Handler;                 /* 127 Digital-to-Analog Converter IRQ 4 */
-  void* pfnI2S_Handler;                   /* 128 Inter-IC Sound Interface */
-  void* pfnPCC_Handler;                   /* 129 Parallel Capture Controller */
-  void* pfnAES_Handler;                   /* 130 Advanced Encryption Standard */
-  void* pfnTRNG_Handler;                  /* 131 True Random Generator */
-  void* pfnICM_Handler;                   /* 132 Integrity Check Monitor */
-  void* pfnPUKCC_Handler;                 /* 133 PUblic-Key Cryptography Controller */
-  void* pfnQSPI_Handler;                  /* 134 Quad SPI interface */
-  void* pfnSDHC0_Handler;                 /* 135 SD/MMC Host Controller 0 */
-  void* pvReserved136;
-} DeviceVectors;
-
-/* Cortex-M4 processor handlers */
-void Reset_Handler               ( void );
-void NMI_Handler                 ( void );
-void HardFault_Handler           ( void );
-void MemManage_Handler           ( void );
-void BusFault_Handler            ( void );
-void UsageFault_Handler          ( void );
-void SVC_Handler                 ( void );
-void DebugMon_Handler            ( void );
-void PendSV_Handler              ( void );
-void SysTick_Handler             ( void );
-
-/* Peripherals handlers */
-void PM_Handler                  ( void );
-void MCLK_Handler                ( void );
-void OSCCTRL_0_Handler           ( void );
-void OSCCTRL_1_Handler           ( void );
-void OSCCTRL_2_Handler           ( void );
-void OSCCTRL_3_Handler           ( void );
-void OSCCTRL_4_Handler           ( void );
-void OSC32KCTRL_Handler          ( void );
-void SUPC_0_Handler              ( void );
-void SUPC_1_Handler              ( void );
-void WDT_Handler                 ( void );
-void RTC_Handler                 ( void );
-void EIC_0_Handler               ( void );
-void EIC_1_Handler               ( void );
-void EIC_2_Handler               ( void );
-void EIC_3_Handler               ( void );
-void EIC_4_Handler               ( void );
-void EIC_5_Handler               ( void );
-void EIC_6_Handler               ( void );
-void EIC_7_Handler               ( void );
-void EIC_8_Handler               ( void );
-void EIC_9_Handler               ( void );
-void EIC_10_Handler              ( void );
-void EIC_11_Handler              ( void );
-void EIC_12_Handler              ( void );
-void EIC_13_Handler              ( void );
-void EIC_14_Handler              ( void );
-void EIC_15_Handler              ( void );
-void FREQM_Handler               ( void );
-void NVMCTRL_0_Handler           ( void );
-void NVMCTRL_1_Handler           ( void );
-void DMAC_0_Handler              ( void );
-void DMAC_1_Handler              ( void );
-void DMAC_2_Handler              ( void );
-void DMAC_3_Handler              ( void );
-void DMAC_4_Handler              ( void );
-void EVSYS_0_Handler             ( void );
-void EVSYS_1_Handler             ( void );
-void EVSYS_2_Handler             ( void );
-void EVSYS_3_Handler             ( void );
-void EVSYS_4_Handler             ( void );
-void PAC_Handler                 ( void );
-void TAL_0_Handler               ( void );
-void TAL_1_Handler               ( void );
-void RAMECC_Handler              ( void );
-void SERCOM0_0_Handler           ( void );
-void SERCOM0_1_Handler           ( void );
-void SERCOM0_2_Handler           ( void );
-void SERCOM0_3_Handler           ( void );
-void SERCOM1_0_Handler           ( void );
-void SERCOM1_1_Handler           ( void );
-void SERCOM1_2_Handler           ( void );
-void SERCOM1_3_Handler           ( void );
-void SERCOM2_0_Handler           ( void );
-void SERCOM2_1_Handler           ( void );
-void SERCOM2_2_Handler           ( void );
-void SERCOM2_3_Handler           ( void );
-void SERCOM3_0_Handler           ( void );
-void SERCOM3_1_Handler           ( void );
-void SERCOM3_2_Handler           ( void );
-void SERCOM3_3_Handler           ( void );
-void SERCOM4_0_Handler           ( void );
-void SERCOM4_1_Handler           ( void );
-void SERCOM4_2_Handler           ( void );
-void SERCOM4_3_Handler           ( void );
-void SERCOM5_0_Handler           ( void );
-void SERCOM5_1_Handler           ( void );
-void SERCOM5_2_Handler           ( void );
-void SERCOM5_3_Handler           ( void );
-void USB_0_Handler               ( void );
-void USB_1_Handler               ( void );
-void USB_2_Handler               ( void );
-void USB_3_Handler               ( void );
-void TCC0_0_Handler              ( void );
-void TCC0_1_Handler              ( void );
-void TCC0_2_Handler              ( void );
-void TCC0_3_Handler              ( void );
-void TCC0_4_Handler              ( void );
-void TCC0_5_Handler              ( void );
-void TCC0_6_Handler              ( void );
-void TCC1_0_Handler              ( void );
-void TCC1_1_Handler              ( void );
-void TCC1_2_Handler              ( void );
-void TCC1_3_Handler              ( void );
-void TCC1_4_Handler              ( void );
-void TCC2_0_Handler              ( void );
-void TCC2_1_Handler              ( void );
-void TCC2_2_Handler              ( void );
-void TCC2_3_Handler              ( void );
-void TCC3_0_Handler              ( void );
-void TCC3_1_Handler              ( void );
-void TCC3_2_Handler              ( void );
-void TCC4_0_Handler              ( void );
-void TCC4_1_Handler              ( void );
-void TCC4_2_Handler              ( void );
-void TC0_Handler                 ( void );
-void TC1_Handler                 ( void );
-void TC2_Handler                 ( void );
-void TC3_Handler                 ( void );
-void TC4_Handler                 ( void );
-void TC5_Handler                 ( void );
-void PDEC_0_Handler              ( void );
-void PDEC_1_Handler              ( void );
-void PDEC_2_Handler              ( void );
-void ADC0_0_Handler              ( void );
-void ADC0_1_Handler              ( void );
-void ADC1_0_Handler              ( void );
-void ADC1_1_Handler              ( void );
-void AC_Handler                  ( void );
-void DAC_0_Handler               ( void );
-void DAC_1_Handler               ( void );
-void DAC_2_Handler               ( void );
-void DAC_3_Handler               ( void );
-void DAC_4_Handler               ( void );
-void I2S_Handler                 ( void );
-void PCC_Handler                 ( void );
-void AES_Handler                 ( void );
-void TRNG_Handler                ( void );
-void ICM_Handler                 ( void );
-void PUKCC_Handler               ( void );
-void QSPI_Handler                ( void );
-void SDHC0_Handler               ( void );
-
-/*
- * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
- */
-
-#define LITTLE_ENDIAN          1        
-#define __CM4_REV              1         /*!< Core revision r0p1 */
-#define __DEBUG_LVL            3         /*!< Full debug plus DWT data matching */
-#define __FPU_PRESENT          1         /*!< FPU present or not */
-#define __MPU_PRESENT          1         /*!< MPU present or not */
-#define __NVIC_PRIO_BITS       3         /*!< Number of bits used for Priority Levels */
-#define __TRACE_LVL            2         /*!< Full trace: ITM, DWT triggers and counters, ETM */
-#define __VTOR_PRESENT         1         /*!< VTOR present or not */
-#define __Vendor_SysTickConfig 0         /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * \brief CMSIS includes
- */
-
-#include <core_cm4.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_samd51.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_api Peripheral Software API */
-/*@{*/
-
-#include "component/ac.h"
-#include "component/adc.h"
-#include "component/aes.h"
-#include "component/ccl.h"
-#include "component/cmcc.h"
-#include "component/dac.h"
-#include "component/dmac.h"
-#include "component/dsu.h"
-#include "component/eic.h"
-#include "component/evsys.h"
-#include "component/freqm.h"
-#include "component/gclk.h"
-#include "component/hmatrixb.h"
-#include "component/icm.h"
-#include "component/i2s.h"
-#include "component/mclk.h"
-#include "component/nvmctrl.h"
-#include "component/oscctrl.h"
-#include "component/osc32kctrl.h"
-#include "component/pac.h"
-#include "component/pcc.h"
-#include "component/pdec.h"
-#include "component/pm.h"
-#include "component/port.h"
-#include "component/qspi.h"
-#include "component/ramecc.h"
-#include "component/rstc.h"
-#include "component/rtc.h"
-#include "component/sdhc.h"
-#include "component/sercom.h"
-#include "component/supc.h"
-#include "component/tal.h"
-#include "component/tc.h"
-#include "component/tcc.h"
-#include "component/trng.h"
-#include "component/usb.h"
-#include "component/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  REGISTERS ACCESS DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/ac.h"
-#include "instance/adc0.h"
-#include "instance/adc1.h"
-#include "instance/aes.h"
-#include "instance/ccl.h"
-#include "instance/cmcc.h"
-#include "instance/dac.h"
-#include "instance/dmac.h"
-#include "instance/dsu.h"
-#include "instance/eic.h"
-#include "instance/evsys.h"
-#include "instance/freqm.h"
-#include "instance/gclk.h"
-#include "instance/hmatrix.h"
-#include "instance/icm.h"
-#include "instance/i2s.h"
-#include "instance/mclk.h"
-#include "instance/nvmctrl.h"
-#include "instance/oscctrl.h"
-#include "instance/osc32kctrl.h"
-#include "instance/pac.h"
-#include "instance/pcc.h"
-#include "instance/pdec.h"
-#include "instance/pm.h"
-#include "instance/port.h"
-#include "instance/qspi.h"
-#include "instance/ramecc.h"
-#include "instance/rstc.h"
-#include "instance/rtc.h"
-#include "instance/sdhc0.h"
-#include "instance/sercom0.h"
-#include "instance/sercom1.h"
-#include "instance/sercom2.h"
-#include "instance/sercom3.h"
-#include "instance/sercom4.h"
-#include "instance/sercom5.h"
-#include "instance/supc.h"
-#include "instance/tal.h"
-#include "instance/tc0.h"
-#include "instance/tc1.h"
-#include "instance/tc2.h"
-#include "instance/tc3.h"
-#include "instance/tc4.h"
-#include "instance/tc5.h"
-#include "instance/tcc0.h"
-#include "instance/tcc1.h"
-#include "instance/tcc2.h"
-#include "instance/tcc3.h"
-#include "instance/tcc4.h"
-#include "instance/trng.h"
-#include "instance/usb.h"
-#include "instance/wdt.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  PERIPHERAL ID DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_id Peripheral Ids Definitions */
-/*@{*/
-
-// Peripheral instances on HPB0 bridge
-#define ID_PAC            0 /**< \brief Peripheral Access Controller (PAC) */
-#define ID_PM             1 /**< \brief Power Manager (PM) */
-#define ID_MCLK           2 /**< \brief Main Clock (MCLK) */
-#define ID_RSTC           3 /**< \brief Reset Controller (RSTC) */
-#define ID_OSCCTRL        4 /**< \brief Oscillators Control (OSCCTRL) */
-#define ID_OSC32KCTRL     5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
-#define ID_SUPC           6 /**< \brief Supply Controller (SUPC) */
-#define ID_GCLK           7 /**< \brief Generic Clock Generator (GCLK) */
-#define ID_WDT            8 /**< \brief Watchdog Timer (WDT) */
-#define ID_RTC            9 /**< \brief Real-Time Counter (RTC) */
-#define ID_EIC           10 /**< \brief External Interrupt Controller (EIC) */
-#define ID_FREQM         11 /**< \brief Frequency Meter (FREQM) */
-#define ID_SERCOM0       12 /**< \brief Serial Communication Interface 0 (SERCOM0) */
-#define ID_SERCOM1       13 /**< \brief Serial Communication Interface 1 (SERCOM1) */
-#define ID_TC0           14 /**< \brief Basic Timer Counter 0 (TC0) */
-#define ID_TC1           15 /**< \brief Basic Timer Counter 1 (TC1) */
-
-// Peripheral instances on HPB1 bridge
-#define ID_USB           32 /**< \brief Universal Serial Bus (USB) */
-#define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
-#define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
-#define ID_CMCC          35 /**< \brief Cortex M Cache Controller (CMCC) */
-#define ID_PORT          36 /**< \brief Port Module (PORT) */
-#define ID_DMAC          37 /**< \brief Direct Memory Access Controller (DMAC) */
-#define ID_HMATRIX       38 /**< \brief HSB Matrix (HMATRIX) */
-#define ID_EVSYS         39 /**< \brief Event System Interface (EVSYS) */
-#define ID_SERCOM2       41 /**< \brief Serial Communication Interface 2 (SERCOM2) */
-#define ID_SERCOM3       42 /**< \brief Serial Communication Interface 3 (SERCOM3) */
-#define ID_TCC0          43 /**< \brief Timer Counter Control 0 (TCC0) */
-#define ID_TCC1          44 /**< \brief Timer Counter Control 1 (TCC1) */
-#define ID_TC2           45 /**< \brief Basic Timer Counter 2 (TC2) */
-#define ID_TC3           46 /**< \brief Basic Timer Counter 3 (TC3) */
-#define ID_TAL           47 /**< \brief Trigger Allocator (TAL) */
-#define ID_RAMECC        48 /**< \brief RAM ECC (RAMECC) */
-#define ID_TCC2          67 /**< \brief Timer Counter Control 2 (TCC2) */
-#define ID_TCC3          68 /**< \brief Timer Counter Control 3 (TCC3) */
-#define ID_TC4           69 /**< \brief Basic Timer Counter 4 (TC4) */
-#define ID_TC5           70 /**< \brief Basic Timer Counter 5 (TC5) */
-#define ID_PDEC          71 /**< \brief Quadrature Decodeur (PDEC) */
-#define ID_AC            72 /**< \brief Analog Comparators (AC) */
-#define ID_AES           73 /**< \brief Advanced Encryption Standard (AES) */
-#define ID_TRNG          74 /**< \brief True Random Generator (TRNG) */
-#define ID_ICM           75 /**< \brief Integrity Check Monitor (ICM) */
-#define ID_PUKCC         76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
-#define ID_QSPI          77 /**< \brief Quad SPI interface (QSPI) */
-#define ID_CCL           78 /**< \brief Configurable Custom Logic (CCL) */
-
-// Peripheral instances on HPB3 bridge
-#define ID_SERCOM4       96 /**< \brief Serial Communication Interface 4 (SERCOM4) */
-#define ID_SERCOM5       97 /**< \brief Serial Communication Interface 5 (SERCOM5) */
-#define ID_TCC4         100 /**< \brief Timer Counter Control 4 (TCC4) */
-#define ID_ADC0         103 /**< \brief Analog Digital Converter 0 (ADC0) */
-#define ID_ADC1         104 /**< \brief Analog Digital Converter 1 (ADC1) */
-#define ID_DAC          105 /**< \brief Digital-to-Analog Converter (DAC) */
-#define ID_I2S          106 /**< \brief Inter-IC Sound Interface (I2S) */
-#define ID_PCC          107 /**< \brief Parallel Capture Controller (PCC) */
-
-// Peripheral instances on AHB (as if on bridge 4)
-#define ID_SDHC0        128 /**< \brief SD/MMC Host Controller (SDHC0) */
-
-#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/**  BASE ADDRESS DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
-#define AC                            (0x42002000) /**< \brief (AC) APB Base Address */
-#define ADC0                          (0x43001C00) /**< \brief (ADC0) APB Base Address */
-#define ADC1                          (0x43002000) /**< \brief (ADC1) APB Base Address */
-#define AES                           (0x42002400) /**< \brief (AES) APB Base Address */
-#define CCL                           (0x42003800) /**< \brief (CCL) APB Base Address */
-#define CMCC                          (0x41006000) /**< \brief (CMCC) APB Base Address */
-#define CMCC_AHB                      (0x03000000) /**< \brief (CMCC) AHB Base Address */
-#define DAC                           (0x43002400) /**< \brief (DAC) APB Base Address */
-#define DMAC                          (0x4100A000) /**< \brief (DMAC) APB Base Address */
-#define DSU                           (0x41002000) /**< \brief (DSU) APB Base Address */
-#define EIC                           (0x40002800) /**< \brief (EIC) APB Base Address */
-#define EVSYS                         (0x4100E000) /**< \brief (EVSYS) APB Base Address */
-#define FREQM                         (0x40002C00) /**< \brief (FREQM) APB Base Address */
-#define GCLK                          (0x40001C00) /**< \brief (GCLK) APB Base Address */
-#define HMATRIX                       (0x4100C000) /**< \brief (HMATRIX) APB Base Address */
-#define ICM                           (0x42002C00) /**< \brief (ICM) APB Base Address */
-#define I2S                           (0x43002800) /**< \brief (I2S) APB Base Address */
-#define MCLK                          (0x40000800) /**< \brief (MCLK) APB Base Address */
-#define NVMCTRL                       (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CB                    (0x00800000) /**< \brief (NVMCTRL) CB Base Address */
-#define NVMCTRL_CBW0                  (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */
-#define NVMCTRL_CBW1                  (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */
-#define NVMCTRL_CBW2                  (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */
-#define NVMCTRL_CBW3                  (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */
-#define NVMCTRL_CBW4                  (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */
-#define NVMCTRL_CBW5                  (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */
-#define NVMCTRL_CBW6                  (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */
-#define NVMCTRL_CBW7                  (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */
-#define NVMCTRL_FS                    (0x00806000) /**< \brief (NVMCTRL) FS Base Address */
-#define NVMCTRL_SW0                   (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */
-#define NVMCTRL_SW1                   (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */
-#define NVMCTRL_SW2                   (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */
-#define NVMCTRL_SW3                   (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */
-#define NVMCTRL_SW4                   (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */
-#define NVMCTRL_SW5                   (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */
-#define NVMCTRL_SW6                   (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */
-#define NVMCTRL_SW7                   (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_TEMP_LOG_W0           (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
-#define NVMCTRL_TEMP_LOG_W1           (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
-#define NVMCTRL_TEMP_LOG_W2           (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
-#define NVMCTRL_TEMP_LOG_W3           (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
-#define NVMCTRL_TEMP_LOG_W4           (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
-#define NVMCTRL_TEMP_LOG_W5           (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
-#define NVMCTRL_TEMP_LOG_W6           (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
-#define NVMCTRL_TEMP_LOG_W7           (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
-#define NVMCTRL_TLATCH                (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */
-#define NVMCTRL_USER                  (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
-#define OSCCTRL                       (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
-#define OSC32KCTRL                    (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
-#define PAC                           (0x40000000) /**< \brief (PAC) APB Base Address */
-#define PCC                           (0x43002C00) /**< \brief (PCC) APB Base Address */
-#define PDEC                          (0x42001C00) /**< \brief (PDEC) APB Base Address */
-#define PM                            (0x40000400) /**< \brief (PM) APB Base Address */
-#define PORT                          (0x41008000) /**< \brief (PORT) APB Base Address */
-#define PUKCC                         (0x42003000) /**< \brief (PUKCC) APB Base Address */
-#define PUKCC_AHB                     (0x02000000) /**< \brief (PUKCC) AHB Base Address */
-#define QSPI                          (0x42003400) /**< \brief (QSPI) APB Base Address */
-#define QSPI_AHB                      (0x04000000) /**< \brief (QSPI) AHB Base Address */
-#define RAMECC                        (0x41020000) /**< \brief (RAMECC) APB Base Address */
-#define RSTC                          (0x40000C00) /**< \brief (RSTC) APB Base Address */
-#define RTC                           (0x40002400) /**< \brief (RTC) APB Base Address */
-#define SDHC0                         (0x45000000) /**< \brief (SDHC0) AHB Base Address */
-#define SERCOM0                       (0x40003000) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1                       (0x40003400) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2                       (0x41012000) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3                       (0x41014000) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4                       (0x43000000) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5                       (0x43000400) /**< \brief (SERCOM5) APB Base Address */
-#define SUPC                          (0x40001800) /**< \brief (SUPC) APB Base Address */
-#define TAL                           (0x4101E000) /**< \brief (TAL) APB Base Address */
-#define TC0                           (0x40003800) /**< \brief (TC0) APB Base Address */
-#define TC1                           (0x40003C00) /**< \brief (TC1) APB Base Address */
-#define TC2                           (0x4101A000) /**< \brief (TC2) APB Base Address */
-#define TC3                           (0x4101C000) /**< \brief (TC3) APB Base Address */
-#define TC4                           (0x42001400) /**< \brief (TC4) APB Base Address */
-#define TC5                           (0x42001800) /**< \brief (TC5) APB Base Address */
-#define TCC0                          (0x41016000) /**< \brief (TCC0) APB Base Address */
-#define TCC1                          (0x41018000) /**< \brief (TCC1) APB Base Address */
-#define TCC2                          (0x42000C00) /**< \brief (TCC2) APB Base Address */
-#define TCC3                          (0x42001000) /**< \brief (TCC3) APB Base Address */
-#define TCC4                          (0x43001000) /**< \brief (TCC4) APB Base Address */
-#define TRNG                          (0x42002800) /**< \brief (TRNG) APB Base Address */
-#define USB                           (0x41000000) /**< \brief (USB) APB Base Address */
-#define WDT                           (0x40002000) /**< \brief (WDT) APB Base Address */
-#else
-#define AC                ((Ac       *)0x42002000UL) /**< \brief (AC) APB Base Address */
-#define AC_INST_NUM       1                          /**< \brief (AC) Number of instances */
-#define AC_INSTS          { AC }                     /**< \brief (AC) Instances List */
-
-#define ADC0              ((Adc      *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */
-#define ADC1              ((Adc      *)0x43002000UL) /**< \brief (ADC1) APB Base Address */
-#define ADC_INST_NUM      2                          /**< \brief (ADC) Number of instances */
-#define ADC_INSTS         { ADC0, ADC1 }             /**< \brief (ADC) Instances List */
-
-#define AES               ((Aes      *)0x42002400UL) /**< \brief (AES) APB Base Address */
-#define AES_INST_NUM      1                          /**< \brief (AES) Number of instances */
-#define AES_INSTS         { AES }                    /**< \brief (AES) Instances List */
-
-#define CCL               ((Ccl      *)0x42003800UL) /**< \brief (CCL) APB Base Address */
-#define CCL_INST_NUM      1                          /**< \brief (CCL) Number of instances */
-#define CCL_INSTS         { CCL }                    /**< \brief (CCL) Instances List */
-
-#define CMCC              ((Cmcc     *)0x41006000UL) /**< \brief (CMCC) APB Base Address */
-#define CMCC_AHB                      (0x03000000UL) /**< \brief (CMCC) AHB Base Address */
-#define CMCC_INST_NUM     1                          /**< \brief (CMCC) Number of instances */
-#define CMCC_INSTS        { CMCC }                   /**< \brief (CMCC) Instances List */
-
-#define DAC               ((Dac      *)0x43002400UL) /**< \brief (DAC) APB Base Address */
-#define DAC_INST_NUM      1                          /**< \brief (DAC) Number of instances */
-#define DAC_INSTS         { DAC }                    /**< \brief (DAC) Instances List */
-
-#define DMAC              ((Dmac     *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */
-#define DMAC_INST_NUM     1                          /**< \brief (DMAC) Number of instances */
-#define DMAC_INSTS        { DMAC }                   /**< \brief (DMAC) Instances List */
-
-#define DSU               ((Dsu      *)0x41002000UL) /**< \brief (DSU) APB Base Address */
-#define DSU_INST_NUM      1                          /**< \brief (DSU) Number of instances */
-#define DSU_INSTS         { DSU }                    /**< \brief (DSU) Instances List */
-
-#define EIC               ((Eic      *)0x40002800UL) /**< \brief (EIC) APB Base Address */
-#define EIC_INST_NUM      1                          /**< \brief (EIC) Number of instances */
-#define EIC_INSTS         { EIC }                    /**< \brief (EIC) Instances List */
-
-#define EVSYS             ((Evsys    *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */
-#define EVSYS_INST_NUM    1                          /**< \brief (EVSYS) Number of instances */
-#define EVSYS_INSTS       { EVSYS }                  /**< \brief (EVSYS) Instances List */
-
-#define FREQM             ((Freqm    *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
-#define FREQM_INST_NUM    1                          /**< \brief (FREQM) Number of instances */
-#define FREQM_INSTS       { FREQM }                  /**< \brief (FREQM) Instances List */
-
-#define GCLK              ((Gclk     *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
-#define GCLK_INST_NUM     1                          /**< \brief (GCLK) Number of instances */
-#define GCLK_INSTS        { GCLK }                   /**< \brief (GCLK) Instances List */
-
-#define HMATRIX           ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */
-#define HMATRIXB_INST_NUM 1                          /**< \brief (HMATRIXB) Number of instances */
-#define HMATRIXB_INSTS    { HMATRIX }                /**< \brief (HMATRIXB) Instances List */
-
-#define ICM               ((Icm      *)0x42002C00UL) /**< \brief (ICM) APB Base Address */
-#define ICM_INST_NUM      1                          /**< \brief (ICM) Number of instances */
-#define ICM_INSTS         { ICM }                    /**< \brief (ICM) Instances List */
-
-#define I2S               ((I2s      *)0x43002800UL) /**< \brief (I2S) APB Base Address */
-#define I2S_INST_NUM      1                          /**< \brief (I2S) Number of instances */
-#define I2S_INSTS         { I2S }                    /**< \brief (I2S) Instances List */
-
-#define MCLK              ((Mclk     *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
-#define MCLK_INST_NUM     1                          /**< \brief (MCLK) Number of instances */
-#define MCLK_INSTS        { MCLK }                   /**< \brief (MCLK) Instances List */
-
-#define NVMCTRL           ((Nvmctrl  *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
-#define NVMCTRL_CB                    (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */
-#define NVMCTRL_CBW0                  (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */
-#define NVMCTRL_CBW1                  (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */
-#define NVMCTRL_CBW2                  (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */
-#define NVMCTRL_CBW3                  (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */
-#define NVMCTRL_CBW4                  (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */
-#define NVMCTRL_CBW5                  (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */
-#define NVMCTRL_CBW6                  (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */
-#define NVMCTRL_CBW7                  (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */
-#define NVMCTRL_FS                    (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */
-#define NVMCTRL_SW0                   (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */
-#define NVMCTRL_SW1                   (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */
-#define NVMCTRL_SW2                   (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */
-#define NVMCTRL_SW3                   (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */
-#define NVMCTRL_SW4                   (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */
-#define NVMCTRL_SW5                   (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */
-#define NVMCTRL_SW6                   (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */
-#define NVMCTRL_SW7                   (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */
-#define NVMCTRL_TEMP_LOG              (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
-#define NVMCTRL_TEMP_LOG_W0           (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */
-#define NVMCTRL_TEMP_LOG_W1           (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */
-#define NVMCTRL_TEMP_LOG_W2           (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */
-#define NVMCTRL_TEMP_LOG_W3           (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */
-#define NVMCTRL_TEMP_LOG_W4           (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */
-#define NVMCTRL_TEMP_LOG_W5           (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */
-#define NVMCTRL_TEMP_LOG_W6           (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */
-#define NVMCTRL_TEMP_LOG_W7           (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */
-#define NVMCTRL_TLATCH                (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */
-#define NVMCTRL_USER                  (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
-#define NVMCTRL_INST_NUM  1                          /**< \brief (NVMCTRL) Number of instances */
-#define NVMCTRL_INSTS     { NVMCTRL }                /**< \brief (NVMCTRL) Instances List */
-
-#define OSCCTRL           ((Oscctrl  *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
-#define OSCCTRL_INST_NUM  1                          /**< \brief (OSCCTRL) Number of instances */
-#define OSCCTRL_INSTS     { OSCCTRL }                /**< \brief (OSCCTRL) Instances List */
-
-#define OSC32KCTRL        ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
-#define OSC32KCTRL_INST_NUM 1                          /**< \brief (OSC32KCTRL) Number of instances */
-#define OSC32KCTRL_INSTS  { OSC32KCTRL }             /**< \brief (OSC32KCTRL) Instances List */
-
-#define PAC               ((Pac      *)0x40000000UL) /**< \brief (PAC) APB Base Address */
-#define PAC_INST_NUM      1                          /**< \brief (PAC) Number of instances */
-#define PAC_INSTS         { PAC }                    /**< \brief (PAC) Instances List */
-
-#define PCC               ((Pcc      *)0x43002C00UL) /**< \brief (PCC) APB Base Address */
-#define PCC_INST_NUM      1                          /**< \brief (PCC) Number of instances */
-#define PCC_INSTS         { PCC }                    /**< \brief (PCC) Instances List */
-
-#define PDEC              ((Pdec     *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */
-#define PDEC_INST_NUM     1                          /**< \brief (PDEC) Number of instances */
-#define PDEC_INSTS        { PDEC }                   /**< \brief (PDEC) Instances List */
-
-#define PM                ((Pm       *)0x40000400UL) /**< \brief (PM) APB Base Address */
-#define PM_INST_NUM       1                          /**< \brief (PM) Number of instances */
-#define PM_INSTS          { PM }                     /**< \brief (PM) Instances List */
-
-#define PORT              ((Port     *)0x41008000UL) /**< \brief (PORT) APB Base Address */
-#define PORT_INST_NUM     1                          /**< \brief (PORT) Number of instances */
-#define PORT_INSTS        { PORT }                   /**< \brief (PORT) Instances List */
-
-#define PUKCC             ((void     *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */
-#define PUKCC_AHB         ((void     *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */
-#define PUKCC_INST_NUM    1                          /**< \brief (PUKCC) Number of instances */
-#define PUKCC_INSTS       { PUKCC }                  /**< \brief (PUKCC) Instances List */
-
-#define QSPI              ((Qspi     *)0x42003400UL) /**< \brief (QSPI) APB Base Address */
-#define QSPI_AHB                      (0x04000000UL) /**< \brief (QSPI) AHB Base Address */
-#define QSPI_INST_NUM     1                          /**< \brief (QSPI) Number of instances */
-#define QSPI_INSTS        { QSPI }                   /**< \brief (QSPI) Instances List */
-
-#define RAMECC            ((Ramecc   *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */
-#define RAMECC_INST_NUM   1                          /**< \brief (RAMECC) Number of instances */
-#define RAMECC_INSTS      { RAMECC }                 /**< \brief (RAMECC) Instances List */
-
-#define RSTC              ((Rstc     *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
-#define RSTC_INST_NUM     1                          /**< \brief (RSTC) Number of instances */
-#define RSTC_INSTS        { RSTC }                   /**< \brief (RSTC) Instances List */
-
-#define RTC               ((Rtc      *)0x40002400UL) /**< \brief (RTC) APB Base Address */
-#define RTC_INST_NUM      1                          /**< \brief (RTC) Number of instances */
-#define RTC_INSTS         { RTC }                    /**< \brief (RTC) Instances List */
-
-#define SDHC0             ((Sdhc     *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */
-#define SDHC_INST_NUM     1                          /**< \brief (SDHC) Number of instances */
-#define SDHC_INSTS        { SDHC0 }                  /**< \brief (SDHC) Instances List */
-
-#define SERCOM0           ((Sercom   *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */
-#define SERCOM1           ((Sercom   *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */
-#define SERCOM2           ((Sercom   *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */
-#define SERCOM3           ((Sercom   *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */
-#define SERCOM4           ((Sercom   *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */
-#define SERCOM5           ((Sercom   *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */
-#define SERCOM_INST_NUM   6                          /**< \brief (SERCOM) Number of instances */
-#define SERCOM_INSTS      { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
-
-#define SUPC              ((Supc     *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
-#define SUPC_INST_NUM     1                          /**< \brief (SUPC) Number of instances */
-#define SUPC_INSTS        { SUPC }                   /**< \brief (SUPC) Instances List */
-
-#define TAL               ((Tal      *)0x4101E000UL) /**< \brief (TAL) APB Base Address */
-#define TAL_INST_NUM      1                          /**< \brief (TAL) Number of instances */
-#define TAL_INSTS         { TAL }                    /**< \brief (TAL) Instances List */
-
-#define TC0               ((Tc       *)0x40003800UL) /**< \brief (TC0) APB Base Address */
-#define TC1               ((Tc       *)0x40003C00UL) /**< \brief (TC1) APB Base Address */
-#define TC2               ((Tc       *)0x4101A000UL) /**< \brief (TC2) APB Base Address */
-#define TC3               ((Tc       *)0x4101C000UL) /**< \brief (TC3) APB Base Address */
-#define TC4               ((Tc       *)0x42001400UL) /**< \brief (TC4) APB Base Address */
-#define TC5               ((Tc       *)0x42001800UL) /**< \brief (TC5) APB Base Address */
-#define TC_INST_NUM       6                          /**< \brief (TC) Number of instances */
-#define TC_INSTS          { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */
-
-#define TCC0              ((Tcc      *)0x41016000UL) /**< \brief (TCC0) APB Base Address */
-#define TCC1              ((Tcc      *)0x41018000UL) /**< \brief (TCC1) APB Base Address */
-#define TCC2              ((Tcc      *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */
-#define TCC3              ((Tcc      *)0x42001000UL) /**< \brief (TCC3) APB Base Address */
-#define TCC4              ((Tcc      *)0x43001000UL) /**< \brief (TCC4) APB Base Address */
-#define TCC_INST_NUM      5                          /**< \brief (TCC) Number of instances */
-#define TCC_INSTS         { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */
-
-#define TRNG              ((Trng     *)0x42002800UL) /**< \brief (TRNG) APB Base Address */
-#define TRNG_INST_NUM     1                          /**< \brief (TRNG) Number of instances */
-#define TRNG_INSTS        { TRNG }                   /**< \brief (TRNG) Instances List */
-
-#define USB               ((Usb      *)0x41000000UL) /**< \brief (USB) APB Base Address */
-#define USB_INST_NUM      1                          /**< \brief (USB) Number of instances */
-#define USB_INSTS         { USB }                    /**< \brief (USB) Instances List */
-
-#define WDT               ((Wdt      *)0x40002000UL) /**< \brief (WDT) APB Base Address */
-#define WDT_INST_NUM      1                          /**< \brief (WDT) Number of instances */
-#define WDT_INSTS         { WDT }                    /**< \brief (WDT) Instances List */
-
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/**  PORT DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-/** \defgroup SAMD51J18A_port PORT Definitions */
-/*@{*/
-
-#include "pio/samd51j18a.h"
-/*@}*/
-
-/* ************************************************************************** */
-/**  MEMORY MAPPING DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-
-#define HSRAM_SIZE            _UL_(0x00020000) /* 128 kB */
-#define FLASH_SIZE            _UL_(0x00040000) /* 256 kB */
-#define FLASH_PAGE_SIZE       512
-#define FLASH_NB_OF_PAGES     512
-#define FLASH_USER_PAGE_SIZE  512
-#define BKUPRAM_SIZE          _UL_(0x00002000) /* 8 kB */
-#define QSPI_SIZE             _UL_(0x01000000) /* 16384 kB */
-
-#define FLASH_ADDR            _UL_(0x00000000) /**< FLASH base address */
-#define CMCC_DATARAM_ADDR     _UL_(0x03000000) /**< CMCC_DATARAM base address */
-#define CMCC_DATARAM_SIZE     _UL_(0x00001000) /**< CMCC_DATARAM size */
-#define CMCC_TAGRAM_ADDR      _UL_(0x03001000) /**< CMCC_TAGRAM base address */
-#define CMCC_TAGRAM_SIZE      _UL_(0x00000400) /**< CMCC_TAGRAM size */
-#define CMCC_VALIDRAM_ADDR    _UL_(0x03002000) /**< CMCC_VALIDRAM base address */
-#define CMCC_VALIDRAM_SIZE    _UL_(0x00000040) /**< CMCC_VALIDRAM size */
-#define HSRAM_ADDR            _UL_(0x20000000) /**< HSRAM base address */
-#define HSRAM_ETB_ADDR        _UL_(0x20000000) /**< HSRAM_ETB base address */
-#define HSRAM_ETB_SIZE        _UL_(0x00008000) /**< HSRAM_ETB size */
-#define HSRAM_RET1_ADDR       _UL_(0x20000000) /**< HSRAM_RET1 base address */
-#define HSRAM_RET1_SIZE       _UL_(0x00008000) /**< HSRAM_RET1 size */
-#define HPB0_ADDR             _UL_(0x40000000) /**< HPB0 base address */
-#define HPB1_ADDR             _UL_(0x41000000) /**< HPB1 base address */
-#define HPB2_ADDR             _UL_(0x42000000) /**< HPB2 base address */
-#define HPB3_ADDR             _UL_(0x43000000) /**< HPB3 base address */
-#define SEEPROM_ADDR          _UL_(0x44000000) /**< SEEPROM base address */
-#define BKUPRAM_ADDR          _UL_(0x47000000) /**< BKUPRAM base address */
-#define PPB_ADDR              _UL_(0xE0000000) /**< PPB base address */
-
-#define DSU_DID_RESETVALUE    _UL_(0x60060006)
-#define ADC0_TOUCH_LINES_NUM  32
-#define PORT_GROUPS           2
-
-/* ************************************************************************** */
-/**  ELECTRICAL DEFINITIONS FOR SAMD51J18A */
-/* ************************************************************************** */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* SAMD51J18A_H */
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h
deleted file mode 100644
index cfbd2b921b..0000000000
--- a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/system_samd51.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
- * \file
- *
- * \brief Low-level initialization functions called upon chip startup
- *
- * Copyright (c) 2017 Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- * 
- * http://www.apache.org/licenses/LICENSE-2.0
- * 
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SYSTEM_SAMD51_H_INCLUDED_
-#define _SYSTEM_SAMD51_H_INCLUDED_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;   /*!< System Clock Frequency (Core Clock)  */
-
-void SystemInit(void);
-void SystemCoreClockUpdate(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_SAMD51_H_INCLUDED */
diff --git a/lib/fnv/Makefile b/lib/fnv/Makefile
deleted file mode 100644
index c0673ded40..0000000000
--- a/lib/fnv/Makefile
+++ /dev/null
@@ -1,304 +0,0 @@
-#!/bin/make
-#
-# hash - makefile for FNV hash tools
-#
-# @(#) $Revision: 5.2 $
-# @(#) $Id: Makefile,v 5.2 2012/03/21 01:42:15 chongo Exp $
-# @(#) $Source: /usr/local/src/cmd/fnv/RCS/Makefile,v $
-#
-# See:
-#	http://www.isthe.com/chongo/tech/comp/fnv/index.html
-#
-# for the most up to date copy of this code and the FNV hash home page.
-#
-# Please do not copyright this code.  This code is in the public domain.
-#
-# LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
-# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
-# EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
-# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
-# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
-# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
-# PERFORMANCE OF THIS SOFTWARE.
-#
-# By:
-#	chongo <Landon Curt Noll> /\oo/\
-#	http://www.isthe.com/chongo/
-#
-# Share and Enjoy!	:-)
-
-# make tools
-#
-SHELL= /bin/sh
-CFLAGS= -O3 -g3
-#CFLAGS= -O2 -g3
-#CC= cc
-AR= ar
-TAR= tar
-EGREP= egrep
-GZIP_BIN= gzip
-INSTALL= install
-
-# If your system needs ranlib use:
-#	RANLIB= ranlib
-# otherwise use:
-#	RANLIB= :
-#
-#RANLIB= ranlib
-RANLIB= :
-
-# where to install things
-#
-DESTBIN= /usr/local/bin
-DESTLIB= /usr/local/lib
-DESTINC= /usr/local/include
-
-# what to build
-#
-SRC=	hash_32.c hash_32a.c hash_64.c hash_64a.c \
-	fnv32.c fnv64.c \
-	have_ulong64.c test_fnv.c
-NO64BIT_SRC= no64bit_fnv64.c no64bit_hash_64.c \
-	no64bit_hash_64a.c no64bit_test_fnv.c
-HSRC=	fnv.h \
-	longlong.h
-ALL=	${SRC} ${HSRC} \
-	README Makefile
-PROGS=	fnv032 fnv064 fnv132 fnv164 fnv1a32 fnv1a64
-OBSOLETE_PROGS=	fnv0_32 fnv0_64 fnv1_32 fnv1_64 fnv1a_32 fnv1a_64
-NO64BIT_PROGS= no64bit_fnv064 no64bit_fnv164 no64bit_fnv1a64
-LIBS=	libfnv.a
-LIBOBJ=	hash_32.o hash_64.o hash_32a.o hash_64a.o test_fnv.o
-NO64BIT_OBJ= no64bit_fnv64.o no64bit_hash_64.o \
-	no64bit_hash_64a.o no64bit_test_fnv.o
-OTHEROBJ= fnv32.o fnv64.o
-TARGETS= ${LIBOBJ} ${LIBS} ${PROGS}
-
-# default rule
-#
-all: ${TARGETS}
-
-# things to build
-#
-hash_32.o: hash_32.c longlong.h fnv.h
-	${CC} ${CFLAGS} hash_32.c -c
-
-hash_64.o: hash_64.c longlong.h fnv.h
-	${CC} ${CFLAGS} hash_64.c -c
-
-hash_32a.o: hash_32a.c longlong.h fnv.h
-	${CC} ${CFLAGS} hash_32a.c -c
-
-hash_64a.o: hash_64a.c longlong.h fnv.h
-	${CC} ${CFLAGS} hash_64a.c -c
-
-test_fnv.o: test_fnv.c longlong.h fnv.h
-	${CC} ${CFLAGS} test_fnv.c -c
-
-fnv32.o: fnv32.c longlong.h fnv.h
-	${CC} ${CFLAGS} fnv32.c -c
-
-fnv032: fnv32.o libfnv.a
-	${CC} fnv32.o libfnv.a -o fnv032
-
-fnv64.o: fnv64.c longlong.h fnv.h
-	${CC} ${CFLAGS} fnv64.c -c
-
-fnv064: fnv64.o libfnv.a
-	${CC} fnv64.o libfnv.a -o fnv064
-
-libfnv.a: ${LIBOBJ}
-	rm -f $@
-	${AR} rv $@ ${LIBOBJ}
-	${RANLIB} $@
-
-fnv132: fnv032
-	-rm -f $@
-	-cp -f $? $@
-
-fnv1a32: fnv032
-	-rm -f $@
-	-cp -f $? $@
-
-fnv164: fnv064
-	-rm -f $@
-	-cp -f $? $@
-
-fnv1a64: fnv064
-	-rm -f $@
-	-cp -f $? $@
-
-longlong.h: have_ulong64.c Makefile
-	-@rm -f have_ulong64 have_ulong64.o ll_tmp longlong.h
-	@echo 'forming longlong.h'
-	@echo '/*' > longlong.h
-	@echo ' * DO NOT EDIT -- generated by the Makefile' >> longlong.h
-	@echo ' */' >> longlong.h
-	@echo '' >> longlong.h
-	@echo '#if !defined(__LONGLONG_H__)' >> longlong.h
-	@echo '#define __LONGLONG_H__' >> longlong.h
-	@echo '' >> longlong.h
-	@echo '/* do we have/want to use a long long type? */' >> longlong.h
-	-@rm -f have_ulong64.o have_ulong64
-	-@${CC} ${CFLAGS} have_ulong64.c -c 2>/dev/null; true
-	-@${CC} ${CFLAGS} have_ulong64.o -o have_ulong64 2>/dev/null; true
-	-@${SHELL} -c "./have_ulong64 > ll_tmp 2>/dev/null" \
-	    >/dev/null 2>&1; true
-	-@if [ -s ll_tmp ]; then \
-	    cat ll_tmp >> longlong.h; \
-	else \
-	    echo '#undef HAVE_64BIT_LONG_LONG	/* no */' >> longlong.h; \
-	fi
-	@echo '' >> longlong.h
-	@echo '/*' >> longlong.h
-	@echo ' * NO64BIT_LONG_LONG undef HAVE_64BIT_LONG_LONG' >> longlong.h
-	@echo ' */' >> longlong.h
-	@echo '#if defined(NO64BIT_LONG_LONG)' >> longlong.h
-	@echo '#undef HAVE_64BIT_LONG_LONG' >> longlong.h
-	@echo '#endif /* NO64BIT_LONG_LONG */' >> longlong.h
-	@echo '' >> longlong.h
-	@echo '#endif /* !__LONGLONG_H__ */' >> longlong.h
-	-@rm -f have_ulong64 have_ulong64.o ll_tmp
-	@echo 'longlong.h formed'
-
-# utilities
-#
-install: all
-	-@if [ -d "${DESTBIN}" ]; then \
-	    echo "	mkdir -p ${DESTBIN}"; \
-	    mkdir -p ${DESTBIN}; \
-	fi
-	-@if [ -d "${DESTLIB}" ]; then \
-	    echo "	mkdir -p ${DESTLIB}"; \
-	    mkdir -p ${DESTLIB}; \
-	fi
-	-@if [ -d "${DESTINC}" ]; then \
-	    echo "	mkdir -p ${DESTINC}"; \
-	    mkdir -p ${DESTINC}; \
-	fi
-	${INSTALL} -m 0755 ${PROGS} ${DESTBIN}
-	${INSTALL} -m 0644 ${LIBS} ${DESTLIB}
-	${RANLIB} ${DESTLIB}/libfnv.a
-	${INSTALL} -m 0644 ${HSRC} ${DESTINC}
-	@# remove osolete programs
-	for i in ${OBSOLETE_PROGS}; do \
-	    if [ -f "${DESTBIN}/$$i" ]; then \
-	        echo "rm -f ${DESTBIN}/$$i"; \
-		rm -f "${DESTBIN}/$$i"; \
-	    fi; \
-	done
-
-clean:
-	-rm -f have_ulong64 have_ulong64.o ll_tmp ll_tmp2 longlong.h
-	-rm -f ${LIBOBJ}
-	-rm -f ${OTHEROBJ}
-
-clobber: clean
-	-rm -f ${TARGETS}
-	-rm -f ${OBSOLETE_PROGS} lltmp lltmp2 ll_tmp
-	-rm -f ${NO64BIT_SRC}
-	-rm -f ${NO64BIT_OBJ}
-	-rm -f ${NO64BIT_PROGS}
-	-rm -f vector.c
-
-check: ${PROGS}
-	@echo -n "FNV-0 32 bit tests: "
-	@./fnv032 -t 1 -v
-	@echo -n "FNV-1 32 bit tests: "
-	@./fnv132 -t 1 -v
-	@echo -n "FNV-1a 32 bit tests: "
-	@./fnv1a32 -t 1 -v
-	@echo -n "FNV-0 64 bit tests: "
-	@./fnv064 -t 1 -v
-	@echo -n "FNV-1 64 bit tests: "
-	@./fnv164 -t 1 -v
-	@echo -n "FNV-1a 64 bit tests: "
-	@./fnv1a64 -t 1 -v
-
-###############################
-# generate test vector source #
-###############################
-
-no64bit_fnv64.c: fnv64.c
-	-rm -f $@
-	-cp -f $? $@
-
-no64bit_hash_64.c: hash_64.c
-	-rm -f $@
-	-cp -f $? $@
-
-no64bit_hash_64a.c: hash_64a.c
-	-rm -f $@
-	-cp -f $? $@
-
-no64bit_test_fnv.c: test_fnv.c
-	-rm -f $@
-	-cp -f $? $@
-
-no64bit_fnv64.o: no64bit_fnv64.c longlong.h fnv.h
-	${CC} ${CFLAGS} -DNO64BIT_LONG_LONG no64bit_fnv64.c -c
-
-no64bit_hash_64.o: no64bit_hash_64.c longlong.h fnv.h
-	${CC} ${CFLAGS} -DNO64BIT_LONG_LONG no64bit_hash_64.c -c
-
-no64bit_hash_64a.o: no64bit_hash_64a.c longlong.h fnv.h
-	${CC} ${CFLAGS} -DNO64BIT_LONG_LONG no64bit_hash_64a.c -c
-
-no64bit_test_fnv.o: no64bit_test_fnv.c longlong.h fnv.h
-	${CC} ${CFLAGS} -DNO64BIT_LONG_LONG no64bit_test_fnv.c -c
-
-no64bit_fnv064: no64bit_fnv64.o no64bit_hash_64.o \
-		no64bit_hash_64a.o no64bit_test_fnv.o
-	${CC} ${CFLAGS} no64bit_fnv64.o no64bit_hash_64.o \
-		        no64bit_hash_64a.o no64bit_test_fnv.o -o $@
-
-no64bit_fnv164: no64bit_fnv064
-	-rm -f $@
-	-cp -f $? $@
-
-no64bit_fnv1a64: no64bit_fnv064
-	-rm -f $@
-	-cp -f $? $@
-
-vector.c: ${PROGS} ${NO64BIT_PROGS}
-	-rm -f $@
-	echo '/* start of output generated by make $@ */' >> $@
-	echo '' >> $@
-	#@
-	echo '/* FNV-0 32 bit test vectors */' >> $@
-	./fnv032 -t 0 >> $@
-	echo '' >> $@
-	#@
-	echo '/* FNV-1 32 bit test vectors */' >> $@
-	./fnv132 -t 0 >> $@
-	echo '' >> $@
-	#@
-	echo '/* FNV-1a 32 bit test vectors */' >> $@
-	./fnv1a32 -t 0 >> $@
-	echo '' >> $@
-	#@
-	echo '/* FNV-0 64 bit test vectors */' >> $@
-	echo '#if defined(HAVE_64BIT_LONG_LONG)' >> $@
-	./fnv064 -t 0 >> $@
-	echo '#else /* HAVE_64BIT_LONG_LONG */' >> $@
-	./no64bit_fnv064 -t 0 >> $@
-	echo '#endif /* HAVE_64BIT_LONG_LONG */' >> $@
-	echo '' >> $@
-	#@
-	echo '/* FNV-1 64 bit test vectors */' >> $@
-	echo '#if defined(HAVE_64BIT_LONG_LONG)' >> $@
-	./fnv164 -t 0 >> $@
-	echo '#else /* HAVE_64BIT_LONG_LONG */' >> $@
-	./no64bit_fnv164 -t 0 >> $@
-	echo '#endif /* HAVE_64BIT_LONG_LONG */' >> $@
-	echo '' >> $@
-	#@
-	echo '/* FNV-1a 64 bit test vectors */' >> $@
-	echo '#if defined(HAVE_64BIT_LONG_LONG)' >> $@
-	./fnv1a64 -t 0 >> $@
-	echo '#else /* HAVE_64BIT_LONG_LONG */' >> $@
-	./no64bit_fnv1a64 -t 0 >> $@
-	echo '#endif /* HAVE_64BIT_LONG_LONG */' >> $@
-	echo '' >> $@
-	#@
-	echo '/* end of output generated by make $@ */' >> $@
diff --git a/lib/fnv/README b/lib/fnv/README
deleted file mode 100644
index 60aa9aaf61..0000000000
--- a/lib/fnv/README
+++ /dev/null
@@ -1,158 +0,0 @@
-#=====================#
-# Fowler/Noll/Vo hash #
-#=====================#
-
-The basis of this hash algorithm was taken from an idea sent
-as reviewer comments to the IEEE POSIX P1003.2 committee by:
-
-     Phong Vo (http://www.research.att.com/info/kpv)
-     Glenn Fowler (http://www.research.att.com/~gsf/)
-
-In a subsequent ballot round:
-
-     Landon Curt Noll (http://www.isthe.com/chongo)
-
-improved on their algorithm.  Some people tried this hash
-and found that it worked rather well.  In an EMail message
-to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash.
-
-FNV hashes are designed to be fast while maintaining a low
-collision rate. The FNV speed allows one to quickly hash lots
-of data while maintaining a reasonable collision rate.  See:
-
-     http://www.isthe.com/chongo/tech/comp/fnv/index.html
-
-for more details as well as other forms of the FNV hash.
-Comments, questions, bug fixes and suggestions welcome at
-the address given in the above URL.
-
-
-#==================#
-# FNV hash utility #
-#==================#
-
-Two hash utilities (32 bit and 64 bit) are provided:
-
-	fnv032 [-b bcnt] [-m] [-s arg] [-t code] [-v] [arg ...]
-	fnv132 [-b bcnt] [-m] [-s arg] [-t code] [-v] [arg ...]
-	fnv1a32 [-b bcnt] [-m] [-s arg] [-t code] [-v] [arg ...]
-
-	fnv064 [-b bcnt] [-m] [-s arg] [-t code] [-v] [arg ...]
-	fnv164 [-b bcnt] [-m] [-s arg] [-t code] [-v] [arg ...]
-	fnv1a64 [-b bcnt] [-m] [-s arg] [-t code] [-v] [arg ...]
-
-	-b bcnt	  mask off all but the lower bcnt bits (default: 32)
- 	-m	  multiple hashes, one per line for each arg
-	-s	  hash arg as a string (ignoring terminating NUL bytes)
-	-t code	  0 ==> generate test vectors, 1 ==> test FNV hash
- 	-v	  verbose mode, print arg after hash (implies -m)
-	arg	  string (if -s was given) or filename (default stdin)
-
-The fnv032, fnv064 implement the historic FNV-0 hash.
-The fnv132, fnv164 implement the recommended FNV-1 hash.
-The fnv1a32, fnv1a64 implement the recommended FNV-1a hash.
-
-This is the original historic FNV algorithm with a 0 offset basis.
-It is recommended that FNV-1, with a non-0 offset basis be used instead.
-
-To test FNV hashes, try:
-
-	fnv032 -t 1 -v
-	fnv132 -t 1 -v
-	fnv1a32 -t 1 -v
-
-	fnv064 -t 1 -v
-	fnv164 -t 1 -v
-	fnv1a64 -t 1 -v
-
-If you are compiling, try:
-
-	make check
-
-
-#==================#
-# FNV hash library #
-#==================#
-
-The libfnv.a library implements both a 32 bit and a 64 bit FNV hash
-on collections of bytes, a NUL terminated strings or on an open file
-descriptor.
-
-Here is the 32 bit FNV 1 hash:
-
-	Fnv32_t fnv_32_buf(void *buf, int len, Fnv32_t hval);	/* byte buf */
-	Fnv32_t fnv_32_str(char *string, Fnv32_t hval);		/* string */
-
-Here is the 32 bit FNV 1a hash:
-
-	Fnv32_t fnv_32a_buf(void *buf, int len, Fnv32_t hval);	/* byte buf */
-	Fnv32_t fnv_32a_str(char *string, Fnv32_t hval);	/* string */
-
-Here is the 64 bit FNV 1 hash:
-
-	Fnv64_t fnv_64_buf(void *buf, int len, Fnv64_t hval);	/* byte buf */
-	Fnv64_t fnv_64_str(char *string, Fnv64_t hval);		/* string */
-
-Here is the 64 bit FNV 1a hash:
-
-	Fnv64_t fnv_64a_buf(void *buf, int len, Fnv64_t hval);	/* byte buf */
-	Fnv64_t fnv_64a_str(char *string, Fnv64_t hval);	/* string */
-
-On the first call to a hash function, one must supply the initial basis
-that is appropriate for the hash in question:
-
-    FNV-0:	(not recommended)
-
-	FNV0_32_INIT		/* 32 bit FNV-0 initial basis */
-	FNV0_64_INIT		/* 64 bit FNV-0 initial basis */
-
-    FNV-1:
-
-	FNV1_32_INIT		/* 32 bit FNV-1 initial basis */
-	FNV1_64_INIT		/* 64 bit FNV-1 initial basis */
-
-    FNV-1a:
-
-	FNV1A_32_INIT		/* 32 bit FNV-1a initial basis */
-	FNV1A_64_INIT		/* 64 bit FNV-1a initial basis */
-
-For example to perform a 64 bit FNV-1 hash:
-
-	#include "fnv.h"
-
-	Fnv64_t hash_val;
-
-	hash_val = fnv_64_str("a string", FNV1_64_INIT);
-	hash_val = fnv_64_str("more string", hash_val);
-
-produces the same final hash value as:
-
-	hash_val = fnv_64_str("a stringmore string", FNV1_64_INIT);
-
-NOTE: If one used 'FNV0_64_INIT' instead of 'FNV1_64_INIT' one would get the
-      historic FNV-0 hash instead recommended FNV-1 hash.
-
-To perform a 32 bit FNV-1 hash:
-
-	#include "fnv.h"
-
-	Fnv32_t hash_val;
-
-	hash_val = fnv_32_buf(buf, length_of_buf, FNV1_32_INIT);
-	hash_val = fnv_32_str("more data", hash_val);
-
-To perform a 64 bit FNV-1a hash:
-
-	#include "fnv.h"
-
-	Fnv64_t hash_val;
-
-	hash_val = fnv_64a_buf(buf, length_of_buf, FNV1_64_INIT);
-	hash_val = fnv_64a_str("more data", hash_val);
-
-=-=
-
-chongo <Landon Curt Noll> /\oo/\
-http://www.isthe.com/chongo
-
-Share and Enjoy!
diff --git a/lib/fnv/fnv.h b/lib/fnv/fnv.h
deleted file mode 100644
index 5249366731..0000000000
--- a/lib/fnv/fnv.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * fnv - Fowler/Noll/Vo- hash code
- *
- * @(#) $Revision: 5.4 $
- * @(#) $Id: fnv.h,v 5.4 2009/07/30 22:49:13 chongo Exp $
- * @(#) $Source: /usr/local/src/cmd/fnv/RCS/fnv.h,v $
- *
- ***
- *
- * Fowler/Noll/Vo- hash
- *
- * The basis of this hash algorithm was taken from an idea sent
- * as reviewer comments to the IEEE POSIX P1003.2 committee by:
- *
- *      Phong Vo (http://www.research.att.com/info/kpv/)
- *      Glenn Fowler (http://www.research.att.com/~gsf/)
- *
- * In a subsequent ballot round:
- *
- *      Landon Curt Noll (http://www.isthe.com/chongo/)
- *
- * improved on their algorithm.  Some people tried this hash
- * and found that it worked rather well.  In an EMail message
- * to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash.
- *
- * FNV hashes are designed to be fast while maintaining a low
- * collision rate. The FNV speed allows one to quickly hash lots
- * of data while maintaining a reasonable collision rate.  See:
- *
- *      http://www.isthe.com/chongo/tech/comp/fnv/index.html
- *
- * for more details as well as other forms of the FNV hash.
- *
- ***
- *
- * NOTE: The FNV-0 historic hash is not recommended.  One should use
- *	 the FNV-1 hash instead.
- *
- * To use the 32 bit FNV-0 historic hash, pass FNV0_32_INIT as the
- * Fnv32_t hashval argument to fnv_32_buf() or fnv_32_str().
- *
- * To use the 64 bit FNV-0 historic hash, pass FNV0_64_INIT as the
- * Fnv64_t hashval argument to fnv_64_buf() or fnv_64_str().
- *
- * To use the recommended 32 bit FNV-1 hash, pass FNV1_32_INIT as the
- * Fnv32_t hashval argument to fnv_32_buf() or fnv_32_str().
- *
- * To use the recommended 64 bit FNV-1 hash, pass FNV1_64_INIT as the
- * Fnv64_t hashval argument to fnv_64_buf() or fnv_64_str().
- *
- * To use the recommended 32 bit FNV-1a hash, pass FNV1_32A_INIT as the
- * Fnv32_t hashval argument to fnv_32a_buf() or fnv_32a_str().
- *
- * To use the recommended 64 bit FNV-1a hash, pass FNV1A_64_INIT as the
- * Fnv64_t hashval argument to fnv_64a_buf() or fnv_64a_str().
- *
- ***
- *
- * Please do not copyright this code.  This code is in the public domain.
- *
- * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * By:
- *	chongo <Landon Curt Noll> /\oo/\
- *      http://www.isthe.com/chongo/
- *
- * Share and Enjoy!	:-)
- */
-
-#if !defined(__FNV_H__)
-#define __FNV_H__
-
-#include <stdlib.h>
-#include <stdint.h>
-
-#define FNV_VERSION "5.0.2"	/* @(#) FNV Version */
-
-
-/*
- * 32 bit FNV-0 hash type
- */
-typedef uint32_t Fnv32_t;
-
-
-/*
- * 32 bit FNV-0 zero initial basis
- *
- * This historic hash is not recommended.  One should use
- * the FNV-1 hash and initial basis instead.
- */
-#define FNV0_32_INIT ((Fnv32_t)0)
-
-
-/*
- * 32 bit FNV-1 and FNV-1a non-zero initial basis
- *
- * The FNV-1 initial basis is the FNV-0 hash of the following 32 octets:
- *
- *              chongo <Landon Curt Noll> /\../\
- *
- * NOTE: The \'s above are not back-slashing escape characters.
- * They are literal ASCII  backslash 0x5c characters.
- *
- * NOTE: The FNV-1a initial basis is the same value as FNV-1 by definition.
- */
-#define FNV1_32_INIT ((Fnv32_t)0x811c9dc5)
-#define FNV1_32A_INIT FNV1_32_INIT
-
-
-/*
- * determine how 64 bit unsigned values are represented
- */
-#include "longlong.h"
-
-
-/*
- * 64 bit FNV-0 hash
- */
-#if defined(HAVE_64BIT_LONG_LONG)
-typedef uint64_t Fnv64_t;
-#else /* HAVE_64BIT_LONG_LONG */
-typedef struct {
-    uint32_t w32[2]; /* w32[0] is low order, w32[1] is high order word */
-} Fnv64_t;
-#endif /* HAVE_64BIT_LONG_LONG */
-
-
-/*
- * 64 bit FNV-0 zero initial basis
- *
- * This historic hash is not recommended.  One should use
- * the FNV-1 hash and initial basis instead.
- */
-#if defined(HAVE_64BIT_LONG_LONG)
-#define FNV0_64_INIT ((Fnv64_t)0)
-#else /* HAVE_64BIT_LONG_LONG */
-extern const Fnv64_t fnv0_64_init;
-#define FNV0_64_INIT (fnv0_64_init)
-#endif /* HAVE_64BIT_LONG_LONG */
-
-
-/*
- * 64 bit FNV-1 non-zero initial basis
- *
- * The FNV-1 initial basis is the FNV-0 hash of the following 32 octets:
- *
- *              chongo <Landon Curt Noll> /\../\
- *
- * NOTE: The \'s above are not back-slashing escape characters.
- * They are literal ASCII  backslash 0x5c characters.
- *
- * NOTE: The FNV-1a initial basis is the same value as FNV-1 by definition.
- */
-#if defined(HAVE_64BIT_LONG_LONG)
-#define FNV1_64_INIT ((Fnv64_t)0xcbf29ce484222325ULL)
-#define FNV1A_64_INIT FNV1_64_INIT
-#else /* HAVE_64BIT_LONG_LONG */
-extern const fnv1_64_init;
-extern const Fnv64_t fnv1a_64_init;
-#define FNV1_64_INIT (fnv1_64_init)
-#define FNV1A_64_INIT (fnv1a_64_init)
-#endif /* HAVE_64BIT_LONG_LONG */
-
-
-/*
- * hash types
- */
-enum fnv_type {
-    FNV_NONE = 0,	/* invalid FNV hash type */
-    FNV0_32 = 1,	/* FNV-0 32 bit hash */
-    FNV1_32 = 2,	/* FNV-1 32 bit hash */
-    FNV1a_32 = 3,	/* FNV-1a 32 bit hash */
-    FNV0_64 = 4,	/* FNV-0 64 bit hash */
-    FNV1_64 = 5,	/* FNV-1 64 bit hash */
-    FNV1a_64 = 6,	/* FNV-1a 64 bit hash */
-};
-
-
-/*
- * these test vectors are used as part o the FNV test suite
- */
-struct test_vector {
-    void *buf;		/* start of test vector buffer */
-    int len;		/* length of test vector */
-};
-struct fnv0_32_test_vector {
-    struct test_vector *test;	/* test vector buffer to hash */
-    Fnv32_t fnv0_32;		/* expected FNV-0 32 bit hash value */
-};
-struct fnv1_32_test_vector {
-    struct test_vector *test;	/* test vector buffer to hash */
-    Fnv32_t fnv1_32;		/* expected FNV-1 32 bit hash value */
-};
-struct fnv1a_32_test_vector {
-    struct test_vector *test;	/* test vector buffer to hash */
-    Fnv32_t fnv1a_32;		/* expected FNV-1a 32 bit hash value */
-};
-struct fnv0_64_test_vector {
-    struct test_vector *test;	/* test vector buffer to hash */
-    Fnv64_t fnv0_64;		/* expected FNV-0 64 bit hash value */
-};
-struct fnv1_64_test_vector {
-    struct test_vector *test;	/* test vector buffer to hash */
-    Fnv64_t fnv1_64;		/* expected FNV-1 64 bit hash value */
-};
-struct fnv1a_64_test_vector {
-    struct test_vector *test;	/* test vector buffer to hash */
-    Fnv64_t fnv1a_64;		/* expected FNV-1a 64 bit hash value */
-};
-
-
-/*
- * external functions
- */
-/* hash_32.c */
-extern Fnv32_t fnv_32_buf(void *buf, size_t len, Fnv32_t hashval);
-extern Fnv32_t fnv_32_str(char *buf, Fnv32_t hashval);
-
-/* hash_32a.c */
-extern Fnv32_t fnv_32a_buf(void *buf, size_t len, Fnv32_t hashval);
-extern Fnv32_t fnv_32a_str(char *buf, Fnv32_t hashval);
-
-/* hash_64.c */
-extern Fnv64_t fnv_64_buf(void *buf, size_t len, Fnv64_t hashval);
-extern Fnv64_t fnv_64_str(char *buf, Fnv64_t hashval);
-
-/* hash_64a.c */
-extern Fnv64_t fnv_64a_buf(void *buf, size_t len, Fnv64_t hashval);
-extern Fnv64_t fnv_64a_str(char *buf, Fnv64_t hashval);
-
-/* test_fnv.c */
-extern struct test_vector fnv_test_str[];
-extern struct fnv0_32_test_vector fnv0_32_vector[];
-extern struct fnv1_32_test_vector fnv1_32_vector[];
-extern struct fnv1a_32_test_vector fnv1a_32_vector[];
-extern struct fnv0_64_test_vector fnv0_64_vector[];
-extern struct fnv1_64_test_vector fnv1_64_vector[];
-extern struct fnv1a_64_test_vector fnv1a_64_vector[];
-extern void unknown_hash_type(char *prog, enum fnv_type type, int code);
-extern void print_fnv32(Fnv32_t hval, Fnv32_t mask, int verbose, char *arg);
-extern void print_fnv64(Fnv64_t hval, Fnv64_t mask, int verbose, char *arg);
-
-
-#endif /* __FNV_H__ */
diff --git a/lib/fnv/fnv32.c b/lib/fnv/fnv32.c
deleted file mode 100644
index 58c61f03fc..0000000000
--- a/lib/fnv/fnv32.c
+++ /dev/null
@@ -1,467 +0,0 @@
-/*
- * fnv32 - 32 bit Fowler/Noll/Vo hash of a buffer or string
- *
- * @(#) $Revision: 5.5 $
- * @(#) $Id: fnv32.c,v 5.5 2012/03/21 01:38:12 chongo Exp $
- * @(#) $Source: /usr/local/src/cmd/fnv/RCS/fnv32.c,v $
- *
- ***
- *
- * Fowler/Noll/Vo hash
- *
- * The basis of this hash algorithm was taken from an idea sent
- * as reviewer comments to the IEEE POSIX P1003.2 committee by:
- *
- *      Phong Vo (http://www.research.att.com/info/kpv/)
- *      Glenn Fowler (http://www.research.att.com/~gsf/)
- *
- * In a subsequent ballot round:
- *
- *      Landon Curt Noll (http://www.isthe.com/chongo/)
- *
- * improved on their algorithm.  Some people tried this hash
- * and found that it worked rather well.  In an EMail message
- * to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash.
- *
- * FNV hashes are designed to be fast while maintaining a low
- * collision rate. The FNV speed allows one to quickly hash lots
- * of data while maintaining a reasonable collision rate.  See:
- *
- *      http://www.isthe.com/chongo/tech/comp/fnv/index.html
- *
- * for more details as well as other forms of the FNV hash.
- *
- ***
- *
- * Please do not copyright this code.  This code is in the public domain.
- *
- * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * By:
- *	chongo <Landon Curt Noll> /\oo/\
- *      http://www.isthe.com/chongo/
- *
- * Share and Enjoy!	:-)
- */
-
-#include <stdio.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <string.h>
-#include "longlong.h"
-#include "fnv.h"
-
-#define WIDTH 32		/* bit width of hash */
-
-#define BUF_SIZE (32*1024)	/* number of bytes to hash at a time */
-
-static char *usage =
-"usage: %s [-b bcnt] [-m] [-s arg] [-t code] [-v] [arg ...]\n"
-"\n"
-"\t-b bcnt\tmask off all but the lower bcnt bits (default 32)\n"
-"\t-m\tmultiple hashes, one per line for each arg\n"
-"\t-s\thash arg as a string (ignoring terminating NUL bytes)\n"
-"\t-t code\t  test hash code: (0 ==> generate test vectors\n"
-"\t\t\t\t   1 ==> validate against FNV test vectors)\n"
-"\t-v\tverbose mode, print arg after hash (implies -m)\n"
-"\targ\tstring (if -s was given) or filename (default stdin)\n"
-"\n"
-"\tNOTE: Programs that begin with fnv0 implement the FNV-0 hash.\n"
-"\t      The FNV-0 hash is historic FNV algorithm that is now deprecated.\n"
-"\n"
-"\tSee http://www.isthe.com/chongo/tech/comp/fnv/index.html for more info.\n"
-"\n"
-"\t@(#) FNV Version: %s\n";
-static char *program;	/* our name */
-
-
-/*
- * test_fnv32 - test the FNV32 hash
- *
- * given:
- *	hash_type	type of FNV hash to test
- *	init_hval	initial hash value
- *	mask	  	lower bit mask
- *	v_flag	  	1 => print test failure info on stderr
- *	code	  0 ==> generate FNV test vectors
- *		  1 ==> validate against FNV test vectors
- *
- * returns:	0 ==> OK, else test vector failure number
- */
-static int
-test_fnv32(enum fnv_type hash_type, Fnv32_t init_hval,
-	   Fnv32_t mask, int v_flag, int code)
-{
-    struct test_vector *t;	/* FNV test vestor */
-    Fnv32_t hval;		/* current hash value */
-    int tstnum;			/* test vector that failed, starting at 1 */
-
-    /*
-     * print preamble if generating test vectors
-     */
-    if (code == 0) {
-	switch (hash_type) {
-	case FNV0_32:
-	    printf("struct fnv0_32_test_vector fnv0_32_vector[] = {\n");
-	    break;
-	case FNV1_32:
-	    printf("struct fnv1_32_test_vector fnv1_32_vector[] = {\n");
-	    break;
-	case FNV1a_32:
-	    printf("struct fnv1a_32_test_vector fnv1a_32_vector[] = {\n");
-	    break;
-	default:
-	    unknown_hash_type(program, hash_type, 12);	/* exit(12) */
-	    /*NOTREACHED*/
-    	}
-    }
-
-    /*
-     * loop thru all test vectors
-     */
-    for (t = fnv_test_str, tstnum = 1; t->buf != NULL; ++t, ++tstnum) {
-
-        /*
-	 * compute the FNV hash
-	 */
-	hval = init_hval;
-	switch (hash_type) {
-	case FNV0_32:
-	case FNV1_32:
-	    hval = fnv_32_buf(t->buf, t->len, hval);
-	    break;
-	case FNV1a_32:
-	    hval = fnv_32a_buf(t->buf, t->len, hval);
-	    break;
-	default:
-	    unknown_hash_type(program, hash_type, 13);	/* exit(13) */
-	    /*NOTREACHED*/
-	}
-
-	/*
-	 * print the vector
-	 */
-	switch (code) {
-	case 0:		/* generate the test vector */
-	    printf("    { &fnv_test_str[%d], (Fnv32_t) 0x%08lxUL },\n",
-	    	    tstnum-1, hval & mask);
-    	    break;
-	case 1:		/* validate against test vector */
-	    switch (hash_type) {
-	    case FNV0_32:
-		if ((hval&mask) != (fnv0_32_vector[tstnum-1].fnv0_32 & mask)) {
-		    if (v_flag) {
-		    	fprintf(stderr, "%s: failed fnv0_32 test # %d\n",
-				program, tstnum);
-		    	fprintf(stderr, "%s: test # 1 is 1st test\n", program);
-			fprintf(stderr,
-			    "%s: expected 0x%08lx != generated: 0x%08lx\n",
-			    program, (hval&mask),
-			    (fnv0_32_vector[tstnum-1].fnv0_32 & mask));
-		    }
-		    return tstnum;
-		}
-	    	break;
-	    case FNV1_32:
-		if ((hval&mask) != (fnv1_32_vector[tstnum-1].fnv1_32 & mask)) {
-		    if (v_flag) {
-		    	fprintf(stderr, "%s: failed fnv1_32 test # %d\n",
-				program, tstnum);
-		    	fprintf(stderr, "%s: test # 1 is 1st test\n", program);
-			fprintf(stderr,
-			    "%s: expected 0x%08lx != generated: 0x%08lx\n",
-			    program, (hval&mask),
-			    (fnv1_32_vector[tstnum-1].fnv1_32 & mask));
-		    }
-		    return tstnum;
-		}
-	    	break;
-	    case FNV1a_32:
-		if ((hval&mask) != (fnv1a_32_vector[tstnum-1].fnv1a_32 &mask)) {
-		    if (v_flag) {
-		    	fprintf(stderr, "%s: failed fnv1a_32 test # %d\n",
-				program, tstnum);
-		    	fprintf(stderr, "%s: test # 1 is 1st test\n", program);
-			fprintf(stderr,
-			    "%s: expected 0x%08lx != generated: 0x%08lx\n",
-			    program, (hval&mask),
-			    (fnv1a_32_vector[tstnum-1].fnv1a_32 & mask));
-		    }
-		    return tstnum;
-		}
-	    	break;
-	    }
-	    break;
-    	default:
-	    fprintf(stderr, "%s: -m %d not implemented yet\n", program, code);
-	    exit(14);
-    	}
-    }
-
-    /*
-     * print completion if generating test vectors
-     */
-    if (code == 0) {
-	printf("    { NULL, 0 }\n");
-	printf("};\n");
-    }
-
-    /*
-     * no failures, return code 0 ==> all OK
-     */
-    return 0;
-}
-
-
-/*
- * main - the main function
- *
- * See the above usage for details.
- */
-int
-main(int argc, char *argv[])
-{
-    char buf[BUF_SIZE+1];	/* read buffer */
-    int readcnt;		/* number of characters written */
-    Fnv32_t hval;		/* current hash value */
-    int s_flag = 0;		/* 1 => -s was given, hash args as strings */
-    int m_flag = 0;		/* 1 => print multiple hashes, one per arg */
-    int v_flag = 0;		/* 1 => verbose hash print */
-    int b_flag = WIDTH;		/* -b flag value */
-    int t_flag = -1;		/* FNV test vector code (0=>print, 1=>test) */
-    enum fnv_type hash_type = FNV_NONE;	/* type of FNV hash to perform */
-    Fnv32_t bmask;		/* mask to apply to output */
-    extern char *optarg;	/* option argument */
-    extern int optind;		/* argv index of the next arg */
-    int fd;			/* open file to process */
-    char *p;
-    int i;
-
-    /*
-     * parse args
-     */
-    program = argv[0];
-    while ((i = getopt(argc, argv, "b:mst:v")) != -1) {
-	switch (i) {
-	case 'b':	/* bcnt bit mask count */
-	    b_flag = atoi(optarg);
-	    break;
-	case 'm':	/* print multiple hashes, one per arg */
-	    m_flag = 1;
-	    break;
-	case 's':	/* hash args as strings */
-	    s_flag = 1;
-	    break;
-	case 't':	/* FNV test vector code */
-	    t_flag = atoi(optarg);
-	    if (t_flag < 0 || t_flag > 1) {
-		fprintf(stderr, "%s: -t code must be 0 or 1\n", program);
-		fprintf(stderr, usage, program, FNV_VERSION);
-		exit(1);
-	    }
-	    m_flag = 1;
-	    break;
-	case 'v':	/* verbose hash print */
-	    m_flag = 1;
-	    v_flag = 1;
-	    break;
-	default:
-	    fprintf(stderr, usage, program, FNV_VERSION);
-	    exit(1);
-	}
-    }
-    /* -t code incompatible with -b, -m and args */
-    if (t_flag >= 0) {
-    	if (b_flag != WIDTH) {
-	    fprintf(stderr, "%s: -t code incompatible with -b\n", program);
-	    exit(2);
-	}
-    	if (s_flag != 0) {
-	    fprintf(stderr, "%s: -t code incompatible with -s\n", program);
-	    exit(3);
-	}
-	if (optind < argc) {
-	    fprintf(stderr, "%s: -t code incompatible args\n", program);
-	    exit(4);
-	}
-    }
-    /* -s requires at least 1 arg */
-    if (s_flag && optind >= argc) {
-	fprintf(stderr, usage, program, FNV_VERSION);
-	exit(5);
-    }
-    /* limit -b values */
-    if (b_flag < 0 || b_flag > WIDTH) {
-	fprintf(stderr, "%s: -b bcnt: %d must be >= 0 and < %d\n",
-		program, b_flag, WIDTH);
-	exit(6);
-    }
-    if (b_flag == WIDTH) {
-	bmask = (Fnv32_t)0xffffffff;
-    } else {
-	bmask = (Fnv32_t)((1 << b_flag) - 1);
-    }
-
-    /*
-     * start with the initial basis depending on the hash type
-     */
-    p = strrchr(program, '/');
-    if (p == NULL) {
-	p = program;
-    } else {
-	++p;
-    }
-    if (strcmp(p, "fnv032") == 0) {
-	/* using non-recommended FNV-0 and zero initial basis */
-	hval = FNV0_32_INIT;
-	hash_type = FNV0_32;
-    } else if (strcmp(p, "fnv132") == 0) {
-	/* using FNV-1 and non-zero initial basis */
-	hval = FNV1_32_INIT;
-	hash_type = FNV1_32;
-    } else if (strcmp(p, "fnv1a32") == 0) {
-	 /* start with the FNV-1a initial basis */
-	hval = FNV1_32A_INIT;
-	hash_type = FNV1a_32;
-    } else {
-	fprintf(stderr, "%s: unknown program name, unknown hash type\n",
-		program);
-	exit(7);
-    }
-
-    /*
-     * FNV test vector processing, if needed
-     */
-    if (t_flag >= 0) {
-	int code;		/* test vector that failed, starting at 1 */
-
-	/*
-	 * perform all tests
-	 */
-	code = test_fnv32(hash_type, hval, bmask, v_flag, t_flag);
-
-	/*
-	 * evaluate the tests
-	 */
-	if (code == 0) {
-	    if (v_flag) {
-	    	printf("passed\n");
-	    }
-	    exit(0);
-	} else {
-	    printf("failed vector (1 is 1st test): %d\n", code);
-	    exit(8);
-	}
-    }
-
-    /*
-     * string hashing
-     */
-    if (s_flag) {
-
-	/* hash any other strings */
-	for (i=optind; i < argc; ++i) {
-	    switch (hash_type) {
-	    case FNV0_32:
-	    case FNV1_32:
-		hval = fnv_32_str(argv[i], hval);
-	    	break;
-	    case FNV1a_32:
-		hval = fnv_32a_str(argv[i], hval);
-		break;
-	    default:
-		unknown_hash_type(program, hash_type, 9);	/* exit(9) */
-		/*NOTREACHED*/
-	    }
-	    if (m_flag) {
-		print_fnv32(hval, bmask, v_flag, argv[i]);
-	    }
-	}
-
-
-    /*
-     * file hashing
-     */
-    } else {
-
-	/*
-	 * case: process only stdin
-	 */
-	if (optind >= argc) {
-
-	    /* case: process only stdin */
-	    while ((readcnt = read(0, buf, BUF_SIZE)) > 0) {
-		switch (hash_type) {
-		case FNV0_32:
-		case FNV1_32:
-		    hval = fnv_32_buf(buf, readcnt, hval);
-		    break;
-		case FNV1a_32:
-		    hval = fnv_32a_buf(buf, readcnt, hval);
-		    break;
-		default:
-		    unknown_hash_type(program, hash_type, 10);	/* exit(10) */
-		    /*NOTREACHED*/
-		}
-	    }
-	    if (m_flag) {
-		print_fnv32(hval, bmask, v_flag, "(stdin)");
-	    }
-
-	} else {
-
-	    /*
-	     * process any other files
-	     */
-	    for (i=optind; i < argc; ++i) {
-
-		/* open the file */
-		fd = open(argv[i], O_RDONLY);
-		if (fd < 0) {
-		    fprintf(stderr, "%s: unable to open file: %s\n",
-			    program, argv[i]);
-		    exit(4);
-		}
-
-		/*  hash the file */
-		while ((readcnt = read(fd, buf, BUF_SIZE)) > 0) {
-		    switch (hash_type) {
-		    case FNV0_32:
-		    case FNV1_32:
-			hval = fnv_32_buf(buf, readcnt, hval);
-			break;
-		    case FNV1a_32:
-			hval = fnv_32a_buf(buf, readcnt, hval);
-			break;
-		    default:
-			unknown_hash_type(program, hash_type, 11);/* exit(11) */
-			/*NOTREACHED*/
-		    }
-		}
-
-		/* finish processing the file */
-		if (m_flag) {
-		    print_fnv32(hval, bmask, v_flag, argv[i]);
-		}
-		close(fd);
-	    }
-	}
-    }
-
-    /*
-     * report hash and exit
-     */
-    if (!m_flag) {
-	print_fnv32(hval, bmask, v_flag, "");
-    }
-    return 0;	/* exit(0); */
-}
diff --git a/lib/fnv/fnv64.c b/lib/fnv/fnv64.c
deleted file mode 100644
index 0662d4d657..0000000000
--- a/lib/fnv/fnv64.c
+++ /dev/null
@@ -1,591 +0,0 @@
-/*
- * fnv_64 - 64 bit Fowler/Noll/Vo hash of a buffer or string
- *
- * @(#) $Revision: 5.5 $
- * @(#) $Id: fnv64.c,v 5.5 2012/03/21 01:38:12 chongo Exp $
- * @(#) $Source: /usr/local/src/cmd/fnv/RCS/fnv64.c,v $
- *
- ***
- *
- * Fowler/Noll/Vo hash
- *
- * The basis of this hash algorithm was taken from an idea sent
- * as reviewer comments to the IEEE POSIX P1003.2 committee by:
- *
- *      Phong Vo (http://www.research.att.com/info/kpv/)
- *      Glenn Fowler (http://www.research.att.com/~gsf/)
- *
- * In a subsequent ballot round:
- *
- *      Landon Curt Noll (http://www.isthe.com/chongo/)
- *
- * improved on their algorithm.  Some people tried this hash
- * and found that it worked rather well.  In an EMail message
- * to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash.
- *
- * FNV hashes are designed to be fast while maintaining a low
- * collision rate. The FNV speed allows one to quickly hash lots
- * of data while maintaining a reasonable collision rate.  See:
- *
- *      http://www.isthe.com/chongo/tech/comp/fnv/index.html
- *
- * for more details as well as other forms of the FNV hash.
- *
- ***
- *
- * Please do not copyright this code.  This code is in the public domain.
- *
- * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * By:
- *	chongo <Landon Curt Noll> /\oo/\
- *      http://www.isthe.com/chongo/
- *
- * Share and Enjoy!	:-)
- */
-
-#include <stdio.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <string.h>
-#include "longlong.h"
-#include "fnv.h"
-
-#define WIDTH 64	/* bit width of hash */
-
-#define BUF_SIZE (32*1024)	/* number of bytes to hash at a time */
-
-static char *usage =
-"usage: %s [-b bcnt] [-m] [-s arg] [-t code] [-v] [arg ...]\n"
-"\n"
-"\t-b bcnt\tmask off all but the lower bcnt bits (default 64)\n"
-"\t-m\tmultiple hashes, one per line for each arg\n"
-"\t-s\thash arg as a string (ignoring terminating NUL bytes)\n"
-"\t-t code\t  test hash code: (0 ==> generate test vectors\n"
-"\t\t\t\t   1 ==> validate against FNV test vectors)\n"
-"\t-v\tverbose mode, print arg after hash (implies -m)\n"
-"\targ\tstring (if -s was given) or filename (default stdin)\n"
-"\n"
-"\tNOTE: Programs that begin with fnv0 implement the FNV-0 hash.\n"
-"\t      The FNV-0 hash is historic FNV algorithm that is now deprecated.\n"
-"\n"
-"\tSee http://www.isthe.com/chongo/tech/comp/fnv/index.html for more info.\n"
-"\n"
-"\t@(#) FNV Version: %s\n";
-static char *program;	/* our name */
-
-
-/*
- * test_fnv64 - test the FNV64 hash
- *
- * given:
- *	hash_type	type of FNV hash to test
- *	init_hval	initial hash value
- *	mask	  	lower bit mask
- *	v_flag	  	1 => print test failure info on stderr
- *	code	  0 ==> generate FNV test vectors
- *		  1 ==> validate against FNV test vectors
- *
- * returns:	0 ==> OK, else test vector failure number
- */
-static int
-test_fnv64(enum fnv_type hash_type, Fnv64_t init_hval,
-	   Fnv64_t mask, int v_flag, int code)
-{
-    struct test_vector *t;	/* FNV test vestor */
-    Fnv64_t hval;		/* current hash value */
-    int tstnum;			/* test vector that failed, starting at 1 */
-
-    /*
-     * print preamble if generating test vectors
-     */
-    if (code == 0) {
-	switch (hash_type) {
-	case FNV0_64:
-	    printf("struct fnv0_64_test_vector fnv0_64_vector[] = {\n");
-	    break;
-	case FNV1_64:
-	    printf("struct fnv1_64_test_vector fnv1_64_vector[] = {\n");
-	    break;
-	case FNV1a_64:
-	    printf("struct fnv1a_64_test_vector fnv1a_64_vector[] = {\n");
-	    break;
-	default:
-	    unknown_hash_type(program, hash_type, 12);	/* exit(12) */
-	    /*NOTREACHED*/
-    	}
-    }
-
-    /*
-     * loop thru all test vectors
-     */
-    for (t = fnv_test_str, tstnum = 1; t->buf != NULL; ++t, ++tstnum) {
-
-        /*
-	 * compute the FNV hash
-	 */
-	hval = init_hval;
-	switch (hash_type) {
-	case FNV0_64:
-	case FNV1_64:
-	    hval = fnv_64_buf(t->buf, t->len, hval);
-	    break;
-	case FNV1a_64:
-	    hval = fnv_64a_buf(t->buf, t->len, hval);
-	    break;
-	default:
-	    unknown_hash_type(program, hash_type, 13);	/* exit(13) */
-	    /*NOTREACHED*/
-	}
-
-	/*
-	 * print the vector
-	 */
-#if defined(HAVE_64BIT_LONG_LONG)
-	/*
-	 * HAVE_64BIT_LONG_LONG testing
-	 */
-	switch (code) {
-	case 0:		/* generate the test vector */
-	    printf("    { &fnv_test_str[%d], (Fnv64_t) 0x%016llxULL },\n",
-	    	   tstnum-1, hval & mask);
-	    break;
-
-	case 1:		/* validate against test vector */
-	    switch (hash_type) {
-	    case FNV0_64:
-		if ((hval&mask) != (fnv0_64_vector[tstnum-1].fnv0_64 & mask)) {
-		    if (v_flag) {
-		    	fprintf(stderr, "%s: failed fnv0_64 test # %d\n",
-				program, tstnum);
-		    	fprintf(stderr, "%s: test # 1 is 1st test\n", program);
-			fprintf(stderr,
-			    "%s: expected 0x%016llx != generated: 0x%016llx\n",
-			    program,
-			    (hval&mask),
-			    (fnv0_64_vector[tstnum-1].fnv0_64 & mask));
-		    }
-		    return tstnum;
-		}
-	    	break;
-	    case FNV1_64:
-		if ((hval&mask) != (fnv1_64_vector[tstnum-1].fnv1_64 & mask)) {
-		    if (v_flag) {
-		    	fprintf(stderr, "%s: failed fnv1_64 test # %d\n",
-				program, tstnum);
-		    	fprintf(stderr, "%s: test # 1 is 1st test\n", program);
-			fprintf(stderr,
-			    "%s: expected 0x%016llx != generated: 0x%016llx\n",
-			    program,
-			    (hval&mask),
-			    (fnv1_64_vector[tstnum-1].fnv1_64 & mask));
-		    }
-		    return tstnum;
-		}
-	    	break;
-	    case FNV1a_64:
-		if ((hval&mask) != (fnv1a_64_vector[tstnum-1].fnv1a_64 &mask)) {
-		    if (v_flag) {
-		    	fprintf(stderr, "%s: failed fnv1a_64 test # %d\n",
-				program, tstnum);
-		    	fprintf(stderr, "%s: test # 1 is 1st test\n", program);
-			fprintf(stderr,
-			    "%s: expected 0x%016llx != generated: 0x%016llx\n",
-			    program,
-			    (hval&mask),
-			    (fnv1a_64_vector[tstnum-1].fnv1a_64 & mask));
-		    }
-		    return tstnum;
-		}
-	    	break;
-	    }
-	    break;
-
-    	default:
-	    fprintf(stderr, "%s: -m %d not implemented yet\n", program, code);
-	    exit(14);
-    	}
-#else /* HAVE_64BIT_LONG_LONG */
-	/*
-	 * non HAVE_64BIT_LONG_LONG testing
-	 */
-	switch (code) {
-	case 0:		/* generate the test vector */
-	    printf("    { &fnv_test_str[%d], "
-	    	   "(Fnv64_t) {0x%08lxUL, 0x%08lxUL} },\n",
-	    	   tstnum-1,
-		   (hval.w32[0] & mask.w32[0]),
-		   (hval.w32[1] & mask.w32[1]));
-	    break;
-
-	case 1:		/* validate against test vector */
-	    switch (hash_type) {
-	    case FNV0_64:
-		if (((hval.w32[0] & mask.w32[0]) !=
-		     (fnv0_64_vector[tstnum-1].fnv0_64.w32[0] &
-		      mask.w32[0])) &&
-		    ((hval.w32[1] & mask.w32[1]) !=
-		     (fnv0_64_vector[tstnum-1].fnv0_64.w32[1] &
-		      mask.w32[1]))) {
-		    if (v_flag) {
-		    	fprintf(stderr, "%s: failed fnv0_64 test # %d\n",
-				program, tstnum);
-		    	fprintf(stderr, "%s: test # 1 is 1st test\n", program);
-			fprintf(stderr,
-			    "%s: expected 0x%08llx%08llx != "
-			    "generated: 0x%08llx%08llx\n",
-			    program,
-			    (hval.w32[0] & mask.w32[0]),
-			    (hval.w32[1] & mask.w32[1]),
-			    ((fnv0_64_vector[tstnum-1].fnv0_64.w32[0] &
-			     mask.w32[0])),
-			    ((fnv0_64_vector[tstnum-1].fnv0_64.w32[1] &
-			     mask.w32[1])));
-		    }
-		    return tstnum;
-		}
-	    	break;
-	    case FNV1_64:
-		if (((hval.w32[0] & mask.w32[0]) !=
-		     (fnv1_64_vector[tstnum-1].fnv1_64.w32[0] &
-		      mask.w32[0])) &&
-		    ((hval.w32[1] & mask.w32[1]) !=
-		     (fnv1_64_vector[tstnum-1].fnv1_64.w32[1] &
-		      mask.w32[1]))) {
-		    if (v_flag) {
-		    	fprintf(stderr, "%s: failed fnv1_64 test # %d\n",
-				program, tstnum);
-		    	fprintf(stderr, "%s: test # 1 is 1st test\n", program);
-			fprintf(stderr,
-			    "%s: expected 0x%08llx%08llx != "
-			    "generated: 0x%08llx%08llx\n",
-			    program,
-			    (hval.w32[0] & mask.w32[0]),
-			    (hval.w32[1] & mask.w32[1]),
-			    ((fnv1_64_vector[tstnum-1].fnv1_64.w32[0] &
-			     mask.w32[0])),
-			    ((fnv1_64_vector[tstnum-1].fnv1_64.w32[1] &
-			     mask.w32[1])));
-		    }
-		    return tstnum;
-		}
-	    	break;
-	    case FNV1a_64:
-		if (((hval.w32[0] & mask.w32[0]) !=
-		     (fnv1a_64_vector[tstnum-1].fnv1a_64.w32[0] &
-		      mask.w32[0])) &&
-		    ((hval.w32[1] & mask.w32[1]) !=
-		     (fnv1a_64_vector[tstnum-1].fnv1a_64.w32[1] &
-		      mask.w32[1]))) {
-		    if (v_flag) {
-		    	fprintf(stderr, "%s: failed fnv1a_64 test # %d\n",
-				program, tstnum);
-		    	fprintf(stderr, "%s: test # 1 is 1st test\n", program);
-			fprintf(stderr,
-			    "%s: expected 0x%08llx%08llx != "
-			    "generated: 0x%08llx%08llx\n",
-			    program,
-			    (hval.w32[0] & mask.w32[0]),
-			    (hval.w32[1] & mask.w32[1]),
-			    ((fnv1a_64_vector[tstnum-1].fnv1a_64.w32[0] &
-			     mask.w32[0])),
-			    ((fnv1a_64_vector[tstnum-1].fnv1a_64.w32[1] &
-			     mask.w32[1])));
-		    }
-		    return tstnum;
-		}
-	    	break;
-	    }
-	    break;
-
-    	default:
-	    fprintf(stderr, "%s: -m %d not implemented yet\n", program, code);
-	    exit(15);
-    	}
-#endif /* HAVE_64BIT_LONG_LONG */
-    }
-
-    /*
-     * print completion if generating test vectors
-     */
-    if (code == 0) {
-#if defined(HAVE_64BIT_LONG_LONG)
-	printf("    { NULL, (Fnv64_t) 0 }\n");
-#else /* HAVE_64BIT_LONG_LONG */
-	printf("    { NULL, (Fnv64_t) {0,0} }\n");
-#endif /* HAVE_64BIT_LONG_LONG */
-	printf("};\n");
-    }
-
-    /*
-     * no failures, return code 0 ==> all OK
-     */
-    return 0;
-}
-
-
-/*
- * main - the main function
- *
- * See the above usage for details.
- */
-int
-main(int argc, char *argv[])
-{
-    char buf[BUF_SIZE+1];	/* read buffer */
-    int readcnt;		/* number of characters written */
-    Fnv64_t hval;		/* current hash value */
-    int s_flag = 0;		/* 1 => -s was given, hash args as strings */
-    int m_flag = 0;		/* 1 => print multiple hashes, one per arg */
-    int v_flag = 0;		/* 1 => verbose hash print */
-    int b_flag = WIDTH;		/* -b flag value */
-    int t_flag = -1;		/* FNV test vector code (0=>print, 1=>test) */
-    enum fnv_type hash_type = FNV_NONE;	/* type of FNV hash to perform */
-    Fnv64_t bmask;		/* mask to apply to output */
-    extern char *optarg;	/* option argument */
-    extern int optind;		/* argv index of the next arg */
-    int fd;			/* open file to process */
-    char *p;
-    int i;
-
-    /*
-     * parse args
-     */
-    program = argv[0];
-    while ((i = getopt(argc, argv, "b:mst:v")) != -1) {
-	switch (i) {
-	case 'b':	/* bcnt bit mask count */
-	    b_flag = atoi(optarg);
-	    break;
-	case 'm':	/* print multiple hashes, one per arg */
-	    m_flag = 1;
-	    break;
-	case 's':	/* hash args as strings */
-	    s_flag = 1;
-	    break;
-	case 't':	/* FNV test vector code */
-	    t_flag = atoi(optarg);
-	    if (t_flag < 0 || t_flag > 1) {
-		fprintf(stderr, "%s: -t code must be 0 or 1\n", program);
-		fprintf(stderr, usage, program, FNV_VERSION);
-		exit(1);
-	    }
-	    m_flag = 1;
-	    break;
-	case 'v':	/* verbose hash print */
-	    m_flag = 1;
-	    v_flag = 1;
-	    break;
-	default:
-	    fprintf(stderr, usage, program, FNV_VERSION);
-	    exit(1);
-	}
-    }
-    /* -t code incompatible with -b, -m and args */
-    if (t_flag >= 0) {
-    	if (b_flag != WIDTH) {
-	    fprintf(stderr, "%s: -t code incompatible with -b\n", program);
-	    exit(2);
-	}
-    	if (s_flag != 0) {
-	    fprintf(stderr, "%s: -t code incompatible with -s\n", program);
-	    exit(3);
-	}
-	if (optind < argc) {
-	    fprintf(stderr, "%s: -t code incompatible args\n", program);
-	    exit(4);
-	}
-    }
-    /* -s requires at least 1 arg */
-    if (s_flag && optind >= argc) {
-	fprintf(stderr, usage, program, FNV_VERSION);
-	exit(5);
-    }
-    /* limit -b values */
-    if (b_flag < 0 || b_flag > WIDTH) {
-	fprintf(stderr, "%s: -b bcnt: %d must be >= 0 and < %d\n",
-		program, b_flag, WIDTH);
-	exit(6);
-    }
-#if defined(HAVE_64BIT_LONG_LONG)
-    if (b_flag == WIDTH) {
-	bmask = (Fnv64_t)0xffffffffffffffffULL;
-    } else {
-	bmask = (Fnv64_t)((1ULL << b_flag) - 1ULL);
-    }
-#else /* HAVE_64BIT_LONG_LONG */
-    if (b_flag == WIDTH) {
-	bmask.w32[0] = 0xffffffffUL;
-	bmask.w32[1] = 0xffffffffUL;
-    } else if (b_flag >= WIDTH/2) {
-	bmask.w32[0] = 0xffffffffUL;
-	bmask.w32[1] = ((1UL << (b_flag-(WIDTH/2))) - 1UL);
-    } else {
-	bmask.w32[0] = ((1UL << b_flag) - 1UL);
-	bmask.w32[1] = 0UL;
-    }
-#endif /* HAVE_64BIT_LONG_LONG */
-
-    /*
-     * start with the initial basis depending on the hash type
-     */
-    p = strrchr(program, '/');
-    if (p == NULL) {
-	p = program;
-    } else {
-	++p;
-    }
-    if (strcmp(p, "fnv064") == 0 || strcmp(p, "no64bit_fnv064") == 0) {
-	/* using non-recommended FNV-0 and zero initial basis */
-	hval = FNV0_64_INIT;
-	hash_type = FNV0_64;
-    } else if (strcmp(p, "fnv164") == 0 || strcmp(p, "no64bit_fnv164") == 0) {
-	/* using FNV-1 and non-zero initial basis */
-	hval = FNV1_64_INIT;
-	hash_type = FNV1_64;
-    } else if (strcmp(p, "fnv1a64") == 0 || strcmp(p, "no64bit_fnv1a64") == 0) {
-	 /* start with the FNV-1a initial basis */
-	hval = FNV1A_64_INIT;
-	hash_type = FNV1a_64;
-    } else {
-	fprintf(stderr, "%s: unknown program name, unknown hash type\n",
-		program);
-	exit(7);
-    }
-
-    /*
-     * FNV test vector processing, if needed
-     */
-    if (t_flag >= 0) {
-	int code;		/* test vector that failed, starting at 1 */
-
-	/*
-	 * perform all tests
-	 */
-	code = test_fnv64(hash_type, hval, bmask, v_flag, t_flag);
-
-	/*
-	 * evaluate the tests
-	 */
-	if (code == 0) {
-	    if (v_flag) {
-	    	printf("passed\n");
-	    }
-	    exit(0);
-	} else {
-	    printf("failed vector (1 is 1st test): %d\n", code);
-	    exit(8);
-	}
-    }
-
-    /*
-     * string hashing
-     */
-    if (s_flag) {
-
-	/* hash any other strings */
-	for (i=optind; i < argc; ++i) {
-	    switch (hash_type) {
-	    case FNV0_64:
-	    case FNV1_64:
-		hval = fnv_64_str(argv[i], hval);
-	    	break;
-	    case FNV1a_64:
-		hval = fnv_64a_str(argv[i], hval);
-		break;
-	    default:
-		unknown_hash_type(program, hash_type, 9);	/* exit(9) */
-		/*NOTREACHED*/
-	    }
-	    if (m_flag) {
-		print_fnv64(hval, bmask, v_flag, argv[i]);
-	    }
-	}
-
-
-    /*
-     * file hashing
-     */
-    } else {
-
-	/*
-	 * case: process only stdin
-	 */
-	if (optind >= argc) {
-
-	    /* case: process only stdin */
-	    while ((readcnt = read(0, buf, BUF_SIZE)) > 0) {
-		switch (hash_type) {
-		case FNV0_64:
-		case FNV1_64:
-		    hval = fnv_64_buf(buf, readcnt, hval);
-		    break;
-		case FNV1a_64:
-		    hval = fnv_64a_buf(buf, readcnt, hval);
-		    break;
-		default:
-		    unknown_hash_type(program, hash_type, 10);	/* exit(10) */
-		    /*NOTREACHED*/
-		}
-	    }
-	    if (m_flag) {
-		print_fnv64(hval, bmask, v_flag, "(stdin)");
-	    }
-
-	} else {
-
-	    /*
-	     * process any other files
-	     */
-	    for (i=optind; i < argc; ++i) {
-
-		/* open the file */
-		fd = open(argv[i], O_RDONLY);
-		if (fd < 0) {
-		    fprintf(stderr, "%s: unable to open file: %s\n",
-			    program, argv[i]);
-		    exit(4);
-		}
-
-		/*  hash the file */
-		while ((readcnt = read(fd, buf, BUF_SIZE)) > 0) {
-		    switch (hash_type) {
-		    case FNV0_64:
-		    case FNV1_64:
-			hval = fnv_64_buf(buf, readcnt, hval);
-			break;
-		    case FNV1a_64:
-			hval = fnv_64a_buf(buf, readcnt, hval);
-			break;
-		    default:
-			unknown_hash_type(program, hash_type, 11);/* exit(11) */
-			/*NOTREACHED*/
-		    }
-		}
-
-		/* finish processing the file */
-		if (m_flag) {
-		    print_fnv64(hval, bmask, v_flag, argv[i]);
-		}
-		close(fd);
-	    }
-	}
-    }
-
-    /*
-     * report hash and exit
-     */
-    if (!m_flag) {
-	print_fnv64(hval, bmask, v_flag, "");
-    }
-    return 0;	/* exit(0); */
-}
diff --git a/lib/fnv/hash_32.c b/lib/fnv/hash_32.c
deleted file mode 100644
index 077170ff6d..0000000000
--- a/lib/fnv/hash_32.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * hash_32 - 32 bit Fowler/Noll/Vo hash code
- *
- * @(#) $Revision: 5.1 $
- * @(#) $Id: hash_32.c,v 5.1 2009/06/30 09:13:32 chongo Exp $
- * @(#) $Source: /usr/local/src/cmd/fnv/RCS/hash_32.c,v $
- *
- ***
- *
- * Fowler/Noll/Vo hash
- *
- * The basis of this hash algorithm was taken from an idea sent
- * as reviewer comments to the IEEE POSIX P1003.2 committee by:
- *
- *      Phong Vo (http://www.research.att.com/info/kpv/)
- *      Glenn Fowler (http://www.research.att.com/~gsf/)
- *
- * In a subsequent ballot round:
- *
- *      Landon Curt Noll (http://www.isthe.com/chongo/)
- *
- * improved on their algorithm.  Some people tried this hash
- * and found that it worked rather well.  In an EMail message
- * to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash.
- *
- * FNV hashes are designed to be fast while maintaining a low
- * collision rate. The FNV speed allows one to quickly hash lots
- * of data while maintaining a reasonable collision rate.  See:
- *
- *      http://www.isthe.com/chongo/tech/comp/fnv/index.html
- *
- * for more details as well as other forms of the FNV hash.
- ***
- *
- * NOTE: The FNV-0 historic hash is not recommended.  One should use
- *	 the FNV-1 hash instead.
- *
- * To use the 32 bit FNV-0 historic hash, pass FNV0_32_INIT as the
- * Fnv32_t hashval argument to fnv_32_buf() or fnv_32_str().
- *
- * To use the recommended 32 bit FNV-1 hash, pass FNV1_32_INIT as the
- * Fnv32_t hashval argument to fnv_32_buf() or fnv_32_str().
- *
- ***
- *
- * Please do not copyright this code.  This code is in the public domain.
- *
- * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * By:
- *	chongo <Landon Curt Noll> /\oo/\
- *      http://www.isthe.com/chongo/
- *
- * Share and Enjoy!	:-)
- */
-
-#include <stdlib.h>
-#include "fnv.h"
-
-
-/*
- * 32 bit magic FNV-0 and FNV-1 prime
- */
-#define FNV_32_PRIME ((Fnv32_t)0x01000193)
-
-
-/*
- * fnv_32_buf - perform a 32 bit Fowler/Noll/Vo hash on a buffer
- *
- * input:
- *	buf	- start of buffer to hash
- *	len	- length of buffer in octets
- *	hval	- previous hash value or 0 if first call
- *
- * returns:
- *	32 bit hash as a static hash type
- *
- * NOTE: To use the 32 bit FNV-0 historic hash, use FNV0_32_INIT as the hval
- *	 argument on the first call to either fnv_32_buf() or fnv_32_str().
- *
- * NOTE: To use the recommended 32 bit FNV-1 hash, use FNV1_32_INIT as the hval
- *	 argument on the first call to either fnv_32_buf() or fnv_32_str().
- */
-Fnv32_t
-fnv_32_buf(void *buf, size_t len, Fnv32_t hval)
-{
-    unsigned char *bp = (unsigned char *)buf;	/* start of buffer */
-    unsigned char *be = bp + len;		/* beyond end of buffer */
-
-    /*
-     * FNV-1 hash each octet in the buffer
-     */
-    while (bp < be) {
-
-	/* multiply by the 32 bit FNV magic prime mod 2^32 */
-#if defined(NO_FNV_GCC_OPTIMIZATION)
-	hval *= FNV_32_PRIME;
-#else
-	hval += (hval<<1) + (hval<<4) + (hval<<7) + (hval<<8) + (hval<<24);
-#endif
-
-	/* xor the bottom with the current octet */
-	hval ^= (Fnv32_t)*bp++;
-    }
-
-    /* return our new hash value */
-    return hval;
-}
-
-
-/*
- * fnv_32_str - perform a 32 bit Fowler/Noll/Vo hash on a string
- *
- * input:
- *	str	- string to hash
- *	hval	- previous hash value or 0 if first call
- *
- * returns:
- *	32 bit hash as a static hash type
- *
- * NOTE: To use the 32 bit FNV-0 historic hash, use FNV0_32_INIT as the hval
- *	 argument on the first call to either fnv_32_buf() or fnv_32_str().
- *
- * NOTE: To use the recommended 32 bit FNV-1 hash, use FNV1_32_INIT as the hval
- *	 argument on the first call to either fnv_32_buf() or fnv_32_str().
- */
-Fnv32_t
-fnv_32_str(char *str, Fnv32_t hval)
-{
-    unsigned char *s = (unsigned char *)str;	/* unsigned string */
-
-    /*
-     * FNV-1 hash each octet in the buffer
-     */
-    while (*s) {
-
-	/* multiply by the 32 bit FNV magic prime mod 2^32 */
-#if defined(NO_FNV_GCC_OPTIMIZATION)
-	hval *= FNV_32_PRIME;
-#else
-	hval += (hval<<1) + (hval<<4) + (hval<<7) + (hval<<8) + (hval<<24);
-#endif
-
-	/* xor the bottom with the current octet */
-	hval ^= (Fnv32_t)*s++;
-    }
-
-    /* return our new hash value */
-    return hval;
-}
diff --git a/lib/fnv/hash_32a.c b/lib/fnv/hash_32a.c
deleted file mode 100644
index 8b10acf3e2..0000000000
--- a/lib/fnv/hash_32a.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * hash_32 - 32 bit Fowler/Noll/Vo FNV-1a hash code
- *
- * @(#) $Revision: 5.1 $
- * @(#) $Id: hash_32a.c,v 5.1 2009/06/30 09:13:32 chongo Exp $
- * @(#) $Source: /usr/local/src/cmd/fnv/RCS/hash_32a.c,v $
- *
- ***
- *
- * Fowler/Noll/Vo hash
- *
- * The basis of this hash algorithm was taken from an idea sent
- * as reviewer comments to the IEEE POSIX P1003.2 committee by:
- *
- *      Phong Vo (http://www.research.att.com/info/kpv/)
- *      Glenn Fowler (http://www.research.att.com/~gsf/)
- *
- * In a subsequent ballot round:
- *
- *      Landon Curt Noll (http://www.isthe.com/chongo/)
- *
- * improved on their algorithm.  Some people tried this hash
- * and found that it worked rather well.  In an EMail message
- * to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash.
- *
- * FNV hashes are designed to be fast while maintaining a low
- * collision rate. The FNV speed allows one to quickly hash lots
- * of data while maintaining a reasonable collision rate.  See:
- *
- *      http://www.isthe.com/chongo/tech/comp/fnv/index.html
- *
- * for more details as well as other forms of the FNV hash.
- ***
- *
- * To use the recommended 32 bit FNV-1a hash, pass FNV1_32A_INIT as the
- * Fnv32_t hashval argument to fnv_32a_buf() or fnv_32a_str().
- *
- ***
- *
- * Please do not copyright this code.  This code is in the public domain.
- *
- * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * By:
- *	chongo <Landon Curt Noll> /\oo/\
- *      http://www.isthe.com/chongo/
- *
- * Share and Enjoy!	:-)
- */
-
-#include <stdlib.h>
-#include "fnv.h"
-
-
-/*
- * 32 bit magic FNV-1a prime
- */
-#define FNV_32_PRIME ((Fnv32_t)0x01000193)
-
-
-/*
- * fnv_32a_buf - perform a 32 bit Fowler/Noll/Vo FNV-1a hash on a buffer
- *
- * input:
- *	buf	- start of buffer to hash
- *	len	- length of buffer in octets
- *	hval	- previous hash value or 0 if first call
- *
- * returns:
- *	32 bit hash as a static hash type
- *
- * NOTE: To use the recommended 32 bit FNV-1a hash, use FNV1_32A_INIT as the
- * 	 hval arg on the first call to either fnv_32a_buf() or fnv_32a_str().
- */
-Fnv32_t
-fnv_32a_buf(void *buf, size_t len, Fnv32_t hval)
-{
-    unsigned char *bp = (unsigned char *)buf;	/* start of buffer */
-    unsigned char *be = bp + len;		/* beyond end of buffer */
-
-    /*
-     * FNV-1a hash each octet in the buffer
-     */
-    while (bp < be) {
-
-	/* xor the bottom with the current octet */
-	hval ^= (Fnv32_t)*bp++;
-
-	/* multiply by the 32 bit FNV magic prime mod 2^32 */
-#if defined(NO_FNV_GCC_OPTIMIZATION)
-	hval *= FNV_32_PRIME;
-#else
-	hval += (hval<<1) + (hval<<4) + (hval<<7) + (hval<<8) + (hval<<24);
-#endif
-    }
-
-    /* return our new hash value */
-    return hval;
-}
-
-
-/*
- * fnv_32a_str - perform a 32 bit Fowler/Noll/Vo FNV-1a hash on a string
- *
- * input:
- *	str	- string to hash
- *	hval	- previous hash value or 0 if first call
- *
- * returns:
- *	32 bit hash as a static hash type
- *
- * NOTE: To use the recommended 32 bit FNV-1a hash, use FNV1_32A_INIT as the
- *  	 hval arg on the first call to either fnv_32a_buf() or fnv_32a_str().
- */
-Fnv32_t
-fnv_32a_str(char *str, Fnv32_t hval)
-{
-    unsigned char *s = (unsigned char *)str;	/* unsigned string */
-
-    /*
-     * FNV-1a hash each octet in the buffer
-     */
-    while (*s) {
-
-	/* xor the bottom with the current octet */
-	hval ^= (Fnv32_t)*s++;
-
-	/* multiply by the 32 bit FNV magic prime mod 2^32 */
-#if defined(NO_FNV_GCC_OPTIMIZATION)
-	hval *= FNV_32_PRIME;
-#else
-	hval += (hval<<1) + (hval<<4) + (hval<<7) + (hval<<8) + (hval<<24);
-#endif
-    }
-
-    /* return our new hash value */
-    return hval;
-}
diff --git a/lib/fnv/hash_64.c b/lib/fnv/hash_64.c
deleted file mode 100644
index 4338605dca..0000000000
--- a/lib/fnv/hash_64.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * hash_64 - 64 bit Fowler/Noll/Vo-0 hash code
- *
- * @(#) $Revision: 5.1 $
- * @(#) $Id: hash_64.c,v 5.1 2009/06/30 09:01:38 chongo Exp $
- * @(#) $Source: /usr/local/src/cmd/fnv/RCS/hash_64.c,v $
- *
- ***
- *
- * Fowler/Noll/Vo hash
- *
- * The basis of this hash algorithm was taken from an idea sent
- * as reviewer comments to the IEEE POSIX P1003.2 committee by:
- *
- *      Phong Vo (http://www.research.att.com/info/kpv/)
- *      Glenn Fowler (http://www.research.att.com/~gsf/)
- *
- * In a subsequent ballot round:
- *
- *      Landon Curt Noll (http://www.isthe.com/chongo/)
- *
- * improved on their algorithm.  Some people tried this hash
- * and found that it worked rather well.  In an EMail message
- * to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash.
- *
- * FNV hashes are designed to be fast while maintaining a low
- * collision rate. The FNV speed allows one to quickly hash lots
- * of data while maintaining a reasonable collision rate.  See:
- *
- *      http://www.isthe.com/chongo/tech/comp/fnv/index.html
- *
- * for more details as well as other forms of the FNV hash.
- *
- ***
- *
- * NOTE: The FNV-0 historic hash is not recommended.  One should use
- *	 the FNV-1 hash instead.
- *
- * To use the 64 bit FNV-0 historic hash, pass FNV0_64_INIT as the
- * Fnv64_t hashval argument to fnv_64_buf() or fnv_64_str().
- *
- * To use the recommended 64 bit FNV-1 hash, pass FNV1_64_INIT as the
- * Fnv64_t hashval argument to fnv_64_buf() or fnv_64_str().
- *
- ***
- *
- * Please do not copyright this code.  This code is in the public domain.
- *
- * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * By:
- *	chongo <Landon Curt Noll> /\oo/\
- *      http://www.isthe.com/chongo/
- *
- * Share and Enjoy!	:-)
- */
-
-#include <stdlib.h>
-#include "fnv.h"
-
-
-/*
- * FNV-0 defines the initial basis to be zero
- */
-#if !defined(HAVE_64BIT_LONG_LONG)
-const Fnv64_t fnv0_64_init = { 0UL, 0UL };
-#endif /* ! HAVE_64BIT_LONG_LONG */
-
-
-/*
- * FNV-1 defines the initial basis to be non-zero
- */
-#if !defined(HAVE_64BIT_LONG_LONG)
-const Fnv64_t fnv1_64_init = { 0x84222325UL, 0xcbf29ce4UL };
-#endif /* ! HAVE_64BIT_LONG_LONG */
-
-
-/*
- * 64 bit magic FNV-0 and FNV-1 prime
- */
-#if defined(HAVE_64BIT_LONG_LONG)
-#define FNV_64_PRIME ((Fnv64_t)0x100000001b3ULL)
-#else /* HAVE_64BIT_LONG_LONG */
-#define FNV_64_PRIME_LOW ((unsigned long)0x1b3)	/* lower bits of FNV prime */
-#define FNV_64_PRIME_SHIFT (8)		/* top FNV prime shift above 2^32 */
-#endif /* HAVE_64BIT_LONG_LONG */
-
-
-/*
- * fnv_64_buf - perform a 64 bit Fowler/Noll/Vo hash on a buffer
- *
- * input:
- *	buf	- start of buffer to hash
- *	len	- length of buffer in octets
- *	hval	- previous hash value or 0 if first call
- *
- * returns:
- *	64 bit hash as a static hash type
- *
- * NOTE: To use the 64 bit FNV-0 historic hash, use FNV0_64_INIT as the hval
- *	 argument on the first call to either fnv_64_buf() or fnv_64_str().
- *
- * NOTE: To use the recommended 64 bit FNV-1 hash, use FNV1_64_INIT as the hval
- *	 argument on the first call to either fnv_64_buf() or fnv_64_str().
- */
-Fnv64_t
-fnv_64_buf(void *buf, size_t len, Fnv64_t hval)
-{
-    unsigned char *bp = (unsigned char *)buf;	/* start of buffer */
-    unsigned char *be = bp + len;		/* beyond end of buffer */
-
-#if defined(HAVE_64BIT_LONG_LONG)
-
-    /*
-     * FNV-1 hash each octet of the buffer
-     */
-    while (bp < be) {
-
-	/* multiply by the 64 bit FNV magic prime mod 2^64 */
-#if defined(NO_FNV_GCC_OPTIMIZATION)
-	hval *= FNV_64_PRIME;
-#else /* NO_FNV_GCC_OPTIMIZATION */
-	hval += (hval << 1) + (hval << 4) + (hval << 5) +
-		(hval << 7) + (hval << 8) + (hval << 40);
-#endif /* NO_FNV_GCC_OPTIMIZATION */
-
-	/* xor the bottom with the current octet */
-	hval ^= (Fnv64_t)*bp++;
-    }
-
-#else /* HAVE_64BIT_LONG_LONG */
-
-    unsigned long val[4];			/* hash value in base 2^16 */
-    unsigned long tmp[4];			/* tmp 64 bit value */
-
-    /*
-     * Convert Fnv64_t hval into a base 2^16 array
-     */
-    val[0] = hval.w32[0];
-    val[1] = (val[0] >> 16);
-    val[0] &= 0xffff;
-    val[2] = hval.w32[1];
-    val[3] = (val[2] >> 16);
-    val[2] &= 0xffff;
-
-    /*
-     * FNV-1 hash each octet of the buffer
-     */
-    while (bp < be) {
-
-	/*
-	 * multiply by the 64 bit FNV magic prime mod 2^64
-	 *
-	 * Using 0x100000001b3 we have the following digits base 2^16:
-	 *
-	 *	0x0	0x100	0x0	0x1b3
-	 *
-	 * which is the same as:
-	 *
-	 *	0x0	1<<FNV_64_PRIME_SHIFT	0x0	FNV_64_PRIME_LOW
-	 */
-	/* multiply by the lowest order digit base 2^16 */
-	tmp[0] = val[0] * FNV_64_PRIME_LOW;
-	tmp[1] = val[1] * FNV_64_PRIME_LOW;
-	tmp[2] = val[2] * FNV_64_PRIME_LOW;
-	tmp[3] = val[3] * FNV_64_PRIME_LOW;
-	/* multiply by the other non-zero digit */
-	tmp[2] += val[0] << FNV_64_PRIME_SHIFT;	/* tmp[2] += val[0] * 0x100 */
-	tmp[3] += val[1] << FNV_64_PRIME_SHIFT;	/* tmp[3] += val[1] * 0x100 */
-	/* propagate carries */
-	tmp[1] += (tmp[0] >> 16);
-	val[0] = tmp[0] & 0xffff;
-	tmp[2] += (tmp[1] >> 16);
-	val[1] = tmp[1] & 0xffff;
-	val[3] = tmp[3] + (tmp[2] >> 16);
-	val[2] = tmp[2] & 0xffff;
-	/*
-	 * Doing a val[3] &= 0xffff; is not really needed since it simply
-	 * removes multiples of 2^64.  We can discard these excess bits
-	 * outside of the loop when we convert to Fnv64_t.
-	 */
-
-	/* xor the bottom with the current octet */
-	val[0] ^= (unsigned long)*bp++;
-    }
-
-    /*
-     * Convert base 2^16 array back into an Fnv64_t
-     */
-    hval.w32[1] = ((val[3]<<16) | val[2]);
-    hval.w32[0] = ((val[1]<<16) | val[0]);
-
-#endif /* HAVE_64BIT_LONG_LONG */
-
-    /* return our new hash value */
-    return hval;
-}
-
-
-/*
- * fnv_64_str - perform a 64 bit Fowler/Noll/Vo hash on a buffer
- *
- * input:
- *	buf	- start of buffer to hash
- *	hval	- previous hash value or 0 if first call
- *
- * returns:
- *	64 bit hash as a static hash type
- *
- * NOTE: To use the 64 bit FNV-0 historic hash, use FNV0_64_INIT as the hval
- *	 argument on the first call to either fnv_64_buf() or fnv_64_str().
- *
- * NOTE: To use the recommended 64 bit FNV-1 hash, use FNV1_64_INIT as the hval
- *	 argument on the first call to either fnv_64_buf() or fnv_64_str().
- */
-Fnv64_t
-fnv_64_str(char *str, Fnv64_t hval)
-{
-    unsigned char *s = (unsigned char *)str;	/* unsigned string */
-
-#if defined(HAVE_64BIT_LONG_LONG)
-
-    /*
-     * FNV-1 hash each octet of the string
-     */
-    while (*s) {
-
-	/* multiply by the 64 bit FNV magic prime mod 2^64 */
-#if defined(NO_FNV_GCC_OPTIMIZATION)
-	hval *= FNV_64_PRIME;
-#else /* NO_FNV_GCC_OPTIMIZATION */
-	hval += (hval << 1) + (hval << 4) + (hval << 5) +
-		(hval << 7) + (hval << 8) + (hval << 40);
-#endif /* NO_FNV_GCC_OPTIMIZATION */
-
-	/* xor the bottom with the current octet */
-	hval ^= (Fnv64_t)*s++;
-    }
-
-#else /* !HAVE_64BIT_LONG_LONG */
-
-    unsigned long val[4];	/* hash value in base 2^16 */
-    unsigned long tmp[4];	/* tmp 64 bit value */
-
-    /*
-     * Convert Fnv64_t hval into a base 2^16 array
-     */
-    val[0] = hval.w32[0];
-    val[1] = (val[0] >> 16);
-    val[0] &= 0xffff;
-    val[2] = hval.w32[1];
-    val[3] = (val[2] >> 16);
-    val[2] &= 0xffff;
-
-    /*
-     * FNV-1 hash each octet of the string
-     */
-    while (*s) {
-
-	/*
-	 * multiply by the 64 bit FNV magic prime mod 2^64
-	 *
-	 * Using 1099511628211, we have the following digits base 2^16:
-	 *
-	 *	0x0	0x100	0x0	0x1b3
-	 *
-	 * which is the same as:
-	 *
-	 *	0x0	1<<FNV_64_PRIME_SHIFT	0x0	FNV_64_PRIME_LOW
-	 */
-	/* multiply by the lowest order digit base 2^16 */
-	tmp[0] = val[0] * FNV_64_PRIME_LOW;
-	tmp[1] = val[1] * FNV_64_PRIME_LOW;
-	tmp[2] = val[2] * FNV_64_PRIME_LOW;
-	tmp[3] = val[3] * FNV_64_PRIME_LOW;
-	/* multiply by the other non-zero digit */
-	tmp[2] += val[0] << FNV_64_PRIME_SHIFT;	/* tmp[2] += val[0] * 0x100 */
-	tmp[3] += val[1] << FNV_64_PRIME_SHIFT;	/* tmp[3] += val[1] * 0x100 */
-	/* propagate carries */
-	tmp[1] += (tmp[0] >> 16);
-	val[0] = tmp[0] & 0xffff;
-	tmp[2] += (tmp[1] >> 16);
-	val[1] = tmp[1] & 0xffff;
-	val[3] = tmp[3] + (tmp[2] >> 16);
-	val[2] = tmp[2] & 0xffff;
-	/*
-	 * Doing a val[3] &= 0xffff; is not really needed since it simply
-	 * removes multiples of 2^64.  We can discard these excess bits
-	 * outside of the loop when we convert to Fnv64_t.
-	 */
-
-	/* xor the bottom with the current octet */
-	val[0] ^= (unsigned long)(*s++);
-    }
-
-    /*
-     * Convert base 2^16 array back into an Fnv64_t
-     */
-    hval.w32[1] = ((val[3]<<16) | val[2]);
-    hval.w32[0] = ((val[1]<<16) | val[0]);
-
-#endif /* !HAVE_64BIT_LONG_LONG */
-
-    /* return our new hash value */
-    return hval;
-}
diff --git a/lib/fnv/hash_64a.c b/lib/fnv/hash_64a.c
deleted file mode 100644
index 6660f92ddf..0000000000
--- a/lib/fnv/hash_64a.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * hash_64 - 64 bit Fowler/Noll/Vo-0 FNV-1a hash code
- *
- * @(#) $Revision: 5.1 $
- * @(#) $Id: hash_64a.c,v 5.1 2009/06/30 09:01:38 chongo Exp $
- * @(#) $Source: /usr/local/src/cmd/fnv/RCS/hash_64a.c,v $
- *
- ***
- *
- * Fowler/Noll/Vo hash
- *
- * The basis of this hash algorithm was taken from an idea sent
- * as reviewer comments to the IEEE POSIX P1003.2 committee by:
- *
- *      Phong Vo (http://www.research.att.com/info/kpv/)
- *      Glenn Fowler (http://www.research.att.com/~gsf/)
- *
- * In a subsequent ballot round:
- *
- *      Landon Curt Noll (http://www.isthe.com/chongo/)
- *
- * improved on their algorithm.  Some people tried this hash
- * and found that it worked rather well.  In an EMail message
- * to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash.
- *
- * FNV hashes are designed to be fast while maintaining a low
- * collision rate. The FNV speed allows one to quickly hash lots
- * of data while maintaining a reasonable collision rate.  See:
- *
- *      http://www.isthe.com/chongo/tech/comp/fnv/index.html
- *
- * for more details as well as other forms of the FNV hash.
- *
- ***
- *
- * To use the recommended 64 bit FNV-1a hash, pass FNV1A_64_INIT as the
- * Fnv64_t hashval argument to fnv_64a_buf() or fnv_64a_str().
- *
- ***
- *
- * Please do not copyright this code.  This code is in the public domain.
- *
- * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * By:
- *	chongo <Landon Curt Noll> /\oo/\
- *      http://www.isthe.com/chongo/
- *
- * Share and Enjoy!	:-)
- */
-
-#include <stdlib.h>
-#include "fnv.h"
-
-
-/*
- * FNV-1a defines the initial basis to be non-zero
- */
-#if !defined(HAVE_64BIT_LONG_LONG)
-const Fnv64_t fnv1a_64_init = { 0x84222325, 0xcbf29ce4 };
-#endif /* ! HAVE_64BIT_LONG_LONG */
-
-
-/*
- * 64 bit magic FNV-1a prime
- */
-#if defined(HAVE_64BIT_LONG_LONG)
-#define FNV_64_PRIME ((Fnv64_t)0x100000001b3ULL)
-#else /* HAVE_64BIT_LONG_LONG */
-#define FNV_64_PRIME_LOW ((unsigned long)0x1b3)	/* lower bits of FNV prime */
-#define FNV_64_PRIME_SHIFT (8)		/* top FNV prime shift above 2^32 */
-#endif /* HAVE_64BIT_LONG_LONG */
-
-
-/*
- * fnv_64a_buf - perform a 64 bit Fowler/Noll/Vo FNV-1a hash on a buffer
- *
- * input:
- *	buf	- start of buffer to hash
- *	len	- length of buffer in octets
- *	hval	- previous hash value or 0 if first call
- *
- * returns:
- *	64 bit hash as a static hash type
- *
- * NOTE: To use the recommended 64 bit FNV-1a hash, use FNV1A_64_INIT as the
- * 	 hval arg on the first call to either fnv_64a_buf() or fnv_64a_str().
- */
-Fnv64_t
-fnv_64a_buf(void *buf, size_t len, Fnv64_t hval)
-{
-    unsigned char *bp = (unsigned char *)buf;	/* start of buffer */
-    unsigned char *be = bp + len;		/* beyond end of buffer */
-
-#if defined(HAVE_64BIT_LONG_LONG)
-    /*
-     * FNV-1a hash each octet of the buffer
-     */
-    while (bp < be) {
-
-	/* xor the bottom with the current octet */
-	hval ^= (Fnv64_t)*bp++;
-
-	/* multiply by the 64 bit FNV magic prime mod 2^64 */
-#if defined(NO_FNV_GCC_OPTIMIZATION)
-	hval *= FNV_64_PRIME;
-#else /* NO_FNV_GCC_OPTIMIZATION */
-	hval += (hval << 1) + (hval << 4) + (hval << 5) +
-		(hval << 7) + (hval << 8) + (hval << 40);
-#endif /* NO_FNV_GCC_OPTIMIZATION */
-    }
-
-#else /* HAVE_64BIT_LONG_LONG */
-
-    unsigned long val[4];			/* hash value in base 2^16 */
-    unsigned long tmp[4];			/* tmp 64 bit value */
-
-    /*
-     * Convert Fnv64_t hval into a base 2^16 array
-     */
-    val[0] = hval.w32[0];
-    val[1] = (val[0] >> 16);
-    val[0] &= 0xffff;
-    val[2] = hval.w32[1];
-    val[3] = (val[2] >> 16);
-    val[2] &= 0xffff;
-
-    /*
-     * FNV-1a hash each octet of the buffer
-     */
-    while (bp < be) {
-
-	/* xor the bottom with the current octet */
-	val[0] ^= (unsigned long)*bp++;
-
-	/*
-	 * multiply by the 64 bit FNV magic prime mod 2^64
-	 *
-	 * Using 0x100000001b3 we have the following digits base 2^16:
-	 *
-	 *	0x0	0x100	0x0	0x1b3
-	 *
-	 * which is the same as:
-	 *
-	 *	0x0	1<<FNV_64_PRIME_SHIFT	0x0	FNV_64_PRIME_LOW
-	 */
-	/* multiply by the lowest order digit base 2^16 */
-	tmp[0] = val[0] * FNV_64_PRIME_LOW;
-	tmp[1] = val[1] * FNV_64_PRIME_LOW;
-	tmp[2] = val[2] * FNV_64_PRIME_LOW;
-	tmp[3] = val[3] * FNV_64_PRIME_LOW;
-	/* multiply by the other non-zero digit */
-	tmp[2] += val[0] << FNV_64_PRIME_SHIFT;	/* tmp[2] += val[0] * 0x100 */
-	tmp[3] += val[1] << FNV_64_PRIME_SHIFT;	/* tmp[3] += val[1] * 0x100 */
-	/* propagate carries */
-	tmp[1] += (tmp[0] >> 16);
-	val[0] = tmp[0] & 0xffff;
-	tmp[2] += (tmp[1] >> 16);
-	val[1] = tmp[1] & 0xffff;
-	val[3] = tmp[3] + (tmp[2] >> 16);
-	val[2] = tmp[2] & 0xffff;
-	/*
-	 * Doing a val[3] &= 0xffff; is not really needed since it simply
-	 * removes multiples of 2^64.  We can discard these excess bits
-	 * outside of the loop when we convert to Fnv64_t.
-	 */
-    }
-
-    /*
-     * Convert base 2^16 array back into an Fnv64_t
-     */
-    hval.w32[1] = ((val[3]<<16) | val[2]);
-    hval.w32[0] = ((val[1]<<16) | val[0]);
-
-#endif /* HAVE_64BIT_LONG_LONG */
-
-    /* return our new hash value */
-    return hval;
-}
-
-
-/*
- * fnv_64a_str - perform a 64 bit Fowler/Noll/Vo FNV-1a hash on a buffer
- *
- * input:
- *	buf	- start of buffer to hash
- *	hval	- previous hash value or 0 if first call
- *
- * returns:
- *	64 bit hash as a static hash type
- *
- * NOTE: To use the recommended 64 bit FNV-1a hash, use FNV1A_64_INIT as the
- * 	 hval arg on the first call to either fnv_64a_buf() or fnv_64a_str().
- */
-Fnv64_t
-fnv_64a_str(char *str, Fnv64_t hval)
-{
-    unsigned char *s = (unsigned char *)str;	/* unsigned string */
-
-#if defined(HAVE_64BIT_LONG_LONG)
-
-    /*
-     * FNV-1a hash each octet of the string
-     */
-    while (*s) {
-
-	/* xor the bottom with the current octet */
-	hval ^= (Fnv64_t)*s++;
-
-	/* multiply by the 64 bit FNV magic prime mod 2^64 */
-#if defined(NO_FNV_GCC_OPTIMIZATION)
-	hval *= FNV_64_PRIME;
-#else /* NO_FNV_GCC_OPTIMIZATION */
-	hval += (hval << 1) + (hval << 4) + (hval << 5) +
-		(hval << 7) + (hval << 8) + (hval << 40);
-#endif /* NO_FNV_GCC_OPTIMIZATION */
-    }
-
-#else /* !HAVE_64BIT_LONG_LONG */
-
-    unsigned long val[4];	/* hash value in base 2^16 */
-    unsigned long tmp[4];	/* tmp 64 bit value */
-
-    /*
-     * Convert Fnv64_t hval into a base 2^16 array
-     */
-    val[0] = hval.w32[0];
-    val[1] = (val[0] >> 16);
-    val[0] &= 0xffff;
-    val[2] = hval.w32[1];
-    val[3] = (val[2] >> 16);
-    val[2] &= 0xffff;
-
-    /*
-     * FNV-1a hash each octet of the string
-     */
-    while (*s) {
-
-	/* xor the bottom with the current octet */
-
-	/*
-	 * multiply by the 64 bit FNV magic prime mod 2^64
-	 *
-	 * Using 1099511628211, we have the following digits base 2^16:
-	 *
-	 *	0x0	0x100	0x0	0x1b3
-	 *
-	 * which is the same as:
-	 *
-	 *	0x0	1<<FNV_64_PRIME_SHIFT	0x0	FNV_64_PRIME_LOW
-	 */
-	/* multiply by the lowest order digit base 2^16 */
-	tmp[0] = val[0] * FNV_64_PRIME_LOW;
-	tmp[1] = val[1] * FNV_64_PRIME_LOW;
-	tmp[2] = val[2] * FNV_64_PRIME_LOW;
-	tmp[3] = val[3] * FNV_64_PRIME_LOW;
-	/* multiply by the other non-zero digit */
-	tmp[2] += val[0] << FNV_64_PRIME_SHIFT;	/* tmp[2] += val[0] * 0x100 */
-	tmp[3] += val[1] << FNV_64_PRIME_SHIFT;	/* tmp[3] += val[1] * 0x100 */
-	/* propagate carries */
-	tmp[1] += (tmp[0] >> 16);
-	val[0] = tmp[0] & 0xffff;
-	tmp[2] += (tmp[1] >> 16);
-	val[1] = tmp[1] & 0xffff;
-	val[3] = tmp[3] + (tmp[2] >> 16);
-	val[2] = tmp[2] & 0xffff;
-	/*
-	 * Doing a val[3] &= 0xffff; is not really needed since it simply
-	 * removes multiples of 2^64.  We can discard these excess bits
-	 * outside of the loop when we convert to Fnv64_t.
-	 */
-	val[0] ^= (unsigned long)(*s++);
-    }
-
-    /*
-     * Convert base 2^16 array back into an Fnv64_t
-     */
-    hval.w32[1] = ((val[3]<<16) | val[2]);
-    hval.w32[0] = ((val[1]<<16) | val[0]);
-
-#endif /* !HAVE_64BIT_LONG_LONG */
-
-    /* return our new hash value */
-    return hval;
-}
diff --git a/lib/fnv/have_ulong64.c b/lib/fnv/have_ulong64.c
deleted file mode 100644
index 5c06262388..0000000000
--- a/lib/fnv/have_ulong64.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * have_ulong64 - Determine if we have a 64 bit unsigned long long
- *
- * usage:
- *	have_ulong64 > longlong.h
- *
- * Not all systems have a 'long long type' so this may not compile on
- * your system.
- *
- * This prog outputs the define:
- *
- *	HAVE_64BIT_LONG_LONG
- *		defined ==> we have a 64 bit unsigned long long
- *		undefined ==> we must simulate a 64 bit unsigned long long
- */
-/*
- *
- * Please do not copyright this code.  This code is in the public domain.
- *
- * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * By:
- *	chongo <Landon Curt Noll> /\oo/\
- *      http://www.isthe.com/chongo/
- *
- * Share and Enjoy!	:-)
- */
-
-/*
- * have the compiler try its hand with unsigned and signed long longs
- */
-#if ! defined(NO64BIT_LONG_LONG)
-unsigned long long val = 1099511628211ULL;
-#endif /* NO64BIT_LONG_LONG */
-
-int
-main(void)
-{
-	/*
-	 * ensure that the length of long long val is what we expect
-	 */
-#if defined(NO64BIT_LONG_LONG)
-	printf("#undef HAVE_64BIT_LONG_LONG\t/* no */\n");
-#else /* NO64BIT_LONG_LONG */
-	if (val == 1099511628211ULL && sizeof(val) == 8) {
-		printf("#define HAVE_64BIT_LONG_LONG\t/* yes */\n");
-	}
-#endif /* NO64BIT_LONG_LONG */
-
-	/* exit(0); */
-	return 0;
-}
diff --git a/lib/fnv/longlong.h b/lib/fnv/longlong.h
deleted file mode 100644
index c8cfe48f29..0000000000
--- a/lib/fnv/longlong.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * DO NOT EDIT -- generated by the Makefile
- */
-
-#if !defined(__LONGLONG_H__)
-#define __LONGLONG_H__
-
-/* do we have/want to use a long long type? */
-#define HAVE_64BIT_LONG_LONG	/* yes */
-
-/*
- * NO64BIT_LONG_LONG undef HAVE_64BIT_LONG_LONG
- */
-#if defined(NO64BIT_LONG_LONG)
-#undef HAVE_64BIT_LONG_LONG
-#endif /* NO64BIT_LONG_LONG */
-
-#endif /* !__LONGLONG_H__ */
diff --git a/lib/fnv/qmk_fnv_type_validation.c b/lib/fnv/qmk_fnv_type_validation.c
deleted file mode 100644
index e8576617ba..0000000000
--- a/lib/fnv/qmk_fnv_type_validation.c
+++ /dev/null
@@ -1,14 +0,0 @@
-// Copyright 2022 Nick Brassel (@tzarc)
-// SPDX-License-Identifier: GPL-2.0-or-later
-#include "fnv.h"
-
-// This library was originally sourced from:
-//     http://www.isthe.com/chongo/tech/comp/fnv/index.html
-//
-// Version at the time of retrieval on 2022-06-26: v5.0.3
-
-_Static_assert(sizeof(long long) == 8, "long long should be 64 bits");
-_Static_assert(sizeof(unsigned long long) == 8, "unsigned long long should be 64 bits");
-
-_Static_assert(sizeof(Fnv32_t) == 4, "Fnv32_t should be 32 bits");
-_Static_assert(sizeof(Fnv64_t) == 8, "Fnv64_t should be 64 bits");
diff --git a/lib/fnv/test_fnv.c b/lib/fnv/test_fnv.c
deleted file mode 100644
index efec3dec1d..0000000000
--- a/lib/fnv/test_fnv.c
+++ /dev/null
@@ -1,2237 +0,0 @@
-/*
- * test_fnv - FNV test suite
- *
- * @(#) $Revision: 5.3 $
- * @(#) $Id: test_fnv.c,v 5.3 2009/06/30 11:50:41 chongo Exp $
- * @(#) $Source: /usr/local/src/cmd/fnv/RCS/test_fnv.c,v $
- *
- ***
- *
- * Fowler/Noll/Vo hash
- *
- * The basis of this hash algorithm was taken from an idea sent
- * as reviewer comments to the IEEE POSIX P1003.2 committee by:
- *
- *      Phong Vo (http://www.research.att.com/info/kpv/)
- *      Glenn Fowler (http://www.research.att.com/~gsf/)
- *
- * In a subsequent ballot round:
- *
- *      Landon Curt Noll (http://www.isthe.com/chongo/)
- *
- * improved on their algorithm.  Some people tried this hash
- * and found that it worked rather well.  In an EMail message
- * to Landon, they named it the ``Fowler/Noll/Vo'' or FNV hash.
- *
- * FNV hashes are designed to be fast while maintaining a low
- * collision rate. The FNV speed allows one to quickly hash lots
- * of data while maintaining a reasonable collision rate.  See:
- *
- *      http://www.isthe.com/chongo/tech/comp/fnv/index.html
- *
- * for more details as well as other forms of the FNV hash.
- *
- ***
- *
- * Please do not copyright this code.  This code is in the public domain.
- *
- * LANDON CURT NOLL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO
- * EVENT SHALL LANDON CURT NOLL BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
- * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
- * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * By:
- *	chongo <Landon Curt Noll> /\oo/\
- *      http://www.isthe.com/chongo/
- *
- * Share and Enjoy!	:-)
- */
-
-#include <stdio.h>
-#include "longlong.h"
-#include "fnv.h"
-
-#define LEN(x) (sizeof(x)-1)
-/* TEST macro does not include trailing NUL byte in the test vector */
-#define TEST(x) {x, LEN(x)}
-/* TEST0 macro includes the trailing NUL byte in the test vector */
-#define TEST0(x) {x, sizeof(x)}
-/* REPEAT500 - repeat a string 500 times */
-#define R500(x) R100(x)R100(x)R100(x)R100(x)R100(x)
-#define R100(x) R10(x)R10(x)R10(x)R10(x)R10(x)R10(x)R10(x)R10(x)R10(x)R10(x)
-#define R10(x) x x x x x x x x x x
-
-/*
- * FNV test vectors
- *
- * NOTE: A NULL pointer marks beyond the end of the test vectors.
- *
- * NOTE: The order of the fnv_test_str[] test vectors is 1-to-1 with:
- *
- *	struct fnv0_32_test_vector fnv0_32_vector[];
- *	struct fnv1_32_test_vector fnv1_32_vector[];
- *	struct fnv1a_32_test_vector fnv1a_32_vector[];
- *	struct fnv0_64_test_vector fnv0_64_vector[];
- *	struct fnv1_64_test_vector fnv1_64_vector[];
- *	struct fnv1a_64_test_vector fnv1a_64_vector[];
- *
- * IMPORTANT NOTE:
- *
- *	If you change the fnv_test_str[] array, you need
- *	to also change ALL of the above fnv*_vector arrays!!!
- *
- *	To rebuild, try:
- *
- *		make vector.c
- *
- *	and then fold the results into the source file.
- *	Of course, you better make sure that the vaules
- *	produced by the above command are valid, otherwise
- * 	you will be testing against invalid vectors!
- */
-struct test_vector fnv_test_str[] = {
-  TEST(""),
-  TEST("a"),
-  TEST("b"),
-  TEST("c"),
-  TEST("d"),
-  TEST("e"),
-  TEST("f"),
-  TEST("fo"),
-  TEST("foo"),
-  TEST("foob"),
-  TEST("fooba"),
-  TEST("foobar"),
-  TEST0(""),
-  TEST0("a"),
-  TEST0("b"),
-  TEST0("c"),
-  TEST0("d"),
-  TEST0("e"),
-  TEST0("f"),
-  TEST0("fo"),
-  TEST0("foo"),
-  TEST0("foob"),
-  TEST0("fooba"),
-  TEST0("foobar"),
-  TEST("ch"),
-  TEST("cho"),
-  TEST("chon"),
-  TEST("chong"),
-  TEST("chongo"),
-  TEST("chongo "),
-  TEST("chongo w"),
-  TEST("chongo wa"),
-  TEST("chongo was"),
-  TEST("chongo was "),
-  TEST("chongo was h"),
-  TEST("chongo was he"),
-  TEST("chongo was her"),
-  TEST("chongo was here"),
-  TEST("chongo was here!"),
-  TEST("chongo was here!\n"),
-  TEST0("ch"),
-  TEST0("cho"),
-  TEST0("chon"),
-  TEST0("chong"),
-  TEST0("chongo"),
-  TEST0("chongo "),
-  TEST0("chongo w"),
-  TEST0("chongo wa"),
-  TEST0("chongo was"),
-  TEST0("chongo was "),
-  TEST0("chongo was h"),
-  TEST0("chongo was he"),
-  TEST0("chongo was her"),
-  TEST0("chongo was here"),
-  TEST0("chongo was here!"),
-  TEST0("chongo was here!\n"),
-  TEST("cu"),
-  TEST("cur"),
-  TEST("curd"),
-  TEST("curds"),
-  TEST("curds "),
-  TEST("curds a"),
-  TEST("curds an"),
-  TEST("curds and"),
-  TEST("curds and "),
-  TEST("curds and w"),
-  TEST("curds and wh"),
-  TEST("curds and whe"),
-  TEST("curds and whey"),
-  TEST("curds and whey\n"),
-  TEST0("cu"),
-  TEST0("cur"),
-  TEST0("curd"),
-  TEST0("curds"),
-  TEST0("curds "),
-  TEST0("curds a"),
-  TEST0("curds an"),
-  TEST0("curds and"),
-  TEST0("curds and "),
-  TEST0("curds and w"),
-  TEST0("curds and wh"),
-  TEST0("curds and whe"),
-  TEST0("curds and whey"),
-  TEST0("curds and whey\n"),
-  TEST("hi"), TEST0("hi"),
-  TEST("hello"), TEST0("hello"),
-  TEST("\xff\x00\x00\x01"), TEST("\x01\x00\x00\xff"),
-  TEST("\xff\x00\x00\x02"), TEST("\x02\x00\x00\xff"),
-  TEST("\xff\x00\x00\x03"), TEST("\x03\x00\x00\xff"),
-  TEST("\xff\x00\x00\x04"), TEST("\x04\x00\x00\xff"),
-  TEST("\x40\x51\x4e\x44"), TEST("\x44\x4e\x51\x40"),
-  TEST("\x40\x51\x4e\x4a"), TEST("\x4a\x4e\x51\x40"),
-  TEST("\x40\x51\x4e\x54"), TEST("\x54\x4e\x51\x40"),
-  TEST("127.0.0.1"), TEST0("127.0.0.1"),
-  TEST("127.0.0.2"), TEST0("127.0.0.2"),
-  TEST("127.0.0.3"), TEST0("127.0.0.3"),
-  TEST("64.81.78.68"), TEST0("64.81.78.68"),
-  TEST("64.81.78.74"), TEST0("64.81.78.74"),
-  TEST("64.81.78.84"), TEST0("64.81.78.84"),
-  TEST("feedface"), TEST0("feedface"),
-  TEST("feedfacedaffdeed"), TEST0("feedfacedaffdeed"),
-  TEST("feedfacedeadbeef"), TEST0("feedfacedeadbeef"),
-  TEST("line 1\nline 2\nline 3"),
-  TEST("chongo <Landon Curt Noll> /\\../\\"),
-  TEST0("chongo <Landon Curt Noll> /\\../\\"),
-  TEST("chongo (Landon Curt Noll) /\\../\\"),
-  TEST0("chongo (Landon Curt Noll) /\\../\\"),
-  TEST("http://antwrp.gsfc.nasa.gov/apod/astropix.html"),
-  TEST("http://en.wikipedia.org/wiki/Fowler_Noll_Vo_hash"),
-  TEST("http://epod.usra.edu/"),
-  TEST("http://exoplanet.eu/"),
-  TEST("http://hvo.wr.usgs.gov/cam3/"),
-  TEST("http://hvo.wr.usgs.gov/cams/HMcam/"),
-  TEST("http://hvo.wr.usgs.gov/kilauea/update/deformation.html"),
-  TEST("http://hvo.wr.usgs.gov/kilauea/update/images.html"),
-  TEST("http://hvo.wr.usgs.gov/kilauea/update/maps.html"),
-  TEST("http://hvo.wr.usgs.gov/volcanowatch/current_issue.html"),
-  TEST("http://neo.jpl.nasa.gov/risk/"),
-  TEST("http://norvig.com/21-days.html"),
-  TEST("http://primes.utm.edu/curios/home.php"),
-  TEST("http://slashdot.org/"),
-  TEST("http://tux.wr.usgs.gov/Maps/155.25-19.5.html"),
-  TEST("http://volcano.wr.usgs.gov/kilaueastatus.php"),
-  TEST("http://www.avo.alaska.edu/activity/Redoubt.php"),
-  TEST("http://www.dilbert.com/fast/"),
-  TEST("http://www.fourmilab.ch/gravitation/orbits/"),
-  TEST("http://www.fpoa.net/"),
-  TEST("http://www.ioccc.org/index.html"),
-  TEST("http://www.isthe.com/cgi-bin/number.cgi"),
-  TEST("http://www.isthe.com/chongo/bio.html"),
-  TEST("http://www.isthe.com/chongo/index.html"),
-  TEST("http://www.isthe.com/chongo/src/calc/lucas-calc"),
-  TEST("http://www.isthe.com/chongo/tech/astro/venus2004.html"),
-  TEST("http://www.isthe.com/chongo/tech/astro/vita.html"),
-  TEST("http://www.isthe.com/chongo/tech/comp/c/expert.html"),
-  TEST("http://www.isthe.com/chongo/tech/comp/calc/index.html"),
-  TEST("http://www.isthe.com/chongo/tech/comp/fnv/index.html"),
-  TEST("http://www.isthe.com/chongo/tech/math/number/howhigh.html"),
-  TEST("http://www.isthe.com/chongo/tech/math/number/number.html"),
-  TEST("http://www.isthe.com/chongo/tech/math/prime/mersenne.html"),
-  TEST("http://www.isthe.com/chongo/tech/math/prime/mersenne.html#largest"),
-  TEST("http://www.lavarnd.org/cgi-bin/corpspeak.cgi"),
-  TEST("http://www.lavarnd.org/cgi-bin/haiku.cgi"),
-  TEST("http://www.lavarnd.org/cgi-bin/rand-none.cgi"),
-  TEST("http://www.lavarnd.org/cgi-bin/randdist.cgi"),
-  TEST("http://www.lavarnd.org/index.html"),
-  TEST("http://www.lavarnd.org/what/nist-test.html"),
-  TEST("http://www.macosxhints.com/"),
-  TEST("http://www.mellis.com/"),
-  TEST("http://www.nature.nps.gov/air/webcams/parks/havoso2alert/havoalert.cfm"),
-  TEST("http://www.nature.nps.gov/air/webcams/parks/havoso2alert/timelines_24.cfm"),
-  TEST("http://www.paulnoll.com/"),
-  TEST("http://www.pepysdiary.com/"),
-  TEST("http://www.sciencenews.org/index/home/activity/view"),
-  TEST("http://www.skyandtelescope.com/"),
-  TEST("http://www.sput.nl/~rob/sirius.html"),
-  TEST("http://www.systemexperts.com/"),
-  TEST("http://www.tq-international.com/phpBB3/index.php"),
-  TEST("http://www.travelquesttours.com/index.htm"),
-  TEST("http://www.wunderground.com/global/stations/89606.html"),
-  TEST(R10("21701")),
-  TEST(R10("M21701")),
-  TEST(R10("2^21701-1")),
-  TEST(R10("\x54\xc5")),
-  TEST(R10("\xc5\x54")),
-  TEST(R10("23209")),
-  TEST(R10("M23209")),
-  TEST(R10("2^23209-1")),
-  TEST(R10("\x5a\xa9")),
-  TEST(R10("\xa9\x5a")),
-  TEST(R10("391581216093")),
-  TEST(R10("391581*2^216093-1")),
-  TEST(R10("\x05\xf9\x9d\x03\x4c\x81")),
-  TEST(R10("FEDCBA9876543210")),
-  TEST(R10("\xfe\xdc\xba\x98\x76\x54\x32\x10")),
-  TEST(R10("EFCDAB8967452301")),
-  TEST(R10("\xef\xcd\xab\x89\x67\x45\x23\x01")),
-  TEST(R10("0123456789ABCDEF")),
-  TEST(R10("\x01\x23\x45\x67\x89\xab\xcd\xef")),
-  TEST(R10("1032547698BADCFE")),
-  TEST(R10("\x10\x32\x54\x76\x98\xba\xdc\xfe")),
-  TEST(R500("\x00")),
-  TEST(R500("\x07")),
-  TEST(R500("~")),
-  TEST(R500("\x7f")),
-  {NULL, 0}	/* MUST BE LAST */
-};
-
-
-/*
- * insert the contents of vector.c below
- *
- *	make vector.c
- *	:r vector.c
- */
-/* start of output generated by make vector.c */
-
-/* FNV-0 32 bit test vectors */
-struct fnv0_32_test_vector fnv0_32_vector[] = {
-    { &fnv_test_str[0], (Fnv32_t) 0x00000000UL },
-    { &fnv_test_str[1], (Fnv32_t) 0x00000061UL },
-    { &fnv_test_str[2], (Fnv32_t) 0x00000062UL },
-    { &fnv_test_str[3], (Fnv32_t) 0x00000063UL },
-    { &fnv_test_str[4], (Fnv32_t) 0x00000064UL },
-    { &fnv_test_str[5], (Fnv32_t) 0x00000065UL },
-    { &fnv_test_str[6], (Fnv32_t) 0x00000066UL },
-    { &fnv_test_str[7], (Fnv32_t) 0x6600a0fdUL },
-    { &fnv_test_str[8], (Fnv32_t) 0x8ffd6e28UL },
-    { &fnv_test_str[9], (Fnv32_t) 0xd3f4689aUL },
-    { &fnv_test_str[10], (Fnv32_t) 0x43c0aa0fUL },
-    { &fnv_test_str[11], (Fnv32_t) 0xb74bb5efUL },
-    { &fnv_test_str[12], (Fnv32_t) 0x00000000UL },
-    { &fnv_test_str[13], (Fnv32_t) 0x610098b3UL },
-    { &fnv_test_str[14], (Fnv32_t) 0x62009a46UL },
-    { &fnv_test_str[15], (Fnv32_t) 0x63009bd9UL },
-    { &fnv_test_str[16], (Fnv32_t) 0x64009d6cUL },
-    { &fnv_test_str[17], (Fnv32_t) 0x65009effUL },
-    { &fnv_test_str[18], (Fnv32_t) 0x6600a092UL },
-    { &fnv_test_str[19], (Fnv32_t) 0x8ffd6e47UL },
-    { &fnv_test_str[20], (Fnv32_t) 0xd3f468f8UL },
-    { &fnv_test_str[21], (Fnv32_t) 0x43c0aa6eUL },
-    { &fnv_test_str[22], (Fnv32_t) 0xb74bb59dUL },
-    { &fnv_test_str[23], (Fnv32_t) 0x7b2f673dUL },
-    { &fnv_test_str[24], (Fnv32_t) 0x63009bb1UL },
-    { &fnv_test_str[25], (Fnv32_t) 0x8af517ccUL },
-    { &fnv_test_str[26], (Fnv32_t) 0x8bd4764aUL },
-    { &fnv_test_str[27], (Fnv32_t) 0x69763619UL },
-    { &fnv_test_str[28], (Fnv32_t) 0x1e172934UL },
-    { &fnv_test_str[29], (Fnv32_t) 0x9275dcfcUL },
-    { &fnv_test_str[30], (Fnv32_t) 0x8b8ae0c3UL },
-    { &fnv_test_str[31], (Fnv32_t) 0x6e9fd298UL },
-    { &fnv_test_str[32], (Fnv32_t) 0xbd98853bUL },
-    { &fnv_test_str[33], (Fnv32_t) 0xb219bbc1UL },
-    { &fnv_test_str[34], (Fnv32_t) 0x1f8290bbUL },
-    { &fnv_test_str[35], (Fnv32_t) 0x5589d604UL },
-    { &fnv_test_str[36], (Fnv32_t) 0xabfbe83eUL },
-    { &fnv_test_str[37], (Fnv32_t) 0xfb8e99ffUL },
-    { &fnv_test_str[38], (Fnv32_t) 0x007c6c4cUL },
-    { &fnv_test_str[39], (Fnv32_t) 0x0fde7baeUL },
-    { &fnv_test_str[40], (Fnv32_t) 0x8af517a3UL },
-    { &fnv_test_str[41], (Fnv32_t) 0x8bd47624UL },
-    { &fnv_test_str[42], (Fnv32_t) 0x6976367eUL },
-    { &fnv_test_str[43], (Fnv32_t) 0x1e17295bUL },
-    { &fnv_test_str[44], (Fnv32_t) 0x9275dcdcUL },
-    { &fnv_test_str[45], (Fnv32_t) 0x8b8ae0b4UL },
-    { &fnv_test_str[46], (Fnv32_t) 0x6e9fd2f9UL },
-    { &fnv_test_str[47], (Fnv32_t) 0xbd988548UL },
-    { &fnv_test_str[48], (Fnv32_t) 0xb219bbe1UL },
-    { &fnv_test_str[49], (Fnv32_t) 0x1f8290d3UL },
-    { &fnv_test_str[50], (Fnv32_t) 0x5589d661UL },
-    { &fnv_test_str[51], (Fnv32_t) 0xabfbe84cUL },
-    { &fnv_test_str[52], (Fnv32_t) 0xfb8e999aUL },
-    { &fnv_test_str[53], (Fnv32_t) 0x007c6c6dUL },
-    { &fnv_test_str[54], (Fnv32_t) 0x0fde7ba4UL },
-    { &fnv_test_str[55], (Fnv32_t) 0xa93cb2eaUL },
-    { &fnv_test_str[56], (Fnv32_t) 0x63009bacUL },
-    { &fnv_test_str[57], (Fnv32_t) 0x85f50fb6UL },
-    { &fnv_test_str[58], (Fnv32_t) 0x96c7bbe6UL },
-    { &fnv_test_str[59], (Fnv32_t) 0x426ccb61UL },
-    { &fnv_test_str[60], (Fnv32_t) 0xf2442993UL },
-    { &fnv_test_str[61], (Fnv32_t) 0xf44d7208UL },
-    { &fnv_test_str[62], (Fnv32_t) 0x9dea82f6UL },
-    { &fnv_test_str[63], (Fnv32_t) 0x8e2c2926UL },
-    { &fnv_test_str[64], (Fnv32_t) 0xf584c6f2UL },
-    { &fnv_test_str[65], (Fnv32_t) 0x72052e81UL },
-    { &fnv_test_str[66], (Fnv32_t) 0xff28357bUL },
-    { &fnv_test_str[67], (Fnv32_t) 0x274c30c4UL },
-    { &fnv_test_str[68], (Fnv32_t) 0xa0f0c4f5UL },
-    { &fnv_test_str[69], (Fnv32_t) 0x50060da5UL },
-    { &fnv_test_str[70], (Fnv32_t) 0x85f50fc4UL },
-    { &fnv_test_str[71], (Fnv32_t) 0x96c7bb82UL },
-    { &fnv_test_str[72], (Fnv32_t) 0x426ccb12UL },
-    { &fnv_test_str[73], (Fnv32_t) 0xf24429b3UL },
-    { &fnv_test_str[74], (Fnv32_t) 0xf44d7269UL },
-    { &fnv_test_str[75], (Fnv32_t) 0x9dea8298UL },
-    { &fnv_test_str[76], (Fnv32_t) 0x8e2c2942UL },
-    { &fnv_test_str[77], (Fnv32_t) 0xf584c6d2UL },
-    { &fnv_test_str[78], (Fnv32_t) 0x72052ef6UL },
-    { &fnv_test_str[79], (Fnv32_t) 0xff283513UL },
-    { &fnv_test_str[80], (Fnv32_t) 0x274c30a1UL },
-    { &fnv_test_str[81], (Fnv32_t) 0xa0f0c48cUL },
-    { &fnv_test_str[82], (Fnv32_t) 0x50060dafUL },
-    { &fnv_test_str[83], (Fnv32_t) 0x9e877abfUL },
-    { &fnv_test_str[84], (Fnv32_t) 0x6800a3d1UL },
-    { &fnv_test_str[85], (Fnv32_t) 0x8a01e203UL },
-    { &fnv_test_str[86], (Fnv32_t) 0xec6d6be8UL },
-    { &fnv_test_str[87], (Fnv32_t) 0x1840de38UL },
-    { &fnv_test_str[88], (Fnv32_t) 0xa7cc97b4UL },
-    { &fnv_test_str[89], (Fnv32_t) 0x3ee6b3b4UL },
-    { &fnv_test_str[90], (Fnv32_t) 0xa7cc97b7UL },
-    { &fnv_test_str[91], (Fnv32_t) 0x7dcd6669UL },
-    { &fnv_test_str[92], (Fnv32_t) 0xa7cc97b6UL },
-    { &fnv_test_str[93], (Fnv32_t) 0xbcb4191eUL },
-    { &fnv_test_str[94], (Fnv32_t) 0xa7cc97b1UL },
-    { &fnv_test_str[95], (Fnv32_t) 0xfb9acdd3UL },
-    { &fnv_test_str[96], (Fnv32_t) 0x89380433UL },
-    { &fnv_test_str[97], (Fnv32_t) 0x8acd2855UL },
-    { &fnv_test_str[98], (Fnv32_t) 0x8938043dUL },
-    { &fnv_test_str[99], (Fnv32_t) 0xcaeed493UL },
-    { &fnv_test_str[100], (Fnv32_t) 0x89380423UL },
-    { &fnv_test_str[101], (Fnv32_t) 0x59382a25UL },
-    { &fnv_test_str[102], (Fnv32_t) 0x567f75d7UL },
-    { &fnv_test_str[103], (Fnv32_t) 0x01a68175UL },
-    { &fnv_test_str[104], (Fnv32_t) 0x567f75d4UL },
-    { &fnv_test_str[105], (Fnv32_t) 0xfea67cbcUL },
-    { &fnv_test_str[106], (Fnv32_t) 0x567f75d5UL },
-    { &fnv_test_str[107], (Fnv32_t) 0xffa67e4fUL },
-    { &fnv_test_str[108], (Fnv32_t) 0xd131b668UL },
-    { &fnv_test_str[109], (Fnv32_t) 0xb94225b8UL },
-    { &fnv_test_str[110], (Fnv32_t) 0xd231b7d7UL },
-    { &fnv_test_str[111], (Fnv32_t) 0xbb446775UL },
-    { &fnv_test_str[112], (Fnv32_t) 0xdf31cc6eUL },
-    { &fnv_test_str[113], (Fnv32_t) 0xc964d12aUL },
-    { &fnv_test_str[114], (Fnv32_t) 0x23af8f9fUL },
-    { &fnv_test_str[115], (Fnv32_t) 0xcc5f174dUL },
-    { &fnv_test_str[116], (Fnv32_t) 0x96b29b8cUL },
-    { &fnv_test_str[117], (Fnv32_t) 0xc72add64UL },
-    { &fnv_test_str[118], (Fnv32_t) 0x528fb7efUL },
-    { &fnv_test_str[119], (Fnv32_t) 0xe73e8d3dUL },
-    { &fnv_test_str[120], (Fnv32_t) 0x876386feUL },
-    { &fnv_test_str[121], (Fnv32_t) 0x811c9dc5UL },
-    { &fnv_test_str[122], (Fnv32_t) 0x050c5d1fUL },
-    { &fnv_test_str[123], (Fnv32_t) 0x14bf7238UL },
-    { &fnv_test_str[124], (Fnv32_t) 0xe160ce28UL },
-    { &fnv_test_str[125], (Fnv32_t) 0x89dc5a75UL },
-    { &fnv_test_str[126], (Fnv32_t) 0xd89b69a0UL },
-    { &fnv_test_str[127], (Fnv32_t) 0x94471a88UL },
-    { &fnv_test_str[128], (Fnv32_t) 0xe78db65fUL },
-    { &fnv_test_str[129], (Fnv32_t) 0x0c3009a2UL },
-    { &fnv_test_str[130], (Fnv32_t) 0x122dff03UL },
-    { &fnv_test_str[131], (Fnv32_t) 0xb4cd8875UL },
-    { &fnv_test_str[132], (Fnv32_t) 0xf4dba725UL },
-    { &fnv_test_str[133], (Fnv32_t) 0x41a16560UL },
-    { &fnv_test_str[134], (Fnv32_t) 0x9c0f941fUL },
-    { &fnv_test_str[135], (Fnv32_t) 0x451a5348UL },
-    { &fnv_test_str[136], (Fnv32_t) 0x3f1d1d89UL },
-    { &fnv_test_str[137], (Fnv32_t) 0x1b91b57aUL },
-    { &fnv_test_str[138], (Fnv32_t) 0x3e99b577UL },
-    { &fnv_test_str[139], (Fnv32_t) 0x4c9de07aUL },
-    { &fnv_test_str[140], (Fnv32_t) 0x1ddf7572UL },
-    { &fnv_test_str[141], (Fnv32_t) 0x64e81976UL },
-    { &fnv_test_str[142], (Fnv32_t) 0x1106a888UL },
-    { &fnv_test_str[143], (Fnv32_t) 0xa498d8e5UL },
-    { &fnv_test_str[144], (Fnv32_t) 0x3c03d2e3UL },
-    { &fnv_test_str[145], (Fnv32_t) 0x26568b28UL },
-    { &fnv_test_str[146], (Fnv32_t) 0x70d7fb42UL },
-    { &fnv_test_str[147], (Fnv32_t) 0xd3ae1d22UL },
-    { &fnv_test_str[148], (Fnv32_t) 0xac8ea5f4UL },
-    { &fnv_test_str[149], (Fnv32_t) 0x4d0abd60UL },
-    { &fnv_test_str[150], (Fnv32_t) 0x48f5e086UL },
-    { &fnv_test_str[151], (Fnv32_t) 0xa8f6241bUL },
-    { &fnv_test_str[152], (Fnv32_t) 0x572f864fUL },
-    { &fnv_test_str[153], (Fnv32_t) 0xa5340803UL },
-    { &fnv_test_str[154], (Fnv32_t) 0x22881aa8UL },
-    { &fnv_test_str[155], (Fnv32_t) 0xc2e2f5a2UL },
-    { &fnv_test_str[156], (Fnv32_t) 0xebf5aec7UL },
-    { &fnv_test_str[157], (Fnv32_t) 0x3cdbfb85UL },
-    { &fnv_test_str[158], (Fnv32_t) 0xbb859704UL },
-    { &fnv_test_str[159], (Fnv32_t) 0xc956fe11UL },
-    { &fnv_test_str[160], (Fnv32_t) 0x8f11a7c9UL },
-    { &fnv_test_str[161], (Fnv32_t) 0x36c48ecfUL },
-    { &fnv_test_str[162], (Fnv32_t) 0x24bfa27eUL },
-    { &fnv_test_str[163], (Fnv32_t) 0xf2596ad1UL },
-    { &fnv_test_str[164], (Fnv32_t) 0xf14a9b45UL },
-    { &fnv_test_str[165], (Fnv32_t) 0x7d45835aUL },
-    { &fnv_test_str[166], (Fnv32_t) 0x6e49334dUL },
-    { &fnv_test_str[167], (Fnv32_t) 0x71767337UL },
-    { &fnv_test_str[168], (Fnv32_t) 0x858a1a8aUL },
-    { &fnv_test_str[169], (Fnv32_t) 0x16e75ac2UL },
-    { &fnv_test_str[170], (Fnv32_t) 0x409f99dfUL },
-    { &fnv_test_str[171], (Fnv32_t) 0x6d6652ddUL },
-    { &fnv_test_str[172], (Fnv32_t) 0x2761a9ffUL },
-    { &fnv_test_str[173], (Fnv32_t) 0x41f0d616UL },
-    { &fnv_test_str[174], (Fnv32_t) 0x0e2d0d0fUL },
-    { &fnv_test_str[175], (Fnv32_t) 0x06adc8fdUL },
-    { &fnv_test_str[176], (Fnv32_t) 0x60e0d4b9UL },
-    { &fnv_test_str[177], (Fnv32_t) 0x5ddc79d3UL },
-    { &fnv_test_str[178], (Fnv32_t) 0x1e6d0b46UL },
-    { &fnv_test_str[179], (Fnv32_t) 0x1d1514d8UL },
-    { &fnv_test_str[180], (Fnv32_t) 0xb1903a4eUL },
-    { &fnv_test_str[181], (Fnv32_t) 0x8200c318UL },
-    { &fnv_test_str[182], (Fnv32_t) 0x15e22888UL },
-    { &fnv_test_str[183], (Fnv32_t) 0x57591760UL },
-    { &fnv_test_str[184], (Fnv32_t) 0x02462efcUL },
-    { &fnv_test_str[185], (Fnv32_t) 0x7651ec44UL },
-    { &fnv_test_str[186], (Fnv32_t) 0x7c24e9d4UL },
-    { &fnv_test_str[187], (Fnv32_t) 0x1952a034UL },
-    { &fnv_test_str[188], (Fnv32_t) 0xd4c46864UL },
-    { &fnv_test_str[189], (Fnv32_t) 0xcb57cde0UL },
-    { &fnv_test_str[190], (Fnv32_t) 0x71136a70UL },
-    { &fnv_test_str[191], (Fnv32_t) 0x0618fb40UL },
-    { &fnv_test_str[192], (Fnv32_t) 0x69a24fc0UL },
-    { &fnv_test_str[193], (Fnv32_t) 0x6a9be510UL },
-    { &fnv_test_str[194], (Fnv32_t) 0xe0477040UL },
-    { &fnv_test_str[195], (Fnv32_t) 0x85aa94b0UL },
-    { &fnv_test_str[196], (Fnv32_t) 0xc6d76240UL },
-    { &fnv_test_str[197], (Fnv32_t) 0xa9f09e40UL },
-    { &fnv_test_str[198], (Fnv32_t) 0xa0291540UL },
-    { &fnv_test_str[199], (Fnv32_t) 0x00000000UL },
-    { &fnv_test_str[200], (Fnv32_t) 0x2e672aa4UL },
-    { &fnv_test_str[201], (Fnv32_t) 0x84b1aa48UL },
-    { &fnv_test_str[202], (Fnv32_t) 0xfc24ba24UL },
-    { NULL, 0 }
-};
-
-/* FNV-1 32 bit test vectors */
-struct fnv1_32_test_vector fnv1_32_vector[] = {
-    { &fnv_test_str[0], (Fnv32_t) 0x811c9dc5UL },
-    { &fnv_test_str[1], (Fnv32_t) 0x050c5d7eUL },
-    { &fnv_test_str[2], (Fnv32_t) 0x050c5d7dUL },
-    { &fnv_test_str[3], (Fnv32_t) 0x050c5d7cUL },
-    { &fnv_test_str[4], (Fnv32_t) 0x050c5d7bUL },
-    { &fnv_test_str[5], (Fnv32_t) 0x050c5d7aUL },
-    { &fnv_test_str[6], (Fnv32_t) 0x050c5d79UL },
-    { &fnv_test_str[7], (Fnv32_t) 0x6b772514UL },
-    { &fnv_test_str[8], (Fnv32_t) 0x408f5e13UL },
-    { &fnv_test_str[9], (Fnv32_t) 0xb4b1178bUL },
-    { &fnv_test_str[10], (Fnv32_t) 0xfdc80fb0UL },
-    { &fnv_test_str[11], (Fnv32_t) 0x31f0b262UL },
-    { &fnv_test_str[12], (Fnv32_t) 0x050c5d1fUL },
-    { &fnv_test_str[13], (Fnv32_t) 0x70772d5aUL },
-    { &fnv_test_str[14], (Fnv32_t) 0x6f772bc7UL },
-    { &fnv_test_str[15], (Fnv32_t) 0x6e772a34UL },
-    { &fnv_test_str[16], (Fnv32_t) 0x6d7728a1UL },
-    { &fnv_test_str[17], (Fnv32_t) 0x6c77270eUL },
-    { &fnv_test_str[18], (Fnv32_t) 0x6b77257bUL },
-    { &fnv_test_str[19], (Fnv32_t) 0x408f5e7cUL },
-    { &fnv_test_str[20], (Fnv32_t) 0xb4b117e9UL },
-    { &fnv_test_str[21], (Fnv32_t) 0xfdc80fd1UL },
-    { &fnv_test_str[22], (Fnv32_t) 0x31f0b210UL },
-    { &fnv_test_str[23], (Fnv32_t) 0xffe8d046UL },
-    { &fnv_test_str[24], (Fnv32_t) 0x6e772a5cUL },
-    { &fnv_test_str[25], (Fnv32_t) 0x4197aebbUL },
-    { &fnv_test_str[26], (Fnv32_t) 0xfcc8100fUL },
-    { &fnv_test_str[27], (Fnv32_t) 0xfdf147faUL },
-    { &fnv_test_str[28], (Fnv32_t) 0xbcd44ee1UL },
-    { &fnv_test_str[29], (Fnv32_t) 0x23382c13UL },
-    { &fnv_test_str[30], (Fnv32_t) 0x846d619eUL },
-    { &fnv_test_str[31], (Fnv32_t) 0x1630abdbUL },
-    { &fnv_test_str[32], (Fnv32_t) 0xc99e89b2UL },
-    { &fnv_test_str[33], (Fnv32_t) 0x1692c316UL },
-    { &fnv_test_str[34], (Fnv32_t) 0x9f091bcaUL },
-    { &fnv_test_str[35], (Fnv32_t) 0x2556be9bUL },
-    { &fnv_test_str[36], (Fnv32_t) 0x628e0e73UL },
-    { &fnv_test_str[37], (Fnv32_t) 0x98a0bf6cUL },
-    { &fnv_test_str[38], (Fnv32_t) 0xb10d5725UL },
-    { &fnv_test_str[39], (Fnv32_t) 0xdd002f35UL },
-    { &fnv_test_str[40], (Fnv32_t) 0x4197aed4UL },
-    { &fnv_test_str[41], (Fnv32_t) 0xfcc81061UL },
-    { &fnv_test_str[42], (Fnv32_t) 0xfdf1479dUL },
-    { &fnv_test_str[43], (Fnv32_t) 0xbcd44e8eUL },
-    { &fnv_test_str[44], (Fnv32_t) 0x23382c33UL },
-    { &fnv_test_str[45], (Fnv32_t) 0x846d61e9UL },
-    { &fnv_test_str[46], (Fnv32_t) 0x1630abbaUL },
-    { &fnv_test_str[47], (Fnv32_t) 0xc99e89c1UL },
-    { &fnv_test_str[48], (Fnv32_t) 0x1692c336UL },
-    { &fnv_test_str[49], (Fnv32_t) 0x9f091ba2UL },
-    { &fnv_test_str[50], (Fnv32_t) 0x2556befeUL },
-    { &fnv_test_str[51], (Fnv32_t) 0x628e0e01UL },
-    { &fnv_test_str[52], (Fnv32_t) 0x98a0bf09UL },
-    { &fnv_test_str[53], (Fnv32_t) 0xb10d5704UL },
-    { &fnv_test_str[54], (Fnv32_t) 0xdd002f3fUL },
-    { &fnv_test_str[55], (Fnv32_t) 0x1c4a506fUL },
-    { &fnv_test_str[56], (Fnv32_t) 0x6e772a41UL },
-    { &fnv_test_str[57], (Fnv32_t) 0x26978421UL },
-    { &fnv_test_str[58], (Fnv32_t) 0xe184ff97UL },
-    { &fnv_test_str[59], (Fnv32_t) 0x9b5e5ac6UL },
-    { &fnv_test_str[60], (Fnv32_t) 0x5b88e592UL },
-    { &fnv_test_str[61], (Fnv32_t) 0xaa8164b7UL },
-    { &fnv_test_str[62], (Fnv32_t) 0x20b18c7bUL },
-    { &fnv_test_str[63], (Fnv32_t) 0xf28025c5UL },
-    { &fnv_test_str[64], (Fnv32_t) 0x84bb753fUL },
-    { &fnv_test_str[65], (Fnv32_t) 0x3219925aUL },
-    { &fnv_test_str[66], (Fnv32_t) 0x384163c6UL },
-    { &fnv_test_str[67], (Fnv32_t) 0x54f010d7UL },
-    { &fnv_test_str[68], (Fnv32_t) 0x8cea820cUL },
-    { &fnv_test_str[69], (Fnv32_t) 0xe12ab8eeUL },
-    { &fnv_test_str[70], (Fnv32_t) 0x26978453UL },
-    { &fnv_test_str[71], (Fnv32_t) 0xe184fff3UL },
-    { &fnv_test_str[72], (Fnv32_t) 0x9b5e5ab5UL },
-    { &fnv_test_str[73], (Fnv32_t) 0x5b88e5b2UL },
-    { &fnv_test_str[74], (Fnv32_t) 0xaa8164d6UL },
-    { &fnv_test_str[75], (Fnv32_t) 0x20b18c15UL },
-    { &fnv_test_str[76], (Fnv32_t) 0xf28025a1UL },
-    { &fnv_test_str[77], (Fnv32_t) 0x84bb751fUL },
-    { &fnv_test_str[78], (Fnv32_t) 0x3219922dUL },
-    { &fnv_test_str[79], (Fnv32_t) 0x384163aeUL },
-    { &fnv_test_str[80], (Fnv32_t) 0x54f010b2UL },
-    { &fnv_test_str[81], (Fnv32_t) 0x8cea8275UL },
-    { &fnv_test_str[82], (Fnv32_t) 0xe12ab8e4UL },
-    { &fnv_test_str[83], (Fnv32_t) 0x64411eaaUL },
-    { &fnv_test_str[84], (Fnv32_t) 0x6977223cUL },
-    { &fnv_test_str[85], (Fnv32_t) 0x428ae474UL },
-    { &fnv_test_str[86], (Fnv32_t) 0xb6fa7167UL },
-    { &fnv_test_str[87], (Fnv32_t) 0x73408525UL },
-    { &fnv_test_str[88], (Fnv32_t) 0xb78320a1UL },
-    { &fnv_test_str[89], (Fnv32_t) 0x0caf4135UL },
-    { &fnv_test_str[90], (Fnv32_t) 0xb78320a2UL },
-    { &fnv_test_str[91], (Fnv32_t) 0xcdc88e80UL },
-    { &fnv_test_str[92], (Fnv32_t) 0xb78320a3UL },
-    { &fnv_test_str[93], (Fnv32_t) 0x8ee1dbcbUL },
-    { &fnv_test_str[94], (Fnv32_t) 0xb78320a4UL },
-    { &fnv_test_str[95], (Fnv32_t) 0x4ffb2716UL },
-    { &fnv_test_str[96], (Fnv32_t) 0x860632aaUL },
-    { &fnv_test_str[97], (Fnv32_t) 0xcc2c5c64UL },
-    { &fnv_test_str[98], (Fnv32_t) 0x860632a4UL },
-    { &fnv_test_str[99], (Fnv32_t) 0x2a7ec4a6UL },
-    { &fnv_test_str[100], (Fnv32_t) 0x860632baUL },
-    { &fnv_test_str[101], (Fnv32_t) 0xfefe8e14UL },
-    { &fnv_test_str[102], (Fnv32_t) 0x0a3cffd8UL },
-    { &fnv_test_str[103], (Fnv32_t) 0xf606c108UL },
-    { &fnv_test_str[104], (Fnv32_t) 0x0a3cffdbUL },
-    { &fnv_test_str[105], (Fnv32_t) 0xf906c5c1UL },
-    { &fnv_test_str[106], (Fnv32_t) 0x0a3cffdaUL },
-    { &fnv_test_str[107], (Fnv32_t) 0xf806c42eUL },
-    { &fnv_test_str[108], (Fnv32_t) 0xc07167d7UL },
-    { &fnv_test_str[109], (Fnv32_t) 0xc9867775UL },
-    { &fnv_test_str[110], (Fnv32_t) 0xbf716668UL },
-    { &fnv_test_str[111], (Fnv32_t) 0xc78435b8UL },
-    { &fnv_test_str[112], (Fnv32_t) 0xc6717155UL },
-    { &fnv_test_str[113], (Fnv32_t) 0xb99568cfUL },
-    { &fnv_test_str[114], (Fnv32_t) 0x7662e0d6UL },
-    { &fnv_test_str[115], (Fnv32_t) 0x33a7f0e2UL },
-    { &fnv_test_str[116], (Fnv32_t) 0xc2732f95UL },
-    { &fnv_test_str[117], (Fnv32_t) 0xb053e78fUL },
-    { &fnv_test_str[118], (Fnv32_t) 0x3a19c02aUL },
-    { &fnv_test_str[119], (Fnv32_t) 0xa089821eUL },
-    { &fnv_test_str[120], (Fnv32_t) 0x31ae8f83UL },
-    { &fnv_test_str[121], (Fnv32_t) 0x995fa9c4UL },
-    { &fnv_test_str[122], (Fnv32_t) 0x35983f8cUL },
-    { &fnv_test_str[123], (Fnv32_t) 0x5036a251UL },
-    { &fnv_test_str[124], (Fnv32_t) 0x97018583UL },
-    { &fnv_test_str[125], (Fnv32_t) 0xb4448d60UL },
-    { &fnv_test_str[126], (Fnv32_t) 0x025dfe59UL },
-    { &fnv_test_str[127], (Fnv32_t) 0xc5eab3afUL },
-    { &fnv_test_str[128], (Fnv32_t) 0x7d21ba1eUL },
-    { &fnv_test_str[129], (Fnv32_t) 0x7704cddbUL },
-    { &fnv_test_str[130], (Fnv32_t) 0xd0071bfeUL },
-    { &fnv_test_str[131], (Fnv32_t) 0x0ff3774cUL },
-    { &fnv_test_str[132], (Fnv32_t) 0xb0fea0eaUL },
-    { &fnv_test_str[133], (Fnv32_t) 0x58177303UL },
-    { &fnv_test_str[134], (Fnv32_t) 0x4f599cdaUL },
-    { &fnv_test_str[135], (Fnv32_t) 0x3e590a47UL },
-    { &fnv_test_str[136], (Fnv32_t) 0x965595f8UL },
-    { &fnv_test_str[137], (Fnv32_t) 0xc37f178dUL },
-    { &fnv_test_str[138], (Fnv32_t) 0x9711dd26UL },
-    { &fnv_test_str[139], (Fnv32_t) 0x23c99b7fUL },
-    { &fnv_test_str[140], (Fnv32_t) 0x6e568b17UL },
-    { &fnv_test_str[141], (Fnv32_t) 0x43f0245bUL },
-    { &fnv_test_str[142], (Fnv32_t) 0xbcb7a001UL },
-    { &fnv_test_str[143], (Fnv32_t) 0x12e6dffeUL },
-    { &fnv_test_str[144], (Fnv32_t) 0x0792f2d6UL },
-    { &fnv_test_str[145], (Fnv32_t) 0xb966936bUL },
-    { &fnv_test_str[146], (Fnv32_t) 0x46439ac5UL },
-    { &fnv_test_str[147], (Fnv32_t) 0x728d49afUL },
-    { &fnv_test_str[148], (Fnv32_t) 0xd33745c9UL },
-    { &fnv_test_str[149], (Fnv32_t) 0xbc382a57UL },
-    { &fnv_test_str[150], (Fnv32_t) 0x4bda1d31UL },
-    { &fnv_test_str[151], (Fnv32_t) 0xce35ccaeUL },
-    { &fnv_test_str[152], (Fnv32_t) 0x3b6eed94UL },
-    { &fnv_test_str[153], (Fnv32_t) 0x445c9c58UL },
-    { &fnv_test_str[154], (Fnv32_t) 0x3db8bf9dUL },
-    { &fnv_test_str[155], (Fnv32_t) 0x2dee116dUL },
-    { &fnv_test_str[156], (Fnv32_t) 0xc18738daUL },
-    { &fnv_test_str[157], (Fnv32_t) 0x5b156176UL },
-    { &fnv_test_str[158], (Fnv32_t) 0x2aa7d593UL },
-    { &fnv_test_str[159], (Fnv32_t) 0xb2409658UL },
-    { &fnv_test_str[160], (Fnv32_t) 0xe1489528UL },
-    { &fnv_test_str[161], (Fnv32_t) 0xfe1ee07eUL },
-    { &fnv_test_str[162], (Fnv32_t) 0xe8842315UL },
-    { &fnv_test_str[163], (Fnv32_t) 0x3a6a63a2UL },
-    { &fnv_test_str[164], (Fnv32_t) 0x06d2c18cUL },
-    { &fnv_test_str[165], (Fnv32_t) 0xf8ef7225UL },
-    { &fnv_test_str[166], (Fnv32_t) 0x843d3300UL },
-    { &fnv_test_str[167], (Fnv32_t) 0xbb24f7aeUL },
-    { &fnv_test_str[168], (Fnv32_t) 0x878c0ec9UL },
-    { &fnv_test_str[169], (Fnv32_t) 0xb557810fUL },
-    { &fnv_test_str[170], (Fnv32_t) 0x57423246UL },
-    { &fnv_test_str[171], (Fnv32_t) 0x87f7505eUL },
-    { &fnv_test_str[172], (Fnv32_t) 0xbb809f20UL },
-    { &fnv_test_str[173], (Fnv32_t) 0x8932abb5UL },
-    { &fnv_test_str[174], (Fnv32_t) 0x0a9b3aa0UL },
-    { &fnv_test_str[175], (Fnv32_t) 0xb8682a24UL },
-    { &fnv_test_str[176], (Fnv32_t) 0xa7ac1c56UL },
-    { &fnv_test_str[177], (Fnv32_t) 0x11409252UL },
-    { &fnv_test_str[178], (Fnv32_t) 0xa987f517UL },
-    { &fnv_test_str[179], (Fnv32_t) 0xf309e7edUL },
-    { &fnv_test_str[180], (Fnv32_t) 0xc9e8f417UL },
-    { &fnv_test_str[181], (Fnv32_t) 0x7f447bddUL },
-    { &fnv_test_str[182], (Fnv32_t) 0xb929adc5UL },
-    { &fnv_test_str[183], (Fnv32_t) 0x57022879UL },
-    { &fnv_test_str[184], (Fnv32_t) 0xdcfd2c49UL },
-    { &fnv_test_str[185], (Fnv32_t) 0x6edafff5UL },
-    { &fnv_test_str[186], (Fnv32_t) 0xf04fb1f1UL },
-    { &fnv_test_str[187], (Fnv32_t) 0xfb7de8b9UL },
-    { &fnv_test_str[188], (Fnv32_t) 0xc5f1d7e9UL },
-    { &fnv_test_str[189], (Fnv32_t) 0x32c1f439UL },
-    { &fnv_test_str[190], (Fnv32_t) 0x7fd3eb7dUL },
-    { &fnv_test_str[191], (Fnv32_t) 0x81597da5UL },
-    { &fnv_test_str[192], (Fnv32_t) 0x05eb7a25UL },
-    { &fnv_test_str[193], (Fnv32_t) 0x9c0fa1b5UL },
-    { &fnv_test_str[194], (Fnv32_t) 0x53ccb1c5UL },
-    { &fnv_test_str[195], (Fnv32_t) 0xfabece15UL },
-    { &fnv_test_str[196], (Fnv32_t) 0x4ad745a5UL },
-    { &fnv_test_str[197], (Fnv32_t) 0xe5bdc495UL },
-    { &fnv_test_str[198], (Fnv32_t) 0x23b3c0a5UL },
-    { &fnv_test_str[199], (Fnv32_t) 0xfa823dd5UL },
-    { &fnv_test_str[200], (Fnv32_t) 0x0c6c58b9UL },
-    { &fnv_test_str[201], (Fnv32_t) 0xe2dbccd5UL },
-    { &fnv_test_str[202], (Fnv32_t) 0xdb7f50f9UL },
-    { NULL, 0 }
-};
-
-/* FNV-1a 32 bit test vectors */
-struct fnv1a_32_test_vector fnv1a_32_vector[] = {
-    { &fnv_test_str[0], (Fnv32_t) 0x811c9dc5UL },
-    { &fnv_test_str[1], (Fnv32_t) 0xe40c292cUL },
-    { &fnv_test_str[2], (Fnv32_t) 0xe70c2de5UL },
-    { &fnv_test_str[3], (Fnv32_t) 0xe60c2c52UL },
-    { &fnv_test_str[4], (Fnv32_t) 0xe10c2473UL },
-    { &fnv_test_str[5], (Fnv32_t) 0xe00c22e0UL },
-    { &fnv_test_str[6], (Fnv32_t) 0xe30c2799UL },
-    { &fnv_test_str[7], (Fnv32_t) 0x6222e842UL },
-    { &fnv_test_str[8], (Fnv32_t) 0xa9f37ed7UL },
-    { &fnv_test_str[9], (Fnv32_t) 0x3f5076efUL },
-    { &fnv_test_str[10], (Fnv32_t) 0x39aaa18aUL },
-    { &fnv_test_str[11], (Fnv32_t) 0xbf9cf968UL },
-    { &fnv_test_str[12], (Fnv32_t) 0x050c5d1fUL },
-    { &fnv_test_str[13], (Fnv32_t) 0x2b24d044UL },
-    { &fnv_test_str[14], (Fnv32_t) 0x9d2c3f7fUL },
-    { &fnv_test_str[15], (Fnv32_t) 0x7729c516UL },
-    { &fnv_test_str[16], (Fnv32_t) 0xb91d6109UL },
-    { &fnv_test_str[17], (Fnv32_t) 0x931ae6a0UL },
-    { &fnv_test_str[18], (Fnv32_t) 0x052255dbUL },
-    { &fnv_test_str[19], (Fnv32_t) 0xbef39fe6UL },
-    { &fnv_test_str[20], (Fnv32_t) 0x6150ac75UL },
-    { &fnv_test_str[21], (Fnv32_t) 0x9aab3a3dUL },
-    { &fnv_test_str[22], (Fnv32_t) 0x519c4c3eUL },
-    { &fnv_test_str[23], (Fnv32_t) 0x0c1c9eb8UL },
-    { &fnv_test_str[24], (Fnv32_t) 0x5f299f4eUL },
-    { &fnv_test_str[25], (Fnv32_t) 0xef8580f3UL },
-    { &fnv_test_str[26], (Fnv32_t) 0xac297727UL },
-    { &fnv_test_str[27], (Fnv32_t) 0x4546b9c0UL },
-    { &fnv_test_str[28], (Fnv32_t) 0xbd564e7dUL },
-    { &fnv_test_str[29], (Fnv32_t) 0x6bdd5c67UL },
-    { &fnv_test_str[30], (Fnv32_t) 0xdd77ed30UL },
-    { &fnv_test_str[31], (Fnv32_t) 0xf4ca9683UL },
-    { &fnv_test_str[32], (Fnv32_t) 0x4aeb9bd0UL },
-    { &fnv_test_str[33], (Fnv32_t) 0xe0e67ad0UL },
-    { &fnv_test_str[34], (Fnv32_t) 0xc2d32fa8UL },
-    { &fnv_test_str[35], (Fnv32_t) 0x7f743fb7UL },
-    { &fnv_test_str[36], (Fnv32_t) 0x6900631fUL },
-    { &fnv_test_str[37], (Fnv32_t) 0xc59c990eUL },
-    { &fnv_test_str[38], (Fnv32_t) 0x448524fdUL },
-    { &fnv_test_str[39], (Fnv32_t) 0xd49930d5UL },
-    { &fnv_test_str[40], (Fnv32_t) 0x1c85c7caUL },
-    { &fnv_test_str[41], (Fnv32_t) 0x0229fe89UL },
-    { &fnv_test_str[42], (Fnv32_t) 0x2c469265UL },
-    { &fnv_test_str[43], (Fnv32_t) 0xce566940UL },
-    { &fnv_test_str[44], (Fnv32_t) 0x8bdd8ec7UL },
-    { &fnv_test_str[45], (Fnv32_t) 0x34787625UL },
-    { &fnv_test_str[46], (Fnv32_t) 0xd3ca6290UL },
-    { &fnv_test_str[47], (Fnv32_t) 0xddeaf039UL },
-    { &fnv_test_str[48], (Fnv32_t) 0xc0e64870UL },
-    { &fnv_test_str[49], (Fnv32_t) 0xdad35570UL },
-    { &fnv_test_str[50], (Fnv32_t) 0x5a740578UL },
-    { &fnv_test_str[51], (Fnv32_t) 0x5b004d15UL },
-    { &fnv_test_str[52], (Fnv32_t) 0x6a9c09cdUL },
-    { &fnv_test_str[53], (Fnv32_t) 0x2384f10aUL },
-    { &fnv_test_str[54], (Fnv32_t) 0xda993a47UL },
-    { &fnv_test_str[55], (Fnv32_t) 0x8227df4fUL },
-    { &fnv_test_str[56], (Fnv32_t) 0x4c298165UL },
-    { &fnv_test_str[57], (Fnv32_t) 0xfc563735UL },
-    { &fnv_test_str[58], (Fnv32_t) 0x8cb91483UL },
-    { &fnv_test_str[59], (Fnv32_t) 0x775bf5d0UL },
-    { &fnv_test_str[60], (Fnv32_t) 0xd5c428d0UL },
-    { &fnv_test_str[61], (Fnv32_t) 0x34cc0ea3UL },
-    { &fnv_test_str[62], (Fnv32_t) 0xea3b4cb7UL },
-    { &fnv_test_str[63], (Fnv32_t) 0x8e59f029UL },
-    { &fnv_test_str[64], (Fnv32_t) 0x2094de2bUL },
-    { &fnv_test_str[65], (Fnv32_t) 0xa65a0ad4UL },
-    { &fnv_test_str[66], (Fnv32_t) 0x9bbee5f4UL },
-    { &fnv_test_str[67], (Fnv32_t) 0xbe836343UL },
-    { &fnv_test_str[68], (Fnv32_t) 0x22d5344eUL },
-    { &fnv_test_str[69], (Fnv32_t) 0x19a1470cUL },
-    { &fnv_test_str[70], (Fnv32_t) 0x4a56b1ffUL },
-    { &fnv_test_str[71], (Fnv32_t) 0x70b8e86fUL },
-    { &fnv_test_str[72], (Fnv32_t) 0x0a5b4a39UL },
-    { &fnv_test_str[73], (Fnv32_t) 0xb5c3f670UL },
-    { &fnv_test_str[74], (Fnv32_t) 0x53cc3f70UL },
-    { &fnv_test_str[75], (Fnv32_t) 0xc03b0a99UL },
-    { &fnv_test_str[76], (Fnv32_t) 0x7259c415UL },
-    { &fnv_test_str[77], (Fnv32_t) 0x4095108bUL },
-    { &fnv_test_str[78], (Fnv32_t) 0x7559bdb1UL },
-    { &fnv_test_str[79], (Fnv32_t) 0xb3bf0bbcUL },
-    { &fnv_test_str[80], (Fnv32_t) 0x2183ff1cUL },
-    { &fnv_test_str[81], (Fnv32_t) 0x2bd54279UL },
-    { &fnv_test_str[82], (Fnv32_t) 0x23a156caUL },
-    { &fnv_test_str[83], (Fnv32_t) 0x64e2d7e4UL },
-    { &fnv_test_str[84], (Fnv32_t) 0x683af69aUL },
-    { &fnv_test_str[85], (Fnv32_t) 0xaed2346eUL },
-    { &fnv_test_str[86], (Fnv32_t) 0x4f9f2cabUL },
-    { &fnv_test_str[87], (Fnv32_t) 0x02935131UL },
-    { &fnv_test_str[88], (Fnv32_t) 0xc48fb86dUL },
-    { &fnv_test_str[89], (Fnv32_t) 0x2269f369UL },
-    { &fnv_test_str[90], (Fnv32_t) 0xc18fb3b4UL },
-    { &fnv_test_str[91], (Fnv32_t) 0x50ef1236UL },
-    { &fnv_test_str[92], (Fnv32_t) 0xc28fb547UL },
-    { &fnv_test_str[93], (Fnv32_t) 0x96c3bf47UL },
-    { &fnv_test_str[94], (Fnv32_t) 0xbf8fb08eUL },
-    { &fnv_test_str[95], (Fnv32_t) 0xf3e4d49cUL },
-    { &fnv_test_str[96], (Fnv32_t) 0x32179058UL },
-    { &fnv_test_str[97], (Fnv32_t) 0x280bfee6UL },
-    { &fnv_test_str[98], (Fnv32_t) 0x30178d32UL },
-    { &fnv_test_str[99], (Fnv32_t) 0x21addaf8UL },
-    { &fnv_test_str[100], (Fnv32_t) 0x4217a988UL },
-    { &fnv_test_str[101], (Fnv32_t) 0x772633d6UL },
-    { &fnv_test_str[102], (Fnv32_t) 0x08a3d11eUL },
-    { &fnv_test_str[103], (Fnv32_t) 0xb7e2323aUL },
-    { &fnv_test_str[104], (Fnv32_t) 0x07a3cf8bUL },
-    { &fnv_test_str[105], (Fnv32_t) 0x91dfb7d1UL },
-    { &fnv_test_str[106], (Fnv32_t) 0x06a3cdf8UL },
-    { &fnv_test_str[107], (Fnv32_t) 0x6bdd3d68UL },
-    { &fnv_test_str[108], (Fnv32_t) 0x1d5636a7UL },
-    { &fnv_test_str[109], (Fnv32_t) 0xd5b808e5UL },
-    { &fnv_test_str[110], (Fnv32_t) 0x1353e852UL },
-    { &fnv_test_str[111], (Fnv32_t) 0xbf16b916UL },
-    { &fnv_test_str[112], (Fnv32_t) 0xa55b89edUL },
-    { &fnv_test_str[113], (Fnv32_t) 0x3c1a2017UL },
-    { &fnv_test_str[114], (Fnv32_t) 0x0588b13cUL },
-    { &fnv_test_str[115], (Fnv32_t) 0xf22f0174UL },
-    { &fnv_test_str[116], (Fnv32_t) 0xe83641e1UL },
-    { &fnv_test_str[117], (Fnv32_t) 0x6e69b533UL },
-    { &fnv_test_str[118], (Fnv32_t) 0xf1760448UL },
-    { &fnv_test_str[119], (Fnv32_t) 0x64c8bd58UL },
-    { &fnv_test_str[120], (Fnv32_t) 0x97b4ea23UL },
-    { &fnv_test_str[121], (Fnv32_t) 0x9a4e92e6UL },
-    { &fnv_test_str[122], (Fnv32_t) 0xcfb14012UL },
-    { &fnv_test_str[123], (Fnv32_t) 0xf01b2511UL },
-    { &fnv_test_str[124], (Fnv32_t) 0x0bbb59c3UL },
-    { &fnv_test_str[125], (Fnv32_t) 0xce524afaUL },
-    { &fnv_test_str[126], (Fnv32_t) 0xdd16ef45UL },
-    { &fnv_test_str[127], (Fnv32_t) 0x60648bb3UL },
-    { &fnv_test_str[128], (Fnv32_t) 0x7fa4bcfcUL },
-    { &fnv_test_str[129], (Fnv32_t) 0x5053ae17UL },
-    { &fnv_test_str[130], (Fnv32_t) 0xc9302890UL },
-    { &fnv_test_str[131], (Fnv32_t) 0x956ded32UL },
-    { &fnv_test_str[132], (Fnv32_t) 0x9136db84UL },
-    { &fnv_test_str[133], (Fnv32_t) 0xdf9d3323UL },
-    { &fnv_test_str[134], (Fnv32_t) 0x32bb6cd0UL },
-    { &fnv_test_str[135], (Fnv32_t) 0xc8f8385bUL },
-    { &fnv_test_str[136], (Fnv32_t) 0xeb08bfbaUL },
-    { &fnv_test_str[137], (Fnv32_t) 0x62cc8e3dUL },
-    { &fnv_test_str[138], (Fnv32_t) 0xc3e20f5cUL },
-    { &fnv_test_str[139], (Fnv32_t) 0x39e97f17UL },
-    { &fnv_test_str[140], (Fnv32_t) 0x7837b203UL },
-    { &fnv_test_str[141], (Fnv32_t) 0x319e877bUL },
-    { &fnv_test_str[142], (Fnv32_t) 0xd3e63f89UL },
-    { &fnv_test_str[143], (Fnv32_t) 0x29b50b38UL },
-    { &fnv_test_str[144], (Fnv32_t) 0x5ed678b8UL },
-    { &fnv_test_str[145], (Fnv32_t) 0xb0d5b793UL },
-    { &fnv_test_str[146], (Fnv32_t) 0x52450be5UL },
-    { &fnv_test_str[147], (Fnv32_t) 0xfa72d767UL },
-    { &fnv_test_str[148], (Fnv32_t) 0x95066709UL },
-    { &fnv_test_str[149], (Fnv32_t) 0x7f52e123UL },
-    { &fnv_test_str[150], (Fnv32_t) 0x76966481UL },
-    { &fnv_test_str[151], (Fnv32_t) 0x063258b0UL },
-    { &fnv_test_str[152], (Fnv32_t) 0x2ded6e8aUL },
-    { &fnv_test_str[153], (Fnv32_t) 0xb07d7c52UL },
-    { &fnv_test_str[154], (Fnv32_t) 0xd0c71b71UL },
-    { &fnv_test_str[155], (Fnv32_t) 0xf684f1bdUL },
-    { &fnv_test_str[156], (Fnv32_t) 0x868ecfa8UL },
-    { &fnv_test_str[157], (Fnv32_t) 0xf794f684UL },
-    { &fnv_test_str[158], (Fnv32_t) 0xd19701c3UL },
-    { &fnv_test_str[159], (Fnv32_t) 0x346e171eUL },
-    { &fnv_test_str[160], (Fnv32_t) 0x91f8f676UL },
-    { &fnv_test_str[161], (Fnv32_t) 0x0bf58848UL },
-    { &fnv_test_str[162], (Fnv32_t) 0x6317b6d1UL },
-    { &fnv_test_str[163], (Fnv32_t) 0xafad4c54UL },
-    { &fnv_test_str[164], (Fnv32_t) 0x0f25681eUL },
-    { &fnv_test_str[165], (Fnv32_t) 0x91b18d49UL },
-    { &fnv_test_str[166], (Fnv32_t) 0x7d61c12eUL },
-    { &fnv_test_str[167], (Fnv32_t) 0x5147d25cUL },
-    { &fnv_test_str[168], (Fnv32_t) 0x9a8b6805UL },
-    { &fnv_test_str[169], (Fnv32_t) 0x4cd2a447UL },
-    { &fnv_test_str[170], (Fnv32_t) 0x1e549b14UL },
-    { &fnv_test_str[171], (Fnv32_t) 0x2fe1b574UL },
-    { &fnv_test_str[172], (Fnv32_t) 0xcf0cd31eUL },
-    { &fnv_test_str[173], (Fnv32_t) 0x6c471669UL },
-    { &fnv_test_str[174], (Fnv32_t) 0x0e5eef1eUL },
-    { &fnv_test_str[175], (Fnv32_t) 0x2bed3602UL },
-    { &fnv_test_str[176], (Fnv32_t) 0xb26249e0UL },
-    { &fnv_test_str[177], (Fnv32_t) 0x2c9b86a4UL },
-    { &fnv_test_str[178], (Fnv32_t) 0xe415e2bbUL },
-    { &fnv_test_str[179], (Fnv32_t) 0x18a98d1dUL },
-    { &fnv_test_str[180], (Fnv32_t) 0xb7df8b7bUL },
-    { &fnv_test_str[181], (Fnv32_t) 0x241e9075UL },
-    { &fnv_test_str[182], (Fnv32_t) 0x063f70ddUL },
-    { &fnv_test_str[183], (Fnv32_t) 0x0295aed9UL },
-    { &fnv_test_str[184], (Fnv32_t) 0x56a7f781UL },
-    { &fnv_test_str[185], (Fnv32_t) 0x253bc645UL },
-    { &fnv_test_str[186], (Fnv32_t) 0x46610921UL },
-    { &fnv_test_str[187], (Fnv32_t) 0x7c1577f9UL },
-    { &fnv_test_str[188], (Fnv32_t) 0x512b2851UL },
-    { &fnv_test_str[189], (Fnv32_t) 0x76823999UL },
-    { &fnv_test_str[190], (Fnv32_t) 0xc0586935UL },
-    { &fnv_test_str[191], (Fnv32_t) 0xf3415c85UL },
-    { &fnv_test_str[192], (Fnv32_t) 0x0ae4ff65UL },
-    { &fnv_test_str[193], (Fnv32_t) 0x58b79725UL },
-    { &fnv_test_str[194], (Fnv32_t) 0xdea43aa5UL },
-    { &fnv_test_str[195], (Fnv32_t) 0x2bb3be35UL },
-    { &fnv_test_str[196], (Fnv32_t) 0xea777a45UL },
-    { &fnv_test_str[197], (Fnv32_t) 0x8f21c305UL },
-    { &fnv_test_str[198], (Fnv32_t) 0x5c9d0865UL },
-    { &fnv_test_str[199], (Fnv32_t) 0xfa823dd5UL },
-    { &fnv_test_str[200], (Fnv32_t) 0x21a27271UL },
-    { &fnv_test_str[201], (Fnv32_t) 0x83c5c6d5UL },
-    { &fnv_test_str[202], (Fnv32_t) 0x813b0881UL },
-    { NULL, 0 }
-};
-
-/* FNV-0 64 bit test vectors */
-#if defined(HAVE_64BIT_LONG_LONG)
-struct fnv0_64_test_vector fnv0_64_vector[] = {
-    { &fnv_test_str[0], (Fnv64_t) 0x0000000000000000ULL },
-    { &fnv_test_str[1], (Fnv64_t) 0x0000000000000061ULL },
-    { &fnv_test_str[2], (Fnv64_t) 0x0000000000000062ULL },
-    { &fnv_test_str[3], (Fnv64_t) 0x0000000000000063ULL },
-    { &fnv_test_str[4], (Fnv64_t) 0x0000000000000064ULL },
-    { &fnv_test_str[5], (Fnv64_t) 0x0000000000000065ULL },
-    { &fnv_test_str[6], (Fnv64_t) 0x0000000000000066ULL },
-    { &fnv_test_str[7], (Fnv64_t) 0x000066000000ad3dULL },
-    { &fnv_test_str[8], (Fnv64_t) 0x015a8f0001265ec8ULL },
-    { &fnv_test_str[9], (Fnv64_t) 0x733fc501f4330dbaULL },
-    { &fnv_test_str[10], (Fnv64_t) 0x08697c51f2c0536fULL },
-    { &fnv_test_str[11], (Fnv64_t) 0x0b91ae3f7ccdc5efULL },
-    { &fnv_test_str[12], (Fnv64_t) 0x0000000000000000ULL },
-    { &fnv_test_str[13], (Fnv64_t) 0x000061000000a4d3ULL },
-    { &fnv_test_str[14], (Fnv64_t) 0x000062000000a686ULL },
-    { &fnv_test_str[15], (Fnv64_t) 0x000063000000a839ULL },
-    { &fnv_test_str[16], (Fnv64_t) 0x000064000000a9ecULL },
-    { &fnv_test_str[17], (Fnv64_t) 0x000065000000ab9fULL },
-    { &fnv_test_str[18], (Fnv64_t) 0x000066000000ad52ULL },
-    { &fnv_test_str[19], (Fnv64_t) 0x015a8f0001265ea7ULL },
-    { &fnv_test_str[20], (Fnv64_t) 0x733fc501f4330dd8ULL },
-    { &fnv_test_str[21], (Fnv64_t) 0x08697c51f2c0530eULL },
-    { &fnv_test_str[22], (Fnv64_t) 0x0b91ae3f7ccdc59dULL },
-    { &fnv_test_str[23], (Fnv64_t) 0x765104e111a7551dULL },
-    { &fnv_test_str[24], (Fnv64_t) 0x000063000000a851ULL },
-    { &fnv_test_str[25], (Fnv64_t) 0x01508a00011e01ccULL },
-    { &fnv_test_str[26], (Fnv64_t) 0x59dc4a01e5fd0dcaULL },
-    { &fnv_test_str[27], (Fnv64_t) 0xae5f8b39ccfe6e59ULL },
-    { &fnv_test_str[28], (Fnv64_t) 0x4ac7ec3754558154ULL },
-    { &fnv_test_str[29], (Fnv64_t) 0x6737b6044d4ac19cULL },
-    { &fnv_test_str[30], (Fnv64_t) 0xae6be54f5606fc63ULL },
-    { &fnv_test_str[31], (Fnv64_t) 0x685308cf2ddedc58ULL },
-    { &fnv_test_str[32], (Fnv64_t) 0x23f4500af1b069fbULL },
-    { &fnv_test_str[33], (Fnv64_t) 0xc88dfd98aec415a1ULL },
-    { &fnv_test_str[34], (Fnv64_t) 0x8d5b8b70f730c0fbULL },
-    { &fnv_test_str[35], (Fnv64_t) 0x634eebf407d7eae4ULL },
-    { &fnv_test_str[36], (Fnv64_t) 0x9705d3a953e4211eULL },
-    { &fnv_test_str[37], (Fnv64_t) 0x8307c6b98ca4459fULL },
-    { &fnv_test_str[38], (Fnv64_t) 0x4a7c4c49fb224d0cULL },
-    { &fnv_test_str[39], (Fnv64_t) 0xb382adb5bb48eb6eULL },
-    { &fnv_test_str[40], (Fnv64_t) 0x01508a00011e01a3ULL },
-    { &fnv_test_str[41], (Fnv64_t) 0x59dc4a01e5fd0da4ULL },
-    { &fnv_test_str[42], (Fnv64_t) 0xae5f8b39ccfe6e3eULL },
-    { &fnv_test_str[43], (Fnv64_t) 0x4ac7ec375455813bULL },
-    { &fnv_test_str[44], (Fnv64_t) 0x6737b6044d4ac1bcULL },
-    { &fnv_test_str[45], (Fnv64_t) 0xae6be54f5606fc14ULL },
-    { &fnv_test_str[46], (Fnv64_t) 0x685308cf2ddedc39ULL },
-    { &fnv_test_str[47], (Fnv64_t) 0x23f4500af1b06988ULL },
-    { &fnv_test_str[48], (Fnv64_t) 0xc88dfd98aec41581ULL },
-    { &fnv_test_str[49], (Fnv64_t) 0x8d5b8b70f730c093ULL },
-    { &fnv_test_str[50], (Fnv64_t) 0x634eebf407d7ea81ULL },
-    { &fnv_test_str[51], (Fnv64_t) 0x9705d3a953e4216cULL },
-    { &fnv_test_str[52], (Fnv64_t) 0x8307c6b98ca445faULL },
-    { &fnv_test_str[53], (Fnv64_t) 0x4a7c4c49fb224d2dULL },
-    { &fnv_test_str[54], (Fnv64_t) 0xb382adb5bb48eb64ULL },
-    { &fnv_test_str[55], (Fnv64_t) 0x4ff899cd3ce80beaULL },
-    { &fnv_test_str[56], (Fnv64_t) 0x000063000000a84cULL },
-    { &fnv_test_str[57], (Fnv64_t) 0x01508500011df956ULL },
-    { &fnv_test_str[58], (Fnv64_t) 0x59cb5501e5eead46ULL },
-    { &fnv_test_str[59], (Fnv64_t) 0x832eb839b4906d81ULL },
-    { &fnv_test_str[60], (Fnv64_t) 0x78d08b0dd16a1213ULL },
-    { &fnv_test_str[61], (Fnv64_t) 0xb46e5b7ad73cb628ULL },
-    { &fnv_test_str[62], (Fnv64_t) 0xd43b99bbbc298596ULL },
-    { &fnv_test_str[63], (Fnv64_t) 0xcacbd000ba8dfd86ULL },
-    { &fnv_test_str[64], (Fnv64_t) 0x264ff73cff45ca92ULL },
-    { &fnv_test_str[65], (Fnv64_t) 0x5fabaea5c3973661ULL },
-    { &fnv_test_str[66], (Fnv64_t) 0x27f024ab59f166bbULL },
-    { &fnv_test_str[67], (Fnv64_t) 0xce750a29d5318fa4ULL },
-    { &fnv_test_str[68], (Fnv64_t) 0x026fe915433713d5ULL },
-    { &fnv_test_str[69], (Fnv64_t) 0x5b3ce4213696b2e5ULL },
-    { &fnv_test_str[70], (Fnv64_t) 0x01508500011df924ULL },
-    { &fnv_test_str[71], (Fnv64_t) 0x59cb5501e5eead22ULL },
-    { &fnv_test_str[72], (Fnv64_t) 0x832eb839b4906df2ULL },
-    { &fnv_test_str[73], (Fnv64_t) 0x78d08b0dd16a1233ULL },
-    { &fnv_test_str[74], (Fnv64_t) 0xb46e5b7ad73cb649ULL },
-    { &fnv_test_str[75], (Fnv64_t) 0xd43b99bbbc2985f8ULL },
-    { &fnv_test_str[76], (Fnv64_t) 0xcacbd000ba8dfde2ULL },
-    { &fnv_test_str[77], (Fnv64_t) 0x264ff73cff45cab2ULL },
-    { &fnv_test_str[78], (Fnv64_t) 0x5fabaea5c3973616ULL },
-    { &fnv_test_str[79], (Fnv64_t) 0x27f024ab59f166d3ULL },
-    { &fnv_test_str[80], (Fnv64_t) 0xce750a29d5318fc1ULL },
-    { &fnv_test_str[81], (Fnv64_t) 0x026fe915433713acULL },
-    { &fnv_test_str[82], (Fnv64_t) 0x5b3ce4213696b2efULL },
-    { &fnv_test_str[83], (Fnv64_t) 0x9f2a896fc211fb1fULL },
-    { &fnv_test_str[84], (Fnv64_t) 0x000068000000b0d1ULL },
-    { &fnv_test_str[85], (Fnv64_t) 0x01618900012c7323ULL },
-    { &fnv_test_str[86], (Fnv64_t) 0x3fa86e63bc7d03c8ULL },
-    { &fnv_test_str[87], (Fnv64_t) 0xa8375b79486d6cd8ULL },
-    { &fnv_test_str[88], (Fnv64_t) 0xa0d18504e316ac54ULL },
-    { &fnv_test_str[89], (Fnv64_t) 0x08a97b0004e7fe54ULL },
-    { &fnv_test_str[90], (Fnv64_t) 0xa0d18504e316ac57ULL },
-    { &fnv_test_str[91], (Fnv64_t) 0x1152f60009cffda9ULL },
-    { &fnv_test_str[92], (Fnv64_t) 0xa0d18504e316ac56ULL },
-    { &fnv_test_str[93], (Fnv64_t) 0x19fc71000eb7fcfeULL },
-    { &fnv_test_str[94], (Fnv64_t) 0xa0d18504e316ac51ULL },
-    { &fnv_test_str[95], (Fnv64_t) 0x22a5ec00139ffa53ULL },
-    { &fnv_test_str[96], (Fnv64_t) 0x29bed00139779a33ULL },
-    { &fnv_test_str[97], (Fnv64_t) 0x4dbc81014e3c19f5ULL },
-    { &fnv_test_str[98], (Fnv64_t) 0x29bed00139779a3dULL },
-    { &fnv_test_str[99], (Fnv64_t) 0x81a72b016b9f7573ULL },
-    { &fnv_test_str[100], (Fnv64_t) 0x29bed00139779a23ULL },
-    { &fnv_test_str[101], (Fnv64_t) 0xd85411019cbbce45ULL },
-    { &fnv_test_str[102], (Fnv64_t) 0xf548616b8621d657ULL },
-    { &fnv_test_str[103], (Fnv64_t) 0xebd3e0b4eb7f35d5ULL },
-    { &fnv_test_str[104], (Fnv64_t) 0xf548616b8621d654ULL },
-    { &fnv_test_str[105], (Fnv64_t) 0xebd3ddb4eb7f30bcULL },
-    { &fnv_test_str[106], (Fnv64_t) 0xf548616b8621d655ULL },
-    { &fnv_test_str[107], (Fnv64_t) 0xebd3deb4eb7f326fULL },
-    { &fnv_test_str[108], (Fnv64_t) 0x581cb60340ab0968ULL },
-    { &fnv_test_str[109], (Fnv64_t) 0x63d2af86e2a0fbb8ULL },
-    { &fnv_test_str[110], (Fnv64_t) 0x581cb70340ab0b37ULL },
-    { &fnv_test_str[111], (Fnv64_t) 0x63d63186e2a40e75ULL },
-    { &fnv_test_str[112], (Fnv64_t) 0x581cc40340ab212eULL },
-    { &fnv_test_str[113], (Fnv64_t) 0x64023f86e2c9612aULL },
-    { &fnv_test_str[114], (Fnv64_t) 0xdbda6a26c33c909fULL },
-    { &fnv_test_str[115], (Fnv64_t) 0xd0b2feddbfe9be2dULL },
-    { &fnv_test_str[116], (Fnv64_t) 0x9c9eae3f5d037decULL },
-    { &fnv_test_str[117], (Fnv64_t) 0x252001ab0ceef804ULL },
-    { &fnv_test_str[118], (Fnv64_t) 0x4456a56f9e05cfefULL },
-    { &fnv_test_str[119], (Fnv64_t) 0x250b0ba983e0531dULL },
-    { &fnv_test_str[120], (Fnv64_t) 0x52b007213b27b33eULL },
-    { &fnv_test_str[121], (Fnv64_t) 0xcbf29ce484222325ULL },
-    { &fnv_test_str[122], (Fnv64_t) 0xaf63bd4c8601b7dfULL },
-    { &fnv_test_str[123], (Fnv64_t) 0x128599ccddae09f8ULL },
-    { &fnv_test_str[124], (Fnv64_t) 0x270e4f1caebaf068ULL },
-    { &fnv_test_str[125], (Fnv64_t) 0x01517d497446a395ULL },
-    { &fnv_test_str[126], (Fnv64_t) 0x9af5a29a89450b40ULL },
-    { &fnv_test_str[127], (Fnv64_t) 0xb502f6c063ba72e8ULL },
-    { &fnv_test_str[128], (Fnv64_t) 0xacf41561498ca7dfULL },
-    { &fnv_test_str[129], (Fnv64_t) 0x6be8c2423a351542ULL },
-    { &fnv_test_str[130], (Fnv64_t) 0xd04f1f6da96ce4a3ULL },
-    { &fnv_test_str[131], (Fnv64_t) 0x69eb9a8f282c7235ULL },
-    { &fnv_test_str[132], (Fnv64_t) 0x6a7e5a418f77cfc5ULL },
-    { &fnv_test_str[133], (Fnv64_t) 0xbcaf568ddc2ecba0ULL },
-    { &fnv_test_str[134], (Fnv64_t) 0xb03b5cc4c38f8b1fULL },
-    { &fnv_test_str[135], (Fnv64_t) 0xf89a9f51432db828ULL },
-    { &fnv_test_str[136], (Fnv64_t) 0x549e856be6103429ULL },
-    { &fnv_test_str[137], (Fnv64_t) 0x3cf50d224d29377aULL },
-    { &fnv_test_str[138], (Fnv64_t) 0xdb762df418c10c37ULL },
-    { &fnv_test_str[139], (Fnv64_t) 0xfeeb4226b0e9a6baULL },
-    { &fnv_test_str[140], (Fnv64_t) 0x7004a4cd9310c052ULL },
-    { &fnv_test_str[141], (Fnv64_t) 0xd1c727d7f5329276ULL },
-    { &fnv_test_str[142], (Fnv64_t) 0xbe313796596ce908ULL },
-    { &fnv_test_str[143], (Fnv64_t) 0x768f67ede090fcc5ULL },
-    { &fnv_test_str[144], (Fnv64_t) 0xa81563cc9db9bfc3ULL },
-    { &fnv_test_str[145], (Fnv64_t) 0x47194043c55197a8ULL },
-    { &fnv_test_str[146], (Fnv64_t) 0xc99d81864aebab02ULL },
-    { &fnv_test_str[147], (Fnv64_t) 0xcc1f161b235ea4a2ULL },
-    { &fnv_test_str[148], (Fnv64_t) 0xaadab0c420ecd434ULL },
-    { &fnv_test_str[149], (Fnv64_t) 0x6b3c034d6f44d740ULL },
-    { &fnv_test_str[150], (Fnv64_t) 0x73a45e850602cbc6ULL },
-    { &fnv_test_str[151], (Fnv64_t) 0x72360f04f0cd227bULL },
-    { &fnv_test_str[152], (Fnv64_t) 0xa9ca80be384a778fULL },
-    { &fnv_test_str[153], (Fnv64_t) 0xd4085e66906889e3ULL },
-    { &fnv_test_str[154], (Fnv64_t) 0x93aa8b2748efdbc8ULL },
-    { &fnv_test_str[155], (Fnv64_t) 0x6f8cd678407436a2ULL },
-    { &fnv_test_str[156], (Fnv64_t) 0xf39a43d4dc8be4c7ULL },
-    { &fnv_test_str[157], (Fnv64_t) 0xd7f5cec91125d245ULL },
-    { &fnv_test_str[158], (Fnv64_t) 0x691d7b73be18adc4ULL },
-    { &fnv_test_str[159], (Fnv64_t) 0xf4361e01caf6b691ULL },
-    { &fnv_test_str[160], (Fnv64_t) 0xde7d8264f64be089ULL },
-    { &fnv_test_str[161], (Fnv64_t) 0xa34ff43e5545c06fULL },
-    { &fnv_test_str[162], (Fnv64_t) 0x181f0b8e908a2bdeULL },
-    { &fnv_test_str[163], (Fnv64_t) 0x28a965b78ddbc071ULL },
-    { &fnv_test_str[164], (Fnv64_t) 0xead9cea0e3cc6ae5ULL },
-    { &fnv_test_str[165], (Fnv64_t) 0x0b6743153b43ebbaULL },
-    { &fnv_test_str[166], (Fnv64_t) 0xa7aa3f012c74528dULL },
-    { &fnv_test_str[167], (Fnv64_t) 0x2d5d8ad7f9dffeb7ULL },
-    { &fnv_test_str[168], (Fnv64_t) 0x00750fb6e19624eaULL },
-    { &fnv_test_str[169], (Fnv64_t) 0x01c125a4e6c76c82ULL },
-    { &fnv_test_str[170], (Fnv64_t) 0x3fde3afac0722f1fULL },
-    { &fnv_test_str[171], (Fnv64_t) 0xd7c3eaf4abaa379dULL },
-    { &fnv_test_str[172], (Fnv64_t) 0xd2217e1c923c9f3fULL },
-    { &fnv_test_str[173], (Fnv64_t) 0x82d0a2e3b725caf6ULL },
-    { &fnv_test_str[174], (Fnv64_t) 0x0a10bee8eeb72e4fULL },
-    { &fnv_test_str[175], (Fnv64_t) 0xc530e8723e72c6fdULL },
-    { &fnv_test_str[176], (Fnv64_t) 0xd8d34dcd2e7bad99ULL },
-    { &fnv_test_str[177], (Fnv64_t) 0xecf77466e9a2baf3ULL },
-    { &fnv_test_str[178], (Fnv64_t) 0xde3d2ddb043b9666ULL },
-    { &fnv_test_str[179], (Fnv64_t) 0xd1cc824e1a8157d8ULL },
-    { &fnv_test_str[180], (Fnv64_t) 0x7d5c68ecbc90512eULL },
-    { &fnv_test_str[181], (Fnv64_t) 0x2f7c691b1d7c76d8ULL },
-    { &fnv_test_str[182], (Fnv64_t) 0x5d88c2bad3a46bc8ULL },
-    { &fnv_test_str[183], (Fnv64_t) 0xdf107320276647a0ULL },
-    { &fnv_test_str[184], (Fnv64_t) 0x0f78f22e7e70e9bcULL },
-    { &fnv_test_str[185], (Fnv64_t) 0x8c67be5c80f67d04ULL },
-    { &fnv_test_str[186], (Fnv64_t) 0x07c1adfa4d019194ULL },
-    { &fnv_test_str[187], (Fnv64_t) 0xce1312420c5b1af4ULL },
-    { &fnv_test_str[188], (Fnv64_t) 0x043a41b2dc53ab24ULL },
-    { &fnv_test_str[189], (Fnv64_t) 0x0b038eebf7340860ULL },
-    { &fnv_test_str[190], (Fnv64_t) 0x1bcd837353fb69b0ULL },
-    { &fnv_test_str[191], (Fnv64_t) 0x46f992fc59eff180ULL },
-    { &fnv_test_str[192], (Fnv64_t) 0x497678ee29ae79c0ULL },
-    { &fnv_test_str[193], (Fnv64_t) 0xb10a62280ddd4450ULL },
-    { &fnv_test_str[194], (Fnv64_t) 0x35eb228db4d68140ULL },
-    { &fnv_test_str[195], (Fnv64_t) 0x8b350e86d9470870ULL },
-    { &fnv_test_str[196], (Fnv64_t) 0x4e1fbdb2812e9540ULL },
-    { &fnv_test_str[197], (Fnv64_t) 0x051e080df69a0600ULL },
-    { &fnv_test_str[198], (Fnv64_t) 0x45e1e8ae54dadb40ULL },
-    { &fnv_test_str[199], (Fnv64_t) 0x0000000000000000ULL },
-    { &fnv_test_str[200], (Fnv64_t) 0xcd73806290557064ULL },
-    { &fnv_test_str[201], (Fnv64_t) 0x2613a37bbe0317c8ULL },
-    { &fnv_test_str[202], (Fnv64_t) 0x1480e21fcf2ae5e4ULL },
-    { NULL, (Fnv64_t) 0 }
-};
-#else /* HAVE_64BIT_LONG_LONG */
-struct fnv0_64_test_vector fnv0_64_vector[] = {
-    { &fnv_test_str[0], (Fnv64_t) {0x00000000UL, 0x00000000UL} },
-    { &fnv_test_str[1], (Fnv64_t) {0x00000061UL, 0x00000000UL} },
-    { &fnv_test_str[2], (Fnv64_t) {0x00000062UL, 0x00000000UL} },
-    { &fnv_test_str[3], (Fnv64_t) {0x00000063UL, 0x00000000UL} },
-    { &fnv_test_str[4], (Fnv64_t) {0x00000064UL, 0x00000000UL} },
-    { &fnv_test_str[5], (Fnv64_t) {0x00000065UL, 0x00000000UL} },
-    { &fnv_test_str[6], (Fnv64_t) {0x00000066UL, 0x00000000UL} },
-    { &fnv_test_str[7], (Fnv64_t) {0x0000ad3dUL, 0x00006600UL} },
-    { &fnv_test_str[8], (Fnv64_t) {0x01265ec8UL, 0x015a8f00UL} },
-    { &fnv_test_str[9], (Fnv64_t) {0xf4330dbaUL, 0x733fc501UL} },
-    { &fnv_test_str[10], (Fnv64_t) {0xf2c0536fUL, 0x08697c51UL} },
-    { &fnv_test_str[11], (Fnv64_t) {0x7ccdc5efUL, 0x0b91ae3fUL} },
-    { &fnv_test_str[12], (Fnv64_t) {0x00000000UL, 0x00000000UL} },
-    { &fnv_test_str[13], (Fnv64_t) {0x0000a4d3UL, 0x00006100UL} },
-    { &fnv_test_str[14], (Fnv64_t) {0x0000a686UL, 0x00006200UL} },
-    { &fnv_test_str[15], (Fnv64_t) {0x0000a839UL, 0x00006300UL} },
-    { &fnv_test_str[16], (Fnv64_t) {0x0000a9ecUL, 0x00006400UL} },
-    { &fnv_test_str[17], (Fnv64_t) {0x0000ab9fUL, 0x00006500UL} },
-    { &fnv_test_str[18], (Fnv64_t) {0x0000ad52UL, 0x00006600UL} },
-    { &fnv_test_str[19], (Fnv64_t) {0x01265ea7UL, 0x015a8f00UL} },
-    { &fnv_test_str[20], (Fnv64_t) {0xf4330dd8UL, 0x733fc501UL} },
-    { &fnv_test_str[21], (Fnv64_t) {0xf2c0530eUL, 0x08697c51UL} },
-    { &fnv_test_str[22], (Fnv64_t) {0x7ccdc59dUL, 0x0b91ae3fUL} },
-    { &fnv_test_str[23], (Fnv64_t) {0x11a7551dUL, 0x765104e1UL} },
-    { &fnv_test_str[24], (Fnv64_t) {0x0000a851UL, 0x00006300UL} },
-    { &fnv_test_str[25], (Fnv64_t) {0x011e01ccUL, 0x01508a00UL} },
-    { &fnv_test_str[26], (Fnv64_t) {0xe5fd0dcaUL, 0x59dc4a01UL} },
-    { &fnv_test_str[27], (Fnv64_t) {0xccfe6e59UL, 0xae5f8b39UL} },
-    { &fnv_test_str[28], (Fnv64_t) {0x54558154UL, 0x4ac7ec37UL} },
-    { &fnv_test_str[29], (Fnv64_t) {0x4d4ac19cUL, 0x6737b604UL} },
-    { &fnv_test_str[30], (Fnv64_t) {0x5606fc63UL, 0xae6be54fUL} },
-    { &fnv_test_str[31], (Fnv64_t) {0x2ddedc58UL, 0x685308cfUL} },
-    { &fnv_test_str[32], (Fnv64_t) {0xf1b069fbUL, 0x23f4500aUL} },
-    { &fnv_test_str[33], (Fnv64_t) {0xaec415a1UL, 0xc88dfd98UL} },
-    { &fnv_test_str[34], (Fnv64_t) {0xf730c0fbUL, 0x8d5b8b70UL} },
-    { &fnv_test_str[35], (Fnv64_t) {0x07d7eae4UL, 0x634eebf4UL} },
-    { &fnv_test_str[36], (Fnv64_t) {0x53e4211eUL, 0x9705d3a9UL} },
-    { &fnv_test_str[37], (Fnv64_t) {0x8ca4459fUL, 0x8307c6b9UL} },
-    { &fnv_test_str[38], (Fnv64_t) {0xfb224d0cUL, 0x4a7c4c49UL} },
-    { &fnv_test_str[39], (Fnv64_t) {0xbb48eb6eUL, 0xb382adb5UL} },
-    { &fnv_test_str[40], (Fnv64_t) {0x011e01a3UL, 0x01508a00UL} },
-    { &fnv_test_str[41], (Fnv64_t) {0xe5fd0da4UL, 0x59dc4a01UL} },
-    { &fnv_test_str[42], (Fnv64_t) {0xccfe6e3eUL, 0xae5f8b39UL} },
-    { &fnv_test_str[43], (Fnv64_t) {0x5455813bUL, 0x4ac7ec37UL} },
-    { &fnv_test_str[44], (Fnv64_t) {0x4d4ac1bcUL, 0x6737b604UL} },
-    { &fnv_test_str[45], (Fnv64_t) {0x5606fc14UL, 0xae6be54fUL} },
-    { &fnv_test_str[46], (Fnv64_t) {0x2ddedc39UL, 0x685308cfUL} },
-    { &fnv_test_str[47], (Fnv64_t) {0xf1b06988UL, 0x23f4500aUL} },
-    { &fnv_test_str[48], (Fnv64_t) {0xaec41581UL, 0xc88dfd98UL} },
-    { &fnv_test_str[49], (Fnv64_t) {0xf730c093UL, 0x8d5b8b70UL} },
-    { &fnv_test_str[50], (Fnv64_t) {0x07d7ea81UL, 0x634eebf4UL} },
-    { &fnv_test_str[51], (Fnv64_t) {0x53e4216cUL, 0x9705d3a9UL} },
-    { &fnv_test_str[52], (Fnv64_t) {0x8ca445faUL, 0x8307c6b9UL} },
-    { &fnv_test_str[53], (Fnv64_t) {0xfb224d2dUL, 0x4a7c4c49UL} },
-    { &fnv_test_str[54], (Fnv64_t) {0xbb48eb64UL, 0xb382adb5UL} },
-    { &fnv_test_str[55], (Fnv64_t) {0x3ce80beaUL, 0x4ff899cdUL} },
-    { &fnv_test_str[56], (Fnv64_t) {0x0000a84cUL, 0x00006300UL} },
-    { &fnv_test_str[57], (Fnv64_t) {0x011df956UL, 0x01508500UL} },
-    { &fnv_test_str[58], (Fnv64_t) {0xe5eead46UL, 0x59cb5501UL} },
-    { &fnv_test_str[59], (Fnv64_t) {0xb4906d81UL, 0x832eb839UL} },
-    { &fnv_test_str[60], (Fnv64_t) {0xd16a1213UL, 0x78d08b0dUL} },
-    { &fnv_test_str[61], (Fnv64_t) {0xd73cb628UL, 0xb46e5b7aUL} },
-    { &fnv_test_str[62], (Fnv64_t) {0xbc298596UL, 0xd43b99bbUL} },
-    { &fnv_test_str[63], (Fnv64_t) {0xba8dfd86UL, 0xcacbd000UL} },
-    { &fnv_test_str[64], (Fnv64_t) {0xff45ca92UL, 0x264ff73cUL} },
-    { &fnv_test_str[65], (Fnv64_t) {0xc3973661UL, 0x5fabaea5UL} },
-    { &fnv_test_str[66], (Fnv64_t) {0x59f166bbUL, 0x27f024abUL} },
-    { &fnv_test_str[67], (Fnv64_t) {0xd5318fa4UL, 0xce750a29UL} },
-    { &fnv_test_str[68], (Fnv64_t) {0x433713d5UL, 0x026fe915UL} },
-    { &fnv_test_str[69], (Fnv64_t) {0x3696b2e5UL, 0x5b3ce421UL} },
-    { &fnv_test_str[70], (Fnv64_t) {0x011df924UL, 0x01508500UL} },
-    { &fnv_test_str[71], (Fnv64_t) {0xe5eead22UL, 0x59cb5501UL} },
-    { &fnv_test_str[72], (Fnv64_t) {0xb4906df2UL, 0x832eb839UL} },
-    { &fnv_test_str[73], (Fnv64_t) {0xd16a1233UL, 0x78d08b0dUL} },
-    { &fnv_test_str[74], (Fnv64_t) {0xd73cb649UL, 0xb46e5b7aUL} },
-    { &fnv_test_str[75], (Fnv64_t) {0xbc2985f8UL, 0xd43b99bbUL} },
-    { &fnv_test_str[76], (Fnv64_t) {0xba8dfde2UL, 0xcacbd000UL} },
-    { &fnv_test_str[77], (Fnv64_t) {0xff45cab2UL, 0x264ff73cUL} },
-    { &fnv_test_str[78], (Fnv64_t) {0xc3973616UL, 0x5fabaea5UL} },
-    { &fnv_test_str[79], (Fnv64_t) {0x59f166d3UL, 0x27f024abUL} },
-    { &fnv_test_str[80], (Fnv64_t) {0xd5318fc1UL, 0xce750a29UL} },
-    { &fnv_test_str[81], (Fnv64_t) {0x433713acUL, 0x026fe915UL} },
-    { &fnv_test_str[82], (Fnv64_t) {0x3696b2efUL, 0x5b3ce421UL} },
-    { &fnv_test_str[83], (Fnv64_t) {0xc211fb1fUL, 0x9f2a896fUL} },
-    { &fnv_test_str[84], (Fnv64_t) {0x0000b0d1UL, 0x00006800UL} },
-    { &fnv_test_str[85], (Fnv64_t) {0x012c7323UL, 0x01618900UL} },
-    { &fnv_test_str[86], (Fnv64_t) {0xbc7d03c8UL, 0x3fa86e63UL} },
-    { &fnv_test_str[87], (Fnv64_t) {0x486d6cd8UL, 0xa8375b79UL} },
-    { &fnv_test_str[88], (Fnv64_t) {0xe316ac54UL, 0xa0d18504UL} },
-    { &fnv_test_str[89], (Fnv64_t) {0x04e7fe54UL, 0x08a97b00UL} },
-    { &fnv_test_str[90], (Fnv64_t) {0xe316ac57UL, 0xa0d18504UL} },
-    { &fnv_test_str[91], (Fnv64_t) {0x09cffda9UL, 0x1152f600UL} },
-    { &fnv_test_str[92], (Fnv64_t) {0xe316ac56UL, 0xa0d18504UL} },
-    { &fnv_test_str[93], (Fnv64_t) {0x0eb7fcfeUL, 0x19fc7100UL} },
-    { &fnv_test_str[94], (Fnv64_t) {0xe316ac51UL, 0xa0d18504UL} },
-    { &fnv_test_str[95], (Fnv64_t) {0x139ffa53UL, 0x22a5ec00UL} },
-    { &fnv_test_str[96], (Fnv64_t) {0x39779a33UL, 0x29bed001UL} },
-    { &fnv_test_str[97], (Fnv64_t) {0x4e3c19f5UL, 0x4dbc8101UL} },
-    { &fnv_test_str[98], (Fnv64_t) {0x39779a3dUL, 0x29bed001UL} },
-    { &fnv_test_str[99], (Fnv64_t) {0x6b9f7573UL, 0x81a72b01UL} },
-    { &fnv_test_str[100], (Fnv64_t) {0x39779a23UL, 0x29bed001UL} },
-    { &fnv_test_str[101], (Fnv64_t) {0x9cbbce45UL, 0xd8541101UL} },
-    { &fnv_test_str[102], (Fnv64_t) {0x8621d657UL, 0xf548616bUL} },
-    { &fnv_test_str[103], (Fnv64_t) {0xeb7f35d5UL, 0xebd3e0b4UL} },
-    { &fnv_test_str[104], (Fnv64_t) {0x8621d654UL, 0xf548616bUL} },
-    { &fnv_test_str[105], (Fnv64_t) {0xeb7f30bcUL, 0xebd3ddb4UL} },
-    { &fnv_test_str[106], (Fnv64_t) {0x8621d655UL, 0xf548616bUL} },
-    { &fnv_test_str[107], (Fnv64_t) {0xeb7f326fUL, 0xebd3deb4UL} },
-    { &fnv_test_str[108], (Fnv64_t) {0x40ab0968UL, 0x581cb603UL} },
-    { &fnv_test_str[109], (Fnv64_t) {0xe2a0fbb8UL, 0x63d2af86UL} },
-    { &fnv_test_str[110], (Fnv64_t) {0x40ab0b37UL, 0x581cb703UL} },
-    { &fnv_test_str[111], (Fnv64_t) {0xe2a40e75UL, 0x63d63186UL} },
-    { &fnv_test_str[112], (Fnv64_t) {0x40ab212eUL, 0x581cc403UL} },
-    { &fnv_test_str[113], (Fnv64_t) {0xe2c9612aUL, 0x64023f86UL} },
-    { &fnv_test_str[114], (Fnv64_t) {0xc33c909fUL, 0xdbda6a26UL} },
-    { &fnv_test_str[115], (Fnv64_t) {0xbfe9be2dUL, 0xd0b2feddUL} },
-    { &fnv_test_str[116], (Fnv64_t) {0x5d037decUL, 0x9c9eae3fUL} },
-    { &fnv_test_str[117], (Fnv64_t) {0x0ceef804UL, 0x252001abUL} },
-    { &fnv_test_str[118], (Fnv64_t) {0x9e05cfefUL, 0x4456a56fUL} },
-    { &fnv_test_str[119], (Fnv64_t) {0x83e0531dUL, 0x250b0ba9UL} },
-    { &fnv_test_str[120], (Fnv64_t) {0x3b27b33eUL, 0x52b00721UL} },
-    { &fnv_test_str[121], (Fnv64_t) {0x84222325UL, 0xcbf29ce4UL} },
-    { &fnv_test_str[122], (Fnv64_t) {0x8601b7dfUL, 0xaf63bd4cUL} },
-    { &fnv_test_str[123], (Fnv64_t) {0xddae09f8UL, 0x128599ccUL} },
-    { &fnv_test_str[124], (Fnv64_t) {0xaebaf068UL, 0x270e4f1cUL} },
-    { &fnv_test_str[125], (Fnv64_t) {0x7446a395UL, 0x01517d49UL} },
-    { &fnv_test_str[126], (Fnv64_t) {0x89450b40UL, 0x9af5a29aUL} },
-    { &fnv_test_str[127], (Fnv64_t) {0x63ba72e8UL, 0xb502f6c0UL} },
-    { &fnv_test_str[128], (Fnv64_t) {0x498ca7dfUL, 0xacf41561UL} },
-    { &fnv_test_str[129], (Fnv64_t) {0x3a351542UL, 0x6be8c242UL} },
-    { &fnv_test_str[130], (Fnv64_t) {0xa96ce4a3UL, 0xd04f1f6dUL} },
-    { &fnv_test_str[131], (Fnv64_t) {0x282c7235UL, 0x69eb9a8fUL} },
-    { &fnv_test_str[132], (Fnv64_t) {0x8f77cfc5UL, 0x6a7e5a41UL} },
-    { &fnv_test_str[133], (Fnv64_t) {0xdc2ecba0UL, 0xbcaf568dUL} },
-    { &fnv_test_str[134], (Fnv64_t) {0xc38f8b1fUL, 0xb03b5cc4UL} },
-    { &fnv_test_str[135], (Fnv64_t) {0x432db828UL, 0xf89a9f51UL} },
-    { &fnv_test_str[136], (Fnv64_t) {0xe6103429UL, 0x549e856bUL} },
-    { &fnv_test_str[137], (Fnv64_t) {0x4d29377aUL, 0x3cf50d22UL} },
-    { &fnv_test_str[138], (Fnv64_t) {0x18c10c37UL, 0xdb762df4UL} },
-    { &fnv_test_str[139], (Fnv64_t) {0xb0e9a6baUL, 0xfeeb4226UL} },
-    { &fnv_test_str[140], (Fnv64_t) {0x9310c052UL, 0x7004a4cdUL} },
-    { &fnv_test_str[141], (Fnv64_t) {0xf5329276UL, 0xd1c727d7UL} },
-    { &fnv_test_str[142], (Fnv64_t) {0x596ce908UL, 0xbe313796UL} },
-    { &fnv_test_str[143], (Fnv64_t) {0xe090fcc5UL, 0x768f67edUL} },
-    { &fnv_test_str[144], (Fnv64_t) {0x9db9bfc3UL, 0xa81563ccUL} },
-    { &fnv_test_str[145], (Fnv64_t) {0xc55197a8UL, 0x47194043UL} },
-    { &fnv_test_str[146], (Fnv64_t) {0x4aebab02UL, 0xc99d8186UL} },
-    { &fnv_test_str[147], (Fnv64_t) {0x235ea4a2UL, 0xcc1f161bUL} },
-    { &fnv_test_str[148], (Fnv64_t) {0x20ecd434UL, 0xaadab0c4UL} },
-    { &fnv_test_str[149], (Fnv64_t) {0x6f44d740UL, 0x6b3c034dUL} },
-    { &fnv_test_str[150], (Fnv64_t) {0x0602cbc6UL, 0x73a45e85UL} },
-    { &fnv_test_str[151], (Fnv64_t) {0xf0cd227bUL, 0x72360f04UL} },
-    { &fnv_test_str[152], (Fnv64_t) {0x384a778fUL, 0xa9ca80beUL} },
-    { &fnv_test_str[153], (Fnv64_t) {0x906889e3UL, 0xd4085e66UL} },
-    { &fnv_test_str[154], (Fnv64_t) {0x48efdbc8UL, 0x93aa8b27UL} },
-    { &fnv_test_str[155], (Fnv64_t) {0x407436a2UL, 0x6f8cd678UL} },
-    { &fnv_test_str[156], (Fnv64_t) {0xdc8be4c7UL, 0xf39a43d4UL} },
-    { &fnv_test_str[157], (Fnv64_t) {0x1125d245UL, 0xd7f5cec9UL} },
-    { &fnv_test_str[158], (Fnv64_t) {0xbe18adc4UL, 0x691d7b73UL} },
-    { &fnv_test_str[159], (Fnv64_t) {0xcaf6b691UL, 0xf4361e01UL} },
-    { &fnv_test_str[160], (Fnv64_t) {0xf64be089UL, 0xde7d8264UL} },
-    { &fnv_test_str[161], (Fnv64_t) {0x5545c06fUL, 0xa34ff43eUL} },
-    { &fnv_test_str[162], (Fnv64_t) {0x908a2bdeUL, 0x181f0b8eUL} },
-    { &fnv_test_str[163], (Fnv64_t) {0x8ddbc071UL, 0x28a965b7UL} },
-    { &fnv_test_str[164], (Fnv64_t) {0xe3cc6ae5UL, 0xead9cea0UL} },
-    { &fnv_test_str[165], (Fnv64_t) {0x3b43ebbaUL, 0x0b674315UL} },
-    { &fnv_test_str[166], (Fnv64_t) {0x2c74528dUL, 0xa7aa3f01UL} },
-    { &fnv_test_str[167], (Fnv64_t) {0xf9dffeb7UL, 0x2d5d8ad7UL} },
-    { &fnv_test_str[168], (Fnv64_t) {0xe19624eaUL, 0x00750fb6UL} },
-    { &fnv_test_str[169], (Fnv64_t) {0xe6c76c82UL, 0x01c125a4UL} },
-    { &fnv_test_str[170], (Fnv64_t) {0xc0722f1fUL, 0x3fde3afaUL} },
-    { &fnv_test_str[171], (Fnv64_t) {0xabaa379dUL, 0xd7c3eaf4UL} },
-    { &fnv_test_str[172], (Fnv64_t) {0x923c9f3fUL, 0xd2217e1cUL} },
-    { &fnv_test_str[173], (Fnv64_t) {0xb725caf6UL, 0x82d0a2e3UL} },
-    { &fnv_test_str[174], (Fnv64_t) {0xeeb72e4fUL, 0x0a10bee8UL} },
-    { &fnv_test_str[175], (Fnv64_t) {0x3e72c6fdUL, 0xc530e872UL} },
-    { &fnv_test_str[176], (Fnv64_t) {0x2e7bad99UL, 0xd8d34dcdUL} },
-    { &fnv_test_str[177], (Fnv64_t) {0xe9a2baf3UL, 0xecf77466UL} },
-    { &fnv_test_str[178], (Fnv64_t) {0x043b9666UL, 0xde3d2ddbUL} },
-    { &fnv_test_str[179], (Fnv64_t) {0x1a8157d8UL, 0xd1cc824eUL} },
-    { &fnv_test_str[180], (Fnv64_t) {0xbc90512eUL, 0x7d5c68ecUL} },
-    { &fnv_test_str[181], (Fnv64_t) {0x1d7c76d8UL, 0x2f7c691bUL} },
-    { &fnv_test_str[182], (Fnv64_t) {0xd3a46bc8UL, 0x5d88c2baUL} },
-    { &fnv_test_str[183], (Fnv64_t) {0x276647a0UL, 0xdf107320UL} },
-    { &fnv_test_str[184], (Fnv64_t) {0x7e70e9bcUL, 0x0f78f22eUL} },
-    { &fnv_test_str[185], (Fnv64_t) {0x80f67d04UL, 0x8c67be5cUL} },
-    { &fnv_test_str[186], (Fnv64_t) {0x4d019194UL, 0x07c1adfaUL} },
-    { &fnv_test_str[187], (Fnv64_t) {0x0c5b1af4UL, 0xce131242UL} },
-    { &fnv_test_str[188], (Fnv64_t) {0xdc53ab24UL, 0x043a41b2UL} },
-    { &fnv_test_str[189], (Fnv64_t) {0xf7340860UL, 0x0b038eebUL} },
-    { &fnv_test_str[190], (Fnv64_t) {0x53fb69b0UL, 0x1bcd8373UL} },
-    { &fnv_test_str[191], (Fnv64_t) {0x59eff180UL, 0x46f992fcUL} },
-    { &fnv_test_str[192], (Fnv64_t) {0x29ae79c0UL, 0x497678eeUL} },
-    { &fnv_test_str[193], (Fnv64_t) {0x0ddd4450UL, 0xb10a6228UL} },
-    { &fnv_test_str[194], (Fnv64_t) {0xb4d68140UL, 0x35eb228dUL} },
-    { &fnv_test_str[195], (Fnv64_t) {0xd9470870UL, 0x8b350e86UL} },
-    { &fnv_test_str[196], (Fnv64_t) {0x812e9540UL, 0x4e1fbdb2UL} },
-    { &fnv_test_str[197], (Fnv64_t) {0xf69a0600UL, 0x051e080dUL} },
-    { &fnv_test_str[198], (Fnv64_t) {0x54dadb40UL, 0x45e1e8aeUL} },
-    { &fnv_test_str[199], (Fnv64_t) {0x00000000UL, 0x00000000UL} },
-    { &fnv_test_str[200], (Fnv64_t) {0x90557064UL, 0xcd738062UL} },
-    { &fnv_test_str[201], (Fnv64_t) {0xbe0317c8UL, 0x2613a37bUL} },
-    { &fnv_test_str[202], (Fnv64_t) {0xcf2ae5e4UL, 0x1480e21fUL} },
-    { NULL, (Fnv64_t) {0,0} }
-};
-#endif /* HAVE_64BIT_LONG_LONG */
-
-/* FNV-1 64 bit test vectors */
-#if defined(HAVE_64BIT_LONG_LONG)
-struct fnv1_64_test_vector fnv1_64_vector[] = {
-    { &fnv_test_str[0], (Fnv64_t) 0xcbf29ce484222325ULL },
-    { &fnv_test_str[1], (Fnv64_t) 0xaf63bd4c8601b7beULL },
-    { &fnv_test_str[2], (Fnv64_t) 0xaf63bd4c8601b7bdULL },
-    { &fnv_test_str[3], (Fnv64_t) 0xaf63bd4c8601b7bcULL },
-    { &fnv_test_str[4], (Fnv64_t) 0xaf63bd4c8601b7bbULL },
-    { &fnv_test_str[5], (Fnv64_t) 0xaf63bd4c8601b7baULL },
-    { &fnv_test_str[6], (Fnv64_t) 0xaf63bd4c8601b7b9ULL },
-    { &fnv_test_str[7], (Fnv64_t) 0x08326207b4eb2f34ULL },
-    { &fnv_test_str[8], (Fnv64_t) 0xd8cbc7186ba13533ULL },
-    { &fnv_test_str[9], (Fnv64_t) 0x0378817ee2ed65cbULL },
-    { &fnv_test_str[10], (Fnv64_t) 0xd329d59b9963f790ULL },
-    { &fnv_test_str[11], (Fnv64_t) 0x340d8765a4dda9c2ULL },
-    { &fnv_test_str[12], (Fnv64_t) 0xaf63bd4c8601b7dfULL },
-    { &fnv_test_str[13], (Fnv64_t) 0x08326707b4eb37daULL },
-    { &fnv_test_str[14], (Fnv64_t) 0x08326607b4eb3627ULL },
-    { &fnv_test_str[15], (Fnv64_t) 0x08326507b4eb3474ULL },
-    { &fnv_test_str[16], (Fnv64_t) 0x08326407b4eb32c1ULL },
-    { &fnv_test_str[17], (Fnv64_t) 0x08326307b4eb310eULL },
-    { &fnv_test_str[18], (Fnv64_t) 0x08326207b4eb2f5bULL },
-    { &fnv_test_str[19], (Fnv64_t) 0xd8cbc7186ba1355cULL },
-    { &fnv_test_str[20], (Fnv64_t) 0x0378817ee2ed65a9ULL },
-    { &fnv_test_str[21], (Fnv64_t) 0xd329d59b9963f7f1ULL },
-    { &fnv_test_str[22], (Fnv64_t) 0x340d8765a4dda9b0ULL },
-    { &fnv_test_str[23], (Fnv64_t) 0x50a6d3b724a774a6ULL },
-    { &fnv_test_str[24], (Fnv64_t) 0x08326507b4eb341cULL },
-    { &fnv_test_str[25], (Fnv64_t) 0xd8d5c8186ba98bfbULL },
-    { &fnv_test_str[26], (Fnv64_t) 0x1ccefc7ef118dbefULL },
-    { &fnv_test_str[27], (Fnv64_t) 0x0c92fab3ad3db77aULL },
-    { &fnv_test_str[28], (Fnv64_t) 0x9b77794f5fdec421ULL },
-    { &fnv_test_str[29], (Fnv64_t) 0x0ac742dfe7874433ULL },
-    { &fnv_test_str[30], (Fnv64_t) 0xd7dad5766ad8e2deULL },
-    { &fnv_test_str[31], (Fnv64_t) 0xa1bb96378e897f5bULL },
-    { &fnv_test_str[32], (Fnv64_t) 0x5b3f9b6733a367d2ULL },
-    { &fnv_test_str[33], (Fnv64_t) 0xb07ce25cbea969f6ULL },
-    { &fnv_test_str[34], (Fnv64_t) 0x8d9e9997f9df0d6aULL },
-    { &fnv_test_str[35], (Fnv64_t) 0x838c673d9603cb7bULL },
-    { &fnv_test_str[36], (Fnv64_t) 0x8b5ee8a5e872c273ULL },
-    { &fnv_test_str[37], (Fnv64_t) 0x4507c4e9fb00690cULL },
-    { &fnv_test_str[38], (Fnv64_t) 0x4c9ca59581b27f45ULL },
-    { &fnv_test_str[39], (Fnv64_t) 0xe0aca20b624e4235ULL },
-    { &fnv_test_str[40], (Fnv64_t) 0xd8d5c8186ba98b94ULL },
-    { &fnv_test_str[41], (Fnv64_t) 0x1ccefc7ef118db81ULL },
-    { &fnv_test_str[42], (Fnv64_t) 0x0c92fab3ad3db71dULL },
-    { &fnv_test_str[43], (Fnv64_t) 0x9b77794f5fdec44eULL },
-    { &fnv_test_str[44], (Fnv64_t) 0x0ac742dfe7874413ULL },
-    { &fnv_test_str[45], (Fnv64_t) 0xd7dad5766ad8e2a9ULL },
-    { &fnv_test_str[46], (Fnv64_t) 0xa1bb96378e897f3aULL },
-    { &fnv_test_str[47], (Fnv64_t) 0x5b3f9b6733a367a1ULL },
-    { &fnv_test_str[48], (Fnv64_t) 0xb07ce25cbea969d6ULL },
-    { &fnv_test_str[49], (Fnv64_t) 0x8d9e9997f9df0d02ULL },
-    { &fnv_test_str[50], (Fnv64_t) 0x838c673d9603cb1eULL },
-    { &fnv_test_str[51], (Fnv64_t) 0x8b5ee8a5e872c201ULL },
-    { &fnv_test_str[52], (Fnv64_t) 0x4507c4e9fb006969ULL },
-    { &fnv_test_str[53], (Fnv64_t) 0x4c9ca59581b27f64ULL },
-    { &fnv_test_str[54], (Fnv64_t) 0xe0aca20b624e423fULL },
-    { &fnv_test_str[55], (Fnv64_t) 0x13998e580afa800fULL },
-    { &fnv_test_str[56], (Fnv64_t) 0x08326507b4eb3401ULL },
-    { &fnv_test_str[57], (Fnv64_t) 0xd8d5ad186ba95dc1ULL },
-    { &fnv_test_str[58], (Fnv64_t) 0x1c72e17ef0ca4e97ULL },
-    { &fnv_test_str[59], (Fnv64_t) 0x2183c1b327c38ae6ULL },
-    { &fnv_test_str[60], (Fnv64_t) 0xb66d096c914504f2ULL },
-    { &fnv_test_str[61], (Fnv64_t) 0x404bf57ad8476757ULL },
-    { &fnv_test_str[62], (Fnv64_t) 0x887976bd815498bbULL },
-    { &fnv_test_str[63], (Fnv64_t) 0x3afd7f02c2bf85a5ULL },
-    { &fnv_test_str[64], (Fnv64_t) 0xfc4476b0eb70177fULL },
-    { &fnv_test_str[65], (Fnv64_t) 0x186d2da00f77ecbaULL },
-    { &fnv_test_str[66], (Fnv64_t) 0xf97140fa48c74066ULL },
-    { &fnv_test_str[67], (Fnv64_t) 0xa2b1cf49aa926d37ULL },
-    { &fnv_test_str[68], (Fnv64_t) 0x0690712cd6cf940cULL },
-    { &fnv_test_str[69], (Fnv64_t) 0xf7045b3102b8906eULL },
-    { &fnv_test_str[70], (Fnv64_t) 0xd8d5ad186ba95db3ULL },
-    { &fnv_test_str[71], (Fnv64_t) 0x1c72e17ef0ca4ef3ULL },
-    { &fnv_test_str[72], (Fnv64_t) 0x2183c1b327c38a95ULL },
-    { &fnv_test_str[73], (Fnv64_t) 0xb66d096c914504d2ULL },
-    { &fnv_test_str[74], (Fnv64_t) 0x404bf57ad8476736ULL },
-    { &fnv_test_str[75], (Fnv64_t) 0x887976bd815498d5ULL },
-    { &fnv_test_str[76], (Fnv64_t) 0x3afd7f02c2bf85c1ULL },
-    { &fnv_test_str[77], (Fnv64_t) 0xfc4476b0eb70175fULL },
-    { &fnv_test_str[78], (Fnv64_t) 0x186d2da00f77eccdULL },
-    { &fnv_test_str[79], (Fnv64_t) 0xf97140fa48c7400eULL },
-    { &fnv_test_str[80], (Fnv64_t) 0xa2b1cf49aa926d52ULL },
-    { &fnv_test_str[81], (Fnv64_t) 0x0690712cd6cf9475ULL },
-    { &fnv_test_str[82], (Fnv64_t) 0xf7045b3102b89064ULL },
-    { &fnv_test_str[83], (Fnv64_t) 0x74f762479f9d6aeaULL },
-    { &fnv_test_str[84], (Fnv64_t) 0x08326007b4eb2b9cULL },
-    { &fnv_test_str[85], (Fnv64_t) 0xd8c4c9186b9b1a14ULL },
-    { &fnv_test_str[86], (Fnv64_t) 0x7b495389bdbdd4c7ULL },
-    { &fnv_test_str[87], (Fnv64_t) 0x3b6dba0d69908e25ULL },
-    { &fnv_test_str[88], (Fnv64_t) 0xd6b2b17bf4b71261ULL },
-    { &fnv_test_str[89], (Fnv64_t) 0x447bfb7f98e615b5ULL },
-    { &fnv_test_str[90], (Fnv64_t) 0xd6b2b17bf4b71262ULL },
-    { &fnv_test_str[91], (Fnv64_t) 0x3bd2807f93fe1660ULL },
-    { &fnv_test_str[92], (Fnv64_t) 0xd6b2b17bf4b71263ULL },
-    { &fnv_test_str[93], (Fnv64_t) 0x3329057f8f16170bULL },
-    { &fnv_test_str[94], (Fnv64_t) 0xd6b2b17bf4b71264ULL },
-    { &fnv_test_str[95], (Fnv64_t) 0x2a7f8a7f8a2e19b6ULL },
-    { &fnv_test_str[96], (Fnv64_t) 0x23d3767e64b2f98aULL },
-    { &fnv_test_str[97], (Fnv64_t) 0xff768d7e4f9d86a4ULL },
-    { &fnv_test_str[98], (Fnv64_t) 0x23d3767e64b2f984ULL },
-    { &fnv_test_str[99], (Fnv64_t) 0xccd1837e334e4aa6ULL },
-    { &fnv_test_str[100], (Fnv64_t) 0x23d3767e64b2f99aULL },
-    { &fnv_test_str[101], (Fnv64_t) 0x7691fd7e028f6754ULL },
-    { &fnv_test_str[102], (Fnv64_t) 0x34ad3b1041204318ULL },
-    { &fnv_test_str[103], (Fnv64_t) 0xa29e749ea9d201c8ULL },
-    { &fnv_test_str[104], (Fnv64_t) 0x34ad3b104120431bULL },
-    { &fnv_test_str[105], (Fnv64_t) 0xa29e779ea9d206e1ULL },
-    { &fnv_test_str[106], (Fnv64_t) 0x34ad3b104120431aULL },
-    { &fnv_test_str[107], (Fnv64_t) 0xa29e769ea9d2052eULL },
-    { &fnv_test_str[108], (Fnv64_t) 0x02a17ebca4aa3497ULL },
-    { &fnv_test_str[109], (Fnv64_t) 0x229ef18bcd375c95ULL },
-    { &fnv_test_str[110], (Fnv64_t) 0x02a17dbca4aa32c8ULL },
-    { &fnv_test_str[111], (Fnv64_t) 0x229b6f8bcd3449d8ULL },
-    { &fnv_test_str[112], (Fnv64_t) 0x02a184bca4aa3ed5ULL },
-    { &fnv_test_str[113], (Fnv64_t) 0x22b3618bcd48c3efULL },
-    { &fnv_test_str[114], (Fnv64_t) 0x5c2c346706186f36ULL },
-    { &fnv_test_str[115], (Fnv64_t) 0xb78c410f5b84f8c2ULL },
-    { &fnv_test_str[116], (Fnv64_t) 0xed9478212b267395ULL },
-    { &fnv_test_str[117], (Fnv64_t) 0xd9bbb55c5256662fULL },
-    { &fnv_test_str[118], (Fnv64_t) 0x8c54f0203249438aULL },
-    { &fnv_test_str[119], (Fnv64_t) 0xbd9790b5727dc37eULL },
-    { &fnv_test_str[120], (Fnv64_t) 0xa64e5f36c9e2b0e3ULL },
-    { &fnv_test_str[121], (Fnv64_t) 0x8fd0680da3088a04ULL },
-    { &fnv_test_str[122], (Fnv64_t) 0x67aad32c078284ccULL },
-    { &fnv_test_str[123], (Fnv64_t) 0xb37d55d81c57b331ULL },
-    { &fnv_test_str[124], (Fnv64_t) 0x55ac0f3829057c43ULL },
-    { &fnv_test_str[125], (Fnv64_t) 0xcb27f4b8e1b6cc20ULL },
-    { &fnv_test_str[126], (Fnv64_t) 0x26caf88bcbef2d19ULL },
-    { &fnv_test_str[127], (Fnv64_t) 0x8e6e063b97e61b8fULL },
-    { &fnv_test_str[128], (Fnv64_t) 0xb42750f7f3b7c37eULL },
-    { &fnv_test_str[129], (Fnv64_t) 0xf3c6ba64cf7ca99bULL },
-    { &fnv_test_str[130], (Fnv64_t) 0xebfb69b427ea80feULL },
-    { &fnv_test_str[131], (Fnv64_t) 0x39b50c3ed970f46cULL },
-    { &fnv_test_str[132], (Fnv64_t) 0x5b9b177aa3eb3e8aULL },
-    { &fnv_test_str[133], (Fnv64_t) 0x6510063ecf4ec903ULL },
-    { &fnv_test_str[134], (Fnv64_t) 0x2b3bbd2c00797c7aULL },
-    { &fnv_test_str[135], (Fnv64_t) 0xf1d6204ff5cb4aa7ULL },
-    { &fnv_test_str[136], (Fnv64_t) 0x4836e27ccf099f38ULL },
-    { &fnv_test_str[137], (Fnv64_t) 0x82efbb0dd073b44dULL },
-    { &fnv_test_str[138], (Fnv64_t) 0x4a80c282ffd7d4c6ULL },
-    { &fnv_test_str[139], (Fnv64_t) 0x305d1a9c9ee43bdfULL },
-    { &fnv_test_str[140], (Fnv64_t) 0x15c366948ffc6997ULL },
-    { &fnv_test_str[141], (Fnv64_t) 0x80153ae218916e7bULL },
-    { &fnv_test_str[142], (Fnv64_t) 0xfa23e2bdf9e2a9e1ULL },
-    { &fnv_test_str[143], (Fnv64_t) 0xd47e8d8a2333c6deULL },
-    { &fnv_test_str[144], (Fnv64_t) 0x7e128095f688b056ULL },
-    { &fnv_test_str[145], (Fnv64_t) 0x2f5356890efcedabULL },
-    { &fnv_test_str[146], (Fnv64_t) 0x95c2b383014f55c5ULL },
-    { &fnv_test_str[147], (Fnv64_t) 0x4727a5339ce6070fULL },
-    { &fnv_test_str[148], (Fnv64_t) 0xb0555ecd575108e9ULL },
-    { &fnv_test_str[149], (Fnv64_t) 0x48d785770bb4af37ULL },
-    { &fnv_test_str[150], (Fnv64_t) 0x09d4701c12af02b1ULL },
-    { &fnv_test_str[151], (Fnv64_t) 0x79f031e78f3cf62eULL },
-    { &fnv_test_str[152], (Fnv64_t) 0x52a1ee85db1b5a94ULL },
-    { &fnv_test_str[153], (Fnv64_t) 0x6bd95b2eb37fa6b8ULL },
-    { &fnv_test_str[154], (Fnv64_t) 0x74971b7077aef85dULL },
-    { &fnv_test_str[155], (Fnv64_t) 0xb4e4fae2ffcc1aadULL },
-    { &fnv_test_str[156], (Fnv64_t) 0x2bd48bd898b8f63aULL },
-    { &fnv_test_str[157], (Fnv64_t) 0xe9966ac1556257f6ULL },
-    { &fnv_test_str[158], (Fnv64_t) 0x92a3d1cd078ba293ULL },
-    { &fnv_test_str[159], (Fnv64_t) 0xf81175a482e20ab8ULL },
-    { &fnv_test_str[160], (Fnv64_t) 0x5bbb3de722e73048ULL },
-    { &fnv_test_str[161], (Fnv64_t) 0x6b4f363492b9f2beULL },
-    { &fnv_test_str[162], (Fnv64_t) 0xc2d559df73d59875ULL },
-    { &fnv_test_str[163], (Fnv64_t) 0xf75f62284bc7a8c2ULL },
-    { &fnv_test_str[164], (Fnv64_t) 0xda8dd8e116a9f1ccULL },
-    { &fnv_test_str[165], (Fnv64_t) 0xbdc1e6ab76057885ULL },
-    { &fnv_test_str[166], (Fnv64_t) 0xfec6a4238a1224a0ULL },
-    { &fnv_test_str[167], (Fnv64_t) 0xc03f40f3223e290eULL },
-    { &fnv_test_str[168], (Fnv64_t) 0x1ed21673466ffda9ULL },
-    { &fnv_test_str[169], (Fnv64_t) 0xdf70f906bb0dd2afULL },
-    { &fnv_test_str[170], (Fnv64_t) 0xf3dcda369f2af666ULL },
-    { &fnv_test_str[171], (Fnv64_t) 0x9ebb11573cdcebdeULL },
-    { &fnv_test_str[172], (Fnv64_t) 0x81c72d9077fedca0ULL },
-    { &fnv_test_str[173], (Fnv64_t) 0x0ec074a31be5fb15ULL },
-    { &fnv_test_str[174], (Fnv64_t) 0x2a8b3280b6c48f20ULL },
-    { &fnv_test_str[175], (Fnv64_t) 0xfd31777513309344ULL },
-    { &fnv_test_str[176], (Fnv64_t) 0x194534a86ad006b6ULL },
-    { &fnv_test_str[177], (Fnv64_t) 0x3be6fdf46e0cfe12ULL },
-    { &fnv_test_str[178], (Fnv64_t) 0x017cc137a07eb057ULL },
-    { &fnv_test_str[179], (Fnv64_t) 0x9428fc6e7d26b54dULL },
-    { &fnv_test_str[180], (Fnv64_t) 0x9aaa2e3603ef8ad7ULL },
-    { &fnv_test_str[181], (Fnv64_t) 0x82c6d3f3a0ccdf7dULL },
-    { &fnv_test_str[182], (Fnv64_t) 0xc86eeea00cf09b65ULL },
-    { &fnv_test_str[183], (Fnv64_t) 0x705f8189dbb58299ULL },
-    { &fnv_test_str[184], (Fnv64_t) 0x415a7f554391ca69ULL },
-    { &fnv_test_str[185], (Fnv64_t) 0xcfe3d49fa2bdc555ULL },
-    { &fnv_test_str[186], (Fnv64_t) 0xf0f9c56039b25191ULL },
-    { &fnv_test_str[187], (Fnv64_t) 0x7075cb6abd1d32d9ULL },
-    { &fnv_test_str[188], (Fnv64_t) 0x43c94e2c8b277509ULL },
-    { &fnv_test_str[189], (Fnv64_t) 0x3cbfd4e4ea670359ULL },
-    { &fnv_test_str[190], (Fnv64_t) 0xc05887810f4d019dULL },
-    { &fnv_test_str[191], (Fnv64_t) 0x14468ff93ac22dc5ULL },
-    { &fnv_test_str[192], (Fnv64_t) 0xebed699589d99c05ULL },
-    { &fnv_test_str[193], (Fnv64_t) 0x6d99f6df321ca5d5ULL },
-    { &fnv_test_str[194], (Fnv64_t) 0x0cd410d08c36d625ULL },
-    { &fnv_test_str[195], (Fnv64_t) 0xef1b2a2c86831d35ULL },
-    { &fnv_test_str[196], (Fnv64_t) 0x3b349c4d69ee5f05ULL },
-    { &fnv_test_str[197], (Fnv64_t) 0x55248ce88f45f035ULL },
-    { &fnv_test_str[198], (Fnv64_t) 0xaa69ca6a18a4c885ULL },
-    { &fnv_test_str[199], (Fnv64_t) 0x1fe3fce62bd816b5ULL },
-    { &fnv_test_str[200], (Fnv64_t) 0x0289a488a8df69d9ULL },
-    { &fnv_test_str[201], (Fnv64_t) 0x15e96e1613df98b5ULL },
-    { &fnv_test_str[202], (Fnv64_t) 0xe6be57375ad89b99ULL },
-    { NULL, (Fnv64_t) 0 }
-};
-#else /* HAVE_64BIT_LONG_LONG */
-struct fnv1_64_test_vector fnv1_64_vector[] = {
-    { &fnv_test_str[0], (Fnv64_t) {0x84222325UL, 0xcbf29ce4UL} },
-    { &fnv_test_str[1], (Fnv64_t) {0x8601b7beUL, 0xaf63bd4cUL} },
-    { &fnv_test_str[2], (Fnv64_t) {0x8601b7bdUL, 0xaf63bd4cUL} },
-    { &fnv_test_str[3], (Fnv64_t) {0x8601b7bcUL, 0xaf63bd4cUL} },
-    { &fnv_test_str[4], (Fnv64_t) {0x8601b7bbUL, 0xaf63bd4cUL} },
-    { &fnv_test_str[5], (Fnv64_t) {0x8601b7baUL, 0xaf63bd4cUL} },
-    { &fnv_test_str[6], (Fnv64_t) {0x8601b7b9UL, 0xaf63bd4cUL} },
-    { &fnv_test_str[7], (Fnv64_t) {0xb4eb2f34UL, 0x08326207UL} },
-    { &fnv_test_str[8], (Fnv64_t) {0x6ba13533UL, 0xd8cbc718UL} },
-    { &fnv_test_str[9], (Fnv64_t) {0xe2ed65cbUL, 0x0378817eUL} },
-    { &fnv_test_str[10], (Fnv64_t) {0x9963f790UL, 0xd329d59bUL} },
-    { &fnv_test_str[11], (Fnv64_t) {0xa4dda9c2UL, 0x340d8765UL} },
-    { &fnv_test_str[12], (Fnv64_t) {0x8601b7dfUL, 0xaf63bd4cUL} },
-    { &fnv_test_str[13], (Fnv64_t) {0xb4eb37daUL, 0x08326707UL} },
-    { &fnv_test_str[14], (Fnv64_t) {0xb4eb3627UL, 0x08326607UL} },
-    { &fnv_test_str[15], (Fnv64_t) {0xb4eb3474UL, 0x08326507UL} },
-    { &fnv_test_str[16], (Fnv64_t) {0xb4eb32c1UL, 0x08326407UL} },
-    { &fnv_test_str[17], (Fnv64_t) {0xb4eb310eUL, 0x08326307UL} },
-    { &fnv_test_str[18], (Fnv64_t) {0xb4eb2f5bUL, 0x08326207UL} },
-    { &fnv_test_str[19], (Fnv64_t) {0x6ba1355cUL, 0xd8cbc718UL} },
-    { &fnv_test_str[20], (Fnv64_t) {0xe2ed65a9UL, 0x0378817eUL} },
-    { &fnv_test_str[21], (Fnv64_t) {0x9963f7f1UL, 0xd329d59bUL} },
-    { &fnv_test_str[22], (Fnv64_t) {0xa4dda9b0UL, 0x340d8765UL} },
-    { &fnv_test_str[23], (Fnv64_t) {0x24a774a6UL, 0x50a6d3b7UL} },
-    { &fnv_test_str[24], (Fnv64_t) {0xb4eb341cUL, 0x08326507UL} },
-    { &fnv_test_str[25], (Fnv64_t) {0x6ba98bfbUL, 0xd8d5c818UL} },
-    { &fnv_test_str[26], (Fnv64_t) {0xf118dbefUL, 0x1ccefc7eUL} },
-    { &fnv_test_str[27], (Fnv64_t) {0xad3db77aUL, 0x0c92fab3UL} },
-    { &fnv_test_str[28], (Fnv64_t) {0x5fdec421UL, 0x9b77794fUL} },
-    { &fnv_test_str[29], (Fnv64_t) {0xe7874433UL, 0x0ac742dfUL} },
-    { &fnv_test_str[30], (Fnv64_t) {0x6ad8e2deUL, 0xd7dad576UL} },
-    { &fnv_test_str[31], (Fnv64_t) {0x8e897f5bUL, 0xa1bb9637UL} },
-    { &fnv_test_str[32], (Fnv64_t) {0x33a367d2UL, 0x5b3f9b67UL} },
-    { &fnv_test_str[33], (Fnv64_t) {0xbea969f6UL, 0xb07ce25cUL} },
-    { &fnv_test_str[34], (Fnv64_t) {0xf9df0d6aUL, 0x8d9e9997UL} },
-    { &fnv_test_str[35], (Fnv64_t) {0x9603cb7bUL, 0x838c673dUL} },
-    { &fnv_test_str[36], (Fnv64_t) {0xe872c273UL, 0x8b5ee8a5UL} },
-    { &fnv_test_str[37], (Fnv64_t) {0xfb00690cUL, 0x4507c4e9UL} },
-    { &fnv_test_str[38], (Fnv64_t) {0x81b27f45UL, 0x4c9ca595UL} },
-    { &fnv_test_str[39], (Fnv64_t) {0x624e4235UL, 0xe0aca20bUL} },
-    { &fnv_test_str[40], (Fnv64_t) {0x6ba98b94UL, 0xd8d5c818UL} },
-    { &fnv_test_str[41], (Fnv64_t) {0xf118db81UL, 0x1ccefc7eUL} },
-    { &fnv_test_str[42], (Fnv64_t) {0xad3db71dUL, 0x0c92fab3UL} },
-    { &fnv_test_str[43], (Fnv64_t) {0x5fdec44eUL, 0x9b77794fUL} },
-    { &fnv_test_str[44], (Fnv64_t) {0xe7874413UL, 0x0ac742dfUL} },
-    { &fnv_test_str[45], (Fnv64_t) {0x6ad8e2a9UL, 0xd7dad576UL} },
-    { &fnv_test_str[46], (Fnv64_t) {0x8e897f3aUL, 0xa1bb9637UL} },
-    { &fnv_test_str[47], (Fnv64_t) {0x33a367a1UL, 0x5b3f9b67UL} },
-    { &fnv_test_str[48], (Fnv64_t) {0xbea969d6UL, 0xb07ce25cUL} },
-    { &fnv_test_str[49], (Fnv64_t) {0xf9df0d02UL, 0x8d9e9997UL} },
-    { &fnv_test_str[50], (Fnv64_t) {0x9603cb1eUL, 0x838c673dUL} },
-    { &fnv_test_str[51], (Fnv64_t) {0xe872c201UL, 0x8b5ee8a5UL} },
-    { &fnv_test_str[52], (Fnv64_t) {0xfb006969UL, 0x4507c4e9UL} },
-    { &fnv_test_str[53], (Fnv64_t) {0x81b27f64UL, 0x4c9ca595UL} },
-    { &fnv_test_str[54], (Fnv64_t) {0x624e423fUL, 0xe0aca20bUL} },
-    { &fnv_test_str[55], (Fnv64_t) {0x0afa800fUL, 0x13998e58UL} },
-    { &fnv_test_str[56], (Fnv64_t) {0xb4eb3401UL, 0x08326507UL} },
-    { &fnv_test_str[57], (Fnv64_t) {0x6ba95dc1UL, 0xd8d5ad18UL} },
-    { &fnv_test_str[58], (Fnv64_t) {0xf0ca4e97UL, 0x1c72e17eUL} },
-    { &fnv_test_str[59], (Fnv64_t) {0x27c38ae6UL, 0x2183c1b3UL} },
-    { &fnv_test_str[60], (Fnv64_t) {0x914504f2UL, 0xb66d096cUL} },
-    { &fnv_test_str[61], (Fnv64_t) {0xd8476757UL, 0x404bf57aUL} },
-    { &fnv_test_str[62], (Fnv64_t) {0x815498bbUL, 0x887976bdUL} },
-    { &fnv_test_str[63], (Fnv64_t) {0xc2bf85a5UL, 0x3afd7f02UL} },
-    { &fnv_test_str[64], (Fnv64_t) {0xeb70177fUL, 0xfc4476b0UL} },
-    { &fnv_test_str[65], (Fnv64_t) {0x0f77ecbaUL, 0x186d2da0UL} },
-    { &fnv_test_str[66], (Fnv64_t) {0x48c74066UL, 0xf97140faUL} },
-    { &fnv_test_str[67], (Fnv64_t) {0xaa926d37UL, 0xa2b1cf49UL} },
-    { &fnv_test_str[68], (Fnv64_t) {0xd6cf940cUL, 0x0690712cUL} },
-    { &fnv_test_str[69], (Fnv64_t) {0x02b8906eUL, 0xf7045b31UL} },
-    { &fnv_test_str[70], (Fnv64_t) {0x6ba95db3UL, 0xd8d5ad18UL} },
-    { &fnv_test_str[71], (Fnv64_t) {0xf0ca4ef3UL, 0x1c72e17eUL} },
-    { &fnv_test_str[72], (Fnv64_t) {0x27c38a95UL, 0x2183c1b3UL} },
-    { &fnv_test_str[73], (Fnv64_t) {0x914504d2UL, 0xb66d096cUL} },
-    { &fnv_test_str[74], (Fnv64_t) {0xd8476736UL, 0x404bf57aUL} },
-    { &fnv_test_str[75], (Fnv64_t) {0x815498d5UL, 0x887976bdUL} },
-    { &fnv_test_str[76], (Fnv64_t) {0xc2bf85c1UL, 0x3afd7f02UL} },
-    { &fnv_test_str[77], (Fnv64_t) {0xeb70175fUL, 0xfc4476b0UL} },
-    { &fnv_test_str[78], (Fnv64_t) {0x0f77eccdUL, 0x186d2da0UL} },
-    { &fnv_test_str[79], (Fnv64_t) {0x48c7400eUL, 0xf97140faUL} },
-    { &fnv_test_str[80], (Fnv64_t) {0xaa926d52UL, 0xa2b1cf49UL} },
-    { &fnv_test_str[81], (Fnv64_t) {0xd6cf9475UL, 0x0690712cUL} },
-    { &fnv_test_str[82], (Fnv64_t) {0x02b89064UL, 0xf7045b31UL} },
-    { &fnv_test_str[83], (Fnv64_t) {0x9f9d6aeaUL, 0x74f76247UL} },
-    { &fnv_test_str[84], (Fnv64_t) {0xb4eb2b9cUL, 0x08326007UL} },
-    { &fnv_test_str[85], (Fnv64_t) {0x6b9b1a14UL, 0xd8c4c918UL} },
-    { &fnv_test_str[86], (Fnv64_t) {0xbdbdd4c7UL, 0x7b495389UL} },
-    { &fnv_test_str[87], (Fnv64_t) {0x69908e25UL, 0x3b6dba0dUL} },
-    { &fnv_test_str[88], (Fnv64_t) {0xf4b71261UL, 0xd6b2b17bUL} },
-    { &fnv_test_str[89], (Fnv64_t) {0x98e615b5UL, 0x447bfb7fUL} },
-    { &fnv_test_str[90], (Fnv64_t) {0xf4b71262UL, 0xd6b2b17bUL} },
-    { &fnv_test_str[91], (Fnv64_t) {0x93fe1660UL, 0x3bd2807fUL} },
-    { &fnv_test_str[92], (Fnv64_t) {0xf4b71263UL, 0xd6b2b17bUL} },
-    { &fnv_test_str[93], (Fnv64_t) {0x8f16170bUL, 0x3329057fUL} },
-    { &fnv_test_str[94], (Fnv64_t) {0xf4b71264UL, 0xd6b2b17bUL} },
-    { &fnv_test_str[95], (Fnv64_t) {0x8a2e19b6UL, 0x2a7f8a7fUL} },
-    { &fnv_test_str[96], (Fnv64_t) {0x64b2f98aUL, 0x23d3767eUL} },
-    { &fnv_test_str[97], (Fnv64_t) {0x4f9d86a4UL, 0xff768d7eUL} },
-    { &fnv_test_str[98], (Fnv64_t) {0x64b2f984UL, 0x23d3767eUL} },
-    { &fnv_test_str[99], (Fnv64_t) {0x334e4aa6UL, 0xccd1837eUL} },
-    { &fnv_test_str[100], (Fnv64_t) {0x64b2f99aUL, 0x23d3767eUL} },
-    { &fnv_test_str[101], (Fnv64_t) {0x028f6754UL, 0x7691fd7eUL} },
-    { &fnv_test_str[102], (Fnv64_t) {0x41204318UL, 0x34ad3b10UL} },
-    { &fnv_test_str[103], (Fnv64_t) {0xa9d201c8UL, 0xa29e749eUL} },
-    { &fnv_test_str[104], (Fnv64_t) {0x4120431bUL, 0x34ad3b10UL} },
-    { &fnv_test_str[105], (Fnv64_t) {0xa9d206e1UL, 0xa29e779eUL} },
-    { &fnv_test_str[106], (Fnv64_t) {0x4120431aUL, 0x34ad3b10UL} },
-    { &fnv_test_str[107], (Fnv64_t) {0xa9d2052eUL, 0xa29e769eUL} },
-    { &fnv_test_str[108], (Fnv64_t) {0xa4aa3497UL, 0x02a17ebcUL} },
-    { &fnv_test_str[109], (Fnv64_t) {0xcd375c95UL, 0x229ef18bUL} },
-    { &fnv_test_str[110], (Fnv64_t) {0xa4aa32c8UL, 0x02a17dbcUL} },
-    { &fnv_test_str[111], (Fnv64_t) {0xcd3449d8UL, 0x229b6f8bUL} },
-    { &fnv_test_str[112], (Fnv64_t) {0xa4aa3ed5UL, 0x02a184bcUL} },
-    { &fnv_test_str[113], (Fnv64_t) {0xcd48c3efUL, 0x22b3618bUL} },
-    { &fnv_test_str[114], (Fnv64_t) {0x06186f36UL, 0x5c2c3467UL} },
-    { &fnv_test_str[115], (Fnv64_t) {0x5b84f8c2UL, 0xb78c410fUL} },
-    { &fnv_test_str[116], (Fnv64_t) {0x2b267395UL, 0xed947821UL} },
-    { &fnv_test_str[117], (Fnv64_t) {0x5256662fUL, 0xd9bbb55cUL} },
-    { &fnv_test_str[118], (Fnv64_t) {0x3249438aUL, 0x8c54f020UL} },
-    { &fnv_test_str[119], (Fnv64_t) {0x727dc37eUL, 0xbd9790b5UL} },
-    { &fnv_test_str[120], (Fnv64_t) {0xc9e2b0e3UL, 0xa64e5f36UL} },
-    { &fnv_test_str[121], (Fnv64_t) {0xa3088a04UL, 0x8fd0680dUL} },
-    { &fnv_test_str[122], (Fnv64_t) {0x078284ccUL, 0x67aad32cUL} },
-    { &fnv_test_str[123], (Fnv64_t) {0x1c57b331UL, 0xb37d55d8UL} },
-    { &fnv_test_str[124], (Fnv64_t) {0x29057c43UL, 0x55ac0f38UL} },
-    { &fnv_test_str[125], (Fnv64_t) {0xe1b6cc20UL, 0xcb27f4b8UL} },
-    { &fnv_test_str[126], (Fnv64_t) {0xcbef2d19UL, 0x26caf88bUL} },
-    { &fnv_test_str[127], (Fnv64_t) {0x97e61b8fUL, 0x8e6e063bUL} },
-    { &fnv_test_str[128], (Fnv64_t) {0xf3b7c37eUL, 0xb42750f7UL} },
-    { &fnv_test_str[129], (Fnv64_t) {0xcf7ca99bUL, 0xf3c6ba64UL} },
-    { &fnv_test_str[130], (Fnv64_t) {0x27ea80feUL, 0xebfb69b4UL} },
-    { &fnv_test_str[131], (Fnv64_t) {0xd970f46cUL, 0x39b50c3eUL} },
-    { &fnv_test_str[132], (Fnv64_t) {0xa3eb3e8aUL, 0x5b9b177aUL} },
-    { &fnv_test_str[133], (Fnv64_t) {0xcf4ec903UL, 0x6510063eUL} },
-    { &fnv_test_str[134], (Fnv64_t) {0x00797c7aUL, 0x2b3bbd2cUL} },
-    { &fnv_test_str[135], (Fnv64_t) {0xf5cb4aa7UL, 0xf1d6204fUL} },
-    { &fnv_test_str[136], (Fnv64_t) {0xcf099f38UL, 0x4836e27cUL} },
-    { &fnv_test_str[137], (Fnv64_t) {0xd073b44dUL, 0x82efbb0dUL} },
-    { &fnv_test_str[138], (Fnv64_t) {0xffd7d4c6UL, 0x4a80c282UL} },
-    { &fnv_test_str[139], (Fnv64_t) {0x9ee43bdfUL, 0x305d1a9cUL} },
-    { &fnv_test_str[140], (Fnv64_t) {0x8ffc6997UL, 0x15c36694UL} },
-    { &fnv_test_str[141], (Fnv64_t) {0x18916e7bUL, 0x80153ae2UL} },
-    { &fnv_test_str[142], (Fnv64_t) {0xf9e2a9e1UL, 0xfa23e2bdUL} },
-    { &fnv_test_str[143], (Fnv64_t) {0x2333c6deUL, 0xd47e8d8aUL} },
-    { &fnv_test_str[144], (Fnv64_t) {0xf688b056UL, 0x7e128095UL} },
-    { &fnv_test_str[145], (Fnv64_t) {0x0efcedabUL, 0x2f535689UL} },
-    { &fnv_test_str[146], (Fnv64_t) {0x014f55c5UL, 0x95c2b383UL} },
-    { &fnv_test_str[147], (Fnv64_t) {0x9ce6070fUL, 0x4727a533UL} },
-    { &fnv_test_str[148], (Fnv64_t) {0x575108e9UL, 0xb0555ecdUL} },
-    { &fnv_test_str[149], (Fnv64_t) {0x0bb4af37UL, 0x48d78577UL} },
-    { &fnv_test_str[150], (Fnv64_t) {0x12af02b1UL, 0x09d4701cUL} },
-    { &fnv_test_str[151], (Fnv64_t) {0x8f3cf62eUL, 0x79f031e7UL} },
-    { &fnv_test_str[152], (Fnv64_t) {0xdb1b5a94UL, 0x52a1ee85UL} },
-    { &fnv_test_str[153], (Fnv64_t) {0xb37fa6b8UL, 0x6bd95b2eUL} },
-    { &fnv_test_str[154], (Fnv64_t) {0x77aef85dUL, 0x74971b70UL} },
-    { &fnv_test_str[155], (Fnv64_t) {0xffcc1aadUL, 0xb4e4fae2UL} },
-    { &fnv_test_str[156], (Fnv64_t) {0x98b8f63aUL, 0x2bd48bd8UL} },
-    { &fnv_test_str[157], (Fnv64_t) {0x556257f6UL, 0xe9966ac1UL} },
-    { &fnv_test_str[158], (Fnv64_t) {0x078ba293UL, 0x92a3d1cdUL} },
-    { &fnv_test_str[159], (Fnv64_t) {0x82e20ab8UL, 0xf81175a4UL} },
-    { &fnv_test_str[160], (Fnv64_t) {0x22e73048UL, 0x5bbb3de7UL} },
-    { &fnv_test_str[161], (Fnv64_t) {0x92b9f2beUL, 0x6b4f3634UL} },
-    { &fnv_test_str[162], (Fnv64_t) {0x73d59875UL, 0xc2d559dfUL} },
-    { &fnv_test_str[163], (Fnv64_t) {0x4bc7a8c2UL, 0xf75f6228UL} },
-    { &fnv_test_str[164], (Fnv64_t) {0x16a9f1ccUL, 0xda8dd8e1UL} },
-    { &fnv_test_str[165], (Fnv64_t) {0x76057885UL, 0xbdc1e6abUL} },
-    { &fnv_test_str[166], (Fnv64_t) {0x8a1224a0UL, 0xfec6a423UL} },
-    { &fnv_test_str[167], (Fnv64_t) {0x223e290eUL, 0xc03f40f3UL} },
-    { &fnv_test_str[168], (Fnv64_t) {0x466ffda9UL, 0x1ed21673UL} },
-    { &fnv_test_str[169], (Fnv64_t) {0xbb0dd2afUL, 0xdf70f906UL} },
-    { &fnv_test_str[170], (Fnv64_t) {0x9f2af666UL, 0xf3dcda36UL} },
-    { &fnv_test_str[171], (Fnv64_t) {0x3cdcebdeUL, 0x9ebb1157UL} },
-    { &fnv_test_str[172], (Fnv64_t) {0x77fedca0UL, 0x81c72d90UL} },
-    { &fnv_test_str[173], (Fnv64_t) {0x1be5fb15UL, 0x0ec074a3UL} },
-    { &fnv_test_str[174], (Fnv64_t) {0xb6c48f20UL, 0x2a8b3280UL} },
-    { &fnv_test_str[175], (Fnv64_t) {0x13309344UL, 0xfd317775UL} },
-    { &fnv_test_str[176], (Fnv64_t) {0x6ad006b6UL, 0x194534a8UL} },
-    { &fnv_test_str[177], (Fnv64_t) {0x6e0cfe12UL, 0x3be6fdf4UL} },
-    { &fnv_test_str[178], (Fnv64_t) {0xa07eb057UL, 0x017cc137UL} },
-    { &fnv_test_str[179], (Fnv64_t) {0x7d26b54dUL, 0x9428fc6eUL} },
-    { &fnv_test_str[180], (Fnv64_t) {0x03ef8ad7UL, 0x9aaa2e36UL} },
-    { &fnv_test_str[181], (Fnv64_t) {0xa0ccdf7dUL, 0x82c6d3f3UL} },
-    { &fnv_test_str[182], (Fnv64_t) {0x0cf09b65UL, 0xc86eeea0UL} },
-    { &fnv_test_str[183], (Fnv64_t) {0xdbb58299UL, 0x705f8189UL} },
-    { &fnv_test_str[184], (Fnv64_t) {0x4391ca69UL, 0x415a7f55UL} },
-    { &fnv_test_str[185], (Fnv64_t) {0xa2bdc555UL, 0xcfe3d49fUL} },
-    { &fnv_test_str[186], (Fnv64_t) {0x39b25191UL, 0xf0f9c560UL} },
-    { &fnv_test_str[187], (Fnv64_t) {0xbd1d32d9UL, 0x7075cb6aUL} },
-    { &fnv_test_str[188], (Fnv64_t) {0x8b277509UL, 0x43c94e2cUL} },
-    { &fnv_test_str[189], (Fnv64_t) {0xea670359UL, 0x3cbfd4e4UL} },
-    { &fnv_test_str[190], (Fnv64_t) {0x0f4d019dUL, 0xc0588781UL} },
-    { &fnv_test_str[191], (Fnv64_t) {0x3ac22dc5UL, 0x14468ff9UL} },
-    { &fnv_test_str[192], (Fnv64_t) {0x89d99c05UL, 0xebed6995UL} },
-    { &fnv_test_str[193], (Fnv64_t) {0x321ca5d5UL, 0x6d99f6dfUL} },
-    { &fnv_test_str[194], (Fnv64_t) {0x8c36d625UL, 0x0cd410d0UL} },
-    { &fnv_test_str[195], (Fnv64_t) {0x86831d35UL, 0xef1b2a2cUL} },
-    { &fnv_test_str[196], (Fnv64_t) {0x69ee5f05UL, 0x3b349c4dUL} },
-    { &fnv_test_str[197], (Fnv64_t) {0x8f45f035UL, 0x55248ce8UL} },
-    { &fnv_test_str[198], (Fnv64_t) {0x18a4c885UL, 0xaa69ca6aUL} },
-    { &fnv_test_str[199], (Fnv64_t) {0x2bd816b5UL, 0x1fe3fce6UL} },
-    { &fnv_test_str[200], (Fnv64_t) {0xa8df69d9UL, 0x0289a488UL} },
-    { &fnv_test_str[201], (Fnv64_t) {0x13df98b5UL, 0x15e96e16UL} },
-    { &fnv_test_str[202], (Fnv64_t) {0x5ad89b99UL, 0xe6be5737UL} },
-    { NULL, (Fnv64_t) {0,0} }
-};
-#endif /* HAVE_64BIT_LONG_LONG */
-
-/* FNV-1a 64 bit test vectors */
-#if defined(HAVE_64BIT_LONG_LONG)
-struct fnv1a_64_test_vector fnv1a_64_vector[] = {
-    { &fnv_test_str[0], (Fnv64_t) 0xcbf29ce484222325ULL },
-    { &fnv_test_str[1], (Fnv64_t) 0xaf63dc4c8601ec8cULL },
-    { &fnv_test_str[2], (Fnv64_t) 0xaf63df4c8601f1a5ULL },
-    { &fnv_test_str[3], (Fnv64_t) 0xaf63de4c8601eff2ULL },
-    { &fnv_test_str[4], (Fnv64_t) 0xaf63d94c8601e773ULL },
-    { &fnv_test_str[5], (Fnv64_t) 0xaf63d84c8601e5c0ULL },
-    { &fnv_test_str[6], (Fnv64_t) 0xaf63db4c8601ead9ULL },
-    { &fnv_test_str[7], (Fnv64_t) 0x08985907b541d342ULL },
-    { &fnv_test_str[8], (Fnv64_t) 0xdcb27518fed9d577ULL },
-    { &fnv_test_str[9], (Fnv64_t) 0xdd120e790c2512afULL },
-    { &fnv_test_str[10], (Fnv64_t) 0xcac165afa2fef40aULL },
-    { &fnv_test_str[11], (Fnv64_t) 0x85944171f73967e8ULL },
-    { &fnv_test_str[12], (Fnv64_t) 0xaf63bd4c8601b7dfULL },
-    { &fnv_test_str[13], (Fnv64_t) 0x089be207b544f1e4ULL },
-    { &fnv_test_str[14], (Fnv64_t) 0x08a61407b54d9b5fULL },
-    { &fnv_test_str[15], (Fnv64_t) 0x08a2ae07b54ab836ULL },
-    { &fnv_test_str[16], (Fnv64_t) 0x0891b007b53c4869ULL },
-    { &fnv_test_str[17], (Fnv64_t) 0x088e4a07b5396540ULL },
-    { &fnv_test_str[18], (Fnv64_t) 0x08987c07b5420ebbULL },
-    { &fnv_test_str[19], (Fnv64_t) 0xdcb28a18fed9f926ULL },
-    { &fnv_test_str[20], (Fnv64_t) 0xdd1270790c25b935ULL },
-    { &fnv_test_str[21], (Fnv64_t) 0xcac146afa2febf5dULL },
-    { &fnv_test_str[22], (Fnv64_t) 0x8593d371f738acfeULL },
-    { &fnv_test_str[23], (Fnv64_t) 0x34531ca7168b8f38ULL },
-    { &fnv_test_str[24], (Fnv64_t) 0x08a25607b54a22aeULL },
-    { &fnv_test_str[25], (Fnv64_t) 0xf5faf0190cf90df3ULL },
-    { &fnv_test_str[26], (Fnv64_t) 0xf27397910b3221c7ULL },
-    { &fnv_test_str[27], (Fnv64_t) 0x2c8c2b76062f22e0ULL },
-    { &fnv_test_str[28], (Fnv64_t) 0xe150688c8217b8fdULL },
-    { &fnv_test_str[29], (Fnv64_t) 0xf35a83c10e4f1f87ULL },
-    { &fnv_test_str[30], (Fnv64_t) 0xd1edd10b507344d0ULL },
-    { &fnv_test_str[31], (Fnv64_t) 0x2a5ee739b3ddb8c3ULL },
-    { &fnv_test_str[32], (Fnv64_t) 0xdcfb970ca1c0d310ULL },
-    { &fnv_test_str[33], (Fnv64_t) 0x4054da76daa6da90ULL },
-    { &fnv_test_str[34], (Fnv64_t) 0xf70a2ff589861368ULL },
-    { &fnv_test_str[35], (Fnv64_t) 0x4c628b38aed25f17ULL },
-    { &fnv_test_str[36], (Fnv64_t) 0x9dd1f6510f78189fULL },
-    { &fnv_test_str[37], (Fnv64_t) 0xa3de85bd491270ceULL },
-    { &fnv_test_str[38], (Fnv64_t) 0x858e2fa32a55e61dULL },
-    { &fnv_test_str[39], (Fnv64_t) 0x46810940eff5f915ULL },
-    { &fnv_test_str[40], (Fnv64_t) 0xf5fadd190cf8edaaULL },
-    { &fnv_test_str[41], (Fnv64_t) 0xf273ed910b32b3e9ULL },
-    { &fnv_test_str[42], (Fnv64_t) 0x2c8c5276062f6525ULL },
-    { &fnv_test_str[43], (Fnv64_t) 0xe150b98c821842a0ULL },
-    { &fnv_test_str[44], (Fnv64_t) 0xf35aa3c10e4f55e7ULL },
-    { &fnv_test_str[45], (Fnv64_t) 0xd1ed680b50729265ULL },
-    { &fnv_test_str[46], (Fnv64_t) 0x2a5f0639b3dded70ULL },
-    { &fnv_test_str[47], (Fnv64_t) 0xdcfbaa0ca1c0f359ULL },
-    { &fnv_test_str[48], (Fnv64_t) 0x4054ba76daa6a430ULL },
-    { &fnv_test_str[49], (Fnv64_t) 0xf709c7f5898562b0ULL },
-    { &fnv_test_str[50], (Fnv64_t) 0x4c62e638aed2f9b8ULL },
-    { &fnv_test_str[51], (Fnv64_t) 0x9dd1a8510f779415ULL },
-    { &fnv_test_str[52], (Fnv64_t) 0xa3de2abd4911d62dULL },
-    { &fnv_test_str[53], (Fnv64_t) 0x858e0ea32a55ae0aULL },
-    { &fnv_test_str[54], (Fnv64_t) 0x46810f40eff60347ULL },
-    { &fnv_test_str[55], (Fnv64_t) 0xc33bce57bef63eafULL },
-    { &fnv_test_str[56], (Fnv64_t) 0x08a24307b54a0265ULL },
-    { &fnv_test_str[57], (Fnv64_t) 0xf5b9fd190cc18d15ULL },
-    { &fnv_test_str[58], (Fnv64_t) 0x4c968290ace35703ULL },
-    { &fnv_test_str[59], (Fnv64_t) 0x07174bd5c64d9350ULL },
-    { &fnv_test_str[60], (Fnv64_t) 0x5a294c3ff5d18750ULL },
-    { &fnv_test_str[61], (Fnv64_t) 0x05b3c1aeb308b843ULL },
-    { &fnv_test_str[62], (Fnv64_t) 0xb92a48da37d0f477ULL },
-    { &fnv_test_str[63], (Fnv64_t) 0x73cdddccd80ebc49ULL },
-    { &fnv_test_str[64], (Fnv64_t) 0xd58c4c13210a266bULL },
-    { &fnv_test_str[65], (Fnv64_t) 0xe78b6081243ec194ULL },
-    { &fnv_test_str[66], (Fnv64_t) 0xb096f77096a39f34ULL },
-    { &fnv_test_str[67], (Fnv64_t) 0xb425c54ff807b6a3ULL },
-    { &fnv_test_str[68], (Fnv64_t) 0x23e520e2751bb46eULL },
-    { &fnv_test_str[69], (Fnv64_t) 0x1a0b44ccfe1385ecULL },
-    { &fnv_test_str[70], (Fnv64_t) 0xf5ba4b190cc2119fULL },
-    { &fnv_test_str[71], (Fnv64_t) 0x4c962690ace2baafULL },
-    { &fnv_test_str[72], (Fnv64_t) 0x0716ded5c64cda19ULL },
-    { &fnv_test_str[73], (Fnv64_t) 0x5a292c3ff5d150f0ULL },
-    { &fnv_test_str[74], (Fnv64_t) 0x05b3e0aeb308ecf0ULL },
-    { &fnv_test_str[75], (Fnv64_t) 0xb92a5eda37d119d9ULL },
-    { &fnv_test_str[76], (Fnv64_t) 0x73ce41ccd80f6635ULL },
-    { &fnv_test_str[77], (Fnv64_t) 0xd58c2c132109f00bULL },
-    { &fnv_test_str[78], (Fnv64_t) 0xe78baf81243f47d1ULL },
-    { &fnv_test_str[79], (Fnv64_t) 0xb0968f7096a2ee7cULL },
-    { &fnv_test_str[80], (Fnv64_t) 0xb425a84ff807855cULL },
-    { &fnv_test_str[81], (Fnv64_t) 0x23e4e9e2751b56f9ULL },
-    { &fnv_test_str[82], (Fnv64_t) 0x1a0b4eccfe1396eaULL },
-    { &fnv_test_str[83], (Fnv64_t) 0x54abd453bb2c9004ULL },
-    { &fnv_test_str[84], (Fnv64_t) 0x08ba5f07b55ec3daULL },
-    { &fnv_test_str[85], (Fnv64_t) 0x337354193006cb6eULL },
-    { &fnv_test_str[86], (Fnv64_t) 0xa430d84680aabd0bULL },
-    { &fnv_test_str[87], (Fnv64_t) 0xa9bc8acca21f39b1ULL },
-    { &fnv_test_str[88], (Fnv64_t) 0x6961196491cc682dULL },
-    { &fnv_test_str[89], (Fnv64_t) 0xad2bb1774799dfe9ULL },
-    { &fnv_test_str[90], (Fnv64_t) 0x6961166491cc6314ULL },
-    { &fnv_test_str[91], (Fnv64_t) 0x8d1bb3904a3b1236ULL },
-    { &fnv_test_str[92], (Fnv64_t) 0x6961176491cc64c7ULL },
-    { &fnv_test_str[93], (Fnv64_t) 0xed205d87f40434c7ULL },
-    { &fnv_test_str[94], (Fnv64_t) 0x6961146491cc5faeULL },
-    { &fnv_test_str[95], (Fnv64_t) 0xcd3baf5e44f8ad9cULL },
-    { &fnv_test_str[96], (Fnv64_t) 0xe3b36596127cd6d8ULL },
-    { &fnv_test_str[97], (Fnv64_t) 0xf77f1072c8e8a646ULL },
-    { &fnv_test_str[98], (Fnv64_t) 0xe3b36396127cd372ULL },
-    { &fnv_test_str[99], (Fnv64_t) 0x6067dce9932ad458ULL },
-    { &fnv_test_str[100], (Fnv64_t) 0xe3b37596127cf208ULL },
-    { &fnv_test_str[101], (Fnv64_t) 0x4b7b10fa9fe83936ULL },
-    { &fnv_test_str[102], (Fnv64_t) 0xaabafe7104d914beULL },
-    { &fnv_test_str[103], (Fnv64_t) 0xf4d3180b3cde3edaULL },
-    { &fnv_test_str[104], (Fnv64_t) 0xaabafd7104d9130bULL },
-    { &fnv_test_str[105], (Fnv64_t) 0xf4cfb20b3cdb5bb1ULL },
-    { &fnv_test_str[106], (Fnv64_t) 0xaabafc7104d91158ULL },
-    { &fnv_test_str[107], (Fnv64_t) 0xf4cc4c0b3cd87888ULL },
-    { &fnv_test_str[108], (Fnv64_t) 0xe729bac5d2a8d3a7ULL },
-    { &fnv_test_str[109], (Fnv64_t) 0x74bc0524f4dfa4c5ULL },
-    { &fnv_test_str[110], (Fnv64_t) 0xe72630c5d2a5b352ULL },
-    { &fnv_test_str[111], (Fnv64_t) 0x6b983224ef8fb456ULL },
-    { &fnv_test_str[112], (Fnv64_t) 0xe73042c5d2ae266dULL },
-    { &fnv_test_str[113], (Fnv64_t) 0x8527e324fdeb4b37ULL },
-    { &fnv_test_str[114], (Fnv64_t) 0x0a83c86fee952abcULL },
-    { &fnv_test_str[115], (Fnv64_t) 0x7318523267779d74ULL },
-    { &fnv_test_str[116], (Fnv64_t) 0x3e66d3d56b8caca1ULL },
-    { &fnv_test_str[117], (Fnv64_t) 0x956694a5c0095593ULL },
-    { &fnv_test_str[118], (Fnv64_t) 0xcac54572bb1a6fc8ULL },
-    { &fnv_test_str[119], (Fnv64_t) 0xa7a4c9f3edebf0d8ULL },
-    { &fnv_test_str[120], (Fnv64_t) 0x7829851fac17b143ULL },
-    { &fnv_test_str[121], (Fnv64_t) 0x2c8f4c9af81bcf06ULL },
-    { &fnv_test_str[122], (Fnv64_t) 0xd34e31539740c732ULL },
-    { &fnv_test_str[123], (Fnv64_t) 0x3605a2ac253d2db1ULL },
-    { &fnv_test_str[124], (Fnv64_t) 0x08c11b8346f4a3c3ULL },
-    { &fnv_test_str[125], (Fnv64_t) 0x6be396289ce8a6daULL },
-    { &fnv_test_str[126], (Fnv64_t) 0xd9b957fb7fe794c5ULL },
-    { &fnv_test_str[127], (Fnv64_t) 0x05be33da04560a93ULL },
-    { &fnv_test_str[128], (Fnv64_t) 0x0957f1577ba9747cULL },
-    { &fnv_test_str[129], (Fnv64_t) 0xda2cc3acc24fba57ULL },
-    { &fnv_test_str[130], (Fnv64_t) 0x74136f185b29e7f0ULL },
-    { &fnv_test_str[131], (Fnv64_t) 0xb2f2b4590edb93b2ULL },
-    { &fnv_test_str[132], (Fnv64_t) 0xb3608fce8b86ae04ULL },
-    { &fnv_test_str[133], (Fnv64_t) 0x4a3a865079359063ULL },
-    { &fnv_test_str[134], (Fnv64_t) 0x5b3a7ef496880a50ULL },
-    { &fnv_test_str[135], (Fnv64_t) 0x48fae3163854c23bULL },
-    { &fnv_test_str[136], (Fnv64_t) 0x07aaa640476e0b9aULL },
-    { &fnv_test_str[137], (Fnv64_t) 0x2f653656383a687dULL },
-    { &fnv_test_str[138], (Fnv64_t) 0xa1031f8e7599d79cULL },
-    { &fnv_test_str[139], (Fnv64_t) 0xa31908178ff92477ULL },
-    { &fnv_test_str[140], (Fnv64_t) 0x097edf3c14c3fb83ULL },
-    { &fnv_test_str[141], (Fnv64_t) 0xb51ca83feaa0971bULL },
-    { &fnv_test_str[142], (Fnv64_t) 0xdd3c0d96d784f2e9ULL },
-    { &fnv_test_str[143], (Fnv64_t) 0x86cd26a9ea767d78ULL },
-    { &fnv_test_str[144], (Fnv64_t) 0xe6b215ff54a30c18ULL },
-    { &fnv_test_str[145], (Fnv64_t) 0xec5b06a1c5531093ULL },
-    { &fnv_test_str[146], (Fnv64_t) 0x45665a929f9ec5e5ULL },
-    { &fnv_test_str[147], (Fnv64_t) 0x8c7609b4a9f10907ULL },
-    { &fnv_test_str[148], (Fnv64_t) 0x89aac3a491f0d729ULL },
-    { &fnv_test_str[149], (Fnv64_t) 0x32ce6b26e0f4a403ULL },
-    { &fnv_test_str[150], (Fnv64_t) 0x614ab44e02b53e01ULL },
-    { &fnv_test_str[151], (Fnv64_t) 0xfa6472eb6eef3290ULL },
-    { &fnv_test_str[152], (Fnv64_t) 0x9e5d75eb1948eb6aULL },
-    { &fnv_test_str[153], (Fnv64_t) 0xb6d12ad4a8671852ULL },
-    { &fnv_test_str[154], (Fnv64_t) 0x88826f56eba07af1ULL },
-    { &fnv_test_str[155], (Fnv64_t) 0x44535bf2645bc0fdULL },
-    { &fnv_test_str[156], (Fnv64_t) 0x169388ffc21e3728ULL },
-    { &fnv_test_str[157], (Fnv64_t) 0xf68aac9e396d8224ULL },
-    { &fnv_test_str[158], (Fnv64_t) 0x8e87d7e7472b3883ULL },
-    { &fnv_test_str[159], (Fnv64_t) 0x295c26caa8b423deULL },
-    { &fnv_test_str[160], (Fnv64_t) 0x322c814292e72176ULL },
-    { &fnv_test_str[161], (Fnv64_t) 0x8a06550eb8af7268ULL },
-    { &fnv_test_str[162], (Fnv64_t) 0xef86d60e661bcf71ULL },
-    { &fnv_test_str[163], (Fnv64_t) 0x9e5426c87f30ee54ULL },
-    { &fnv_test_str[164], (Fnv64_t) 0xf1ea8aa826fd047eULL },
-    { &fnv_test_str[165], (Fnv64_t) 0x0babaf9a642cb769ULL },
-    { &fnv_test_str[166], (Fnv64_t) 0x4b3341d4068d012eULL },
-    { &fnv_test_str[167], (Fnv64_t) 0xd15605cbc30a335cULL },
-    { &fnv_test_str[168], (Fnv64_t) 0x5b21060aed8412e5ULL },
-    { &fnv_test_str[169], (Fnv64_t) 0x45e2cda1ce6f4227ULL },
-    { &fnv_test_str[170], (Fnv64_t) 0x50ae3745033ad7d4ULL },
-    { &fnv_test_str[171], (Fnv64_t) 0xaa4588ced46bf414ULL },
-    { &fnv_test_str[172], (Fnv64_t) 0xc1b0056c4a95467eULL },
-    { &fnv_test_str[173], (Fnv64_t) 0x56576a71de8b4089ULL },
-    { &fnv_test_str[174], (Fnv64_t) 0xbf20965fa6dc927eULL },
-    { &fnv_test_str[175], (Fnv64_t) 0x569f8383c2040882ULL },
-    { &fnv_test_str[176], (Fnv64_t) 0xe1e772fba08feca0ULL },
-    { &fnv_test_str[177], (Fnv64_t) 0x4ced94af97138ac4ULL },
-    { &fnv_test_str[178], (Fnv64_t) 0xc4112ffb337a82fbULL },
-    { &fnv_test_str[179], (Fnv64_t) 0xd64a4fd41de38b7dULL },
-    { &fnv_test_str[180], (Fnv64_t) 0x4cfc32329edebcbbULL },
-    { &fnv_test_str[181], (Fnv64_t) 0x0803564445050395ULL },
-    { &fnv_test_str[182], (Fnv64_t) 0xaa1574ecf4642ffdULL },
-    { &fnv_test_str[183], (Fnv64_t) 0x694bc4e54cc315f9ULL },
-    { &fnv_test_str[184], (Fnv64_t) 0xa3d7cb273b011721ULL },
-    { &fnv_test_str[185], (Fnv64_t) 0x577c2f8b6115bfa5ULL },
-    { &fnv_test_str[186], (Fnv64_t) 0xb7ec8c1a769fb4c1ULL },
-    { &fnv_test_str[187], (Fnv64_t) 0x5d5cfce63359ab19ULL },
-    { &fnv_test_str[188], (Fnv64_t) 0x33b96c3cd65b5f71ULL },
-    { &fnv_test_str[189], (Fnv64_t) 0xd845097780602bb9ULL },
-    { &fnv_test_str[190], (Fnv64_t) 0x84d47645d02da3d5ULL },
-    { &fnv_test_str[191], (Fnv64_t) 0x83544f33b58773a5ULL },
-    { &fnv_test_str[192], (Fnv64_t) 0x9175cbb2160836c5ULL },
-    { &fnv_test_str[193], (Fnv64_t) 0xc71b3bc175e72bc5ULL },
-    { &fnv_test_str[194], (Fnv64_t) 0x636806ac222ec985ULL },
-    { &fnv_test_str[195], (Fnv64_t) 0xb6ef0e6950f52ed5ULL },
-    { &fnv_test_str[196], (Fnv64_t) 0xead3d8a0f3dfdaa5ULL },
-    { &fnv_test_str[197], (Fnv64_t) 0x922908fe9a861ba5ULL },
-    { &fnv_test_str[198], (Fnv64_t) 0x6d4821de275fd5c5ULL },
-    { &fnv_test_str[199], (Fnv64_t) 0x1fe3fce62bd816b5ULL },
-    { &fnv_test_str[200], (Fnv64_t) 0xc23e9fccd6f70591ULL },
-    { &fnv_test_str[201], (Fnv64_t) 0xc1af12bdfe16b5b5ULL },
-    { &fnv_test_str[202], (Fnv64_t) 0x39e9f18f2f85e221ULL },
-    { NULL, (Fnv64_t) 0 }
-};
-#else /* HAVE_64BIT_LONG_LONG */
-struct fnv1a_64_test_vector fnv1a_64_vector[] = {
-    { &fnv_test_str[0], (Fnv64_t) {0x84222325UL, 0xcbf29ce4UL} },
-    { &fnv_test_str[1], (Fnv64_t) {0x8601ec8cUL, 0xaf63dc4cUL} },
-    { &fnv_test_str[2], (Fnv64_t) {0x8601f1a5UL, 0xaf63df4cUL} },
-    { &fnv_test_str[3], (Fnv64_t) {0x8601eff2UL, 0xaf63de4cUL} },
-    { &fnv_test_str[4], (Fnv64_t) {0x8601e773UL, 0xaf63d94cUL} },
-    { &fnv_test_str[5], (Fnv64_t) {0x8601e5c0UL, 0xaf63d84cUL} },
-    { &fnv_test_str[6], (Fnv64_t) {0x8601ead9UL, 0xaf63db4cUL} },
-    { &fnv_test_str[7], (Fnv64_t) {0xb541d342UL, 0x08985907UL} },
-    { &fnv_test_str[8], (Fnv64_t) {0xfed9d577UL, 0xdcb27518UL} },
-    { &fnv_test_str[9], (Fnv64_t) {0x0c2512afUL, 0xdd120e79UL} },
-    { &fnv_test_str[10], (Fnv64_t) {0xa2fef40aUL, 0xcac165afUL} },
-    { &fnv_test_str[11], (Fnv64_t) {0xf73967e8UL, 0x85944171UL} },
-    { &fnv_test_str[12], (Fnv64_t) {0x8601b7dfUL, 0xaf63bd4cUL} },
-    { &fnv_test_str[13], (Fnv64_t) {0xb544f1e4UL, 0x089be207UL} },
-    { &fnv_test_str[14], (Fnv64_t) {0xb54d9b5fUL, 0x08a61407UL} },
-    { &fnv_test_str[15], (Fnv64_t) {0xb54ab836UL, 0x08a2ae07UL} },
-    { &fnv_test_str[16], (Fnv64_t) {0xb53c4869UL, 0x0891b007UL} },
-    { &fnv_test_str[17], (Fnv64_t) {0xb5396540UL, 0x088e4a07UL} },
-    { &fnv_test_str[18], (Fnv64_t) {0xb5420ebbUL, 0x08987c07UL} },
-    { &fnv_test_str[19], (Fnv64_t) {0xfed9f926UL, 0xdcb28a18UL} },
-    { &fnv_test_str[20], (Fnv64_t) {0x0c25b935UL, 0xdd127079UL} },
-    { &fnv_test_str[21], (Fnv64_t) {0xa2febf5dUL, 0xcac146afUL} },
-    { &fnv_test_str[22], (Fnv64_t) {0xf738acfeUL, 0x8593d371UL} },
-    { &fnv_test_str[23], (Fnv64_t) {0x168b8f38UL, 0x34531ca7UL} },
-    { &fnv_test_str[24], (Fnv64_t) {0xb54a22aeUL, 0x08a25607UL} },
-    { &fnv_test_str[25], (Fnv64_t) {0x0cf90df3UL, 0xf5faf019UL} },
-    { &fnv_test_str[26], (Fnv64_t) {0x0b3221c7UL, 0xf2739791UL} },
-    { &fnv_test_str[27], (Fnv64_t) {0x062f22e0UL, 0x2c8c2b76UL} },
-    { &fnv_test_str[28], (Fnv64_t) {0x8217b8fdUL, 0xe150688cUL} },
-    { &fnv_test_str[29], (Fnv64_t) {0x0e4f1f87UL, 0xf35a83c1UL} },
-    { &fnv_test_str[30], (Fnv64_t) {0x507344d0UL, 0xd1edd10bUL} },
-    { &fnv_test_str[31], (Fnv64_t) {0xb3ddb8c3UL, 0x2a5ee739UL} },
-    { &fnv_test_str[32], (Fnv64_t) {0xa1c0d310UL, 0xdcfb970cUL} },
-    { &fnv_test_str[33], (Fnv64_t) {0xdaa6da90UL, 0x4054da76UL} },
-    { &fnv_test_str[34], (Fnv64_t) {0x89861368UL, 0xf70a2ff5UL} },
-    { &fnv_test_str[35], (Fnv64_t) {0xaed25f17UL, 0x4c628b38UL} },
-    { &fnv_test_str[36], (Fnv64_t) {0x0f78189fUL, 0x9dd1f651UL} },
-    { &fnv_test_str[37], (Fnv64_t) {0x491270ceUL, 0xa3de85bdUL} },
-    { &fnv_test_str[38], (Fnv64_t) {0x2a55e61dUL, 0x858e2fa3UL} },
-    { &fnv_test_str[39], (Fnv64_t) {0xeff5f915UL, 0x46810940UL} },
-    { &fnv_test_str[40], (Fnv64_t) {0x0cf8edaaUL, 0xf5fadd19UL} },
-    { &fnv_test_str[41], (Fnv64_t) {0x0b32b3e9UL, 0xf273ed91UL} },
-    { &fnv_test_str[42], (Fnv64_t) {0x062f6525UL, 0x2c8c5276UL} },
-    { &fnv_test_str[43], (Fnv64_t) {0x821842a0UL, 0xe150b98cUL} },
-    { &fnv_test_str[44], (Fnv64_t) {0x0e4f55e7UL, 0xf35aa3c1UL} },
-    { &fnv_test_str[45], (Fnv64_t) {0x50729265UL, 0xd1ed680bUL} },
-    { &fnv_test_str[46], (Fnv64_t) {0xb3dded70UL, 0x2a5f0639UL} },
-    { &fnv_test_str[47], (Fnv64_t) {0xa1c0f359UL, 0xdcfbaa0cUL} },
-    { &fnv_test_str[48], (Fnv64_t) {0xdaa6a430UL, 0x4054ba76UL} },
-    { &fnv_test_str[49], (Fnv64_t) {0x898562b0UL, 0xf709c7f5UL} },
-    { &fnv_test_str[50], (Fnv64_t) {0xaed2f9b8UL, 0x4c62e638UL} },
-    { &fnv_test_str[51], (Fnv64_t) {0x0f779415UL, 0x9dd1a851UL} },
-    { &fnv_test_str[52], (Fnv64_t) {0x4911d62dUL, 0xa3de2abdUL} },
-    { &fnv_test_str[53], (Fnv64_t) {0x2a55ae0aUL, 0x858e0ea3UL} },
-    { &fnv_test_str[54], (Fnv64_t) {0xeff60347UL, 0x46810f40UL} },
-    { &fnv_test_str[55], (Fnv64_t) {0xbef63eafUL, 0xc33bce57UL} },
-    { &fnv_test_str[56], (Fnv64_t) {0xb54a0265UL, 0x08a24307UL} },
-    { &fnv_test_str[57], (Fnv64_t) {0x0cc18d15UL, 0xf5b9fd19UL} },
-    { &fnv_test_str[58], (Fnv64_t) {0xace35703UL, 0x4c968290UL} },
-    { &fnv_test_str[59], (Fnv64_t) {0xc64d9350UL, 0x07174bd5UL} },
-    { &fnv_test_str[60], (Fnv64_t) {0xf5d18750UL, 0x5a294c3fUL} },
-    { &fnv_test_str[61], (Fnv64_t) {0xb308b843UL, 0x05b3c1aeUL} },
-    { &fnv_test_str[62], (Fnv64_t) {0x37d0f477UL, 0xb92a48daUL} },
-    { &fnv_test_str[63], (Fnv64_t) {0xd80ebc49UL, 0x73cdddccUL} },
-    { &fnv_test_str[64], (Fnv64_t) {0x210a266bUL, 0xd58c4c13UL} },
-    { &fnv_test_str[65], (Fnv64_t) {0x243ec194UL, 0xe78b6081UL} },
-    { &fnv_test_str[66], (Fnv64_t) {0x96a39f34UL, 0xb096f770UL} },
-    { &fnv_test_str[67], (Fnv64_t) {0xf807b6a3UL, 0xb425c54fUL} },
-    { &fnv_test_str[68], (Fnv64_t) {0x751bb46eUL, 0x23e520e2UL} },
-    { &fnv_test_str[69], (Fnv64_t) {0xfe1385ecUL, 0x1a0b44ccUL} },
-    { &fnv_test_str[70], (Fnv64_t) {0x0cc2119fUL, 0xf5ba4b19UL} },
-    { &fnv_test_str[71], (Fnv64_t) {0xace2baafUL, 0x4c962690UL} },
-    { &fnv_test_str[72], (Fnv64_t) {0xc64cda19UL, 0x0716ded5UL} },
-    { &fnv_test_str[73], (Fnv64_t) {0xf5d150f0UL, 0x5a292c3fUL} },
-    { &fnv_test_str[74], (Fnv64_t) {0xb308ecf0UL, 0x05b3e0aeUL} },
-    { &fnv_test_str[75], (Fnv64_t) {0x37d119d9UL, 0xb92a5edaUL} },
-    { &fnv_test_str[76], (Fnv64_t) {0xd80f6635UL, 0x73ce41ccUL} },
-    { &fnv_test_str[77], (Fnv64_t) {0x2109f00bUL, 0xd58c2c13UL} },
-    { &fnv_test_str[78], (Fnv64_t) {0x243f47d1UL, 0xe78baf81UL} },
-    { &fnv_test_str[79], (Fnv64_t) {0x96a2ee7cUL, 0xb0968f70UL} },
-    { &fnv_test_str[80], (Fnv64_t) {0xf807855cUL, 0xb425a84fUL} },
-    { &fnv_test_str[81], (Fnv64_t) {0x751b56f9UL, 0x23e4e9e2UL} },
-    { &fnv_test_str[82], (Fnv64_t) {0xfe1396eaUL, 0x1a0b4eccUL} },
-    { &fnv_test_str[83], (Fnv64_t) {0xbb2c9004UL, 0x54abd453UL} },
-    { &fnv_test_str[84], (Fnv64_t) {0xb55ec3daUL, 0x08ba5f07UL} },
-    { &fnv_test_str[85], (Fnv64_t) {0x3006cb6eUL, 0x33735419UL} },
-    { &fnv_test_str[86], (Fnv64_t) {0x80aabd0bUL, 0xa430d846UL} },
-    { &fnv_test_str[87], (Fnv64_t) {0xa21f39b1UL, 0xa9bc8accUL} },
-    { &fnv_test_str[88], (Fnv64_t) {0x91cc682dUL, 0x69611964UL} },
-    { &fnv_test_str[89], (Fnv64_t) {0x4799dfe9UL, 0xad2bb177UL} },
-    { &fnv_test_str[90], (Fnv64_t) {0x91cc6314UL, 0x69611664UL} },
-    { &fnv_test_str[91], (Fnv64_t) {0x4a3b1236UL, 0x8d1bb390UL} },
-    { &fnv_test_str[92], (Fnv64_t) {0x91cc64c7UL, 0x69611764UL} },
-    { &fnv_test_str[93], (Fnv64_t) {0xf40434c7UL, 0xed205d87UL} },
-    { &fnv_test_str[94], (Fnv64_t) {0x91cc5faeUL, 0x69611464UL} },
-    { &fnv_test_str[95], (Fnv64_t) {0x44f8ad9cUL, 0xcd3baf5eUL} },
-    { &fnv_test_str[96], (Fnv64_t) {0x127cd6d8UL, 0xe3b36596UL} },
-    { &fnv_test_str[97], (Fnv64_t) {0xc8e8a646UL, 0xf77f1072UL} },
-    { &fnv_test_str[98], (Fnv64_t) {0x127cd372UL, 0xe3b36396UL} },
-    { &fnv_test_str[99], (Fnv64_t) {0x932ad458UL, 0x6067dce9UL} },
-    { &fnv_test_str[100], (Fnv64_t) {0x127cf208UL, 0xe3b37596UL} },
-    { &fnv_test_str[101], (Fnv64_t) {0x9fe83936UL, 0x4b7b10faUL} },
-    { &fnv_test_str[102], (Fnv64_t) {0x04d914beUL, 0xaabafe71UL} },
-    { &fnv_test_str[103], (Fnv64_t) {0x3cde3edaUL, 0xf4d3180bUL} },
-    { &fnv_test_str[104], (Fnv64_t) {0x04d9130bUL, 0xaabafd71UL} },
-    { &fnv_test_str[105], (Fnv64_t) {0x3cdb5bb1UL, 0xf4cfb20bUL} },
-    { &fnv_test_str[106], (Fnv64_t) {0x04d91158UL, 0xaabafc71UL} },
-    { &fnv_test_str[107], (Fnv64_t) {0x3cd87888UL, 0xf4cc4c0bUL} },
-    { &fnv_test_str[108], (Fnv64_t) {0xd2a8d3a7UL, 0xe729bac5UL} },
-    { &fnv_test_str[109], (Fnv64_t) {0xf4dfa4c5UL, 0x74bc0524UL} },
-    { &fnv_test_str[110], (Fnv64_t) {0xd2a5b352UL, 0xe72630c5UL} },
-    { &fnv_test_str[111], (Fnv64_t) {0xef8fb456UL, 0x6b983224UL} },
-    { &fnv_test_str[112], (Fnv64_t) {0xd2ae266dUL, 0xe73042c5UL} },
-    { &fnv_test_str[113], (Fnv64_t) {0xfdeb4b37UL, 0x8527e324UL} },
-    { &fnv_test_str[114], (Fnv64_t) {0xee952abcUL, 0x0a83c86fUL} },
-    { &fnv_test_str[115], (Fnv64_t) {0x67779d74UL, 0x73185232UL} },
-    { &fnv_test_str[116], (Fnv64_t) {0x6b8caca1UL, 0x3e66d3d5UL} },
-    { &fnv_test_str[117], (Fnv64_t) {0xc0095593UL, 0x956694a5UL} },
-    { &fnv_test_str[118], (Fnv64_t) {0xbb1a6fc8UL, 0xcac54572UL} },
-    { &fnv_test_str[119], (Fnv64_t) {0xedebf0d8UL, 0xa7a4c9f3UL} },
-    { &fnv_test_str[120], (Fnv64_t) {0xac17b143UL, 0x7829851fUL} },
-    { &fnv_test_str[121], (Fnv64_t) {0xf81bcf06UL, 0x2c8f4c9aUL} },
-    { &fnv_test_str[122], (Fnv64_t) {0x9740c732UL, 0xd34e3153UL} },
-    { &fnv_test_str[123], (Fnv64_t) {0x253d2db1UL, 0x3605a2acUL} },
-    { &fnv_test_str[124], (Fnv64_t) {0x46f4a3c3UL, 0x08c11b83UL} },
-    { &fnv_test_str[125], (Fnv64_t) {0x9ce8a6daUL, 0x6be39628UL} },
-    { &fnv_test_str[126], (Fnv64_t) {0x7fe794c5UL, 0xd9b957fbUL} },
-    { &fnv_test_str[127], (Fnv64_t) {0x04560a93UL, 0x05be33daUL} },
-    { &fnv_test_str[128], (Fnv64_t) {0x7ba9747cUL, 0x0957f157UL} },
-    { &fnv_test_str[129], (Fnv64_t) {0xc24fba57UL, 0xda2cc3acUL} },
-    { &fnv_test_str[130], (Fnv64_t) {0x5b29e7f0UL, 0x74136f18UL} },
-    { &fnv_test_str[131], (Fnv64_t) {0x0edb93b2UL, 0xb2f2b459UL} },
-    { &fnv_test_str[132], (Fnv64_t) {0x8b86ae04UL, 0xb3608fceUL} },
-    { &fnv_test_str[133], (Fnv64_t) {0x79359063UL, 0x4a3a8650UL} },
-    { &fnv_test_str[134], (Fnv64_t) {0x96880a50UL, 0x5b3a7ef4UL} },
-    { &fnv_test_str[135], (Fnv64_t) {0x3854c23bUL, 0x48fae316UL} },
-    { &fnv_test_str[136], (Fnv64_t) {0x476e0b9aUL, 0x07aaa640UL} },
-    { &fnv_test_str[137], (Fnv64_t) {0x383a687dUL, 0x2f653656UL} },
-    { &fnv_test_str[138], (Fnv64_t) {0x7599d79cUL, 0xa1031f8eUL} },
-    { &fnv_test_str[139], (Fnv64_t) {0x8ff92477UL, 0xa3190817UL} },
-    { &fnv_test_str[140], (Fnv64_t) {0x14c3fb83UL, 0x097edf3cUL} },
-    { &fnv_test_str[141], (Fnv64_t) {0xeaa0971bUL, 0xb51ca83fUL} },
-    { &fnv_test_str[142], (Fnv64_t) {0xd784f2e9UL, 0xdd3c0d96UL} },
-    { &fnv_test_str[143], (Fnv64_t) {0xea767d78UL, 0x86cd26a9UL} },
-    { &fnv_test_str[144], (Fnv64_t) {0x54a30c18UL, 0xe6b215ffUL} },
-    { &fnv_test_str[145], (Fnv64_t) {0xc5531093UL, 0xec5b06a1UL} },
-    { &fnv_test_str[146], (Fnv64_t) {0x9f9ec5e5UL, 0x45665a92UL} },
-    { &fnv_test_str[147], (Fnv64_t) {0xa9f10907UL, 0x8c7609b4UL} },
-    { &fnv_test_str[148], (Fnv64_t) {0x91f0d729UL, 0x89aac3a4UL} },
-    { &fnv_test_str[149], (Fnv64_t) {0xe0f4a403UL, 0x32ce6b26UL} },
-    { &fnv_test_str[150], (Fnv64_t) {0x02b53e01UL, 0x614ab44eUL} },
-    { &fnv_test_str[151], (Fnv64_t) {0x6eef3290UL, 0xfa6472ebUL} },
-    { &fnv_test_str[152], (Fnv64_t) {0x1948eb6aUL, 0x9e5d75ebUL} },
-    { &fnv_test_str[153], (Fnv64_t) {0xa8671852UL, 0xb6d12ad4UL} },
-    { &fnv_test_str[154], (Fnv64_t) {0xeba07af1UL, 0x88826f56UL} },
-    { &fnv_test_str[155], (Fnv64_t) {0x645bc0fdUL, 0x44535bf2UL} },
-    { &fnv_test_str[156], (Fnv64_t) {0xc21e3728UL, 0x169388ffUL} },
-    { &fnv_test_str[157], (Fnv64_t) {0x396d8224UL, 0xf68aac9eUL} },
-    { &fnv_test_str[158], (Fnv64_t) {0x472b3883UL, 0x8e87d7e7UL} },
-    { &fnv_test_str[159], (Fnv64_t) {0xa8b423deUL, 0x295c26caUL} },
-    { &fnv_test_str[160], (Fnv64_t) {0x92e72176UL, 0x322c8142UL} },
-    { &fnv_test_str[161], (Fnv64_t) {0xb8af7268UL, 0x8a06550eUL} },
-    { &fnv_test_str[162], (Fnv64_t) {0x661bcf71UL, 0xef86d60eUL} },
-    { &fnv_test_str[163], (Fnv64_t) {0x7f30ee54UL, 0x9e5426c8UL} },
-    { &fnv_test_str[164], (Fnv64_t) {0x26fd047eUL, 0xf1ea8aa8UL} },
-    { &fnv_test_str[165], (Fnv64_t) {0x642cb769UL, 0x0babaf9aUL} },
-    { &fnv_test_str[166], (Fnv64_t) {0x068d012eUL, 0x4b3341d4UL} },
-    { &fnv_test_str[167], (Fnv64_t) {0xc30a335cUL, 0xd15605cbUL} },
-    { &fnv_test_str[168], (Fnv64_t) {0xed8412e5UL, 0x5b21060aUL} },
-    { &fnv_test_str[169], (Fnv64_t) {0xce6f4227UL, 0x45e2cda1UL} },
-    { &fnv_test_str[170], (Fnv64_t) {0x033ad7d4UL, 0x50ae3745UL} },
-    { &fnv_test_str[171], (Fnv64_t) {0xd46bf414UL, 0xaa4588ceUL} },
-    { &fnv_test_str[172], (Fnv64_t) {0x4a95467eUL, 0xc1b0056cUL} },
-    { &fnv_test_str[173], (Fnv64_t) {0xde8b4089UL, 0x56576a71UL} },
-    { &fnv_test_str[174], (Fnv64_t) {0xa6dc927eUL, 0xbf20965fUL} },
-    { &fnv_test_str[175], (Fnv64_t) {0xc2040882UL, 0x569f8383UL} },
-    { &fnv_test_str[176], (Fnv64_t) {0xa08feca0UL, 0xe1e772fbUL} },
-    { &fnv_test_str[177], (Fnv64_t) {0x97138ac4UL, 0x4ced94afUL} },
-    { &fnv_test_str[178], (Fnv64_t) {0x337a82fbUL, 0xc4112ffbUL} },
-    { &fnv_test_str[179], (Fnv64_t) {0x1de38b7dUL, 0xd64a4fd4UL} },
-    { &fnv_test_str[180], (Fnv64_t) {0x9edebcbbUL, 0x4cfc3232UL} },
-    { &fnv_test_str[181], (Fnv64_t) {0x45050395UL, 0x08035644UL} },
-    { &fnv_test_str[182], (Fnv64_t) {0xf4642ffdUL, 0xaa1574ecUL} },
-    { &fnv_test_str[183], (Fnv64_t) {0x4cc315f9UL, 0x694bc4e5UL} },
-    { &fnv_test_str[184], (Fnv64_t) {0x3b011721UL, 0xa3d7cb27UL} },
-    { &fnv_test_str[185], (Fnv64_t) {0x6115bfa5UL, 0x577c2f8bUL} },
-    { &fnv_test_str[186], (Fnv64_t) {0x769fb4c1UL, 0xb7ec8c1aUL} },
-    { &fnv_test_str[187], (Fnv64_t) {0x3359ab19UL, 0x5d5cfce6UL} },
-    { &fnv_test_str[188], (Fnv64_t) {0xd65b5f71UL, 0x33b96c3cUL} },
-    { &fnv_test_str[189], (Fnv64_t) {0x80602bb9UL, 0xd8450977UL} },
-    { &fnv_test_str[190], (Fnv64_t) {0xd02da3d5UL, 0x84d47645UL} },
-    { &fnv_test_str[191], (Fnv64_t) {0xb58773a5UL, 0x83544f33UL} },
-    { &fnv_test_str[192], (Fnv64_t) {0x160836c5UL, 0x9175cbb2UL} },
-    { &fnv_test_str[193], (Fnv64_t) {0x75e72bc5UL, 0xc71b3bc1UL} },
-    { &fnv_test_str[194], (Fnv64_t) {0x222ec985UL, 0x636806acUL} },
-    { &fnv_test_str[195], (Fnv64_t) {0x50f52ed5UL, 0xb6ef0e69UL} },
-    { &fnv_test_str[196], (Fnv64_t) {0xf3dfdaa5UL, 0xead3d8a0UL} },
-    { &fnv_test_str[197], (Fnv64_t) {0x9a861ba5UL, 0x922908feUL} },
-    { &fnv_test_str[198], (Fnv64_t) {0x275fd5c5UL, 0x6d4821deUL} },
-    { &fnv_test_str[199], (Fnv64_t) {0x2bd816b5UL, 0x1fe3fce6UL} },
-    { &fnv_test_str[200], (Fnv64_t) {0xd6f70591UL, 0xc23e9fccUL} },
-    { &fnv_test_str[201], (Fnv64_t) {0xfe16b5b5UL, 0xc1af12bdUL} },
-    { &fnv_test_str[202], (Fnv64_t) {0x2f85e221UL, 0x39e9f18fUL} },
-    { NULL, (Fnv64_t) {0,0} }
-};
-#endif /* HAVE_64BIT_LONG_LONG */
-
-/* end of output generated by make vector.c */
-/*
- * insert the contents of vector.c above
- */
-
-
-/*
- * unknown_hash_type - report an unknown hash type error
- *
- * NOTE: Does not return.
- */
-void
-unknown_hash_type(char *prog, enum fnv_type type, int code)
-{
-    fprintf(stderr, "%s: unknown or unexpexted hash type: %d\n", prog, type);
-    exit(code);
-}
-
-
-/*
- * print_fnv32 - print an FNV hash
- *
- * given:
- *	hval	  the hash value to print
- *	mask	  lower bit mask
- *	verbose	  1 => print arg with hash
- *	arg	  string or filename arg
- */
-void
-print_fnv32(Fnv32_t hval, Fnv32_t mask, int verbose, char *arg)
-{
-    if (verbose) {
-	printf("0x%08lx %s\n", hval & mask, arg);
-    } else {
-	printf("0x%08lx\n", hval & mask);
-    }
-}
-
-
-/*
- * print_fnv64 - print an FNV hash
- *
- * given:
- *	hval	  the hash value to print
- *	mask	  lower bit mask
- *	verbose	  1 => print arg with hash
- *	arg	  string or filename arg
- */
-void
-print_fnv64(Fnv64_t hval, Fnv64_t mask, int verbose, char *arg)
-{
-#if defined(HAVE_64BIT_LONG_LONG)
-    if (verbose) {
-	printf("0x%016llx %s\n", hval & mask, arg);
-    } else {
-	printf("0x%016llx\n", hval & mask);
-    }
-#else
-    if (verbose) {
-	printf("0x%08lx%08lx %s\n",
-	       hval.w32[1] & mask.w32[1],
-	       hval.w32[0] & mask.w32[0],
-	       arg);
-    } else {
-	printf("0x%08lx%08lx\n",
-	       hval.w32[1] & mask.w32[1],
-	       hval.w32[0] & mask.w32[0]);
-    }
-#endif
-}
diff --git a/lib/lib8tion/LICENSE b/lib/lib8tion/LICENSE
deleted file mode 100644
index ebe476330b..0000000000
--- a/lib/lib8tion/LICENSE
+++ /dev/null
@@ -1,20 +0,0 @@
-The MIT License (MIT)
-
-Copyright (c) 2013 FastLED
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-the Software, and to permit persons to whom the Software is furnished to do so,
-subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
diff --git a/lib/lib8tion/lib8tion.c b/lib/lib8tion/lib8tion.c
deleted file mode 100644
index 84b3e9c61c..0000000000
--- a/lib/lib8tion/lib8tion.c
+++ /dev/null
@@ -1,242 +0,0 @@
-#define FASTLED_INTERNAL
-#include <stdint.h>
-
-#define RAND16_SEED  1337
-uint16_t rand16seed = RAND16_SEED;
-
-
-// memset8, memcpy8, memmove8:
-//  optimized avr replacements for the standard "C" library
-//  routines memset, memcpy, and memmove.
-//
-//  There are two techniques that make these routines
-//  faster than the standard avr-libc routines.
-//  First, the loops are unrolled 2X, meaning that
-//  the average loop overhead is cut in half.
-//  And second, the compare-and-branch at the bottom
-//  of each loop decrements the low byte of the
-//  counter, and if the carry is clear, it branches
-//  back up immediately.  Only if the low byte math
-//  causes carry do we bother to decrement the high
-//  byte and check that result for carry as well.
-//  Results for a 100-byte buffer are 20-40% faster
-//  than standard avr-libc, at a cost of a few extra
-//  bytes of code.
-
-#if defined(__AVR__)
-//__attribute__ ((noinline))
-void * memset8 ( void * ptr, uint8_t val, uint16_t num )
-{
-    asm volatile(
-         "  movw r26, %[ptr]        \n\t"
-         "  sbrs %A[num], 0         \n\t"
-         "  rjmp Lseteven_%=        \n\t"
-         "  rjmp Lsetodd_%=         \n\t"
-         "Lsetloop_%=:              \n\t"
-         "  st X+, %[val]           \n\t"
-         "Lsetodd_%=:               \n\t"
-         "  st X+, %[val]           \n\t"
-         "Lseteven_%=:              \n\t"
-         "  subi %A[num], 2         \n\t"
-         "  brcc Lsetloop_%=        \n\t"
-         "  sbci %B[num], 0         \n\t"
-         "  brcc Lsetloop_%=        \n\t"
-         : [num] "+r" (num)
-         : [ptr]  "r" (ptr),
-           [val]  "r" (val)
-         : "memory"
-         );
-    return ptr;
-}
-
-
-
-//__attribute__ ((noinline))
-void * memcpy8 ( void * dst, const void* src, uint16_t num )
-{
-    asm volatile(
-         "  movw r30, %[src]        \n\t"
-         "  movw r26, %[dst]        \n\t"
-         "  sbrs %A[num], 0         \n\t"
-         "  rjmp Lcpyeven_%=        \n\t"
-         "  rjmp Lcpyodd_%=         \n\t"
-         "Lcpyloop_%=:              \n\t"
-         "  ld __tmp_reg__, Z+      \n\t"
-         "  st X+, __tmp_reg__      \n\t"
-         "Lcpyodd_%=:               \n\t"
-         "  ld __tmp_reg__, Z+      \n\t"
-         "  st X+, __tmp_reg__      \n\t"
-         "Lcpyeven_%=:              \n\t"
-         "  subi %A[num], 2         \n\t"
-         "  brcc Lcpyloop_%=        \n\t"
-         "  sbci %B[num], 0         \n\t"
-         "  brcc Lcpyloop_%=        \n\t"
-         : [num] "+r" (num)
-         : [src] "r" (src),
-           [dst] "r" (dst)
-         : "memory"
-         );
-    return dst;
-}
-
-//__attribute__ ((noinline))
-void * memmove8 ( void * dst, const void* src, uint16_t num )
-{
-    if( src > dst) {
-        // if src > dst then we can use the forward-stepping memcpy8
-        return memcpy8( dst, src, num);
-    } else {
-        // if src < dst then we have to step backward:
-        dst = (char*)dst + num;
-        src = (char*)src + num;
-        asm volatile(
-             "  movw r30, %[src]        \n\t"
-             "  movw r26, %[dst]        \n\t"
-             "  sbrs %A[num], 0         \n\t"
-             "  rjmp Lmoveven_%=        \n\t"
-             "  rjmp Lmovodd_%=         \n\t"
-             "Lmovloop_%=:              \n\t"
-             "  ld __tmp_reg__, -Z      \n\t"
-             "  st -X, __tmp_reg__      \n\t"
-             "Lmovodd_%=:               \n\t"
-             "  ld __tmp_reg__, -Z      \n\t"
-             "  st -X, __tmp_reg__      \n\t"
-             "Lmoveven_%=:              \n\t"
-             "  subi %A[num], 2         \n\t"
-             "  brcc Lmovloop_%=        \n\t"
-             "  sbci %B[num], 0         \n\t"
-             "  brcc Lmovloop_%=        \n\t"
-             : [num] "+r" (num)
-             : [src] "r" (src),
-               [dst] "r" (dst)
-             : "memory"
-             );
-        return dst;
-    }
-}
-
-#endif /* AVR */
-
-
-
-
-#if 0
-// TEST / VERIFICATION CODE ONLY BELOW THIS POINT
-#include <Arduino.h>
-#include "lib8tion.h"
-
-void test1abs( int8_t i)
-{
-    Serial.print("abs("); Serial.print(i); Serial.print(") = ");
-    int8_t j = abs8(i);
-    Serial.print(j); Serial.println(" ");
-}
-
-void testabs()
-{
-    delay(5000);
-    for( int8_t q = -128; q != 127; q++) {
-        test1abs(q);
-    }
-    for(;;){};
-}
-
-
-void testmul8()
-{
-    delay(5000);
-    byte r, c;
-
-    Serial.println("mul8:");
-    for( r = 0; r <= 20; r += 1) {
-        Serial.print(r); Serial.print(" : ");
-        for( c = 0; c <= 20; c += 1) {
-            byte t;
-            t = mul8( r, c);
-            Serial.print(t); Serial.print(' ');
-        }
-        Serial.println(' ');
-    }
-    Serial.println("done.");
-    for(;;){};
-}
-
-
-void testscale8()
-{
-    delay(5000);
-    byte r, c;
-
-    Serial.println("scale8:");
-    for( r = 0; r <= 240; r += 10) {
-        Serial.print(r); Serial.print(" : ");
-        for( c = 0; c <= 240; c += 10) {
-            byte t;
-            t = scale8( r, c);
-            Serial.print(t); Serial.print(' ');
-        }
-        Serial.println(' ');
-    }
-
-    Serial.println(' ');
-    Serial.println("scale8_video:");
-
-    for( r = 0; r <= 100; r += 4) {
-        Serial.print(r); Serial.print(" : ");
-        for( c = 0; c <= 100; c += 4) {
-            byte t;
-            t = scale8_video( r, c);
-            Serial.print(t); Serial.print(' ');
-        }
-        Serial.println(' ');
-    }
-
-    Serial.println("done.");
-    for(;;){};
-}
-
-
-
-void testqadd8()
-{
-    delay(5000);
-    byte r, c;
-    for( r = 0; r <= 240; r += 10) {
-        Serial.print(r); Serial.print(" : ");
-        for( c = 0; c <= 240; c += 10) {
-            byte t;
-            t = qadd8( r, c);
-            Serial.print(t); Serial.print(' ');
-        }
-        Serial.println(' ');
-    }
-    Serial.println("done.");
-    for(;;){};
-}
-
-void testnscale8x3()
-{
-    delay(5000);
-    byte r, g, b, sc;
-    for( byte z = 0; z < 10; z++) {
-        r = random8(); g = random8(); b = random8(); sc = random8();
-
-        Serial.print("nscale8x3_video( ");
-        Serial.print(r); Serial.print(", ");
-        Serial.print(g); Serial.print(", ");
-        Serial.print(b); Serial.print(", ");
-        Serial.print(sc); Serial.print(") = [ ");
-
-        nscale8x3_video( r, g, b, sc);
-
-        Serial.print(r); Serial.print(", ");
-        Serial.print(g); Serial.print(", ");
-        Serial.print(b); Serial.print("]");
-
-        Serial.println(' ');
-    }
-    Serial.println("done.");
-    for(;;){};
-}
-
-#endif
diff --git a/lib/lib8tion/lib8tion.h b/lib/lib8tion/lib8tion.h
deleted file mode 100644
index 4c770cbcb5..0000000000
--- a/lib/lib8tion/lib8tion.h
+++ /dev/null
@@ -1,934 +0,0 @@
-#ifndef __INC_LIB8TION_H
-#define __INC_LIB8TION_H
-
-/*
-
- Fast, efficient 8-bit math functions specifically
- designed for high-performance LED programming.
-
- Because of the AVR(Arduino) and ARM assembly language
- implementations provided, using these functions often
- results in smaller and faster code than the equivalent
- program using plain "C" arithmetic and logic.
-
-
- Included are:
-
-
- - Saturating unsigned 8-bit add and subtract.
-   Instead of wrapping around if an overflow occurs,
-   these routines just 'clamp' the output at a maxumum
-   of 255, or a minimum of 0.  Useful for adding pixel
-   values.  E.g., qadd8( 200, 100) = 255.
-
-     qadd8( i, j) == MIN( (i + j), 0xFF )
-     qsub8( i, j) == MAX( (i - j), 0 )
-
- - Saturating signed 8-bit ("7-bit") add.
-     qadd7( i, j) == MIN( (i + j), 0x7F)
-
-
- - Scaling (down) of unsigned 8- and 16- bit values.
-   Scaledown value is specified in 1/256ths.
-     scale8( i, sc) == (i * sc) / 256
-     scale16by8( i, sc) == (i * sc) / 256
-
-   Example: scaling a 0-255 value down into a
-   range from 0-99:
-     downscaled = scale8( originalnumber, 100);
-
-   A special version of scale8 is provided for scaling
-   LED brightness values, to make sure that they don't
-   accidentally scale down to total black at low
-   dimming levels, since that would look wrong:
-     scale8_video( i, sc) = ((i * sc) / 256) +? 1
-
-   Example: reducing an LED brightness by a
-   dimming factor:
-     new_bright = scale8_video( orig_bright, dimming);
-
-
- - Fast 8- and 16- bit unsigned random numbers.
-   Significantly faster than Arduino random(), but
-   also somewhat less random.  You can add entropy.
-     random8()       == random from 0..255
-     random8( n)     == random from 0..(N-1)
-     random8( n, m)  == random from N..(M-1)
-
-     random16()      == random from 0..65535
-     random16( n)    == random from 0..(N-1)
-     random16( n, m) == random from N..(M-1)
-
-     random16_set_seed( k)    ==  seed = k
-     random16_add_entropy( k) ==  seed += k
-
-
- - Absolute value of a signed 8-bit value.
-     abs8( i)     == abs( i)
-
-
- - 8-bit math operations which return 8-bit values.
-   These are provided mostly for completeness,
-   not particularly for performance.
-     mul8( i, j)  == (i * j) & 0xFF
-     add8( i, j)  == (i + j) & 0xFF
-     sub8( i, j)  == (i - j) & 0xFF
-
-
- - Fast 16-bit approximations of sin and cos.
-   Input angle is a uint16_t from 0-65535.
-   Output is a signed int16_t from -32767 to 32767.
-      sin16( x)  == sin( (x/32768.0) * pi) * 32767
-      cos16( x)  == cos( (x/32768.0) * pi) * 32767
-   Accurate to more than 99% in all cases.
-
- - Fast 8-bit approximations of sin and cos.
-   Input angle is a uint8_t from 0-255.
-   Output is an UNsigned uint8_t from 0 to 255.
-       sin8( x)  == (sin( (x/128.0) * pi) * 128) + 128
-       cos8( x)  == (cos( (x/128.0) * pi) * 128) + 128
-   Accurate to within about 2%.
-
-
- - Fast 8-bit "easing in/out" function.
-     ease8InOutCubic(x) == 3(x^i) - 2(x^3)
-     ease8InOutApprox(x) ==
-       faster, rougher, approximation of cubic easing
-     ease8InOutQuad(x) == quadratic (vs cubic) easing
-
- - Cubic, Quadratic, and Triangle wave functions.
-   Input is a uint8_t representing phase withing the wave,
-     similar to how sin8 takes an angle 'theta'.
-   Output is a uint8_t representing the amplitude of
-     the wave at that point.
-       cubicwave8( x)
-       quadwave8( x)
-       triwave8( x)
-
- - Square root for 16-bit integers.  About three times
-   faster and five times smaller than Arduino's built-in
-   generic 32-bit sqrt routine.
-     sqrt16( uint16_t x ) == sqrt( x)
-
- - Dimming and brightening functions for 8-bit
-   light values.
-     dim8_video( x)  == scale8_video( x, x)
-     dim8_raw( x)    == scale8( x, x)
-     dim8_lin( x)    == (x<128) ? ((x+1)/2) : scale8(x,x)
-     brighten8_video( x) == 255 - dim8_video( 255 - x)
-     brighten8_raw( x) == 255 - dim8_raw( 255 - x)
-     brighten8_lin( x) == 255 - dim8_lin( 255 - x)
-   The dimming functions in particular are suitable
-   for making LED light output appear more 'linear'.
-
-
- - Linear interpolation between two values, with the
-   fraction between them expressed as an 8- or 16-bit
-   fixed point fraction (fract8 or fract16).
-     lerp8by8(   fromU8, toU8, fract8 )
-     lerp16by8(  fromU16, toU16, fract8 )
-     lerp15by8(  fromS16, toS16, fract8 )
-       == from + (( to - from ) * fract8) / 256)
-     lerp16by16( fromU16, toU16, fract16 )
-       == from + (( to - from ) * fract16) / 65536)
-     map8( in, rangeStart, rangeEnd)
-       == map( in, 0, 255, rangeStart, rangeEnd);
-
- - Optimized memmove, memcpy, and memset, that are
-   faster than standard avr-libc 1.8.
-      memmove8( dest, src,  bytecount)
-      memcpy8(  dest, src,  bytecount)
-      memset8(  buf, value, bytecount)
-
- - Beat generators which return sine or sawtooth
-   waves in a specified number of Beats Per Minute.
-   Sine wave beat generators can specify a low and
-   high range for the output.  Sawtooth wave beat
-   generators always range 0-255 or 0-65535.
-     beatsin8( BPM, low8, high8)
-         = (sine(beatphase) * (high8-low8)) + low8
-     beatsin16( BPM, low16, high16)
-         = (sine(beatphase) * (high16-low16)) + low16
-     beatsin88( BPM88, low16, high16)
-         = (sine(beatphase) * (high16-low16)) + low16
-     beat8( BPM)  = 8-bit repeating sawtooth wave
-     beat16( BPM) = 16-bit repeating sawtooth wave
-     beat88( BPM88) = 16-bit repeating sawtooth wave
-   BPM is beats per minute in either simple form
-   e.g. 120, or Q8.8 fixed-point form.
-   BPM88 is beats per minute in ONLY Q8.8 fixed-point
-   form.
-
-Lib8tion is pronounced like 'libation': lie-BAY-shun
-
-*/
-
-
-
-#include <stdint.h>
-
-#define LIB8STATIC static inline
-#define LIB8STATIC_ALWAYS_INLINE static inline
-
-#if !defined(__AVR__)
-#include <string.h>
-// for memmove, memcpy, and memset if not defined here
-#endif
-
-#if defined(__arm__)
-
-#if defined(FASTLED_TEENSY3)
-// Can use Cortex M4 DSP instructions
-#define QADD8_C 0
-#define QADD7_C 0
-#define QADD8_ARM_DSP_ASM 1
-#define QADD7_ARM_DSP_ASM 1
-#else
-// Generic ARM
-#define QADD8_C 1
-#define QADD7_C 1
-#endif
-
-#define QSUB8_C 1
-#define SCALE8_C 1
-#define SCALE16BY8_C 1
-#define SCALE16_C 1
-#define ABS8_C 1
-#define MUL8_C 1
-#define QMUL8_C 1
-#define ADD8_C 1
-#define SUB8_C 1
-#define EASE8_C 1
-#define AVG8_C 1
-#define AVG7_C 1
-#define AVG16_C 1
-#define AVG15_C 1
-#define BLEND8_C 1
-
-
-#elif defined(__AVR__)
-
-// AVR ATmega and friends Arduino
-
-#define QADD8_C 0
-#define QADD7_C 0
-#define QSUB8_C 0
-#define ABS8_C 0
-#define ADD8_C 0
-#define SUB8_C 0
-#define AVG8_C 0
-#define AVG7_C 0
-#define AVG16_C 0
-#define AVG15_C 0
-
-#define QADD8_AVRASM 1
-#define QADD7_AVRASM 1
-#define QSUB8_AVRASM 1
-#define ABS8_AVRASM 1
-#define ADD8_AVRASM 1
-#define SUB8_AVRASM 1
-#define AVG8_AVRASM 1
-#define AVG7_AVRASM 1
-#define AVG16_AVRASM 1
-#define AVG15_AVRASM 1
-
-// Note: these require hardware MUL instruction
-//       -- sorry, ATtiny!
-#if !defined(LIB8_ATTINY)
-#define SCALE8_C 0
-#define SCALE16BY8_C 0
-#define SCALE16_C 0
-#define MUL8_C 0
-#define QMUL8_C 0
-#define EASE8_C 0
-#define BLEND8_C 0
-#define SCALE8_AVRASM 1
-#define SCALE16BY8_AVRASM 1
-#define SCALE16_AVRASM 1
-#define MUL8_AVRASM 1
-#define QMUL8_AVRASM 1
-#define EASE8_AVRASM 1
-#define CLEANUP_R1_AVRASM 1
-#define BLEND8_AVRASM 1
-#else
-// On ATtiny, we just use C implementations
-#define SCALE8_C 1
-#define SCALE16BY8_C 1
-#define SCALE16_C 1
-#define MUL8_C 1
-#define QMUL8_C 1
-#define EASE8_C 1
-#define BLEND8_C 1
-#define SCALE8_AVRASM 0
-#define SCALE16BY8_AVRASM 0
-#define SCALE16_AVRASM 0
-#define MUL8_AVRASM 0
-#define QMUL8_AVRASM 0
-#define EASE8_AVRASM 0
-#define BLEND8_AVRASM 0
-#endif
-
-#else
-
-// unspecified architecture, so
-// no ASM, everything in C
-#define QADD8_C 1
-#define QADD7_C 1
-#define QSUB8_C 1
-#define SCALE8_C 1
-#define SCALE16BY8_C 1
-#define SCALE16_C 1
-#define ABS8_C 1
-#define MUL8_C 1
-#define QMUL8_C 1
-#define ADD8_C 1
-#define SUB8_C 1
-#define EASE8_C 1
-#define AVG8_C 1
-#define AVG7_C 1
-#define AVG16_C 1
-#define AVG15_C 1
-#define BLEND8_C 1
-
-#endif
-
-///@defgroup lib8tion Fast math functions
-///A variety of functions for working with numbers.
-///@{
-
-
-///////////////////////////////////////////////////////////////////////
-//
-// typdefs for fixed-point fractional types.
-//
-// sfract7 should be interpreted as signed 128ths.
-// fract8 should be interpreted as unsigned 256ths.
-// sfract15 should be interpreted as signed 32768ths.
-// fract16 should be interpreted as unsigned 65536ths.
-//
-// Example: if a fract8 has the value "64", that should be interpreted
-//          as 64/256ths, or one-quarter.
-//
-//
-//  fract8   range is 0 to 0.99609375
-//                 in steps of 0.00390625
-//
-//  sfract7  range is -0.9921875 to 0.9921875
-//                 in steps of 0.0078125
-//
-//  fract16  range is 0 to 0.99998474121
-//                 in steps of 0.00001525878
-//
-//  sfract15 range is -0.99996948242 to 0.99996948242
-//                 in steps of 0.00003051757
-//
-
-/// ANSI unsigned short _Fract.  range is 0 to 0.99609375
-///                 in steps of 0.00390625
-typedef uint8_t   fract8;   ///< ANSI: unsigned short _Fract
-
-///  ANSI: signed short _Fract.  range is -0.9921875 to 0.9921875
-///                 in steps of 0.0078125
-typedef int8_t    sfract7;  ///< ANSI: signed   short _Fract
-
-///  ANSI: unsigned _Fract.  range is 0 to 0.99998474121
-///                 in steps of 0.00001525878
-typedef uint16_t  fract16;  ///< ANSI: unsigned       _Fract
-
-///  ANSI: signed _Fract.  range is -0.99996948242 to 0.99996948242
-///                 in steps of 0.00003051757
-typedef int16_t   sfract15; ///< ANSI: signed         _Fract
-
-
-// accumXY types should be interpreted as X bits of integer,
-//         and Y bits of fraction.
-//         E.g., accum88 has 8 bits of int, 8 bits of fraction
-
-typedef uint16_t  accum88;  ///< ANSI: unsigned short _Accum.  8 bits int, 8 bits fraction
-typedef int16_t   saccum78; ///< ANSI: signed   short _Accum.  7 bits int, 8 bits fraction
-typedef uint32_t  accum1616;///< ANSI: signed         _Accum. 16 bits int, 16 bits fraction
-typedef int32_t   saccum1516;///< ANSI: signed         _Accum. 15 bits int, 16 bits fraction
-typedef uint16_t  accum124; ///< no direct ANSI counterpart. 12 bits int, 4 bits fraction
-typedef int32_t   saccum114;///< no direct ANSI counterpart. 1 bit int, 14 bits fraction
-
-
-
-#include "math8.h"
-#include "scale8.h"
-#include "random8.h"
-#include "trig8.h"
-
-///////////////////////////////////////////////////////////////////////
-
-
-
-
-
-
-
-///////////////////////////////////////////////////////////////////////
-//
-// float-to-fixed and fixed-to-float conversions
-//
-// Note that anything involving a 'float' on AVR will be slower.
-
-/// sfract15ToFloat: conversion from sfract15 fixed point to
-///                  IEEE754 32-bit float.
-LIB8STATIC float sfract15ToFloat( sfract15 y)
-{
-    return y / 32768.0;
-}
-
-/// conversion from IEEE754 float in the range (-1,1)
-///                  to 16-bit fixed point.  Note that the extremes of
-///                  one and negative one are NOT representable.  The
-///                  representable range is basically
-LIB8STATIC sfract15 floatToSfract15( float f)
-{
-    return f * 32768.0;
-}
-
-
-
-///////////////////////////////////////////////////////////////////////
-//
-// memmove8, memcpy8, and memset8:
-//   alternatives to memmove, memcpy, and memset that are
-//   faster on AVR than standard avr-libc 1.8
-
-#if defined(__AVR__)
-void * memmove8( void * dst, const void * src, uint16_t num );
-void * memcpy8 ( void * dst, const void * src, uint16_t num )  __attribute__ ((noinline));
-void * memset8 ( void * ptr, uint8_t value, uint16_t num ) __attribute__ ((noinline)) ;
-#else
-// on non-AVR platforms, these names just call standard libc.
-#define memmove8 memmove
-#define memcpy8 memcpy
-#define memset8 memset
-#endif
-
-
-///////////////////////////////////////////////////////////////////////
-//
-// linear interpolation, such as could be used for Perlin noise, etc.
-//
-
-// A note on the structure of the lerp functions:
-// The cases for b>a and b<=a are handled separately for
-// speed: without knowing the relative order of a and b,
-// the value (a-b) might be overflow the width of a or b,
-// and have to be promoted to a wider, slower type.
-// To avoid that, we separate the two cases, and are able
-// to do all the math in the same width as the arguments,
-// which is much faster and smaller on AVR.
-
-/// linear interpolation between two unsigned 8-bit values,
-/// with 8-bit fraction
-LIB8STATIC uint8_t lerp8by8( uint8_t a, uint8_t b, fract8 frac)
-{
-    uint8_t result;
-    if( b > a) {
-        uint8_t delta = b - a;
-        uint8_t scaled = scale8( delta, frac);
-        result = a + scaled;
-    } else {
-        uint8_t delta = a - b;
-        uint8_t scaled = scale8( delta, frac);
-        result = a - scaled;
-    }
-    return result;
-}
-
-/// linear interpolation between two unsigned 16-bit values,
-/// with 16-bit fraction
-LIB8STATIC uint16_t lerp16by16( uint16_t a, uint16_t b, fract16 frac)
-{
-    uint16_t result;
-    if( b > a ) {
-        uint16_t delta = b - a;
-        uint16_t scaled = scale16(delta, frac);
-        result = a + scaled;
-    } else {
-        uint16_t delta = a - b;
-        uint16_t scaled = scale16( delta, frac);
-        result = a - scaled;
-    }
-    return result;
-}
-
-/// linear interpolation between two unsigned 16-bit values,
-/// with 8-bit fraction
-LIB8STATIC uint16_t lerp16by8( uint16_t a, uint16_t b, fract8 frac)
-{
-    uint16_t result;
-    if( b > a) {
-        uint16_t delta = b - a;
-        uint16_t scaled = scale16by8( delta, frac);
-        result = a + scaled;
-    } else {
-        uint16_t delta = a - b;
-        uint16_t scaled = scale16by8( delta, frac);
-        result = a - scaled;
-    }
-    return result;
-}
-
-/// linear interpolation between two signed 15-bit values,
-/// with 8-bit fraction
-LIB8STATIC int16_t lerp15by8( int16_t a, int16_t b, fract8 frac)
-{
-    int16_t result;
-    if( b > a) {
-        uint16_t delta = b - a;
-        uint16_t scaled = scale16by8( delta, frac);
-        result = a + scaled;
-    } else {
-        uint16_t delta = a - b;
-        uint16_t scaled = scale16by8( delta, frac);
-        result = a - scaled;
-    }
-    return result;
-}
-
-/// linear interpolation between two signed 15-bit values,
-/// with 8-bit fraction
-LIB8STATIC int16_t lerp15by16( int16_t a, int16_t b, fract16 frac)
-{
-    int16_t result;
-    if( b > a) {
-        uint16_t delta = b - a;
-        uint16_t scaled = scale16( delta, frac);
-        result = a + scaled;
-    } else {
-        uint16_t delta = a - b;
-        uint16_t scaled = scale16( delta, frac);
-        result = a - scaled;
-    }
-    return result;
-}
-
-///  map8: map from one full-range 8-bit value into a narrower
-/// range of 8-bit values, possibly a range of hues.
-///
-/// E.g. map myValue into a hue in the range blue..purple..pink..red
-/// hue = map8( myValue, HUE_BLUE, HUE_RED);
-///
-/// Combines nicely with the waveform functions (like sin8, etc)
-/// to produce continuous hue gradients back and forth:
-///
-///          hue = map8( sin8( myValue), HUE_BLUE, HUE_RED);
-///
-/// Mathematically simiar to lerp8by8, but arguments are more
-/// like Arduino's "map"; this function is similar to
-///
-///          map( in, 0, 255, rangeStart, rangeEnd)
-///
-/// but faster and specifically designed for 8-bit values.
-LIB8STATIC uint8_t map8( uint8_t in, uint8_t rangeStart, uint8_t rangeEnd)
-{
-    uint8_t rangeWidth = rangeEnd - rangeStart;
-    uint8_t out = scale8( in, rangeWidth);
-    out += rangeStart;
-    return out;
-}
-
-
-///////////////////////////////////////////////////////////////////////
-//
-// easing functions; see http://easings.net
-//
-
-/// ease8InOutQuad: 8-bit quadratic ease-in / ease-out function
-///                Takes around 13 cycles on AVR
-#if EASE8_C == 1
-LIB8STATIC uint8_t ease8InOutQuad( uint8_t i)
-{
-    uint8_t j = i;
-    if( j & 0x80 ) {
-        j = 255 - j;
-    }
-    uint8_t jj  = scale8(  j, j);
-    uint8_t jj2 = jj << 1;
-    if( i & 0x80 ) {
-        jj2 = 255 - jj2;
-    }
-    return jj2;
-}
-
-#elif EASE8_AVRASM == 1
-// This AVR asm version of ease8InOutQuad preserves one more
-// low-bit of precision than the C version, and is also slightly
-// smaller and faster.
-LIB8STATIC uint8_t ease8InOutQuad(uint8_t val) {
-    uint8_t j=val;
-    asm volatile (
-      "sbrc %[val], 7 \n"
-      "com %[j]       \n"
-      "mul %[j], %[j] \n"
-      "add r0, %[j]   \n"
-      "ldi %[j], 0    \n"
-      "adc %[j], r1   \n"
-      "lsl r0         \n" // carry = high bit of low byte of mul product
-      "rol %[j]       \n" // j = (j * 2) + carry // preserve add'l bit of precision
-      "sbrc %[val], 7 \n"
-      "com %[j]       \n"
-      "clr __zero_reg__   \n"
-      : [j] "+&a" (j)
-      : [val] "a" (val)
-      : "r0", "r1"
-      );
-    return j;
-}
-
-#else
-#error "No implementation for ease8InOutQuad available."
-#endif
-
-/// ease16InOutQuad: 16-bit quadratic ease-in / ease-out function
-// C implementation at this point
-LIB8STATIC uint16_t ease16InOutQuad( uint16_t i)
-{
-    uint16_t j = i;
-    if( j & 0x8000 ) {
-        j = 65535 - j;
-    }
-    uint16_t jj  = scale16( j, j);
-    uint16_t jj2 = jj << 1;
-    if( i & 0x8000 ) {
-        jj2 = 65535 - jj2;
-    }
-    return jj2;
-}
-
-
-/// ease8InOutCubic: 8-bit cubic ease-in / ease-out function
-///                 Takes around 18 cycles on AVR
-LIB8STATIC fract8 ease8InOutCubic( fract8 i)
-{
-    uint8_t ii  = scale8_LEAVING_R1_DIRTY(  i, i);
-    uint8_t iii = scale8_LEAVING_R1_DIRTY( ii, i);
-
-    uint16_t r1 = (3 * (uint16_t)(ii)) - ( 2 * (uint16_t)(iii));
-
-    /* the code generated for the above *'s automatically
-       cleans up R1, so there's no need to explicitily call
-       cleanup_R1(); */
-
-    uint8_t result = r1;
-
-    // if we got "256", return 255:
-    if( r1 & 0x100 ) {
-        result = 255;
-    }
-    return result;
-}
-
-/// ease8InOutApprox: fast, rough 8-bit ease-in/ease-out function
-///                   shaped approximately like 'ease8InOutCubic',
-///                   it's never off by more than a couple of percent
-///                   from the actual cubic S-curve, and it executes
-///                   more than twice as fast.  Use when the cycles
-///                   are more important than visual smoothness.
-///                   Asm version takes around 7 cycles on AVR.
-
-#if EASE8_C == 1
-LIB8STATIC fract8 ease8InOutApprox( fract8 i)
-{
-    if( i < 64) {
-        // start with slope 0.5
-        i /= 2;
-    } else if( i > (255 - 64)) {
-        // end with slope 0.5
-        i = 255 - i;
-        i /= 2;
-        i = 255 - i;
-    } else {
-        // in the middle, use slope 192/128 = 1.5
-        i -= 64;
-        i += (i / 2);
-        i += 32;
-    }
-
-    return i;
-}
-
-#elif EASE8_AVRASM == 1
-LIB8STATIC uint8_t ease8InOutApprox( fract8 i)
-{
-    // takes around 7 cycles on AVR
-    asm volatile (
-        "  subi %[i], 64         \n\t"
-        "  cpi  %[i], 128        \n\t"
-        "  brcc Lshift_%=        \n\t"
-
-        // middle case
-        "  mov __tmp_reg__, %[i] \n\t"
-        "  lsr __tmp_reg__       \n\t"
-        "  add %[i], __tmp_reg__ \n\t"
-        "  subi %[i], 224        \n\t"
-        "  rjmp Ldone_%=         \n\t"
-
-        // start or end case
-        "Lshift_%=:              \n\t"
-        "  lsr %[i]              \n\t"
-        "  subi %[i], 96         \n\t"
-
-        "Ldone_%=:               \n\t"
-
-        : [i] "+&a" (i)
-        :
-        : "r0", "r1"
-        );
-    return i;
-}
-#else
-#error "No implementation for ease8 available."
-#endif
-
-
-
-/// triwave8: triangle (sawtooth) wave generator.  Useful for
-///           turning a one-byte ever-increasing value into a
-///           one-byte value that oscillates up and down.
-///
-///           input         output
-///           0..127        0..254 (positive slope)
-///           128..255      254..0 (negative slope)
-///
-/// On AVR this function takes just three cycles.
-///
-LIB8STATIC uint8_t triwave8(uint8_t in)
-{
-    if( in & 0x80) {
-        in = 255 - in;
-    }
-    uint8_t out = in << 1;
-    return out;
-}
-
-
-// quadwave8 and cubicwave8: S-shaped wave generators (like 'sine').
-//           Useful for turning a one-byte 'counter' value into a
-//           one-byte oscillating value that moves smoothly up and down,
-//           with an 'acceleration' and 'deceleration' curve.
-//
-//           These are even faster than 'sin8', and have
-//           slightly different curve shapes.
-//
-
-/// quadwave8: quadratic waveform generator.  Spends just a little more
-///            time at the limits than 'sine' does.
-LIB8STATIC uint8_t quadwave8(uint8_t in)
-{
-    return ease8InOutQuad( triwave8( in));
-}
-
-/// cubicwave8: cubic waveform generator.  Spends visibly more time
-///             at the limits than 'sine' does.
-LIB8STATIC uint8_t cubicwave8(uint8_t in)
-{
-    return ease8InOutCubic( triwave8( in));
-}
-
-/// squarewave8: square wave generator.  Useful for
-///           turning a one-byte ever-increasing value
-///           into a one-byte value that is either 0 or 255.
-///           The width of the output 'pulse' is
-///           determined by the pulsewidth argument:
-///
-///~~~
-///           If pulsewidth is 255, output is always 255.
-///           If pulsewidth < 255, then
-///             if input < pulsewidth  then output is 255
-///             if input >= pulsewidth then output is 0
-///~~~
-///
-/// the output looking like:
-///
-///~~~
-///     255   +--pulsewidth--+
-///      .    |              |
-///      0    0              +--------(256-pulsewidth)--------
-///~~~
-///
-/// @param in
-/// @param pulsewidth
-/// @returns square wave output
-LIB8STATIC uint8_t squarewave8( uint8_t in, uint8_t pulsewidth)
-{
-    if( in < pulsewidth || (pulsewidth == 255)) {
-        return 255;
-    } else {
-        return 0;
-    }
-}
-
-
-// Beat generators - These functions produce waves at a given
-//                   number of 'beats per minute'.  Internally, they use
-//                   the Arduino function 'millis' to track elapsed time.
-//                   Accuracy is a bit better than one part in a thousand.
-//
-//       beat8( BPM ) returns an 8-bit value that cycles 'BPM' times
-//                    per minute, rising from 0 to 255, resetting to zero,
-//                    rising up again, etc..  The output of this function
-//                    is suitable for feeding directly into sin8, and cos8,
-//                    triwave8, quadwave8, and cubicwave8.
-//       beat16( BPM ) returns a 16-bit value that cycles 'BPM' times
-//                    per minute, rising from 0 to 65535, resetting to zero,
-//                    rising up again, etc.  The output of this function is
-//                    suitable for feeding directly into sin16 and cos16.
-//       beat88( BPM88) is the same as beat16, except that the BPM88 argument
-//                    MUST be in Q8.8 fixed point format, e.g. 120BPM must
-//                    be specified as 120*256 = 30720.
-//       beatsin8( BPM, uint8_t low, uint8_t high) returns an 8-bit value that
-//                    rises and falls in a sine wave, 'BPM' times per minute,
-//                    between the values of 'low' and 'high'.
-//       beatsin16( BPM, uint16_t low, uint16_t high) returns a 16-bit value
-//                    that rises and falls in a sine wave, 'BPM' times per
-//                    minute, between the values of 'low' and 'high'.
-//       beatsin88( BPM88, ...) is the same as beatsin16, except that the
-//                    BPM88 argument MUST be in Q8.8 fixed point format,
-//                    e.g. 120BPM must be specified as 120*256 = 30720.
-//
-//  BPM can be supplied two ways.  The simpler way of specifying BPM is as
-//  a simple 8-bit integer from 1-255, (e.g., "120").
-//  The more sophisticated way of specifying BPM allows for fractional
-//  "Q8.8" fixed point number (an 'accum88') with an 8-bit integer part and
-//  an 8-bit fractional part.  The easiest way to construct this is to multiply
-//  a floating point BPM value (e.g. 120.3) by 256, (e.g. resulting in 30796
-//  in this case), and pass that as the 16-bit BPM argument.
-//  "BPM88" MUST always be specified in Q8.8 format.
-//
-//  Originally designed to make an entire animation project pulse with brightness.
-//  For that effect, add this line just above your existing call to "FastLED.show()":
-//
-//     uint8_t bright = beatsin8( 60 /*BPM*/, 192 /*dimmest*/, 255 /*brightest*/ ));
-//     FastLED.setBrightness( bright );
-//     FastLED.show();
-//
-//  The entire animation will now pulse between brightness 192 and 255 once per second.
-
-
-// The beat generators need access to a millisecond counter.
-// On Arduino, this is "millis()".  On other platforms, you'll
-// need to provide a function with this signature:
-//   uint32_t get_millisecond_timer();
-// that provides similar functionality.
-// You can also force use of the get_millisecond_timer function
-// by #defining USE_GET_MILLISECOND_TIMER.
-#if (defined(ARDUINO) || defined(SPARK) || defined(FASTLED_HAS_MILLIS)) && !defined(USE_GET_MILLISECOND_TIMER)
-// Forward declaration of Arduino function 'millis'.
-//uint32_t millis();
-#define GET_MILLIS millis
-#else
-uint32_t get_millisecond_timer(void);
-#define GET_MILLIS get_millisecond_timer
-#endif
-
-// beat16 generates a 16-bit 'sawtooth' wave at a given BPM,
-///        with BPM specified in Q8.8 fixed-point format; e.g.
-///        for this function, 120 BPM MUST BE specified as
-///        120*256 = 30720.
-///        If you just want to specify "120", use beat16 or beat8.
-LIB8STATIC uint16_t beat88( accum88 beats_per_minute_88, uint32_t timebase)
-{
-    // BPM is 'beats per minute', or 'beats per 60000ms'.
-    // To avoid using the (slower) division operator, we
-    // want to convert 'beats per 60000ms' to 'beats per 65536ms',
-    // and then use a simple, fast bit-shift to divide by 65536.
-    //
-    // The ratio 65536:60000 is 279.620266667:256; we'll call it 280:256.
-    // The conversion is accurate to about 0.05%, more or less,
-    // e.g. if you ask for "120 BPM", you'll get about "119.93".
-    return (((GET_MILLIS()) - timebase) * beats_per_minute_88 * 280) >> 16;
-}
-
-/// beat16 generates a 16-bit 'sawtooth' wave at a given BPM
-LIB8STATIC uint16_t beat16( accum88 beats_per_minute, uint32_t timebase)
-{
-    // Convert simple 8-bit BPM's to full Q8.8 accum88's if needed
-    if( beats_per_minute < 256) beats_per_minute <<= 8;
-    return beat88(beats_per_minute, timebase);
-}
-
-/// beat8 generates an 8-bit 'sawtooth' wave at a given BPM
-LIB8STATIC uint8_t beat8( accum88 beats_per_minute, uint32_t timebase)
-{
-    return beat16( beats_per_minute, timebase) >> 8;
-}
-
-/// beatsin88 generates a 16-bit sine wave at a given BPM,
-///           that oscillates within a given range.
-///           For this function, BPM MUST BE SPECIFIED as
-///           a Q8.8 fixed-point value; e.g. 120BPM must be
-///           specified as 120*256 = 30720.
-///           If you just want to specify "120", use beatsin16 or beatsin8.
-LIB8STATIC uint16_t beatsin88( accum88 beats_per_minute_88, uint16_t lowest, uint16_t highest, uint32_t timebase, uint16_t phase_offset)
-{
-    uint16_t beat = beat88( beats_per_minute_88, timebase);
-    uint16_t beatsin = (sin16( beat + phase_offset) + 32768);
-    uint16_t rangewidth = highest - lowest;
-    uint16_t scaledbeat = scale16( beatsin, rangewidth);
-    uint16_t result = lowest + scaledbeat;
-    return result;
-}
-
-/// beatsin16 generates a 16-bit sine wave at a given BPM,
-///           that oscillates within a given range.
-LIB8STATIC uint16_t beatsin16(accum88 beats_per_minute, uint16_t lowest, uint16_t highest, uint32_t timebase, uint16_t phase_offset)
-{
-    uint16_t beat = beat16( beats_per_minute, timebase);
-    uint16_t beatsin = (sin16( beat + phase_offset) + 32768);
-    uint16_t rangewidth = highest - lowest;
-    uint16_t scaledbeat = scale16( beatsin, rangewidth);
-    uint16_t result = lowest + scaledbeat;
-    return result;
-}
-
-/// beatsin8 generates an 8-bit sine wave at a given BPM,
-///           that oscillates within a given range.
-LIB8STATIC uint8_t beatsin8( accum88 beats_per_minute, uint8_t lowest, uint8_t highest, uint32_t timebase, uint8_t phase_offset)
-{
-    uint8_t beat = beat8( beats_per_minute, timebase);
-    uint8_t beatsin = sin8( beat + phase_offset);
-    uint8_t rangewidth = highest - lowest;
-    uint8_t scaledbeat = scale8( beatsin, rangewidth);
-    uint8_t result = lowest + scaledbeat;
-    return result;
-}
-
-
-/// Return the current seconds since boot in a 16-bit value.  Used as part of the
-/// "every N time-periods" mechanism
-LIB8STATIC uint16_t seconds16(void)
-{
-    uint32_t ms = GET_MILLIS();
-    uint16_t s16;
-    s16 = ms / 1000;
-    return s16;
-}
-
-/// Return the current minutes since boot in a 16-bit value.  Used as part of the
-/// "every N time-periods" mechanism
-LIB8STATIC uint16_t minutes16(void)
-{
-    uint32_t ms = GET_MILLIS();
-    uint16_t m16;
-    m16 = (ms / (60000L)) & 0xFFFF;
-    return m16;
-}
-
-/// Return the current hours since boot in an 8-bit value.  Used as part of the
-/// "every N time-periods" mechanism
-LIB8STATIC uint8_t hours8(void)
-{
-    uint32_t ms = GET_MILLIS();
-    uint8_t h8;
-    h8 = (ms / (3600000L)) & 0xFF;
-    return h8;
-}
-
-///@}
-
-#endif
diff --git a/lib/lib8tion/math8.h b/lib/lib8tion/math8.h
deleted file mode 100644
index 8c6b6c227e..0000000000
--- a/lib/lib8tion/math8.h
+++ /dev/null
@@ -1,552 +0,0 @@
-#ifndef __INC_LIB8TION_MATH_H
-#define __INC_LIB8TION_MATH_H
-
-#include "scale8.h"
-
-///@ingroup lib8tion
-
-///@defgroup Math Basic math operations
-/// Fast, efficient 8-bit math functions specifically
-/// designed for high-performance LED programming.
-///
-/// Because of the AVR(Arduino) and ARM assembly language
-/// implementations provided, using these functions often
-/// results in smaller and faster code than the equivalent
-/// program using plain "C" arithmetic and logic.
-///@{
-
-
-/// add one byte to another, saturating at 0xFF
-/// @param i - first byte to add
-/// @param j - second byte to add
-/// @returns the sum of i & j, capped at 0xFF
-LIB8STATIC_ALWAYS_INLINE uint8_t qadd8( uint8_t i, uint8_t j)
-{
-#if QADD8_C == 1
-    uint16_t t = i + j;
-    if (t > 255) t = 255;
-    return t;
-#elif QADD8_AVRASM == 1
-    asm volatile(
-         /* First, add j to i, conditioning the C flag */
-         "add %0, %1    \n\t"
-
-         /* Now test the C flag.
-           If C is clear, we branch around a load of 0xFF into i.
-           If C is set, we go ahead and load 0xFF into i.
-         */
-         "brcc L_%=     \n\t"
-         "ldi %0, 0xFF  \n\t"
-         "L_%=: "
-         : "+a" (i)
-         : "a"  (j) );
-    return i;
-#elif QADD8_ARM_DSP_ASM == 1
-    asm volatile( "uqadd8 %0, %0, %1" : "+r" (i) : "r" (j));
-    return i;
-#else
-#error "No implementation for qadd8 available."
-#endif
-}
-
-/// Add one byte to another, saturating at 0x7F
-/// @param i - first byte to add
-/// @param j - second byte to add
-/// @returns the sum of i & j, capped at 0xFF
-LIB8STATIC_ALWAYS_INLINE int8_t qadd7( int8_t i, int8_t j)
-{
-#if QADD7_C == 1
-    int16_t t = i + j;
-    if (t > 127) t = 127;
-    return t;
-#elif QADD7_AVRASM == 1
-    asm volatile(
-         /* First, add j to i, conditioning the V flag */
-         "add %0, %1    \n\t"
-
-         /* Now test the V flag.
-          If V is clear, we branch around a load of 0x7F into i.
-          If V is set, we go ahead and load 0x7F into i.
-          */
-         "brvc L_%=     \n\t"
-         "ldi %0, 0x7F  \n\t"
-         "L_%=: "
-         : "+a" (i)
-         : "a"  (j) );
-
-    return i;
-#elif QADD7_ARM_DSP_ASM == 1
-    asm volatile( "qadd8 %0, %0, %1" : "+r" (i) : "r" (j));
-    return i;
-#else
-#error "No implementation for qadd7 available."
-#endif
-}
-
-/// subtract one byte from another, saturating at 0x00
-/// @returns i - j with a floor of 0
-LIB8STATIC_ALWAYS_INLINE uint8_t qsub8( uint8_t i, uint8_t j)
-{
-#if QSUB8_C == 1
-    int16_t t = i - j;
-    if (t < 0) t = 0;
-    return t;
-#elif QSUB8_AVRASM == 1
-
-    asm volatile(
-         /* First, subtract j from i, conditioning the C flag */
-         "sub %0, %1    \n\t"
-
-         /* Now test the C flag.
-          If C is clear, we branch around a load of 0x00 into i.
-          If C is set, we go ahead and load 0x00 into i.
-          */
-         "brcc L_%=     \n\t"
-         "ldi %0, 0x00  \n\t"
-         "L_%=: "
-         : "+a" (i)
-         : "a"  (j) );
-
-    return i;
-#else
-#error "No implementation for qsub8 available."
-#endif
-}
-
-/// add one byte to another, with one byte result
-LIB8STATIC_ALWAYS_INLINE uint8_t add8( uint8_t i, uint8_t j)
-{
-#if ADD8_C == 1
-    uint16_t t = i + j;
-    return t;
-#elif ADD8_AVRASM == 1
-    // Add j to i, period.
-    asm volatile( "add %0, %1" : "+a" (i) : "a" (j));
-    return i;
-#else
-#error "No implementation for add8 available."
-#endif
-}
-
-/// add one byte to another, with one byte result
-LIB8STATIC_ALWAYS_INLINE uint16_t add8to16( uint8_t i, uint16_t j)
-{
-#if ADD8_C == 1
-    uint16_t t = i + j;
-    return t;
-#elif ADD8_AVRASM == 1
-    // Add i(one byte) to j(two bytes)
-    asm volatile( "add %A[j], %[i]              \n\t"
-                  "adc %B[j], __zero_reg__      \n\t"
-                 : [j] "+a" (j)
-                 : [i] "a"  (i)
-                 );
-    return i;
-#else
-#error "No implementation for add8to16 available."
-#endif
-}
-
-
-/// subtract one byte from another, 8-bit result
-LIB8STATIC_ALWAYS_INLINE uint8_t sub8( uint8_t i, uint8_t j)
-{
-#if SUB8_C == 1
-    int16_t t = i - j;
-    return t;
-#elif SUB8_AVRASM == 1
-    // Subtract j from i, period.
-    asm volatile( "sub %0, %1" : "+a" (i) : "a" (j));
-    return i;
-#else
-#error "No implementation for sub8 available."
-#endif
-}
-
-/// Calculate an integer average of two unsigned
-///       8-bit integer values (uint8_t).
-///       Fractional results are rounded down, e.g. avg8(20,41) = 30
-LIB8STATIC_ALWAYS_INLINE uint8_t avg8( uint8_t i, uint8_t j)
-{
-#if AVG8_C == 1
-    return (i + j) >> 1;
-#elif AVG8_AVRASM == 1
-    asm volatile(
-         /* First, add j to i, 9th bit overflows into C flag */
-         "add %0, %1    \n\t"
-         /* Divide by two, moving C flag into high 8th bit */
-         "ror %0        \n\t"
-         : "+a" (i)
-         : "a"  (j) );
-    return i;
-#else
-#error "No implementation for avg8 available."
-#endif
-}
-
-/// Calculate an integer average of two unsigned
-///       16-bit integer values (uint16_t).
-///       Fractional results are rounded down, e.g. avg16(20,41) = 30
-LIB8STATIC_ALWAYS_INLINE uint16_t avg16( uint16_t i, uint16_t j)
-{
-#if AVG16_C == 1
-    return (uint32_t)((uint32_t)(i) + (uint32_t)(j)) >> 1;
-#elif AVG16_AVRASM == 1
-    asm volatile(
-                 /* First, add jLo (heh) to iLo, 9th bit overflows into C flag */
-                 "add %A[i], %A[j]    \n\t"
-                 /* Now, add C + jHi to iHi, 17th bit overflows into C flag */
-                 "adc %B[i], %B[j]    \n\t"
-                 /* Divide iHi by two, moving C flag into high 16th bit, old 9th bit now in C */
-                 "ror %B[i]        \n\t"
-                 /* Divide iLo by two, moving C flag into high 8th bit */
-                 "ror %A[i]        \n\t"
-                 : [i] "+a" (i)
-                 : [j] "a"  (j) );
-    return i;
-#else
-#error "No implementation for avg16 available."
-#endif
-}
-
-
-/// Calculate an integer average of two signed 7-bit
-///       integers (int8_t)
-///       If the first argument is even, result is rounded down.
-///       If the first argument is odd, result is result up.
-LIB8STATIC_ALWAYS_INLINE int8_t avg7( int8_t i, int8_t j)
-{
-#if AVG7_C == 1
-    return ((i + j) >> 1) + (i & 0x1);
-#elif AVG7_AVRASM == 1
-    asm volatile(
-                 "asr %1        \n\t"
-                 "asr %0        \n\t"
-                 "adc %0, %1    \n\t"
-                 : "+a" (i)
-                 : "a"  (j) );
-    return i;
-#else
-#error "No implementation for avg7 available."
-#endif
-}
-
-/// Calculate an integer average of two signed 15-bit
-///       integers (int16_t)
-///       If the first argument is even, result is rounded down.
-///       If the first argument is odd, result is result up.
-LIB8STATIC_ALWAYS_INLINE int16_t avg15( int16_t i, int16_t j)
-{
-#if AVG15_C == 1
-    return ((int32_t)((int32_t)(i) + (int32_t)(j)) >> 1) + (i & 0x1);
-#elif AVG15_AVRASM == 1
-    asm volatile(
-                 /* first divide j by 2, throwing away lowest bit */
-                 "asr %B[j]          \n\t"
-                 "ror %A[j]          \n\t"
-                 /* now divide i by 2, with lowest bit going into C */
-                 "asr %B[i]          \n\t"
-                 "ror %A[i]          \n\t"
-                 /* add j + C to i */
-                 "adc %A[i], %A[j]   \n\t"
-                 "adc %B[i], %B[j]   \n\t"
-                 : [i] "+a" (i)
-                 : [j] "a"  (j) );
-    return i;
-#else
-#error "No implementation for avg15 available."
-#endif
-}
-
-
-///       Calculate the remainder of one unsigned 8-bit
-///       value divided by anoter, aka A % M.
-///       Implemented by repeated subtraction, which is
-///       very compact, and very fast if A is 'probably'
-///       less than M.  If A is a large multiple of M,
-///       the loop has to execute multiple times.  However,
-///       even in that case, the loop is only two
-///       instructions long on AVR, i.e., quick.
-LIB8STATIC_ALWAYS_INLINE uint8_t mod8( uint8_t a, uint8_t m)
-{
-#if defined(__AVR__)
-    asm volatile (
-                  "L_%=:  sub %[a],%[m]    \n\t"
-                  "       brcc L_%=        \n\t"
-                  "       add %[a],%[m]    \n\t"
-                  : [a] "+r" (a)
-                  : [m] "r"  (m)
-                  );
-#else
-    while( a >= m) a -= m;
-#endif
-    return a;
-}
-
-///          Add two numbers, and calculate the modulo
-///          of the sum and a third number, M.
-///          In other words, it returns (A+B) % M.
-///          It is designed as a compact mechanism for
-///          incrementing a 'mode' switch and wrapping
-///          around back to 'mode 0' when the switch
-///          goes past the end of the available range.
-///          e.g. if you have seven modes, this switches
-///          to the next one and wraps around if needed:
-///            mode = addmod8( mode, 1, 7);
-///LIB8STATIC_ALWAYS_INLINESee 'mod8' for notes on performance.
-LIB8STATIC uint8_t addmod8( uint8_t a, uint8_t b, uint8_t m)
-{
-#if defined(__AVR__)
-    asm volatile (
-                  "       add %[a],%[b]    \n\t"
-                  "L_%=:  sub %[a],%[m]    \n\t"
-                  "       brcc L_%=        \n\t"
-                  "       add %[a],%[m]    \n\t"
-                  : [a] "+r" (a)
-                  : [b] "r"  (b), [m] "r" (m)
-                  );
-#else
-    a += b;
-    while( a >= m) a -= m;
-#endif
-    return a;
-}
-
-///          Subtract two numbers, and calculate the modulo
-///          of the difference and a third number, M.
-///          In other words, it returns (A-B) % M.
-///          It is designed as a compact mechanism for
-///          incrementing a 'mode' switch and wrapping
-///          around back to 'mode 0' when the switch
-///          goes past the end of the available range.
-///          e.g. if you have seven modes, this switches
-///          to the next one and wraps around if needed:
-///            mode = addmod8( mode, 1, 7);
-///LIB8STATIC_ALWAYS_INLINESee 'mod8' for notes on performance.
-LIB8STATIC uint8_t submod8( uint8_t a, uint8_t b, uint8_t m)
-{
-#if defined(__AVR__)
-    asm volatile (
-                  "       sub %[a],%[b]    \n\t"
-                  "L_%=:  sub %[a],%[m]    \n\t"
-                  "       brcc L_%=        \n\t"
-                  "       add %[a],%[m]    \n\t"
-                  : [a] "+r" (a)
-                  : [b] "r"  (b), [m] "r" (m)
-                  );
-#else
-    a -= b;
-    while( a >= m) a -= m;
-#endif
-    return a;
-}
-
-/// 8x8 bit multiplication, with 8 bit result
-LIB8STATIC_ALWAYS_INLINE uint8_t mul8( uint8_t i, uint8_t j)
-{
-#if MUL8_C == 1
-    return ((uint16_t)i * (uint16_t)(j) ) & 0xFF;
-#elif MUL8_AVRASM == 1
-    asm volatile(
-         /* Multiply 8-bit i * 8-bit j, giving 16-bit r1,r0 */
-         "mul %0, %1          \n\t"
-         /* Extract the LOW 8-bits (r0) */
-         "mov %0, r0          \n\t"
-         /* Restore r1 to "0"; it's expected to always be that */
-         "clr __zero_reg__    \n\t"
-         : "+a" (i)
-         : "a"  (j)
-         : "r0", "r1");
-
-    return i;
-#else
-#error "No implementation for mul8 available."
-#endif
-}
-
-
-/// saturating 8x8 bit multiplication, with 8 bit result
-/// @returns the product of i * j, capping at 0xFF
-LIB8STATIC_ALWAYS_INLINE uint8_t qmul8( uint8_t i, uint8_t j)
-{
-#if QMUL8_C == 1
-    int p = ((uint16_t)i * (uint16_t)(j) );
-    if( p > 255) p = 255;
-    return p;
-#elif QMUL8_AVRASM == 1
-    asm volatile(
-                 /* Multiply 8-bit i * 8-bit j, giving 16-bit r1,r0 */
-                 "  mul %0, %1          \n\t"
-                 /* If high byte of result is zero, all is well. */
-                 "  tst r1              \n\t"
-                 "  breq Lnospill_%=    \n\t"
-                 /* If high byte of result > 0, saturate low byte to 0xFF */
-                 "  ldi %0,0xFF         \n\t"
-                 "  rjmp Ldone_%=       \n\t"
-                 "Lnospill_%=:          \n\t"
-                 /* Extract the LOW 8-bits (r0) */
-                 "  mov %0, r0          \n\t"
-                 "Ldone_%=:             \n\t"
-                 /* Restore r1 to "0"; it's expected to always be that */
-                 "  clr __zero_reg__    \n\t"
-                 : "+a" (i)
-                 : "a"  (j)
-                 : "r0", "r1");
-
-    return i;
-#else
-#error "No implementation for qmul8 available."
-#endif
-}
-
-
-/// take abs() of a signed 8-bit uint8_t
-LIB8STATIC_ALWAYS_INLINE int8_t abs8( int8_t i)
-{
-#if ABS8_C == 1
-    if( i < 0) i = -i;
-    return i;
-#elif ABS8_AVRASM == 1
-
-
-    asm volatile(
-         /* First, check the high bit, and prepare to skip if it's clear */
-         "sbrc %0, 7 \n"
-
-         /* Negate the value */
-         "neg %0     \n"
-
-         : "+r" (i) : "r" (i) );
-    return i;
-#else
-#error "No implementation for abs8 available."
-#endif
-}
-
-///         square root for 16-bit integers
-///         About three times faster and five times smaller
-///         than Arduino's general sqrt on AVR.
-LIB8STATIC uint8_t sqrt16(uint16_t x)
-{
-    if( x <= 1) {
-        return x;
-    }
-
-    uint8_t low = 1; // lower bound
-    uint8_t hi, mid;
-
-    if( x > 7904) {
-        hi = 255;
-    } else {
-        hi = (x >> 5) + 8; // initial estimate for upper bound
-    }
-
-    do {
-        mid = (low + hi) >> 1;
-        if ((uint16_t)(mid * mid) > x) {
-            hi = mid - 1;
-        } else {
-            if( mid == 255) {
-                return 255;
-            }
-            low = mid + 1;
-        }
-    } while (hi >= low);
-
-    return low - 1;
-}
-
-/// blend a variable proproportion(0-255) of one byte to another
-/// @param a - the starting byte value
-/// @param b - the byte value to blend toward
-/// @param amountOfB - the proportion (0-255) of b to blend
-/// @returns a byte value between a and b, inclusive
-#if (FASTLED_BLEND_FIXED == 1)
-LIB8STATIC uint8_t blend8( uint8_t a, uint8_t b, uint8_t amountOfB)
-{
-#if BLEND8_C == 1
-    uint16_t partial;
-    uint8_t result;
-
-    uint8_t amountOfA = 255 - amountOfB;
-
-    partial = (a * amountOfA);
-#if (FASTLED_SCALE8_FIXED == 1)
-    partial += a;
-    //partial = add8to16( a, partial);
-#endif
-
-    partial += (b * amountOfB);
-#if (FASTLED_SCALE8_FIXED == 1)
-    partial += b;
-    //partial = add8to16( b, partial);
-#endif
-
-    result = partial >> 8;
-
-    return result;
-
-#elif BLEND8_AVRASM == 1
-    uint16_t partial;
-    uint8_t result;
-
-    asm volatile (
-        /* partial = b * amountOfB */
-        "  mul %[b], %[amountOfB]        \n\t"
-        "  movw %A[partial], r0          \n\t"
-
-        /* amountOfB (aka amountOfA) = 255 - amountOfB */
-        "  com %[amountOfB]              \n\t"
-
-        /* partial += a * amountOfB (aka amountOfA) */
-        "  mul %[a], %[amountOfB]        \n\t"
-
-        "  add %A[partial], r0           \n\t"
-        "  adc %B[partial], r1           \n\t"
-
-        "  clr __zero_reg__              \n\t"
-
-#if (FASTLED_SCALE8_FIXED == 1)
-        /* partial += a */
-        "  add %A[partial], %[a]         \n\t"
-        "  adc %B[partial], __zero_reg__ \n\t"
-
-        // partial += b
-        "  add %A[partial], %[b]         \n\t"
-        "  adc %B[partial], __zero_reg__ \n\t"
-#endif
-
-        : [partial] "=r" (partial),
-          [amountOfB] "+a" (amountOfB)
-        : [a] "a" (a),
-          [b] "a" (b)
-        : "r0", "r1"
-    );
-
-    result = partial >> 8;
-
-    return result;
-
-#else
-#error "No implementation for blend8 available."
-#endif
-}
-
-#else
-LIB8STATIC uint8_t blend8( uint8_t a, uint8_t b, uint8_t amountOfB)
-{
-    // This version loses precision in the integer math
-    // and can actually return results outside of the range
-    // from a to b.  Its use is not recommended.
-    uint8_t result;
-    uint8_t amountOfA = 255 - amountOfB;
-    result = scale8_LEAVING_R1_DIRTY( a, amountOfA)
-           + scale8_LEAVING_R1_DIRTY( b, amountOfB);
-    cleanup_R1();
-    return result;
-}
-#endif
-
-
-///@}
-#endif
diff --git a/lib/lib8tion/random8.h b/lib/lib8tion/random8.h
deleted file mode 100644
index 7ee67cbb36..0000000000
--- a/lib/lib8tion/random8.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef __INC_LIB8TION_RANDOM_H
-#define __INC_LIB8TION_RANDOM_H
-///@ingroup lib8tion
-
-///@defgroup Random Fast random number generators
-/// Fast 8- and 16- bit unsigned random numbers.
-///  Significantly faster than Arduino random(), but
-///  also somewhat less random.  You can add entropy.
-///@{
-
-// X(n+1) = (2053 * X(n)) + 13849)
-#define FASTLED_RAND16_2053  ((uint16_t)(2053))
-#define FASTLED_RAND16_13849 ((uint16_t)(13849))
-
-/// random number seed
-extern uint16_t rand16seed;// = RAND16_SEED;
-
-/// Generate an 8-bit random number
-LIB8STATIC uint8_t random8(void)
-{
-    rand16seed = (rand16seed * FASTLED_RAND16_2053) + FASTLED_RAND16_13849;
-    // return the sum of the high and low bytes, for better
-    //  mixing and non-sequential correlation
-    return (uint8_t)(((uint8_t)(rand16seed & 0xFF)) +
-                     ((uint8_t)(rand16seed >> 8)));
-}
-
-/// Generate a 16 bit random number
-LIB8STATIC uint16_t random16(void)
-{
-    rand16seed = (rand16seed * FASTLED_RAND16_2053) + FASTLED_RAND16_13849;
-    return rand16seed;
-}
-
-/// Generate an 8-bit random number between 0 and lim
-/// @param lim the upper bound for the result
-LIB8STATIC uint8_t random8_max(uint8_t lim)
-{
-    uint8_t r = random8();
-    r = (r*lim) >> 8;
-    return r;
-}
-
-/// Generate an 8-bit random number in the given range
-/// @param min the lower bound for the random number
-/// @param lim the upper bound for the random number
-LIB8STATIC uint8_t random8_min_max(uint8_t min, uint8_t lim)
-{
-    uint8_t delta = lim - min;
-    uint8_t r = random8_max(delta) + min;
-    return r;
-}
-
-/// Generate an 16-bit random number between 0 and lim
-/// @param lim the upper bound for the result
-LIB8STATIC uint16_t random16_max(uint16_t lim)
-{
-    uint16_t r = random16();
-    uint32_t p = (uint32_t)lim * (uint32_t)r;
-    r = p >> 16;
-    return r;
-}
-
-/// Generate an 16-bit random number in the given range
-/// @param min the lower bound for the random number
-/// @param lim the upper bound for the random number
-LIB8STATIC uint16_t random16_min_max( uint16_t min, uint16_t lim)
-{
-    uint16_t delta = lim - min;
-    uint16_t r = random16_max(delta) + min;
-    return r;
-}
-
-/// Set the 16-bit seed used for the random number generator
-LIB8STATIC void random16_set_seed(uint16_t seed)
-{
-    rand16seed = seed;
-}
-
-/// Get the current seed value for the random number generator
-LIB8STATIC uint16_t random16_get_seed(void)
-{
-    return rand16seed;
-}
-
-/// Add entropy into the random number generator
-LIB8STATIC void random16_add_entropy(uint16_t entropy)
-{
-    rand16seed += entropy;
-}
-
-///@}
-
-#endif
diff --git a/lib/lib8tion/scale8.h b/lib/lib8tion/scale8.h
deleted file mode 100644
index 9895fd4d79..0000000000
--- a/lib/lib8tion/scale8.h
+++ /dev/null
@@ -1,542 +0,0 @@
-#ifndef __INC_LIB8TION_SCALE_H
-#define __INC_LIB8TION_SCALE_H
-
-///@ingroup lib8tion
-
-///@defgroup Scaling Scaling functions
-/// Fast, efficient 8-bit scaling functions specifically
-/// designed for high-performance LED programming.
-///
-/// Because of the AVR(Arduino) and ARM assembly language
-/// implementations provided, using these functions often
-/// results in smaller and faster code than the equivalent
-/// program using plain "C" arithmetic and logic.
-///@{
-
-///  scale one byte by a second one, which is treated as
-///  the numerator of a fraction whose denominator is 256
-///  In other words, it computes i * (scale / 256)
-///  4 clocks AVR with MUL, 2 clocks ARM
-LIB8STATIC_ALWAYS_INLINE uint8_t scale8( uint8_t i, fract8 scale)
-{
-#if SCALE8_C == 1
-#if (FASTLED_SCALE8_FIXED == 1)
-    return (((uint16_t)i) * (1+(uint16_t)(scale))) >> 8;
-#else
-    return ((uint16_t)i * (uint16_t)(scale) ) >> 8;
-#endif
-#elif SCALE8_AVRASM == 1
-#if defined(LIB8_ATTINY)
-#if (FASTLED_SCALE8_FIXED == 1)
-    uint8_t work=i;
-#else
-    uint8_t work=0;
-#endif
-    uint8_t cnt=0x80;
-    asm volatile(
-#if (FASTLED_SCALE8_FIXED == 1)
-        "  inc %[scale]                 \n\t"
-        "  breq DONE_%=                 \n\t"
-        "  clr %[work]                  \n\t"
-#endif
-        "LOOP_%=:                       \n\t"
-        /*"  sbrc %[scale], 0             \n\t"
-        "  add %[work], %[i]            \n\t"
-        "  ror %[work]                  \n\t"
-        "  lsr %[scale]                 \n\t"
-        "  clc                          \n\t"*/
-        "  sbrc %[scale], 0             \n\t"
-        "  add %[work], %[i]            \n\t"
-        "  ror %[work]                  \n\t"
-        "  lsr %[scale]                 \n\t"
-        "  lsr %[cnt]                   \n\t"
-        "brcc LOOP_%=                   \n\t"
-        "DONE_%=:                       \n\t"
-        : [work] "+r" (work), [cnt] "+r" (cnt)
-        : [scale] "r" (scale), [i] "r" (i)
-        :
-      );
-    return work;
-#else
-    asm volatile(
-#if (FASTLED_SCALE8_FIXED==1)
-        // Multiply 8-bit i * 8-bit scale, giving 16-bit r1,r0
-        "mul %0, %1          \n\t"
-        // Add i to r0, possibly setting the carry flag
-        "add r0, %0         \n\t"
-        // load the immediate 0 into i (note, this does _not_ touch any flags)
-        "ldi %0, 0x00       \n\t"
-        // walk and chew gum at the same time
-        "adc %0, r1          \n\t"
-#else
-         /* Multiply 8-bit i * 8-bit scale, giving 16-bit r1,r0 */
-         "mul %0, %1          \n\t"
-         /* Move the high 8-bits of the product (r1) back to i */
-         "mov %0, r1          \n\t"
-         /* Restore r1 to "0"; it's expected to always be that */
-#endif
-         "clr __zero_reg__    \n\t"
-
-         : "+a" (i)      /* writes to i */
-         : "a"  (scale)  /* uses scale */
-         : "r0", "r1"    /* clobbers r0, r1 */ );
-
-    /* Return the result */
-    return i;
-#endif
-#else
-#error "No implementation for scale8 available."
-#endif
-}
-
-
-///  The "video" version of scale8 guarantees that the output will
-///  be only be zero if one or both of the inputs are zero.  If both
-///  inputs are non-zero, the output is guaranteed to be non-zero.
-///  This makes for better 'video'/LED dimming, at the cost of
-///  several additional cycles.
-LIB8STATIC_ALWAYS_INLINE uint8_t scale8_video( uint8_t i, fract8 scale)
-{
-#if SCALE8_C == 1 || defined(LIB8_ATTINY)
-    uint8_t j = (((int)i * (int)scale) >> 8) + ((i&&scale)?1:0);
-    // uint8_t nonzeroscale = (scale != 0) ? 1 : 0;
-    // uint8_t j = (i == 0) ? 0 : (((int)i * (int)(scale) ) >> 8) + nonzeroscale;
-    return j;
-#elif SCALE8_AVRASM == 1
-    uint8_t j=0;
-    asm volatile(
-        "  tst %[i]\n\t"
-        "  breq L_%=\n\t"
-        "  mul %[i], %[scale]\n\t"
-        "  mov %[j], r1\n\t"
-        "  clr __zero_reg__\n\t"
-        "  cpse %[scale], r1\n\t"
-        "  subi %[j], 0xFF\n\t"
-        "L_%=: \n\t"
-        : [j] "+a" (j)
-        : [i] "a" (i), [scale] "a" (scale)
-        : "r0", "r1");
-
-    return j;
-    // uint8_t nonzeroscale = (scale != 0) ? 1 : 0;
-    // asm volatile(
-    //      "      tst %0           \n"
-    //      "      breq L_%=        \n"
-    //      "      mul %0, %1       \n"
-    //      "      mov %0, r1       \n"
-    //      "      add %0, %2       \n"
-    //      "      clr __zero_reg__ \n"
-    //      "L_%=:                  \n"
-
-    //      : "+a" (i)
-    //      : "a" (scale), "a" (nonzeroscale)
-    //      : "r0", "r1");
-
-    // // Return the result
-    // return i;
-#else
-#error "No implementation for scale8_video available."
-#endif
-}
-
-
-/// This version of scale8 does not clean up the R1 register on AVR
-/// If you are doing several 'scale8's in a row, use this, and
-/// then explicitly call cleanup_R1.
-LIB8STATIC_ALWAYS_INLINE uint8_t scale8_LEAVING_R1_DIRTY( uint8_t i, fract8 scale)
-{
-#if SCALE8_C == 1
-#if (FASTLED_SCALE8_FIXED == 1)
-    return (((uint16_t)i) * ((uint16_t)(scale)+1)) >> 8;
-#else
-    return ((int)i * (int)(scale) ) >> 8;
-#endif
-#elif SCALE8_AVRASM == 1
-    asm volatile(
-      #if (FASTLED_SCALE8_FIXED==1)
-              // Multiply 8-bit i * 8-bit scale, giving 16-bit r1,r0
-              "mul %0, %1          \n\t"
-              // Add i to r0, possibly setting the carry flag
-              "add r0, %0         \n\t"
-              // load the immediate 0 into i (note, this does _not_ touch any flags)
-              "ldi %0, 0x00       \n\t"
-              // walk and chew gum at the same time
-              "adc %0, r1          \n\t"
-      #else
-         /* Multiply 8-bit i * 8-bit scale, giving 16-bit r1,r0 */
-         "mul %0, %1    \n\t"
-         /* Move the high 8-bits of the product (r1) back to i */
-         "mov %0, r1    \n\t"
-      #endif
-         /* R1 IS LEFT DIRTY HERE; YOU MUST ZERO IT OUT YOURSELF  */
-         /* "clr __zero_reg__    \n\t" */
-
-         : "+a" (i)      /* writes to i */
-         : "a"  (scale)  /* uses scale */
-         : "r0", "r1"    /* clobbers r0, r1 */ );
-
-    // Return the result
-    return i;
-#else
-#error "No implementation for scale8_LEAVING_R1_DIRTY available."
-#endif
-}
-
-
-/// This version of scale8_video does not clean up the R1 register on AVR
-/// If you are doing several 'scale8_video's in a row, use this, and
-/// then explicitly call cleanup_R1.
-LIB8STATIC_ALWAYS_INLINE uint8_t scale8_video_LEAVING_R1_DIRTY( uint8_t i, fract8 scale)
-{
-#if SCALE8_C == 1 || defined(LIB8_ATTINY)
-    uint8_t j = (((int)i * (int)scale) >> 8) + ((i&&scale)?1:0);
-    // uint8_t nonzeroscale = (scale != 0) ? 1 : 0;
-    // uint8_t j = (i == 0) ? 0 : (((int)i * (int)(scale) ) >> 8) + nonzeroscale;
-    return j;
-#elif SCALE8_AVRASM == 1
-    uint8_t j=0;
-    asm volatile(
-        "  tst %[i]\n\t"
-        "  breq L_%=\n\t"
-        "  mul %[i], %[scale]\n\t"
-        "  mov %[j], r1\n\t"
-        "  breq L_%=\n\t"
-        "  subi %[j], 0xFF\n\t"
-        "L_%=: \n\t"
-        : [j] "+a" (j)
-        : [i] "a" (i), [scale] "a" (scale)
-        : "r0", "r1");
-
-    return j;
-    // uint8_t nonzeroscale = (scale != 0) ? 1 : 0;
-    // asm volatile(
-    //      "      tst %0           \n"
-    //      "      breq L_%=        \n"
-    //      "      mul %0, %1       \n"
-    //      "      mov %0, r1       \n"
-    //      "      add %0, %2       \n"
-    //      "      clr __zero_reg__ \n"
-    //      "L_%=:                  \n"
-
-    //      : "+a" (i)
-    //      : "a" (scale), "a" (nonzeroscale)
-    //      : "r0", "r1");
-
-    // // Return the result
-    // return i;
-#else
-#error "No implementation for scale8_video_LEAVING_R1_DIRTY available."
-#endif
-}
-
-/// Clean up the r1 register after a series of *LEAVING_R1_DIRTY calls
-LIB8STATIC_ALWAYS_INLINE void cleanup_R1(void)
-{
-#if CLEANUP_R1_AVRASM == 1
-    // Restore r1 to "0"; it's expected to always be that
-    asm volatile( "clr __zero_reg__  \n\t" : : : "r1" );
-#endif
-}
-
-
-/// scale a 16-bit unsigned value by an 8-bit value,
-///         considered as numerator of a fraction whose denominator
-///         is 256. In other words, it computes i * (scale / 256)
-
-LIB8STATIC_ALWAYS_INLINE uint16_t scale16by8( uint16_t i, fract8 scale )
-{
-#if SCALE16BY8_C == 1
-    uint16_t result;
-#if FASTLED_SCALE8_FIXED == 1
-    result = (i * (1+((uint16_t)scale))) >> 8;
-#else
-    result = (i * scale) / 256;
-#endif
-    return result;
-#elif SCALE16BY8_AVRASM == 1
-#if FASTLED_SCALE8_FIXED == 1
-    uint16_t result = 0;
-    asm volatile(
-                 // result.A = HighByte( (i.A x scale) + i.A )
-                 "  mul %A[i], %[scale]                 \n\t"
-                 "  add r0, %A[i]                       \n\t"
-            //   "  adc r1, [zero]                      \n\t"
-            //   "  mov %A[result], r1                  \n\t"
-                 "  adc %A[result], r1                  \n\t"
-
-                 // result.A-B += i.B x scale
-                 "  mul %B[i], %[scale]                 \n\t"
-                 "  add %A[result], r0                  \n\t"
-                 "  adc %B[result], r1                  \n\t"
-
-                 // cleanup r1
-                 "  clr __zero_reg__                    \n\t"
-
-                 // result.A-B += i.B
-                 "  add %A[result], %B[i]               \n\t"
-                 "  adc %B[result], __zero_reg__        \n\t"
-
-                 : [result] "+r" (result)
-                 : [i] "r" (i), [scale] "r" (scale)
-                 : "r0", "r1"
-                 );
-    return result;
-#else
-    uint16_t result = 0;
-    asm volatile(
-         // result.A = HighByte(i.A x j )
-         "  mul %A[i], %[scale]                 \n\t"
-         "  mov %A[result], r1                  \n\t"
-         //"  clr %B[result]                      \n\t"
-
-         // result.A-B += i.B x j
-         "  mul %B[i], %[scale]                 \n\t"
-         "  add %A[result], r0                  \n\t"
-         "  adc %B[result], r1                  \n\t"
-
-         // cleanup r1
-         "  clr __zero_reg__                    \n\t"
-
-         : [result] "+r" (result)
-         : [i] "r" (i), [scale] "r" (scale)
-         : "r0", "r1"
-         );
-    return result;
-#endif
-#else
-    #error "No implementation for scale16by8 available."
-#endif
-}
-
-/// scale a 16-bit unsigned value by a 16-bit value,
-///         considered as numerator of a fraction whose denominator
-///         is 65536. In other words, it computes i * (scale / 65536)
-
-LIB8STATIC uint16_t scale16( uint16_t i, fract16 scale )
-{
-  #if SCALE16_C == 1
-    uint16_t result;
-#if FASTLED_SCALE8_FIXED == 1
-    result = ((uint32_t)(i) * (1+(uint32_t)(scale))) / 65536;
-#else
-    result = ((uint32_t)(i) * (uint32_t)(scale)) / 65536;
-#endif
-    return result;
-#elif SCALE16_AVRASM == 1
-#if FASTLED_SCALE8_FIXED == 1
-    // implemented sort of like
-    //   result = ((i * scale) + i ) / 65536
-    //
-    // why not like this, you may ask?
-    //   result = (i * (scale+1)) / 65536
-    // the answer is that if scale is 65535, then scale+1
-    // will be zero, which is not what we want.
-    uint32_t result;
-    asm volatile(
-                 // result.A-B  = i.A x scale.A
-                 "  mul %A[i], %A[scale]                 \n\t"
-                 //  save results...
-                 // basic idea:
-                 //"  mov %A[result], r0                 \n\t"
-                 //"  mov %B[result], r1                 \n\t"
-                 // which can be written as...
-                 "  movw %A[result], r0                   \n\t"
-                 // Because we're going to add i.A-B to
-                 // result.A-D, we DO need to keep both
-                 // the r0 and r1 portions of the product
-                 // UNlike in the 'unfixed scale8' version.
-                 // So the movw here is needed.
-                 : [result] "=r" (result)
-                 : [i] "r" (i),
-                 [scale] "r" (scale)
-                 : "r0", "r1"
-                 );
-
-    asm volatile(
-                 // result.C-D  = i.B x scale.B
-                 "  mul %B[i], %B[scale]                 \n\t"
-                 //"  mov %C[result], r0                 \n\t"
-                 //"  mov %D[result], r1                 \n\t"
-                 "  movw %C[result], r0                   \n\t"
-                 : [result] "+r" (result)
-                 : [i] "r" (i),
-                 [scale] "r" (scale)
-                 : "r0", "r1"
-                 );
-
-    const uint8_t  zero = 0;
-    asm volatile(
-                 // result.B-D += i.B x scale.A
-                 "  mul %B[i], %A[scale]                 \n\t"
-
-                 "  add %B[result], r0                   \n\t"
-                 "  adc %C[result], r1                   \n\t"
-                 "  adc %D[result], %[zero]              \n\t"
-
-                 // result.B-D += i.A x scale.B
-                 "  mul %A[i], %B[scale]                 \n\t"
-
-                 "  add %B[result], r0                   \n\t"
-                 "  adc %C[result], r1                   \n\t"
-                 "  adc %D[result], %[zero]              \n\t"
-
-                 // cleanup r1
-                 "  clr r1                               \n\t"
-
-                 : [result] "+r" (result)
-                 : [i] "r" (i),
-                 [scale] "r" (scale),
-                 [zero] "r" (zero)
-                 : "r0", "r1"
-                 );
-
-    asm volatile(
-                 // result.A-D += i.A-B
-                 "  add %A[result], %A[i]                \n\t"
-                 "  adc %B[result], %B[i]                \n\t"
-                 "  adc %C[result], %[zero]              \n\t"
-                 "  adc %D[result], %[zero]              \n\t"
-                 : [result] "+r" (result)
-                 : [i] "r" (i),
-                 [zero] "r" (zero)
-                 );
-
-    result = result >> 16;
-    return result;
-#else
-    uint32_t result;
-    asm volatile(
-                 // result.A-B  = i.A x scale.A
-                 "  mul %A[i], %A[scale]                 \n\t"
-                 //  save results...
-                 // basic idea:
-                 //"  mov %A[result], r0                 \n\t"
-                 //"  mov %B[result], r1                 \n\t"
-                 // which can be written as...
-                 "  movw %A[result], r0                   \n\t"
-                 // We actually don't need to do anything with r0,
-                 // as result.A is never used again here, so we
-                 // could just move the high byte, but movw is
-                 // one clock cycle, just like mov, so might as
-                 // well, in case we want to use this code for
-                 // a generic 16x16 multiply somewhere.
-
-                 : [result] "=r" (result)
-                 : [i] "r" (i),
-                   [scale] "r" (scale)
-                 : "r0", "r1"
-                 );
-
-    asm volatile(
-                 // result.C-D  = i.B x scale.B
-                 "  mul %B[i], %B[scale]                 \n\t"
-                 //"  mov %C[result], r0                 \n\t"
-                 //"  mov %D[result], r1                 \n\t"
-                 "  movw %C[result], r0                   \n\t"
-                 : [result] "+r" (result)
-                 : [i] "r" (i),
-                   [scale] "r" (scale)
-                 : "r0", "r1"
-                 );
-
-    const uint8_t  zero = 0;
-    asm volatile(
-                 // result.B-D += i.B x scale.A
-                 "  mul %B[i], %A[scale]                 \n\t"
-
-                 "  add %B[result], r0                   \n\t"
-                 "  adc %C[result], r1                   \n\t"
-                 "  adc %D[result], %[zero]              \n\t"
-
-                 // result.B-D += i.A x scale.B
-                 "  mul %A[i], %B[scale]                 \n\t"
-
-                 "  add %B[result], r0                   \n\t"
-                 "  adc %C[result], r1                   \n\t"
-                 "  adc %D[result], %[zero]              \n\t"
-
-                 // cleanup r1
-                 "  clr r1                               \n\t"
-
-                 : [result] "+r" (result)
-                 : [i] "r" (i),
-                   [scale] "r" (scale),
-                   [zero] "r" (zero)
-                 : "r0", "r1"
-                 );
-
-    result = result >> 16;
-    return result;
-#endif
-#else
-    #error "No implementation for scale16 available."
-#endif
-}
-///@}
-
-///@defgroup Dimming Dimming and brightening functions
-///
-/// Dimming and brightening functions
-///
-/// The eye does not respond in a linear way to light.
-/// High speed PWM'd LEDs at 50% duty cycle appear far
-/// brighter then the 'half as bright' you might expect.
-///
-/// If you want your midpoint brightness leve (128) to
-/// appear half as bright as 'full' brightness (255), you
-/// have to apply a 'dimming function'.
-///@{
-
-/// Adjust a scaling value for dimming
-LIB8STATIC uint8_t dim8_raw( uint8_t x)
-{
-    return scale8( x, x);
-}
-
-/// Adjust a scaling value for dimming for video (value will never go below 1)
-LIB8STATIC uint8_t dim8_video( uint8_t x)
-{
-    return scale8_video( x, x);
-}
-
-/// Linear version of the dimming function that halves for values < 128
-LIB8STATIC uint8_t dim8_lin( uint8_t x )
-{
-    if( x & 0x80 ) {
-        x = scale8( x, x);
-    } else {
-        x += 1;
-        x /= 2;
-    }
-    return x;
-}
-
-/// inverse of the dimming function, brighten a value
-LIB8STATIC uint8_t brighten8_raw( uint8_t x)
-{
-    uint8_t ix = 255 - x;
-    return 255 - scale8( ix, ix);
-}
-
-/// inverse of the dimming function, brighten a value
-LIB8STATIC uint8_t brighten8_video( uint8_t x)
-{
-    uint8_t ix = 255 - x;
-    return 255 - scale8_video( ix, ix);
-}
-
-/// inverse of the dimming function, brighten a value
-LIB8STATIC uint8_t brighten8_lin( uint8_t x )
-{
-    uint8_t ix = 255 - x;
-    if( ix & 0x80 ) {
-        ix = scale8( ix, ix);
-    } else {
-        ix += 1;
-        ix /= 2;
-    }
-    return 255 - ix;
-}
-
-///@}
-#endif
diff --git a/lib/lib8tion/trig8.h b/lib/lib8tion/trig8.h
deleted file mode 100644
index cfba6373fb..0000000000
--- a/lib/lib8tion/trig8.h
+++ /dev/null
@@ -1,284 +0,0 @@
-#ifndef __INC_LIB8TION_TRIG_H
-#define __INC_LIB8TION_TRIG_H
-
-///@ingroup lib8tion
-
-///@defgroup Trig Fast trig functions
-/// Fast 8 and 16-bit approximations of sin(x) and cos(x).
-///        Don't use these approximations for calculating the
-///        trajectory of a rocket to Mars, but they're great
-///        for art projects and LED displays.
-///
-///        On Arduino/AVR, the 16-bit approximation is more than
-///        10X faster than floating point sin(x) and cos(x), while
-/// the 8-bit approximation is more than 20X faster.
-///@{
-
-#if defined(__AVR__)
-#define sin16 sin16_avr
-#else
-#define sin16 sin16_C
-#endif
-
-/// Fast 16-bit approximation of sin(x). This approximation never varies more than
-/// 0.69% from the floating point value you'd get by doing
-///
-///     float s = sin(x) * 32767.0;
-///
-/// @param theta input angle from 0-65535
-/// @returns sin of theta, value between -32767 to 32767.
-LIB8STATIC int16_t sin16_avr( uint16_t theta )
-{
-    static const uint8_t data[] =
-    { 0,         0,         49, 0, 6393%256,   6393/256, 48, 0,
-      12539%256, 12539/256, 44, 0, 18204%256, 18204/256, 38, 0,
-      23170%256, 23170/256, 31, 0, 27245%256, 27245/256, 23, 0,
-      30273%256, 30273/256, 14, 0, 32137%256, 32137/256,  4 /*,0*/ };
-
-    uint16_t offset = (theta & 0x3FFF);
-
-    // AVR doesn't have a multi-bit shift instruction,
-    // so if we say "offset >>= 3", gcc makes a tiny loop.
-    // Inserting empty volatile statements between each
-    // bit shift forces gcc to unroll the loop.
-    offset >>= 1; // 0..8191
-    asm volatile("");
-    offset >>= 1; // 0..4095
-    asm volatile("");
-    offset >>= 1; // 0..2047
-
-    if( theta & 0x4000 ) offset = 2047 - offset;
-
-    uint8_t sectionX4;
-    sectionX4 = offset / 256;
-    sectionX4 *= 4;
-
-    uint8_t m;
-
-    union {
-        uint16_t b;
-        struct {
-            uint8_t blo;
-            uint8_t bhi;
-        };
-    } u;
-
-    //in effect u.b = blo + (256 * bhi);
-    u.blo = data[ sectionX4 ];
-    u.bhi = data[ sectionX4 + 1];
-    m     = data[ sectionX4 + 2];
-
-    uint8_t secoffset8 = (uint8_t)(offset) / 2;
-
-    uint16_t mx = m * secoffset8;
-
-    int16_t  y  = mx + u.b;
-    if( theta & 0x8000 ) y = -y;
-
-    return y;
-}
-
-/// Fast 16-bit approximation of sin(x). This approximation never varies more than
-/// 0.69% from the floating point value you'd get by doing
-///
-///     float s = sin(x) * 32767.0;
-///
-/// @param theta input angle from 0-65535
-/// @returns sin of theta, value between -32767 to 32767.
-LIB8STATIC int16_t sin16_C( uint16_t theta )
-{
-    static const uint16_t base[] =
-    { 0, 6393, 12539, 18204, 23170, 27245, 30273, 32137 };
-    static const uint8_t slope[] =
-    { 49, 48, 44, 38, 31, 23, 14, 4 };
-
-    uint16_t offset = (theta & 0x3FFF) >> 3; // 0..2047
-    if( theta & 0x4000 ) offset = 2047 - offset;
-
-    uint8_t section = offset / 256; // 0..7
-    uint16_t b   = base[section];
-    uint8_t  m   = slope[section];
-
-    uint8_t secoffset8 = (uint8_t)(offset) / 2;
-
-    uint16_t mx = m * secoffset8;
-    int16_t  y  = mx + b;
-
-    if( theta & 0x8000 ) y = -y;
-
-    return y;
-}
-
-
-/// Fast 16-bit approximation of cos(x). This approximation never varies more than
-/// 0.69% from the floating point value you'd get by doing
-///
-///     float s = cos(x) * 32767.0;
-///
-/// @param theta input angle from 0-65535
-/// @returns sin of theta, value between -32767 to 32767.
-LIB8STATIC int16_t cos16( uint16_t theta)
-{
-    return sin16( theta + 16384);
-}
-
-///////////////////////////////////////////////////////////////////////
-
-// sin8 & cos8
-//        Fast 8-bit approximations of sin(x) & cos(x).
-//        Input angle is an unsigned int from 0-255.
-//        Output is an unsigned int from 0 to 255.
-//
-//        This approximation can vary to to 2%
-//        from the floating point value you'd get by doing
-//          float s = (sin( x ) * 128.0) + 128;
-//
-//        Don't use this approximation for calculating the
-//        "real" trigonometric calculations, but it's great
-//        for art projects and LED displays.
-//
-//        On Arduino/AVR, this approximation is more than
-//        20X faster than floating point sin(x) and cos(x)
-
-#if defined(__AVR__) && !defined(LIB8_ATTINY)
-#define sin8 sin8_avr
-#else
-#define sin8 sin8_C
-#endif
-
-
-static const uint8_t b_m16_interleave[8] = { 0, 49, 49, 41, 90, 27, 117, 10 };
-
-/// Fast 8-bit approximation of sin(x). This approximation never varies more than
-/// 2% from the floating point value you'd get by doing
-///
-///     float s = (sin(x) * 128.0) + 128;
-///
-/// @param theta input angle from 0-255
-/// @returns sin of theta, value between 0 and 255
-LIB8STATIC uint8_t  sin8_avr( uint8_t theta)
-{
-    uint8_t offset = theta;
-
-    asm volatile(
-                 "sbrc %[theta],6         \n\t"
-                 "com  %[offset]           \n\t"
-                 : [theta] "+r" (theta), [offset] "+r" (offset)
-                 );
-
-    offset &= 0x3F; // 0..63
-
-    uint8_t secoffset  = offset & 0x0F; // 0..15
-    if( theta & 0x40) secoffset++;
-
-    uint8_t m16; uint8_t b;
-
-    uint8_t section = offset >> 4; // 0..3
-    uint8_t s2 = section * 2;
-
-    const uint8_t* p = b_m16_interleave;
-    p += s2;
-    b   = *p;
-    p++;
-    m16 = *p;
-
-    uint8_t mx;
-    uint8_t xr1;
-    asm volatile(
-                 "mul %[m16],%[secoffset]   \n\t"
-                 "mov %[mx],r0              \n\t"
-                 "mov %[xr1],r1             \n\t"
-                 "eor  r1, r1               \n\t"
-                 "swap %[mx]                \n\t"
-                 "andi %[mx],0x0F           \n\t"
-                 "swap %[xr1]               \n\t"
-                 "andi %[xr1], 0xF0         \n\t"
-                 "or   %[mx], %[xr1]        \n\t"
-                 : [mx] "=d" (mx), [xr1] "=d" (xr1)
-                 : [m16] "d" (m16), [secoffset] "d" (secoffset)
-                 );
-
-    int8_t y = mx + b;
-    if( theta & 0x80 ) y = -y;
-
-    y += 128;
-
-    return y;
-}
-
-
-/// Fast 8-bit approximation of sin(x). This approximation never varies more than
-/// 2% from the floating point value you'd get by doing
-///
-///     float s = (sin(x) * 128.0) + 128;
-///
-/// @param theta input angle from 0-255
-/// @returns sin of theta, value between 0 and 255
-LIB8STATIC uint8_t sin8_C( uint8_t theta)
-{
-    uint8_t offset = theta;
-    if( theta & 0x40 ) {
-        offset = (uint8_t)255 - offset;
-    }
-    offset &= 0x3F; // 0..63
-
-    uint8_t secoffset  = offset & 0x0F; // 0..15
-    if( theta & 0x40) secoffset++;
-
-    uint8_t section = offset >> 4; // 0..3
-    uint8_t s2 = section * 2;
-    const uint8_t* p = b_m16_interleave;
-    p += s2;
-    uint8_t b   =  *p;
-    p++;
-    uint8_t m16 =  *p;
-
-    uint8_t mx = (m16 * secoffset) >> 4;
-
-    int8_t y = mx + b;
-    if( theta & 0x80 ) y = -y;
-
-    y += 128;
-
-    return y;
-}
-
-/// Fast 8-bit approximation of cos(x). This approximation never varies more than
-/// 2% from the floating point value you'd get by doing
-///
-///     float s = (cos(x) * 128.0) + 128;
-///
-/// @param theta input angle from 0-255
-/// @returns sin of theta, value between 0 and 255
-LIB8STATIC uint8_t cos8( uint8_t theta)
-{
-    return sin8( theta + 64);
-}
-
-/// Fast 16-bit approximation of atan2(x).
-/// @returns atan2, value between 0 and 255
-LIB8STATIC uint8_t atan2_8(int16_t dy, int16_t dx)
-{
-    if (dy == 0)
-    {
-        if (dx >= 0)
-            return 0;
-        else
-            return 128;
-    }
-
-    int16_t abs_y = dy > 0 ? dy : -dy;
-    int8_t a;
-
-    if (dx >= 0)
-        a = 32 - (32 * (dx - abs_y) / (dx + abs_y));
-    else
-        a = 96 - (32 * (dx + abs_y) / (abs_y - dx));
-
-    if (dy < 0)
-        return -a;     // negate if in quad III or IV
-    return a;
-}
-
-///@}
-#endif
diff --git a/lib/printf b/lib/printf
deleted file mode 160000
-Subproject c2e3b4e10d281e7f0f694d3ecbd9f320977288c
diff --git a/lib/usbhost/USB_Host_Shield_2.0/.gitattributes b/lib/usbhost/USB_Host_Shield_2.0/.gitattributes
deleted file mode 100644
index 6238b035a3..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/.gitattributes
+++ /dev/null
@@ -1,23 +0,0 @@
-# Auto detect text files and perform LF normalization
-* text=auto
-* text eol=lf
-
-# Custom for Visual Studio
-*.cs     diff=csharp
-*.sln    merge=union
-*.csproj merge=union
-*.vbproj merge=union
-*.fsproj merge=union
-*.dbproj merge=union
-
-# Standard to msysgit
-*.doc	 diff=astextplain
-*.DOC	 diff=astextplain
-*.docx diff=astextplain
-*.DOCX diff=astextplain
-*.dot  diff=astextplain
-*.DOT  diff=astextplain
-*.pdf  diff=astextplain
-*.PDF	 diff=astextplain
-*.rtf	 diff=astextplain
-*.RTF	 diff=astextplain
diff --git a/lib/usbhost/USB_Host_Shield_2.0/.gitignore b/lib/usbhost/USB_Host_Shield_2.0/.gitignore
deleted file mode 100644
index 7e69f457ba..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-*.bak
-*.zip
-*.rar
-build/
\ No newline at end of file
diff --git a/lib/usbhost/USB_Host_Shield_2.0/.gitmodules b/lib/usbhost/USB_Host_Shield_2.0/.gitmodules
deleted file mode 100644
index 32a0783a89..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/.gitmodules
+++ /dev/null
@@ -1,12 +0,0 @@
-[submodule "examples/testusbhostFAT/generic_storage"]
-	path = examples/testusbhostFAT/generic_storage
-	url = https://github.com/xxxajk/generic_storage
-[submodule "examples/testusbhostFAT/xmem2"]
-	path = examples/testusbhostFAT/xmem2
-	url = https://github.com/xxxajk/xmem2
-[submodule "examples/testusbhostFAT/Arduino_Makefile_master"]
-	path = examples/testusbhostFAT/Arduino_Makefile_master
-	url = https://github.com/xxxajk/Arduino_Makefile_master
-[submodule "examples/testusbhostFAT/RTClib"]
-	path = examples/testusbhostFAT/RTClib
-	url = https://github.com/xxxajk/RTClib
diff --git a/lib/usbhost/USB_Host_Shield_2.0/BTD.cpp b/lib/usbhost/USB_Host_Shield_2.0/BTD.cpp
deleted file mode 100644
index bcfba14b2b..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/BTD.cpp
+++ /dev/null
@@ -1,1364 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#include "BTD.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-
-const uint8_t BTD::BTD_CONTROL_PIPE = 0;
-const uint8_t BTD::BTD_EVENT_PIPE = 1;
-const uint8_t BTD::BTD_DATAIN_PIPE = 2;
-const uint8_t BTD::BTD_DATAOUT_PIPE = 3;
-
-BTD::BTD(USB *p) :
-connectToWii(false),
-pairWithWii(false),
-connectToHIDDevice(false),
-pairWithHIDDevice(false),
-pUsb(p), // Pointer to USB class instance - mandatory
-bAddress(0), // Device address - mandatory
-bNumEP(1), // If config descriptor needs to be parsed
-qNextPollTime(0), // Reset NextPollTime
-pollInterval(0),
-bPollEnable(false) // Don't start polling before dongle is connected
-{
-        for(uint8_t i = 0; i < BTD_NUM_SERVICES; i++)
-                btService[i] = NULL;
-
-        Initialize(); // Set all variables, endpoint structs etc. to default values
-
-        if(pUsb) // Register in USB subsystem
-                pUsb->RegisterDeviceClass(this); // Set devConfig[] entry
-}
-
-uint8_t BTD::ConfigureDevice(uint8_t parent, uint8_t port, bool lowspeed) {
-        const uint8_t constBufSize = sizeof (USB_DEVICE_DESCRIPTOR);
-        uint8_t buf[constBufSize];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-
-        Initialize(); // Set all variables, endpoint structs etc. to default values
-
-        AddressPool &addrPool = pUsb->GetAddressPool(); // Get memory address of USB device address pool
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nBTD ConfigureDevice"), 0x80);
-#endif
-
-        if(bAddress) { // Check if address has already been assigned to an instance
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress in use"), 0x80);
-#endif
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-        }
-
-        p = addrPool.GetUsbDevicePtr(0); // Get pointer to pseudo device with address 0 assigned
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        if(!p->epinfo) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nepinfo is null"), 0x80);
-#endif
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        oldep_ptr = p->epinfo; // Save old pointer to EP_RECORD of address 0
-        p->epinfo = epInfo; // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->lowspeed = lowspeed;
-        rcode = pUsb->getDevDescr(0, 0, constBufSize, (uint8_t*)buf); // Get device descriptor - addr, ep, nbytes, data
-
-        p->epinfo = oldep_ptr; // Restore p->epinfo
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        bAddress = addrPool.AllocAddress(parent, false, port); // Allocate new address according to device class
-
-        if(!bAddress) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nOut of address space"), 0x80);
-#endif
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-        }
-
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0; // Extract Max Packet Size from device descriptor
-        epInfo[1].epAddr = udd->bNumConfigurations; // Steal and abuse from epInfo structure to save memory
-
-        VID = udd->idVendor;
-        PID = udd->idProduct;
-
-        return USB_ERROR_CONFIG_REQUIRES_ADDITIONAL_RESET;
-
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr(rcode);
-#endif
-        if(rcode != hrJERR)
-                rcode = USB_ERROR_FailGetDevDescr;
-        Release();
-        return rcode;
-};
-
-uint8_t BTD::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        uint8_t rcode;
-        uint8_t num_of_conf = epInfo[1].epAddr; // Number of configurations
-        epInfo[1].epAddr = 0;
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nBTD Init"), 0x80);
-#endif
-        UsbDevice *p = addrPool.GetUsbDevicePtr(bAddress); // Get pointer to assigned address record
-
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        delay(300); // Assign new address to the device
-
-        rcode = pUsb->setAddr(0, 0, bAddress); // Assign new address to the device
-        if(rcode) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nsetAddr: "), 0x80);
-                D_PrintHex<uint8_t > (rcode, 0x80);
-#endif
-                p->lowspeed = false;
-                goto Fail;
-        }
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nAddr: "), 0x80);
-        D_PrintHex<uint8_t > (bAddress, 0x80);
-#endif
-
-        p->lowspeed = false;
-
-        p = addrPool.GetUsbDevicePtr(bAddress); // Get pointer to assigned address record
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        p->lowspeed = lowspeed;
-
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo); // Assign epInfo to epinfo pointer - only EP0 is known
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        if(VID == PS3_VID && (PID == PS3_PID || PID == PS3NAVIGATION_PID || PID == PS3MOVE_PID)) {
-                delay(100);
-                rcode = pUsb->setConf(bAddress, epInfo[ BTD_CONTROL_PIPE ].epAddr, 1); // We only need the Control endpoint, so we don't have to initialize the other endpoints of device
-                if(rcode)
-                        goto FailSetConfDescr;
-
-#ifdef DEBUG_USB_HOST
-                if(PID == PS3_PID || PID == PS3NAVIGATION_PID) {
-                        if(PID == PS3_PID)
-                                Notify(PSTR("\r\nDualshock 3 Controller Connected"), 0x80);
-                        else // It must be a navigation controller
-                                Notify(PSTR("\r\nNavigation Controller Connected"), 0x80);
-                } else // It must be a Motion controller
-                        Notify(PSTR("\r\nMotion Controller Connected"), 0x80);
-#endif
-
-                if(my_bdaddr[0] == 0x00 && my_bdaddr[1] == 0x00 && my_bdaddr[2] == 0x00 && my_bdaddr[3] == 0x00 && my_bdaddr[4] == 0x00 && my_bdaddr[5] == 0x00) {
-#ifdef DEBUG_USB_HOST
-                        Notify(PSTR("\r\nPlease plug in the dongle before trying to pair with the PS3 Controller\r\nor set the Bluetooth address in the constructor of the PS3BT class"), 0x80);
-#endif
-                } else {
-                        if(PID == PS3_PID || PID == PS3NAVIGATION_PID)
-                                setBdaddr(my_bdaddr); // Set internal Bluetooth address
-                        else
-                                setMoveBdaddr(my_bdaddr); // Set internal Bluetooth address
-#ifdef DEBUG_USB_HOST
-                        Notify(PSTR("\r\nBluetooth Address was set to: "), 0x80);
-                        for(int8_t i = 5; i > 0; i--) {
-                                D_PrintHex<uint8_t > (my_bdaddr[i], 0x80);
-                                Notify(PSTR(":"), 0x80);
-                        }
-                        D_PrintHex<uint8_t > (my_bdaddr[0], 0x80);
-#endif
-                }
-
-                pUsb->setConf(bAddress, epInfo[ BTD_CONTROL_PIPE ].epAddr, 0); // Reset configuration value
-                pUsb->setAddr(bAddress, 0, 0); // Reset address
-                Release(); // Release device
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED; // Return
-        } else {
-                // Check if attached device is a Bluetooth dongle and fill endpoint data structure
-                // First interface in the configuration must have Bluetooth assigned Class/Subclass/Protocol
-                // And 3 endpoints - interrupt-IN, bulk-IN, bulk-OUT, not necessarily in this order
-                for(uint8_t i = 0; i < num_of_conf; i++) {
-                        if(VID == IOGEAR_GBU521_VID && PID == IOGEAR_GBU521_PID) {
-                                ConfigDescParser<USB_CLASS_VENDOR_SPECIFIC, WI_SUBCLASS_RF, WI_PROTOCOL_BT, CP_MASK_COMPARE_ALL> confDescrParser(this); // Needed for the IOGEAR GBU521
-                                rcode = pUsb->getConfDescr(bAddress, 0, i, &confDescrParser);
-                        } else {
-                                ConfigDescParser<USB_CLASS_WIRELESS_CTRL, WI_SUBCLASS_RF, WI_PROTOCOL_BT, CP_MASK_COMPARE_ALL> confDescrParser(this);
-                                rcode = pUsb->getConfDescr(bAddress, 0, i, &confDescrParser);
-                        }
-                        if(rcode) // Check error code
-                                goto FailGetConfDescr;
-                        if(bNumEP >= BTD_MAX_ENDPOINTS) // All endpoints extracted
-                                break;
-                }
-
-                if(bNumEP < BTD_MAX_ENDPOINTS)
-                        goto FailUnknownDevice;
-
-                // Assign epInfo to epinfo pointer - this time all 3 endpoins
-                rcode = pUsb->setEpInfoEntry(bAddress, bNumEP, epInfo);
-                if(rcode)
-                        goto FailSetDevTblEntry;
-
-                // Set Configuration Value
-                rcode = pUsb->setConf(bAddress, epInfo[ BTD_CONTROL_PIPE ].epAddr, bConfNum);
-                if(rcode)
-                        goto FailSetConfDescr;
-
-                hci_num_reset_loops = 100; // only loop 100 times before trying to send the hci reset command
-                hci_counter = 0;
-                hci_state = HCI_INIT_STATE;
-                watingForConnection = false;
-                bPollEnable = true;
-
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nBluetooth Dongle Initialized"), 0x80);
-#endif
-        }
-        return 0; // Successful configuration
-
-        /* Diagnostic messages */
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailGetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetConfDescr();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-#endif
-        goto Fail;
-
-FailUnknownDevice:
-#ifdef DEBUG_USB_HOST
-        NotifyFailUnknownDevice(VID, PID);
-#endif
-        pUsb->setAddr(bAddress, 0, 0); // Reset address
-        rcode = USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-Fail:
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nBTD Init Failed, error code: "), 0x80);
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-void BTD::Initialize() {
-        uint8_t i;
-        for(i = 0; i < BTD_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-        }
-        for(i = 0; i < BTD_NUM_SERVICES; i++) {
-                if(btService[i])
-                        btService[i]->Reset(); // Reset all Bluetooth services
-        }
-
-        connectToWii = false;
-        incomingWii = false;
-        connectToHIDDevice = false;
-        incomingHIDDevice = false;
-        incomingPS4 = false;
-        bAddress = 0; // Clear device address
-        bNumEP = 1; // Must have to be reset to 1
-        qNextPollTime = 0; // Reset next poll time
-        pollInterval = 0;
-        bPollEnable = false; // Don't start polling before dongle is connected
-}
-
-/* Extracts interrupt-IN, bulk-IN, bulk-OUT endpoint information from config descriptor */
-void BTD::EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *pep) {
-        //ErrorMessage<uint8_t>(PSTR("Conf.Val"),conf);
-        //ErrorMessage<uint8_t>(PSTR("Iface Num"),iface);
-        //ErrorMessage<uint8_t>(PSTR("Alt.Set"),alt);
-
-        if(alt) // Wrong interface - by BT spec, no alt setting
-                return;
-
-        bConfNum = conf;
-        uint8_t index;
-
-        if((pep->bmAttributes & 0x03) == 3 && (pep->bEndpointAddress & 0x80) == 0x80) { // Interrupt In endpoint found
-                index = BTD_EVENT_PIPE;
-                epInfo[index].bmNakPower = USB_NAK_NOWAIT;
-        } else {
-                if((pep->bmAttributes & 0x02) == 2) // Bulk endpoint found
-                        index = ((pep->bEndpointAddress & 0x80) == 0x80) ? BTD_DATAIN_PIPE : BTD_DATAOUT_PIPE;
-                else
-                        return;
-        }
-
-        // Fill the rest of endpoint data structure
-        epInfo[index].epAddr = (pep->bEndpointAddress & 0x0F);
-        epInfo[index].maxPktSize = (uint8_t)pep->wMaxPacketSize;
-#ifdef EXTRADEBUG
-        PrintEndpointDescriptor(pep);
-#endif
-        if(pollInterval < pep->bInterval) // Set the polling interval as the largest polling interval obtained from endpoints
-                pollInterval = pep->bInterval;
-        bNumEP++;
-}
-
-void BTD::PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr) {
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nEndpoint descriptor:"), 0x80);
-        Notify(PSTR("\r\nLength:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bLength, 0x80);
-        Notify(PSTR("\r\nType:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bDescriptorType, 0x80);
-        Notify(PSTR("\r\nAddress:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bEndpointAddress, 0x80);
-        Notify(PSTR("\r\nAttributes:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bmAttributes, 0x80);
-        Notify(PSTR("\r\nMaxPktSize:\t"), 0x80);
-        D_PrintHex<uint16_t > (ep_ptr->wMaxPacketSize, 0x80);
-        Notify(PSTR("\r\nPoll Intrv:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bInterval, 0x80);
-#endif
-}
-
-/* Performs a cleanup after failed Init() attempt */
-uint8_t BTD::Release() {
-        Initialize(); // Set all variables, endpoint structs etc. to default values
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-        return 0;
-}
-
-uint8_t BTD::Poll() {
-        if(!bPollEnable)
-                return 0;
-        if((long)(millis() - qNextPollTime) >= 0L) { // Don't poll if shorter than polling interval
-                qNextPollTime = millis() + pollInterval; // Set new poll time
-                HCI_event_task(); // Poll the HCI event pipe
-                HCI_task(); // HCI state machine
-                ACL_event_task(); // Poll the ACL input pipe too
-        }
-        return 0;
-}
-
-void BTD::disconnect() {
-        for(uint8_t i = 0; i < BTD_NUM_SERVICES; i++)
-                if(btService[i])
-                        btService[i]->disconnect();
-};
-
-void BTD::HCI_event_task() {
-        uint16_t length = BULK_MAXPKTSIZE; // Request more than 16 bytes anyway, the inTransfer routine will take care of this
-        uint8_t rcode = pUsb->inTransfer(bAddress, epInfo[ BTD_EVENT_PIPE ].epAddr, &length, hcibuf); // Input on endpoint 1
-
-        if(!rcode || rcode == hrNAK) { // Check for errors
-                switch(hcibuf[0]) { // Switch on event type
-                        case EV_COMMAND_COMPLETE:
-                                if(!hcibuf[5]) { // Check if command succeeded
-                                        hci_set_flag(HCI_FLAG_CMD_COMPLETE); // Set command complete flag
-                                        if((hcibuf[3] == 0x01) && (hcibuf[4] == 0x10)) { // Parameters from read local version information
-                                                hci_version = hcibuf[6]; // Used to check if it supports 2.0+EDR - see http://www.bluetooth.org/Technical/AssignedNumbers/hci.htm
-                                                hci_set_flag(HCI_FLAG_READ_VERSION);
-                                        } else if((hcibuf[3] == 0x09) && (hcibuf[4] == 0x10)) { // Parameters from read local bluetooth address
-                                                for(uint8_t i = 0; i < 6; i++)
-                                                        my_bdaddr[i] = hcibuf[6 + i];
-                                                hci_set_flag(HCI_FLAG_READ_BDADDR);
-                                        }
-                                }
-                                break;
-
-                        case EV_COMMAND_STATUS:
-                                if(hcibuf[2]) { // Show status on serial if not OK
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nHCI Command Failed: "), 0x80);
-                                        D_PrintHex<uint8_t > (hcibuf[2], 0x80);
-#endif
-                                }
-                                break;
-
-                        case EV_INQUIRY_COMPLETE:
-                                if(inquiry_counter >= 5 && (pairWithWii || pairWithHIDDevice)) {
-                                        inquiry_counter = 0;
-#ifdef DEBUG_USB_HOST
-                                        if(pairWithWii)
-                                                Notify(PSTR("\r\nCouldn't find Wiimote"), 0x80);
-                                        else
-                                                Notify(PSTR("\r\nCouldn't find HID device"), 0x80);
-#endif
-                                        connectToWii = false;
-                                        pairWithWii = false;
-                                        connectToHIDDevice = false;
-                                        pairWithHIDDevice = false;
-                                        hci_state = HCI_SCANNING_STATE;
-                                }
-                                inquiry_counter++;
-                                break;
-
-                        case EV_INQUIRY_RESULT:
-                                if(hcibuf[2]) { // Check that there is more than zero responses
-#ifdef EXTRADEBUG
-                                        Notify(PSTR("\r\nNumber of responses: "), 0x80);
-                                        Notify(hcibuf[2], 0x80);
-#endif
-                                        for(uint8_t i = 0; i < hcibuf[2]; i++) {
-                                                uint8_t offset = 8 * hcibuf[2] + 3 * i;
-
-                                                for(uint8_t j = 0; j < 3; j++)
-                                                        classOfDevice[j] = hcibuf[j + 4 + offset];
-
-#ifdef EXTRADEBUG
-                                                Notify(PSTR("\r\nClass of device: "), 0x80);
-                                                D_PrintHex<uint8_t > (classOfDevice[2], 0x80);
-                                                Notify(PSTR(" "), 0x80);
-                                                D_PrintHex<uint8_t > (classOfDevice[1], 0x80);
-                                                Notify(PSTR(" "), 0x80);
-                                                D_PrintHex<uint8_t > (classOfDevice[0], 0x80);
-#endif
-
-                                                if(pairWithWii && classOfDevice[2] == 0x00 && (classOfDevice[1] & 0x05) && (classOfDevice[0] & 0x0C)) { // See http://wiibrew.org/wiki/Wiimote#SDP_information
-                                                        checkRemoteName = true; // Check remote name to distinguish between the different controllers
-
-                                                        for(uint8_t j = 0; j < 6; j++)
-                                                                disc_bdaddr[j] = hcibuf[j + 3 + 6 * i];
-
-                                                        hci_set_flag(HCI_FLAG_DEVICE_FOUND);
-                                                        break;
-                                                } else if(pairWithHIDDevice && (classOfDevice[1] & 0x05) && (classOfDevice[0] & 0xC8)) { // Check if it is a mouse, keyboard or a gamepad - see: http://bluetooth-pentest.narod.ru/software/bluetooth_class_of_device-service_generator.html
-#ifdef DEBUG_USB_HOST
-                                                        if(classOfDevice[0] & 0x80)
-                                                                Notify(PSTR("\r\nMouse found"), 0x80);
-                                                        if(classOfDevice[0] & 0x40)
-                                                                Notify(PSTR("\r\nKeyboard found"), 0x80);
-                                                        if(classOfDevice[0] & 0x08)
-                                                                Notify(PSTR("\r\nGamepad found"), 0x80);
-#endif
-
-                                                        for(uint8_t j = 0; j < 6; j++)
-                                                                disc_bdaddr[j] = hcibuf[j + 3 + 6 * i];
-
-                                                        hci_set_flag(HCI_FLAG_DEVICE_FOUND);
-                                                        break;
-                                                }
-                                        }
-                                }
-                                break;
-
-                        case EV_CONNECT_COMPLETE:
-                                hci_set_flag(HCI_FLAG_CONNECT_EVENT);
-                                if(!hcibuf[2]) { // Check if connected OK
-#ifdef EXTRADEBUG
-                                        Notify(PSTR("\r\nConnection established"), 0x80);
-#endif
-                                        hci_handle = hcibuf[3] | ((hcibuf[4] & 0x0F) << 8); // Store the handle for the ACL connection
-                                        hci_set_flag(HCI_FLAG_CONNECT_COMPLETE); // Set connection complete flag
-                                } else {
-                                        hci_state = HCI_CHECK_DEVICE_SERVICE;
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nConnection Failed: "), 0x80);
-                                        D_PrintHex<uint8_t > (hcibuf[2], 0x80);
-#endif
-                                }
-                                break;
-
-                        case EV_DISCONNECT_COMPLETE:
-                                if(!hcibuf[2]) { // Check if disconnected OK
-                                        hci_set_flag(HCI_FLAG_DISCONNECT_COMPLETE); // Set disconnect command complete flag
-                                        hci_clear_flag(HCI_FLAG_CONNECT_COMPLETE); // Clear connection complete flag
-                                }
-                                break;
-
-                        case EV_REMOTE_NAME_COMPLETE:
-                                if(!hcibuf[2]) { // Check if reading is OK
-                                        for(uint8_t i = 0; i < min(sizeof (remote_name), sizeof (hcibuf) - 9); i++) {
-                                                remote_name[i] = hcibuf[9 + i];
-                                                if(remote_name[i] == '\0') // End of string
-                                                        break;
-                                        }
-                                        // TODO: Altid sæt '\0' i remote name!
-                                        hci_set_flag(HCI_FLAG_REMOTE_NAME_COMPLETE);
-                                }
-                                break;
-
-                        case EV_INCOMING_CONNECT:
-                                for(uint8_t i = 0; i < 6; i++)
-                                        disc_bdaddr[i] = hcibuf[i + 2];
-
-                                for(uint8_t i = 0; i < 3; i++)
-                                        classOfDevice[i] = hcibuf[i + 8];
-
-                                if((classOfDevice[1] & 0x05) && (classOfDevice[0] & 0xC8)) { // Check if it is a mouse, keyboard or a gamepad
-#ifdef DEBUG_USB_HOST
-                                        if(classOfDevice[0] & 0x80)
-                                                Notify(PSTR("\r\nMouse is connecting"), 0x80);
-                                        if(classOfDevice[0] & 0x40)
-                                                Notify(PSTR("\r\nKeyboard is connecting"), 0x80);
-                                        if(classOfDevice[0] & 0x08)
-                                                Notify(PSTR("\r\nGamepad is connecting"), 0x80);
-#endif
-                                        incomingHIDDevice = true;
-                                }
-
-#ifdef EXTRADEBUG
-                                Notify(PSTR("\r\nClass of device: "), 0x80);
-                                D_PrintHex<uint8_t > (classOfDevice[2], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (classOfDevice[1], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (classOfDevice[0], 0x80);
-#endif
-                                hci_set_flag(HCI_FLAG_INCOMING_REQUEST);
-                                break;
-
-                        case EV_PIN_CODE_REQUEST:
-                                if(pairWithWii) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nPairing with Wiimote"), 0x80);
-#endif
-                                        hci_pin_code_request_reply();
-                                } else if(btdPin != NULL) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nBluetooth pin is set too: "), 0x80);
-                                        NotifyStr(btdPin, 0x80);
-#endif
-                                        hci_pin_code_request_reply();
-                                } else {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nNo pin was set"), 0x80);
-#endif
-                                        hci_pin_code_negative_request_reply();
-                                }
-                                break;
-
-                        case EV_LINK_KEY_REQUEST:
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nReceived Key Request"), 0x80);
-#endif
-                                hci_link_key_request_negative_reply();
-                                break;
-
-                        case EV_AUTHENTICATION_COMPLETE:
-                                if(pairWithWii && !connectToWii) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nPairing successful with Wiimote"), 0x80);
-#endif
-                                        connectToWii = true; // Used to indicate to the Wii service, that it should connect to this device
-                                } else if(pairWithHIDDevice && !connectToHIDDevice) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nPairing successful with HID device"), 0x80);
-#endif
-                                        connectToHIDDevice = true; // Used to indicate to the BTHID service, that it should connect to this device
-                                }
-                                break;
-                                /* We will just ignore the following events */
-                        case EV_NUM_COMPLETE_PKT:
-                        case EV_ROLE_CHANGED:
-                        case EV_PAGE_SCAN_REP_MODE:
-                        case EV_LOOPBACK_COMMAND:
-                        case EV_DATA_BUFFER_OVERFLOW:
-                        case EV_CHANGE_CONNECTION_LINK:
-                        case EV_MAX_SLOTS_CHANGE:
-                        case EV_QOS_SETUP_COMPLETE:
-                        case EV_LINK_KEY_NOTIFICATION:
-                        case EV_ENCRYPTION_CHANGE:
-                        case EV_READ_REMOTE_VERSION_INFORMATION_COMPLETE:
-                                break;
-#ifdef EXTRADEBUG
-                        default:
-                                if(hcibuf[0] != 0x00) {
-                                        Notify(PSTR("\r\nUnmanaged HCI Event: "), 0x80);
-                                        D_PrintHex<uint8_t > (hcibuf[0], 0x80);
-                                }
-                                break;
-#endif
-                } // Switch
-        }
-#ifdef EXTRADEBUG
-        else {
-                Notify(PSTR("\r\nHCI event error: "), 0x80);
-                D_PrintHex<uint8_t > (rcode, 0x80);
-        }
-#endif
-}
-
-/* Poll Bluetooth and print result */
-void BTD::HCI_task() {
-        switch(hci_state) {
-                case HCI_INIT_STATE:
-                        hci_counter++;
-                        if(hci_counter > hci_num_reset_loops) { // wait until we have looped x times to clear any old events
-                                hci_reset();
-                                hci_state = HCI_RESET_STATE;
-                                hci_counter = 0;
-                        }
-                        break;
-
-                case HCI_RESET_STATE:
-                        hci_counter++;
-                        if(hci_check_flag(HCI_FLAG_CMD_COMPLETE)) {
-                                hci_counter = 0;
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHCI Reset complete"), 0x80);
-#endif
-                                hci_state = HCI_CLASS_STATE;
-                                hci_write_class_of_device();
-                        } else if(hci_counter > hci_num_reset_loops) {
-                                hci_num_reset_loops *= 10;
-                                if(hci_num_reset_loops > 2000)
-                                        hci_num_reset_loops = 2000;
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nNo response to HCI Reset"), 0x80);
-#endif
-                                hci_state = HCI_INIT_STATE;
-                                hci_counter = 0;
-                        }
-                        break;
-
-                case HCI_CLASS_STATE:
-                        if(hci_check_flag(HCI_FLAG_CMD_COMPLETE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nWrite class of device"), 0x80);
-#endif
-                                hci_state = HCI_BDADDR_STATE;
-                                hci_read_bdaddr();
-                        }
-                        break;
-
-                case HCI_BDADDR_STATE:
-                        if(hci_check_flag(HCI_FLAG_READ_BDADDR)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nLocal Bluetooth Address: "), 0x80);
-                                for(int8_t i = 5; i > 0; i--) {
-                                        D_PrintHex<uint8_t > (my_bdaddr[i], 0x80);
-                                        Notify(PSTR(":"), 0x80);
-                                }
-                                D_PrintHex<uint8_t > (my_bdaddr[0], 0x80);
-#endif
-                                hci_read_local_version_information();
-                                hci_state = HCI_LOCAL_VERSION_STATE;
-                        }
-                        break;
-
-                case HCI_LOCAL_VERSION_STATE: // The local version is used by the PS3BT class
-                        if(hci_check_flag(HCI_FLAG_READ_VERSION)) {
-                                if(btdName != NULL) {
-                                        hci_set_local_name(btdName);
-                                        hci_state = HCI_SET_NAME_STATE;
-                                } else
-                                        hci_state = HCI_CHECK_DEVICE_SERVICE;
-                        }
-                        break;
-
-                case HCI_SET_NAME_STATE:
-                        if(hci_check_flag(HCI_FLAG_CMD_COMPLETE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nThe name is set to: "), 0x80);
-                                NotifyStr(btdName, 0x80);
-#endif
-                                hci_state = HCI_CHECK_DEVICE_SERVICE;
-                        }
-                        break;
-
-                case HCI_CHECK_DEVICE_SERVICE:
-                        if(pairWithHIDDevice || pairWithWii) { // Check if it should try to connect to a Wiimote
-#ifdef DEBUG_USB_HOST
-                                if(pairWithWii)
-                                        Notify(PSTR("\r\nStarting inquiry\r\nPress 1 & 2 on the Wiimote\r\nOr press the SYNC button if you are using a Wii U Pro Controller or a Wii Balance Board"), 0x80);
-                                else
-                                        Notify(PSTR("\r\nPlease enable discovery of your device"), 0x80);
-#endif
-                                hci_inquiry();
-                                hci_state = HCI_INQUIRY_STATE;
-                        } else
-                                hci_state = HCI_SCANNING_STATE; // Don't try to connect to a Wiimote
-                        break;
-
-                case HCI_INQUIRY_STATE:
-                        if(hci_check_flag(HCI_FLAG_DEVICE_FOUND)) {
-                                hci_inquiry_cancel(); // Stop inquiry
-#ifdef DEBUG_USB_HOST
-                                if(pairWithWii)
-                                        Notify(PSTR("\r\nWiimote found"), 0x80);
-                                else
-                                        Notify(PSTR("\r\nHID device found"), 0x80);
-
-                                Notify(PSTR("\r\nNow just create the instance like so:"), 0x80);
-                                if(pairWithWii)
-                                        Notify(PSTR("\r\nWII Wii(&Btd);"), 0x80);
-                                else
-                                        Notify(PSTR("\r\nBTHID bthid(&Btd);"), 0x80);
-
-                                Notify(PSTR("\r\nAnd then press any button on the "), 0x80);
-                                if(pairWithWii)
-                                        Notify(PSTR("Wiimote"), 0x80);
-                                else
-                                        Notify(PSTR("device"), 0x80);
-#endif
-                                if(checkRemoteName) {
-                                        hci_remote_name(); // We need to know the name to distinguish between the Wiimote, the new Wiimote with Motion Plus inside, a Wii U Pro Controller and a Wii Balance Board
-                                        hci_state = HCI_REMOTE_NAME_STATE;
-                                } else
-                                        hci_state = HCI_CONNECT_DEVICE_STATE;
-                        }
-                        break;
-
-                case HCI_CONNECT_DEVICE_STATE:
-                        if(hci_check_flag(HCI_FLAG_CMD_COMPLETE)) {
-#ifdef DEBUG_USB_HOST
-                                if(pairWithWii)
-                                        Notify(PSTR("\r\nConnecting to Wiimote"), 0x80);
-                                else
-                                        Notify(PSTR("\r\nConnecting to HID device"), 0x80);
-#endif
-                                checkRemoteName = false;
-                                hci_connect();
-                                hci_state = HCI_CONNECTED_DEVICE_STATE;
-                        }
-                        break;
-
-                case HCI_CONNECTED_DEVICE_STATE:
-                        if(hci_check_flag(HCI_FLAG_CONNECT_EVENT)) {
-                                if(hci_check_flag(HCI_FLAG_CONNECT_COMPLETE)) {
-#ifdef DEBUG_USB_HOST
-                                        if(pairWithWii)
-                                                Notify(PSTR("\r\nConnected to Wiimote"), 0x80);
-                                        else
-                                                Notify(PSTR("\r\nConnected to HID device"), 0x80);
-#endif
-                                        hci_authentication_request(); // This will start the pairing with the Wiimote
-                                        hci_state = HCI_SCANNING_STATE;
-                                } else {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nTrying to connect one more time..."), 0x80);
-#endif
-                                        hci_connect(); // Try to connect one more time
-                                }
-                        }
-                        break;
-
-                case HCI_SCANNING_STATE:
-                        if(!connectToWii && !pairWithWii && !connectToHIDDevice && !pairWithHIDDevice) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nWait For Incoming Connection Request"), 0x80);
-#endif
-                                hci_write_scan_enable();
-                                watingForConnection = true;
-                                hci_state = HCI_CONNECT_IN_STATE;
-                        }
-                        break;
-
-                case HCI_CONNECT_IN_STATE:
-                        if(hci_check_flag(HCI_FLAG_INCOMING_REQUEST)) {
-                                watingForConnection = false;
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nIncoming Connection Request"), 0x80);
-#endif
-                                hci_remote_name();
-                                hci_state = HCI_REMOTE_NAME_STATE;
-                        } else if(hci_check_flag(HCI_FLAG_DISCONNECT_COMPLETE))
-                                hci_state = HCI_DISCONNECT_STATE;
-                        break;
-
-                case HCI_REMOTE_NAME_STATE:
-                        if(hci_check_flag(HCI_FLAG_REMOTE_NAME_COMPLETE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nRemote Name: "), 0x80);
-                                for(uint8_t i = 0; i < strlen(remote_name); i++)
-                                        Notifyc(remote_name[i], 0x80);
-#endif
-                                if(strncmp((const char*)remote_name, "Nintendo", 8) == 0) {
-                                        incomingWii = true;
-                                        motionPlusInside = false;
-                                        wiiUProController = false;
-                                        pairWiiUsingSync = false;
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nWiimote is connecting"), 0x80);
-#endif
-                                        if(strncmp((const char*)remote_name, "Nintendo RVL-CNT-01-TR", 22) == 0) {
-#ifdef DEBUG_USB_HOST
-                                                Notify(PSTR(" with Motion Plus Inside"), 0x80);
-#endif
-                                                motionPlusInside = true;
-                                        } else if(strncmp((const char*)remote_name, "Nintendo RVL-CNT-01-UC", 22) == 0) {
-#ifdef DEBUG_USB_HOST
-                                                Notify(PSTR(" - Wii U Pro Controller"), 0x80);
-#endif
-                                                wiiUProController = motionPlusInside = pairWiiUsingSync = true;
-                                        } else if(strncmp((const char*)remote_name, "Nintendo RVL-WBC-01", 19) == 0) {
-#ifdef DEBUG_USB_HOST
-                                                Notify(PSTR(" - Wii Balance Board"), 0x80);
-#endif
-                                                pairWiiUsingSync = true;
-                                        }
-                                }
-                                if(classOfDevice[2] == 0 && classOfDevice[1] == 0x25 && classOfDevice[0] == 0x08 && strncmp((const char*)remote_name, "Wireless Controller", 19) == 0) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nPS4 controller is connecting"), 0x80);
-#endif
-                                        incomingPS4 = true;
-                                }
-                                if(pairWithWii && checkRemoteName)
-                                        hci_state = HCI_CONNECT_DEVICE_STATE;
-                                else {
-                                        hci_accept_connection();
-                                        hci_state = HCI_CONNECTED_STATE;
-                                }
-                        }
-                        break;
-
-                case HCI_CONNECTED_STATE:
-                        if(hci_check_flag(HCI_FLAG_CONNECT_COMPLETE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nConnected to Device: "), 0x80);
-                                for(int8_t i = 5; i > 0; i--) {
-                                        D_PrintHex<uint8_t > (disc_bdaddr[i], 0x80);
-                                        Notify(PSTR(":"), 0x80);
-                                }
-                                D_PrintHex<uint8_t > (disc_bdaddr[0], 0x80);
-#endif
-                                if(incomingPS4)
-                                        connectToHIDDevice = true; // We should always connect to the PS4 controller
-
-                                // Clear these flags for a new connection
-                                l2capConnectionClaimed = false;
-                                sdpConnectionClaimed = false;
-                                rfcommConnectionClaimed = false;
-
-                                hci_event_flag = 0;
-                                hci_state = HCI_DONE_STATE;
-                        }
-                        break;
-
-                case HCI_DONE_STATE:
-                        hci_counter++;
-                        if(hci_counter > 1000) { // Wait until we have looped 1000 times to make sure that the L2CAP connection has been started
-                                hci_counter = 0;
-                                hci_state = HCI_SCANNING_STATE;
-                        }
-                        break;
-
-                case HCI_DISCONNECT_STATE:
-                        if(hci_check_flag(HCI_FLAG_DISCONNECT_COMPLETE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHCI Disconnected from Device"), 0x80);
-#endif
-                                hci_event_flag = 0; // Clear all flags
-
-                                // Reset all buffers
-                                memset(hcibuf, 0, BULK_MAXPKTSIZE);
-                                memset(l2capinbuf, 0, BULK_MAXPKTSIZE);
-
-                                connectToWii = incomingWii = pairWithWii = false;
-                                connectToHIDDevice = incomingHIDDevice = pairWithHIDDevice = checkRemoteName = false;
-                                incomingPS4 = false;
-
-                                hci_state = HCI_SCANNING_STATE;
-                        }
-                        break;
-                default:
-                        break;
-        }
-}
-
-void BTD::ACL_event_task() {
-        uint16_t length = BULK_MAXPKTSIZE;
-        uint8_t rcode = pUsb->inTransfer(bAddress, epInfo[ BTD_DATAIN_PIPE ].epAddr, &length, l2capinbuf); // Input on endpoint 2
-
-        if(!rcode) { // Check for errors
-                if(length > 0) { // Check if any data was read
-                        for(uint8_t i = 0; i < BTD_NUM_SERVICES; i++) {
-                                if(btService[i])
-                                        btService[i]->ACLData(l2capinbuf);
-                        }
-                }
-        }
-#ifdef EXTRADEBUG
-        else if(rcode != hrNAK) {
-                Notify(PSTR("\r\nACL data in error: "), 0x80);
-                D_PrintHex<uint8_t > (rcode, 0x80);
-        }
-#endif
-        for(uint8_t i = 0; i < BTD_NUM_SERVICES; i++)
-                if(btService[i])
-                        btService[i]->Run();
-}
-
-/************************************************************/
-/*                    HCI Commands                        */
-
-/************************************************************/
-void BTD::HCI_Command(uint8_t* data, uint16_t nbytes) {
-        hci_clear_flag(HCI_FLAG_CMD_COMPLETE);
-        pUsb->ctrlReq(bAddress, epInfo[ BTD_CONTROL_PIPE ].epAddr, bmREQ_HCI_OUT, 0x00, 0x00, 0x00, 0x00, nbytes, nbytes, data, NULL);
-}
-
-void BTD::hci_reset() {
-        hci_event_flag = 0; // Clear all the flags
-        hcibuf[0] = 0x03; // HCI OCF = 3
-        hcibuf[1] = 0x03 << 2; // HCI OGF = 3
-        hcibuf[2] = 0x00;
-
-        HCI_Command(hcibuf, 3);
-}
-
-void BTD::hci_write_scan_enable() {
-        hci_clear_flag(HCI_FLAG_INCOMING_REQUEST);
-        hcibuf[0] = 0x1A; // HCI OCF = 1A
-        hcibuf[1] = 0x03 << 2; // HCI OGF = 3
-        hcibuf[2] = 0x01; // parameter length = 1
-        if(btdName != NULL)
-                hcibuf[3] = 0x03; // Inquiry Scan enabled. Page Scan enabled.
-        else
-                hcibuf[3] = 0x02; // Inquiry Scan disabled. Page Scan enabled.
-
-        HCI_Command(hcibuf, 4);
-}
-
-void BTD::hci_write_scan_disable() {
-        hcibuf[0] = 0x1A; // HCI OCF = 1A
-        hcibuf[1] = 0x03 << 2; // HCI OGF = 3
-        hcibuf[2] = 0x01; // parameter length = 1
-        hcibuf[3] = 0x00; // Inquiry Scan disabled. Page Scan disabled.
-
-        HCI_Command(hcibuf, 4);
-}
-
-void BTD::hci_read_bdaddr() {
-        hci_clear_flag(HCI_FLAG_READ_BDADDR);
-        hcibuf[0] = 0x09; // HCI OCF = 9
-        hcibuf[1] = 0x04 << 2; // HCI OGF = 4
-        hcibuf[2] = 0x00;
-
-        HCI_Command(hcibuf, 3);
-}
-
-void BTD::hci_read_local_version_information() {
-        hci_clear_flag(HCI_FLAG_READ_VERSION);
-        hcibuf[0] = 0x01; // HCI OCF = 1
-        hcibuf[1] = 0x04 << 2; // HCI OGF = 4
-        hcibuf[2] = 0x00;
-
-        HCI_Command(hcibuf, 3);
-}
-
-void BTD::hci_accept_connection() {
-        hci_clear_flag(HCI_FLAG_CONNECT_COMPLETE);
-        hcibuf[0] = 0x09; // HCI OCF = 9
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x07; // parameter length 7
-        hcibuf[3] = disc_bdaddr[0]; // 6 octet bdaddr
-        hcibuf[4] = disc_bdaddr[1];
-        hcibuf[5] = disc_bdaddr[2];
-        hcibuf[6] = disc_bdaddr[3];
-        hcibuf[7] = disc_bdaddr[4];
-        hcibuf[8] = disc_bdaddr[5];
-        hcibuf[9] = 0x00; // Switch role to master
-
-        HCI_Command(hcibuf, 10);
-}
-
-void BTD::hci_remote_name() {
-        hci_clear_flag(HCI_FLAG_REMOTE_NAME_COMPLETE);
-        hcibuf[0] = 0x19; // HCI OCF = 19
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x0A; // parameter length = 10
-        hcibuf[3] = disc_bdaddr[0]; // 6 octet bdaddr
-        hcibuf[4] = disc_bdaddr[1];
-        hcibuf[5] = disc_bdaddr[2];
-        hcibuf[6] = disc_bdaddr[3];
-        hcibuf[7] = disc_bdaddr[4];
-        hcibuf[8] = disc_bdaddr[5];
-        hcibuf[9] = 0x01; // Page Scan Repetition Mode
-        hcibuf[10] = 0x00; // Reserved
-        hcibuf[11] = 0x00; // Clock offset - low byte
-        hcibuf[12] = 0x00; // Clock offset - high byte
-
-        HCI_Command(hcibuf, 13);
-}
-
-void BTD::hci_set_local_name(const char* name) {
-        hcibuf[0] = 0x13; // HCI OCF = 13
-        hcibuf[1] = 0x03 << 2; // HCI OGF = 3
-        hcibuf[2] = strlen(name) + 1; // parameter length = the length of the string + end byte
-        uint8_t i;
-        for(i = 0; i < strlen(name); i++)
-                hcibuf[i + 3] = name[i];
-        hcibuf[i + 3] = 0x00; // End of string
-
-        HCI_Command(hcibuf, 4 + strlen(name));
-}
-
-void BTD::hci_inquiry() {
-        hci_clear_flag(HCI_FLAG_DEVICE_FOUND);
-        hcibuf[0] = 0x01;
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x05; // Parameter Total Length = 5
-        hcibuf[3] = 0x33; // LAP: Genera/Unlimited Inquiry Access Code (GIAC = 0x9E8B33) - see https://www.bluetooth.org/Technical/AssignedNumbers/baseband.htm
-        hcibuf[4] = 0x8B;
-        hcibuf[5] = 0x9E;
-        hcibuf[6] = 0x30; // Inquiry time = 61.44 sec (maximum)
-        hcibuf[7] = 0x0A; // 10 number of responses
-
-        HCI_Command(hcibuf, 8);
-}
-
-void BTD::hci_inquiry_cancel() {
-        hcibuf[0] = 0x02;
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x00; // Parameter Total Length = 0
-
-        HCI_Command(hcibuf, 3);
-}
-
-void BTD::hci_connect() {
-        hci_connect(disc_bdaddr); // Use last discovered device
-}
-
-void BTD::hci_connect(uint8_t *bdaddr) {
-        hci_clear_flag(HCI_FLAG_CONNECT_COMPLETE | HCI_FLAG_CONNECT_EVENT);
-        hcibuf[0] = 0x05;
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x0D; // parameter Total Length = 13
-        hcibuf[3] = bdaddr[0]; // 6 octet bdaddr (LSB)
-        hcibuf[4] = bdaddr[1];
-        hcibuf[5] = bdaddr[2];
-        hcibuf[6] = bdaddr[3];
-        hcibuf[7] = bdaddr[4];
-        hcibuf[8] = bdaddr[5];
-        hcibuf[9] = 0x18; // DM1 or DH1 may be used
-        hcibuf[10] = 0xCC; // DM3, DH3, DM5, DH5 may be used
-        hcibuf[11] = 0x01; // Page repetition mode R1
-        hcibuf[12] = 0x00; // Reserved
-        hcibuf[13] = 0x00; // Clock offset
-        hcibuf[14] = 0x00; // Invalid clock offset
-        hcibuf[15] = 0x00; // Do not allow role switch
-
-        HCI_Command(hcibuf, 16);
-}
-
-void BTD::hci_pin_code_request_reply() {
-        hcibuf[0] = 0x0D; // HCI OCF = 0D
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x17; // parameter length 23
-        hcibuf[3] = disc_bdaddr[0]; // 6 octet bdaddr
-        hcibuf[4] = disc_bdaddr[1];
-        hcibuf[5] = disc_bdaddr[2];
-        hcibuf[6] = disc_bdaddr[3];
-        hcibuf[7] = disc_bdaddr[4];
-        hcibuf[8] = disc_bdaddr[5];
-        if(pairWithWii) {
-                hcibuf[9] = 6; // Pin length is the length of the Bluetooth address
-                if(pairWiiUsingSync) {
-#ifdef DEBUG_USB_HOST
-                        Notify(PSTR("\r\nParing with Wii controller via SYNC"), 0x80);
-#endif
-                        for(uint8_t i = 0; i < 6; i++)
-                                hcibuf[10 + i] = my_bdaddr[i]; // The pin is the Bluetooth dongles Bluetooth address backwards
-                } else {
-                        for(uint8_t i = 0; i < 6; i++)
-                                hcibuf[10 + i] = disc_bdaddr[i]; // The pin is the Wiimote's Bluetooth address backwards
-                }
-                for(uint8_t i = 16; i < 26; i++)
-                        hcibuf[i] = 0x00; // The rest should be 0
-        } else {
-                hcibuf[9] = strlen(btdPin); // Length of pin
-                uint8_t i;
-                for(i = 0; i < strlen(btdPin); i++) // The maximum size of the pin is 16
-                        hcibuf[i + 10] = btdPin[i];
-                for(; i < 16; i++)
-                        hcibuf[i + 10] = 0x00; // The rest should be 0
-        }
-
-        HCI_Command(hcibuf, 26);
-}
-
-void BTD::hci_pin_code_negative_request_reply() {
-        hcibuf[0] = 0x0E; // HCI OCF = 0E
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x06; // parameter length 6
-        hcibuf[3] = disc_bdaddr[0]; // 6 octet bdaddr
-        hcibuf[4] = disc_bdaddr[1];
-        hcibuf[5] = disc_bdaddr[2];
-        hcibuf[6] = disc_bdaddr[3];
-        hcibuf[7] = disc_bdaddr[4];
-        hcibuf[8] = disc_bdaddr[5];
-
-        HCI_Command(hcibuf, 9);
-}
-
-void BTD::hci_link_key_request_negative_reply() {
-        hcibuf[0] = 0x0C; // HCI OCF = 0C
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x06; // parameter length 6
-        hcibuf[3] = disc_bdaddr[0]; // 6 octet bdaddr
-        hcibuf[4] = disc_bdaddr[1];
-        hcibuf[5] = disc_bdaddr[2];
-        hcibuf[6] = disc_bdaddr[3];
-        hcibuf[7] = disc_bdaddr[4];
-        hcibuf[8] = disc_bdaddr[5];
-
-        HCI_Command(hcibuf, 9);
-}
-
-void BTD::hci_authentication_request() {
-        hcibuf[0] = 0x11; // HCI OCF = 11
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x02; // parameter length = 2
-        hcibuf[3] = (uint8_t)(hci_handle & 0xFF); //connection handle - low byte
-        hcibuf[4] = (uint8_t)((hci_handle >> 8) & 0x0F); //connection handle - high byte
-
-        HCI_Command(hcibuf, 5);
-}
-
-void BTD::hci_disconnect(uint16_t handle) { // This is called by the different services
-        hci_clear_flag(HCI_FLAG_DISCONNECT_COMPLETE);
-        hcibuf[0] = 0x06; // HCI OCF = 6
-        hcibuf[1] = 0x01 << 2; // HCI OGF = 1
-        hcibuf[2] = 0x03; // parameter length = 3
-        hcibuf[3] = (uint8_t)(handle & 0xFF); //connection handle - low byte
-        hcibuf[4] = (uint8_t)((handle >> 8) & 0x0F); //connection handle - high byte
-        hcibuf[5] = 0x13; // reason
-
-        HCI_Command(hcibuf, 6);
-}
-
-void BTD::hci_write_class_of_device() { // See http://bluetooth-pentest.narod.ru/software/bluetooth_class_of_device-service_generator.html
-        hcibuf[0] = 0x24; // HCI OCF = 24
-        hcibuf[1] = 0x03 << 2; // HCI OGF = 3
-        hcibuf[2] = 0x03; // parameter length = 3
-        hcibuf[3] = 0x04; // Robot
-        hcibuf[4] = 0x08; // Toy
-        hcibuf[5] = 0x00;
-
-        HCI_Command(hcibuf, 6);
-}
-/*******************************************************************
- *                                                                 *
- *                        HCI ACL Data Packet                      *
- *                                                                 *
- *   buf[0]          buf[1]          buf[2]          buf[3]
- *   0       4       8    11 12      16              24            31 MSB
- *  .-+-+-+-+-+-+-+-|-+-+-+-|-+-|-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-.
- *  |      HCI Handle       |PB |BC |       Data Total Length       |   HCI ACL Data Packet
- *  .-+-+-+-+-+-+-+-|-+-+-+-|-+-|-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-.
- *
- *   buf[4]          buf[5]          buf[6]          buf[7]
- *   0               8               16                            31 MSB
- *  .-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-.
- *  |            Length             |          Channel ID           |   Basic L2CAP header
- *  .-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-.
- *
- *   buf[8]          buf[9]          buf[10]         buf[11]
- *   0               8               16                            31 MSB
- *  .-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-.
- *  |     Code      |  Identifier   |            Length             |   Control frame (C-frame)
- *  .-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-.   (signaling packet format)
- */
-/************************************************************/
-/*                    L2CAP Commands                        */
-
-/************************************************************/
-void BTD::L2CAP_Command(uint16_t handle, uint8_t* data, uint8_t nbytes, uint8_t channelLow, uint8_t channelHigh) {
-        uint8_t buf[8 + nbytes];
-        buf[0] = (uint8_t)(handle & 0xff); // HCI handle with PB,BC flag
-        buf[1] = (uint8_t)(((handle >> 8) & 0x0f) | 0x20);
-        buf[2] = (uint8_t)((4 + nbytes) & 0xff); // HCI ACL total data length
-        buf[3] = (uint8_t)((4 + nbytes) >> 8);
-        buf[4] = (uint8_t)(nbytes & 0xff); // L2CAP header: Length
-        buf[5] = (uint8_t)(nbytes >> 8);
-        buf[6] = channelLow;
-        buf[7] = channelHigh;
-
-        for(uint16_t i = 0; i < nbytes; i++) // L2CAP C-frame
-                buf[8 + i] = data[i];
-
-        uint8_t rcode = pUsb->outTransfer(bAddress, epInfo[ BTD_DATAOUT_PIPE ].epAddr, (8 + nbytes), buf);
-        if(rcode) {
-                delay(100); // This small delay prevents it from overflowing if it fails
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nError sending L2CAP message: 0x"), 0x80);
-                D_PrintHex<uint8_t > (rcode, 0x80);
-                Notify(PSTR(" - Channel ID: "), 0x80);
-                D_PrintHex<uint8_t > (channelHigh, 0x80);
-                Notify(PSTR(" "), 0x80);
-                D_PrintHex<uint8_t > (channelLow, 0x80);
-#endif
-        }
-}
-
-void BTD::l2cap_connection_request(uint16_t handle, uint8_t rxid, uint8_t* scid, uint16_t psm) {
-        l2capoutbuf[0] = L2CAP_CMD_CONNECTION_REQUEST; // Code
-        l2capoutbuf[1] = rxid; // Identifier
-        l2capoutbuf[2] = 0x04; // Length
-        l2capoutbuf[3] = 0x00;
-        l2capoutbuf[4] = (uint8_t)(psm & 0xff); // PSM
-        l2capoutbuf[5] = (uint8_t)(psm >> 8);
-        l2capoutbuf[6] = scid[0]; // Source CID
-        l2capoutbuf[7] = scid[1];
-
-        L2CAP_Command(handle, l2capoutbuf, 8);
-}
-
-void BTD::l2cap_connection_response(uint16_t handle, uint8_t rxid, uint8_t* dcid, uint8_t* scid, uint8_t result) {
-        l2capoutbuf[0] = L2CAP_CMD_CONNECTION_RESPONSE; // Code
-        l2capoutbuf[1] = rxid; // Identifier
-        l2capoutbuf[2] = 0x08; // Length
-        l2capoutbuf[3] = 0x00;
-        l2capoutbuf[4] = dcid[0]; // Destination CID
-        l2capoutbuf[5] = dcid[1];
-        l2capoutbuf[6] = scid[0]; // Source CID
-        l2capoutbuf[7] = scid[1];
-        l2capoutbuf[8] = result; // Result: Pending or Success
-        l2capoutbuf[9] = 0x00;
-        l2capoutbuf[10] = 0x00; // No further information
-        l2capoutbuf[11] = 0x00;
-
-        L2CAP_Command(handle, l2capoutbuf, 12);
-}
-
-void BTD::l2cap_config_request(uint16_t handle, uint8_t rxid, uint8_t* dcid) {
-        l2capoutbuf[0] = L2CAP_CMD_CONFIG_REQUEST; // Code
-        l2capoutbuf[1] = rxid; // Identifier
-        l2capoutbuf[2] = 0x08; // Length
-        l2capoutbuf[3] = 0x00;
-        l2capoutbuf[4] = dcid[0]; // Destination CID
-        l2capoutbuf[5] = dcid[1];
-        l2capoutbuf[6] = 0x00; // Flags
-        l2capoutbuf[7] = 0x00;
-        l2capoutbuf[8] = 0x01; // Config Opt: type = MTU (Maximum Transmission Unit) - Hint
-        l2capoutbuf[9] = 0x02; // Config Opt: length
-        l2capoutbuf[10] = 0xFF; // MTU
-        l2capoutbuf[11] = 0xFF;
-
-        L2CAP_Command(handle, l2capoutbuf, 12);
-}
-
-void BTD::l2cap_config_response(uint16_t handle, uint8_t rxid, uint8_t* scid) {
-        l2capoutbuf[0] = L2CAP_CMD_CONFIG_RESPONSE; // Code
-        l2capoutbuf[1] = rxid; // Identifier
-        l2capoutbuf[2] = 0x0A; // Length
-        l2capoutbuf[3] = 0x00;
-        l2capoutbuf[4] = scid[0]; // Source CID
-        l2capoutbuf[5] = scid[1];
-        l2capoutbuf[6] = 0x00; // Flag
-        l2capoutbuf[7] = 0x00;
-        l2capoutbuf[8] = 0x00; // Result
-        l2capoutbuf[9] = 0x00;
-        l2capoutbuf[10] = 0x01; // Config
-        l2capoutbuf[11] = 0x02;
-        l2capoutbuf[12] = 0xA0;
-        l2capoutbuf[13] = 0x02;
-
-        L2CAP_Command(handle, l2capoutbuf, 14);
-}
-
-void BTD::l2cap_disconnection_request(uint16_t handle, uint8_t rxid, uint8_t* dcid, uint8_t* scid) {
-        l2capoutbuf[0] = L2CAP_CMD_DISCONNECT_REQUEST; // Code
-        l2capoutbuf[1] = rxid; // Identifier
-        l2capoutbuf[2] = 0x04; // Length
-        l2capoutbuf[3] = 0x00;
-        l2capoutbuf[4] = dcid[0];
-        l2capoutbuf[5] = dcid[1];
-        l2capoutbuf[6] = scid[0];
-        l2capoutbuf[7] = scid[1];
-
-        L2CAP_Command(handle, l2capoutbuf, 8);
-}
-
-void BTD::l2cap_disconnection_response(uint16_t handle, uint8_t rxid, uint8_t* dcid, uint8_t* scid) {
-        l2capoutbuf[0] = L2CAP_CMD_DISCONNECT_RESPONSE; // Code
-        l2capoutbuf[1] = rxid; // Identifier
-        l2capoutbuf[2] = 0x04; // Length
-        l2capoutbuf[3] = 0x00;
-        l2capoutbuf[4] = dcid[0];
-        l2capoutbuf[5] = dcid[1];
-        l2capoutbuf[6] = scid[0];
-        l2capoutbuf[7] = scid[1];
-
-        L2CAP_Command(handle, l2capoutbuf, 8);
-}
-
-void BTD::l2cap_information_response(uint16_t handle, uint8_t rxid, uint8_t infoTypeLow, uint8_t infoTypeHigh) {
-        l2capoutbuf[0] = L2CAP_CMD_INFORMATION_RESPONSE; // Code
-        l2capoutbuf[1] = rxid; // Identifier
-        l2capoutbuf[2] = 0x08; // Length
-        l2capoutbuf[3] = 0x00;
-        l2capoutbuf[4] = infoTypeLow;
-        l2capoutbuf[5] = infoTypeHigh;
-        l2capoutbuf[6] = 0x00; // Result = success
-        l2capoutbuf[7] = 0x00; // Result = success
-        l2capoutbuf[8] = 0x00;
-        l2capoutbuf[9] = 0x00;
-        l2capoutbuf[10] = 0x00;
-        l2capoutbuf[11] = 0x00;
-
-        L2CAP_Command(handle, l2capoutbuf, 12);
-}
-
-/* PS3 Commands - only set Bluetooth address is implemented in this library */
-void BTD::setBdaddr(uint8_t* bdaddr) {
-        /* Set the internal Bluetooth address */
-        uint8_t buf[8];
-        buf[0] = 0x01;
-        buf[1] = 0x00;
-
-        for(uint8_t i = 0; i < 6; i++)
-                buf[i + 2] = bdaddr[5 - i]; // Copy into buffer, has to be written reversed, so it is MSB first
-
-        // bmRequest = Host to device (0x00) | Class (0x20) | Interface (0x01) = 0x21, bRequest = Set Report (0x09), Report ID (0xF5), Report Type (Feature 0x03), interface (0x00), datalength, datalength, data
-        pUsb->ctrlReq(bAddress, epInfo[BTD_CONTROL_PIPE].epAddr, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, 0xF5, 0x03, 0x00, 8, 8, buf, NULL);
-}
-
-void BTD::setMoveBdaddr(uint8_t* bdaddr) {
-        /* Set the internal Bluetooth address */
-        uint8_t buf[11];
-        buf[0] = 0x05;
-        buf[7] = 0x10;
-        buf[8] = 0x01;
-        buf[9] = 0x02;
-        buf[10] = 0x12;
-
-        for(uint8_t i = 0; i < 6; i++)
-                buf[i + 1] = bdaddr[i];
-
-        // bmRequest = Host to device (0x00) | Class (0x20) | Interface (0x01) = 0x21, bRequest = Set Report (0x09), Report ID (0x05), Report Type (Feature 0x03), interface (0x00), datalength, datalength, data
-        pUsb->ctrlReq(bAddress, epInfo[BTD_CONTROL_PIPE].epAddr, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, 0x05, 0x03, 0x00, 11, 11, buf, NULL);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/BTD.h b/lib/usbhost/USB_Host_Shield_2.0/BTD.h
deleted file mode 100644
index 6549c30c98..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/BTD.h
+++ /dev/null
@@ -1,620 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _btd_h_
-#define _btd_h_
-
-#include "Usb.h"
-#include "hid.h"
-
-//PID and VID of the Sony PS3 devices
-#define PS3_VID                 0x054C  // Sony Corporation
-#define PS3_PID                 0x0268  // PS3 Controller DualShock 3
-#define PS3NAVIGATION_PID       0x042F  // Navigation controller
-#define PS3MOVE_PID             0x03D5  // Motion controller
-
-#define IOGEAR_GBU521_VID       0x0A5C // The IOGEAR GBU521 dongle does not presents itself correctly, so we have to check for it manually
-#define IOGEAR_GBU521_PID       0x21E8
-
-/* Bluetooth dongle data taken from descriptors */
-#define BULK_MAXPKTSIZE         64 // Max size for ACL data
-
-// Used in control endpoint header for HCI Commands
-#define bmREQ_HCI_OUT USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_DEVICE
-
-/* Bluetooth HCI states for hci_task() */
-#define HCI_INIT_STATE                  0
-#define HCI_RESET_STATE                 1
-#define HCI_CLASS_STATE                 2
-#define HCI_BDADDR_STATE                3
-#define HCI_LOCAL_VERSION_STATE         4
-#define HCI_SET_NAME_STATE              5
-#define HCI_CHECK_DEVICE_SERVICE        6
-
-#define HCI_INQUIRY_STATE               7 // These three states are only used if it should pair and connect to a device
-#define HCI_CONNECT_DEVICE_STATE        8
-#define HCI_CONNECTED_DEVICE_STATE      9
-
-#define HCI_SCANNING_STATE              10
-#define HCI_CONNECT_IN_STATE            11
-#define HCI_REMOTE_NAME_STATE           12
-#define HCI_CONNECTED_STATE             13
-#define HCI_DISABLE_SCAN_STATE          14
-#define HCI_DONE_STATE                  15
-#define HCI_DISCONNECT_STATE            16
-
-/* HCI event flags*/
-#define HCI_FLAG_CMD_COMPLETE           (1UL << 0)
-#define HCI_FLAG_CONNECT_COMPLETE       (1UL << 1)
-#define HCI_FLAG_DISCONNECT_COMPLETE    (1UL << 2)
-#define HCI_FLAG_REMOTE_NAME_COMPLETE   (1UL << 3)
-#define HCI_FLAG_INCOMING_REQUEST       (1UL << 4)
-#define HCI_FLAG_READ_BDADDR            (1UL << 5)
-#define HCI_FLAG_READ_VERSION           (1UL << 6)
-#define HCI_FLAG_DEVICE_FOUND           (1UL << 7)
-#define HCI_FLAG_CONNECT_EVENT          (1UL << 8)
-
-/* Macros for HCI event flag tests */
-#define hci_check_flag(flag) (hci_event_flag & (flag))
-#define hci_set_flag(flag) (hci_event_flag |= (flag))
-#define hci_clear_flag(flag) (hci_event_flag &= ~(flag))
-
-/* HCI Events managed */
-#define EV_INQUIRY_COMPLETE                             0x01
-#define EV_INQUIRY_RESULT                               0x02
-#define EV_CONNECT_COMPLETE                             0x03
-#define EV_INCOMING_CONNECT                             0x04
-#define EV_DISCONNECT_COMPLETE                          0x05
-#define EV_AUTHENTICATION_COMPLETE                      0x06
-#define EV_REMOTE_NAME_COMPLETE                         0x07
-#define EV_ENCRYPTION_CHANGE                            0x08
-#define EV_CHANGE_CONNECTION_LINK                       0x09
-#define EV_ROLE_CHANGED                                 0x12
-#define EV_NUM_COMPLETE_PKT                             0x13
-#define EV_PIN_CODE_REQUEST                             0x16
-#define EV_LINK_KEY_REQUEST                             0x17
-#define EV_LINK_KEY_NOTIFICATION                        0x18
-#define EV_DATA_BUFFER_OVERFLOW                         0x1A
-#define EV_MAX_SLOTS_CHANGE                             0x1B
-#define EV_READ_REMOTE_VERSION_INFORMATION_COMPLETE     0x0C
-#define EV_QOS_SETUP_COMPLETE                           0x0D
-#define EV_COMMAND_COMPLETE                             0x0E
-#define EV_COMMAND_STATUS                               0x0F
-#define EV_LOOPBACK_COMMAND                             0x19
-#define EV_PAGE_SCAN_REP_MODE                           0x20
-
-/* Bluetooth states for the different Bluetooth drivers */
-#define L2CAP_WAIT                      0
-#define L2CAP_DONE                      1
-
-/* Used for HID Control channel */
-#define L2CAP_CONTROL_CONNECT_REQUEST   2
-#define L2CAP_CONTROL_CONFIG_REQUEST    3
-#define L2CAP_CONTROL_SUCCESS           4
-#define L2CAP_CONTROL_DISCONNECT        5
-
-/* Used for HID Interrupt channel */
-#define L2CAP_INTERRUPT_SETUP           6
-#define L2CAP_INTERRUPT_CONNECT_REQUEST 7
-#define L2CAP_INTERRUPT_CONFIG_REQUEST  8
-#define L2CAP_INTERRUPT_DISCONNECT      9
-
-/* Used for SDP channel */
-#define L2CAP_SDP_WAIT                  10
-#define L2CAP_SDP_SUCCESS               11
-
-/* Used for RFCOMM channel */
-#define L2CAP_RFCOMM_WAIT               12
-#define L2CAP_RFCOMM_SUCCESS            13
-
-#define L2CAP_DISCONNECT_RESPONSE       14 // Used for both SDP and RFCOMM channel
-
-/* Bluetooth states used by some drivers */
-#define TURN_ON_LED                     17
-#define PS3_ENABLE_SIXAXIS              18
-#define WII_CHECK_MOTION_PLUS_STATE     19
-#define WII_CHECK_EXTENSION_STATE       20
-#define WII_INIT_MOTION_PLUS_STATE      21
-
-/* L2CAP event flags for HID Control channel */
-#define L2CAP_FLAG_CONNECTION_CONTROL_REQUEST           (1UL << 0)
-#define L2CAP_FLAG_CONFIG_CONTROL_SUCCESS               (1UL << 1)
-#define L2CAP_FLAG_CONTROL_CONNECTED                    (1UL << 2)
-#define L2CAP_FLAG_DISCONNECT_CONTROL_RESPONSE          (1UL << 3)
-
-/* L2CAP event flags for HID Interrupt channel */
-#define L2CAP_FLAG_CONNECTION_INTERRUPT_REQUEST         (1UL << 4)
-#define L2CAP_FLAG_CONFIG_INTERRUPT_SUCCESS             (1UL << 5)
-#define L2CAP_FLAG_INTERRUPT_CONNECTED                  (1UL << 6)
-#define L2CAP_FLAG_DISCONNECT_INTERRUPT_RESPONSE        (1UL << 7)
-
-/* L2CAP event flags for SDP channel */
-#define L2CAP_FLAG_CONNECTION_SDP_REQUEST               (1UL << 8)
-#define L2CAP_FLAG_CONFIG_SDP_SUCCESS                   (1UL << 9)
-#define L2CAP_FLAG_DISCONNECT_SDP_REQUEST               (1UL << 10)
-
-/* L2CAP event flags for RFCOMM channel */
-#define L2CAP_FLAG_CONNECTION_RFCOMM_REQUEST            (1UL << 11)
-#define L2CAP_FLAG_CONFIG_RFCOMM_SUCCESS                (1UL << 12)
-#define L2CAP_FLAG_DISCONNECT_RFCOMM_REQUEST            (1UL << 13)
-
-#define L2CAP_FLAG_DISCONNECT_RESPONSE                  (1UL << 14)
-
-/* Macros for L2CAP event flag tests */
-#define l2cap_check_flag(flag) (l2cap_event_flag & (flag))
-#define l2cap_set_flag(flag) (l2cap_event_flag |= (flag))
-#define l2cap_clear_flag(flag) (l2cap_event_flag &= ~(flag))
-
-/* L2CAP signaling commands */
-#define L2CAP_CMD_COMMAND_REJECT        0x01
-#define L2CAP_CMD_CONNECTION_REQUEST    0x02
-#define L2CAP_CMD_CONNECTION_RESPONSE   0x03
-#define L2CAP_CMD_CONFIG_REQUEST        0x04
-#define L2CAP_CMD_CONFIG_RESPONSE       0x05
-#define L2CAP_CMD_DISCONNECT_REQUEST    0x06
-#define L2CAP_CMD_DISCONNECT_RESPONSE   0x07
-#define L2CAP_CMD_INFORMATION_REQUEST   0x0A
-#define L2CAP_CMD_INFORMATION_RESPONSE  0x0B
-
-// Used For Connection Response - Remember to Include High Byte
-#define PENDING     0x01
-#define SUCCESSFUL  0x00
-
-/* Bluetooth L2CAP PSM - see http://www.bluetooth.org/Technical/AssignedNumbers/logical_link.htm */
-#define SDP_PSM         0x01 // Service Discovery Protocol PSM Value
-#define RFCOMM_PSM      0x03 // RFCOMM PSM Value
-#define HID_CTRL_PSM    0x11 // HID_Control PSM Value
-#define HID_INTR_PSM    0x13 // HID_Interrupt PSM Value
-
-// Used to determine if it is a Bluetooth dongle
-#define WI_SUBCLASS_RF      0x01 // RF Controller
-#define WI_PROTOCOL_BT      0x01 // Bluetooth Programming Interface
-
-#define BTD_MAX_ENDPOINTS   4
-#define BTD_NUM_SERVICES    4 // Max number of Bluetooth services - if you need more than 4 simply increase this number
-
-#define PAIR    1
-
-class BluetoothService;
-
-/**
- * The Bluetooth Dongle class will take care of all the USB communication
- * and then pass the data to the BluetoothService classes.
- */
-class BTD : public USBDeviceConfig, public UsbConfigXtracter {
-public:
-        /**
-         * Constructor for the BTD class.
-         * @param  p   Pointer to USB class instance.
-         */
-        BTD(USB *p);
-
-        /** @name USBDeviceConfig implementation */
-        /**
-         * Address assignment and basic initialization is done here.
-         * @param  parent   Hub number.
-         * @param  port     Port number on the hub.
-         * @param  lowspeed Speed of the device.
-         * @return          0 on success.
-         */
-        uint8_t ConfigureDevice(uint8_t parent, uint8_t port, bool lowspeed);
-        /**
-         * Initialize the Bluetooth dongle.
-         * @param  parent   Hub number.
-         * @param  port     Port number on the hub.
-         * @param  lowspeed Speed of the device.
-         * @return          0 on success.
-         */
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        /**
-         * Release the USB device.
-         * @return 0 on success.
-         */
-        uint8_t Release();
-        /**
-         * Poll the USB Input endpoints and run the state machines.
-         * @return 0 on success.
-         */
-        uint8_t Poll();
-
-        /**
-         * Get the device address.
-         * @return The device address.
-         */
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        /**
-         * Used to check if the dongle has been initialized.
-         * @return True if it's ready.
-         */
-        virtual bool isReady() {
-                return bPollEnable;
-        };
-
-        /**
-         * Used by the USB core to check what this driver support.
-         * @param  klass The device's USB class.
-         * @return       Returns true if the device's USB class matches this driver.
-         */
-        virtual bool DEVCLASSOK(uint8_t klass) {
-                return (klass == USB_CLASS_WIRELESS_CTRL);
-        };
-
-        /**
-         * Used by the USB core to check what this driver support.
-         * Used to set the Bluetooth address into the PS3 controllers.
-         * @param  vid The device's VID.
-         * @param  pid The device's PID.
-         * @return     Returns true if the device's VID and PID matches this driver.
-         */
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                if(vid == IOGEAR_GBU521_VID && pid == IOGEAR_GBU521_PID)
-                        return true;
-                if(my_bdaddr[0] != 0x00 || my_bdaddr[1] != 0x00 || my_bdaddr[2] != 0x00 || my_bdaddr[3] != 0x00 || my_bdaddr[4] != 0x00 || my_bdaddr[5] != 0x00) { // Check if Bluetooth address is set
-                        if(vid == PS3_VID && (pid == PS3_PID || pid == PS3NAVIGATION_PID || pid == PS3MOVE_PID))
-                                return true;
-                }
-                return false;
-        };
-        /**@}*/
-
-        /** @name UsbConfigXtracter implementation */
-        /**
-         * UsbConfigXtracter implementation, used to extract endpoint information.
-         * @param conf  Configuration value.
-         * @param iface Interface number.
-         * @param alt   Alternate setting.
-         * @param proto Interface Protocol.
-         * @param ep    Endpoint Descriptor.
-         */
-        void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep);
-        /**@}*/
-
-        /** Disconnects both the L2CAP Channel and the HCI Connection for all Bluetooth services. */
-        void disconnect();
-
-        /**
-         * Register Bluetooth dongle members/services.
-         * @param  pService Pointer to BluetoothService class instance.
-         * @return          The service ID on success or -1 on fail.
-         */
-        int8_t registerBluetoothService(BluetoothService *pService) {
-                for(uint8_t i = 0; i < BTD_NUM_SERVICES; i++) {
-                        if(!btService[i]) {
-                                btService[i] = pService;
-                                return i; // Return ID
-                        }
-                }
-                return -1; // Error registering BluetoothService
-        };
-
-        /** @name HCI Commands */
-        /**
-         * Used to send a HCI Command.
-         * @param data   Data to send.
-         * @param nbytes Number of bytes to send.
-         */
-        void HCI_Command(uint8_t* data, uint16_t nbytes);
-        /** Reset the Bluetooth dongle. */
-        void hci_reset();
-        /** Read the Bluetooth address of the dongle. */
-        void hci_read_bdaddr();
-        /** Read the HCI Version of the Bluetooth dongle. */
-        void hci_read_local_version_information();
-        /**
-         * Set the local name of the Bluetooth dongle.
-         * @param name Desired name.
-         */
-        void hci_set_local_name(const char* name);
-        /** Enable visibility to other Bluetooth devices. */
-        void hci_write_scan_enable();
-        /** Disable visibility to other Bluetooth devices. */
-        void hci_write_scan_disable();
-        /** Read the remote devices name. */
-        void hci_remote_name();
-        /** Accept the connection with the Bluetooth device. */
-        void hci_accept_connection();
-        /**
-         * Disconnect the HCI connection.
-         * @param handle The HCI Handle for the connection.
-         */
-        void hci_disconnect(uint16_t handle);
-        /**
-         * Respond with the pin for the connection.
-         * The pin is automatically set for the Wii library,
-         * but can be customized for the SPP library.
-         */
-        void hci_pin_code_request_reply();
-        /** Respons when no pin was set. */
-        void hci_pin_code_negative_request_reply();
-        /**
-         * Command is used to reply to a Link Key Request event from the BR/EDR Controller
-         * if the Host does not have a stored Link Key for the connection.
-         */
-        void hci_link_key_request_negative_reply();
-        /** Used to try to authenticate with the remote device. */
-        void hci_authentication_request();
-        /** Start a HCI inquiry. */
-        void hci_inquiry();
-        /** Cancel a HCI inquiry. */
-        void hci_inquiry_cancel();
-        /** Connect to last device communicated with. */
-        void hci_connect();
-        /**
-         * Connect to device.
-         * @param bdaddr Bluetooth address of the device.
-         */
-        void hci_connect(uint8_t *bdaddr);
-        /** Used to a set the class of the device. */
-        void hci_write_class_of_device();
-        /**@}*/
-
-        /** @name L2CAP Commands */
-        /**
-         * Used to send L2CAP Commands.
-         * @param handle      HCI Handle.
-         * @param data        Data to send.
-         * @param nbytes      Number of bytes to send.
-         * @param channelLow,channelHigh  Low and high byte of channel to send to.
-         * If argument is omitted then the Standard L2CAP header: Channel ID (0x01) for ACL-U will be used.
-         */
-        void L2CAP_Command(uint16_t handle, uint8_t* data, uint8_t nbytes, uint8_t channelLow = 0x01, uint8_t channelHigh = 0x00);
-        /**
-         * L2CAP Connection Request.
-         * @param handle HCI handle.
-         * @param rxid   Identifier.
-         * @param scid   Source Channel Identifier.
-         * @param psm    Protocol/Service Multiplexer - see: https://www.bluetooth.org/Technical/AssignedNumbers/logical_link.htm.
-         */
-        void l2cap_connection_request(uint16_t handle, uint8_t rxid, uint8_t* scid, uint16_t psm);
-        /**
-         * L2CAP Connection Response.
-         * @param handle HCI handle.
-         * @param rxid   Identifier.
-         * @param dcid   Destination Channel Identifier.
-         * @param scid   Source Channel Identifier.
-         * @param result Result - First send ::PENDING and then ::SUCCESSFUL.
-         */
-        void l2cap_connection_response(uint16_t handle, uint8_t rxid, uint8_t* dcid, uint8_t* scid, uint8_t result);
-        /**
-         * L2CAP Config Request.
-         * @param handle HCI Handle.
-         * @param rxid   Identifier.
-         * @param dcid   Destination Channel Identifier.
-         */
-        void l2cap_config_request(uint16_t handle, uint8_t rxid, uint8_t* dcid);
-        /**
-         * L2CAP Config Response.
-         * @param handle HCI Handle.
-         * @param rxid   Identifier.
-         * @param scid   Source Channel Identifier.
-         */
-        void l2cap_config_response(uint16_t handle, uint8_t rxid, uint8_t* scid);
-        /**
-         * L2CAP Disconnection Request.
-         * @param handle HCI Handle.
-         * @param rxid   Identifier.
-         * @param dcid   Device Channel Identifier.
-         * @param scid   Source Channel Identifier.
-         */
-        void l2cap_disconnection_request(uint16_t handle, uint8_t rxid, uint8_t* dcid, uint8_t* scid);
-        /**
-         * L2CAP Disconnection Response.
-         * @param handle HCI Handle.
-         * @param rxid   Identifier.
-         * @param dcid   Device Channel Identifier.
-         * @param scid   Source Channel Identifier.
-         */
-        void l2cap_disconnection_response(uint16_t handle, uint8_t rxid, uint8_t* dcid, uint8_t* scid);
-        /**
-         * L2CAP Information Response.
-         * @param handle       HCI Handle.
-         * @param rxid         Identifier.
-         * @param infoTypeLow,infoTypeHigh  Infotype.
-         */
-        void l2cap_information_response(uint16_t handle, uint8_t rxid, uint8_t infoTypeLow, uint8_t infoTypeHigh);
-        /**@}*/
-
-        /** Use this to see if it is waiting for a incoming connection. */
-        bool watingForConnection;
-        /** This is used by the service to know when to store the device information. */
-        bool l2capConnectionClaimed;
-        /** This is used by the SPP library to claim the current SDP incoming request. */
-        bool sdpConnectionClaimed;
-        /** This is used by the SPP library to claim the current RFCOMM incoming request. */
-        bool rfcommConnectionClaimed;
-
-        /** The name you wish to make the dongle show up as. It is set automatically by the SPP library. */
-        const char* btdName;
-        /** The pin you wish to make the dongle use for authentication. It is set automatically by the SPP and BTHID library. */
-        const char* btdPin;
-
-        /** The bluetooth dongles Bluetooth address. */
-        uint8_t my_bdaddr[6];
-        /** HCI handle for the last connection. */
-        uint16_t hci_handle;
-        /** Last incoming devices Bluetooth address. */
-        uint8_t disc_bdaddr[6];
-        /** First 30 chars of last remote name. */
-        char remote_name[30];
-        /**
-         * The supported HCI Version read from the Bluetooth dongle.
-         * Used by the PS3BT library to check the HCI Version of the Bluetooth dongle,
-         * it should be at least 3 to work properly with the library.
-         */
-        uint8_t hci_version;
-
-        /** Call this function to pair with a Wiimote */
-        void pairWithWiimote() {
-                pairWithWii = true;
-                hci_state = HCI_CHECK_DEVICE_SERVICE;
-        };
-        /** Used to only send the ACL data to the Wiimote. */
-        bool connectToWii;
-        /** True if a Wiimote is connecting. */
-        bool incomingWii;
-        /** True when it should pair with a Wiimote. */
-        bool pairWithWii;
-        /** True if it's the new Wiimote with the Motion Plus Inside or a Wii U Pro Controller. */
-        bool motionPlusInside;
-        /** True if it's a Wii U Pro Controller. */
-        bool wiiUProController;
-
-        /** Call this function to pair with a Wiimote */
-        void pairWithHID() {
-                pairWithHIDDevice = true;
-                hci_state = HCI_CHECK_DEVICE_SERVICE;
-        };
-        /** Used to only send the ACL data to the Wiimote. */
-        bool connectToHIDDevice;
-        /** True if a Wiimote is connecting. */
-        bool incomingHIDDevice;
-        /** True when it should pair with a device like a mouse or keyboard. */
-        bool pairWithHIDDevice;
-
-        /**
-         * Read the poll interval taken from the endpoint descriptors.
-         * @return The poll interval in ms.
-         */
-        uint8_t readPollInterval() {
-                return pollInterval;
-        };
-
-protected:
-        /** Pointer to USB class instance. */
-        USB *pUsb;
-        /** Device address. */
-        uint8_t bAddress;
-        /** Endpoint info structure. */
-        EpInfo epInfo[BTD_MAX_ENDPOINTS];
-
-        /** Configuration number. */
-        uint8_t bConfNum;
-        /** Total number of endpoints in the configuration. */
-        uint8_t bNumEP;
-        /** Next poll time based on poll interval taken from the USB descriptor. */
-        uint32_t qNextPollTime;
-
-        /** Bluetooth dongle control endpoint. */
-        static const uint8_t BTD_CONTROL_PIPE;
-        /** HCI event endpoint index. */
-        static const uint8_t BTD_EVENT_PIPE;
-        /** ACL In endpoint index. */
-        static const uint8_t BTD_DATAIN_PIPE;
-        /** ACL Out endpoint index. */
-        static const uint8_t BTD_DATAOUT_PIPE;
-
-        /**
-         * Used to print the USB Endpoint Descriptor.
-         * @param ep_ptr Pointer to USB Endpoint Descriptor.
-         */
-        void PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr);
-
-private:
-        void Initialize(); // Set all variables, endpoint structs etc. to default values
-        BluetoothService *btService[BTD_NUM_SERVICES];
-
-        uint16_t PID, VID; // PID and VID of device connected
-
-        uint8_t pollInterval;
-        bool bPollEnable;
-
-        bool pairWiiUsingSync; // True if paring was done using the Wii SYNC button.
-        bool checkRemoteName; // Used to check remote device's name before connecting.
-        bool incomingPS4; // True if a PS4 controller is connecting
-        uint8_t classOfDevice[3]; // Class of device of last device
-
-        /* Variables used by high level HCI task */
-        uint8_t hci_state; // Current state of Bluetooth HCI connection
-        uint16_t hci_counter; // Counter used for Bluetooth HCI reset loops
-        uint16_t hci_num_reset_loops; // This value indicate how many times it should read before trying to reset
-        uint16_t hci_event_flag; // HCI flags of received Bluetooth events
-        uint8_t inquiry_counter;
-
-        uint8_t hcibuf[BULK_MAXPKTSIZE]; // General purpose buffer for HCI data
-        uint8_t l2capinbuf[BULK_MAXPKTSIZE]; // General purpose buffer for L2CAP in data
-        uint8_t l2capoutbuf[14]; // General purpose buffer for L2CAP out data
-
-        /* State machines */
-        void HCI_event_task(); // Poll the HCI event pipe
-        void HCI_task(); // HCI state machine
-        void ACL_event_task(); // ACL input pipe
-
-        /* Used to set the Bluetooth Address internally to the PS3 Controllers */
-        void setBdaddr(uint8_t* BDADDR);
-        void setMoveBdaddr(uint8_t* BDADDR);
-};
-
-/** All Bluetooth services should inherit this class. */
-class BluetoothService {
-public:
-        BluetoothService(BTD *p) : pBtd(p) {
-                if(pBtd)
-                        pBtd->registerBluetoothService(this); // Register it as a Bluetooth service
-        };
-        /**
-         * Used to pass acldata to the Bluetooth service.
-         * @param ACLData Pointer to the incoming acldata.
-         */
-        virtual void ACLData(uint8_t* ACLData) = 0;
-        /** Used to run the different state machines in the Bluetooth service. */
-        virtual void Run() = 0;
-        /** Used to reset the Bluetooth service. */
-        virtual void Reset() = 0;
-        /** Used to disconnect both the L2CAP Channel and the HCI Connection for the Bluetooth service. */
-        virtual void disconnect() = 0;
-
-        /**
-         * Used to call your own function when the device is successfully initialized.
-         * @param funcOnInit Function to call.
-         */
-        void attachOnInit(void (*funcOnInit)(void)) {
-                pFuncOnInit = funcOnInit; // TODO: This really belong in a class of it's own as it is repeated several times
-        };
-
-protected:
-        /**
-         * Called when a device is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        virtual void onInit() = 0;
-
-        /** Used to check if the incoming L2CAP data matches the HCI Handle */
-        bool checkHciHandle(uint8_t *buf, uint16_t handle) {
-                return (buf[0] == (handle & 0xFF)) && (buf[1] == ((handle >> 8) | 0x20));
-        }
-
-        /** Pointer to function called in onInit(). */
-        void (*pFuncOnInit)(void);
-
-        /** Pointer to BTD instance. */
-        BTD *pBtd;
-
-        /** The HCI Handle for the connection. */
-        uint16_t hci_handle;
-
-        /** L2CAP flags of received Bluetooth events. */
-        uint32_t l2cap_event_flag;
-
-        /** Identifier for L2CAP commands. */
-        uint8_t identifier;
-};
-
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/BTHID.cpp b/lib/usbhost/USB_Host_Shield_2.0/BTHID.cpp
deleted file mode 100644
index bfa9202c39..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/BTHID.cpp
+++ /dev/null
@@ -1,399 +0,0 @@
-/* Copyright (C) 2013 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#include "BTHID.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-//#define PRINTREPORT // Uncomment to print the report send by the HID device
-
-BTHID::BTHID(BTD *p, bool pair, const char *pin) :
-BluetoothService(p), // Pointer to USB class instance - mandatory
-protocolMode(HID_BOOT_PROTOCOL) {
-        for(uint8_t i = 0; i < NUM_PARSERS; i++)
-                pRptParser[i] = NULL;
-
-        pBtd->pairWithHIDDevice = pair;
-        pBtd->btdPin = pin;
-
-        /* Set device cid for the control and intterrupt channelse - LSB */
-        control_dcid[0] = 0x70; // 0x0070
-        control_dcid[1] = 0x00;
-        interrupt_dcid[0] = 0x71; // 0x0071
-        interrupt_dcid[1] = 0x00;
-
-        Reset();
-}
-
-void BTHID::Reset() {
-        connected = false;
-        activeConnection = false;
-        l2cap_event_flag = 0; // Reset flags
-        l2cap_state = L2CAP_WAIT;
-        ResetBTHID();
-}
-
-void BTHID::disconnect() { // Use this void to disconnect the device
-        // First the HID interrupt channel has to be disconnected, then the HID control channel and finally the HCI connection
-        pBtd->l2cap_disconnection_request(hci_handle, ++identifier, interrupt_scid, interrupt_dcid);
-        Reset();
-        l2cap_state = L2CAP_INTERRUPT_DISCONNECT;
-}
-
-void BTHID::ACLData(uint8_t* l2capinbuf) {
-        if(!pBtd->l2capConnectionClaimed && pBtd->incomingHIDDevice && !connected && !activeConnection) {
-                if(l2capinbuf[8] == L2CAP_CMD_CONNECTION_REQUEST) {
-                        if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == HID_CTRL_PSM) {
-                                pBtd->incomingHIDDevice = false;
-                                pBtd->l2capConnectionClaimed = true; // Claim that the incoming connection belongs to this service
-                                activeConnection = true;
-                                hci_handle = pBtd->hci_handle; // Store the HCI Handle for the connection
-                                l2cap_state = L2CAP_WAIT;
-                        }
-                }
-        }
-
-        if(checkHciHandle(l2capinbuf, hci_handle)) { // acl_handle_ok
-                if((l2capinbuf[6] | (l2capinbuf[7] << 8)) == 0x0001U) { // l2cap_control - Channel ID for ACL-U
-                        if(l2capinbuf[8] == L2CAP_CMD_COMMAND_REJECT) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nL2CAP Command Rejected - Reason: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[12], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[17], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[16], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[15], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-#endif
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONNECTION_RESPONSE) {
-                                if(((l2capinbuf[16] | (l2capinbuf[17] << 8)) == 0x0000) && ((l2capinbuf[18] | (l2capinbuf[19] << 8)) == SUCCESSFUL)) { // Success
-                                        if(l2capinbuf[14] == control_dcid[0] && l2capinbuf[15] == control_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Control Connection Complete"), 0x80);
-                                                identifier = l2capinbuf[9];
-                                                control_scid[0] = l2capinbuf[12];
-                                                control_scid[1] = l2capinbuf[13];
-                                                l2cap_set_flag(L2CAP_FLAG_CONTROL_CONNECTED);
-                                        } else if(l2capinbuf[14] == interrupt_dcid[0] && l2capinbuf[15] == interrupt_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Interrupt Connection Complete"), 0x80);
-                                                identifier = l2capinbuf[9];
-                                                interrupt_scid[0] = l2capinbuf[12];
-                                                interrupt_scid[1] = l2capinbuf[13];
-                                                l2cap_set_flag(L2CAP_FLAG_INTERRUPT_CONNECTED);
-                                        }
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONNECTION_REQUEST) {
-#ifdef EXTRADEBUG
-                                Notify(PSTR("\r\nL2CAP Connection Request - PSM: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[12], 0x80);
-                                Notify(PSTR(" SCID: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[15], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-                                Notify(PSTR(" Identifier: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[9], 0x80);
-#endif
-                                if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == HID_CTRL_PSM) {
-                                        identifier = l2capinbuf[9];
-                                        control_scid[0] = l2capinbuf[14];
-                                        control_scid[1] = l2capinbuf[15];
-                                        l2cap_set_flag(L2CAP_FLAG_CONNECTION_CONTROL_REQUEST);
-                                } else if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == HID_INTR_PSM) {
-                                        identifier = l2capinbuf[9];
-                                        interrupt_scid[0] = l2capinbuf[14];
-                                        interrupt_scid[1] = l2capinbuf[15];
-                                        l2cap_set_flag(L2CAP_FLAG_CONNECTION_INTERRUPT_REQUEST);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONFIG_RESPONSE) {
-                                if((l2capinbuf[16] | (l2capinbuf[17] << 8)) == 0x0000) { // Success
-                                        if(l2capinbuf[12] == control_dcid[0] && l2capinbuf[13] == control_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Control Configuration Complete"), 0x80);
-                                                identifier = l2capinbuf[9];
-                                                l2cap_set_flag(L2CAP_FLAG_CONFIG_CONTROL_SUCCESS);
-                                        } else if(l2capinbuf[12] == interrupt_dcid[0] && l2capinbuf[13] == interrupt_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Interrupt Configuration Complete"), 0x80);
-                                                identifier = l2capinbuf[9];
-                                                l2cap_set_flag(L2CAP_FLAG_CONFIG_INTERRUPT_SUCCESS);
-                                        }
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONFIG_REQUEST) {
-                                if(l2capinbuf[12] == control_dcid[0] && l2capinbuf[13] == control_dcid[1]) {
-                                        //Notify(PSTR("\r\nHID Control Configuration Request"), 0x80);
-                                        pBtd->l2cap_config_response(hci_handle, l2capinbuf[9], control_scid);
-                                } else if(l2capinbuf[12] == interrupt_dcid[0] && l2capinbuf[13] == interrupt_dcid[1]) {
-                                        //Notify(PSTR("\r\nHID Interrupt Configuration Request"), 0x80);
-                                        pBtd->l2cap_config_response(hci_handle, l2capinbuf[9], interrupt_scid);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_DISCONNECT_REQUEST) {
-                                if(l2capinbuf[12] == control_dcid[0] && l2capinbuf[13] == control_dcid[1]) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nDisconnect Request: Control Channel"), 0x80);
-#endif
-                                        identifier = l2capinbuf[9];
-                                        pBtd->l2cap_disconnection_response(hci_handle, identifier, control_dcid, control_scid);
-                                        Reset();
-                                } else if(l2capinbuf[12] == interrupt_dcid[0] && l2capinbuf[13] == interrupt_dcid[1]) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nDisconnect Request: Interrupt Channel"), 0x80);
-#endif
-                                        identifier = l2capinbuf[9];
-                                        pBtd->l2cap_disconnection_response(hci_handle, identifier, interrupt_dcid, interrupt_scid);
-                                        Reset();
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_DISCONNECT_RESPONSE) {
-                                if(l2capinbuf[12] == control_scid[0] && l2capinbuf[13] == control_scid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Response: Control Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_CONTROL_RESPONSE);
-                                } else if(l2capinbuf[12] == interrupt_scid[0] && l2capinbuf[13] == interrupt_scid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Response: Interrupt Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_INTERRUPT_RESPONSE);
-                                }
-                        }
-#ifdef EXTRADEBUG
-                        else {
-                                identifier = l2capinbuf[9];
-                                Notify(PSTR("\r\nL2CAP Unknown Signaling Command: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[8], 0x80);
-                        }
-#endif
-                } else if(l2capinbuf[6] == interrupt_dcid[0] && l2capinbuf[7] == interrupt_dcid[1]) { // l2cap_interrupt
-#ifdef PRINTREPORT
-                        Notify(PSTR("\r\nL2CAP Interrupt: "), 0x80);
-                        for(uint16_t i = 0; i < ((uint16_t)l2capinbuf[5] << 8 | l2capinbuf[4]); i++) {
-                                D_PrintHex<uint8_t > (l2capinbuf[i + 8], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                        }
-#endif
-                        if(l2capinbuf[8] == 0xA1) { // HID_THDR_DATA_INPUT
-                                uint16_t length = ((uint16_t)l2capinbuf[5] << 8 | l2capinbuf[4]);
-                                ParseBTHIDData((uint8_t)(length - 1), &l2capinbuf[9]);
-
-                                switch(l2capinbuf[9]) {
-                                        case 0x01: // Keyboard or Joystick events
-                                                if(pRptParser[KEYBOARD_PARSER_ID])
-                                                        pRptParser[KEYBOARD_PARSER_ID]->Parse(reinterpret_cast<HID *>(this), 0, (uint8_t)(length - 2), &l2capinbuf[10]); // Use reinterpret_cast again to extract the instance
-                                                break;
-
-                                        case 0x02: // Mouse events
-                                                if(pRptParser[MOUSE_PARSER_ID])
-                                                        pRptParser[MOUSE_PARSER_ID]->Parse(reinterpret_cast<HID *>(this), 0, (uint8_t)(length - 2), &l2capinbuf[10]); // Use reinterpret_cast again to extract the instance
-                                                break;
-#ifdef EXTRADEBUG
-                                        default:
-                                                Notify(PSTR("\r\nUnknown Report type: "), 0x80);
-                                                D_PrintHex<uint8_t > (l2capinbuf[9], 0x80);
-                                                break;
-#endif
-                                }
-                        }
-                } else if(l2capinbuf[6] == control_dcid[0] && l2capinbuf[7] == control_dcid[1]) { // l2cap_control
-#ifdef PRINTREPORT
-                        Notify(PSTR("\r\nL2CAP Control: "), 0x80);
-                        for(uint16_t i = 0; i < ((uint16_t)l2capinbuf[5] << 8 | l2capinbuf[4]); i++) {
-                                D_PrintHex<uint8_t > (l2capinbuf[i + 8], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                        }
-#endif
-                }
-#ifdef EXTRADEBUG
-                else {
-                        Notify(PSTR("\r\nUnsupported L2CAP Data - Channel ID: "), 0x80);
-                        D_PrintHex<uint8_t > (l2capinbuf[7], 0x80);
-                        Notify(PSTR(" "), 0x80);
-                        D_PrintHex<uint8_t > (l2capinbuf[6], 0x80);
-
-                        Notify(PSTR("\r\nData: "), 0x80);
-                        Notify(PSTR("\r\n"), 0x80);
-                        for(uint16_t i = 0; i < ((uint16_t)l2capinbuf[5] << 8 | l2capinbuf[4]); i++) {
-                                D_PrintHex<uint8_t > (l2capinbuf[i + 8], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                        }
-                }
-#endif
-                L2CAP_task();
-        }
-}
-
-void BTHID::L2CAP_task() {
-        switch(l2cap_state) {
-                        /* These states are used if the HID device is the host */
-                case L2CAP_CONTROL_SUCCESS:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_CONTROL_SUCCESS)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Control Successfully Configured"), 0x80);
-#endif
-                                setProtocol(); // Set protocol before establishing HID interrupt channel
-                                l2cap_state = L2CAP_INTERRUPT_SETUP;
-                        }
-                        break;
-
-                case L2CAP_INTERRUPT_SETUP:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONNECTION_INTERRUPT_REQUEST)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Interrupt Incoming Connection Request"), 0x80);
-#endif
-                                pBtd->l2cap_connection_response(hci_handle, identifier, interrupt_dcid, interrupt_scid, PENDING);
-                                delay(1);
-                                pBtd->l2cap_connection_response(hci_handle, identifier, interrupt_dcid, interrupt_scid, SUCCESSFUL);
-                                identifier++;
-                                delay(1);
-                                pBtd->l2cap_config_request(hci_handle, identifier, interrupt_scid);
-
-                                l2cap_state = L2CAP_INTERRUPT_CONFIG_REQUEST;
-                        }
-                        break;
-
-                        /* These states are used if the Arduino is the host */
-                case L2CAP_CONTROL_CONNECT_REQUEST:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONTROL_CONNECTED)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSend HID Control Config Request"), 0x80);
-#endif
-                                identifier++;
-                                pBtd->l2cap_config_request(hci_handle, identifier, control_scid);
-                                l2cap_state = L2CAP_CONTROL_CONFIG_REQUEST;
-                        }
-                        break;
-
-                case L2CAP_CONTROL_CONFIG_REQUEST:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_CONTROL_SUCCESS)) {
-                                setProtocol(); // Set protocol before establishing HID interrupt channel
-                                delay(1); // Short delay between commands - just to be sure
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSend HID Interrupt Connection Request"), 0x80);
-#endif
-                                identifier++;
-                                pBtd->l2cap_connection_request(hci_handle, identifier, interrupt_dcid, HID_INTR_PSM);
-                                l2cap_state = L2CAP_INTERRUPT_CONNECT_REQUEST;
-                        }
-                        break;
-
-                case L2CAP_INTERRUPT_CONNECT_REQUEST:
-                        if(l2cap_check_flag(L2CAP_FLAG_INTERRUPT_CONNECTED)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSend HID Interrupt Config Request"), 0x80);
-#endif
-                                identifier++;
-                                pBtd->l2cap_config_request(hci_handle, identifier, interrupt_scid);
-                                l2cap_state = L2CAP_INTERRUPT_CONFIG_REQUEST;
-                        }
-                        break;
-
-                case L2CAP_INTERRUPT_CONFIG_REQUEST:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_INTERRUPT_SUCCESS)) { // Now the HID channels is established
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Channels Established"), 0x80);
-#endif
-                                pBtd->connectToHIDDevice = false;
-                                pBtd->pairWithHIDDevice = false;
-                                connected = true;
-                                onInit();
-                                l2cap_state = L2CAP_DONE;
-                        }
-                        break;
-
-                case L2CAP_DONE:
-                        break;
-
-                case L2CAP_INTERRUPT_DISCONNECT:
-                        if(l2cap_check_flag(L2CAP_FLAG_DISCONNECT_INTERRUPT_RESPONSE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nDisconnected Interrupt Channel"), 0x80);
-#endif
-                                identifier++;
-                                pBtd->l2cap_disconnection_request(hci_handle, identifier, control_scid, control_dcid);
-                                l2cap_state = L2CAP_CONTROL_DISCONNECT;
-                        }
-                        break;
-
-                case L2CAP_CONTROL_DISCONNECT:
-                        if(l2cap_check_flag(L2CAP_FLAG_DISCONNECT_CONTROL_RESPONSE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nDisconnected Control Channel"), 0x80);
-#endif
-                                pBtd->hci_disconnect(hci_handle);
-                                hci_handle = -1; // Reset handle
-                                l2cap_event_flag = 0; // Reset flags
-                                l2cap_state = L2CAP_WAIT;
-                        }
-                        break;
-        }
-}
-
-void BTHID::Run() {
-        switch(l2cap_state) {
-                case L2CAP_WAIT:
-                        if(pBtd->connectToHIDDevice && !pBtd->l2capConnectionClaimed && !connected && !activeConnection) {
-                                pBtd->l2capConnectionClaimed = true;
-                                activeConnection = true;
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSend HID Control Connection Request"), 0x80);
-#endif
-                                hci_handle = pBtd->hci_handle; // Store the HCI Handle for the connection
-                                l2cap_event_flag = 0; // Reset flags
-                                identifier = 0;
-                                pBtd->l2cap_connection_request(hci_handle, identifier, control_dcid, HID_CTRL_PSM);
-                                l2cap_state = L2CAP_CONTROL_CONNECT_REQUEST;
-                        } else if(l2cap_check_flag(L2CAP_FLAG_CONNECTION_CONTROL_REQUEST)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Control Incoming Connection Request"), 0x80);
-#endif
-                                pBtd->l2cap_connection_response(hci_handle, identifier, control_dcid, control_scid, PENDING);
-                                delay(1);
-                                pBtd->l2cap_connection_response(hci_handle, identifier, control_dcid, control_scid, SUCCESSFUL);
-                                identifier++;
-                                delay(1);
-                                pBtd->l2cap_config_request(hci_handle, identifier, control_scid);
-                                l2cap_state = L2CAP_CONTROL_SUCCESS;
-                        }
-                        break;
-        }
-}
-
-/************************************************************/
-/*                    HID Commands                          */
-
-/************************************************************/
-void BTHID::setProtocol() {
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nSet protocol mode: "), 0x80);
-        D_PrintHex<uint8_t > (protocolMode, 0x80);
-#endif
-        if (protocolMode != HID_BOOT_PROTOCOL && protocolMode != HID_RPT_PROTOCOL) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nNot a valid protocol mode. Using Boot protocol instead."), 0x80);
-#endif
-                protocolMode = HID_BOOT_PROTOCOL; // Use Boot Protocol by default
-        }
-        uint8_t command = 0x70 | protocolMode; // Set Protocol, see Bluetooth HID specs page 33
-        pBtd->L2CAP_Command(hci_handle, &command, 1, control_scid[0], control_scid[1]);
-}
-
-void BTHID::setLeds(uint8_t data) {
-        uint8_t buf[3];
-        buf[0] = 0xA2; // HID BT DATA_request (0xA0) | Report Type (Output 0x02)
-        buf[1] = 0x01; // Report ID
-        buf[2] = data;
-        pBtd->L2CAP_Command(hci_handle, buf, 3, interrupt_scid[0], interrupt_scid[1]);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/BTHID.h b/lib/usbhost/USB_Host_Shield_2.0/BTHID.h
deleted file mode 100644
index 1a7d8687c7..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/BTHID.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright (C) 2013 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _bthid_h_
-#define _bthid_h_
-
-#include "BTD.h"
-#include "hidboot.h"
-
-#define KEYBOARD_PARSER_ID      0
-#define MOUSE_PARSER_ID         1
-#define NUM_PARSERS             2
-
-/** This BluetoothService class implements support for Bluetooth HID devices. */
-class BTHID : public BluetoothService {
-public:
-        /**
-         * Constructor for the BTHID class.
-         * @param  p   Pointer to the BTD class instance.
-         * @param  pair   Set this to true in order to pair with the device. If the argument is omitted then it will not pair with it. One can use ::PAIR to set it to true.
-         * @param  pin   Write the pin to BTD#btdPin. If argument is omitted, then "0000" will be used.
-         */
-        BTHID(BTD *p, bool pair = false, const char *pin = "0000");
-
-        /** @name BluetoothService implementation */
-        /** Used this to disconnect the devices. */
-        void disconnect();
-        /**@}*/
-
-        /**
-         * Get HIDReportParser.
-         * @param  id ID of parser.
-         * @return    Returns the corresponding HIDReportParser. Returns NULL if id is not valid.
-         */
-        HIDReportParser *GetReportParser(uint8_t id) {
-                if (id >= NUM_PARSERS)
-                        return NULL;
-                return pRptParser[id];
-        };
-
-        /**
-         * Set HIDReportParser to be used.
-         * @param  id  Id of parser.
-         * @param  prs Pointer to HIDReportParser.
-         * @return     Returns true if the HIDReportParser is set. False otherwise.
-         */
-        bool SetReportParser(uint8_t id, HIDReportParser *prs) {
-                if (id >= NUM_PARSERS)
-                        return false;
-                pRptParser[id] = prs;
-                return true;
-        };
-
-        /**
-         * Set HID protocol mode.
-         * @param mode HID protocol to use. Either HID_BOOT_PROTOCOL or HID_RPT_PROTOCOL.
-         */
-        void setProtocolMode(uint8_t mode) {
-                protocolMode = mode;
-        };
-
-        /**
-         * Used to set the leds on a keyboard.
-         * @param data See KBDLEDS in hidboot.h
-         */
-        void setLeds(uint8_t data);
-
-        /** True if a device is connected */
-        bool connected;
-
-        /** Call this to start the paring sequence with a device */
-        void pair(void) {
-                if(pBtd)
-                        pBtd->pairWithHID();
-        };
-
-protected:
-        /** @name BluetoothService implementation */
-        /**
-         * Used to pass acldata to the services.
-         * @param ACLData Incoming acldata.
-         */
-        void ACLData(uint8_t* ACLData);
-        /** Used to run part of the state machine. */
-        void Run();
-        /** Use this to reset the service. */
-        void Reset();
-        /**
-         * Called when a device is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        void onInit() {
-                if(pFuncOnInit)
-                        pFuncOnInit(); // Call the user function
-                OnInitBTHID();
-        };
-        /**@}*/
-
-        /** @name Overridable functions */
-        /**
-         * Used to parse Bluetooth HID data to any class that inherits this class.
-         * @param len The length of the incoming data.
-         * @param buf Pointer to the data buffer.
-         */
-        virtual void ParseBTHIDData(uint8_t len, uint8_t *buf) {
-                return;
-        };
-        /** Called when a device is connected */
-        virtual void OnInitBTHID() {
-                return;
-        };
-        /** Used to reset any buffers in the class that inherits this */
-        virtual void ResetBTHID() {
-                return;
-        }
-        /**@}*/
-
-        /** L2CAP source CID for HID_Control */
-        uint8_t control_scid[2];
-
-        /** L2CAP source CID for HID_Interrupt */
-        uint8_t interrupt_scid[2];
-
-private:
-        HIDReportParser *pRptParser[NUM_PARSERS]; // Pointer to HIDReportParsers.
-
-        /** Set report protocol. */
-        void setProtocol();
-        uint8_t protocolMode;
-
-        void L2CAP_task(); // L2CAP state machine
-
-        bool activeConnection; // Used to indicate if it already has established a connection
-
-        /* Variables used for L2CAP communication */
-        uint8_t control_dcid[2]; // L2CAP device CID for HID_Control - Always 0x0070
-        uint8_t interrupt_dcid[2]; // L2CAP device CID for HID_Interrupt - Always 0x0071
-        uint8_t l2cap_state;
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PS3BT.cpp b/lib/usbhost/USB_Host_Shield_2.0/PS3BT.cpp
deleted file mode 100644
index 235092e0ac..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PS3BT.cpp
+++ /dev/null
@@ -1,634 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#include "PS3BT.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-//#define PRINTREPORT // Uncomment to print the report send by the PS3 Controllers
-
-PS3BT::PS3BT(BTD *p, uint8_t btadr5, uint8_t btadr4, uint8_t btadr3, uint8_t btadr2, uint8_t btadr1, uint8_t btadr0) :
-BluetoothService(p) // Pointer to USB class instance - mandatory
-{
-        pBtd->my_bdaddr[5] = btadr5; // Change to your dongle's Bluetooth address instead
-        pBtd->my_bdaddr[4] = btadr4;
-        pBtd->my_bdaddr[3] = btadr3;
-        pBtd->my_bdaddr[2] = btadr2;
-        pBtd->my_bdaddr[1] = btadr1;
-        pBtd->my_bdaddr[0] = btadr0;
-
-        HIDBuffer[0] = 0x52; // HID BT Set_report (0x50) | Report Type (Output 0x02)
-        HIDBuffer[1] = 0x01; // Report ID
-
-        // Needed for PS3 Move Controller commands to work via bluetooth
-        HIDMoveBuffer[0] = 0xA2; // HID BT DATA_request (0xA0) | Report Type (Output 0x02)
-        HIDMoveBuffer[1] = 0x02; // Report ID
-
-        /* Set device cid for the control and intterrupt channelse - LSB */
-        control_dcid[0] = 0x40; // 0x0040
-        control_dcid[1] = 0x00;
-        interrupt_dcid[0] = 0x41; // 0x0041
-        interrupt_dcid[1] = 0x00;
-
-        Reset();
-}
-
-bool PS3BT::getButtonPress(ButtonEnum b) {
-        return (ButtonState & pgm_read_dword(&PS3_BUTTONS[(uint8_t)b]));
-}
-
-bool PS3BT::getButtonClick(ButtonEnum b) {
-        uint32_t button = pgm_read_dword(&PS3_BUTTONS[(uint8_t)b]);
-        bool click = (ButtonClickState & button);
-        ButtonClickState &= ~button; // Clear "click" event
-        return click;
-}
-
-uint8_t PS3BT::getAnalogButton(ButtonEnum a) {
-        return (uint8_t)(l2capinbuf[pgm_read_byte(&PS3_ANALOG_BUTTONS[(uint8_t)a])]);
-}
-
-uint8_t PS3BT::getAnalogHat(AnalogHatEnum a) {
-        return (uint8_t)(l2capinbuf[(uint8_t)a + 15]);
-}
-
-int16_t PS3BT::getSensor(SensorEnum a) {
-        if(PS3Connected) {
-                if(a == aX || a == aY || a == aZ || a == gZ)
-                        return ((l2capinbuf[(uint16_t)a] << 8) | l2capinbuf[(uint16_t)a + 1]);
-                else
-                        return 0;
-        } else if(PS3MoveConnected) {
-                if(a == mXmove || a == mYmove) // These are all 12-bits long
-                        return (((l2capinbuf[(uint16_t)a] & 0x0F) << 8) | (l2capinbuf[(uint16_t)a + 1]));
-                else if(a == mZmove || a == tempMove) // The tempearature is also 12 bits long
-                        return ((l2capinbuf[(uint16_t)a] << 4) | ((l2capinbuf[(uint16_t)a + 1] & 0xF0) >> 4));
-                else // aXmove, aYmove, aZmove, gXmove, gYmove and gZmove
-                        return (l2capinbuf[(uint16_t)a] | (l2capinbuf[(uint16_t)a + 1] << 8));
-        } else
-                return 0;
-}
-
-double PS3BT::getAngle(AngleEnum a) {
-        double accXval, accYval, accZval;
-
-        if(PS3Connected) {
-                // Data for the Kionix KXPC4 used in the DualShock 3
-                const double zeroG = 511.5; // 1.65/3.3*1023 (1.65V)
-                accXval = -((double)getSensor(aX) - zeroG);
-                accYval = -((double)getSensor(aY) - zeroG);
-                accZval = -((double)getSensor(aZ) - zeroG);
-        } else if(PS3MoveConnected) {
-                // It's a Kionix KXSC4 inside the Motion controller
-                const uint16_t zeroG = 0x8000;
-                accXval = -(int16_t)(getSensor(aXmove) - zeroG);
-                accYval = (int16_t)(getSensor(aYmove) - zeroG);
-                accZval = (int16_t)(getSensor(aZmove) - zeroG);
-        } else
-                return 0;
-
-        // Convert to 360 degrees resolution
-        // atan2 outputs the value of -π to π (radians)
-        // We are then converting it to 0 to 2π and then to degrees
-        if(a == Pitch)
-                return (atan2(accYval, accZval) + PI) * RAD_TO_DEG;
-        else
-                return (atan2(accXval, accZval) + PI) * RAD_TO_DEG;
-}
-
-double PS3BT::get9DOFValues(SensorEnum a) { // Thanks to Manfred Piendl
-        if(!PS3MoveConnected)
-                return 0;
-        int16_t value = getSensor(a);
-        if(a == mXmove || a == mYmove || a == mZmove) {
-                if(value > 2047)
-                        value -= 0x1000;
-                return (double)value / 3.2; // unit: muT = 10^(-6) Tesla
-        } else if(a == aXmove || a == aYmove || a == aZmove) {
-                if(value < 0)
-                        value += 0x8000;
-                else
-                        value -= 0x8000;
-                return (double)value / 442.0; // unit: m/(s^2)
-        } else if(a == gXmove || a == gYmove || a == gZmove) {
-                if(value < 0)
-                        value += 0x8000;
-                else
-                        value -= 0x8000;
-                if(a == gXmove)
-                        return (double)value / 11.6; // unit: deg/s
-                else if(a == gYmove)
-                        return (double)value / 11.2; // unit: deg/s
-                else // gZmove
-                        return (double)value / 9.6; // unit: deg/s
-        } else
-                return 0;
-}
-
-String PS3BT::getTemperature() {
-        if(PS3MoveConnected) {
-                int16_t input = getSensor(tempMove);
-
-                String output = String(input / 100);
-                output += ".";
-                if(input % 100 < 10)
-                        output += "0";
-                output += String(input % 100);
-
-                return output;
-        } else
-                return "Error";
-}
-
-bool PS3BT::getStatus(StatusEnum c) {
-        return (l2capinbuf[(uint16_t)c >> 8] == ((uint8_t)c & 0xff));
-}
-
-void PS3BT::printStatusString() {
-        char statusOutput[100]; // Max string length plus null character
-        if(PS3Connected || PS3NavigationConnected) {
-                strcpy_P(statusOutput, PSTR("ConnectionStatus: "));
-
-                if(getStatus(Plugged)) strcat_P(statusOutput, PSTR("Plugged"));
-                else if(getStatus(Unplugged)) strcat_P(statusOutput, PSTR("Unplugged"));
-                else strcat_P(statusOutput, PSTR("Error"));
-
-                strcat_P(statusOutput, PSTR(" - PowerRating: "));
-
-                if(getStatus(Charging)) strcat_P(statusOutput, PSTR("Charging"));
-                else if(getStatus(NotCharging)) strcat_P(statusOutput, PSTR("Not Charging"));
-                else if(getStatus(Shutdown)) strcat_P(statusOutput, PSTR("Shutdown"));
-                else if(getStatus(Dying)) strcat_P(statusOutput, PSTR("Dying"));
-                else if(getStatus(Low)) strcat_P(statusOutput, PSTR("Low"));
-                else if(getStatus(High)) strcat_P(statusOutput, PSTR("High"));
-                else if(getStatus(Full)) strcat_P(statusOutput, PSTR("Full"));
-                else strcat_P(statusOutput, PSTR("Error"));
-
-                strcat_P(statusOutput, PSTR(" - WirelessStatus: "));
-
-                if(getStatus(CableRumble)) strcat_P(statusOutput, PSTR("Cable - Rumble is on"));
-                else if(getStatus(Cable)) strcat_P(statusOutput, PSTR("Cable - Rumble is off"));
-                else if(getStatus(BluetoothRumble)) strcat_P(statusOutput, PSTR("Bluetooth - Rumble is on"));
-                else if(getStatus(Bluetooth)) strcat_P(statusOutput, PSTR("Bluetooth - Rumble is off"));
-                else strcat_P(statusOutput, PSTR("Error"));
-        } else if(PS3MoveConnected) {
-                strcpy_P(statusOutput, PSTR("PowerRating: "));
-
-                if(getStatus(MoveCharging)) strcat_P(statusOutput, PSTR("Charging"));
-                else if(getStatus(MoveNotCharging)) strcat_P(statusOutput, PSTR("Not Charging"));
-                else if(getStatus(MoveShutdown)) strcat_P(statusOutput, PSTR("Shutdown"));
-                else if(getStatus(MoveDying)) strcat_P(statusOutput, PSTR("Dying"));
-                else if(getStatus(MoveLow)) strcat_P(statusOutput, PSTR("Low"));
-                else if(getStatus(MoveHigh)) strcat_P(statusOutput, PSTR("High"));
-                else if(getStatus(MoveFull)) strcat_P(statusOutput, PSTR("Full"));
-                else strcat_P(statusOutput, PSTR("Error"));
-        } else
-                strcpy_P(statusOutput, PSTR("Error"));
-
-        USB_HOST_SERIAL.write(statusOutput);
-}
-
-void PS3BT::Reset() {
-        PS3Connected = false;
-        PS3MoveConnected = false;
-        PS3NavigationConnected = false;
-        activeConnection = false;
-        l2cap_event_flag = 0; // Reset flags
-        l2cap_state = L2CAP_WAIT;
-
-        // Needed for PS3 Dualshock Controller commands to work via Bluetooth
-        for(uint8_t i = 0; i < PS3_REPORT_BUFFER_SIZE; i++)
-                HIDBuffer[i + 2] = pgm_read_byte(&PS3_REPORT_BUFFER[i]); // First two bytes reserved for report type and ID
-}
-
-void PS3BT::disconnect() { // Use this void to disconnect any of the controllers
-        // First the HID interrupt channel has to be disconnected, then the HID control channel and finally the HCI connection
-        pBtd->l2cap_disconnection_request(hci_handle, ++identifier, interrupt_scid, interrupt_dcid);
-        Reset();
-        l2cap_state = L2CAP_INTERRUPT_DISCONNECT;
-}
-
-void PS3BT::ACLData(uint8_t* ACLData) {
-        if(!pBtd->l2capConnectionClaimed && !PS3Connected && !PS3MoveConnected && !PS3NavigationConnected && !activeConnection && !pBtd->connectToWii && !pBtd->incomingWii && !pBtd->pairWithWii) {
-                if(ACLData[8] == L2CAP_CMD_CONNECTION_REQUEST) {
-                        if((ACLData[12] | (ACLData[13] << 8)) == HID_CTRL_PSM) {
-                                pBtd->l2capConnectionClaimed = true; // Claim that the incoming connection belongs to this service
-                                activeConnection = true;
-                                hci_handle = pBtd->hci_handle; // Store the HCI Handle for the connection
-                                l2cap_state = L2CAP_WAIT;
-                                remote_name_first = pBtd->remote_name[0]; // Store the first letter in remote name for the connection
-#ifdef DEBUG_USB_HOST
-                                if(pBtd->hci_version < 3) { // Check the HCI Version of the Bluetooth dongle
-                                        Notify(PSTR("\r\nYour dongle may not support reading the analog buttons, sensors and status\r\nYour HCI Version is: "), 0x80);
-                                        Notify(pBtd->hci_version, 0x80);
-                                        Notify(PSTR("\r\nBut should be at least 3\r\nThis means that it doesn't support Bluetooth Version 2.0+EDR"), 0x80);
-                                }
-#endif
-                        }
-                }
-        }
-
-        if(checkHciHandle(ACLData, hci_handle)) { // acl_handle_ok
-                memcpy(l2capinbuf, ACLData, BULK_MAXPKTSIZE);
-                if((l2capinbuf[6] | (l2capinbuf[7] << 8)) == 0x0001U) { // l2cap_control - Channel ID for ACL-U
-                        if(l2capinbuf[8] == L2CAP_CMD_COMMAND_REJECT) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nL2CAP Command Rejected - Reason: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[12], 0x80);
-                                Notify(PSTR(" Data: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[17], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[16], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[15], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-#endif
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONNECTION_REQUEST) {
-#ifdef EXTRADEBUG
-                                Notify(PSTR("\r\nL2CAP Connection Request - PSM: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[12], 0x80);
-                                Notify(PSTR(" SCID: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[15], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-                                Notify(PSTR(" Identifier: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[9], 0x80);
-#endif
-                                if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == HID_CTRL_PSM) {
-                                        identifier = l2capinbuf[9];
-                                        control_scid[0] = l2capinbuf[14];
-                                        control_scid[1] = l2capinbuf[15];
-                                        l2cap_set_flag(L2CAP_FLAG_CONNECTION_CONTROL_REQUEST);
-                                } else if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == HID_INTR_PSM) {
-                                        identifier = l2capinbuf[9];
-                                        interrupt_scid[0] = l2capinbuf[14];
-                                        interrupt_scid[1] = l2capinbuf[15];
-                                        l2cap_set_flag(L2CAP_FLAG_CONNECTION_INTERRUPT_REQUEST);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONFIG_RESPONSE) {
-                                if((l2capinbuf[16] | (l2capinbuf[17] << 8)) == 0x0000) { // Success
-                                        if(l2capinbuf[12] == control_dcid[0] && l2capinbuf[13] == control_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Control Configuration Complete"), 0x80);
-                                                l2cap_set_flag(L2CAP_FLAG_CONFIG_CONTROL_SUCCESS);
-                                        } else if(l2capinbuf[12] == interrupt_dcid[0] && l2capinbuf[13] == interrupt_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Interrupt Configuration Complete"), 0x80);
-                                                l2cap_set_flag(L2CAP_FLAG_CONFIG_INTERRUPT_SUCCESS);
-                                        }
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONFIG_REQUEST) {
-                                if(l2capinbuf[12] == control_dcid[0] && l2capinbuf[13] == control_dcid[1]) {
-                                        //Notify(PSTR("\r\nHID Control Configuration Request"), 0x80);
-                                        pBtd->l2cap_config_response(hci_handle, l2capinbuf[9], control_scid);
-                                } else if(l2capinbuf[12] == interrupt_dcid[0] && l2capinbuf[13] == interrupt_dcid[1]) {
-                                        //Notify(PSTR("\r\nHID Interrupt Configuration Request"), 0x80);
-                                        pBtd->l2cap_config_response(hci_handle, l2capinbuf[9], interrupt_scid);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_DISCONNECT_REQUEST) {
-                                if(l2capinbuf[12] == control_dcid[0] && l2capinbuf[13] == control_dcid[1]) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nDisconnect Request: Control Channel"), 0x80);
-#endif
-                                        identifier = l2capinbuf[9];
-                                        pBtd->l2cap_disconnection_response(hci_handle, identifier, control_dcid, control_scid);
-                                        Reset();
-                                } else if(l2capinbuf[12] == interrupt_dcid[0] && l2capinbuf[13] == interrupt_dcid[1]) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nDisconnect Request: Interrupt Channel"), 0x80);
-#endif
-                                        identifier = l2capinbuf[9];
-                                        pBtd->l2cap_disconnection_response(hci_handle, identifier, interrupt_dcid, interrupt_scid);
-                                        Reset();
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_DISCONNECT_RESPONSE) {
-                                if(l2capinbuf[12] == control_scid[0] && l2capinbuf[13] == control_scid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Response: Control Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_CONTROL_RESPONSE);
-                                } else if(l2capinbuf[12] == interrupt_scid[0] && l2capinbuf[13] == interrupt_scid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Response: Interrupt Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_INTERRUPT_RESPONSE);
-                                }
-                        }
-#ifdef EXTRADEBUG
-                        else {
-                                Notify(PSTR("\r\nL2CAP Unknown Signaling Command: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[8], 0x80);
-                        }
-#endif
-                } else if(l2capinbuf[6] == interrupt_dcid[0] && l2capinbuf[7] == interrupt_dcid[1]) { // l2cap_interrupt
-                        //Notify(PSTR("\r\nL2CAP Interrupt"), 0x80);
-                        if(PS3Connected || PS3MoveConnected || PS3NavigationConnected) {
-                                /* Read Report */
-                                if(l2capinbuf[8] == 0xA1) { // HID_THDR_DATA_INPUT
-                                        lastMessageTime = millis(); // Store the last message time
-
-                                        if(PS3Connected || PS3NavigationConnected)
-                                                ButtonState = (uint32_t)(l2capinbuf[11] | ((uint16_t)l2capinbuf[12] << 8) | ((uint32_t)l2capinbuf[13] << 16));
-                                        else if(PS3MoveConnected)
-                                                ButtonState = (uint32_t)(l2capinbuf[10] | ((uint16_t)l2capinbuf[11] << 8) | ((uint32_t)l2capinbuf[12] << 16));
-
-                                        //Notify(PSTR("\r\nButtonState", 0x80);
-                                        //PrintHex<uint32_t>(ButtonState, 0x80);
-
-                                        if(ButtonState != OldButtonState) {
-                                                ButtonClickState = ButtonState & ~OldButtonState; // Update click state variable
-                                                OldButtonState = ButtonState;
-                                        }
-
-#ifdef PRINTREPORT // Uncomment "#define PRINTREPORT" to print the report send by the PS3 Controllers
-                                        for(uint8_t i = 10; i < 58; i++) {
-                                                D_PrintHex<uint8_t > (l2capinbuf[i], 0x80);
-                                                Notify(PSTR(" "), 0x80);
-                                        }
-                                        Notify(PSTR("\r\n"), 0x80);
-#endif
-                                }
-                        }
-                }
-                L2CAP_task();
-        }
-}
-
-void PS3BT::L2CAP_task() {
-        switch(l2cap_state) {
-                case L2CAP_WAIT:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONNECTION_CONTROL_REQUEST)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Control Incoming Connection Request"), 0x80);
-#endif
-                                pBtd->l2cap_connection_response(hci_handle, identifier, control_dcid, control_scid, PENDING);
-                                delay(1);
-                                pBtd->l2cap_connection_response(hci_handle, identifier, control_dcid, control_scid, SUCCESSFUL);
-                                identifier++;
-                                delay(1);
-                                pBtd->l2cap_config_request(hci_handle, identifier, control_scid);
-                                l2cap_state = L2CAP_CONTROL_SUCCESS;
-                        }
-                        break;
-
-                case L2CAP_CONTROL_SUCCESS:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_CONTROL_SUCCESS)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Control Successfully Configured"), 0x80);
-#endif
-                                l2cap_state = L2CAP_INTERRUPT_SETUP;
-                        }
-                        break;
-
-                case L2CAP_INTERRUPT_SETUP:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONNECTION_INTERRUPT_REQUEST)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Interrupt Incoming Connection Request"), 0x80);
-#endif
-                                pBtd->l2cap_connection_response(hci_handle, identifier, interrupt_dcid, interrupt_scid, PENDING);
-                                delay(1);
-                                pBtd->l2cap_connection_response(hci_handle, identifier, interrupt_dcid, interrupt_scid, SUCCESSFUL);
-                                identifier++;
-                                delay(1);
-                                pBtd->l2cap_config_request(hci_handle, identifier, interrupt_scid);
-
-                                l2cap_state = L2CAP_INTERRUPT_CONFIG_REQUEST;
-                        }
-                        break;
-
-                case L2CAP_INTERRUPT_CONFIG_REQUEST:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_INTERRUPT_SUCCESS)) { // Now the HID channels is established
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Interrupt Successfully Configured"), 0x80);
-#endif
-                                if(remote_name_first == 'M') { // First letter in Motion Controller ('M')
-                                        memset(l2capinbuf, 0, BULK_MAXPKTSIZE); // Reset l2cap in buffer as it sometimes read it as a button has been pressed
-                                        l2cap_state = TURN_ON_LED;
-                                } else
-                                        l2cap_state = PS3_ENABLE_SIXAXIS;
-                                timer = millis();
-                        }
-                        break;
-
-                        /* These states are handled in Run() */
-
-                case L2CAP_INTERRUPT_DISCONNECT:
-                        if(l2cap_check_flag(L2CAP_FLAG_DISCONNECT_INTERRUPT_RESPONSE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nDisconnected Interrupt Channel"), 0x80);
-#endif
-                                identifier++;
-                                pBtd->l2cap_disconnection_request(hci_handle, identifier, control_scid, control_dcid);
-                                l2cap_state = L2CAP_CONTROL_DISCONNECT;
-                        }
-                        break;
-
-                case L2CAP_CONTROL_DISCONNECT:
-                        if(l2cap_check_flag(L2CAP_FLAG_DISCONNECT_CONTROL_RESPONSE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nDisconnected Control Channel"), 0x80);
-#endif
-                                pBtd->hci_disconnect(hci_handle);
-                                hci_handle = -1; // Reset handle
-                                l2cap_event_flag = 0; // Reset flags
-                                l2cap_state = L2CAP_WAIT;
-                        }
-                        break;
-        }
-}
-
-void PS3BT::Run() {
-        switch(l2cap_state) {
-                case PS3_ENABLE_SIXAXIS:
-                        if(millis() - timer > 1000) { // loop 1 second before sending the command
-                                memset(l2capinbuf, 0, BULK_MAXPKTSIZE); // Reset l2cap in buffer as it sometimes read it as a button has been pressed
-                                for(uint8_t i = 15; i < 19; i++)
-                                        l2capinbuf[i] = 0x7F; // Set the analog joystick values to center position
-                                enable_sixaxis();
-                                l2cap_state = TURN_ON_LED;
-                                timer = millis();
-                        }
-                        break;
-
-                case TURN_ON_LED:
-                        if(millis() - timer > 1000) { // loop 1 second before sending the command
-                                if(remote_name_first == 'P') { // First letter in PLAYSTATION(R)3 Controller ('P')
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nDualshock 3 Controller Enabled\r\n"), 0x80);
-#endif
-                                        PS3Connected = true;
-                                } else if(remote_name_first == 'N') { // First letter in Navigation Controller ('N')
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nNavigation Controller Enabled\r\n"), 0x80);
-#endif
-                                        PS3NavigationConnected = true;
-                                } else if(remote_name_first == 'M') { // First letter in Motion Controller ('M')
-                                        timer = millis();
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nMotion Controller Enabled\r\n"), 0x80);
-#endif
-                                        PS3MoveConnected = true;
-                                }
-                                ButtonState = 0; // Clear all values
-                                OldButtonState = 0;
-                                ButtonClickState = 0;
-
-                                onInit(); // Turn on the LED on the controller
-                                l2cap_state = L2CAP_DONE;
-                        }
-                        break;
-
-                case L2CAP_DONE:
-                        if(PS3MoveConnected) { // The Bulb and rumble values, has to be send at approximately every 5th second for it to stay on
-                                if(millis() - timer > 4000) { // Send at least every 4th second
-                                        HIDMove_Command(HIDMoveBuffer, HID_BUFFERSIZE); // The Bulb and rumble values, has to be written again and again, for it to stay turned on
-                                        timer = millis();
-                                }
-                        }
-                        break;
-        }
-}
-
-/************************************************************/
-/*                    HID Commands                          */
-/************************************************************/
-
-// Playstation Sixaxis Dualshock and Navigation Controller commands
-
-void PS3BT::HID_Command(uint8_t* data, uint8_t nbytes) {
-        if(millis() - timerHID <= 150) // Check if is has been more than 150ms since last command
-                delay((uint32_t)(150 - (millis() - timerHID))); // There have to be a delay between commands
-        pBtd->L2CAP_Command(hci_handle, data, nbytes, control_scid[0], control_scid[1]); // Both the Navigation and Dualshock controller sends data via the control channel
-        timerHID = millis();
-}
-
-void PS3BT::setAllOff() {
-        HIDBuffer[3] = 0x00; // Rumble bytes
-        HIDBuffer[4] = 0x00;
-        HIDBuffer[5] = 0x00;
-        HIDBuffer[6] = 0x00;
-
-        HIDBuffer[11] = 0x00; // LED byte
-
-        HID_Command(HIDBuffer, HID_BUFFERSIZE);
-}
-
-void PS3BT::setRumbleOff() {
-        HIDBuffer[3] = 0x00;
-        HIDBuffer[4] = 0x00;
-        HIDBuffer[5] = 0x00;
-        HIDBuffer[6] = 0x00;
-
-        HID_Command(HIDBuffer, HID_BUFFERSIZE);
-}
-
-void PS3BT::setRumbleOn(RumbleEnum mode) {
-        uint8_t power[2] = {0xff, 0x00}; // Defaults to RumbleLow
-        if(mode == RumbleHigh) {
-                power[0] = 0x00;
-                power[1] = 0xff;
-        }
-        setRumbleOn(0xfe, power[0], 0xfe, power[1]);
-}
-
-void PS3BT::setRumbleOn(uint8_t rightDuration, uint8_t rightPower, uint8_t leftDuration, uint8_t leftPower) {
-        HIDBuffer[3] = rightDuration;
-        HIDBuffer[4] = rightPower;
-        HIDBuffer[5] = leftDuration;
-        HIDBuffer[6] = leftPower;
-        HID_Command(HIDBuffer, HID_BUFFERSIZE);
-}
-
-void PS3BT::setLedRaw(uint8_t value) {
-        HIDBuffer[11] = value << 1;
-        HID_Command(HIDBuffer, HID_BUFFERSIZE);
-}
-
-void PS3BT::setLedOff(LEDEnum a) {
-        HIDBuffer[11] &= ~((uint8_t)((pgm_read_byte(&PS3_LEDS[(uint8_t)a]) & 0x0f) << 1));
-        HID_Command(HIDBuffer, HID_BUFFERSIZE);
-}
-
-void PS3BT::setLedOn(LEDEnum a) {
-        if(a == OFF)
-                setLedRaw(0);
-        else {
-                HIDBuffer[11] |= (uint8_t)((pgm_read_byte(&PS3_LEDS[(uint8_t)a]) & 0x0f) << 1);
-                HID_Command(HIDBuffer, HID_BUFFERSIZE);
-        }
-}
-
-void PS3BT::setLedToggle(LEDEnum a) {
-        HIDBuffer[11] ^= (uint8_t)((pgm_read_byte(&PS3_LEDS[(uint8_t)a]) & 0x0f) << 1);
-        HID_Command(HIDBuffer, HID_BUFFERSIZE);
-}
-
-void PS3BT::enable_sixaxis() { // Command used to enable the Dualshock 3 and Navigation controller to send data via Bluetooth
-        uint8_t cmd_buf[6];
-        cmd_buf[0] = 0x53; // HID BT Set_report (0x50) | Report Type (Feature 0x03)
-        cmd_buf[1] = 0xF4; // Report ID
-        cmd_buf[2] = 0x42; // Special PS3 Controller enable commands
-        cmd_buf[3] = 0x03;
-        cmd_buf[4] = 0x00;
-        cmd_buf[5] = 0x00;
-
-        HID_Command(cmd_buf, 6);
-}
-
-// Playstation Move Controller commands
-
-void PS3BT::HIDMove_Command(uint8_t* data, uint8_t nbytes) {
-        if(millis() - timerHID <= 150)// Check if is has been less than 150ms since last command
-                delay((uint32_t)(150 - (millis() - timerHID))); // There have to be a delay between commands
-        pBtd->L2CAP_Command(hci_handle, data, nbytes, interrupt_scid[0], interrupt_scid[1]); // The Move controller sends it's data via the intterrupt channel
-        timerHID = millis();
-}
-
-void PS3BT::moveSetBulb(uint8_t r, uint8_t g, uint8_t b) { // Use this to set the Color using RGB values
-        // Set the Bulb's values into the write buffer
-        HIDMoveBuffer[3] = r;
-        HIDMoveBuffer[4] = g;
-        HIDMoveBuffer[5] = b;
-
-        HIDMove_Command(HIDMoveBuffer, HID_BUFFERSIZE);
-}
-
-void PS3BT::moveSetBulb(ColorsEnum color) { // Use this to set the Color using the predefined colors in enum
-        moveSetBulb((uint8_t)(color >> 16), (uint8_t)(color >> 8), (uint8_t)(color));
-}
-
-void PS3BT::moveSetRumble(uint8_t rumble) {
-#ifdef DEBUG_USB_HOST
-        if(rumble < 64 && rumble != 0) // The rumble value has to at least 64, or approximately 25% (64/255*100)
-                Notify(PSTR("\r\nThe rumble value has to at least 64, or approximately 25%"), 0x80);
-#endif
-        // Set the rumble value into the write buffer
-        HIDMoveBuffer[7] = rumble;
-
-        HIDMove_Command(HIDMoveBuffer, HID_BUFFERSIZE);
-}
-
-void PS3BT::onInit() {
-        if(pFuncOnInit)
-                pFuncOnInit(); // Call the user function
-        else {
-                if(PS3MoveConnected)
-                        moveSetBulb(Red);
-                else // Dualshock 3 or Navigation controller
-                        setLedOn(LED1);
-        }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PS3BT.h b/lib/usbhost/USB_Host_Shield_2.0/PS3BT.h
deleted file mode 100644
index c25ac5e59d..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PS3BT.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _ps3bt_h_
-#define _ps3bt_h_
-
-#include "BTD.h"
-#include "PS3Enums.h"
-
-#define HID_BUFFERSIZE 50 // Size of the buffer for the Playstation Motion Controller
-
-/**
- * This BluetoothService class implements support for all the official PS3 Controllers:
- * Dualshock 3, Navigation or a Motion controller via Bluetooth.
- *
- * Information about the protocol can be found at the wiki: https://github.com/felis/USB_Host_Shield_2.0/wiki/PS3-Information.
- */
-class PS3BT : public BluetoothService {
-public:
-        /**
-         * Constructor for the PS3BT class.
-         * @param  pBtd   Pointer to BTD class instance.
-         * @param  btadr5,btadr4,btadr3,btadr2,btadr1,btadr0
-         * Pass your dongles Bluetooth address into the constructor,
-         * This will set BTD#my_bdaddr, so you don't have to plug in the dongle before pairing with your controller.
-         */
-        PS3BT(BTD *pBtd, uint8_t btadr5 = 0, uint8_t btadr4 = 0, uint8_t btadr3 = 0, uint8_t btadr2 = 0, uint8_t btadr1 = 0, uint8_t btadr0 = 0);
-
-        /** @name BluetoothService implementation */
-        /** Used this to disconnect any of the controllers. */
-        void disconnect();
-        /**@}*/
-
-        /** @name PS3 Controller functions */
-        /**
-         * getButtonPress(ButtonEnum b) will return true as long as the button is held down.
-         *
-         * While getButtonClick(ButtonEnum b) will only return it once.
-         *
-         * So you instance if you need to increase a variable once you would use getButtonClick(ButtonEnum b),
-         * but if you need to drive a robot forward you would use getButtonPress(ButtonEnum b).
-         * @param  b          ::ButtonEnum to read.
-         * @return            getButtonPress(ButtonEnum b) will return a true as long as a button is held down, while getButtonClick(ButtonEnum b) will return true once for each button press.
-         */
-        bool getButtonPress(ButtonEnum b);
-        bool getButtonClick(ButtonEnum b);
-        /**@}*/
-        /** @name PS3 Controller functions */
-        /**
-         * Used to get the analog value from button presses.
-         * @param  a The ::ButtonEnum to read.
-         * The supported buttons are:
-         * ::UP, ::RIGHT, ::DOWN, ::LEFT, ::L1, ::L2, ::R1, ::R2,
-         * ::TRIANGLE, ::CIRCLE, ::CROSS, ::SQUARE, and ::T.
-         * @return   Analog value in the range of 0-255.
-         */
-        uint8_t getAnalogButton(ButtonEnum a);
-        /**
-         * Used to read the analog joystick.
-         * @param  a ::LeftHatX, ::LeftHatY, ::RightHatX, and ::RightHatY.
-         * @return   Return the analog value in the range of 0-255.
-         */
-        uint8_t getAnalogHat(AnalogHatEnum a);
-        /**
-         * Used to read the sensors inside the Dualshock 3 and Move controller.
-         * @param  a
-         * The Dualshock 3 has a 3-axis accelerometer and a 1-axis gyro inside.
-         * The Move controller has a 3-axis accelerometer, a 3-axis gyro, a 3-axis magnetometer
-         * and a temperature sensor inside.
-         * @return   Return the raw sensor value.
-         */
-        int16_t getSensor(SensorEnum a);
-        /**
-         * Use this to get ::Pitch and ::Roll calculated using the accelerometer.
-         * @param  a Either ::Pitch or ::Roll.
-         * @return   Return the angle in the range of 0-360.
-         */
-        double getAngle(AngleEnum a);
-        /**
-         * Read the sensors inside the Move controller.
-         * @param  a ::aXmove, ::aYmove, ::aZmove, ::gXmove, ::gYmove, ::gZmove, ::mXmove, ::mYmove, and ::mXmove.
-         * @return   The value in SI units.
-         */
-        double get9DOFValues(SensorEnum a);
-        /**
-         * Get the status from the controller.
-         * @param  c The ::StatusEnum you want to read.
-         * @return   True if correct and false if not.
-         */
-        bool getStatus(StatusEnum c);
-        /** Read all the available statuses from the controller and prints it as a nice formated string. */
-        void printStatusString();
-        /**
-         * Read the temperature from the Move controller.
-         * @return The temperature in degrees Celsius.
-         */
-        String getTemperature();
-
-        /** Used to set all LEDs and rumble off. */
-        void setAllOff();
-        /** Turn off rumble. */
-        void setRumbleOff();
-        /**
-         * Turn on rumble.
-         * @param mode Either ::RumbleHigh or ::RumbleLow.
-         */
-        void setRumbleOn(RumbleEnum mode);
-        /**
-         * Turn on rumble using custom duration and power.
-         * @param rightDuration The duration of the right/low rumble effect.
-         * @param rightPower The intensity of the right/low rumble effect.
-         * @param leftDuration The duration of the left/high rumble effect.
-         * @param leftPower The intensity of the left/high rumble effect.
-         */
-        void setRumbleOn(uint8_t rightDuration, uint8_t rightPower, uint8_t leftDuration, uint8_t leftPower);
-
-        /**
-         * Set LED value without using ::LEDEnum.
-         * @param value See: ::LEDEnum.
-         */
-        void setLedRaw(uint8_t value);
-
-        /** Turn all LEDs off. */
-        void setLedOff() {
-                setLedRaw(0);
-        };
-        /**
-         * Turn the specific LED off.
-         * @param a The ::LEDEnum to turn off.
-         */
-        void setLedOff(LEDEnum a);
-        /**
-         * Turn the specific LED on.
-         * @param a The ::LEDEnum to turn on.
-         */
-        void setLedOn(LEDEnum a);
-        /**
-         * Toggle the specific LED.
-         * @param a The ::LEDEnum to toggle.
-         */
-        void setLedToggle(LEDEnum a);
-
-        /**
-         * Use this to set the Color using RGB values.
-         * @param r,g,b RGB value.
-         */
-        void moveSetBulb(uint8_t r, uint8_t g, uint8_t b);
-        /**
-         * Use this to set the color using the predefined colors in ::ColorsEnum.
-         * @param color The desired color.
-         */
-        void moveSetBulb(ColorsEnum color);
-        /**
-         * Set the rumble value inside the Move controller.
-         * @param rumble The desired value in the range from 64-255.
-         */
-        void moveSetRumble(uint8_t rumble);
-
-        /** Used to get the millis() of the last message */
-        uint32_t getLastMessageTime() {
-                return lastMessageTime;
-        };
-        /**@}*/
-
-        /** Variable used to indicate if the normal Playstation controller is successfully connected. */
-        bool PS3Connected;
-        /** Variable used to indicate if the Move controller is successfully connected. */
-        bool PS3MoveConnected;
-        /** Variable used to indicate if the Navigation controller is successfully connected. */
-        bool PS3NavigationConnected;
-
-protected:
-        /** @name BluetoothService implementation */
-        /**
-         * Used to pass acldata to the services.
-         * @param ACLData Incoming acldata.
-         */
-        void ACLData(uint8_t* ACLData);
-        /** Used to run part of the state machine. */
-        void Run();
-        /** Use this to reset the service. */
-        void Reset();
-        /**
-         * Called when the controller is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        void onInit();
-        /**@}*/
-
-private:
-
-        void L2CAP_task(); // L2CAP state machine
-
-        /* Variables filled from HCI event management */
-        char remote_name_first; // First letter in remote name
-        bool activeConnection; // Used to indicate if it's already has established a connection
-
-        /* Variables used by high level L2CAP task */
-        uint8_t l2cap_state;
-
-        uint32_t lastMessageTime; // Variable used to store the millis value of the last message.
-
-        uint32_t ButtonState;
-        uint32_t OldButtonState;
-        uint32_t ButtonClickState;
-
-        uint32_t timer; // Timer used to limit time between messages and also used to continuously set PS3 Move controller Bulb and rumble values
-        uint32_t timerHID; // Timer used see if there has to be a delay before a new HID command
-
-        uint8_t l2capinbuf[BULK_MAXPKTSIZE]; // General purpose buffer for L2CAP in data
-        uint8_t HIDBuffer[HID_BUFFERSIZE]; // Used to store HID commands
-        uint8_t HIDMoveBuffer[HID_BUFFERSIZE]; // Used to store HID commands for the Move controller
-
-        /* L2CAP Channels */
-        uint8_t control_scid[2]; // L2CAP source CID for HID_Control
-        uint8_t control_dcid[2]; // 0x0040
-        uint8_t interrupt_scid[2]; // L2CAP source CID for HID_Interrupt
-        uint8_t interrupt_dcid[2]; // 0x0041
-
-        /* HID Commands */
-        void HID_Command(uint8_t* data, uint8_t nbytes);
-        void HIDMove_Command(uint8_t* data, uint8_t nbytes);
-        void enable_sixaxis(); // Command used to enable the Dualshock 3 and Navigation controller to send data via Bluetooth
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PS3Enums.h b/lib/usbhost/USB_Host_Shield_2.0/PS3Enums.h
deleted file mode 100644
index 77801945f2..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PS3Enums.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _ps3enums_h
-#define _ps3enums_h
-
-#include "controllerEnums.h"
-
-/** Size of the output report buffer for the Dualshock and Navigation controllers */
-#define PS3_REPORT_BUFFER_SIZE  48
-
-/** Report buffer for all PS3 commands */
-const uint8_t PS3_REPORT_BUFFER[PS3_REPORT_BUFFER_SIZE] PROGMEM = {
-        0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00,
-        0xff, 0x27, 0x10, 0x00, 0x32,
-        0xff, 0x27, 0x10, 0x00, 0x32,
-        0xff, 0x27, 0x10, 0x00, 0x32,
-        0xff, 0x27, 0x10, 0x00, 0x32,
-        0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-/** Size of the output report buffer for the Move Controller */
-#define MOVE_REPORT_BUFFER_SIZE 7
-
-/** Used to set the LEDs on the controllers */
-const uint8_t PS3_LEDS[] PROGMEM = {
-        0x00, // OFF
-        0x01, // LED1
-        0x02, // LED2
-        0x04, // LED3
-        0x08, // LED4
-
-        0x09, // LED5
-        0x0A, // LED6
-        0x0C, // LED7
-        0x0D, // LED8
-        0x0E, // LED9
-        0x0F, // LED10
-};
-
-/**
- * Buttons on the controllers.
- * <B>Note:</B> that the location is shifted 9 when it's connected via USB.
- */
-const uint32_t PS3_BUTTONS[] PROGMEM = {
-        0x10, // UP
-        0x20, // RIGHT
-        0x40, // DOWN
-        0x80, // LEFT
-
-        0x01, // SELECT
-        0x08, // START
-        0x02, // L3
-        0x04, // R3
-
-        0x0100, // L2
-        0x0200, // R2
-        0x0400, // L1
-        0x0800, // R1
-
-        0x1000, // TRIANGLE
-        0x2000, // CIRCLE
-        0x4000, // CROSS
-        0x8000, // SQUARE
-
-        0x010000, // PS
-        0x080000, // MOVE - covers 12 bits - we only need to read the top 8
-        0x100000, // T - covers 12 bits - we only need to read the top 8
-};
-
-/**
- * Analog buttons on the controllers.
- * <B>Note:</B> that the location is shifted 9 when it's connected via USB.
- */
-const uint8_t PS3_ANALOG_BUTTONS[] PROGMEM = {
-        23, // UP_ANALOG
-        24, // RIGHT_ANALOG
-        25, // DOWN_ANALOG
-        26, // LEFT_ANALOG
-        0, 0, 0, 0, // Skip SELECT, L3, R3 and START
-
-        27, // L2_ANALOG
-        28, // R2_ANALOG
-        29, // L1_ANALOG
-        30, // R1_ANALOG
-        31, // TRIANGLE_ANALOG
-        32, // CIRCLE_ANALOG
-        33, // CROSS_ANALOG
-        34, // SQUARE_ANALOG
-        0, 0, // Skip PS and MOVE
-
-        // Playstation Move Controller
-        15, // T_ANALOG - Both at byte 14 (last reading) and byte 15 (current reading)
-};
-
-enum StatusEnum {
-        // Note that the location is shifted 9 when it's connected via USB
-        // Byte location | bit location
-        Plugged = (38 << 8) | 0x02,
-        Unplugged = (38 << 8) | 0x03,
-
-        Charging = (39 << 8) | 0xEE,
-        NotCharging = (39 << 8) | 0xF1,
-        Shutdown = (39 << 8) | 0x01,
-        Dying = (39 << 8) | 0x02,
-        Low = (39 << 8) | 0x03,
-        High = (39 << 8) | 0x04,
-        Full = (39 << 8) | 0x05,
-
-        MoveCharging = (21 << 8) | 0xEE,
-        MoveNotCharging = (21 << 8) | 0xF1,
-        MoveShutdown = (21 << 8) | 0x01,
-        MoveDying = (21 << 8) | 0x02,
-        MoveLow = (21 << 8) | 0x03,
-        MoveHigh = (21 << 8) | 0x04,
-        MoveFull = (21 << 8) | 0x05,
-
-        CableRumble = (40 << 8) | 0x10, // Operating by USB and rumble is turned on
-        Cable = (40 << 8) | 0x12, // Operating by USB and rumble is turned off
-        BluetoothRumble = (40 << 8) | 0x14, // Operating by Bluetooth and rumble is turned on
-        Bluetooth = (40 << 8) | 0x16, // Operating by Bluetooth and rumble is turned off
-};
-
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PS3USB.cpp b/lib/usbhost/USB_Host_Shield_2.0/PS3USB.cpp
deleted file mode 100644
index c32175389c..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PS3USB.cpp
+++ /dev/null
@@ -1,572 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#include "PS3USB.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-//#define PRINTREPORT // Uncomment to print the report send by the PS3 Controllers
-
-PS3USB::PS3USB(USB *p, uint8_t btadr5, uint8_t btadr4, uint8_t btadr3, uint8_t btadr2, uint8_t btadr1, uint8_t btadr0) :
-pUsb(p), // pointer to USB class instance - mandatory
-bAddress(0), // device address - mandatory
-bPollEnable(false) // don't start polling before dongle is connected
-{
-        for(uint8_t i = 0; i < PS3_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-        }
-
-        if(pUsb) // register in USB subsystem
-                pUsb->RegisterDeviceClass(this); //set devConfig[] entry
-
-        my_bdaddr[5] = btadr5; // Change to your dongle's Bluetooth address instead
-        my_bdaddr[4] = btadr4;
-        my_bdaddr[3] = btadr3;
-        my_bdaddr[2] = btadr2;
-        my_bdaddr[1] = btadr1;
-        my_bdaddr[0] = btadr0;
-}
-
-uint8_t PS3USB::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        uint8_t buf[sizeof (USB_DEVICE_DESCRIPTOR)];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint16_t PID;
-        uint16_t VID;
-
-        // get memory address of USB device address pool
-        AddressPool &addrPool = pUsb->GetAddressPool();
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nPS3USB Init"), 0x80);
-#endif
-        // check if address has already been assigned to an instance
-        if(bAddress) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress in use"), 0x80);
-#endif
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-        }
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        if(!p->epinfo) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nepinfo is null"), 0x80);
-#endif
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, sizeof (USB_DEVICE_DESCRIPTOR), (uint8_t*)buf); // Get device descriptor - addr, ep, nbytes, data
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        VID = udd->idVendor;
-        PID = udd->idProduct;
-
-        if(VID != PS3_VID || (PID != PS3_PID && PID != PS3NAVIGATION_PID && PID != PS3MOVE_PID))
-                goto FailUnknownDevice;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nsetAddr: "), 0x80);
-                D_PrintHex<uint8_t > (rcode, 0x80);
-#endif
-                return rcode;
-        }
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nAddr: "), 0x80);
-        D_PrintHex<uint8_t > (bAddress, 0x80);
-#endif
-        //delay(300); // Spec says you should wait at least 200ms
-
-        p->lowspeed = false;
-
-        //get pointer to assigned address record
-        p = addrPool.GetUsbDevicePtr(bAddress);
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        // Assign epInfo to epinfo pointer - only EP0 is known
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-
-        /* The application will work in reduced host mode, so we can save program and data
-           memory space. After verifying the PID and VID we will use known values for the
-           configuration values for device, interface, endpoints and HID for the PS3 Controllers */
-
-        /* Initialize data structures for endpoints of device */
-        epInfo[ PS3_OUTPUT_PIPE ].epAddr = 0x02; // PS3 output endpoint
-        epInfo[ PS3_OUTPUT_PIPE ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ PS3_OUTPUT_PIPE ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ PS3_OUTPUT_PIPE ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ PS3_OUTPUT_PIPE ].bmSndToggle = 0;
-        epInfo[ PS3_OUTPUT_PIPE ].bmRcvToggle = 0;
-        epInfo[ PS3_INPUT_PIPE ].epAddr = 0x01; // PS3 report endpoint
-        epInfo[ PS3_INPUT_PIPE ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ PS3_INPUT_PIPE ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ PS3_INPUT_PIPE ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ PS3_INPUT_PIPE ].bmSndToggle = 0;
-        epInfo[ PS3_INPUT_PIPE ].bmRcvToggle = 0;
-
-        rcode = pUsb->setEpInfoEntry(bAddress, 3, epInfo);
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        delay(200); //Give time for address change
-
-        rcode = pUsb->setConf(bAddress, epInfo[ PS3_CONTROL_PIPE ].epAddr, 1);
-        if(rcode)
-                goto FailSetConfDescr;
-
-        if(PID == PS3_PID || PID == PS3NAVIGATION_PID) {
-                if(PID == PS3_PID) {
-#ifdef DEBUG_USB_HOST
-                        Notify(PSTR("\r\nDualshock 3 Controller Connected"), 0x80);
-#endif
-                        PS3Connected = true;
-                } else { // must be a navigation controller
-#ifdef DEBUG_USB_HOST
-                        Notify(PSTR("\r\nNavigation Controller Connected"), 0x80);
-#endif
-                        PS3NavigationConnected = true;
-                }
-                enable_sixaxis(); // The PS3 controller needs a special command before it starts sending data
-
-                // Needed for PS3 Dualshock and Navigation commands to work
-                for(uint8_t i = 0; i < PS3_REPORT_BUFFER_SIZE; i++)
-                        writeBuf[i] = pgm_read_byte(&PS3_REPORT_BUFFER[i]);
-
-                for(uint8_t i = 6; i < 10; i++)
-                        readBuf[i] = 0x7F; // Set the analog joystick values to center position
-        } else { // must be a Motion controller
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nMotion Controller Connected"), 0x80);
-#endif
-                PS3MoveConnected = true;
-                writeBuf[0] = 0x02; // Set report ID, this is needed for Move commands to work
-        }
-        if(my_bdaddr[0] != 0x00 || my_bdaddr[1] != 0x00 || my_bdaddr[2] != 0x00 || my_bdaddr[3] != 0x00 || my_bdaddr[4] != 0x00 || my_bdaddr[5] != 0x00) {
-                if(PS3MoveConnected)
-                        setMoveBdaddr(my_bdaddr); // Set internal Bluetooth address
-                else
-                        setBdaddr(my_bdaddr); // Set internal Bluetooth address
-
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nBluetooth Address was set to: "), 0x80);
-                for(int8_t i = 5; i > 0; i--) {
-                        D_PrintHex<uint8_t > (my_bdaddr[i], 0x80);
-                        Notify(PSTR(":"), 0x80);
-                }
-                D_PrintHex<uint8_t > (my_bdaddr[0], 0x80);
-#endif
-        }
-        onInit();
-
-        bPollEnable = true;
-        Notify(PSTR("\r\n"), 0x80);
-        timer = millis();
-        return 0; // Successful configuration
-
-        /* Diagnostic messages */
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-#endif
-        goto Fail;
-
-FailUnknownDevice:
-#ifdef DEBUG_USB_HOST
-        NotifyFailUnknownDevice(VID, PID);
-#endif
-        rcode = USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-Fail:
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nPS3 Init Failed, error code: "), 0x80);
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-/* Performs a cleanup after failed Init() attempt */
-uint8_t PS3USB::Release() {
-        PS3Connected = false;
-        PS3MoveConnected = false;
-        PS3NavigationConnected = false;
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-        bAddress = 0;
-        bPollEnable = false;
-        return 0;
-}
-
-uint8_t PS3USB::Poll() {
-        if(!bPollEnable)
-                return 0;
-
-        if(PS3Connected || PS3NavigationConnected) {
-                uint16_t BUFFER_SIZE = EP_MAXPKTSIZE;
-                pUsb->inTransfer(bAddress, epInfo[ PS3_INPUT_PIPE ].epAddr, &BUFFER_SIZE, readBuf); // input on endpoint 1
-                if(millis() - timer > 100) { // Loop 100ms before processing data
-                        readReport();
-#ifdef PRINTREPORT
-                        printReport(); // Uncomment "#define PRINTREPORT" to print the report send by the PS3 Controllers
-#endif
-                }
-        } else if(PS3MoveConnected) { // One can only set the color of the bulb, set the rumble, set and get the bluetooth address and calibrate the magnetometer via USB
-                if(millis() - timer > 4000) { // Send at least every 4th second
-                        Move_Command(writeBuf, MOVE_REPORT_BUFFER_SIZE); // The Bulb and rumble values, has to be written again and again, for it to stay turned on
-                        timer = millis();
-                }
-        }
-        return 0;
-}
-
-void PS3USB::readReport() {
-        ButtonState = (uint32_t)(readBuf[2] | ((uint16_t)readBuf[3] << 8) | ((uint32_t)readBuf[4] << 16));
-
-        //Notify(PSTR("\r\nButtonState", 0x80);
-        //PrintHex<uint32_t>(ButtonState, 0x80);
-
-        if(ButtonState != OldButtonState) {
-                ButtonClickState = ButtonState & ~OldButtonState; // Update click state variable
-                OldButtonState = ButtonState;
-        }
-}
-
-void PS3USB::printReport() { // Uncomment "#define PRINTREPORT" to print the report send by the PS3 Controllers
-#ifdef PRINTREPORT
-        for(uint8_t i = 0; i < PS3_REPORT_BUFFER_SIZE; i++) {
-                D_PrintHex<uint8_t > (readBuf[i], 0x80);
-                Notify(PSTR(" "), 0x80);
-        }
-        Notify(PSTR("\r\n"), 0x80);
-#endif
-}
-
-bool PS3USB::getButtonPress(ButtonEnum b) {
-        return (ButtonState & pgm_read_dword(&PS3_BUTTONS[(uint8_t)b]));
-}
-
-bool PS3USB::getButtonClick(ButtonEnum b) {
-        uint32_t button = pgm_read_dword(&PS3_BUTTONS[(uint8_t)b]);
-        bool click = (ButtonClickState & button);
-        ButtonClickState &= ~button; // Clear "click" event
-        return click;
-}
-
-uint8_t PS3USB::getAnalogButton(ButtonEnum a) {
-        return (uint8_t)(readBuf[(pgm_read_byte(&PS3_ANALOG_BUTTONS[(uint8_t)a])) - 9]);
-}
-
-uint8_t PS3USB::getAnalogHat(AnalogHatEnum a) {
-        return (uint8_t)(readBuf[((uint8_t)a + 6)]);
-}
-
-uint16_t PS3USB::getSensor(SensorEnum a) {
-        return ((readBuf[((uint16_t)a) - 9] << 8) | readBuf[((uint16_t)a + 1) - 9]);
-}
-
-double PS3USB::getAngle(AngleEnum a) {
-        if(PS3Connected) {
-                double accXval;
-                double accYval;
-                double accZval;
-
-                // Data for the Kionix KXPC4 used in the DualShock 3
-                const double zeroG = 511.5; // 1.65/3.3*1023 (1,65V)
-                accXval = -((double)getSensor(aX) - zeroG);
-                accYval = -((double)getSensor(aY) - zeroG);
-                accZval = -((double)getSensor(aZ) - zeroG);
-
-                // Convert to 360 degrees resolution
-                // atan2 outputs the value of -π to π (radians)
-                // We are then converting it to 0 to 2π and then to degrees
-                if(a == Pitch)
-                        return (atan2(accYval, accZval) + PI) * RAD_TO_DEG;
-                else
-                        return (atan2(accXval, accZval) + PI) * RAD_TO_DEG;
-        } else
-                return 0;
-}
-
-bool PS3USB::getStatus(StatusEnum c) {
-        return (readBuf[((uint16_t)c >> 8) - 9] == ((uint8_t)c & 0xff));
-}
-
-void PS3USB::printStatusString() {
-        char statusOutput[100]; // Max string length plus null character
-        if(PS3Connected || PS3NavigationConnected) {
-                strcpy_P(statusOutput, PSTR("ConnectionStatus: "));
-
-                if(getStatus(Plugged)) strcat_P(statusOutput, PSTR("Plugged"));
-                else if(getStatus(Unplugged)) strcat_P(statusOutput, PSTR("Unplugged"));
-                else strcat_P(statusOutput, PSTR("Error"));
-
-                strcat_P(statusOutput, PSTR(" - PowerRating: "));
-
-                if(getStatus(Charging)) strcat_P(statusOutput, PSTR("Charging"));
-                else if(getStatus(NotCharging)) strcat_P(statusOutput, PSTR("Not Charging"));
-                else if(getStatus(Shutdown)) strcat_P(statusOutput, PSTR("Shutdown"));
-                else if(getStatus(Dying)) strcat_P(statusOutput, PSTR("Dying"));
-                else if(getStatus(Low)) strcat_P(statusOutput, PSTR("Low"));
-                else if(getStatus(High)) strcat_P(statusOutput, PSTR("High"));
-                else if(getStatus(Full)) strcat_P(statusOutput, PSTR("Full"));
-                else strcat_P(statusOutput, PSTR("Error"));
-
-                strcat_P(statusOutput, PSTR(" - WirelessStatus: "));
-
-                if(getStatus(CableRumble)) strcat_P(statusOutput, PSTR("Cable - Rumble is on"));
-                else if(getStatus(Cable)) strcat_P(statusOutput, PSTR("Cable - Rumble is off"));
-                else if(getStatus(BluetoothRumble)) strcat_P(statusOutput, PSTR("Bluetooth - Rumble is on"));
-                else if(getStatus(Bluetooth)) strcat_P(statusOutput, PSTR("Bluetooth - Rumble is off"));
-                else strcat_P(statusOutput, PSTR("Error"));
-        } else
-                strcpy_P(statusOutput, PSTR("Error"));
-
-        USB_HOST_SERIAL.write(statusOutput);
-}
-
-/* Playstation Sixaxis Dualshock and Navigation Controller commands */
-void PS3USB::PS3_Command(uint8_t *data, uint16_t nbytes) {
-        // bmRequest = Host to device (0x00) | Class (0x20) | Interface (0x01) = 0x21, bRequest = Set Report (0x09), Report ID (0x01), Report Type (Output 0x02), interface (0x00), datalength, datalength, data)
-        pUsb->ctrlReq(bAddress, epInfo[PS3_CONTROL_PIPE].epAddr, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, 0x01, 0x02, 0x00, nbytes, nbytes, data, NULL);
-}
-
-void PS3USB::setAllOff() {
-        for(uint8_t i = 0; i < PS3_REPORT_BUFFER_SIZE; i++)
-                writeBuf[i] = pgm_read_byte(&PS3_REPORT_BUFFER[i]); // Reset buffer
-
-        PS3_Command(writeBuf, PS3_REPORT_BUFFER_SIZE);
-}
-
-void PS3USB::setRumbleOff() {
-        writeBuf[1] = 0x00;
-        writeBuf[2] = 0x00; // Low mode off
-        writeBuf[3] = 0x00;
-        writeBuf[4] = 0x00; // High mode off
-
-        PS3_Command(writeBuf, PS3_REPORT_BUFFER_SIZE);
-}
-
-void PS3USB::setRumbleOn(RumbleEnum mode) {
-        if((mode & 0x30) > 0x00) {
-                uint8_t power[2] = {0xff, 0x00}; // Defaults to RumbleLow
-                if(mode == RumbleHigh) {
-                        power[0] = 0x00;
-                        power[1] = 0xff;
-                }
-                setRumbleOn(0xfe, power[0], 0xfe, power[1]);
-        }
-}
-
-void PS3USB::setRumbleOn(uint8_t rightDuration, uint8_t rightPower, uint8_t leftDuration, uint8_t leftPower) {
-        writeBuf[1] = rightDuration;
-        writeBuf[2] = rightPower;
-        writeBuf[3] = leftDuration;
-        writeBuf[4] = leftPower;
-        PS3_Command(writeBuf, PS3_REPORT_BUFFER_SIZE);
-}
-
-void PS3USB::setLedRaw(uint8_t value) {
-        writeBuf[9] = value << 1;
-        PS3_Command(writeBuf, PS3_REPORT_BUFFER_SIZE);
-}
-
-void PS3USB::setLedOff(LEDEnum a) {
-        writeBuf[9] &= ~((uint8_t)((pgm_read_byte(&PS3_LEDS[(uint8_t)a]) & 0x0f) << 1));
-        PS3_Command(writeBuf, PS3_REPORT_BUFFER_SIZE);
-}
-
-void PS3USB::setLedOn(LEDEnum a) {
-        if(a == OFF)
-                setLedRaw(0);
-        else {
-                writeBuf[9] |= (uint8_t)((pgm_read_byte(&PS3_LEDS[(uint8_t)a]) & 0x0f) << 1);
-                PS3_Command(writeBuf, PS3_REPORT_BUFFER_SIZE);
-        }
-}
-
-void PS3USB::setLedToggle(LEDEnum a) {
-        writeBuf[9] ^= (uint8_t)((pgm_read_byte(&PS3_LEDS[(uint8_t)a]) & 0x0f) << 1);
-        PS3_Command(writeBuf, PS3_REPORT_BUFFER_SIZE);
-}
-
-void PS3USB::setBdaddr(uint8_t *bdaddr) {
-        /* Set the internal Bluetooth address */
-        uint8_t buf[8];
-        buf[0] = 0x01;
-        buf[1] = 0x00;
-
-        for(uint8_t i = 0; i < 6; i++)
-                buf[i + 2] = bdaddr[5 - i]; // Copy into buffer, has to be written reversed, so it is MSB first
-
-        // bmRequest = Host to device (0x00) | Class (0x20) | Interface (0x01) = 0x21, bRequest = Set Report (0x09), Report ID (0xF5), Report Type (Feature 0x03), interface (0x00), datalength, datalength, data
-        pUsb->ctrlReq(bAddress, epInfo[PS3_CONTROL_PIPE].epAddr, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, 0xF5, 0x03, 0x00, 8, 8, buf, NULL);
-}
-
-void PS3USB::getBdaddr(uint8_t *bdaddr) {
-        uint8_t buf[8];
-
-        // bmRequest = Device to host (0x80) | Class (0x20) | Interface (0x01) = 0xA1, bRequest = Get Report (0x01), Report ID (0xF5), Report Type (Feature 0x03), interface (0x00), datalength, datalength, data
-        pUsb->ctrlReq(bAddress, epInfo[PS3_CONTROL_PIPE].epAddr, bmREQ_HID_IN, HID_REQUEST_GET_REPORT, 0xF5, 0x03, 0x00, 8, 8, buf, NULL);
-
-        for(uint8_t i = 0; i < 6; i++)
-                bdaddr[5 - i] = buf[i + 2]; // Copy into buffer reversed, so it is LSB first
-}
-
-void PS3USB::enable_sixaxis() { // Command used to enable the Dualshock 3 and Navigation controller to send data via USB
-        uint8_t cmd_buf[4];
-        cmd_buf[0] = 0x42; // Special PS3 Controller enable commands
-        cmd_buf[1] = 0x0c;
-        cmd_buf[2] = 0x00;
-        cmd_buf[3] = 0x00;
-
-        // bmRequest = Host to device (0x00) | Class (0x20) | Interface (0x01) = 0x21, bRequest = Set Report (0x09), Report ID (0xF4), Report Type (Feature 0x03), interface (0x00), datalength, datalength, data)
-        pUsb->ctrlReq(bAddress, epInfo[PS3_CONTROL_PIPE].epAddr, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, 0xF4, 0x03, 0x00, 4, 4, cmd_buf, NULL);
-}
-
-/* Playstation Move Controller commands */
-void PS3USB::Move_Command(uint8_t *data, uint16_t nbytes) {
-        pUsb->outTransfer(bAddress, epInfo[ PS3_OUTPUT_PIPE ].epAddr, nbytes, data);
-}
-
-void PS3USB::moveSetBulb(uint8_t r, uint8_t g, uint8_t b) { // Use this to set the Color using RGB values
-        // Set the Bulb's values into the write buffer
-        writeBuf[2] = r;
-        writeBuf[3] = g;
-        writeBuf[4] = b;
-
-        Move_Command(writeBuf, MOVE_REPORT_BUFFER_SIZE);
-}
-
-void PS3USB::moveSetBulb(ColorsEnum color) { // Use this to set the Color using the predefined colors in "enums.h"
-        moveSetBulb((uint8_t)(color >> 16), (uint8_t)(color >> 8), (uint8_t)(color));
-}
-
-void PS3USB::moveSetRumble(uint8_t rumble) {
-#ifdef DEBUG_USB_HOST
-        if(rumble < 64 && rumble != 0) // The rumble value has to at least 64, or approximately 25% (64/255*100)
-                Notify(PSTR("\r\nThe rumble value has to at least 64, or approximately 25%"), 0x80);
-#endif
-        writeBuf[6] = rumble; // Set the rumble value into the write buffer
-
-        Move_Command(writeBuf, MOVE_REPORT_BUFFER_SIZE);
-}
-
-void PS3USB::setMoveBdaddr(uint8_t *bdaddr) {
-        /* Set the internal Bluetooth address */
-        uint8_t buf[11];
-        buf[0] = 0x05;
-        buf[7] = 0x10;
-        buf[8] = 0x01;
-        buf[9] = 0x02;
-        buf[10] = 0x12;
-
-        for(uint8_t i = 0; i < 6; i++)
-                buf[i + 1] = bdaddr[i];
-
-        // bmRequest = Host to device (0x00) | Class (0x20) | Interface (0x01) = 0x21, bRequest = Set Report (0x09), Report ID (0x05), Report Type (Feature 0x03), interface (0x00), datalength, datalength, data
-        pUsb->ctrlReq(bAddress, epInfo[PS3_CONTROL_PIPE].epAddr, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, 0x05, 0x03, 0x00, 11, 11, buf, NULL);
-}
-
-void PS3USB::getMoveBdaddr(uint8_t *bdaddr) {
-        uint8_t buf[16];
-
-        // bmRequest = Device to host (0x80) | Class (0x20) | Interface (0x01) = 0xA1, bRequest = Get Report (0x01), Report ID (0x04), Report Type (Feature 0x03), interface (0x00), datalength, datalength, data
-        pUsb->ctrlReq(bAddress, epInfo[PS3_CONTROL_PIPE].epAddr, bmREQ_HID_IN, HID_REQUEST_GET_REPORT, 0x04, 0x03, 0x00, 16, 16, buf, NULL);
-
-        for(uint8_t i = 0; i < 6; i++)
-                bdaddr[i] = buf[10 + i];
-}
-
-void PS3USB::getMoveCalibration(uint8_t *data) {
-        uint8_t buf[49];
-
-        for(uint8_t i = 0; i < 3; i++) {
-                // bmRequest = Device to host (0x80) | Class (0x20) | Interface (0x01) = 0xA1, bRequest = Get Report (0x01), Report ID (0x10), Report Type (Feature 0x03), interface (0x00), datalength, datalength, data
-                pUsb->ctrlReq(bAddress, epInfo[PS3_CONTROL_PIPE].epAddr, bmREQ_HID_IN, HID_REQUEST_GET_REPORT, 0x10, 0x03, 0x00, 49, 49, buf, NULL);
-
-                for(byte j = 0; j < 49; j++)
-                        data[49 * i + j] = buf[j];
-        }
-}
-
-void PS3USB::onInit() {
-        if(pFuncOnInit)
-                pFuncOnInit(); // Call the user function
-        else {
-                if(PS3MoveConnected)
-                        moveSetBulb(Red);
-                else // Dualshock 3 or Navigation controller
-                        setLedOn(LED1);
-        }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PS3USB.h b/lib/usbhost/USB_Host_Shield_2.0/PS3USB.h
deleted file mode 100644
index 2eba9258cf..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PS3USB.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _ps3usb_h_
-#define _ps3usb_h_
-
-#include "Usb.h"
-#include "hid.h"
-#include "PS3Enums.h"
-
-/* PS3 data taken from descriptors */
-#define EP_MAXPKTSIZE           64 // max size for data via USB
-
-/* Names we give to the 3 ps3 pipes - this is only used for setting the bluetooth address into the ps3 controllers */
-#define PS3_CONTROL_PIPE        0
-#define PS3_OUTPUT_PIPE         1
-#define PS3_INPUT_PIPE          2
-
-//PID and VID of the different devices
-#define PS3_VID                 0x054C  // Sony Corporation
-#define PS3_PID                 0x0268  // PS3 Controller DualShock 3
-#define PS3NAVIGATION_PID       0x042F  // Navigation controller
-#define PS3MOVE_PID             0x03D5  // Motion controller
-
-#define PS3_MAX_ENDPOINTS       3
-
-/**
- * This class implements support for all the official PS3 Controllers:
- * Dualshock 3, Navigation or a Motion controller via USB.
- *
- * One can only set the color of the bulb, set the rumble, set and get the bluetooth address and calibrate the magnetometer via USB on the Move controller.
- *
- * Information about the protocol can be found at the wiki: https://github.com/felis/USB_Host_Shield_2.0/wiki/PS3-Information.
- */
-class PS3USB : public USBDeviceConfig {
-public:
-        /**
-         * Constructor for the PS3USB class.
-         * @param  pUsb   Pointer to USB class instance.
-         * @param  btadr5,btadr4,btadr3,btadr2,btadr1,btadr0
-         * Pass your dongles Bluetooth address into the constructor,
-         * so you are able to pair the controller with a Bluetooth dongle.
-         */
-        PS3USB(USB *pUsb, uint8_t btadr5 = 0, uint8_t btadr4 = 0, uint8_t btadr3 = 0, uint8_t btadr2 = 0, uint8_t btadr1 = 0, uint8_t btadr0 = 0);
-
-        /** @name USBDeviceConfig implementation */
-        /**
-         * Initialize the PS3 Controller.
-         * @param  parent   Hub number.
-         * @param  port     Port number on the hub.
-         * @param  lowspeed Speed of the device.
-         * @return          0 on success.
-         */
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        /**
-         * Release the USB device.
-         * @return 0 on success.
-         */
-        uint8_t Release();
-        /**
-         * Poll the USB Input endpoins and run the state machines.
-         * @return 0 on success.
-         */
-        uint8_t Poll();
-
-        /**
-         * Get the device address.
-         * @return The device address.
-         */
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        /**
-         * Used to check if the controller has been initialized.
-         * @return True if it's ready.
-         */
-        virtual bool isReady() {
-                return bPollEnable;
-        };
-
-        /**
-         * Used by the USB core to check what this driver support.
-         * @param  vid The device's VID.
-         * @param  pid The device's PID.
-         * @return     Returns true if the device's VID and PID matches this driver.
-         */
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return (vid == PS3_VID && (pid == PS3_PID || pid == PS3NAVIGATION_PID || pid == PS3MOVE_PID));
-        };
-        /**@}*/
-
-        /**
-         * Used to set the Bluetooth address inside the Dualshock 3 and Navigation controller.
-         * Set using LSB first.
-         * @param bdaddr Your dongles Bluetooth address.
-         */
-        void setBdaddr(uint8_t *bdaddr);
-        /**
-         * Used to get the Bluetooth address inside the Dualshock 3 and Navigation controller.
-         * Will return LSB first.
-         * @param bdaddr Your dongles Bluetooth address.
-         */
-        void getBdaddr(uint8_t *bdaddr);
-
-        /**
-         * Used to set the Bluetooth address inside the Move controller.
-         * Set using LSB first.
-         * @param bdaddr Your dongles Bluetooth address.
-         */
-        void setMoveBdaddr(uint8_t *bdaddr);
-        /**
-         * Used to get the Bluetooth address inside the Move controller.
-         * Will return LSB first.
-         * @param bdaddr Your dongles Bluetooth address.
-         */
-        void getMoveBdaddr(uint8_t *bdaddr);
-        /**
-         * Used to get the calibration data inside the Move controller.
-         * @param data Buffer to store data in. Must be at least 147 bytes
-         */
-        void getMoveCalibration(uint8_t *data);
-
-        /** @name PS3 Controller functions */
-        /**
-         * getButtonPress(ButtonEnum b) will return true as long as the button is held down.
-         *
-         * While getButtonClick(ButtonEnum b) will only return it once.
-         *
-         * So you instance if you need to increase a variable once you would use getButtonClick(ButtonEnum b),
-         * but if you need to drive a robot forward you would use getButtonPress(ButtonEnum b).
-         * @param  b          ::ButtonEnum to read.
-         * @return            getButtonPress(ButtonEnum b) will return a true as long as a button is held down, while getButtonClick(ButtonEnum b) will return true once for each button press.
-         */
-        bool getButtonPress(ButtonEnum b);
-        bool getButtonClick(ButtonEnum b);
-        /**@}*/
-        /** @name PS3 Controller functions */
-        /**
-         * Used to get the analog value from button presses.
-         * @param  a The ::ButtonEnum to read.
-         * The supported buttons are:
-         * ::UP, ::RIGHT, ::DOWN, ::LEFT, ::L1, ::L2, ::R1, ::R2,
-         * ::TRIANGLE, ::CIRCLE, ::CROSS, ::SQUARE, and ::T.
-         * @return   Analog value in the range of 0-255.
-         */
-        uint8_t getAnalogButton(ButtonEnum a);
-        /**
-         * Used to read the analog joystick.
-         * @param  a ::LeftHatX, ::LeftHatY, ::RightHatX, and ::RightHatY.
-         * @return   Return the analog value in the range of 0-255.
-         */
-        uint8_t getAnalogHat(AnalogHatEnum a);
-        /**
-         * Used to read the sensors inside the Dualshock 3 controller.
-         * @param  a
-         * The Dualshock 3 has a 3-axis accelerometer and a 1-axis gyro inside.
-         * @return   Return the raw sensor value.
-         */
-        uint16_t getSensor(SensorEnum a);
-        /**
-         * Use this to get ::Pitch and ::Roll calculated using the accelerometer.
-         * @param  a Either ::Pitch or ::Roll.
-         * @return   Return the angle in the range of 0-360.
-         */
-        double getAngle(AngleEnum a);
-        /**
-         * Get the ::StatusEnum from the controller.
-         * @param  c The ::StatusEnum you want to read.
-         * @return   True if correct and false if not.
-         */
-        bool getStatus(StatusEnum c);
-        /** Read all the available statuses from the controller and prints it as a nice formated string. */
-        void printStatusString();
-
-        /** Used to set all LEDs and rumble off. */
-        void setAllOff();
-        /** Turn off rumble. */
-        void setRumbleOff();
-        /**
-         * Turn on rumble.
-         * @param mode Either ::RumbleHigh or ::RumbleLow.
-         */
-        void setRumbleOn(RumbleEnum mode);
-        /**
-         * Turn on rumble using custom duration and power.
-         * @param rightDuration The duration of the right/low rumble effect.
-         * @param rightPower The intensity of the right/low rumble effect.
-         * @param leftDuration The duration of the left/high rumble effect.
-         * @param leftPower The intensity of the left/high rumble effect.
-         */
-        void setRumbleOn(uint8_t rightDuration, uint8_t rightPower, uint8_t leftDuration, uint8_t leftPower);
-
-        /**
-         * Set LED value without using the ::LEDEnum.
-         * @param value See: ::LEDEnum.
-         */
-        void setLedRaw(uint8_t value);
-
-        /** Turn all LEDs off. */
-        void setLedOff() {
-                setLedRaw(0);
-        }
-        /**
-         * Turn the specific ::LEDEnum off.
-         * @param a The ::LEDEnum to turn off.
-         */
-        void setLedOff(LEDEnum a);
-        /**
-         * Turn the specific ::LEDEnum on.
-         * @param a The ::LEDEnum to turn on.
-         */
-        void setLedOn(LEDEnum a);
-        /**
-         * Toggle the specific ::LEDEnum.
-         * @param a The ::LEDEnum to toggle.
-         */
-        void setLedToggle(LEDEnum a);
-
-        /**
-         * Use this to set the Color using RGB values.
-         * @param r,g,b RGB value.
-         */
-        void moveSetBulb(uint8_t r, uint8_t g, uint8_t b);
-        /**
-         * Use this to set the color using the predefined colors in ::ColorsEnum.
-         * @param color The desired color.
-         */
-        void moveSetBulb(ColorsEnum color);
-        /**
-         * Set the rumble value inside the Move controller.
-         * @param rumble The desired value in the range from 64-255.
-         */
-        void moveSetRumble(uint8_t rumble);
-
-        /**
-         * Used to call your own function when the controller is successfully initialized.
-         * @param funcOnInit Function to call.
-         */
-        void attachOnInit(void (*funcOnInit)(void)) {
-                pFuncOnInit = funcOnInit;
-        };
-        /**@}*/
-
-        /** Variable used to indicate if the normal playstation controller is successfully connected. */
-        bool PS3Connected;
-        /** Variable used to indicate if the move controller is successfully connected. */
-        bool PS3MoveConnected;
-        /** Variable used to indicate if the navigation controller is successfully connected. */
-        bool PS3NavigationConnected;
-
-protected:
-        /** Pointer to USB class instance. */
-        USB *pUsb;
-        /** Device address. */
-        uint8_t bAddress;
-        /** Endpoint info structure. */
-        EpInfo epInfo[PS3_MAX_ENDPOINTS];
-
-private:
-        /**
-         * Called when the controller is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        void onInit();
-        void (*pFuncOnInit)(void); // Pointer to function called in onInit()
-
-        bool bPollEnable;
-
-        uint32_t timer; // used to continuously set PS3 Move controller Bulb and rumble values
-
-        uint32_t ButtonState;
-        uint32_t OldButtonState;
-        uint32_t ButtonClickState;
-
-        uint8_t my_bdaddr[6]; // Change to your dongles Bluetooth address in the constructor
-        uint8_t readBuf[EP_MAXPKTSIZE]; // General purpose buffer for input data
-        uint8_t writeBuf[EP_MAXPKTSIZE]; // General purpose buffer for output data
-
-        void readReport(); // read incoming data
-        void printReport(); // print incoming date - Uncomment for debugging
-
-        /* Private commands */
-        void PS3_Command(uint8_t *data, uint16_t nbytes);
-        void enable_sixaxis(); // Command used to enable the Dualshock 3 and Navigation controller to send data via USB
-        void Move_Command(uint8_t *data, uint16_t nbytes);
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PS4BT.h b/lib/usbhost/USB_Host_Shield_2.0/PS4BT.h
deleted file mode 100644
index b7eb4b5a91..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PS4BT.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright (C) 2014 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _ps4bt_h_
-#define _ps4bt_h_
-
-#include "BTHID.h"
-#include "PS4Parser.h"
-
-/**
- * This class implements support for the PS4 controller via Bluetooth.
- * It uses the BTHID class for all the Bluetooth communication.
- */
-class PS4BT : public BTHID, public PS4Parser {
-public:
-        /**
-         * Constructor for the PS4BT class.
-         * @param  p     Pointer to the BTD class instance.
-         * @param  pair  Set this to true in order to pair with the device. If the argument is omitted then it will not pair with it. One can use ::PAIR to set it to true.
-         * @param  pin   Write the pin to BTD#btdPin. If argument is omitted, then "0000" will be used.
-         */
-        PS4BT(BTD *p, bool pair = false, const char *pin = "0000") :
-        BTHID(p, pair, pin) {
-                PS4Parser::Reset();
-        };
-
-        /**
-         * Used to check if a PS4 controller is connected.
-         * @return Returns true if it is connected.
-         */
-        bool connected() {
-                return BTHID::connected;
-        };
-
-protected:
-        /** @name BTHID implementation */
-        /**
-         * Used to parse Bluetooth HID data.
-         * @param len The length of the incoming data.
-         * @param buf Pointer to the data buffer.
-         */
-        virtual void ParseBTHIDData(uint8_t len, uint8_t *buf) {
-                PS4Parser::Parse(len, buf);
-        };
-
-        /**
-         * Called when a device is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        virtual void OnInitBTHID() {
-                PS4Parser::Reset();
-                enable_sixaxis(); // Make the controller send out the entire output report
-                if (pFuncOnInit)
-                        pFuncOnInit(); // Call the user function
-                else
-                        setLed(Blue);
-        };
-
-        /** Used to reset the different buffers to there default values */
-        virtual void ResetBTHID() {
-                PS4Parser::Reset();
-        };
-        /**@}*/
-
-        /** @name PS4Parser implementation */
-        virtual void sendOutputReport(PS4Output *output) { // Source: https://github.com/chrippa/ds4drv
-                uint8_t buf[79];
-                memset(buf, 0, sizeof(buf));
-
-                buf[0] = 0x52; // HID BT Set_report (0x50) | Report Type (Output 0x02)
-                buf[1] = 0x11; // Report ID
-                buf[2] = 0x80;
-                buf[4]= 0xFF;
-
-                buf[7] = output->smallRumble; // Small Rumble
-                buf[8] = output->bigRumble; // Big rumble
-
-                buf[9] = output->r; // Red
-                buf[10] = output->g; // Green
-                buf[11] = output->b; // Blue
-
-                buf[12] = output->flashOn; // Time to flash bright (255 = 2.5 seconds)
-                buf[13] = output->flashOff; // Time to flash dark (255 = 2.5 seconds)
-
-                output->reportChanged = false;
-
-                // The PS4 console actually set the four last bytes to a CRC32 checksum, but it seems like it is actually not needed
-
-                HID_Command(buf, sizeof(buf));
-        };
-        /**@}*/
-
-private:
-        void enable_sixaxis() { // Command used to make the PS4 controller send out the entire output report
-                uint8_t buf[2];
-                buf[0] = 0x43; // HID BT Get_report (0x40) | Report Type (Feature 0x03)
-                buf[1] = 0x02; // Report ID
-
-                HID_Command(buf, 2);
-        };
-
-        void HID_Command(uint8_t *data, uint8_t nbytes) {
-                pBtd->L2CAP_Command(hci_handle, data, nbytes, control_scid[0], control_scid[1]);
-        };
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PS4Parser.cpp b/lib/usbhost/USB_Host_Shield_2.0/PS4Parser.cpp
deleted file mode 100644
index ca6adce403..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PS4Parser.cpp
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright (C) 2014 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#include "PS4Parser.h"
-
-// To enable serial debugging see "settings.h"
-//#define PRINTREPORT // Uncomment to print the report send by the PS4 Controller
-
-bool PS4Parser::checkDpad(ButtonEnum b) {
-        switch (b) {
-                case UP:
-                        return ps4Data.btn.dpad == DPAD_LEFT_UP || ps4Data.btn.dpad == DPAD_UP || ps4Data.btn.dpad == DPAD_UP_RIGHT;
-                case RIGHT:
-                        return ps4Data.btn.dpad == DPAD_UP_RIGHT || ps4Data.btn.dpad == DPAD_RIGHT || ps4Data.btn.dpad == DPAD_RIGHT_DOWN;
-                case DOWN:
-                        return ps4Data.btn.dpad == DPAD_RIGHT_DOWN || ps4Data.btn.dpad == DPAD_DOWN || ps4Data.btn.dpad == DPAD_DOWN_LEFT;
-                case LEFT:
-                        return ps4Data.btn.dpad == DPAD_DOWN_LEFT || ps4Data.btn.dpad == DPAD_LEFT || ps4Data.btn.dpad == DPAD_LEFT_UP;
-                default:
-                        return false;
-        }
-}
-
-bool PS4Parser::getButtonPress(ButtonEnum b) {
-        if (b <= LEFT) // Dpad
-                return checkDpad(b);
-        else
-                return ps4Data.btn.val & (1UL << pgm_read_byte(&PS4_BUTTONS[(uint8_t)b]));
-}
-
-bool PS4Parser::getButtonClick(ButtonEnum b) {
-        uint32_t mask = 1UL << pgm_read_byte(&PS4_BUTTONS[(uint8_t)b]);
-        bool click = buttonClickState.val & mask;
-        buttonClickState.val &= ~mask; // Clear "click" event
-        return click;
-}
-
-uint8_t PS4Parser::getAnalogButton(ButtonEnum b) {
-        if (b == L2) // These are the only analog buttons on the controller
-                return ps4Data.trigger[0];
-        else if (b == R2)
-                return ps4Data.trigger[1];
-        return 0;
-}
-
-uint8_t PS4Parser::getAnalogHat(AnalogHatEnum a) {
-        return ps4Data.hatValue[(uint8_t)a];
-}
-
-void PS4Parser::Parse(uint8_t len, uint8_t *buf) {
-        if (len > 1 && buf)  {
-#ifdef PRINTREPORT
-                Notify(PSTR("\r\n"), 0x80);
-                for (uint8_t i = 0; i < len; i++) {
-                        D_PrintHex<uint8_t > (buf[i], 0x80);
-                        Notify(PSTR(" "), 0x80);
-                }
-#endif
-
-                if (buf[0] == 0x01) // Check report ID
-                        memcpy(&ps4Data, buf + 1, min((uint8_t)(len - 1), sizeof(ps4Data)));
-                else if (buf[0] == 0x11) { // This report is send via Bluetooth, it has an offset of 2 compared to the USB data
-                        if (len < 4) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nReport is too short: "), 0x80);
-                                D_PrintHex<uint8_t > (len, 0x80);
-#endif
-                                return;
-                        }
-                        memcpy(&ps4Data, buf + 3, min((uint8_t)(len - 3), sizeof(ps4Data)));
-                } else {
-#ifdef DEBUG_USB_HOST
-                        Notify(PSTR("\r\nUnknown report id: "), 0x80);
-                        D_PrintHex<uint8_t > (buf[0], 0x80);
-#endif
-                        return;
-                }
-
-                if (ps4Data.btn.val != oldButtonState.val) { // Check if anything has changed
-                        buttonClickState.val = ps4Data.btn.val & ~oldButtonState.val; // Update click state variable
-                        oldButtonState.val = ps4Data.btn.val;
-
-                        // The DPAD buttons does not set the different bits, but set a value corresponding to the buttons pressed, we will simply set the bits ourself
-                        uint8_t newDpad = 0;
-                        if (checkDpad(UP))
-                                newDpad |= 1 << UP;
-                        if (checkDpad(RIGHT))
-                                newDpad |= 1 << RIGHT;
-                        if (checkDpad(DOWN))
-                                newDpad |= 1 << DOWN;
-                        if (checkDpad(LEFT))
-                                newDpad |= 1 << LEFT;
-                        if (newDpad != oldDpad) {
-                                buttonClickState.dpad = newDpad & ~oldDpad; // Override values
-                                oldDpad = newDpad;
-                        }
-                }
-        }
-
-        if (ps4Output.reportChanged)
-                sendOutputReport(&ps4Output); // Send output report
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PS4Parser.h b/lib/usbhost/USB_Host_Shield_2.0/PS4Parser.h
deleted file mode 100644
index 51f0806361..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PS4Parser.h
+++ /dev/null
@@ -1,407 +0,0 @@
-/* Copyright (C) 2014 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _ps4parser_h_
-#define _ps4parser_h_
-
-#include "Usb.h"
-#include "controllerEnums.h"
-
-/** Buttons on the controller */
-const uint8_t PS4_BUTTONS[] PROGMEM = {
-        UP, // UP
-        RIGHT, // RIGHT
-        DOWN, // DOWN
-        LEFT, // LEFT
-
-        0x0C, // SHARE
-        0x0D, // OPTIONS
-        0x0E, // L3
-        0x0F, // R3
-
-        0x0A, // L2
-        0x0B, // R2
-        0x08, // L1
-        0x09, // R1
-
-        0x07, // TRIANGLE
-        0x06, // CIRCLE
-        0x05, // CROSS
-        0x04, // SQUARE
-
-        0x10, // PS
-        0x11, // TOUCHPAD
-};
-
-union PS4Buttons {
-        struct {
-                uint8_t dpad : 4;
-                uint8_t square : 1;
-                uint8_t cross : 1;
-                uint8_t circle : 1;
-                uint8_t triangle : 1;
-
-                uint8_t l1 : 1;
-                uint8_t r1 : 1;
-                uint8_t l2 : 1;
-                uint8_t r2 : 1;
-                uint8_t share : 1;
-                uint8_t options : 1;
-                uint8_t l3 : 1;
-                uint8_t r3 : 1;
-
-                uint8_t ps : 1;
-                uint8_t touchpad : 1;
-                uint8_t reportCounter : 6;
-        } __attribute__((packed));
-        uint32_t val : 24;
-} __attribute__((packed));
-
-struct touchpadXY {
-        uint8_t dummy; // I can not figure out what this data is for, it seems to change randomly, maybe a timestamp?
-        struct {
-                uint8_t counter : 7; // Increments every time a finger is touching the touchpad
-                uint8_t touching : 1; // The top bit is cleared if the finger is touching the touchpad
-                uint16_t x : 12;
-                uint16_t y : 12;
-        } __attribute__((packed)) finger[2]; // 0 = first finger, 1 = second finger
-} __attribute__((packed));
-
-struct PS4Status {
-        uint8_t battery : 4;
-        uint8_t usb : 1;
-        uint8_t audio : 1;
-        uint8_t mic : 1;
-        uint8_t unknown : 1; // Extension port?
-} __attribute__((packed));
-
-struct PS4Data {
-        /* Button and joystick values */
-        uint8_t hatValue[4];
-        PS4Buttons btn;
-        uint8_t trigger[2];
-
-        /* Gyro and accelerometer values */
-        uint8_t dummy[3]; // First two looks random, while the third one might be some kind of status - it increments once in a while
-        int16_t gyroY, gyroZ, gyroX;
-        int16_t accX, accZ, accY;
-
-        uint8_t dummy2[5];
-        PS4Status status;
-        uint8_t dummy3[3];
-
-        /* The rest is data for the touchpad */
-        touchpadXY xy[3]; // It looks like it sends out three coordinates each time, this might be because the microcontroller inside the PS4 controller is much faster than the Bluetooth connection.
-                          // The last data is read from the last position in the array while the oldest measurement is from the first position.
-                          // The first position will also keep it's value after the finger is released, while the other two will set them to zero.
-                          // Note that if you read fast enough from the device, then only the first one will contain any data.
-
-        // The last three bytes are always: 0x00, 0x80, 0x00
-} __attribute__((packed));
-
-struct PS4Output {
-        uint8_t bigRumble, smallRumble; // Rumble
-        uint8_t r, g, b; // RGB
-        uint8_t flashOn, flashOff; // Time to flash bright/dark (255 = 2.5 seconds)
-        bool reportChanged; // The data is send when data is received from the controller
-} __attribute__((packed));
-
-enum DPADEnum {
-        DPAD_UP = 0x0,
-        DPAD_UP_RIGHT = 0x1,
-        DPAD_RIGHT = 0x2,
-        DPAD_RIGHT_DOWN = 0x3,
-        DPAD_DOWN = 0x4,
-        DPAD_DOWN_LEFT = 0x5,
-        DPAD_LEFT = 0x6,
-        DPAD_LEFT_UP = 0x7,
-        DPAD_OFF = 0x8,
-};
-
-/** This class parses all the data sent by the PS4 controller */
-class PS4Parser {
-public:
-        /** Constructor for the PS4Parser class. */
-        PS4Parser() {
-                Reset();
-        };
-
-        /** @name PS4 Controller functions */
-        /**
-         * getButtonPress(ButtonEnum b) will return true as long as the button is held down.
-         *
-         * While getButtonClick(ButtonEnum b) will only return it once.
-         *
-         * So you instance if you need to increase a variable once you would use getButtonClick(ButtonEnum b),
-         * but if you need to drive a robot forward you would use getButtonPress(ButtonEnum b).
-         * @param  b          ::ButtonEnum to read.
-         * @return            getButtonPress(ButtonEnum b) will return a true as long as a button is held down, while getButtonClick(ButtonEnum b) will return true once for each button press.
-         */
-        bool getButtonPress(ButtonEnum b);
-        bool getButtonClick(ButtonEnum b);
-        /**@}*/
-        /** @name PS4 Controller functions */
-        /**
-         * Used to get the analog value from button presses.
-         * @param  b The ::ButtonEnum to read.
-         * The supported buttons are:
-         * ::UP, ::RIGHT, ::DOWN, ::LEFT, ::L1, ::L2, ::R1, ::R2,
-         * ::TRIANGLE, ::CIRCLE, ::CROSS, ::SQUARE, and ::T.
-         * @return   Analog value in the range of 0-255.
-         */
-        uint8_t getAnalogButton(ButtonEnum b);
-
-        /**
-         * Used to read the analog joystick.
-         * @param  a ::LeftHatX, ::LeftHatY, ::RightHatX, and ::RightHatY.
-         * @return   Return the analog value in the range of 0-255.
-         */
-        uint8_t getAnalogHat(AnalogHatEnum a);
-
-        /**
-         * Get the x-coordinate of the touchpad. Position 0 is in the top left.
-         * @param  finger 0 = first finger, 1 = second finger. If omitted, then 0 will be used.
-         * @param  xyId   The controller sends out three packets with the same structure.
-         *                The third one will contain the last measure, but if you read from the controller then there is only be data in the first one.
-         *                For that reason it will be set to 0 if the argument is omitted.
-         * @return        Returns the x-coordinate of the finger.
-         */
-        uint16_t getX(uint8_t finger = 0, uint8_t xyId = 0) {
-                return ps4Data.xy[xyId].finger[finger].x;
-        };
-
-        /**
-         * Get the y-coordinate of the touchpad. Position 0 is in the top left.
-         * @param  finger 0 = first finger, 1 = second finger. If omitted, then 0 will be used.
-         * @param  xyId   The controller sends out three packets with the same structure.
-         *                The third one will contain the last measure, but if you read from the controller then there is only be data in the first one.
-         *                For that reason it will be set to 0 if the argument is omitted.
-         * @return        Returns the y-coordinate of the finger.
-         */
-        uint16_t getY(uint8_t finger = 0, uint8_t xyId = 0) {
-                return ps4Data.xy[xyId].finger[finger].y;
-        };
-
-        /**
-         * Returns whenever the user is toucing the touchpad.
-         * @param  finger 0 = first finger, 1 = second finger. If omitted, then 0 will be used.
-         * @param  xyId   The controller sends out three packets with the same structure.
-         *                The third one will contain the last measure, but if you read from the controller then there is only be data in the first one.
-         *                For that reason it will be set to 0 if the argument is omitted.
-         * @return        Returns true if the specific finger is touching the touchpad.
-         */
-        bool isTouching(uint8_t finger = 0, uint8_t xyId = 0) {
-                return !(ps4Data.xy[xyId].finger[finger].touching); // The bit is cleared when a finger is touching the touchpad
-        };
-
-        /**
-         * This counter increments every time a finger touches the touchpad.
-         * @param  finger 0 = first finger, 1 = second finger. If omitted, then 0 will be used.
-         * @param  xyId   The controller sends out three packets with the same structure.
-         *                The third one will contain the last measure, but if you read from the controller then there is only be data in the first one.
-         *                For that reason it will be set to 0 if the argument is omitted.
-         * @return        Return the value of the counter, note that it is only a 7-bit value.
-         */
-        uint8_t getTouchCounter(uint8_t finger = 0, uint8_t xyId = 0) {
-                return ps4Data.xy[xyId].finger[finger].counter;
-        };
-
-        /**
-         * Get the angle of the controller calculated using the accelerometer.
-         * @param  a Either ::Pitch or ::Roll.
-         * @return   Return the angle in the range of 0-360.
-         */
-        double getAngle(AngleEnum a) {
-                if (a == Pitch)
-                        return (atan2(ps4Data.accY, ps4Data.accZ) + PI) * RAD_TO_DEG;
-                else
-                        return (atan2(ps4Data.accX, ps4Data.accZ) + PI) * RAD_TO_DEG;
-        };
-
-        /**
-         * Used to get the raw values from the 3-axis gyroscope and 3-axis accelerometer inside the PS4 controller.
-         * @param  s The sensor to read.
-         * @return   Returns the raw sensor reading.
-         */
-        int16_t getSensor(SensorEnum s) {
-                switch(s) {
-                        case gX:
-                                return ps4Data.gyroX;
-                        case gY:
-                                return ps4Data.gyroY;
-                        case gZ:
-                                return ps4Data.gyroZ;
-                        case aX:
-                                return ps4Data.accX;
-                        case aY:
-                                return ps4Data.accY;
-                        case aZ:
-                                return ps4Data.accZ;
-                        default:
-                                return 0;
-                }
-        };
-
-        /**
-         * Return the battery level of the PS4 controller.
-         * @return The battery level in the range 0-15.
-         */
-        uint8_t getBatteryLevel() {
-                return ps4Data.status.battery;
-        };
-
-        /**
-         * Use this to check if an USB cable is connected to the PS4 controller.
-         * @return Returns true if an USB cable is connected.
-         */
-        bool getUsbStatus() {
-                return ps4Data.status.usb;
-        };
-
-        /**
-         * Use this to check if an audio jack cable is connected to the PS4 controller.
-         * @return Returns true if an audio jack cable is connected.
-         */
-        bool getAudioStatus() {
-                return ps4Data.status.audio;
-        };
-
-        /**
-         * Use this to check if a microphone is connected to the PS4 controller.
-         * @return Returns true if a microphone is connected.
-         */
-        bool getMicStatus() {
-                return ps4Data.status.mic;
-        };
-
-        /** Turn both rumble and the LEDs off. */
-        void setAllOff() {
-                setRumbleOff();
-                setLedOff();
-        };
-
-        /** Set rumble off. */
-        void setRumbleOff() {
-                setRumbleOn(0, 0);
-        };
-
-        /**
-         * Turn on rumble.
-         * @param mode Either ::RumbleHigh or ::RumbleLow.
-         */
-        void setRumbleOn(RumbleEnum mode) {
-                if (mode == RumbleLow)
-                        setRumbleOn(0x00, 0xFF);
-                else
-                        setRumbleOn(0xFF, 0x00);
-        };
-
-        /**
-         * Turn on rumble.
-         * @param bigRumble   Value for big motor.
-         * @param smallRumble Value for small motor.
-         */
-        void setRumbleOn(uint8_t bigRumble, uint8_t smallRumble) {
-                ps4Output.bigRumble = bigRumble;
-                ps4Output.smallRumble = smallRumble;
-                ps4Output.reportChanged = true;
-        };
-
-        /** Turn all LEDs off. */
-        void setLedOff() {
-                setLed(0, 0, 0);
-        };
-
-        /**
-         * Use this to set the color using RGB values.
-         * @param r,g,b RGB value.
-         */
-        void setLed(uint8_t r, uint8_t g, uint8_t b) {
-                ps4Output.r = r;
-                ps4Output.g = g;
-                ps4Output.b = b;
-                ps4Output.reportChanged = true;
-        };
-
-        /**
-         * Use this to set the color using the predefined colors in ::ColorsEnum.
-         * @param color The desired color.
-         */
-        void setLed(ColorsEnum color) {
-                setLed((uint8_t)(color >> 16), (uint8_t)(color >> 8), (uint8_t)(color));
-        };
-
-        /**
-         * Set the LEDs flash time.
-         * @param flashOn  Time to flash bright (255 = 2.5 seconds).
-         * @param flashOff Time to flash dark (255 = 2.5 seconds).
-         */
-        void setLedFlash(uint8_t flashOn, uint8_t flashOff) {
-                ps4Output.flashOn = flashOn;
-                ps4Output.flashOff = flashOff;
-                ps4Output.reportChanged = true;
-        };
-        /**@}*/
-
-protected:
-        /**
-         * Used to parse data sent from the PS4 controller.
-         * @param len Length of the data.
-         * @param buf Pointer to the data buffer.
-         */
-        void Parse(uint8_t len, uint8_t *buf);
-
-        /** Used to reset the different buffers to their default values */
-        void Reset() {
-                uint8_t i;
-                for (i = 0; i < sizeof(ps4Data.hatValue); i++)
-                        ps4Data.hatValue[i] = 127; // Center value
-                ps4Data.btn.val = 0;
-                oldButtonState.val = 0;
-                for (i = 0; i < sizeof(ps4Data.trigger); i++)
-                        ps4Data.trigger[i] = 0;
-                for (i = 0; i < sizeof(ps4Data.xy)/sizeof(ps4Data.xy[0]); i++) {
-                        for (uint8_t j = 0; j < sizeof(ps4Data.xy[0].finger)/sizeof(ps4Data.xy[0].finger[0]); j++)
-                                ps4Data.xy[i].finger[j].touching = 1; // The bit is cleared if the finger is touching the touchpad
-                }
-
-                ps4Data.btn.dpad = DPAD_OFF;
-                oldButtonState.dpad = DPAD_OFF;
-                buttonClickState.dpad = 0;
-                oldDpad = 0;
-
-                ps4Output.bigRumble = ps4Output.smallRumble = 0;
-                ps4Output.r = ps4Output.g = ps4Output.b = 0;
-                ps4Output.flashOn = ps4Output.flashOff = 0;
-                ps4Output.reportChanged = false;
-        };
-
-        /**
-         * Send the output to the PS4 controller. This is implemented in PS4BT.h and PS4USB.h.
-         * @param output Pointer to PS4Output buffer;
-         */
-        virtual void sendOutputReport(PS4Output *output) = 0;
-
-private:
-        bool checkDpad(ButtonEnum b); // Used to check PS4 DPAD buttons
-
-        PS4Data ps4Data;
-        PS4Buttons oldButtonState, buttonClickState;
-        PS4Output ps4Output;
-        uint8_t oldDpad;
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PS4USB.h b/lib/usbhost/USB_Host_Shield_2.0/PS4USB.h
deleted file mode 100644
index b43079a6e9..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PS4USB.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright (C) 2014 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _ps4usb_h_
-#define _ps4usb_h_
-
-#include "hiduniversal.h"
-#include "PS4Parser.h"
-
-#define PS4_VID 0x054C // Sony Corporation
-#define PS4_PID 0x05C4 // PS4 Controller
-
-/**
- * This class implements support for the PS4 controller via USB.
- * It uses the HIDUniversal class for all the USB communication.
- */
-class PS4USB : public HIDUniversal, public PS4Parser {
-public:
-        /**
-         * Constructor for the PS4USB class.
-         * @param  p   Pointer to the USB class instance.
-         */
-        PS4USB(USB *p) :
-        HIDUniversal(p) {
-                PS4Parser::Reset();
-        };
-
-        /**
-         * Used to check if a PS4 controller is connected.
-         * @return Returns true if it is connected.
-         */
-        bool connected() {
-                return HIDUniversal::isReady() && HIDUniversal::VID == PS4_VID && HIDUniversal::PID == PS4_PID;
-        };
-
-        /**
-         * Used to call your own function when the device is successfully initialized.
-         * @param funcOnInit Function to call.
-         */
-        void attachOnInit(void (*funcOnInit)(void)) {
-                pFuncOnInit = funcOnInit;
-        };
-
-protected:
-        /** @name HIDUniversal implementation */
-        /**
-         * Used to parse USB HID data.
-         * @param hid       Pointer to the HID class.
-         * @param is_rpt_id Only used for Hubs.
-         * @param len       The length of the incoming data.
-         * @param buf       Pointer to the data buffer.
-         */
-        virtual void ParseHIDData(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf) {
-                if (HIDUniversal::VID == PS4_VID && HIDUniversal::PID == PS4_PID)
-                        PS4Parser::Parse(len, buf);
-        };
-
-        /**
-         * Called when a device is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        virtual uint8_t OnInitSuccessful() {
-                if (HIDUniversal::VID == PS4_VID && HIDUniversal::PID == PS4_PID) {
-                        PS4Parser::Reset();
-                        if (pFuncOnInit)
-                                pFuncOnInit(); // Call the user function
-                        else
-                                setLed(Blue);
-                };
-                return 0;
-        };
-        /**@}*/
-
-        /** @name PS4Parser implementation */
-        virtual void sendOutputReport(PS4Output *output) { // Source: https://github.com/chrippa/ds4drv
-                uint8_t buf[32];
-                memset(buf, 0, sizeof(buf));
-
-                buf[0] = 0x05; // Report ID
-                buf[1]= 0xFF;
-
-                buf[4] = output->smallRumble; // Small Rumble
-                buf[5] = output->bigRumble; // Big rumble
-
-                buf[6] = output->r; // Red
-                buf[7] = output->g; // Green
-                buf[8] = output->b; // Blue
-
-                buf[9] = output->flashOn; // Time to flash bright (255 = 2.5 seconds)
-                buf[10] = output->flashOff; // Time to flash dark (255 = 2.5 seconds)
-
-                output->reportChanged = false;
-
-                // The PS4 console actually set the four last bytes to a CRC32 checksum, but it seems like it is actually not needed
-
-                pUsb->outTransfer(bAddress, epInfo[ hidInterfaces[0].epIndex[epInterruptOutIndex] ].epAddr, sizeof(buf), buf);
-        };
-        /**@}*/
-
-        /** @name USBDeviceConfig implementation */
-        /**
-         * Used by the USB core to check what this driver support.
-         * @param  vid The device's VID.
-         * @param  pid The device's PID.
-         * @return     Returns true if the device's VID and PID matches this driver.
-         */
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return (vid == PS4_VID && pid == PS4_PID);
-        };
-        /**@}*/
-
-private:
-        void (*pFuncOnInit)(void); // Pointer to function called in onInit()
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PSBuzz.cpp b/lib/usbhost/USB_Host_Shield_2.0/PSBuzz.cpp
deleted file mode 100644
index 498164d5a6..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PSBuzz.cpp
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright (C) 2014 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#include "PSBuzz.h"
-
-// To enable serial debugging see "settings.h"
-//#define PRINTREPORT // Uncomment to print the report send by the PS Buzz Controllers
-
-void PSBuzz::ParseHIDData(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf) {
-        if (HIDUniversal::VID == PSBUZZ_VID && HIDUniversal::PID == PSBUZZ_PID && len > 2 && buf) {
-#ifdef PRINTREPORT
-                Notify(PSTR("\r\n"), 0x80);
-                for (uint8_t i = 0; i < len; i++) {
-                        D_PrintHex<uint8_t > (buf[i], 0x80);
-                        Notify(PSTR(" "), 0x80);
-                }
-#endif
-                memcpy(&psbuzzButtons, buf + 2, min((uint8_t)(len - 2), sizeof(psbuzzButtons)));
-
-                if (psbuzzButtons.val != oldButtonState.val) { // Check if anything has changed
-                        buttonClickState.val = psbuzzButtons.val & ~oldButtonState.val; // Update click state variable
-                        oldButtonState.val = psbuzzButtons.val;
-                }
-        }
-};
-
-uint8_t PSBuzz::OnInitSuccessful() {
-        if (HIDUniversal::VID == PSBUZZ_VID && HIDUniversal::PID == PSBUZZ_PID) {
-                Reset();
-                if (pFuncOnInit)
-                        pFuncOnInit(); // Call the user function
-                else
-                        setLedOnAll(); // Turn the LED on, on all four controllers
-        };
-        return 0;
-};
-
-bool PSBuzz::getButtonPress(ButtonEnum b, uint8_t controller) {
-        return psbuzzButtons.val & (1UL << (b + 5 * controller)); // Each controller uses 5 bits, so the value is shifted 5 for each controller
-};
-
-bool PSBuzz::getButtonClick(ButtonEnum b, uint8_t controller) {
-        uint32_t mask = (1UL << (b + 5 * controller)); // Each controller uses 5 bits, so the value is shifted 5 for each controller
-        bool click = buttonClickState.val & mask;
-        buttonClickState.val &= ~mask; // Clear "click" event
-        return click;
-};
-
-// Source: http://www.developerfusion.com/article/84338/making-usb-c-friendly/ and https://github.com/torvalds/linux/blob/master/drivers/hid/hid-sony.c
-void PSBuzz::setLedRaw(bool value, uint8_t controller) {
-        ledState[controller] = value; // Save value for next time it is called
-
-        uint8_t buf[7];
-        buf[0] = 0x00;
-        buf[1] = ledState[0] ? 0xFF : 0x00;
-        buf[2] = ledState[1] ? 0xFF : 0x00;
-        buf[3] = ledState[2] ? 0xFF : 0x00;
-        buf[4] = ledState[3] ? 0xFF : 0x00;
-        buf[5] = 0x00;
-        buf[6] = 0x00;
-
-        PSBuzz_Command(buf, sizeof(buf));
-};
-
-void PSBuzz::PSBuzz_Command(uint8_t *data, uint16_t nbytes) {
-        // bmRequest = Host to device (0x00) | Class (0x20) | Interface (0x01) = 0x21, bRequest = Set Report (0x09), Report ID (0x00), Report Type (Output 0x02), interface (0x00), datalength, datalength, data)
-        pUsb->ctrlReq(bAddress, epInfo[0].epAddr, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, 0x00, 0x02, 0x00, nbytes, nbytes, data, NULL);
-};
diff --git a/lib/usbhost/USB_Host_Shield_2.0/PSBuzz.h b/lib/usbhost/USB_Host_Shield_2.0/PSBuzz.h
deleted file mode 100644
index 8880d9e50a..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/PSBuzz.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* Copyright (C) 2014 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _psbuzz_h_
-#define _psbuzz_h_
-
-#include "hiduniversal.h"
-#include "controllerEnums.h"
-
-#define PSBUZZ_VID 0x054C // Sony Corporation
-#define PSBUZZ_PID 0x1000 // PS Buzz Controller
-
-/** Struct used to easily read the different buttons on the controllers */
-union PSBUZZButtons {
-        struct {
-                uint8_t red : 1;
-                uint8_t yellow : 1;
-                uint8_t green : 1;
-                uint8_t orange : 1;
-                uint8_t blue : 1;
-        } __attribute__((packed)) btn[4];
-        uint32_t val : 20;
-} __attribute__((packed));
-
-/**
- * This class implements support for the PS Buzz controllers via USB.
- * It uses the HIDUniversal class for all the USB communication.
- */
-class PSBuzz : public HIDUniversal {
-public:
-        /**
-         * Constructor for the PSBuzz class.
-         * @param  p   Pointer to the USB class instance.
-         */
-        PSBuzz(USB *p) :
-        HIDUniversal(p) {
-                Reset();
-        };
-
-        /**
-         * Used to check if a PS Buzz controller is connected.
-         * @return Returns true if it is connected.
-         */
-        bool connected() {
-                return HIDUniversal::isReady() && HIDUniversal::VID == PSBUZZ_VID && HIDUniversal::PID == PSBUZZ_PID;
-        };
-
-        /**
-         * Used to call your own function when the device is successfully initialized.
-         * @param funcOnInit Function to call.
-         */
-        void attachOnInit(void (*funcOnInit)(void)) {
-                pFuncOnInit = funcOnInit;
-        };
-
-        /** @name PS Buzzer Controller functions */
-        /**
-         * getButtonPress(ButtonEnum b) will return true as long as the button is held down.
-         *
-         * While getButtonClick(ButtonEnum b) will only return it once.
-         *
-         * So you instance if you need to increase a variable once you would use getButtonClick(ButtonEnum b),
-         * but if you need to drive a robot forward you would use getButtonPress(ButtonEnum b).
-         * @param  b          ::ButtonEnum to read.
-         * @param  controller The controller to read from. Default to 0.
-         * @return            getButtonPress(ButtonEnum b) will return a true as long as a button is held down, while getButtonClick(ButtonEnum b) will return true once for each button press.
-         */
-        bool getButtonPress(ButtonEnum b, uint8_t controller = 0);
-        bool getButtonClick(ButtonEnum b, uint8_t controller = 0);
-        /**@}*/
-        /** @name PS Buzzer Controller functions */
-        /**
-         * Set LED value without using ::LEDEnum.
-         * @param value See: ::LEDEnum.
-         */
-        /**
-         * Set LED values directly.
-         * @param value      Used to set whenever the LED should be on or off
-         * @param controller The controller to control. Defaults to 0.
-         */
-        void setLedRaw(bool value, uint8_t controller = 0);
-
-        /** Turn all LEDs off. */
-        void setLedOffAll() {
-                for (uint8_t i = 1; i < 4; i++) // Skip first as it will be set in setLedRaw
-                        ledState[i] = false; // Just an easy way to set all four off at the same time
-                setLedRaw(false); // Turn the LED off, on all four controllers
-        };
-
-        /**
-         * Turn the LED off on a specific controller.
-         * @param controller The controller to turn off. Defaults to 0.
-         */
-        void setLedOff(uint8_t controller = 0) {
-                setLedRaw(false, controller);
-        };
-
-
-        /** Turn all LEDs on. */
-        void setLedOnAll() {
-                for (uint8_t i = 1; i < 4; i++) // Skip first as it will be set in setLedRaw
-                        ledState[i] = true; // Just an easy way to set all four off at the same time
-                setLedRaw(true); // Turn the LED on, on all four controllers
-        };
-
-        /**
-         * Turn the LED on on a specific controller.
-         * @param controller The controller to turn off. Defaults to 0.
-         */
-        void setLedOn(uint8_t controller = 0) {
-                setLedRaw(true, controller);
-        };
-
-        /**
-         * Toggle the LED on a specific controller.
-         * @param controller The controller to turn off. Defaults to 0.
-         */
-        void setLedToggle(uint8_t controller = 0) {
-                setLedRaw(!ledState[controller], controller);
-        };
-        /**@}*/
-
-protected:
-        /** @name HIDUniversal implementation */
-        /**
-         * Used to parse USB HID data.
-         * @param hid       Pointer to the HID class.
-         * @param is_rpt_id Only used for Hubs.
-         * @param len       The length of the incoming data.
-         * @param buf       Pointer to the data buffer.
-         */
-        void ParseHIDData(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf);
-
-        /**
-         * Called when a device is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        uint8_t OnInitSuccessful();
-        /**@}*/
-
-        /** Used to reset the different buffers to their default values */
-        void Reset() {
-                psbuzzButtons.val = 0;
-                oldButtonState.val = 0;
-                buttonClickState.val = 0;
-                for (uint8_t i = 0; i < sizeof(ledState); i++)
-                        ledState[i] = 0;
-        };
-
-        /** @name USBDeviceConfig implementation */
-        /**
-         * Used by the USB core to check what this driver support.
-         * @param  vid The device's VID.
-         * @param  pid The device's PID.
-         * @return     Returns true if the device's VID and PID matches this driver.
-         */
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return (vid == PSBUZZ_VID && pid == PSBUZZ_PID);
-        };
-        /**@}*/
-
-private:
-        void (*pFuncOnInit)(void); // Pointer to function called in onInit()
-
-        void PSBuzz_Command(uint8_t *data, uint16_t nbytes);
-
-        PSBUZZButtons psbuzzButtons, oldButtonState, buttonClickState;
-        bool ledState[4];
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/README.md b/lib/usbhost/USB_Host_Shield_2.0/README.md
deleted file mode 100644
index 1eecb78ef2..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/README.md
+++ /dev/null
@@ -1,351 +0,0 @@
-# USB Host Library Rev.2.0
-
-The code is released under the GNU General Public License.
-__________
-
-# Summary
-This is Revision 2.0 of MAX3421E-based USB Host Shield Library for AVR's.
-
-Project main web site is: <http://www.circuitsathome.com>.
-
-Some information can also be found at: <http://blog.tkjelectronics.dk/>.
-
-The shield can be purchased at the main site: <https://www.circuitsathome.com/arduino_usb_host_shield_projects/> or from [TKJ Electronics](http://tkjelectronics.com/): <http://shop.tkjelectronics.dk/product_info.php?products_id=43>.
-
-![USB Host Shield](http://shop.tkjelectronics.dk/images/USB_Host_Shield1.jpg)
-
-For more information about the hardware see the [Hardware Manual](http://www.circuitsathome.com/usb-host-shield-hardware-manual).
-
-# Developed By
-
-* __Oleg Mazurov, Circuits@Home__ - <mazurov@circuitsathome.com>
-* __Alexei Glushchenko, Circuits@Home__ - <alex-gl@mail.ru>
-    * Developers of the USB Core, HID, FTDI, ADK, ACM, and PL2303 libraries
-* __Kristian Lauszus, TKJ Electronics__ - <kristianl@tkjelectronics.com>
-    * Developer of the [BTD](#bluetooth-libraries), [BTHID](#bthid-library), [SPP](#spp-library), [PS4](#ps4-library), [PS3](#ps3-library), [Wii](#wii-library), [Xbox](#xbox-library), and [PSBuzz](#ps-buzz-library) libraries
-* __Andrew Kroll__ - <xxxajk@gmail.com>
-    * Major contributor to mass storage code
-* __guruthree__
-    * [Xbox ONE](#xbox-one-library) controller support
-
-# Donate
-
-Help yourself by helping us support you! Many thousands of hours have been spent developing the USB Host Shield library. Since you find it useful, please consider donating via the button below. Donations will allow us to support you by ensuring hardware that you have can be acquired in order to add support for your microcontroller board.
-
-<a href="https://www.paypal.com/cgi-bin/webscr?cmd=_donations&amp;business=donate@circuitsathome.com&amp;lc=US&amp;item_name=Donate%20to%20the%20USB%20Host%20Library%20project&amp;no_note=0&amp;currency_code=USD&amp;bn=PP%2dDonationsBF%3abtn_donate_LG%2egif%3aNonHostedGuest"><img src="https://www.paypalobjects.com/en_US/i/btn/btn_donate_LG.gif" alt="PayPal - The safer, easier way to pay online!" /></a>
-
-# Table of Contents
-
-* [How to include the library](#how-to-include-the-library)
-    * [Arduino Library Manager](#arduino-library-manager)
-    * [Manual installation](#manual-installation)
-* [How to use the library](#how-to-use-the-library)
-    * [Documentation](#documentation)
-    * [Enable debugging](#enable-debugging)
-    * [Boards](#boards)
-    * [Bluetooth libraries](#bluetooth-libraries)
-    * [BTHID library](#bthid-library)
-    * [SPP library](#spp-library)
-    * [PS4 Library](#ps4-library)
-    * [PS3 Library](#ps3-library)
-    * [Xbox Libraries](#xbox-libraries)
-        * [Xbox library](#xbox-library)
-        * [Xbox 360 Library](#xbox-360-library)
-        * [Xbox ONE Library](#xbox-one-library)
-    * [Wii library](#wii-library)
-    * [PS Buzz Library](#ps-buzz-library)
-* [Interface modifications](#interface-modifications)
-* [FAQ](#faq)
-
-# How to include the library
-
-### Arduino Library Manager
-
-First install Arduino IDE version 1.6.2 or newer, then simply use the Arduino Library Manager to install the library.
-
-Please see the following page for instructions: <http://www.arduino.cc/en/Guide/Libraries#toc3>.
-
-### Manual installation
-
-First download the library by clicking on the following link: <https://github.com/felis/USB_Host_Shield_2.0/archive/master.zip>.
-
-Then uncompress the zip folder and rename the directory to "USB\_Host\_Shield\_20", as any special characters are not supported by the Arduino IDE.
-
-Now open up the Arduino IDE and open "File>Preferences". There you will see the location of your sketchbook. Open that directory and create a directory called "libraries" inside that directory.
-Now move the "USB\_Host\_Shield\_20" directory to the "libraries" directory.
-
-The final structure should look like this:
-
-* Arduino/
-    * libraries/
-        * USB\_Host\_Shield\_20/
-
-Now quit the Arduino IDE and reopen it.
-
-Now you should be able to go open all the examples codes by navigating to "File>Examples>USB\_Host\_Shield\_20" and then select the example you will like to open.
-
-For more information visit the following sites: <http://arduino.cc/en/Guide/Libraries> and <https://learn.adafruit.com/adafruit-all-about-arduino-libraries-install-use>.
-
-# How to use the library
-
-### Documentation
-
-Documentation for the library can be found at the following link: <http://felis.github.com/USB_Host_Shield_2.0/>.
-
-### Enable debugging
-
-By default serial debugging is disabled. To turn it on simply change ```ENABLE_UHS_DEBUGGING``` to 1 in [settings.h](settings.h) like so:
-
-```C++
-#define ENABLE_UHS_DEBUGGING 1
-```
-
-### Boards
-
-Currently the following boards are supported by the library:
-
-* All official Arduino AVR boards (Uno, Duemilanove, Mega, Mega 2560, Mega ADK, Leonardo etc.)
-* Arduino Due, Intel Galileo, Intel Galileo 2, and Intel Edison
-    * Note that the Intel Galileo uses pin 2 and 3 as INT and SS pin respectively by default, so some modifications to the shield are needed. See the "Interface modifications" section in the [hardware manual](https://www.circuitsathome.com/usb-host-shield-hardware-manual) for more information.
-* Teensy (Teensy++ 1.0, Teensy 2.0, Teensy++ 2.0, and Teensy 3.x)
-    * Note if you are using the Teensy 3.x you should download this SPI library as well: <https://github.com/xxxajk/spi4teensy3>. You should then add ```#include <spi4teensy3.h>``` to your .ino file.
-* Balanduino
-* Sanguino
-* Black Widdow
-* RedBearLab nRF51822
-* Digilent chipKIT
-    * Please see: <http://www.circuitsathome.com/mcu/usb/running-usb-host-code-on-digilent-chipkit-board>.
-
-The following boards need to be activated manually in [settings.h](settings.h):
-
-* Arduino Mega ADK
-    * If you are using Arduino 1.5.5 or newer there is no need to activate the Arduino Mega ADK manually
-* Black Widdow
-
-Simply set the corresponding value to 1 instead of 0.
-
-### [Bluetooth libraries](BTD.cpp)
-
-The [BTD library](BTD.cpp) is a general purpose library for an ordinary Bluetooth dongle.
-This library make it easy to add support for different Bluetooth services like a PS3 or a Wii controller or SPP which is a virtual serial port via Bluetooth.
-Some different examples can be found in the [example directory](examples/Bluetooth).
-
-The BTD library also makes it possible to use multiple services at once, the following example sketch is an example of this:
-[PS3SPP.ino](examples/Bluetooth/PS3SPP/PS3SPP.ino).
-
-### [BTHID library](BTHID.cpp)
-
-The [Bluetooth HID library](BTHID.cpp) allows you to connect HID devices via Bluetooth to the USB Host Shield.
-
-Currently HID mice and keyboards are supported.
-
-It uses the standard Boot protocol by default, but it is also able to use the Report protocol as well. You would simply have to call ```setProtocolMode()``` and then parse ```HID_RPT_PROTOCOL``` as an argument. You will then have to modify the parser for your device. See the example: [BTHID.ino](examples/Bluetooth/BTHID/BTHID.ino) for more information.
-
-The [PS4 library](#ps4-library) also uses this class to handle all Bluetooth communication.
-
-For information see the following blog post: <http://blog.tkjelectronics.dk/2013/12/bluetooth-hid-devices-now-supported-by-the-usb-host-library/>.
-
-### [SPP library](SPP.cpp)
-
-SPP stands for "Serial Port Profile" and is a Bluetooth protocol that implements a virtual comport which allows you to send data back and forth from your computer/phone to your Arduino via Bluetooth.
-It has been tested successfully on Windows, Mac OS X, Linux, and Android.
-
-Take a look at the [SPP.ino](examples/Bluetooth/SPP/SPP.ino) example for more information.
-
-More information can be found at these blog posts:
-
-* <http://www.circuitsathome.com/mcu/bluetooth-rfcommspp-service-support-for-usb-host-2-0-library-released>
-* <http://blog.tkjelectronics.dk/2012/07/rfcommspp-library-for-arduino/>
-
-To implement the SPP protocol I used a Bluetooth sniffing tool called [PacketLogger](http://www.tkjelectronics.com/uploads/PacketLogger.zip) developed by Apple.
-It enables me to see the Bluetooth communication between my Mac and any device.
-
-### PS4 Library
-
-The PS4BT library is split up into the [PS4BT](PS4BT.h) and the [PS4USB](PS4USB.h) library. These allow you to use the Sony PS4 controller via Bluetooth and USB.
-
-The [PS4BT.ino](examples/Bluetooth/PS4BT/PS4BT.ino) and [PS4USB.ino](examples/PS4USB/PS4USB.ino) examples shows how to easily read the buttons, joysticks, touchpad and IMU on the controller via Bluetooth and USB respectively. It is also possible to control the rumble and light on the controller and get the battery level.
-
-Before you can use the PS4 controller via Bluetooth you will need to pair with it.
-
-Simply create the PS4BT instance like so: ```PS4BT PS4(&Btd, PAIR);``` and then hold down the Share button and then hold down the PS without releasing the Share button. The PS4 controller will then start to blink rapidly indicating that it is in paring mode.
-
-It should then automatically pair the dongle with your controller. This only have to be done once.
-
-For information see the following blog post: <http://blog.tkjelectronics.dk/2014/01/ps4-controller-now-supported-by-the-usb-host-library/>.
-
-Also check out this excellent Wiki by Frank Zhao about the PS4 controller: <http://eleccelerator.com/wiki/index.php?title=DualShock_4> and this Linux driver: <https://github.com/chrippa/ds4drv>.
-
-### PS3 Library
-
-These libraries consist of the [PS3BT](PS3BT.cpp) and [PS3USB](PS3USB.cpp). These libraries allows you to use a Dualshock 3, Navigation or a Motion controller with the USB Host Shield both via Bluetooth and USB.
-
-In order to use your Playstation controller via Bluetooth you have to set the Bluetooth address of the dongle internally to your PS3 Controller. This can be achieved by first plugging in the Bluetooth dongle and wait a few seconds. Now plug in the controller via USB and wait until the LEDs start to flash. The library has now written the Bluetooth address of the dongle to the PS3 controller.
-
-Finally simply plug in the Bluetooth dongle again and press PS on the PS3 controller. After a few seconds it should be connected to the dongle and ready to use.
-
-__Note:__ You will have to plug in the Bluetooth dongle before connecting the controller, as the library needs to read the address of the dongle. Alternatively you could set it in code like so: [PS3BT.ino#L20](examples/Bluetooth/PS3BT/PS3BT.ino#L20).
-
-For more information about the PS3 protocol see the official wiki: <https://github.com/felis/USB_Host_Shield_2.0/wiki/PS3-Information>.
-
-Also take a look at the blog posts:
-
-* <http://blog.tkjelectronics.dk/2012/01/ps3-controller-bt-library-for-arduino/>
-* <http://www.circuitsathome.com/mcu/sony-ps3-controller-support-added-to-usb-host-library>
-* <http://www.circuitsathome.com/mcu/arduino/interfacing-ps3-controllers-via-usb>
-
-A special thanks go to the following people:
-
-1. _Richard Ibbotson_ who made this excellent guide: <https://www.circuitsathome.com/mcu/ps3-and-wiimote-game-controllers-on-the-arduino-host-shield-part-1/>
-2. _Tomoyuki Tanaka_ for releasing his code for the Arduino USB Host shield connected to the wiimote: <http://www.circuitsathome.com/mcu/rc-car-controlled-by-wii-remote-on-arduino>
-
-Also a big thanks all the people behind these sites about the Motion controller:
-
-* <http://thp.io/2010/psmove/>
-* <http://www.copenhagengamecollective.org/unimove/>
-* <https://github.com/thp/psmoveapi>
-* <http://code.google.com/p/moveonpc/>
-
-### Xbox Libraries
-
-The library supports both the original Xbox controller via USB and the Xbox 360 controller both via USB and wirelessly.
-
-#### Xbox library
-
-The [XBOXOLD](XBOXOLD.cpp) class implements support for the original Xbox controller via USB.
-
-All the information are from the following sites:
-
-* <https://github.com/torvalds/linux/blob/master/Documentation/input/devices/xpad.rst>
-* <https://github.com/torvalds/linux/blob/master/drivers/input/joystick/xpad.c>
-* <http://euc.jp/periphs/xbox-controller.ja.html>
-* <https://github.com/Grumbel/xboxdrv/blob/stable/PROTOCOL#L15>
-
-#### Xbox 360 Library
-
-The library support one Xbox 360 via USB or up to four Xbox 360 controllers wirelessly by using a [Xbox 360 wireless receiver](http://blog.tkjelectronics.dk/wp-content/uploads/xbox360-wireless-receiver.jpg).
-
-To use it via USB use the [XBOXUSB](XBOXUSB.cpp) library or to use it wirelessly use the [XBOXRECV](XBOXRECV.cpp) library.
-
-__Note that a Wireless controller can NOT be used via USB!__
-
-Examples code can be found in the [examples directory](examples/Xbox).
-
-Also see the following blog posts:
-
-* <http://www.circuitsathome.com/mcu/xbox360-controller-support-added-to-usb-host-shield-2-0-library>
-* <http://blog.tkjelectronics.dk/2012/07/xbox-360-controller-support-added-to-the-usb-host-library/>
-* <http://blog.tkjelectronics.dk/2012/12/xbox-360-receiver-added-to-the-usb-host-library/>
-
-All the information regarding the Xbox 360 controller protocol are form these sites:
-
-* <http://tattiebogle.net/index.php/ProjectRoot/Xbox360Controller/UsbInfo>
-* <http://tattiebogle.net/index.php/ProjectRoot/Xbox360Controller/WirelessUsbInfo>
-* <https://github.com/Grumbel/xboxdrv/blob/stable/PROTOCOL>
-
-#### Xbox ONE Library
-
-An Xbox ONE controller is supported via USB in the [XBOXONE](XBOXONE.cpp) class. It is heavily based on the 360 library above. In addition to cross referencing the above, information on the protocol was found at:
-
-* <https://github.com/quantus/xbox-one-controller-protocol>
-* <https://github.com/torvalds/linux/blob/master/drivers/input/joystick/xpad.c>
-* <https://github.com/kylelemons/xbox/blob/master/xbox.go>
-
-### [Wii library](Wii.cpp)
-
-The [Wii](Wii.cpp) library support the Wiimote, but also the Nunchuch and Motion Plus extensions via Bluetooth. The Wii U Pro Controller and Wii Balance Board are also supported via Bluetooth.
-
-First you have to pair with the controller, this is done automatically by the library if you create the instance like so:
-
-```C++
-WII Wii(&Btd, PAIR);
-```
-
-And then press 1 & 2 at once on the Wiimote or the SYNC buttons if you are using a Wii U Pro Controller or a Wii Balance Board.
-
-After that you can simply create the instance like so:
-
-```C++
-WII Wii(&Btd);
-```
-
-Then just press any button on the Wiimote and it will then connect to the dongle.
-
-Take a look at the example for more information: [Wii.ino](examples/Bluetooth/Wii/Wii.ino).
-
-Also take a look at the blog post:
-
-* <http://blog.tkjelectronics.dk/2012/08/wiimote-added-to-usb-host-library/>
-
-The Wii IR camera can also be used, but you will have to activate the code for it manually as it is quite large. Simply set ```ENABLE_WII_IR_CAMERA``` to 1 in [settings.h](settings.h).
-
-The [WiiIRCamera.ino](examples/Bluetooth/WiiIRCamera/WiiIRCamera.ino) example shows how it can be used.
-
-All the information about the Wii controllers are from these sites:
-
-* <http://wiibrew.org/wiki/Wiimote>
-* <http://wiibrew.org/wiki/Wiimote/Extension_Controllers>
-* <http://wiibrew.org/wiki/Wiimote/Extension_Controllers/Nunchuck>
-* <http://wiibrew.org/wiki/Wiimote/Extension_Controllers/Wii_Motion_Plus>
-* <http://wiibrew.org/wiki/Wii_Balance_Board>
-* The old library created by _Tomoyuki Tanaka_: <https://github.com/moyuchin/WiiRemote_on_Arduino> also helped a lot.
-
-### [PS Buzz Library](PSBuzz.cpp)
-
-This library implements support for the Playstation Buzz controllers via USB.
-
-It is essentially just a wrapper around the [HIDUniversal](hiduniversal.cpp) which takes care of the initializing and reading of the controllers. The [PSBuzz](PSBuzz.cpp) class simply inherits this and parses the data, so it is easy for users to read the buttons and turn the big red button on the controllers on and off.
-
-The example [PSBuzz.ino](examples/PSBuzz/PSBuzz.ino) shows how one can do this with just a few lines of code.
-
-More information about the controller can be found at the following sites:
-
-* http://www.developerfusion.com/article/84338/making-usb-c-friendly/
-* https://github.com/torvalds/linux/blob/master/drivers/hid/hid-sony.c
-
-# Interface modifications
-
-The shield is using SPI for communicating with the MAX3421E USB host controller. It uses the SCK, MISO and MOSI pins via the ICSP on your board.
-
-Note this means that it uses pin 13, 12, 11 on an Arduino Uno, so these pins can not be used for anything else than SPI communication!
-
-Furthermore it uses one pin as SS and one INT pin. These are by default located on pin 10 and 9 respectively. They can easily be reconfigured in case you need to use them for something else by cutting the jumper on the shield and then solder a wire from the pad to the new pin.
-
-After that you need modify the following entry in [UsbCore.h](UsbCore.h):
-
-```C++
-typedef MAX3421e<P10, P9> MAX3421E;
-```
-
-For instance if you have rerouted SS to pin 7 it should read:
-
-```C++
-typedef MAX3421e<P7, P9> MAX3421E;
-```
-
-See the "Interface modifications" section in the [hardware manual](https://www.circuitsathome.com/usb-host-shield-hardware-manual) for more information.
-
-# FAQ
-
-> When I plug my device into the USB connector nothing happens?
-
-* Try to connect a external power supply to the Arduino - this solves the problem in most cases.
-* You can also use a powered hub between the device and the USB Host Shield. You should then include the USB hub library: ```#include <usbhub.h>``` and create the instance like so: ```USBHub Hub1(&Usb);```.
-
-> When I connecting my PS3 controller I get a output like this:
-
-```
-Dualshock 3 Controller Enabled
-
-LeftHatX: 0 LeftHatY: 0 RightHatX: 0 RightHatY: 0
-LeftHatX: 0 LeftHatY: 0 RightHatX: 0 RightHatY: 0
-LeftHatX: 0 LeftHatY: 0 RightHatX: 0 RightHatY: 0
-LeftHatX: 0 LeftHatY: 0 RightHatX: 0 RightHatY: 0
-LeftHatX: 0 LeftHatY: 0 RightHatX: 0 RightHatY: 0
-```
-
-* This means that your dongle does not support 2.0+EDR, so you will need another dongle. Please see the following [list](https://github.com/felis/USB_Host_Shield_2.0/wiki/Bluetooth-dongles) for tested working dongles.
-
-> When compiling I am getting the following error: "fatal error: SPI.h: No such file or directory".
-
-* Please make sure to include the SPI library like so: ```#include <SPI.h>``` in your .ino file.
diff --git a/lib/usbhost/USB_Host_Shield_2.0/SPP.cpp b/lib/usbhost/USB_Host_Shield_2.0/SPP.cpp
deleted file mode 100644
index 0f4ee5e981..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/SPP.cpp
+++ /dev/null
@@ -1,829 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#include "SPP.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-//#define PRINTREPORT // Uncomment to print the report sent to the Arduino
-
-/*
- * CRC (reversed crc) lookup table as calculated by the table generator in ETSI TS 101 369 V6.3.0.
- */
-const uint8_t rfcomm_crc_table[256] PROGMEM = {/* reversed, 8-bit, poly=0x07 */
-        0x00, 0x91, 0xE3, 0x72, 0x07, 0x96, 0xE4, 0x75, 0x0E, 0x9F, 0xED, 0x7C, 0x09, 0x98, 0xEA, 0x7B,
-        0x1C, 0x8D, 0xFF, 0x6E, 0x1B, 0x8A, 0xF8, 0x69, 0x12, 0x83, 0xF1, 0x60, 0x15, 0x84, 0xF6, 0x67,
-        0x38, 0xA9, 0xDB, 0x4A, 0x3F, 0xAE, 0xDC, 0x4D, 0x36, 0xA7, 0xD5, 0x44, 0x31, 0xA0, 0xD2, 0x43,
-        0x24, 0xB5, 0xC7, 0x56, 0x23, 0xB2, 0xC0, 0x51, 0x2A, 0xBB, 0xC9, 0x58, 0x2D, 0xBC, 0xCE, 0x5F,
-        0x70, 0xE1, 0x93, 0x02, 0x77, 0xE6, 0x94, 0x05, 0x7E, 0xEF, 0x9D, 0x0C, 0x79, 0xE8, 0x9A, 0x0B,
-        0x6C, 0xFD, 0x8F, 0x1E, 0x6B, 0xFA, 0x88, 0x19, 0x62, 0xF3, 0x81, 0x10, 0x65, 0xF4, 0x86, 0x17,
-        0x48, 0xD9, 0xAB, 0x3A, 0x4F, 0xDE, 0xAC, 0x3D, 0x46, 0xD7, 0xA5, 0x34, 0x41, 0xD0, 0xA2, 0x33,
-        0x54, 0xC5, 0xB7, 0x26, 0x53, 0xC2, 0xB0, 0x21, 0x5A, 0xCB, 0xB9, 0x28, 0x5D, 0xCC, 0xBE, 0x2F,
-        0xE0, 0x71, 0x03, 0x92, 0xE7, 0x76, 0x04, 0x95, 0xEE, 0x7F, 0x0D, 0x9C, 0xE9, 0x78, 0x0A, 0x9B,
-        0xFC, 0x6D, 0x1F, 0x8E, 0xFB, 0x6A, 0x18, 0x89, 0xF2, 0x63, 0x11, 0x80, 0xF5, 0x64, 0x16, 0x87,
-        0xD8, 0x49, 0x3B, 0xAA, 0xDF, 0x4E, 0x3C, 0xAD, 0xD6, 0x47, 0x35, 0xA4, 0xD1, 0x40, 0x32, 0xA3,
-        0xC4, 0x55, 0x27, 0xB6, 0xC3, 0x52, 0x20, 0xB1, 0xCA, 0x5B, 0x29, 0xB8, 0xCD, 0x5C, 0x2E, 0xBF,
-        0x90, 0x01, 0x73, 0xE2, 0x97, 0x06, 0x74, 0xE5, 0x9E, 0x0F, 0x7D, 0xEC, 0x99, 0x08, 0x7A, 0xEB,
-        0x8C, 0x1D, 0x6F, 0xFE, 0x8B, 0x1A, 0x68, 0xF9, 0x82, 0x13, 0x61, 0xF0, 0x85, 0x14, 0x66, 0xF7,
-        0xA8, 0x39, 0x4B, 0xDA, 0xAF, 0x3E, 0x4C, 0xDD, 0xA6, 0x37, 0x45, 0xD4, 0xA1, 0x30, 0x42, 0xD3,
-        0xB4, 0x25, 0x57, 0xC6, 0xB3, 0x22, 0x50, 0xC1, 0xBA, 0x2B, 0x59, 0xC8, 0xBD, 0x2C, 0x5E, 0xCF
-};
-
-SPP::SPP(BTD *p, const char* name, const char* pin) :
-BluetoothService(p) // Pointer to BTD class instance - mandatory
-{
-        pBtd->btdName = name;
-        pBtd->btdPin = pin;
-
-        /* Set device cid for the SDP and RFCOMM channelse */
-        sdp_dcid[0] = 0x50; // 0x0050
-        sdp_dcid[1] = 0x00;
-        rfcomm_dcid[0] = 0x51; // 0x0051
-        rfcomm_dcid[1] = 0x00;
-
-        Reset();
-}
-
-void SPP::Reset() {
-        connected = false;
-        RFCOMMConnected = false;
-        SDPConnected = false;
-        waitForLastCommand = false;
-        l2cap_sdp_state = L2CAP_SDP_WAIT;
-        l2cap_rfcomm_state = L2CAP_RFCOMM_WAIT;
-        l2cap_event_flag = 0;
-        sppIndex = 0;
-        creditSent = false;
-}
-
-void SPP::disconnect() {
-        connected = false;
-        // First the two L2CAP channels has to be disconnected and then the HCI connection
-        if(RFCOMMConnected)
-                pBtd->l2cap_disconnection_request(hci_handle, ++identifier, rfcomm_scid, rfcomm_dcid);
-        if(RFCOMMConnected && SDPConnected)
-                delay(1); // Add delay between commands
-        if(SDPConnected)
-                pBtd->l2cap_disconnection_request(hci_handle, ++identifier, sdp_scid, sdp_dcid);
-        l2cap_sdp_state = L2CAP_DISCONNECT_RESPONSE;
-}
-
-void SPP::ACLData(uint8_t* l2capinbuf) {
-        if(!connected) {
-                if(l2capinbuf[8] == L2CAP_CMD_CONNECTION_REQUEST) {
-                        if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == SDP_PSM && !pBtd->sdpConnectionClaimed) {
-                                pBtd->sdpConnectionClaimed = true;
-                                hci_handle = pBtd->hci_handle; // Store the HCI Handle for the connection
-                                l2cap_sdp_state = L2CAP_SDP_WAIT; // Reset state
-                        } else if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == RFCOMM_PSM && !pBtd->rfcommConnectionClaimed) {
-                                pBtd->rfcommConnectionClaimed = true;
-                                hci_handle = pBtd->hci_handle; // Store the HCI Handle for the connection
-                                l2cap_rfcomm_state = L2CAP_RFCOMM_WAIT; // Reset state
-                        }
-                }
-        }
-
-        if(checkHciHandle(l2capinbuf, hci_handle)) { // acl_handle_ok
-                if((l2capinbuf[6] | (l2capinbuf[7] << 8)) == 0x0001U) { // l2cap_control - Channel ID for ACL-U
-                        if(l2capinbuf[8] == L2CAP_CMD_COMMAND_REJECT) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nL2CAP Command Rejected - Reason: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[12], 0x80);
-                                Notify(PSTR(" Data: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[17], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[16], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[15], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-#endif
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONNECTION_REQUEST) {
-#ifdef EXTRADEBUG
-                                Notify(PSTR("\r\nL2CAP Connection Request - PSM: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[12], 0x80);
-                                Notify(PSTR(" SCID: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[15], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-                                Notify(PSTR(" Identifier: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[9], 0x80);
-#endif
-                                if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == SDP_PSM) { // It doesn't matter if it receives another reqeust, since it waits for the channel to disconnect in the L2CAP_SDP_DONE state, and the l2cap_event_flag will be cleared if so
-                                        identifier = l2capinbuf[9];
-                                        sdp_scid[0] = l2capinbuf[14];
-                                        sdp_scid[1] = l2capinbuf[15];
-                                        l2cap_set_flag(L2CAP_FLAG_CONNECTION_SDP_REQUEST);
-                                } else if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == RFCOMM_PSM) { // ----- || -----
-                                        identifier = l2capinbuf[9];
-                                        rfcomm_scid[0] = l2capinbuf[14];
-                                        rfcomm_scid[1] = l2capinbuf[15];
-                                        l2cap_set_flag(L2CAP_FLAG_CONNECTION_RFCOMM_REQUEST);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONFIG_RESPONSE) {
-                                if((l2capinbuf[16] | (l2capinbuf[17] << 8)) == 0x0000) { // Success
-                                        if(l2capinbuf[12] == sdp_dcid[0] && l2capinbuf[13] == sdp_dcid[1]) {
-                                                //Notify(PSTR("\r\nSDP Configuration Complete"), 0x80);
-                                                l2cap_set_flag(L2CAP_FLAG_CONFIG_SDP_SUCCESS);
-                                        } else if(l2capinbuf[12] == rfcomm_dcid[0] && l2capinbuf[13] == rfcomm_dcid[1]) {
-                                                //Notify(PSTR("\r\nRFCOMM Configuration Complete"), 0x80);
-                                                l2cap_set_flag(L2CAP_FLAG_CONFIG_RFCOMM_SUCCESS);
-                                        }
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONFIG_REQUEST) {
-                                if(l2capinbuf[12] == sdp_dcid[0] && l2capinbuf[13] == sdp_dcid[1]) {
-                                        //Notify(PSTR("\r\nSDP Configuration Request"), 0x80);
-                                        pBtd->l2cap_config_response(hci_handle, l2capinbuf[9], sdp_scid);
-                                } else if(l2capinbuf[12] == rfcomm_dcid[0] && l2capinbuf[13] == rfcomm_dcid[1]) {
-                                        //Notify(PSTR("\r\nRFCOMM Configuration Request"), 0x80);
-                                        pBtd->l2cap_config_response(hci_handle, l2capinbuf[9], rfcomm_scid);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_DISCONNECT_REQUEST) {
-                                if(l2capinbuf[12] == sdp_dcid[0] && l2capinbuf[13] == sdp_dcid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Request: SDP Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_SDP_REQUEST);
-                                } else if(l2capinbuf[12] == rfcomm_dcid[0] && l2capinbuf[13] == rfcomm_dcid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Request: RFCOMM Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_RFCOMM_REQUEST);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_DISCONNECT_RESPONSE) {
-                                if(l2capinbuf[12] == sdp_scid[0] && l2capinbuf[13] == sdp_scid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Response: SDP Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_RESPONSE);
-                                } else if(l2capinbuf[12] == rfcomm_scid[0] && l2capinbuf[13] == rfcomm_scid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Response: RFCOMM Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_RESPONSE);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_INFORMATION_REQUEST) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nInformation request"), 0x80);
-#endif
-                                identifier = l2capinbuf[9];
-                                pBtd->l2cap_information_response(hci_handle, identifier, l2capinbuf[12], l2capinbuf[13]);
-                        }
-#ifdef EXTRADEBUG
-                        else {
-                                Notify(PSTR("\r\nL2CAP Unknown Signaling Command: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[8], 0x80);
-                        }
-#endif
-                } else if(l2capinbuf[6] == sdp_dcid[0] && l2capinbuf[7] == sdp_dcid[1]) { // SDP
-                        if(l2capinbuf[8] == SDP_SERVICE_SEARCH_ATTRIBUTE_REQUEST_PDU) {
-                                if(((l2capinbuf[16] << 8 | l2capinbuf[17]) == SERIALPORT_UUID) || ((l2capinbuf[16] << 8 | l2capinbuf[17]) == 0x0000 && (l2capinbuf[18] << 8 | l2capinbuf[19]) == SERIALPORT_UUID)) { // Check if it's sending the full UUID, see: https://www.bluetooth.org/Technical/AssignedNumbers/service_discovery.htm, we will just check the first four bytes
-                                        if(firstMessage) {
-                                                serialPortResponse1(l2capinbuf[9], l2capinbuf[10]);
-                                                firstMessage = false;
-                                        } else {
-                                                serialPortResponse2(l2capinbuf[9], l2capinbuf[10]); // Serialport continuation state
-                                                firstMessage = true;
-                                        }
-                                } else if(((l2capinbuf[16] << 8 | l2capinbuf[17]) == L2CAP_UUID) || ((l2capinbuf[16] << 8 | l2capinbuf[17]) == 0x0000 && (l2capinbuf[18] << 8 | l2capinbuf[19]) == L2CAP_UUID)) {
-                                        if(firstMessage) {
-                                                l2capResponse1(l2capinbuf[9], l2capinbuf[10]);
-                                                firstMessage = false;
-                                        } else {
-                                                l2capResponse2(l2capinbuf[9], l2capinbuf[10]); // L2CAP continuation state
-                                                firstMessage = true;
-                                        }
-                                } else
-                                        serviceNotSupported(l2capinbuf[9], l2capinbuf[10]); // The service is not supported
-#ifdef EXTRADEBUG
-                                Notify(PSTR("\r\nUUID: "), 0x80);
-                                uint16_t uuid;
-                                if((l2capinbuf[16] << 8 | l2capinbuf[17]) == 0x0000) // Check if it's sending the UUID as a 128-bit UUID
-                                        uuid = (l2capinbuf[18] << 8 | l2capinbuf[19]);
-                                else // Short UUID
-                                        uuid = (l2capinbuf[16] << 8 | l2capinbuf[17]);
-                                D_PrintHex<uint16_t > (uuid, 0x80);
-
-                                Notify(PSTR("\r\nLength: "), 0x80);
-                                uint16_t length = l2capinbuf[11] << 8 | l2capinbuf[12];
-                                D_PrintHex<uint16_t > (length, 0x80);
-                                Notify(PSTR("\r\nData: "), 0x80);
-                                for(uint8_t i = 0; i < length; i++) {
-                                        D_PrintHex<uint8_t > (l2capinbuf[13 + i], 0x80);
-                                        Notify(PSTR(" "), 0x80);
-                                }
-#endif
-                        }
-#ifdef EXTRADEBUG
-                        else {
-                                Notify(PSTR("\r\nUnknown PDU: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[8], 0x80);
-                        }
-#endif
-                } else if(l2capinbuf[6] == rfcomm_dcid[0] && l2capinbuf[7] == rfcomm_dcid[1]) { // RFCOMM
-                        rfcommChannel = l2capinbuf[8] & 0xF8;
-                        rfcommDirection = l2capinbuf[8] & 0x04;
-                        rfcommCommandResponse = l2capinbuf[8] & 0x02;
-                        rfcommChannelType = l2capinbuf[9] & 0xEF;
-                        rfcommPfBit = l2capinbuf[9] & 0x10;
-
-                        if(rfcommChannel >> 3 != 0x00)
-                                rfcommChannelConnection = rfcommChannel;
-
-#ifdef EXTRADEBUG
-                        Notify(PSTR("\r\nRFCOMM Channel: "), 0x80);
-                        D_PrintHex<uint8_t > (rfcommChannel >> 3, 0x80);
-                        Notify(PSTR(" Direction: "), 0x80);
-                        D_PrintHex<uint8_t > (rfcommDirection >> 2, 0x80);
-                        Notify(PSTR(" CommandResponse: "), 0x80);
-                        D_PrintHex<uint8_t > (rfcommCommandResponse >> 1, 0x80);
-                        Notify(PSTR(" ChannelType: "), 0x80);
-                        D_PrintHex<uint8_t > (rfcommChannelType, 0x80);
-                        Notify(PSTR(" PF_BIT: "), 0x80);
-                        D_PrintHex<uint8_t > (rfcommPfBit, 0x80);
-#endif
-                        if(rfcommChannelType == RFCOMM_DISC) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nReceived Disconnect RFCOMM Command on channel: "), 0x80);
-                                D_PrintHex<uint8_t > (rfcommChannel >> 3, 0x80);
-#endif
-                                connected = false;
-                                sendRfcomm(rfcommChannel, rfcommDirection, rfcommCommandResponse, RFCOMM_UA, rfcommPfBit, rfcommbuf, 0x00); // UA Command
-                        }
-                        if(connected) {
-                                /* Read the incoming message */
-                                if(rfcommChannelType == RFCOMM_UIH && rfcommChannel == rfcommChannelConnection) {
-                                        uint8_t length = l2capinbuf[10] >> 1; // Get length
-                                        uint8_t offset = l2capinbuf[4] - length - 4; // Check if there is credit
-                                        if(checkFcs(&l2capinbuf[8], l2capinbuf[11 + length + offset])) {
-                                                uint8_t i = 0;
-                                                for(; i < length; i++) {
-                                                        if(rfcommAvailable + i >= sizeof (rfcommDataBuffer)) {
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nWarning: Buffer is full!"), 0x80);
-#endif
-                                                                break;
-                                                        }
-                                                        rfcommDataBuffer[rfcommAvailable + i] = l2capinbuf[11 + i + offset];
-                                                }
-                                                rfcommAvailable += i;
-#ifdef EXTRADEBUG
-                                                Notify(PSTR("\r\nRFCOMM Data Available: "), 0x80);
-                                                Notify(rfcommAvailable, 0x80);
-                                                if(offset) {
-                                                        Notify(PSTR(" - Credit: 0x"), 0x80);
-                                                        D_PrintHex<uint8_t > (l2capinbuf[11], 0x80);
-                                                }
-#endif
-                                        }
-#ifdef DEBUG_USB_HOST
-                                        else
-                                                Notify(PSTR("\r\nError in FCS checksum!"), 0x80);
-#endif
-#ifdef PRINTREPORT // Uncomment "#define PRINTREPORT" to print the report send to the Arduino via Bluetooth
-                                        for(uint8_t i = 0; i < length; i++)
-                                                Notifyc(l2capinbuf[i + 11 + offset], 0x80);
-#endif
-                                } else if(rfcommChannelType == RFCOMM_UIH && l2capinbuf[11] == BT_RFCOMM_RPN_CMD) { // UIH Remote Port Negotiation Command
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nReceived UIH Remote Port Negotiation Command"), 0x80);
-#endif
-                                        rfcommbuf[0] = BT_RFCOMM_RPN_RSP; // Command
-                                        rfcommbuf[1] = l2capinbuf[12]; // Length and shiftet like so: length << 1 | 1
-                                        rfcommbuf[2] = l2capinbuf[13]; // Channel: channel << 1 | 1
-                                        rfcommbuf[3] = l2capinbuf[14]; // Pre difined for Bluetooth, see 5.5.3 of TS 07.10 Adaption for RFCOMM
-                                        rfcommbuf[4] = l2capinbuf[15]; // Priority
-                                        rfcommbuf[5] = l2capinbuf[16]; // Timer
-                                        rfcommbuf[6] = l2capinbuf[17]; // Max Fram Size LSB
-                                        rfcommbuf[7] = l2capinbuf[18]; // Max Fram Size MSB
-                                        rfcommbuf[8] = l2capinbuf[19]; // MaxRatransm.
-                                        rfcommbuf[9] = l2capinbuf[20]; // Number of Frames
-                                        sendRfcomm(rfcommChannel, rfcommDirection, 0, RFCOMM_UIH, rfcommPfBit, rfcommbuf, 0x0A); // UIH Remote Port Negotiation Response
-                                } else if(rfcommChannelType == RFCOMM_UIH && l2capinbuf[11] == BT_RFCOMM_MSC_CMD) { // UIH Modem Status Command
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nSend UIH Modem Status Response"), 0x80);
-#endif
-                                        rfcommbuf[0] = BT_RFCOMM_MSC_RSP; // UIH Modem Status Response
-                                        rfcommbuf[1] = 2 << 1 | 1; // Length and shiftet like so: length << 1 | 1
-                                        rfcommbuf[2] = l2capinbuf[13]; // Channel: (1 << 0) | (1 << 1) | (0 << 2) | (channel << 3)
-                                        rfcommbuf[3] = l2capinbuf[14];
-                                        sendRfcomm(rfcommChannel, rfcommDirection, 0, RFCOMM_UIH, rfcommPfBit, rfcommbuf, 0x04);
-                                }
-                        } else {
-                                if(rfcommChannelType == RFCOMM_SABM) { // SABM Command - this is sent twice: once for channel 0 and then for the channel to establish
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nReceived SABM Command"), 0x80);
-#endif
-                                        sendRfcomm(rfcommChannel, rfcommDirection, rfcommCommandResponse, RFCOMM_UA, rfcommPfBit, rfcommbuf, 0x00); // UA Command
-                                } else if(rfcommChannelType == RFCOMM_UIH && l2capinbuf[11] == BT_RFCOMM_PN_CMD) { // UIH Parameter Negotiation Command
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nReceived UIH Parameter Negotiation Command"), 0x80);
-#endif
-                                        rfcommbuf[0] = BT_RFCOMM_PN_RSP; // UIH Parameter Negotiation Response
-                                        rfcommbuf[1] = l2capinbuf[12]; // Length and shiftet like so: length << 1 | 1
-                                        rfcommbuf[2] = l2capinbuf[13]; // Channel: channel << 1 | 1
-                                        rfcommbuf[3] = 0xE0; // Pre difined for Bluetooth, see 5.5.3 of TS 07.10 Adaption for RFCOMM
-                                        rfcommbuf[4] = 0x00; // Priority
-                                        rfcommbuf[5] = 0x00; // Timer
-                                        rfcommbuf[6] = BULK_MAXPKTSIZE - 14; // Max Fram Size LSB - set to the size of received data (50)
-                                        rfcommbuf[7] = 0x00; // Max Fram Size MSB
-                                        rfcommbuf[8] = 0x00; // MaxRatransm.
-                                        rfcommbuf[9] = 0x00; // Number of Frames
-                                        sendRfcomm(rfcommChannel, rfcommDirection, 0, RFCOMM_UIH, rfcommPfBit, rfcommbuf, 0x0A);
-                                } else if(rfcommChannelType == RFCOMM_UIH && l2capinbuf[11] == BT_RFCOMM_MSC_CMD) { // UIH Modem Status Command
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nSend UIH Modem Status Response"), 0x80);
-#endif
-                                        rfcommbuf[0] = BT_RFCOMM_MSC_RSP; // UIH Modem Status Response
-                                        rfcommbuf[1] = 2 << 1 | 1; // Length and shiftet like so: length << 1 | 1
-                                        rfcommbuf[2] = l2capinbuf[13]; // Channel: (1 << 0) | (1 << 1) | (0 << 2) | (channel << 3)
-                                        rfcommbuf[3] = l2capinbuf[14];
-                                        sendRfcomm(rfcommChannel, rfcommDirection, 0, RFCOMM_UIH, rfcommPfBit, rfcommbuf, 0x04);
-
-                                        delay(1);
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nSend UIH Modem Status Command"), 0x80);
-#endif
-                                        rfcommbuf[0] = BT_RFCOMM_MSC_CMD; // UIH Modem Status Command
-                                        rfcommbuf[1] = 2 << 1 | 1; // Length and shiftet like so: length << 1 | 1
-                                        rfcommbuf[2] = l2capinbuf[13]; // Channel: (1 << 0) | (1 << 1) | (0 << 2) | (channel << 3)
-                                        rfcommbuf[3] = 0x8D; // Can receive frames (YES), Ready to Communicate (YES), Ready to Receive (YES), Incomig Call (NO), Data is Value (YES)
-
-                                        sendRfcomm(rfcommChannel, rfcommDirection, 0, RFCOMM_UIH, rfcommPfBit, rfcommbuf, 0x04);
-                                } else if(rfcommChannelType == RFCOMM_UIH && l2capinbuf[11] == BT_RFCOMM_MSC_RSP) { // UIH Modem Status Response
-                                        if(!creditSent) {
-#ifdef DEBUG_USB_HOST
-                                                Notify(PSTR("\r\nSend UIH Command with credit"), 0x80);
-#endif
-                                                sendRfcommCredit(rfcommChannelConnection, rfcommDirection, 0, RFCOMM_UIH, 0x10, sizeof (rfcommDataBuffer)); // Send credit
-                                                creditSent = true;
-                                                timer = millis();
-                                                waitForLastCommand = true;
-                                        }
-                                } else if(rfcommChannelType == RFCOMM_UIH && l2capinbuf[10] == 0x01) { // UIH Command with credit
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nReceived UIH Command with credit"), 0x80);
-#endif
-                                } else if(rfcommChannelType == RFCOMM_UIH && l2capinbuf[11] == BT_RFCOMM_RPN_CMD) { // UIH Remote Port Negotiation Command
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nReceived UIH Remote Port Negotiation Command"), 0x80);
-#endif
-                                        rfcommbuf[0] = BT_RFCOMM_RPN_RSP; // Command
-                                        rfcommbuf[1] = l2capinbuf[12]; // Length and shiftet like so: length << 1 | 1
-                                        rfcommbuf[2] = l2capinbuf[13]; // Channel: channel << 1 | 1
-                                        rfcommbuf[3] = l2capinbuf[14]; // Pre difined for Bluetooth, see 5.5.3 of TS 07.10 Adaption for RFCOMM
-                                        rfcommbuf[4] = l2capinbuf[15]; // Priority
-                                        rfcommbuf[5] = l2capinbuf[16]; // Timer
-                                        rfcommbuf[6] = l2capinbuf[17]; // Max Fram Size LSB
-                                        rfcommbuf[7] = l2capinbuf[18]; // Max Fram Size MSB
-                                        rfcommbuf[8] = l2capinbuf[19]; // MaxRatransm.
-                                        rfcommbuf[9] = l2capinbuf[20]; // Number of Frames
-                                        sendRfcomm(rfcommChannel, rfcommDirection, 0, RFCOMM_UIH, rfcommPfBit, rfcommbuf, 0x0A); // UIH Remote Port Negotiation Response
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nRFCOMM Connection is now established\r\n"), 0x80);
-#endif
-                                        onInit();
-                                }
-#ifdef EXTRADEBUG
-                                else if(rfcommChannelType != RFCOMM_DISC) {
-                                        Notify(PSTR("\r\nUnsupported RFCOMM Data - ChannelType: "), 0x80);
-                                        D_PrintHex<uint8_t > (rfcommChannelType, 0x80);
-                                        Notify(PSTR(" Command: "), 0x80);
-                                        D_PrintHex<uint8_t > (l2capinbuf[11], 0x80);
-                                }
-#endif
-                        }
-                }
-#ifdef EXTRADEBUG
-                else {
-                        Notify(PSTR("\r\nUnsupported L2CAP Data - Channel ID: "), 0x80);
-                        D_PrintHex<uint8_t > (l2capinbuf[7], 0x80);
-                        Notify(PSTR(" "), 0x80);
-                        D_PrintHex<uint8_t > (l2capinbuf[6], 0x80);
-                }
-#endif
-                SDP_task();
-                RFCOMM_task();
-        }
-}
-
-void SPP::Run() {
-        if(waitForLastCommand && (millis() - timer) > 100) { // We will only wait 100ms and see if the UIH Remote Port Negotiation Command is send, as some deviced don't send it
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nRFCOMM Connection is now established - Automatic\r\n"), 0x80);
-#endif
-                onInit();
-        }
-        send(); // Send all bytes currently in the buffer
-}
-
-void SPP::onInit() {
-        creditSent = false;
-        waitForLastCommand = false;
-        connected = true; // The RFCOMM channel is now established
-        sppIndex = 0;
-        if(pFuncOnInit)
-                pFuncOnInit(); // Call the user function
-};
-
-void SPP::SDP_task() {
-        switch(l2cap_sdp_state) {
-                case L2CAP_SDP_WAIT:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONNECTION_SDP_REQUEST)) {
-                                l2cap_clear_flag(L2CAP_FLAG_CONNECTION_SDP_REQUEST); // Clear flag
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSDP Incoming Connection Request"), 0x80);
-#endif
-                                pBtd->l2cap_connection_response(hci_handle, identifier, sdp_dcid, sdp_scid, PENDING);
-                                delay(1);
-                                pBtd->l2cap_connection_response(hci_handle, identifier, sdp_dcid, sdp_scid, SUCCESSFUL);
-                                identifier++;
-                                delay(1);
-                                pBtd->l2cap_config_request(hci_handle, identifier, sdp_scid);
-                                l2cap_sdp_state = L2CAP_SDP_SUCCESS;
-                        } else if(l2cap_check_flag(L2CAP_FLAG_DISCONNECT_SDP_REQUEST)) {
-                                l2cap_clear_flag(L2CAP_FLAG_DISCONNECT_SDP_REQUEST); // Clear flag
-                                SDPConnected = false;
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nDisconnected SDP Channel"), 0x80);
-#endif
-                                pBtd->l2cap_disconnection_response(hci_handle, identifier, sdp_dcid, sdp_scid);
-                        }
-                        break;
-                case L2CAP_SDP_SUCCESS:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_SDP_SUCCESS)) {
-                                l2cap_clear_flag(L2CAP_FLAG_CONFIG_SDP_SUCCESS); // Clear flag
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSDP Successfully Configured"), 0x80);
-#endif
-                                firstMessage = true; // Reset bool
-                                SDPConnected = true;
-                                l2cap_sdp_state = L2CAP_SDP_WAIT;
-                        }
-                        break;
-
-                case L2CAP_DISCONNECT_RESPONSE: // This is for both disconnection response from the RFCOMM and SDP channel if they were connected
-                        if(l2cap_check_flag(L2CAP_FLAG_DISCONNECT_RESPONSE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nDisconnected L2CAP Connection"), 0x80);
-#endif
-                                pBtd->hci_disconnect(hci_handle);
-                                hci_handle = -1; // Reset handle
-                                Reset();
-                        }
-                        break;
-        }
-}
-
-void SPP::RFCOMM_task() {
-        switch(l2cap_rfcomm_state) {
-                case L2CAP_RFCOMM_WAIT:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONNECTION_RFCOMM_REQUEST)) {
-                                l2cap_clear_flag(L2CAP_FLAG_CONNECTION_RFCOMM_REQUEST); // Clear flag
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nRFCOMM Incoming Connection Request"), 0x80);
-#endif
-                                pBtd->l2cap_connection_response(hci_handle, identifier, rfcomm_dcid, rfcomm_scid, PENDING);
-                                delay(1);
-                                pBtd->l2cap_connection_response(hci_handle, identifier, rfcomm_dcid, rfcomm_scid, SUCCESSFUL);
-                                identifier++;
-                                delay(1);
-                                pBtd->l2cap_config_request(hci_handle, identifier, rfcomm_scid);
-                                l2cap_rfcomm_state = L2CAP_RFCOMM_SUCCESS;
-                        } else if(l2cap_check_flag(L2CAP_FLAG_DISCONNECT_RFCOMM_REQUEST)) {
-                                l2cap_clear_flag(L2CAP_FLAG_DISCONNECT_RFCOMM_REQUEST); // Clear flag
-                                RFCOMMConnected = false;
-                                connected = false;
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nDisconnected RFCOMM Channel"), 0x80);
-#endif
-                                pBtd->l2cap_disconnection_response(hci_handle, identifier, rfcomm_dcid, rfcomm_scid);
-                        }
-                        break;
-                case L2CAP_RFCOMM_SUCCESS:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_RFCOMM_SUCCESS)) {
-                                l2cap_clear_flag(L2CAP_FLAG_CONFIG_RFCOMM_SUCCESS); // Clear flag
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nRFCOMM Successfully Configured"), 0x80);
-#endif
-                                rfcommAvailable = 0; // Reset number of bytes available
-                                bytesRead = 0; // Reset number of bytes received
-                                RFCOMMConnected = true;
-                                l2cap_rfcomm_state = L2CAP_RFCOMM_WAIT;
-                        }
-                        break;
-        }
-}
-/************************************************************/
-/*                    SDP Commands                          */
-
-/************************************************************/
-void SPP::SDP_Command(uint8_t* data, uint8_t nbytes) { // See page 223 in the Bluetooth specs
-        pBtd->L2CAP_Command(hci_handle, data, nbytes, sdp_scid[0], sdp_scid[1]);
-}
-
-void SPP::serviceNotSupported(uint8_t transactionIDHigh, uint8_t transactionIDLow) { // See page 235 in the Bluetooth specs
-        l2capoutbuf[0] = SDP_SERVICE_SEARCH_ATTRIBUTE_RESPONSE_PDU;
-        l2capoutbuf[1] = transactionIDHigh;
-        l2capoutbuf[2] = transactionIDLow;
-        l2capoutbuf[3] = 0x00; // MSB Parameter Length
-        l2capoutbuf[4] = 0x05; // LSB Parameter Length = 5
-        l2capoutbuf[5] = 0x00; // MSB AttributeListsByteCount
-        l2capoutbuf[6] = 0x02; // LSB AttributeListsByteCount = 2
-
-        /* Attribute ID/Value Sequence: */
-        l2capoutbuf[7] = 0x35; // Data element sequence - length in next byte
-        l2capoutbuf[8] = 0x00; // Length = 0
-        l2capoutbuf[9] = 0x00; // No continuation state
-
-        SDP_Command(l2capoutbuf, 10);
-}
-
-void SPP::serialPortResponse1(uint8_t transactionIDHigh, uint8_t transactionIDLow) {
-        l2capoutbuf[0] = SDP_SERVICE_SEARCH_ATTRIBUTE_RESPONSE_PDU;
-        l2capoutbuf[1] = transactionIDHigh;
-        l2capoutbuf[2] = transactionIDLow;
-        l2capoutbuf[3] = 0x00; // MSB Parameter Length
-        l2capoutbuf[4] = 0x2B; // LSB Parameter Length = 43
-        l2capoutbuf[5] = 0x00; // MSB AttributeListsByteCount
-        l2capoutbuf[6] = 0x26; // LSB AttributeListsByteCount = 38
-
-        /* Attribute ID/Value Sequence: */
-        l2capoutbuf[7] = 0x36; // Data element sequence - length in next two bytes
-        l2capoutbuf[8] = 0x00; // MSB Length
-        l2capoutbuf[9] = 0x3C; // LSB Length = 60
-
-        l2capoutbuf[10] = 0x36; // Data element sequence - length in next two bytes
-        l2capoutbuf[11] = 0x00; // MSB Length
-        l2capoutbuf[12] = 0x39; // LSB Length = 57
-
-        l2capoutbuf[13] = 0x09; // Unsigned Integer - length 2 bytes
-        l2capoutbuf[14] = 0x00; // MSB ServiceRecordHandle
-        l2capoutbuf[15] = 0x00; // LSB ServiceRecordHandle
-        l2capoutbuf[16] = 0x0A; // Unsigned int - length 4 bytes
-        l2capoutbuf[17] = 0x00; // ServiceRecordHandle value - TODO: Is this related to HCI_Handle?
-        l2capoutbuf[18] = 0x01;
-        l2capoutbuf[19] = 0x00;
-        l2capoutbuf[20] = 0x06;
-
-        l2capoutbuf[21] = 0x09; // Unsigned Integer - length 2 bytes
-        l2capoutbuf[22] = 0x00; // MSB ServiceClassIDList
-        l2capoutbuf[23] = 0x01; // LSB ServiceClassIDList
-        l2capoutbuf[24] = 0x35; // Data element sequence - length in next byte
-        l2capoutbuf[25] = 0x03; // Length = 3
-        l2capoutbuf[26] = 0x19; // UUID (universally unique identifier) - length = 2 bytes
-        l2capoutbuf[27] = 0x11; // MSB SerialPort
-        l2capoutbuf[28] = 0x01; // LSB SerialPort
-
-        l2capoutbuf[29] = 0x09; // Unsigned Integer - length 2 bytes
-        l2capoutbuf[30] = 0x00; // MSB ProtocolDescriptorList
-        l2capoutbuf[31] = 0x04; // LSB ProtocolDescriptorList
-        l2capoutbuf[32] = 0x35; // Data element sequence - length in next byte
-        l2capoutbuf[33] = 0x0C; // Length = 12
-
-        l2capoutbuf[34] = 0x35; // Data element sequence - length in next byte
-        l2capoutbuf[35] = 0x03; // Length = 3
-        l2capoutbuf[36] = 0x19; // UUID (universally unique identifier) - length = 2 bytes
-        l2capoutbuf[37] = 0x01; // MSB L2CAP
-        l2capoutbuf[38] = 0x00; // LSB L2CAP
-
-        l2capoutbuf[39] = 0x35; // Data element sequence - length in next byte
-        l2capoutbuf[40] = 0x05; // Length = 5
-        l2capoutbuf[41] = 0x19; // UUID (universally unique identifier) - length = 2 bytes
-        l2capoutbuf[42] = 0x00; // MSB RFCOMM
-        l2capoutbuf[43] = 0x03; // LSB RFCOMM
-        l2capoutbuf[44] = 0x08; // Unsigned Integer - length 1 byte
-
-        l2capoutbuf[45] = 0x02; // ContinuationState - Two more bytes
-        l2capoutbuf[46] = 0x00; // MSB length
-        l2capoutbuf[47] = 0x19; // LSB length = 25 more bytes to come
-
-        SDP_Command(l2capoutbuf, 48);
-}
-
-void SPP::serialPortResponse2(uint8_t transactionIDHigh, uint8_t transactionIDLow) {
-        l2capoutbuf[0] = SDP_SERVICE_SEARCH_ATTRIBUTE_RESPONSE_PDU;
-        l2capoutbuf[1] = transactionIDHigh;
-        l2capoutbuf[2] = transactionIDLow;
-        l2capoutbuf[3] = 0x00; // MSB Parameter Length
-        l2capoutbuf[4] = 0x1C; // LSB Parameter Length = 28
-        l2capoutbuf[5] = 0x00; // MSB AttributeListsByteCount
-        l2capoutbuf[6] = 0x19; // LSB AttributeListsByteCount = 25
-
-        /* Attribute ID/Value Sequence: */
-        l2capoutbuf[7] = 0x01; // Channel 1 - TODO: Try different values, so multiple servers can be used at once
-
-        l2capoutbuf[8] = 0x09; // Unsigned Integer - length 2 bytes
-        l2capoutbuf[9] = 0x00; // MSB LanguageBaseAttributeIDList
-        l2capoutbuf[10] = 0x06; // LSB LanguageBaseAttributeIDList
-        l2capoutbuf[11] = 0x35; // Data element sequence - length in next byte
-        l2capoutbuf[12] = 0x09; // Length = 9
-
-        // Identifier representing the natural language = en = English - see: "ISO 639:1988"
-        l2capoutbuf[13] = 0x09; // Unsigned Integer - length 2 bytes
-        l2capoutbuf[14] = 0x65; // 'e'
-        l2capoutbuf[15] = 0x6E; // 'n'
-
-        // "The second element of each triplet contains an identifier that specifies a character encoding used for the language"
-        // Encoding is set to 106 (UTF-8) - see: http://www.iana.org/assignments/character-sets/character-sets.xhtml
-        l2capoutbuf[16] = 0x09; // Unsigned Integer - length 2 bytes
-        l2capoutbuf[17] = 0x00; // MSB of character encoding
-        l2capoutbuf[18] = 0x6A; // LSB of character encoding (106)
-
-        // Attribute ID that serves as the base attribute ID for the natural language in the service record
-        // "To facilitate the retrieval of human-readable universal attributes in a principal language, the base attribute ID value for the primary language supported by a service record shall be 0x0100"
-        l2capoutbuf[19] = 0x09; // Unsigned Integer - length 2 bytes
-        l2capoutbuf[20] = 0x01;
-        l2capoutbuf[21] = 0x00;
-
-        l2capoutbuf[22] = 0x09; // Unsigned Integer - length 2 bytes
-        l2capoutbuf[23] = 0x01; // MSB ServiceDescription
-        l2capoutbuf[24] = 0x00; // LSB ServiceDescription
-
-        l2capoutbuf[25] = 0x25; // Text string - length in next byte
-        l2capoutbuf[26] = 0x05; // Name length
-        l2capoutbuf[27] = 'T';
-        l2capoutbuf[28] = 'K';
-        l2capoutbuf[29] = 'J';
-        l2capoutbuf[30] = 'S';
-        l2capoutbuf[31] = 'P';
-        l2capoutbuf[32] = 0x00; // No continuation state
-
-        SDP_Command(l2capoutbuf, 33);
-}
-
-void SPP::l2capResponse1(uint8_t transactionIDHigh, uint8_t transactionIDLow) {
-        serialPortResponse1(transactionIDHigh, transactionIDLow); // These has to send all the supported functions, since it only supports virtual serialport it just sends the message again
-}
-
-void SPP::l2capResponse2(uint8_t transactionIDHigh, uint8_t transactionIDLow) {
-        serialPortResponse2(transactionIDHigh, transactionIDLow); // Same data as serialPortResponse2
-}
-/************************************************************/
-/*                    RFCOMM Commands                       */
-
-/************************************************************/
-void SPP::RFCOMM_Command(uint8_t* data, uint8_t nbytes) {
-        pBtd->L2CAP_Command(hci_handle, data, nbytes, rfcomm_scid[0], rfcomm_scid[1]);
-}
-
-void SPP::sendRfcomm(uint8_t channel, uint8_t direction, uint8_t CR, uint8_t channelType, uint8_t pfBit, uint8_t* data, uint8_t length) {
-        l2capoutbuf[0] = channel | direction | CR | extendAddress; // RFCOMM Address
-        l2capoutbuf[1] = channelType | pfBit; // RFCOMM Control
-        l2capoutbuf[2] = length << 1 | 0x01; // Length and format (always 0x01 bytes format)
-        uint8_t i = 0;
-        for(; i < length; i++)
-                l2capoutbuf[i + 3] = data[i];
-        l2capoutbuf[i + 3] = calcFcs(l2capoutbuf);
-#ifdef EXTRADEBUG
-        Notify(PSTR(" - RFCOMM Data: "), 0x80);
-        for(i = 0; i < length + 4; i++) {
-                D_PrintHex<uint8_t > (l2capoutbuf[i], 0x80);
-                Notify(PSTR(" "), 0x80);
-        }
-#endif
-        RFCOMM_Command(l2capoutbuf, length + 4);
-}
-
-void SPP::sendRfcommCredit(uint8_t channel, uint8_t direction, uint8_t CR, uint8_t channelType, uint8_t pfBit, uint8_t credit) {
-        l2capoutbuf[0] = channel | direction | CR | extendAddress; // RFCOMM Address
-        l2capoutbuf[1] = channelType | pfBit; // RFCOMM Control
-        l2capoutbuf[2] = 0x01; // Length = 0
-        l2capoutbuf[3] = credit; // Credit
-        l2capoutbuf[4] = calcFcs(l2capoutbuf);
-#ifdef EXTRADEBUG
-        Notify(PSTR(" - RFCOMM Credit Data: "), 0x80);
-        for(uint8_t i = 0; i < 5; i++) {
-                D_PrintHex<uint8_t > (l2capoutbuf[i], 0x80);
-                Notify(PSTR(" "), 0x80);
-        }
-#endif
-        RFCOMM_Command(l2capoutbuf, 5);
-}
-
-/* CRC on 2 bytes */
-uint8_t SPP::crc(uint8_t *data) {
-        return (pgm_read_byte(&rfcomm_crc_table[pgm_read_byte(&rfcomm_crc_table[0xFF ^ data[0]]) ^ data[1]]));
-}
-
-/* Calculate FCS */
-uint8_t SPP::calcFcs(uint8_t *data) {
-        uint8_t temp = crc(data);
-        if((data[1] & 0xEF) == RFCOMM_UIH)
-                return (0xFF - temp); // FCS on 2 bytes
-        else
-                return (0xFF - pgm_read_byte(&rfcomm_crc_table[temp ^ data[2]])); // FCS on 3 bytes
-}
-
-/* Check FCS */
-bool SPP::checkFcs(uint8_t *data, uint8_t fcs) {
-        uint8_t temp = crc(data);
-        if((data[1] & 0xEF) != RFCOMM_UIH)
-                temp = pgm_read_byte(&rfcomm_crc_table[temp ^ data[2]]); // FCS on 3 bytes
-        return (pgm_read_byte(&rfcomm_crc_table[temp ^ fcs]) == 0xCF);
-}
-
-/* Serial commands */
-#if defined(ARDUINO) && ARDUINO >=100
-
-size_t SPP::write(uint8_t data) {
-        return write(&data, 1);
-}
-#else
-
-void SPP::write(uint8_t data) {
-        write(&data, 1);
-}
-#endif
-
-#if defined(ARDUINO) && ARDUINO >=100
-
-size_t SPP::write(const uint8_t *data, size_t size) {
-#else
-
-void SPP::write(const uint8_t *data, size_t size) {
-#endif
-        for(uint8_t i = 0; i < size; i++) {
-                if(sppIndex >= sizeof (sppOutputBuffer) / sizeof (sppOutputBuffer[0]))
-                        send(); // Send the current data in the buffer
-                sppOutputBuffer[sppIndex++] = data[i]; // All the bytes are put into a buffer and then send using the send() function
-        }
-#if defined(ARDUINO) && ARDUINO >=100
-        return size;
-#endif
-}
-
-void SPP::send() {
-        if(!connected || !sppIndex)
-                return;
-        uint8_t length; // This is the length of the string we are sending
-        uint8_t offset = 0; // This is used to keep track of where we are in the string
-
-        l2capoutbuf[0] = rfcommChannelConnection | 0 | 0 | extendAddress; // RFCOMM Address
-        l2capoutbuf[1] = RFCOMM_UIH; // RFCOMM Control
-
-        while(sppIndex) { // We will run this while loop until this variable is 0
-                if(sppIndex > (sizeof (l2capoutbuf) - 4)) // Check if the string is larger than the outgoing buffer
-                        length = sizeof (l2capoutbuf) - 4;
-                else
-                        length = sppIndex;
-
-                l2capoutbuf[2] = length << 1 | 1; // Length
-                uint8_t i = 0;
-                for(; i < length; i++)
-                        l2capoutbuf[i + 3] = sppOutputBuffer[i + offset];
-                l2capoutbuf[i + 3] = calcFcs(l2capoutbuf); // Calculate checksum
-
-                RFCOMM_Command(l2capoutbuf, length + 4);
-
-                sppIndex -= length;
-                offset += length; // Increment the offset
-        }
-}
-
-int SPP::available(void) {
-        return rfcommAvailable;
-};
-
-void SPP::discard(void) {
-        rfcommAvailable = 0;
-}
-
-int SPP::peek(void) {
-        if(rfcommAvailable == 0) // Don't read if there is nothing in the buffer
-                return -1;
-        return rfcommDataBuffer[0];
-}
-
-int SPP::read(void) {
-        if(rfcommAvailable == 0) // Don't read if there is nothing in the buffer
-                return -1;
-        uint8_t output = rfcommDataBuffer[0];
-        for(uint8_t i = 1; i < rfcommAvailable; i++)
-                rfcommDataBuffer[i - 1] = rfcommDataBuffer[i]; // Shift the buffer one left
-        rfcommAvailable--;
-        bytesRead++;
-        if(bytesRead > (sizeof (rfcommDataBuffer) - 5)) { // We will send the command just before it runs out of credit
-                bytesRead = 0;
-                sendRfcommCredit(rfcommChannelConnection, rfcommDirection, 0, RFCOMM_UIH, 0x10, sizeof (rfcommDataBuffer)); // Send more credit
-#ifdef EXTRADEBUG
-                Notify(PSTR("\r\nSent "), 0x80);
-                Notify((uint8_t)sizeof (rfcommDataBuffer), 0x80);
-                Notify(PSTR(" more credit"), 0x80);
-#endif
-        }
-        return output;
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/SPP.h b/lib/usbhost/USB_Host_Shield_2.0/SPP.h
deleted file mode 100644
index 233ac611fd..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/SPP.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _spp_h_
-#define _spp_h_
-
-#include "BTD.h"
-
-/* Used for SDP */
-#define SDP_SERVICE_SEARCH_ATTRIBUTE_REQUEST_PDU    0x06 // See the RFCOMM specs
-#define SDP_SERVICE_SEARCH_ATTRIBUTE_RESPONSE_PDU   0x07 // See the RFCOMM specs
-#define SERIALPORT_UUID     0x1101 // See http://www.bluetooth.org/Technical/AssignedNumbers/service_discovery.htm
-#define L2CAP_UUID          0x0100
-
-/* Used for RFCOMM */
-#define RFCOMM_SABM     0x2F
-#define RFCOMM_UA       0x63
-#define RFCOMM_UIH      0xEF
-//#define RFCOMM_DM       0x0F
-#define RFCOMM_DISC     0x43
-
-#define extendAddress   0x01 // Always 1
-
-// Multiplexer message types
-#define BT_RFCOMM_PN_CMD     0x83
-#define BT_RFCOMM_PN_RSP     0x81
-#define BT_RFCOMM_MSC_CMD    0xE3
-#define BT_RFCOMM_MSC_RSP    0xE1
-#define BT_RFCOMM_RPN_CMD    0x93
-#define BT_RFCOMM_RPN_RSP    0x91
-/*
-#define BT_RFCOMM_TEST_CMD   0x23
-#define BT_RFCOMM_TEST_RSP   0x21
-#define BT_RFCOMM_FCON_CMD   0xA3
-#define BT_RFCOMM_FCON_RSP   0xA1
-#define BT_RFCOMM_FCOFF_CMD  0x63
-#define BT_RFCOMM_FCOFF_RSP  0x61
-#define BT_RFCOMM_RLS_CMD    0x53
-#define BT_RFCOMM_RLS_RSP    0x51
-#define BT_RFCOMM_NSC_RSP    0x11
- */
-
-/**
- * This BluetoothService class implements the Serial Port Protocol (SPP).
- * It inherits the Arduino Stream class. This allows it to use all the standard Arduino print and stream functions.
- */
-class SPP : public BluetoothService, public Stream {
-public:
-        /**
-         * Constructor for the SPP class.
-         * @param  p   Pointer to BTD class instance.
-         * @param  name   Set the name to BTD#btdName. If argument is omitted, then "Arduino" will be used.
-         * @param  pin   Write the pin to BTD#btdPin. If argument is omitted, then "0000" will be used.
-         */
-        SPP(BTD *p, const char *name = "Arduino", const char *pin = "0000");
-
-        /** @name BluetoothService implementation */
-        /** Used this to disconnect the virtual serial port. */
-        void disconnect();
-        /**@}*/
-
-        /**
-         * Used to provide Boolean tests for the class.
-         * @return Return true if SPP communication is connected.
-         */
-        operator bool() {
-                return connected;
-        }
-        /** Variable used to indicate if the connection is established. */
-        bool connected;
-
-        /** @name Serial port profile (SPP) Print functions */
-        /**
-         * Get number of bytes waiting to be read.
-         * @return Return the number of bytes ready to be read.
-         */
-        int available(void);
-
-        /** Send out all bytes in the buffer. */
-        void flush(void) {
-                send();
-        };
-        /**
-         * Used to read the next value in the buffer without advancing to the next one.
-         * @return Return the byte. Will return -1 if no bytes are available.
-         */
-        int peek(void);
-        /**
-         * Used to read the buffer.
-         * @return Return the byte. Will return -1 if no bytes are available.
-         */
-        int read(void);
-
-#if defined(ARDUINO) && ARDUINO >=100
-        /**
-         * Writes the byte to send to a buffer. The message is send when either send() or after Usb.Task() is called.
-         * @param  data The byte to write.
-         * @return      Return the number of bytes written.
-         */
-        size_t write(uint8_t data);
-        /**
-         * Writes the bytes to send to a buffer. The message is send when either send() or after Usb.Task() is called.
-         * @param  data The data array to send.
-         * @param  size Size of the data.
-         * @return      Return the number of bytes written.
-         */
-        size_t write(const uint8_t* data, size_t size);
-        /** Pull in write(const char *str) from Print */
-        using Print::write;
-#else
-        /**
-         * Writes the byte to send to a buffer. The message is send when either send() or after Usb.Task() is called.
-         * @param  data The byte to write.
-         */
-        void write(uint8_t data);
-        /**
-         * Writes the bytes to send to a buffer. The message is send when either send() or after Usb.Task() is called.
-         * @param data The data array to send.
-         * @param size Size of the data.
-         */
-        void write(const uint8_t* data, size_t size);
-#endif
-
-        /** Discard all the bytes in the buffer. */
-        void discard(void);
-        /**
-         * This will send all the bytes in the buffer.
-         * This is called whenever Usb.Task() is called,
-         * but can also be called via this function.
-         */
-        void send(void);
-        /**@}*/
-
-protected:
-        /** @name BluetoothService implementation */
-        /**
-         * Used to pass acldata to the services.
-         * @param ACLData Incoming acldata.
-         */
-        void ACLData(uint8_t* ACLData);
-        /** Used to establish the connection automatically. */
-        void Run();
-        /** Use this to reset the service. */
-        void Reset();
-        /**
-         * Called when a device is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        void onInit();
-        /**@}*/
-
-private:
-        /* Set true when a channel is created */
-        bool SDPConnected;
-        bool RFCOMMConnected;
-
-        /* Variables used by L2CAP state machines */
-        uint8_t l2cap_sdp_state;
-        uint8_t l2cap_rfcomm_state;
-
-        uint8_t l2capoutbuf[BULK_MAXPKTSIZE]; // General purpose buffer for l2cap out data
-        uint8_t rfcommbuf[10]; // Buffer for RFCOMM Commands
-
-        /* L2CAP Channels */
-        uint8_t sdp_scid[2]; // L2CAP source CID for SDP
-        uint8_t sdp_dcid[2]; // 0x0050
-        uint8_t rfcomm_scid[2]; // L2CAP source CID for RFCOMM
-        uint8_t rfcomm_dcid[2]; // 0x0051
-
-        /* RFCOMM Variables */
-        uint8_t rfcommChannel;
-        uint8_t rfcommChannelConnection; // This is the channel the SPP channel will be running at
-        uint8_t rfcommDirection;
-        uint8_t rfcommCommandResponse;
-        uint8_t rfcommChannelType;
-        uint8_t rfcommPfBit;
-
-        uint32_t timer;
-        bool waitForLastCommand;
-        bool creditSent;
-
-        uint8_t rfcommDataBuffer[100]; // Create a 100 sized buffer for incoming data
-        uint8_t sppOutputBuffer[100]; // Create a 100 sized buffer for outgoing SPP data
-        uint8_t sppIndex;
-        uint8_t rfcommAvailable;
-
-        bool firstMessage; // Used to see if it's the first SDP request received
-        uint8_t bytesRead; // Counter to see when it's time to send more credit
-
-        /* State machines */
-        void SDP_task(); // SDP state machine
-        void RFCOMM_task(); // RFCOMM state machine
-
-        /* SDP Commands */
-        void SDP_Command(uint8_t *data, uint8_t nbytes);
-        void serviceNotSupported(uint8_t transactionIDHigh, uint8_t transactionIDLow);
-        void serialPortResponse1(uint8_t transactionIDHigh, uint8_t transactionIDLow);
-        void serialPortResponse2(uint8_t transactionIDHigh, uint8_t transactionIDLow);
-        void l2capResponse1(uint8_t transactionIDHigh, uint8_t transactionIDLow);
-        void l2capResponse2(uint8_t transactionIDHigh, uint8_t transactionIDLow);
-
-        /* RFCOMM Commands */
-        void RFCOMM_Command(uint8_t *data, uint8_t nbytes);
-        void sendRfcomm(uint8_t channel, uint8_t direction, uint8_t CR, uint8_t channelType, uint8_t pfBit, uint8_t *data, uint8_t length);
-        void sendRfcommCredit(uint8_t channel, uint8_t direction, uint8_t CR, uint8_t channelType, uint8_t pfBit, uint8_t credit);
-        uint8_t calcFcs(uint8_t *data);
-        bool checkFcs(uint8_t *data, uint8_t fcs);
-        uint8_t crc(uint8_t *data);
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/Usb.cpp b/lib/usbhost/USB_Host_Shield_2.0/Usb.cpp
deleted file mode 100644
index 14272588a1..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/Usb.cpp
+++ /dev/null
@@ -1,812 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-/* USB functions */
-
-#include "Usb.h"
-
-static uint8_t usb_error = 0;
-static uint8_t usb_task_state;
-
-/* constructor */
-USB::USB() : bmHubPre(0) {
-        usb_task_state = USB_DETACHED_SUBSTATE_INITIALIZE; //set up state machine
-        init();
-}
-
-/* Initialize data structures */
-void USB::init() {
-        //devConfigIndex = 0;
-        bmHubPre = 0;
-}
-
-uint8_t USB::getUsbTaskState(void) {
-        return ( usb_task_state);
-}
-
-void USB::setUsbTaskState(uint8_t state) {
-        usb_task_state = state;
-}
-
-EpInfo* USB::getEpInfoEntry(uint8_t addr, uint8_t ep) {
-        UsbDevice *p = addrPool.GetUsbDevicePtr(addr);
-
-        if(!p || !p->epinfo)
-                return NULL;
-
-        EpInfo *pep = p->epinfo;
-
-        for(uint8_t i = 0; i < p->epcount; i++) {
-                if((pep)->epAddr == ep)
-                        return pep;
-
-                pep++;
-        }
-        return NULL;
-}
-
-/* set device table entry */
-
-/* each device is different and has different number of endpoints. This function plugs endpoint record structure, defined in application, to devtable */
-uint8_t USB::setEpInfoEntry(uint8_t addr, uint8_t epcount, EpInfo* eprecord_ptr) {
-        if(!eprecord_ptr)
-                return USB_ERROR_INVALID_ARGUMENT;
-
-        UsbDevice *p = addrPool.GetUsbDevicePtr(addr);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->address.devAddress = addr;
-        p->epinfo = eprecord_ptr;
-        p->epcount = epcount;
-
-        return 0;
-}
-
-uint8_t USB::SetAddress(uint8_t addr, uint8_t ep, EpInfo **ppep, uint16_t *nak_limit) {
-        UsbDevice *p = addrPool.GetUsbDevicePtr(addr);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        if(!p->epinfo)
-                return USB_ERROR_EPINFO_IS_NULL;
-
-        *ppep = getEpInfoEntry(addr, ep);
-
-        if(!*ppep)
-                return USB_ERROR_EP_NOT_FOUND_IN_TBL;
-
-        *nak_limit = (0x0001UL << (((*ppep)->bmNakPower > USB_NAK_MAX_POWER) ? USB_NAK_MAX_POWER : (*ppep)->bmNakPower));
-        (*nak_limit)--;
-        /*
-          USBTRACE2("\r\nAddress: ", addr);
-          USBTRACE2(" EP: ", ep);
-          USBTRACE2(" NAK Power: ",(*ppep)->bmNakPower);
-          USBTRACE2(" NAK Limit: ", nak_limit);
-          USBTRACE("\r\n");
-         */
-        regWr(rPERADDR, addr); //set peripheral address
-
-        uint8_t mode = regRd(rMODE);
-
-        //Serial.print("\r\nMode: ");
-        //Serial.println( mode, HEX);
-        //Serial.print("\r\nLS: ");
-        //Serial.println(p->lowspeed, HEX);
-
-
-
-        // Set bmLOWSPEED and bmHUBPRE in case of low-speed device, reset them otherwise
-        regWr(rMODE, (p->lowspeed) ? mode | bmLOWSPEED | bmHubPre : mode & ~(bmHUBPRE | bmLOWSPEED));
-
-        return 0;
-}
-
-/* Control transfer. Sets address, endpoint, fills control packet with necessary data, dispatches control packet, and initiates bulk IN transfer,   */
-/* depending on request. Actual requests are defined as inlines                                                                                      */
-/* return codes:                */
-/* 00       =   success         */
-
-/* 01-0f    =   non-zero HRSLT  */
-uint8_t USB::ctrlReq(uint8_t addr, uint8_t ep, uint8_t bmReqType, uint8_t bRequest, uint8_t wValLo, uint8_t wValHi,
-        uint16_t wInd, uint16_t total, uint16_t nbytes, uint8_t* dataptr, USBReadParser *p) {
-        bool direction = false; //request direction, IN or OUT
-        uint8_t rcode;
-        SETUP_PKT setup_pkt;
-
-        EpInfo *pep = NULL;
-        uint16_t nak_limit = 0;
-
-        rcode = SetAddress(addr, ep, &pep, &nak_limit);
-
-        if(rcode)
-                return rcode;
-
-        direction = ((bmReqType & 0x80) > 0);
-
-        /* fill in setup packet */
-        setup_pkt.ReqType_u.bmRequestType = bmReqType;
-        setup_pkt.bRequest = bRequest;
-        setup_pkt.wVal_u.wValueLo = wValLo;
-        setup_pkt.wVal_u.wValueHi = wValHi;
-        setup_pkt.wIndex = wInd;
-        setup_pkt.wLength = total;
-
-        bytesWr(rSUDFIFO, 8, (uint8_t*) & setup_pkt); //transfer to setup packet FIFO
-
-        rcode = dispatchPkt(tokSETUP, ep, nak_limit); //dispatch packet
-
-        if(rcode) //return HRSLT if not zero
-                return ( rcode);
-
-        if(dataptr != NULL) //data stage, if present
-        {
-                if(direction) //IN transfer
-                {
-                        uint16_t left = total;
-
-                        pep->bmRcvToggle = 1; //bmRCVTOG1;
-
-                        while(left) {
-                                // Bytes read into buffer
-                                uint16_t read = nbytes;
-                                //uint16_t read = (left<nbytes) ? left : nbytes;
-
-                                rcode = InTransfer(pep, nak_limit, &read, dataptr);
-                                if(rcode == hrTOGERR) {
-                                        // yes, we flip it wrong here so that next time it is actually correct!
-                                        pep->bmRcvToggle = (regRd(rHRSL) & bmSNDTOGRD) ? 0 : 1;
-                                        continue;
-                                }
-
-                                if(rcode)
-                                        return rcode;
-
-                                // Invoke callback function if inTransfer completed successfully and callback function pointer is specified
-                                if(!rcode && p)
-                                        ((USBReadParser*)p)->Parse(read, dataptr, total - left);
-
-                                left -= read;
-
-                                if(read < nbytes)
-                                        break;
-                        }
-                } else //OUT transfer
-                {
-                        pep->bmSndToggle = 1; //bmSNDTOG1;
-                        rcode = OutTransfer(pep, nak_limit, nbytes, dataptr);
-                }
-                if(rcode) //return error
-                        return ( rcode);
-        }
-        // Status stage
-        return dispatchPkt((direction) ? tokOUTHS : tokINHS, ep, nak_limit); //GET if direction
-}
-
-/* IN transfer to arbitrary endpoint. Assumes PERADDR is set. Handles multiple packets if necessary. Transfers 'nbytes' bytes. */
-/* Keep sending INs and writes data to memory area pointed by 'data'                                                           */
-
-/* rcode 0 if no errors. rcode 01-0f is relayed from dispatchPkt(). Rcode f0 means RCVDAVIRQ error,
-            fe USB xfer timeout */
-uint8_t USB::inTransfer(uint8_t addr, uint8_t ep, uint16_t *nbytesptr, uint8_t* data) {
-        EpInfo *pep = NULL;
-        uint16_t nak_limit = 0;
-
-        uint8_t rcode = SetAddress(addr, ep, &pep, &nak_limit);
-
-        if(rcode) {
-                USBTRACE3("(USB::InTransfer) SetAddress Failed ", rcode, 0x81);
-                USBTRACE3("(USB::InTransfer) addr requested ", addr, 0x81);
-                USBTRACE3("(USB::InTransfer) ep requested ", ep, 0x81);
-                return rcode;
-        }
-        return InTransfer(pep, nak_limit, nbytesptr, data);
-}
-
-uint8_t USB::InTransfer(EpInfo *pep, uint16_t nak_limit, uint16_t *nbytesptr, uint8_t* data) {
-        uint8_t rcode = 0;
-        uint8_t pktsize;
-
-        uint16_t nbytes = *nbytesptr;
-        //printf("Requesting %i bytes ", nbytes);
-        uint8_t maxpktsize = pep->maxPktSize;
-
-        *nbytesptr = 0;
-        regWr(rHCTL, (pep->bmRcvToggle) ? bmRCVTOG1 : bmRCVTOG0); //set toggle value
-
-        // use a 'break' to exit this loop
-        while(1) {
-                rcode = dispatchPkt(tokIN, pep->epAddr, nak_limit); //IN packet to EP-'endpoint'. Function takes care of NAKS.
-                if(rcode == hrTOGERR) {
-                        // yes, we flip it wrong here so that next time it is actually correct!
-                        pep->bmRcvToggle = (regRd(rHRSL) & bmRCVTOGRD) ? 0 : 1;
-                        regWr(rHCTL, (pep->bmRcvToggle) ? bmRCVTOG1 : bmRCVTOG0); //set toggle value
-                        continue;
-                }
-                if(rcode) {
-                        //printf(">>>>>>>> Problem! dispatchPkt %2.2x\r\n", rcode);
-                        break; //should be 0, indicating ACK. Else return error code.
-                }
-                /* check for RCVDAVIRQ and generate error if not present */
-                /* the only case when absence of RCVDAVIRQ makes sense is when toggle error occurred. Need to add handling for that */
-                if((regRd(rHIRQ) & bmRCVDAVIRQ) == 0) {
-                        //printf(">>>>>>>> Problem! NO RCVDAVIRQ!\r\n");
-                        rcode = 0xf0; //receive error
-                        break;
-                }
-                pktsize = regRd(rRCVBC); //number of received bytes
-                //printf("Got %i bytes \r\n", pktsize);
-                // This would be OK, but...
-                //assert(pktsize <= nbytes);
-                if(pktsize > nbytes) {
-                        // This can happen. Use of assert on Arduino locks up the Arduino.
-                        // So I will trim the value, and hope for the best.
-                        //printf(">>>>>>>> Problem! Wanted %i bytes but got %i.\r\n", nbytes, pktsize);
-                        pktsize = nbytes;
-                }
-
-                int16_t mem_left = (int16_t)nbytes - *((int16_t*)nbytesptr);
-
-                if(mem_left < 0)
-                        mem_left = 0;
-
-                data = bytesRd(rRCVFIFO, ((pktsize > mem_left) ? mem_left : pktsize), data);
-
-                regWr(rHIRQ, bmRCVDAVIRQ); // Clear the IRQ & free the buffer
-                *nbytesptr += pktsize; // add this packet's byte count to total transfer length
-
-                /* The transfer is complete under two conditions:           */
-                /* 1. The device sent a short packet (L.T. maxPacketSize)   */
-                /* 2. 'nbytes' have been transferred.                       */
-                if((pktsize < maxpktsize) || (*nbytesptr >= nbytes)) // have we transferred 'nbytes' bytes?
-                {
-                        // Save toggle value
-                        pep->bmRcvToggle = ((regRd(rHRSL) & bmRCVTOGRD)) ? 1 : 0;
-                        //printf("\r\n");
-                        rcode = 0;
-                        break;
-                } // if
-        } //while( 1 )
-        return ( rcode);
-}
-
-/* OUT transfer to arbitrary endpoint. Handles multiple packets if necessary. Transfers 'nbytes' bytes. */
-/* Handles NAK bug per Maxim Application Note 4000 for single buffer transfer   */
-
-/* rcode 0 if no errors. rcode 01-0f is relayed from HRSL                       */
-uint8_t USB::outTransfer(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t* data) {
-        EpInfo *pep = NULL;
-        uint16_t nak_limit = 0;
-
-        uint8_t rcode = SetAddress(addr, ep, &pep, &nak_limit);
-
-        if(rcode)
-                return rcode;
-
-        return OutTransfer(pep, nak_limit, nbytes, data);
-}
-
-uint8_t USB::OutTransfer(EpInfo *pep, uint16_t nak_limit, uint16_t nbytes, uint8_t *data) {
-        uint8_t rcode = hrSUCCESS, retry_count;
-        uint8_t *data_p = data; //local copy of the data pointer
-        uint16_t bytes_tosend, nak_count;
-        uint16_t bytes_left = nbytes;
-
-        uint8_t maxpktsize = pep->maxPktSize;
-
-        if(maxpktsize < 1 || maxpktsize > 64)
-                return USB_ERROR_INVALID_MAX_PKT_SIZE;
-
-        unsigned long timeout = millis() + USB_XFER_TIMEOUT;
-
-        regWr(rHCTL, (pep->bmSndToggle) ? bmSNDTOG1 : bmSNDTOG0); //set toggle value
-
-        while(bytes_left) {
-                retry_count = 0;
-                nak_count = 0;
-                bytes_tosend = (bytes_left >= maxpktsize) ? maxpktsize : bytes_left;
-                bytesWr(rSNDFIFO, bytes_tosend, data_p); //filling output FIFO
-                regWr(rSNDBC, bytes_tosend); //set number of bytes
-                regWr(rHXFR, (tokOUT | pep->epAddr)); //dispatch packet
-                while(!(regRd(rHIRQ) & bmHXFRDNIRQ)); //wait for the completion IRQ
-                regWr(rHIRQ, bmHXFRDNIRQ); //clear IRQ
-                rcode = (regRd(rHRSL) & 0x0f);
-
-                while(rcode && ((long)(millis() - timeout) < 0L)) {
-                        switch(rcode) {
-                                case hrNAK:
-                                        nak_count++;
-                                        if(nak_limit && (nak_count == nak_limit))
-                                                goto breakout;
-                                        //return ( rcode);
-                                        break;
-                                case hrTIMEOUT:
-                                        retry_count++;
-                                        if(retry_count == USB_RETRY_LIMIT)
-                                                goto breakout;
-                                        //return ( rcode);
-                                        break;
-                                case hrTOGERR:
-                                        // yes, we flip it wrong here so that next time it is actually correct!
-                                        pep->bmSndToggle = (regRd(rHRSL) & bmSNDTOGRD) ? 0 : 1;
-                                        regWr(rHCTL, (pep->bmSndToggle) ? bmSNDTOG1 : bmSNDTOG0); //set toggle value
-                                        break;
-                                default:
-                                        goto breakout;
-                        }//switch( rcode
-
-                        /* process NAK according to Host out NAK bug */
-                        regWr(rSNDBC, 0);
-                        regWr(rSNDFIFO, *data_p);
-                        regWr(rSNDBC, bytes_tosend);
-                        regWr(rHXFR, (tokOUT | pep->epAddr)); //dispatch packet
-                        while(!(regRd(rHIRQ) & bmHXFRDNIRQ)); //wait for the completion IRQ
-                        regWr(rHIRQ, bmHXFRDNIRQ); //clear IRQ
-                        rcode = (regRd(rHRSL) & 0x0f);
-                }//while( rcode && ....
-                bytes_left -= bytes_tosend;
-                data_p += bytes_tosend;
-        }//while( bytes_left...
-breakout:
-
-        pep->bmSndToggle = (regRd(rHRSL) & bmSNDTOGRD) ? 1 : 0; //bmSNDTOG1 : bmSNDTOG0;  //update toggle
-        return ( rcode); //should be 0 in all cases
-}
-/* dispatch USB packet. Assumes peripheral address is set and relevant buffer is loaded/empty       */
-/* If NAK, tries to re-send up to nak_limit times                                                   */
-/* If nak_limit == 0, do not count NAKs, exit after timeout                                         */
-/* If bus timeout, re-sends up to USB_RETRY_LIMIT times                                             */
-
-/* return codes 0x00-0x0f are HRSLT( 0x00 being success ), 0xff means timeout                       */
-uint8_t USB::dispatchPkt(uint8_t token, uint8_t ep, uint16_t nak_limit) {
-        unsigned long timeout = millis() + USB_XFER_TIMEOUT;
-        uint8_t tmpdata;
-        uint8_t rcode = hrSUCCESS;
-        uint8_t retry_count = 0;
-        uint16_t nak_count = 0;
-
-        while((long)(millis() - timeout) < 0L) {
-                regWr(rHXFR, (token | ep)); //launch the transfer
-                rcode = USB_ERROR_TRANSFER_TIMEOUT;
-
-                while((long)(millis() - timeout) < 0L) //wait for transfer completion
-                {
-                        tmpdata = regRd(rHIRQ);
-
-                        if(tmpdata & bmHXFRDNIRQ) {
-                                regWr(rHIRQ, bmHXFRDNIRQ); //clear the interrupt
-                                rcode = 0x00;
-                                break;
-                        }//if( tmpdata & bmHXFRDNIRQ
-
-                }//while ( millis() < timeout
-
-                //if (rcode != 0x00) //exit if timeout
-                //        return ( rcode);
-
-                rcode = (regRd(rHRSL) & 0x0f); //analyze transfer result
-
-                switch(rcode) {
-                        case hrNAK:
-                                nak_count++;
-                                if(nak_limit && (nak_count == nak_limit))
-                                        return (rcode);
-                                break;
-                        case hrTIMEOUT:
-                                retry_count++;
-                                if(retry_count == USB_RETRY_LIMIT)
-                                        return (rcode);
-                                break;
-                        default:
-                                return (rcode);
-                }//switch( rcode
-
-        }//while( timeout > millis()
-        return ( rcode);
-}
-
-/* USB main task. Performs enumeration/cleanup */
-void USB::Task(void) //USB state machine
-{
-        uint8_t rcode;
-        uint8_t tmpdata;
-        static unsigned long delay = 0;
-        //USB_DEVICE_DESCRIPTOR buf;
-        bool lowspeed = false;
-
-        MAX3421E::Task();
-
-        tmpdata = getVbusState();
-
-        /* modify USB task state if Vbus changed */
-        switch(tmpdata) {
-                case SE1: //illegal state
-                        usb_task_state = USB_DETACHED_SUBSTATE_ILLEGAL;
-                        lowspeed = false;
-                        break;
-                case SE0: //disconnected
-                        if((usb_task_state & USB_STATE_MASK) != USB_STATE_DETACHED)
-                                usb_task_state = USB_DETACHED_SUBSTATE_INITIALIZE;
-                        lowspeed = false;
-                        break;
-                case LSHOST:
-
-                        lowspeed = true;
-                        //intentional fallthrough
-                case FSHOST: //attached
-                        if((usb_task_state & USB_STATE_MASK) == USB_STATE_DETACHED) {
-                                delay = millis() + USB_SETTLE_DELAY;
-                                usb_task_state = USB_ATTACHED_SUBSTATE_SETTLE;
-                        }
-                        break;
-        }// switch( tmpdata
-
-        for(uint8_t i = 0; i < USB_NUMDEVICES; i++)
-                if(devConfig[i])
-                        rcode = devConfig[i]->Poll();
-
-        switch(usb_task_state) {
-                case USB_DETACHED_SUBSTATE_INITIALIZE:
-                        init();
-
-                        for(uint8_t i = 0; i < USB_NUMDEVICES; i++)
-                                if(devConfig[i])
-                                        rcode = devConfig[i]->Release();
-
-                        usb_task_state = USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE;
-                        break;
-                case USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE: //just sit here
-                        break;
-                case USB_DETACHED_SUBSTATE_ILLEGAL: //just sit here
-                        break;
-                case USB_ATTACHED_SUBSTATE_SETTLE: //settle time for just attached device
-                        if((long)(millis() - delay) >= 0L)
-                                usb_task_state = USB_ATTACHED_SUBSTATE_RESET_DEVICE;
-                        else break; // don't fall through
-                case USB_ATTACHED_SUBSTATE_RESET_DEVICE:
-                        regWr(rHCTL, bmBUSRST); //issue bus reset
-                        usb_task_state = USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE;
-                        break;
-                case USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE:
-                        if((regRd(rHCTL) & bmBUSRST) == 0) {
-                                tmpdata = regRd(rMODE) | bmSOFKAENAB; //start SOF generation
-                                regWr(rMODE, tmpdata);
-                                usb_task_state = USB_ATTACHED_SUBSTATE_WAIT_SOF;
-                                //delay = millis() + 20; //20ms wait after reset per USB spec
-                        }
-                        break;
-                case USB_ATTACHED_SUBSTATE_WAIT_SOF: //todo: change check order
-                        if(regRd(rHIRQ) & bmFRAMEIRQ) {
-                                //when first SOF received _and_ 20ms has passed we can continue
-                                /*
-                                if (delay < millis()) //20ms passed
-                                        usb_task_state = USB_STATE_CONFIGURING;
-                                 */
-                                usb_task_state = USB_ATTACHED_SUBSTATE_WAIT_RESET;
-                                delay = millis() + 20;
-                        }
-                        break;
-                case USB_ATTACHED_SUBSTATE_WAIT_RESET:
-                        if((long)(millis() - delay) >= 0L) usb_task_state = USB_STATE_CONFIGURING;
-                        else break; // don't fall through
-                case USB_STATE_CONFIGURING:
-
-                        //Serial.print("\r\nConf.LS: ");
-                        //Serial.println(lowspeed, HEX);
-
-                        rcode = Configuring(0, 0, lowspeed);
-
-                        if(rcode) {
-                                if(rcode != USB_DEV_CONFIG_ERROR_DEVICE_INIT_INCOMPLETE) {
-                                        usb_error = rcode;
-                                        usb_task_state = USB_STATE_ERROR;
-                                }
-                        } else
-                                usb_task_state = USB_STATE_RUNNING;
-                        break;
-                case USB_STATE_RUNNING:
-                        break;
-                case USB_STATE_ERROR:
-                        //MAX3421E::Init();
-                        break;
-        } // switch( usb_task_state )
-}
-
-uint8_t USB::DefaultAddressing(uint8_t parent, uint8_t port, bool lowspeed) {
-        //uint8_t                buf[12];
-        uint8_t rcode;
-        UsbDevice *p0 = NULL, *p = NULL;
-
-        // Get pointer to pseudo device with address 0 assigned
-        p0 = addrPool.GetUsbDevicePtr(0);
-
-        if(!p0)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        if(!p0->epinfo)
-                return USB_ERROR_EPINFO_IS_NULL;
-
-        p0->lowspeed = (lowspeed) ? true : false;
-
-        // Allocate new address according to device class
-        uint8_t bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        p = addrPool.GetUsbDevicePtr(bAddress);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        // Assign new address to the device
-        rcode = setAddr(0, 0, bAddress);
-
-        if(rcode) {
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                return rcode;
-        }
-        return 0;
-};
-
-uint8_t USB::AttemptConfig(uint8_t driver, uint8_t parent, uint8_t port, bool lowspeed) {
-        //printf("AttemptConfig: parent = %i, port = %i\r\n", parent, port);
-        uint8_t retries = 0;
-
-again:
-        uint8_t rcode = devConfig[driver]->ConfigureDevice(parent, port, lowspeed);
-        if(rcode == USB_ERROR_CONFIG_REQUIRES_ADDITIONAL_RESET) {
-                if(parent == 0) {
-                        // Send a bus reset on the root interface.
-                        regWr(rHCTL, bmBUSRST); //issue bus reset
-                        delay(102); // delay 102ms, compensate for clock inaccuracy.
-                } else {
-                        // reset parent port
-                        devConfig[parent]->ResetHubPort(port);
-                }
-        } else if(rcode == hrJERR && retries < 3) { // Some devices returns this when plugged in - trying to initialize the device again usually works
-                delay(100);
-                retries++;
-                goto again;
-        } else if(rcode)
-                return rcode;
-
-        rcode = devConfig[driver]->Init(parent, port, lowspeed);
-        if(rcode == hrJERR && retries < 3) { // Some devices returns this when plugged in - trying to initialize the device again usually works
-                delay(100);
-                retries++;
-                goto again;
-        }
-        if(rcode) {
-                // Issue a bus reset, because the device may be in a limbo state
-                if(parent == 0) {
-                        // Send a bus reset on the root interface.
-                        regWr(rHCTL, bmBUSRST); //issue bus reset
-                        delay(102); // delay 102ms, compensate for clock inaccuracy.
-                } else {
-                        // reset parent port
-                        devConfig[parent]->ResetHubPort(port);
-                }
-        }
-        return rcode;
-}
-
-/*
- * This is broken. We need to enumerate differently.
- * It causes major problems with several devices if detected in an unexpected order.
- *
- *
- * Oleg - I wouldn't do anything before the newly connected device is considered sane.
- * i.e.(delays are not indicated for brevity):
- * 1. reset
- * 2. GetDevDescr();
- * 3a. If ACK, continue with allocating address, addressing, etc.
- * 3b. Else reset again, count resets, stop at some number (5?).
- * 4. When max.number of resets is reached, toggle power/fail
- * If desired, this could be modified by performing two resets with GetDevDescr() in the middle - however, from my experience, if a device answers to GDD()
- * it doesn't need to be reset again
- * New steps proposal:
- * 1: get address pool instance. exit on fail
- * 2: pUsb->getDevDescr(0, 0, constBufSize, (uint8_t*)buf). exit on fail.
- * 3: bus reset, 100ms delay
- * 4: set address
- * 5: pUsb->setEpInfoEntry(bAddress, 1, epInfo), exit on fail
- * 6: while (configurations) {
- *              for(each configuration) {
- *                      for (each driver) {
- *                              6a: Ask device if it likes configuration. Returns 0 on OK.
- *                                      If successful, the driver configured device.
- *                                      The driver now owns the endpoints, and takes over managing them.
- *                                      The following will need codes:
- *                                          Everything went well, instance consumed, exit with success.
- *                                          Instance already in use, ignore it, try next driver.
- *                                          Not a supported device, ignore it, try next driver.
- *                                          Not a supported configuration for this device, ignore it, try next driver.
- *                                          Could not configure device, fatal, exit with fail.
- *                      }
- *              }
- *    }
- * 7: for(each driver) {
- *      7a: Ask device if it knows this VID/PID. Acts exactly like 6a, but using VID/PID
- * 8: if we get here, no driver likes the device plugged in, so exit failure.
- *
- */
-uint8_t USB::Configuring(uint8_t parent, uint8_t port, bool lowspeed) {
-        //uint8_t bAddress = 0;
-        //printf("Configuring: parent = %i, port = %i\r\n", parent, port);
-        uint8_t devConfigIndex;
-        uint8_t rcode = 0;
-        uint8_t buf[sizeof (USB_DEVICE_DESCRIPTOR)];
-        USB_DEVICE_DESCRIPTOR *udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR *>(buf);
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        EpInfo epInfo;
-
-        epInfo.epAddr = 0;
-        epInfo.maxPktSize = 8;
-        epInfo.epAttribs = 0;
-        epInfo.bmNakPower = USB_NAK_MAX_POWER;
-
-        //delay(2000);
-        AddressPool &addrPool = GetAddressPool();
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-        if(!p) {
-                //printf("Configuring error: USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL\r\n");
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to
-        // avoid toggle inconsistence
-
-        p->epinfo = &epInfo;
-
-        p->lowspeed = lowspeed;
-        // Get device descriptor
-        rcode = getDevDescr(0, 0, sizeof (USB_DEVICE_DESCRIPTOR), (uint8_t*)buf);
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode) {
-                //printf("Configuring error: Can't get USB_DEVICE_DESCRIPTOR\r\n");
-                return rcode;
-        }
-
-        // to-do?
-        // Allocate new address according to device class
-        //bAddress = addrPool.AllocAddress(parent, false, port);
-
-        uint16_t vid = udd->idVendor;
-        uint16_t pid = udd->idProduct;
-        uint8_t klass = udd->bDeviceClass;
-        uint8_t subklass = udd->bDeviceSubClass;
-        // Attempt to configure if VID/PID or device class matches with a driver
-        // Qualify with subclass too.
-        //
-        // VID/PID & class tests default to false for drivers not yet ported
-        // subclass defaults to true, so you don't have to define it if you don't have to.
-        //
-        for(devConfigIndex = 0; devConfigIndex < USB_NUMDEVICES; devConfigIndex++) {
-                if(!devConfig[devConfigIndex]) continue; // no driver
-                if(devConfig[devConfigIndex]->GetAddress()) continue; // consumed
-                if(devConfig[devConfigIndex]->DEVSUBCLASSOK(subklass) && (devConfig[devConfigIndex]->VIDPIDOK(vid, pid) || devConfig[devConfigIndex]->DEVCLASSOK(klass))) {
-                        rcode = AttemptConfig(devConfigIndex, parent, port, lowspeed);
-                        if(rcode != USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED)
-                                break;
-                }
-        }
-
-        if(devConfigIndex < USB_NUMDEVICES) {
-                return rcode;
-        }
-
-
-        // blindly attempt to configure
-        for(devConfigIndex = 0; devConfigIndex < USB_NUMDEVICES; devConfigIndex++) {
-                if(!devConfig[devConfigIndex]) continue;
-                if(devConfig[devConfigIndex]->GetAddress()) continue; // consumed
-                if(devConfig[devConfigIndex]->DEVSUBCLASSOK(subklass) && (devConfig[devConfigIndex]->VIDPIDOK(vid, pid) || devConfig[devConfigIndex]->DEVCLASSOK(klass))) continue; // If this is true it means it must have returned USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED above
-                rcode = AttemptConfig(devConfigIndex, parent, port, lowspeed);
-
-                //printf("ERROR ENUMERATING %2.2x\r\n", rcode);
-                if(!(rcode == USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED || rcode == USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE)) {
-                        // in case of an error dev_index should be reset to 0
-                        //                in order to start from the very beginning the
-                        //                next time the program gets here
-                        //if (rcode != USB_DEV_CONFIG_ERROR_DEVICE_INIT_INCOMPLETE)
-                        //        devConfigIndex = 0;
-                        return rcode;
-                }
-        }
-        // if we get here that means that the device class is not supported by any of registered classes
-        rcode = DefaultAddressing(parent, port, lowspeed);
-
-        return rcode;
-}
-
-uint8_t USB::ReleaseDevice(uint8_t addr) {
-        if(!addr)
-                return 0;
-
-        for(uint8_t i = 0; i < USB_NUMDEVICES; i++) {
-                if(!devConfig[i]) continue;
-                if(devConfig[i]->GetAddress() == addr)
-                        return devConfig[i]->Release();
-        }
-        return 0;
-}
-
-#if 1 //!defined(USB_METHODS_INLINE)
-//get device descriptor
-
-uint8_t USB::getDevDescr(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t* dataptr) {
-        return ( ctrlReq(addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, 0x00, USB_DESCRIPTOR_DEVICE, 0x0000, nbytes, nbytes, dataptr, NULL));
-}
-//get configuration descriptor
-
-uint8_t USB::getConfDescr(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t conf, uint8_t* dataptr) {
-        return ( ctrlReq(addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, conf, USB_DESCRIPTOR_CONFIGURATION, 0x0000, nbytes, nbytes, dataptr, NULL));
-}
-
-/* Requests Configuration Descriptor. Sends two Get Conf Descr requests. The first one gets the total length of all descriptors, then the second one requests this
- total length. The length of the first request can be shorter ( 4 bytes ), however, there are devices which won't work unless this length is set to 9 */
-uint8_t USB::getConfDescr(uint8_t addr, uint8_t ep, uint8_t conf, USBReadParser *p) {
-        const uint8_t bufSize = 64;
-        uint8_t buf[bufSize];
-        USB_CONFIGURATION_DESCRIPTOR *ucd = reinterpret_cast<USB_CONFIGURATION_DESCRIPTOR *>(buf);
-
-        uint8_t ret = getConfDescr(addr, ep, 9, conf, buf);
-
-        if(ret)
-                return ret;
-
-        uint16_t total = ucd->wTotalLength;
-
-        //USBTRACE2("\r\ntotal conf.size:", total);
-
-        return ( ctrlReq(addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, conf, USB_DESCRIPTOR_CONFIGURATION, 0x0000, total, bufSize, buf, p));
-}
-
-//get string descriptor
-
-uint8_t USB::getStrDescr(uint8_t addr, uint8_t ep, uint16_t ns, uint8_t index, uint16_t langid, uint8_t* dataptr) {
-        return ( ctrlReq(addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, index, USB_DESCRIPTOR_STRING, langid, ns, ns, dataptr, NULL));
-}
-//set address
-
-uint8_t USB::setAddr(uint8_t oldaddr, uint8_t ep, uint8_t newaddr) {
-        uint8_t rcode = ctrlReq(oldaddr, ep, bmREQ_SET, USB_REQUEST_SET_ADDRESS, newaddr, 0x00, 0x0000, 0x0000, 0x0000, NULL, NULL);
-        //delay(2); //per USB 2.0 sect.9.2.6.3
-        delay(300); // Older spec says you should wait at least 200ms
-        return rcode;
-        //return ( ctrlReq(oldaddr, ep, bmREQ_SET, USB_REQUEST_SET_ADDRESS, newaddr, 0x00, 0x0000, 0x0000, 0x0000, NULL, NULL));
-}
-//set configuration
-
-uint8_t USB::setConf(uint8_t addr, uint8_t ep, uint8_t conf_value) {
-        return ( ctrlReq(addr, ep, bmREQ_SET, USB_REQUEST_SET_CONFIGURATION, conf_value, 0x00, 0x0000, 0x0000, 0x0000, NULL, NULL));
-}
-
-#endif // defined(USB_METHODS_INLINE)
diff --git a/lib/usbhost/USB_Host_Shield_2.0/Usb.h b/lib/usbhost/USB_Host_Shield_2.0/Usb.h
deleted file mode 100644
index 47bd626cce..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/Usb.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-/* USB functions */
-#ifndef _usb_h_
-#define _usb_h_
-
-// WARNING: Do not change the order of includes, or stuff will break!
-#include <inttypes.h>
-#include <stddef.h>
-#include <stdio.h>
-
-// None of these should ever be included by a driver, or a user's sketch.
-#include "settings.h"
-#include "printhex.h"
-#include "message.h"
-#include "hexdump.h"
-#include "sink_parser.h"
-#include "max3421e.h"
-#include "address.h"
-#include "avrpins.h"
-#include "usb_ch9.h"
-#include "usbhost.h"
-#include "UsbCore.h"
-#include "parsetools.h"
-#include "confdescparser.h"
-
-#endif //_usb_h_
diff --git a/lib/usbhost/USB_Host_Shield_2.0/UsbCore.h b/lib/usbhost/USB_Host_Shield_2.0/UsbCore.h
deleted file mode 100644
index 5c6c771017..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/UsbCore.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#if !defined(_usb_h_) || defined(USBCORE_H)
-#error "Never include UsbCore.h directly; include Usb.h instead"
-#else
-#define USBCORE_H
-
-// Not used anymore? If anyone uses this, please let us know so that this may be
-// moved to the proper place, settings.h.
-//#define USB_METHODS_INLINE
-
-/* shield pins. First parameter - SS pin, second parameter - INT pin */
-#ifdef BOARD_BLACK_WIDDOW
-typedef MAX3421e<P6, P3> MAX3421E; // Black Widow
-#elif defined(CORE_TEENSY) && (defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__))
-#if EXT_RAM
-typedef MAX3421e<P20, P7> MAX3421E; // Teensy++ 2.0 with XMEM2
-#else
-typedef MAX3421e<P9, P8> MAX3421E; // Teensy++ 1.0 and 2.0
-#endif
-#elif defined(BOARD_MEGA_ADK)
-typedef MAX3421e<P53, P54> MAX3421E; // Arduino Mega ADK
-#elif defined(ARDUINO_AVR_BALANDUINO)
-typedef MAX3421e<P20, P19> MAX3421E; // Balanduino
-#elif defined(__ARDUINO_X86__) && PLATFORM_ID == 0x06
-typedef MAX3421e<P3, P2> MAX3421E; // The Intel Galileo supports much faster read and write speed at pin 2 and 3
-#else
-typedef MAX3421e<P10, P9> MAX3421E; // Official Arduinos (UNO, Duemilanove, Mega, 2560, Leonardo, Due etc.), Intel Edison, Intel Galileo 2 or Teensy 2.0 and 3.0
-#endif
-
-/* Common setup data constant combinations  */
-#define bmREQ_GET_DESCR     USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_STANDARD|USB_SETUP_RECIPIENT_DEVICE     //get descriptor request type
-#define bmREQ_SET           USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_STANDARD|USB_SETUP_RECIPIENT_DEVICE     //set request type for all but 'set feature' and 'set interface'
-#define bmREQ_CL_GET_INTF   USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE     //get interface request type
-
-// D7           data transfer direction (0 - host-to-device, 1 - device-to-host)
-// D6-5         Type (0- standard, 1 - class, 2 - vendor, 3 - reserved)
-// D4-0         Recipient (0 - device, 1 - interface, 2 - endpoint, 3 - other, 4..31 - reserved)
-
-// USB Device Classes
-#define USB_CLASS_USE_CLASS_INFO        0x00    // Use Class Info in the Interface Descriptors
-#define USB_CLASS_AUDIO                 0x01    // Audio
-#define USB_CLASS_COM_AND_CDC_CTRL      0x02    // Communications and CDC Control
-#define USB_CLASS_HID                   0x03    // HID
-#define USB_CLASS_PHYSICAL              0x05    // Physical
-#define USB_CLASS_IMAGE                 0x06    // Image
-#define USB_CLASS_PRINTER               0x07    // Printer
-#define USB_CLASS_MASS_STORAGE          0x08    // Mass Storage
-#define USB_CLASS_HUB                   0x09    // Hub
-#define USB_CLASS_CDC_DATA              0x0a    // CDC-Data
-#define USB_CLASS_SMART_CARD            0x0b    // Smart-Card
-#define USB_CLASS_CONTENT_SECURITY      0x0d    // Content Security
-#define USB_CLASS_VIDEO                 0x0e    // Video
-#define USB_CLASS_PERSONAL_HEALTH       0x0f    // Personal Healthcare
-#define USB_CLASS_DIAGNOSTIC_DEVICE     0xdc    // Diagnostic Device
-#define USB_CLASS_WIRELESS_CTRL         0xe0    // Wireless Controller
-#define USB_CLASS_MISC                  0xef    // Miscellaneous
-#define USB_CLASS_APP_SPECIFIC          0xfe    // Application Specific
-#define USB_CLASS_VENDOR_SPECIFIC       0xff    // Vendor Specific
-
-// Additional Error Codes
-#define USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED       0xD1
-#define USB_DEV_CONFIG_ERROR_DEVICE_INIT_INCOMPLETE     0xD2
-#define USB_ERROR_UNABLE_TO_REGISTER_DEVICE_CLASS       0xD3
-#define USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL          0xD4
-#define USB_ERROR_HUB_ADDRESS_OVERFLOW                  0xD5
-#define USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL             0xD6
-#define USB_ERROR_EPINFO_IS_NULL                        0xD7
-#define USB_ERROR_INVALID_ARGUMENT                      0xD8
-#define USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE         0xD9
-#define USB_ERROR_INVALID_MAX_PKT_SIZE                  0xDA
-#define USB_ERROR_EP_NOT_FOUND_IN_TBL                   0xDB
-#define USB_ERROR_CONFIG_REQUIRES_ADDITIONAL_RESET      0xE0
-#define USB_ERROR_FailGetDevDescr                       0xE1
-#define USB_ERROR_FailSetDevTblEntry                    0xE2
-#define USB_ERROR_FailGetConfDescr                      0xE3
-#define USB_ERROR_TRANSFER_TIMEOUT                      0xFF
-
-#define USB_XFER_TIMEOUT        5000    // (5000) USB transfer timeout in milliseconds, per section 9.2.6.1 of USB 2.0 spec
-//#define USB_NAK_LIMIT         32000   // NAK limit for a transfer. 0 means NAKs are not counted
-#define USB_RETRY_LIMIT         3       // 3 retry limit for a transfer
-#define USB_SETTLE_DELAY        200     // settle delay in milliseconds
-
-#define USB_NUMDEVICES          16      //number of USB devices
-//#define HUB_MAX_HUBS          7       // maximum number of hubs that can be attached to the host controller
-#define HUB_PORT_RESET_DELAY    20      // hub port reset delay 10 ms recomended, can be up to 20 ms
-
-/* USB state machine states */
-#define USB_STATE_MASK                                      0xf0
-
-#define USB_STATE_DETACHED                                  0x10
-#define USB_DETACHED_SUBSTATE_INITIALIZE                    0x11
-#define USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE               0x12
-#define USB_DETACHED_SUBSTATE_ILLEGAL                       0x13
-#define USB_ATTACHED_SUBSTATE_SETTLE                        0x20
-#define USB_ATTACHED_SUBSTATE_RESET_DEVICE                  0x30
-#define USB_ATTACHED_SUBSTATE_WAIT_RESET_COMPLETE           0x40
-#define USB_ATTACHED_SUBSTATE_WAIT_SOF                      0x50
-#define USB_ATTACHED_SUBSTATE_WAIT_RESET                    0x51
-#define USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE    0x60
-#define USB_STATE_ADDRESSING                                0x70
-#define USB_STATE_CONFIGURING                               0x80
-#define USB_STATE_RUNNING                                   0x90
-#define USB_STATE_ERROR                                     0xa0
-
-class USBDeviceConfig {
-public:
-
-        virtual uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed) {
-                return 0;
-        }
-
-        virtual uint8_t ConfigureDevice(uint8_t parent, uint8_t port, bool lowspeed) {
-                return 0;
-        }
-
-        virtual uint8_t Release() {
-                return 0;
-        }
-
-        virtual uint8_t Poll() {
-                return 0;
-        }
-
-        virtual uint8_t GetAddress() {
-                return 0;
-        }
-
-        virtual void ResetHubPort(uint8_t port) {
-                return;
-        } // Note used for hubs only!
-
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return false;
-        }
-
-        virtual bool DEVCLASSOK(uint8_t klass) {
-                return false;
-        }
-
-        virtual bool DEVSUBCLASSOK(uint8_t subklass) {
-                return true;
-        }
-
-};
-
-/* USB Setup Packet Structure   */
-typedef struct {
-
-        union { // offset   description
-                uint8_t bmRequestType; //   0      Bit-map of request type
-
-                struct {
-                        uint8_t recipient : 5; //          Recipient of the request
-                        uint8_t type : 2; //          Type of request
-                        uint8_t direction : 1; //          Direction of data X-fer
-                } __attribute__((packed));
-        } ReqType_u;
-        uint8_t bRequest; //   1      Request
-
-        union {
-                uint16_t wValue; //   2      Depends on bRequest
-
-                struct {
-                        uint8_t wValueLo;
-                        uint8_t wValueHi;
-                } __attribute__((packed));
-        } wVal_u;
-        uint16_t wIndex; //   4      Depends on bRequest
-        uint16_t wLength; //   6      Depends on bRequest
-} __attribute__((packed)) SETUP_PKT, *PSETUP_PKT;
-
-
-
-// Base class for incoming data parser
-
-class USBReadParser {
-public:
-        virtual void Parse(const uint16_t len, const uint8_t *pbuf, const uint16_t &offset) = 0;
-};
-
-class USB : public MAX3421E {
-        AddressPoolImpl<USB_NUMDEVICES> addrPool;
-        USBDeviceConfig* devConfig[USB_NUMDEVICES];
-        uint8_t bmHubPre;
-
-public:
-        USB(void);
-
-        void SetHubPreMask() {
-                bmHubPre |= bmHUBPRE;
-        };
-
-        void ResetHubPreMask() {
-                bmHubPre &= (~bmHUBPRE);
-        };
-
-        AddressPool& GetAddressPool() {
-                return (AddressPool&)addrPool;
-        };
-
-        uint8_t RegisterDeviceClass(USBDeviceConfig *pdev) {
-                for(uint8_t i = 0; i < USB_NUMDEVICES; i++) {
-                        if(!devConfig[i]) {
-                                devConfig[i] = pdev;
-                                return 0;
-                        }
-                }
-                return USB_ERROR_UNABLE_TO_REGISTER_DEVICE_CLASS;
-        };
-
-        void ForEachUsbDevice(UsbDeviceHandleFunc pfunc) {
-                addrPool.ForEachUsbDevice(pfunc);
-        };
-        uint8_t getUsbTaskState(void);
-        void setUsbTaskState(uint8_t state);
-
-        EpInfo* getEpInfoEntry(uint8_t addr, uint8_t ep);
-        uint8_t setEpInfoEntry(uint8_t addr, uint8_t epcount, EpInfo* eprecord_ptr);
-
-        /* Control requests */
-        uint8_t getDevDescr(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t* dataptr);
-        uint8_t getConfDescr(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t conf, uint8_t* dataptr);
-
-        uint8_t getConfDescr(uint8_t addr, uint8_t ep, uint8_t conf, USBReadParser *p);
-
-        uint8_t getStrDescr(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t index, uint16_t langid, uint8_t* dataptr);
-        uint8_t setAddr(uint8_t oldaddr, uint8_t ep, uint8_t newaddr);
-        uint8_t setConf(uint8_t addr, uint8_t ep, uint8_t conf_value);
-        /**/
-        uint8_t ctrlData(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t* dataptr, bool direction);
-        uint8_t ctrlStatus(uint8_t ep, bool direction, uint16_t nak_limit);
-        uint8_t inTransfer(uint8_t addr, uint8_t ep, uint16_t *nbytesptr, uint8_t* data);
-        uint8_t outTransfer(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t* data);
-        uint8_t dispatchPkt(uint8_t token, uint8_t ep, uint16_t nak_limit);
-
-        void Task(void);
-
-        uint8_t DefaultAddressing(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t Configuring(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t ReleaseDevice(uint8_t addr);
-
-        uint8_t ctrlReq(uint8_t addr, uint8_t ep, uint8_t bmReqType, uint8_t bRequest, uint8_t wValLo, uint8_t wValHi,
-                uint16_t wInd, uint16_t total, uint16_t nbytes, uint8_t* dataptr, USBReadParser *p);
-
-private:
-        void init();
-        uint8_t SetAddress(uint8_t addr, uint8_t ep, EpInfo **ppep, uint16_t *nak_limit);
-        uint8_t OutTransfer(EpInfo *pep, uint16_t nak_limit, uint16_t nbytes, uint8_t *data);
-        uint8_t InTransfer(EpInfo *pep, uint16_t nak_limit, uint16_t *nbytesptr, uint8_t *data);
-        uint8_t AttemptConfig(uint8_t driver, uint8_t parent, uint8_t port, bool lowspeed);
-};
-
-#if 0 //defined(USB_METHODS_INLINE)
-//get device descriptor
-
-inline uint8_t USB::getDevDescr(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t* dataptr) {
-        return ( ctrlReq(addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, 0x00, USB_DESCRIPTOR_DEVICE, 0x0000, nbytes, dataptr));
-}
-//get configuration descriptor
-
-inline uint8_t USB::getConfDescr(uint8_t addr, uint8_t ep, uint16_t nbytes, uint8_t conf, uint8_t* dataptr) {
-        return ( ctrlReq(addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, conf, USB_DESCRIPTOR_CONFIGURATION, 0x0000, nbytes, dataptr));
-}
-//get string descriptor
-
-inline uint8_t USB::getStrDescr(uint8_t addr, uint8_t ep, uint16_t nuint8_ts, uint8_t index, uint16_t langid, uint8_t* dataptr) {
-        return ( ctrlReq(addr, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, index, USB_DESCRIPTOR_STRING, langid, nuint8_ts, dataptr));
-}
-//set address
-
-inline uint8_t USB::setAddr(uint8_t oldaddr, uint8_t ep, uint8_t newaddr) {
-        return ( ctrlReq(oldaddr, ep, bmREQ_SET, USB_REQUEST_SET_ADDRESS, newaddr, 0x00, 0x0000, 0x0000, NULL));
-}
-//set configuration
-
-inline uint8_t USB::setConf(uint8_t addr, uint8_t ep, uint8_t conf_value) {
-        return ( ctrlReq(addr, ep, bmREQ_SET, USB_REQUEST_SET_CONFIGURATION, conf_value, 0x00, 0x0000, 0x0000, NULL));
-}
-
-#endif // defined(USB_METHODS_INLINE)
-
-#endif /* USBCORE_H */
diff --git a/lib/usbhost/USB_Host_Shield_2.0/Wii.cpp b/lib/usbhost/USB_Host_Shield_2.0/Wii.cpp
deleted file mode 100644
index 4bbf4c91cb..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/Wii.cpp
+++ /dev/null
@@ -1,1268 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
-
- IR camera support added by Allan Glover (adglover9.81@gmail.com) and Kristian Lauszus
- */
-
-#include "Wii.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-//#define PRINTREPORT // Uncomment to print the report send by the Wii controllers
-
-const uint8_t WII_LEDS[] PROGMEM = {
-        0x00, // OFF
-        0x10, // LED1
-        0x20, // LED2
-        0x40, // LED3
-        0x80, // LED4
-
-        0x90, // LED5
-        0xA0, // LED6
-        0xC0, // LED7
-        0xD0, // LED8
-        0xE0, // LED9
-        0xF0, // LED10
-};
-
-const uint32_t WII_BUTTONS[] PROGMEM = {
-        0x00008, // UP
-        0x00002, // RIGHT
-        0x00004, // DOWN
-        0x00001, // LEFT
-
-        0, // Skip
-        0x00010, // PLUS
-        0x00100, // TWO
-        0x00200, // ONE
-
-        0x01000, // MINUS
-        0x08000, // HOME
-        0x10000, // Z
-        0x20000, // C
-
-        0x00400, // B
-        0x00800, // A
-};
-const uint32_t WII_PROCONTROLLER_BUTTONS[] PROGMEM = {
-        0x00100, // UP
-        0x00080, // RIGHT
-        0x00040, // DOWN
-        0x00200, // LEFT
-
-        0, // Skip
-        0x00004, // PLUS
-        0x20000, // L3
-        0x10000, // R3
-
-        0x00010, // MINUS
-        0x00008, // HOME
-        0, 0, // Skip
-
-        0x04000, // B
-        0x01000, // A
-        0x00800, // X
-        0x02000, // Y
-
-        0x00020, // L
-        0x00002, // R
-        0x08000, // ZL
-        0x00400, // ZR
-};
-
-WII::WII(BTD *p, bool pair) :
-BluetoothService(p) // Pointer to USB class instance - mandatory
-{
-        pBtd->pairWithWii = pair;
-
-        HIDBuffer[0] = 0xA2; // HID BT DATA_request (0xA0) | Report Type (Output 0x02)
-
-        /* Set device cid for the control and intterrupt channelse - LSB */
-        control_dcid[0] = 0x60; // 0x0060
-        control_dcid[1] = 0x00;
-        interrupt_dcid[0] = 0x61; // 0x0061
-        interrupt_dcid[1] = 0x00;
-
-        Reset();
-}
-
-void WII::Reset() {
-        wiimoteConnected = false;
-        nunchuckConnected = false;
-        motionPlusConnected = false;
-        activateNunchuck = false;
-        motionValuesReset = false;
-        activeConnection = false;
-        motionPlusInside = false;
-        pBtd->wiiUProController = false;
-        wiiUProControllerConnected = false;
-        wiiBalanceBoardConnected = false;
-        l2cap_event_flag = 0; // Reset flags
-        l2cap_state = L2CAP_WAIT;
-}
-
-void WII::disconnect() { // Use this void to disconnect any of the controllers
-        if(!motionPlusInside) { // The old Wiimote needs a delay after the first command or it will automatically reconnect
-                if(motionPlusConnected) {
-#ifdef DEBUG_USB_HOST
-                        Notify(PSTR("\r\nDeactivating Motion Plus"), 0x80);
-#endif
-                        initExtension1(); // This will disable the Motion Plus extension
-                }
-                timer = millis() + 1000; // We have to wait for the message before the rest of the channels can be deactivated
-        } else
-                timer = millis(); // Don't wait
-        // First the HID interrupt channel has to be disconnected, then the HID control channel and finally the HCI connection
-        pBtd->l2cap_disconnection_request(hci_handle, ++identifier, interrupt_scid, interrupt_dcid);
-        Reset();
-        l2cap_state = L2CAP_INTERRUPT_DISCONNECT;
-}
-
-void WII::ACLData(uint8_t* l2capinbuf) {
-        if(!pBtd->l2capConnectionClaimed && pBtd->incomingWii && !wiimoteConnected && !activeConnection) {
-                if(l2capinbuf[8] == L2CAP_CMD_CONNECTION_REQUEST) {
-                        if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == HID_CTRL_PSM) {
-                                motionPlusInside = pBtd->motionPlusInside;
-                                pBtd->incomingWii = false;
-                                pBtd->l2capConnectionClaimed = true; // Claim that the incoming connection belongs to this service
-                                activeConnection = true;
-                                hci_handle = pBtd->hci_handle; // Store the HCI Handle for the connection
-                                l2cap_state = L2CAP_WAIT;
-                        }
-                }
-        }
-
-        if(checkHciHandle(l2capinbuf, hci_handle)) { // acl_handle_ok
-                if((l2capinbuf[6] | (l2capinbuf[7] << 8)) == 0x0001U) { // l2cap_control - Channel ID for ACL-U
-                        if(l2capinbuf[8] == L2CAP_CMD_COMMAND_REJECT) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nL2CAP Command Rejected - Reason: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[12], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[17], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[16], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[15], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-#endif
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONNECTION_RESPONSE) {
-                                if(((l2capinbuf[16] | (l2capinbuf[17] << 8)) == 0x0000) && ((l2capinbuf[18] | (l2capinbuf[19] << 8)) == SUCCESSFUL)) { // Success
-                                        if(l2capinbuf[14] == control_dcid[0] && l2capinbuf[15] == control_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Control Connection Complete"), 0x80);
-                                                identifier = l2capinbuf[9];
-                                                control_scid[0] = l2capinbuf[12];
-                                                control_scid[1] = l2capinbuf[13];
-                                                l2cap_set_flag(L2CAP_FLAG_CONTROL_CONNECTED);
-                                        } else if(l2capinbuf[14] == interrupt_dcid[0] && l2capinbuf[15] == interrupt_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Interrupt Connection Complete"), 0x80);
-                                                identifier = l2capinbuf[9];
-                                                interrupt_scid[0] = l2capinbuf[12];
-                                                interrupt_scid[1] = l2capinbuf[13];
-                                                l2cap_set_flag(L2CAP_FLAG_INTERRUPT_CONNECTED);
-                                        }
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONNECTION_REQUEST) {
-#ifdef EXTRADEBUG
-                                Notify(PSTR("\r\nL2CAP Connection Request - PSM: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[12], 0x80);
-                                Notify(PSTR(" SCID: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[15], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-                                Notify(PSTR(" Identifier: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[9], 0x80);
-#endif
-                                if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == HID_CTRL_PSM) {
-                                        identifier = l2capinbuf[9];
-                                        control_scid[0] = l2capinbuf[14];
-                                        control_scid[1] = l2capinbuf[15];
-                                        l2cap_set_flag(L2CAP_FLAG_CONNECTION_CONTROL_REQUEST);
-                                } else if((l2capinbuf[12] | (l2capinbuf[13] << 8)) == HID_INTR_PSM) {
-                                        identifier = l2capinbuf[9];
-                                        interrupt_scid[0] = l2capinbuf[14];
-                                        interrupt_scid[1] = l2capinbuf[15];
-                                        l2cap_set_flag(L2CAP_FLAG_CONNECTION_INTERRUPT_REQUEST);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONFIG_RESPONSE) {
-                                if((l2capinbuf[16] | (l2capinbuf[17] << 8)) == 0x0000) { // Success
-                                        if(l2capinbuf[12] == control_dcid[0] && l2capinbuf[13] == control_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Control Configuration Complete"), 0x80);
-                                                identifier = l2capinbuf[9];
-                                                l2cap_set_flag(L2CAP_FLAG_CONFIG_CONTROL_SUCCESS);
-                                        } else if(l2capinbuf[12] == interrupt_dcid[0] && l2capinbuf[13] == interrupt_dcid[1]) {
-                                                //Notify(PSTR("\r\nHID Interrupt Configuration Complete"), 0x80);
-                                                identifier = l2capinbuf[9];
-                                                l2cap_set_flag(L2CAP_FLAG_CONFIG_INTERRUPT_SUCCESS);
-                                        }
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_CONFIG_REQUEST) {
-                                if(l2capinbuf[12] == control_dcid[0] && l2capinbuf[13] == control_dcid[1]) {
-                                        //Notify(PSTR("\r\nHID Control Configuration Request"), 0x80);
-                                        pBtd->l2cap_config_response(hci_handle, l2capinbuf[9], control_scid);
-                                } else if(l2capinbuf[12] == interrupt_dcid[0] && l2capinbuf[13] == interrupt_dcid[1]) {
-                                        //Notify(PSTR("\r\nHID Interrupt Configuration Request"), 0x80);
-                                        pBtd->l2cap_config_response(hci_handle, l2capinbuf[9], interrupt_scid);
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_DISCONNECT_REQUEST) {
-                                if(l2capinbuf[12] == control_dcid[0] && l2capinbuf[13] == control_dcid[1]) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nDisconnect Request: Control Channel"), 0x80);
-#endif
-                                        identifier = l2capinbuf[9];
-                                        pBtd->l2cap_disconnection_response(hci_handle, identifier, control_dcid, control_scid);
-                                        Reset();
-                                } else if(l2capinbuf[12] == interrupt_dcid[0] && l2capinbuf[13] == interrupt_dcid[1]) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nDisconnect Request: Interrupt Channel"), 0x80);
-#endif
-                                        identifier = l2capinbuf[9];
-                                        pBtd->l2cap_disconnection_response(hci_handle, identifier, interrupt_dcid, interrupt_scid);
-                                        Reset();
-                                }
-                        } else if(l2capinbuf[8] == L2CAP_CMD_DISCONNECT_RESPONSE) {
-                                if(l2capinbuf[12] == control_scid[0] && l2capinbuf[13] == control_scid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Response: Control Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_CONTROL_RESPONSE);
-                                } else if(l2capinbuf[12] == interrupt_scid[0] && l2capinbuf[13] == interrupt_scid[1]) {
-                                        //Notify(PSTR("\r\nDisconnect Response: Interrupt Channel"), 0x80);
-                                        identifier = l2capinbuf[9];
-                                        l2cap_set_flag(L2CAP_FLAG_DISCONNECT_INTERRUPT_RESPONSE);
-                                }
-                        }
-#ifdef EXTRADEBUG
-                        else {
-                                identifier = l2capinbuf[9];
-                                Notify(PSTR("\r\nL2CAP Unknown Signaling Command: "), 0x80);
-                                D_PrintHex<uint8_t > (l2capinbuf[8], 0x80);
-                        }
-#endif
-                } else if(l2capinbuf[6] == interrupt_dcid[0] && l2capinbuf[7] == interrupt_dcid[1]) { // l2cap_interrupt
-                        //Notify(PSTR("\r\nL2CAP Interrupt"), 0x80);
-                        if(l2capinbuf[8] == 0xA1) { // HID_THDR_DATA_INPUT
-                                if((l2capinbuf[9] >= 0x20 && l2capinbuf[9] <= 0x22) || (l2capinbuf[9] >= 0x30 && l2capinbuf[9] <= 0x37) || l2capinbuf[9] == 0x3e || l2capinbuf[9] == 0x3f) { // These reports include the buttons
-                                        if((l2capinbuf[9] >= 0x20 && l2capinbuf[9] <= 0x22) || l2capinbuf[9] == 0x31 || l2capinbuf[9] == 0x33) // These reports have no extensions bytes
-                                                ButtonState = (uint32_t)((l2capinbuf[10] & 0x1F) | ((uint16_t)(l2capinbuf[11] & 0x9F) << 8));
-                                        else if(wiiUProControllerConnected)
-                                                ButtonState = (uint32_t)(((~l2capinbuf[23]) & 0xFE) | ((uint16_t)(~l2capinbuf[24]) << 8) | ((uint32_t)((~l2capinbuf[25]) & 0x03) << 16));
-                                        else if(motionPlusConnected) {
-                                                if(l2capinbuf[20] & 0x02) // Only update the Wiimote buttons, since the extension bytes are from the Motion Plus
-                                                        ButtonState = (uint32_t)((l2capinbuf[10] & 0x1F) | ((uint16_t)(l2capinbuf[11] & 0x9F) << 8) | ((uint32_t)(ButtonState & 0xFFFF0000)));
-                                                else if(nunchuckConnected) // Update if it's a report from the Nunchuck
-                                                        ButtonState = (uint32_t)((l2capinbuf[10] & 0x1F) | ((uint16_t)(l2capinbuf[11] & 0x9F) << 8) | ((uint32_t)((~l2capinbuf[20]) & 0x0C) << 14));
-                                                //else if(classicControllerConnected) // Update if it's a report from the Classic Controller
-                                        } else if(nunchuckConnected) // The Nunchuck is directly connected
-                                                ButtonState = (uint32_t)((l2capinbuf[10] & 0x1F) | ((uint16_t)(l2capinbuf[11] & 0x9F) << 8) | ((uint32_t)((~l2capinbuf[20]) & 0x03) << 16));
-                                                //else if(classicControllerConnected) // The Classic Controller is directly connected
-                                        else if(!unknownExtensionConnected)
-                                                ButtonState = (uint32_t)((l2capinbuf[10] & 0x1F) | ((uint16_t)(l2capinbuf[11] & 0x9F) << 8));
-#ifdef PRINTREPORT
-                                        Notify(PSTR("ButtonState: "), 0x80);
-                                        D_PrintHex<uint32_t > (ButtonState, 0x80);
-                                        Notify(PSTR("\r\n"), 0x80);
-#endif
-                                        if(ButtonState != OldButtonState) {
-                                                ButtonClickState = ButtonState & ~OldButtonState; // Update click state variable
-                                                OldButtonState = ButtonState;
-                                        }
-                                }
-                                if(l2capinbuf[9] == 0x31 || l2capinbuf[9] == 0x33 || l2capinbuf[9] == 0x35 || l2capinbuf[9] == 0x37) { // Read the accelerometer
-                                        accXwiimote = ((l2capinbuf[12] << 2) | (l2capinbuf[10] & 0x60 >> 5)) - 500;
-                                        accYwiimote = ((l2capinbuf[13] << 2) | (l2capinbuf[11] & 0x20 >> 4)) - 500;
-                                        accZwiimote = ((l2capinbuf[14] << 2) | (l2capinbuf[11] & 0x40 >> 5)) - 500;
-                                }
-                                switch(l2capinbuf[9]) {
-                                        case 0x20: // Status Information - (a1) 20 BB BB LF 00 00 VV
-#ifdef EXTRADEBUG
-                                                Notify(PSTR("\r\nStatus report was received"), 0x80);
-#endif
-                                                wiiState = l2capinbuf[12]; // (0x01: Battery is nearly empty), (0x02:  An Extension Controller is connected), (0x04: Speaker enabled), (0x08: IR enabled), (0x10: LED1, 0x20: LED2, 0x40: LED3, 0x80: LED4)
-                                                batteryLevel = l2capinbuf[15]; // Update battery level
-
-                                                if(!checkBatteryLevel) { // If this is true it means that the user must have called getBatteryLevel()
-                                                        if(l2capinbuf[12] & 0x02) { // Check if a extension is connected
-#ifdef DEBUG_USB_HOST
-                                                                if(!unknownExtensionConnected)
-                                                                        Notify(PSTR("\r\nExtension connected"), 0x80);
-#endif
-                                                                unknownExtensionConnected = true;
-#ifdef WIICAMERA
-                                                                if(!isIRCameraEnabled()) // Don't activate the Motion Plus if we are trying to initialize the IR camera
-#endif
-                                                                        setReportMode(false, 0x35); // Also read the extension
-                                                        } else {
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nExtension disconnected"), 0x80);
-#endif
-                                                                if(motionPlusConnected) {
-#ifdef DEBUG_USB_HOST
-                                                                        Notify(PSTR(" - from Motion Plus"), 0x80);
-#endif
-                                                                        wii_clear_flag(WII_FLAG_NUNCHUCK_CONNECTED);
-                                                                        if(!activateNunchuck) // If it's already trying to initialize the Nunchuck don't set it to false
-                                                                                nunchuckConnected = false;
-                                                                        //else if(classicControllerConnected)
-                                                                } else if(nunchuckConnected) {
-#ifdef DEBUG_USB_HOST
-                                                                        Notify(PSTR(" - Nunchuck"), 0x80);
-#endif
-                                                                        nunchuckConnected = false; // It must be the Nunchuck controller then
-                                                                        wii_clear_flag(WII_FLAG_NUNCHUCK_CONNECTED);
-                                                                        onInit();
-                                                                        setReportMode(false, 0x31); // If there is no extension connected we will read the buttons and accelerometer
-                                                                } else
-                                                                        setReportMode(false, 0x31); // If there is no extension connected we will read the buttons and accelerometer
-                                                        }
-                                                }
-                                                else {
-#ifdef EXTRADEBUG
-                                                        Notify(PSTR("\r\nChecking battery level"), 0x80);
-#endif
-                                                        checkBatteryLevel = false; // Check for extensions by default
-                                                }
-#ifdef DEBUG_USB_HOST
-                                                if(l2capinbuf[12] & 0x01)
-                                                        Notify(PSTR("\r\nWARNING: Battery is nearly empty"), 0x80);
-#endif
-
-                                                break;
-                                        case 0x21: // Read Memory Data
-                                                if((l2capinbuf[12] & 0x0F) == 0) { // No error
-                                                        uint8_t reportLength = (l2capinbuf[12] >> 4) + 1; // // Bit 4-7 is the length - 1
-                                                        // See: http://wiibrew.org/wiki/Wiimote/Extension_Controllers
-                                                        if(l2capinbuf[16] == 0x00 && l2capinbuf[17] == 0xA4 && l2capinbuf[18] == 0x20 && l2capinbuf[19] == 0x00 && l2capinbuf[20] == 0x00) {
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nNunchuck connected"), 0x80);
-#endif
-                                                                wii_set_flag(WII_FLAG_NUNCHUCK_CONNECTED);
-                                                        } else if(l2capinbuf[16] == 0x00 && (l2capinbuf[17] == 0xA6 || l2capinbuf[17] == 0xA4) && l2capinbuf[18] == 0x20 && l2capinbuf[19] == 0x00 && l2capinbuf[20] == 0x05) {
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nMotion Plus connected"), 0x80);
-#endif
-                                                                wii_set_flag(WII_FLAG_MOTION_PLUS_CONNECTED);
-                                                        } else if(l2capinbuf[16] == 0x00 && l2capinbuf[17] == 0xA4 && l2capinbuf[18] == 0x20 && l2capinbuf[19] == 0x04 && l2capinbuf[20] == 0x05) {
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nMotion Plus activated in normal mode"), 0x80);
-#endif
-                                                                motionPlusConnected = true;
-#ifdef WIICAMERA
-                                                                if(!isIRCameraEnabled()) // Don't activate the Motion Plus if we are trying to initialize the IR camera
-#endif
-                                                                        setReportMode(false, 0x35); // Also read the extension
-                                                        } else if(l2capinbuf[16] == 0x00 && l2capinbuf[17] == 0xA4 && l2capinbuf[18] == 0x20 && l2capinbuf[19] == 0x05 && l2capinbuf[20] == 0x05) {
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nMotion Plus activated in Nunchuck pass-through mode"), 0x80);
-#endif
-                                                                activateNunchuck = false;
-                                                                motionPlusConnected = true;
-                                                                nunchuckConnected = true;
-#ifdef WIICAMERA
-                                                                if(!isIRCameraEnabled()) // Don't activate the Motion Plus if we are trying to initialize the IR camera
-#endif
-                                                                        setReportMode(false, 0x35); // Also read the extension
-                                                        } else if(l2capinbuf[16] == 0x00 && l2capinbuf[17] == 0xA6 && l2capinbuf[18] == 0x20 && (l2capinbuf[19] == 0x00 || l2capinbuf[19] == 0x04 || l2capinbuf[19] == 0x05 || l2capinbuf[19] == 0x07) && l2capinbuf[20] == 0x05) {
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nInactive Wii Motion Plus"), 0x80);
-                                                                Notify(PSTR("\r\nPlease unplug the Motion Plus, disconnect the Wiimote and then replug the Motion Plus Extension"), 0x80);
-#endif
-                                                                stateCounter = 300; // Skip the rest in "WII_CHECK_MOTION_PLUS_STATE"
-                                                        } else if(l2capinbuf[16] == 0x00 && l2capinbuf[17] == 0xA4 && l2capinbuf[18] == 0x20 && l2capinbuf[19] == 0x01 && l2capinbuf[20] == 0x20) {
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nWii U Pro Controller connected"), 0x80);
-#endif
-                                                                wiiUProControllerConnected = true;
-                                                        } else if(l2capinbuf[16] == 0x00 && l2capinbuf[17] == 0xA4 && l2capinbuf[18] == 0x20 && l2capinbuf[19] == 0x04 && l2capinbuf[20] == 0x02) {
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nWii Balance Board connected"), 0x80);
-#endif
-                                                                setReportMode(false, 0x32); // Read the Wii Balance Board extension
-                                                                wii_set_flag(WII_FLAG_CALIBRATE_BALANCE_BOARD);
-                                                        }
-                                                        // Wii Balance Board calibration reports (24 bits in total)
-                                                        else if(l2capinbuf[13] == 0x00 && l2capinbuf[14] == 0x24 && reportLength == 16) { // First 16-bit
-                                                                for(uint8_t i = 0; i < 2; i++) {
-                                                                        for(uint8_t j = 0; j < 4; j++)
-                                                                                wiiBalanceBoardCal[i][j] = l2capinbuf[16 + 8 * i + 2 * j] | l2capinbuf[15 + 8 * i + 2 * j] << 8;
-                                                                }
-                                                        } else if(l2capinbuf[13] == 0x00 && l2capinbuf[14] == 0x34 && reportLength == 8) { // Last 8-bit
-                                                                for(uint8_t j = 0; j < 4; j++)
-                                                                        wiiBalanceBoardCal[2][j] = l2capinbuf[16 + 2 * j] | l2capinbuf[15 + 2 * j] << 8;
-#ifdef DEBUG_USB_HOST
-                                                                Notify(PSTR("\r\nWii Balance Board calibration values read successfully"), 0x80);
-#endif
-                                                                wii_clear_flag(WII_FLAG_CALIBRATE_BALANCE_BOARD);
-                                                                wiiBalanceBoardConnected = true;
-                                                        }
-#ifdef DEBUG_USB_HOST
-                                                        else {
-                                                                Notify(PSTR("\r\nUnknown Device: "), 0x80);
-                                                                D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                                                D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-                                                                Notify(PSTR("\r\nData: "), 0x80);
-                                                                for(uint8_t i = 0; i < reportLength; i++) {
-                                                                        D_PrintHex<uint8_t > (l2capinbuf[15 + i], 0x80);
-                                                                        Notify(PSTR(" "), 0x80);
-                                                                }
-                                                        }
-#endif
-                                                }
-#ifdef EXTRADEBUG
-                                                else {
-                                                        Notify(PSTR("\r\nReport Error: "), 0x80);
-                                                        D_PrintHex<uint8_t > (l2capinbuf[13], 0x80);
-                                                        D_PrintHex<uint8_t > (l2capinbuf[14], 0x80);
-                                                }
-#endif
-                                                break;
-                                        case 0x22: // Acknowledge output report, return function result
-#ifdef DEBUG_USB_HOST
-                                                if(l2capinbuf[13] != 0x00) { // Check if there is an error
-                                                        Notify(PSTR("\r\nCommand failed: "), 0x80);
-                                                        D_PrintHex<uint8_t > (l2capinbuf[12], 0x80);
-                                                }
-#endif
-                                                break;
-                                        case 0x30: // Core buttons - (a1) 30 BB BB
-                                                break;
-                                        case 0x31: // Core Buttons and Accelerometer - (a1) 31 BB BB AA AA AA
-                                                break;
-                                        case 0x32: // Core Buttons with 8 Extension bytes - (a1) 32 BB BB EE EE EE EE EE EE EE EE
-                                                // See: http://wiibrew.org/wiki/Wii_Balance_Board#Data_Format
-                                                wiiBalanceBoardRaw[TopRight] = l2capinbuf[13] | l2capinbuf[12] << 8; // Top right
-                                                wiiBalanceBoardRaw[BotRight] = l2capinbuf[15] | l2capinbuf[14] << 8; // Bottom right
-                                                wiiBalanceBoardRaw[TopLeft] = l2capinbuf[17] | l2capinbuf[16] << 8; // Top left
-                                                wiiBalanceBoardRaw[BotLeft] = l2capinbuf[19] | l2capinbuf[18] << 8; // Bottom left
-                                                break;
-                                        case 0x33: // Core Buttons with Accelerometer and 12 IR bytes - (a1) 33 BB BB AA AA AA II II II II II II II II II II II II
-#ifdef WIICAMERA
-                                                // Read the IR data
-                                                IR_object_x1 = (l2capinbuf[15] | ((uint16_t)(l2capinbuf[17] & 0x30) << 4)); // x position
-                                                IR_object_y1 = (l2capinbuf[16] | ((uint16_t)(l2capinbuf[17] & 0xC0) << 2)); // y position
-                                                IR_object_s1 = (l2capinbuf[17] & 0x0F); // Size value, 0-15
-
-                                                IR_object_x2 = (l2capinbuf[18] | ((uint16_t)(l2capinbuf[20] & 0x30) << 4));
-                                                IR_object_y2 = (l2capinbuf[19] | ((uint16_t)(l2capinbuf[20] & 0xC0) << 2));
-                                                IR_object_s2 = (l2capinbuf[20] & 0x0F);
-
-                                                IR_object_x3 = (l2capinbuf[21] | ((uint16_t)(l2capinbuf[23] & 0x30) << 4));
-                                                IR_object_y3 = (l2capinbuf[22] | ((uint16_t)(l2capinbuf[23] & 0xC0) << 2));
-                                                IR_object_s3 = (l2capinbuf[23] & 0x0F);
-
-                                                IR_object_x4 = (l2capinbuf[24] | ((uint16_t)(l2capinbuf[26] & 0x30) << 4));
-                                                IR_object_y4 = (l2capinbuf[25] | ((uint16_t)(l2capinbuf[26] & 0xC0) << 2));
-                                                IR_object_s4 = (l2capinbuf[26] & 0x0F);
-#endif
-                                                break;
-                                        case 0x34: // Core Buttons with 19 Extension bytes - (a1) 34 BB BB EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
-                                                break;
-                                                /* 0x3e and 0x3f both give unknown report types when report mode is 0x3e or 0x3f with mode number 0x05 */
-                                        case 0x3E: // Core Buttons with Accelerometer and 32 IR bytes
-                                                // (a1) 31 BB BB AA AA AA II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II II
-                                                // corresponds to output report mode 0x3e
-
-                                                /**** for reading in full mode: DOES NOT WORK YET ****/
-                                                /* When it works it will also have intensity and bounding box data */
-                                                /*
-                                                IR_object_x1 = (l2capinbuf[13] | ((uint16_t)(l2capinbuf[15] & 0x30) << 4));
-                                                IR_object_y1 = (l2capinbuf[14] | ((uint16_t)(l2capinbuf[15] & 0xC0) << 2));
-                                                IR_object_s1 = (l2capinbuf[15] & 0x0F);
-                                                 */
-                                                break;
-                                        case 0x3F:
-                                                /*
-                                                IR_object_x1 = (l2capinbuf[13] | ((uint16_t)(l2capinbuf[15] & 0x30) << 4));
-                                                IR_object_y1 = (l2capinbuf[14] | ((uint16_t)(l2capinbuf[15] & 0xC0) << 2));
-                                                IR_object_s1 = (l2capinbuf[15] & 0x0F);
-                                                 */
-                                                break;
-                                        case 0x35: // Core Buttons and Accelerometer with 16 Extension Bytes
-                                                // (a1) 35 BB BB AA AA AA EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE EE
-#if 1 // Set this to 0 if you don't want to use an extension, this reduceds the size of the library a lot!
-                                                if(motionPlusConnected) {
-                                                        if(l2capinbuf[20] & 0x02) { // Check if it's a report from the Motion controller or the extension
-                                                                if(motionValuesReset) { // We will only use the values when the gyro value has been set
-                                                                        gyroYawRaw = ((l2capinbuf[15] | ((l2capinbuf[18] & 0xFC) << 6)) - gyroYawZero);
-                                                                        gyroRollRaw = ((l2capinbuf[16] | ((l2capinbuf[19] & 0xFC) << 6)) - gyroRollZero);
-                                                                        gyroPitchRaw = ((l2capinbuf[17] | ((l2capinbuf[20] & 0xFC) << 6)) - gyroPitchZero);
-
-                                                                        yawGyroSpeed = (double)gyroYawRaw / ((double)gyroYawZero / yawGyroScale);
-                                                                        rollGyroSpeed = -(double)gyroRollRaw / ((double)gyroRollZero / rollGyroScale); // We invert these values so they will fit the acc values
-                                                                        pitchGyroSpeed = (double)gyroPitchRaw / ((double)gyroPitchZero / pitchGyroScale);
-
-                                                                        /* The onboard gyro has two ranges for slow and fast mode */
-                                                                        if(!(l2capinbuf[18] & 0x02)) // Check if fast mode is used
-                                                                                yawGyroSpeed *= 4.545;
-                                                                        if(!(l2capinbuf[18] & 0x01)) // Check if fast mode is used
-                                                                                pitchGyroSpeed *= 4.545;
-                                                                        if(!(l2capinbuf[19] & 0x02)) // Check if fast mode is used
-                                                                                rollGyroSpeed *= 4.545;
-
-                                                                        compPitch = (0.93 * (compPitch + (pitchGyroSpeed * (double)(micros() - timer) / 1000000)))+(0.07 * getWiimotePitch()); // Use a complimentary filter to calculate the angle
-                                                                        compRoll = (0.93 * (compRoll + (rollGyroSpeed * (double)(micros() - timer) / 1000000)))+(0.07 * getWiimoteRoll());
-
-                                                                        gyroYaw += (yawGyroSpeed * ((double)(micros() - timer) / 1000000));
-                                                                        gyroRoll += (rollGyroSpeed * ((double)(micros() - timer) / 1000000));
-                                                                        gyroPitch += (pitchGyroSpeed * ((double)(micros() - timer) / 1000000));
-                                                                        timer = micros();
-                                                                        /*
-                                                                        // Uncomment these lines to tune the gyro scale variabels
-                                                                        Notify(PSTR("\r\ngyroYaw: "), 0x80);
-                                                                        Notify(gyroYaw, 0x80);
-                                                                        Notify(PSTR("\tgyroRoll: "), 0x80);
-                                                                        Notify(gyroRoll, 0x80);
-                                                                        Notify(PSTR("\tgyroPitch: "), 0x80);
-                                                                        Notify(gyroPitch, 0x80);
-                                                                         */
-                                                                        /*
-                                                                        Notify(PSTR("\twiimoteRoll: "), 0x80);
-                                                                        Notify(wiimoteRoll, 0x80);
-                                                                        Notify(PSTR("\twiimotePitch: "), 0x80);
-                                                                        Notify(wiimotePitch, 0x80);
-                                                                         */
-                                                                } else {
-                                                                        if((micros() - timer) > 1000000) { // Loop for 1 sec before resetting the values
-#ifdef DEBUG_USB_HOST
-                                                                                Notify(PSTR("\r\nThe gyro values has been reset"), 0x80);
-#endif
-                                                                                gyroYawZero = (l2capinbuf[15] | ((l2capinbuf[18] & 0xFC) << 6));
-                                                                                gyroRollZero = (l2capinbuf[16] | ((l2capinbuf[19] & 0xFC) << 6));
-                                                                                gyroPitchZero = (l2capinbuf[17] | ((l2capinbuf[20] & 0xFC) << 6));
-
-                                                                                rollGyroScale = 500; // You might need to adjust these
-                                                                                pitchGyroScale = 400;
-                                                                                yawGyroScale = 415;
-
-                                                                                gyroYaw = 0;
-                                                                                gyroRoll = 0;
-                                                                                gyroPitch = 0;
-
-                                                                                motionValuesReset = true;
-                                                                                timer = micros();
-                                                                        }
-                                                                }
-                                                        } else {
-                                                                if(nunchuckConnected) {
-                                                                        hatValues[HatX] = l2capinbuf[15];
-                                                                        hatValues[HatY] = l2capinbuf[16];
-                                                                        accXnunchuck = ((l2capinbuf[17] << 2) | (l2capinbuf[20] & 0x10 >> 3)) - 416;
-                                                                        accYnunchuck = ((l2capinbuf[18] << 2) | (l2capinbuf[20] & 0x20 >> 4)) - 416;
-                                                                        accZnunchuck = (((l2capinbuf[19] & 0xFE) << 2) | (l2capinbuf[20] & 0xC0 >> 5)) - 416;
-                                                                }
-                                                                //else if(classicControllerConnected) { }
-                                                        }
-                                                        if(l2capinbuf[19] & 0x01) {
-                                                                if(!extensionConnected) {
-                                                                        extensionConnected = true;
-                                                                        unknownExtensionConnected = true;
-#ifdef DEBUG_USB_HOST
-                                                                        Notify(PSTR("\r\nExtension connected to Motion Plus"), 0x80);
-#endif
-                                                                }
-                                                        } else {
-                                                                if(extensionConnected && !unknownExtensionConnected) {
-                                                                        extensionConnected = false;
-                                                                        unknownExtensionConnected = true;
-#ifdef DEBUG_USB_HOST
-                                                                        Notify(PSTR("\r\nExtension disconnected from Motion Plus"), 0x80);
-#endif
-                                                                        nunchuckConnected = false; // There is no extension connected to the Motion Plus if this report is sent
-                                                                }
-                                                        }
-
-                                                } else if(nunchuckConnected) {
-                                                        hatValues[HatX] = l2capinbuf[15];
-                                                        hatValues[HatY] = l2capinbuf[16];
-                                                        accXnunchuck = ((l2capinbuf[17] << 2) | (l2capinbuf[20] & 0x0C >> 2)) - 416;
-                                                        accYnunchuck = ((l2capinbuf[18] << 2) | (l2capinbuf[20] & 0x30 >> 4)) - 416;
-                                                        accZnunchuck = ((l2capinbuf[19] << 2) | (l2capinbuf[20] & 0xC0 >> 6)) - 416;
-                                                } else if(wiiUProControllerConnected) {
-                                                        hatValues[LeftHatX] = (l2capinbuf[15] | l2capinbuf[16] << 8);
-                                                        hatValues[RightHatX] = (l2capinbuf[17] | l2capinbuf[18] << 8);
-                                                        hatValues[LeftHatY] = (l2capinbuf[19] | l2capinbuf[20] << 8);
-                                                        hatValues[RightHatY] = (l2capinbuf[21] | l2capinbuf[22] << 8);
-                                                }
-#endif
-                                                break;
-#ifdef DEBUG_USB_HOST
-                                        default:
-                                                Notify(PSTR("\r\nUnknown Report type: "), 0x80);
-                                                D_PrintHex<uint8_t > (l2capinbuf[9], 0x80);
-                                                break;
-#endif
-                                }
-                        }
-                }
-                L2CAP_task();
-        }
-}
-
-void WII::L2CAP_task() {
-        switch(l2cap_state) {
-                        /* These states are used if the Wiimote is the host */
-                case L2CAP_CONTROL_SUCCESS:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_CONTROL_SUCCESS)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Control Successfully Configured"), 0x80);
-#endif
-                                l2cap_state = L2CAP_INTERRUPT_SETUP;
-                        }
-                        break;
-
-                case L2CAP_INTERRUPT_SETUP:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONNECTION_INTERRUPT_REQUEST)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Interrupt Incoming Connection Request"), 0x80);
-#endif
-                                pBtd->l2cap_connection_response(hci_handle, identifier, interrupt_dcid, interrupt_scid, PENDING);
-                                delay(1);
-                                pBtd->l2cap_connection_response(hci_handle, identifier, interrupt_dcid, interrupt_scid, SUCCESSFUL);
-                                identifier++;
-                                delay(1);
-                                pBtd->l2cap_config_request(hci_handle, identifier, interrupt_scid);
-
-                                l2cap_state = L2CAP_INTERRUPT_CONFIG_REQUEST;
-                        }
-                        break;
-
-                        /* These states are used if the Arduino is the host */
-                case L2CAP_CONTROL_CONNECT_REQUEST:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONTROL_CONNECTED)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSend HID Control Config Request"), 0x80);
-#endif
-                                identifier++;
-                                pBtd->l2cap_config_request(hci_handle, identifier, control_scid);
-                                l2cap_state = L2CAP_CONTROL_CONFIG_REQUEST;
-                        }
-                        break;
-
-                case L2CAP_CONTROL_CONFIG_REQUEST:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_CONTROL_SUCCESS)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSend HID Interrupt Connection Request"), 0x80);
-#endif
-                                identifier++;
-                                pBtd->l2cap_connection_request(hci_handle, identifier, interrupt_dcid, HID_INTR_PSM);
-                                l2cap_state = L2CAP_INTERRUPT_CONNECT_REQUEST;
-                        }
-                        break;
-
-                case L2CAP_INTERRUPT_CONNECT_REQUEST:
-                        if(l2cap_check_flag(L2CAP_FLAG_INTERRUPT_CONNECTED)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSend HID Interrupt Config Request"), 0x80);
-#endif
-                                identifier++;
-                                pBtd->l2cap_config_request(hci_handle, identifier, interrupt_scid);
-                                l2cap_state = L2CAP_INTERRUPT_CONFIG_REQUEST;
-                        }
-                        break;
-
-                case L2CAP_INTERRUPT_CONFIG_REQUEST:
-                        if(l2cap_check_flag(L2CAP_FLAG_CONFIG_INTERRUPT_SUCCESS)) { // Now the HID channels is established
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Channels Established"), 0x80);
-#endif
-                                pBtd->connectToWii = false;
-                                pBtd->pairWithWii = false;
-                                stateCounter = 0;
-                                l2cap_state = WII_CHECK_MOTION_PLUS_STATE;
-                        }
-                        break;
-
-                        /* The next states are in run() */
-
-                case L2CAP_INTERRUPT_DISCONNECT:
-                        if(l2cap_check_flag(L2CAP_FLAG_DISCONNECT_INTERRUPT_RESPONSE) && ((long)(millis() - timer) >= 0L)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nDisconnected Interrupt Channel"), 0x80);
-#endif
-                                identifier++;
-                                pBtd->l2cap_disconnection_request(hci_handle, identifier, control_scid, control_dcid);
-                                l2cap_state = L2CAP_CONTROL_DISCONNECT;
-                        }
-                        break;
-
-                case L2CAP_CONTROL_DISCONNECT:
-                        if(l2cap_check_flag(L2CAP_FLAG_DISCONNECT_CONTROL_RESPONSE)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nDisconnected Control Channel"), 0x80);
-#endif
-                                pBtd->hci_disconnect(hci_handle);
-                                hci_handle = -1; // Reset handle
-                                l2cap_event_flag = 0; // Reset flags
-                                l2cap_state = L2CAP_WAIT;
-                        }
-                        break;
-        }
-}
-
-void WII::Run() {
-        if(l2cap_state == L2CAP_INTERRUPT_DISCONNECT && ((long)(millis() - timer) >= 0L))
-                L2CAP_task(); // Call the rest of the disconnection routine after we have waited long enough
-
-        switch(l2cap_state) {
-                case L2CAP_WAIT:
-                        if(pBtd->connectToWii && !pBtd->l2capConnectionClaimed && !wiimoteConnected && !activeConnection) {
-                                pBtd->l2capConnectionClaimed = true;
-                                activeConnection = true;
-                                motionPlusInside = pBtd->motionPlusInside;
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nSend HID Control Connection Request"), 0x80);
-#endif
-                                hci_handle = pBtd->hci_handle; // Store the HCI Handle for the connection
-                                l2cap_event_flag = 0; // Reset flags
-                                identifier = 0;
-                                pBtd->l2cap_connection_request(hci_handle, identifier, control_dcid, HID_CTRL_PSM);
-                                l2cap_state = L2CAP_CONTROL_CONNECT_REQUEST;
-                        } else if(l2cap_check_flag(L2CAP_FLAG_CONNECTION_CONTROL_REQUEST)) {
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nHID Control Incoming Connection Request"), 0x80);
-#endif
-                                pBtd->l2cap_connection_response(hci_handle, identifier, control_dcid, control_scid, PENDING);
-                                delay(1);
-                                pBtd->l2cap_connection_response(hci_handle, identifier, control_dcid, control_scid, SUCCESSFUL);
-                                identifier++;
-                                delay(1);
-                                pBtd->l2cap_config_request(hci_handle, identifier, control_scid);
-                                l2cap_state = L2CAP_CONTROL_SUCCESS;
-                        }
-                        break;
-
-                case WII_CHECK_MOTION_PLUS_STATE:
-#ifdef DEBUG_USB_HOST
-                        if(stateCounter == 0) // Only print onnce
-                                Notify(PSTR("\r\nChecking if a Motion Plus is connected"), 0x80);
-#endif
-                        stateCounter++;
-                        if(stateCounter % 200 == 0)
-                                checkMotionPresent(); // Check if there is a motion plus connected
-                        if(wii_check_flag(WII_FLAG_MOTION_PLUS_CONNECTED)) {
-                                stateCounter = 0;
-                                l2cap_state = WII_INIT_MOTION_PLUS_STATE;
-                                timer = micros();
-
-                                if(unknownExtensionConnected) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nA extension is also connected"), 0x80);
-#endif
-                                        activateNunchuck = true; // For we will just set this to true as this the only extension supported so far
-                                }
-
-                        } else if(stateCounter == 601) { // We will try three times to check for the motion plus
-#ifdef DEBUG_USB_HOST
-                                Notify(PSTR("\r\nNo Motion Plus was detected"), 0x80);
-#endif
-                                stateCounter = 0;
-                                l2cap_state = WII_CHECK_EXTENSION_STATE;
-                        }
-                        break;
-
-                case WII_CHECK_EXTENSION_STATE: // This is used to check if there is anything plugged in to the extension port
-#ifdef DEBUG_USB_HOST
-                        if(stateCounter == 0) // Only print onnce
-                                Notify(PSTR("\r\nChecking if there is any extension connected"), 0x80);
-#endif
-                        stateCounter++; // We use this counter as there has to be a short delay between the commands
-                        if(stateCounter == 1)
-                                statusRequest(); // See if a new device has connected
-                        if(stateCounter == 100) {
-                                if(unknownExtensionConnected) // Check if there is a extension is connected to the port
-                                        initExtension1();
-                                else
-                                        stateCounter = 499;
-                        } else if(stateCounter == 200)
-                                initExtension2();
-                        else if(stateCounter == 300) {
-                                readExtensionType();
-                                unknownExtensionConnected = false;
-                        } else if(stateCounter == 400) {
-                                if(wii_check_flag(WII_FLAG_CALIBRATE_BALANCE_BOARD)) {
-#ifdef DEBUG_USB_HOST
-                                        Notify(PSTR("\r\nReading Wii Balance Board calibration values"), 0x80);
-#endif
-                                        readWiiBalanceBoardCalibration();
-                                } else
-                                        stateCounter = 499;
-                        } else if(stateCounter == 500) {
-                                stateCounter = 0;
-                                l2cap_state = TURN_ON_LED;
-                        }
-                        break;
-
-                case WII_INIT_MOTION_PLUS_STATE:
-                        stateCounter++;
-                        if(stateCounter == 1)
-                                initMotionPlus();
-                        else if(stateCounter == 100)
-                                activateMotionPlus();
-                        else if(stateCounter == 200)
-                                readExtensionType(); // Check if it has been activated
-                        else if(stateCounter == 300) {
-                                stateCounter = 0;
-                                unknownExtensionConnected = false; // The motion plus will send a status report when it's activated, we will set this to false so it doesn't reinitialize the Motion Plus
-                                l2cap_state = TURN_ON_LED;
-                        }
-                        break;
-
-                case TURN_ON_LED:
-                        if(wii_check_flag(WII_FLAG_NUNCHUCK_CONNECTED))
-                                nunchuckConnected = true;
-                        wiimoteConnected = true;
-                        onInit();
-                        l2cap_state = L2CAP_DONE;
-                        break;
-
-                case L2CAP_DONE:
-                        if(unknownExtensionConnected) {
-#ifdef DEBUG_USB_HOST
-                                if(stateCounter == 0) // Only print once
-                                        Notify(PSTR("\r\nChecking extension port"), 0x80);
-#endif
-                                stateCounter++; // We will use this counter as there has to be a short delay between the commands
-                                if(stateCounter == 50)
-                                        statusRequest();
-                                else if(stateCounter == 100)
-                                        initExtension1();
-                                else if(stateCounter == 150)
-                                        if((extensionConnected && motionPlusConnected) || (unknownExtensionConnected && !motionPlusConnected))
-                                                initExtension2();
-                                        else
-                                                stateCounter = 299; // There is no extension connected
-                                else if(stateCounter == 200)
-                                        readExtensionType();
-                                else if(stateCounter == 250) {
-                                        if(wii_check_flag(WII_FLAG_NUNCHUCK_CONNECTED)) {
-#ifdef DEBUG_USB_HOST
-                                                Notify(PSTR("\r\nNunchuck was reconnected"), 0x80);
-#endif
-                                                activateNunchuck = true;
-                                                nunchuckConnected = true;
-                                        }
-                                        if(!motionPlusConnected)
-                                                stateCounter = 449;
-                                } else if(stateCounter == 300) {
-                                        if(motionPlusConnected) {
-#ifdef DEBUG_USB_HOST
-                                                Notify(PSTR("\r\nReactivating the Motion Plus"), 0x80);
-#endif
-                                                initMotionPlus();
-                                        } else
-                                                stateCounter = 449;
-                                } else if(stateCounter == 350)
-                                        activateMotionPlus();
-                                else if(stateCounter == 400)
-                                        readExtensionType(); // Check if it has been activated
-                                else if(stateCounter == 450) {
-                                        onInit();
-                                        stateCounter = 0;
-                                        unknownExtensionConnected = false;
-                                }
-                        } else
-                                stateCounter = 0;
-                        break;
-        }
-}
-
-/************************************************************/
-/*                    HID Commands                          */
-/************************************************************/
-
-void WII::HID_Command(uint8_t* data, uint8_t nbytes) {
-        if(motionPlusInside)
-                pBtd->L2CAP_Command(hci_handle, data, nbytes, interrupt_scid[0], interrupt_scid[1]); // It's the new Wiimote with the Motion Plus Inside or Wii U Pro controller
-        else
-                pBtd->L2CAP_Command(hci_handle, data, nbytes, control_scid[0], control_scid[1]);
-}
-
-void WII::setAllOff() {
-        HIDBuffer[1] = 0x11;
-        HIDBuffer[2] = 0x00;
-        HID_Command(HIDBuffer, 3);
-}
-
-void WII::setRumbleOff() {
-        HIDBuffer[1] = 0x11;
-        HIDBuffer[2] &= ~0x01; // Bit 0 control the rumble
-        HID_Command(HIDBuffer, 3);
-}
-
-void WII::setRumbleOn() {
-        HIDBuffer[1] = 0x11;
-        HIDBuffer[2] |= 0x01; // Bit 0 control the rumble
-        HID_Command(HIDBuffer, 3);
-}
-
-void WII::setRumbleToggle() {
-        HIDBuffer[1] = 0x11;
-        HIDBuffer[2] ^= 0x01; // Bit 0 control the rumble
-        HID_Command(HIDBuffer, 3);
-}
-
-void WII::setLedRaw(uint8_t value) {
-        HIDBuffer[1] = 0x11;
-        HIDBuffer[2] = value | (HIDBuffer[2] & 0x01); // Keep the rumble bit
-        HID_Command(HIDBuffer, 3);
-}
-
-void WII::setLedOff(LEDEnum a) {
-        HIDBuffer[1] = 0x11;
-        HIDBuffer[2] &= ~(pgm_read_byte(&WII_LEDS[(uint8_t)a]));
-        HID_Command(HIDBuffer, 3);
-}
-
-void WII::setLedOn(LEDEnum a) {
-        if(a == OFF)
-                setLedRaw(0);
-        else {
-                HIDBuffer[1] = 0x11;
-                HIDBuffer[2] |= pgm_read_byte(&WII_LEDS[(uint8_t)a]);
-                HID_Command(HIDBuffer, 3);
-        }
-}
-
-void WII::setLedToggle(LEDEnum a) {
-        HIDBuffer[1] = 0x11;
-        HIDBuffer[2] ^= pgm_read_byte(&WII_LEDS[(uint8_t)a]);
-        HID_Command(HIDBuffer, 3);
-}
-
-void WII::setLedStatus() {
-        HIDBuffer[1] = 0x11;
-        HIDBuffer[2] = (HIDBuffer[2] & 0x01); // Keep the rumble bit
-        if(wiimoteConnected)
-                HIDBuffer[2] |= 0x10; // If it's connected LED1 will light up
-        if(motionPlusConnected)
-                HIDBuffer[2] |= 0x20; // If it's connected LED2 will light up
-        if(nunchuckConnected)
-                HIDBuffer[2] |= 0x40; // If it's connected LED3 will light up
-
-        HID_Command(HIDBuffer, 3);
-}
-
-uint8_t WII::getBatteryLevel() {
-        checkBatteryLevel = true; // This is needed so the library knows that the status response is a response to this function
-        statusRequest(); // This will update the battery level
-        return batteryLevel;
-};
-
-void WII::setReportMode(bool continuous, uint8_t mode) {
-        uint8_t cmd_buf[4];
-        cmd_buf[0] = 0xA2; // HID BT DATA_request (0xA0) | Report Type (Output 0x02)
-        cmd_buf[1] = 0x12;
-        if(continuous)
-                cmd_buf[2] = 0x04 | (HIDBuffer[2] & 0x01); // Keep the rumble bit
-        else
-                cmd_buf[2] = 0x00 | (HIDBuffer[2] & 0x01); // Keep the rumble bit
-        cmd_buf[3] = mode;
-        HID_Command(cmd_buf, 4);
-}
-
-void WII::statusRequest() {
-        uint8_t cmd_buf[3];
-        cmd_buf[0] = 0xA2; // HID BT DATA_request (0xA0) | Report Type (Output 0x02)
-        cmd_buf[1] = 0x15;
-        cmd_buf[2] = (HIDBuffer[2] & 0x01); // Keep the rumble bit
-        HID_Command(cmd_buf, 3);
-}
-
-/************************************************************/
-/*                    Memmory Commands                      */
-/************************************************************/
-
-void WII::writeData(uint32_t offset, uint8_t size, uint8_t* data) {
-        uint8_t cmd_buf[23];
-        cmd_buf[0] = 0xA2; // HID BT DATA_request (0xA0) | Report Type (Output 0x02)
-        cmd_buf[1] = 0x16; // Write data
-        cmd_buf[2] = 0x04 | (HIDBuffer[2] & 0x01); // Write to memory, clear bit 2 to write to EEPROM
-        cmd_buf[3] = (uint8_t)((offset & 0xFF0000) >> 16);
-        cmd_buf[4] = (uint8_t)((offset & 0xFF00) >> 8);
-        cmd_buf[5] = (uint8_t)(offset & 0xFF);
-        cmd_buf[6] = size;
-        uint8_t i = 0;
-        for(; i < size; i++)
-                cmd_buf[7 + i] = data[i];
-        for(; i < 16; i++) // Set the rest to zero
-                cmd_buf[7 + i] = 0x00;
-        HID_Command(cmd_buf, 23);
-}
-
-void WII::initExtension1() {
-        uint8_t buf[1];
-        buf[0] = 0x55;
-        writeData(0xA400F0, 1, buf);
-}
-
-void WII::initExtension2() {
-        uint8_t buf[1];
-        buf[0] = 0x00;
-        writeData(0xA400FB, 1, buf);
-}
-
-void WII::initMotionPlus() {
-        uint8_t buf[1];
-        buf[0] = 0x55;
-        writeData(0xA600F0, 1, buf);
-}
-
-void WII::activateMotionPlus() {
-        uint8_t buf[1];
-        if(pBtd->wiiUProController) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nActivating Wii U Pro Controller"), 0x80);
-#endif
-                buf[0] = 0x00; // It seems like you can send anything but 0x04, 0x05, and 0x07
-        } else if(activateNunchuck) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nActivating Motion Plus in pass-through mode"), 0x80);
-#endif
-                buf[0] = 0x05; // Activate nunchuck pass-through mode
-        }//else if(classicControllerConnected && extensionConnected)
-                //buf[0] = 0x07;
-        else {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nActivating Motion Plus in normal mode"), 0x80);
-#endif
-                buf[0] = 0x04; // Don't use any extension
-        }
-        writeData(0xA600FE, 1, buf);
-}
-
-void WII::readData(uint32_t offset, uint16_t size, bool EEPROM) {
-        uint8_t cmd_buf[8];
-        cmd_buf[0] = 0xA2; // HID BT DATA_request (0xA0) | Report Type (Output 0x02)
-        cmd_buf[1] = 0x17; // Read data
-        if(EEPROM)
-                cmd_buf[2] = 0x00 | (HIDBuffer[2] & 0x01); // Read from EEPROM
-        else
-                cmd_buf[2] = 0x04 | (HIDBuffer[2] & 0x01); // Read from memory
-        cmd_buf[3] = (uint8_t)((offset & 0xFF0000) >> 16);
-        cmd_buf[4] = (uint8_t)((offset & 0xFF00) >> 8);
-        cmd_buf[5] = (uint8_t)(offset & 0xFF);
-        cmd_buf[6] = (uint8_t)((size & 0xFF00) >> 8);
-        cmd_buf[7] = (uint8_t)(size & 0xFF);
-
-        HID_Command(cmd_buf, 8);
-}
-
-void WII::readExtensionType() {
-        readData(0xA400FA, 6, false);
-}
-
-void WII::readCalData() {
-        readData(0x0016, 8, true);
-}
-
-void WII::checkMotionPresent() {
-        readData(0xA600FA, 6, false);
-}
-
-void WII::readWiiBalanceBoardCalibration() {
-        readData(0xA40024, 24, false);
-}
-
-/************************************************************/
-/*                    WII Commands                          */
-/************************************************************/
-
-bool WII::getButtonPress(ButtonEnum b) { // Return true when a button is pressed
-        if(wiiUProControllerConnected)
-                return (ButtonState & pgm_read_dword(&WII_PROCONTROLLER_BUTTONS[(uint8_t)b]));
-        else
-                return (ButtonState & pgm_read_dword(&WII_BUTTONS[(uint8_t)b]));
-}
-
-bool WII::getButtonClick(ButtonEnum b) { // Only return true when a button is clicked
-        uint32_t button;
-        if(wiiUProControllerConnected)
-                button = pgm_read_dword(&WII_PROCONTROLLER_BUTTONS[(uint8_t)b]);
-        else
-                button = pgm_read_dword(&WII_BUTTONS[(uint8_t)b]);
-        bool click = (ButtonClickState & button);
-        ButtonClickState &= ~button; // clear "click" event
-        return click;
-}
-
-uint8_t WII::getAnalogHat(HatEnum a) {
-        if(!nunchuckConnected)
-                return 127; // Return center position
-        else {
-                uint8_t output = hatValues[(uint8_t)a];
-                if(output == 0xFF || output == 0x00) // The joystick will only read 255 or 0 when the cable is unplugged or initializing, so we will just return the center position
-                        return 127;
-                else
-                        return output;
-        }
-}
-
-uint16_t WII::getAnalogHat(AnalogHatEnum a) {
-        if(!wiiUProControllerConnected)
-                return 2000;
-        else {
-                uint16_t output = hatValues[(uint8_t)a];
-                if(output == 0x00) // The joystick will only read 0 when it is first initializing, so we will just return the center position
-                        return 2000;
-                else
-                        return output;
-        }
-}
-
-void WII::onInit() {
-        if(pFuncOnInit)
-                pFuncOnInit(); // Call the user function
-        else
-                setLedStatus();
-}
-
-/************************************************************/
-/*                 Wii Balance Board Commands               */
-/************************************************************/
-
-float WII::getWeight(BalanceBoardEnum pos) {
-        // Use interpolating between two points - based on: https://github.com/skorokithakis/gr8w8upd8m8/blob/master/gr8w8upd8m8.py
-        // wiiBalanceBoardCal[pos][0] is calibration values for 0 kg
-        // wiiBalanceBoardCal[pos][1] is calibration values for 17 kg
-        // wiiBalanceBoardCal[pos][2] is calibration values for 34 kg
-        if(wiiBalanceBoardRaw[pos] < wiiBalanceBoardCal[0][pos])
-            return 0.0f; // Below 0 kg
-        else if(wiiBalanceBoardRaw[pos] < wiiBalanceBoardCal[1][pos]) // Between 0 and 17 kg
-            return 17.0f * (float)(wiiBalanceBoardRaw[pos] - wiiBalanceBoardCal[0][pos]) / (float)(wiiBalanceBoardCal[1][pos] - wiiBalanceBoardCal[0][pos]);
-        else // More than 17 kg
-            return 17.0f + 17.0f * (float)(wiiBalanceBoardRaw[pos] - wiiBalanceBoardCal[1][pos]) / (float)(wiiBalanceBoardCal[2][pos] - wiiBalanceBoardCal[1][pos]);
-};
-
-float WII::getTotalWeight() {
-        return getWeight(TopRight) + getWeight(BotRight) + getWeight(TopLeft) + getWeight(BotLeft);
-};
-
-/************************************************************/
-/*       The following functions are for the IR camera      */
-/************************************************************/
-
-#ifdef WIICAMERA
-
-void WII::IRinitialize() { // Turns on and initialises the IR camera
-
-        enableIRCamera1();
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nEnable IR Camera1 Complete"), 0x80);
-#endif
-        delay(80);
-
-        enableIRCamera2();
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nEnable IR Camera2 Complete"), 0x80);
-#endif
-        delay(80);
-
-        write0x08Value();
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nWrote hex number 0x08"), 0x80);
-#endif
-        delay(80);
-
-        writeSensitivityBlock1();
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nWrote Sensitivity Block 1"), 0x80);
-#endif
-        delay(80);
-
-        writeSensitivityBlock2();
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nWrote Sensitivity Block 2"), 0x80);
-#endif
-        delay(80);
-
-        uint8_t mode_num = 0x03;
-        setWiiModeNumber(mode_num); // Change input for whatever mode you want i.e. 0x01, 0x03, or 0x05
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nSet Wii Mode Number To 0x"), 0x80);
-        D_PrintHex<uint8_t > (mode_num, 0x80);
-#endif
-        delay(80);
-
-        write0x08Value();
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nWrote Hex Number 0x08"), 0x80);
-#endif
-        delay(80);
-
-        setReportMode(false, 0x33);
-        //setReportMode(false, 0x3f); // For full reporting mode, doesn't work yet
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nSet Report Mode to 0x33"), 0x80);
-#endif
-        delay(80);
-
-        statusRequest(); // Used to update wiiState - call isIRCameraEnabled() afterwards to check if it actually worked
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nIR Initialized"), 0x80);
-#endif
-}
-
-void WII::enableIRCamera1() {
-        uint8_t cmd_buf[3];
-        cmd_buf[0] = 0xA2; // HID BT DATA_request (0xA0) | Report Type (Output 0x02)
-        cmd_buf[1] = 0x13; // Output report 13
-        cmd_buf[2] = 0x04 | (HIDBuffer[2] & 0x01); // Keep the rumble bit and sets bit 2
-        HID_Command(cmd_buf, 3);
-}
-
-void WII::enableIRCamera2() {
-        uint8_t cmd_buf[3];
-        cmd_buf[0] = 0xA2; // HID BT DATA_request (0xA0) | Report Type (Output 0x02)
-        cmd_buf[1] = 0x1A; // Output report 1A
-        cmd_buf[2] = 0x04 | (HIDBuffer[2] & 0x01); // Keep the rumble bit and sets bit 2
-        HID_Command(cmd_buf, 3);
-}
-
-void WII::writeSensitivityBlock1() {
-        uint8_t buf[9];
-        buf[0] = 0x00;
-        buf[1] = 0x00;
-        buf[2] = 0x00;
-        buf[3] = 0x00;
-        buf[4] = 0x00;
-        buf[5] = 0x00;
-        buf[6] = 0x90;
-        buf[7] = 0x00;
-        buf[8] = 0x41;
-
-        writeData(0xB00000, 9, buf);
-}
-
-void WII::writeSensitivityBlock2() {
-        uint8_t buf[2];
-        buf[0] = 0x40;
-        buf[1] = 0x00;
-
-        writeData(0xB0001A, 2, buf);
-}
-
-void WII::write0x08Value() {
-        uint8_t cmd = 0x08;
-        writeData(0xb00030, 1, &cmd);
-}
-
-void WII::setWiiModeNumber(uint8_t mode_number) { // mode_number in hex i.e. 0x03 for extended mode
-        writeData(0xb00033, 1, &mode_number);
-}
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/Wii.h b/lib/usbhost/USB_Host_Shield_2.0/Wii.h
deleted file mode 100644
index 960f2273de..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/Wii.h
+++ /dev/null
@@ -1,518 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
-
- IR camera support added by Allan Glover (adglover9.81@gmail.com) and Kristian Lauszus
- */
-
-#ifndef _wii_h_
-#define _wii_h_
-
-#include "BTD.h"
-#include "controllerEnums.h"
-
-/* Wii event flags */
-#define WII_FLAG_MOTION_PLUS_CONNECTED          (1 << 0)
-#define WII_FLAG_NUNCHUCK_CONNECTED             (1 << 1)
-#define WII_FLAG_CALIBRATE_BALANCE_BOARD        (1 << 2)
-
-#define wii_check_flag(flag)  (wii_event_flag & (flag))
-#define wii_set_flag(flag)  (wii_event_flag |= (flag))
-#define wii_clear_flag(flag)  (wii_event_flag &= ~(flag))
-
-/** Enum used to read the joystick on the Nunchuck. */
-enum HatEnum {
-        /** Read the x-axis on the Nunchuck joystick. */
-        HatX = 0,
-        /** Read the y-axis on the Nunchuck joystick. */
-        HatY = 1,
-};
-
-/** Enum used to read the weight on Wii Balance Board. */
-enum BalanceBoardEnum {
-        TopRight = 0,
-        BotRight = 1,
-        TopLeft = 2,
-        BotLeft = 3,
-};
-
-/**
- * This BluetoothService class implements support for the Wiimote including the Nunchuck and Motion Plus extension.
- *
- * It also support the Wii U Pro Controller.
- */
-class WII : public BluetoothService {
-public:
-        /**
-         * Constructor for the WII class.
-         * @param  p   Pointer to BTD class instance.
-         * @param  pair   Set this to true in order to pair with the Wiimote. If the argument is omitted then it won't pair with it.
-         * One can use ::PAIR to set it to true.
-         */
-        WII(BTD *p, bool pair = false);
-
-        /** @name BluetoothService implementation */
-        /** Used this to disconnect any of the controllers. */
-        void disconnect();
-        /**@}*/
-
-        /** @name Wii Controller functions */
-        /**
-         * getButtonPress(Button b) will return true as long as the button is held down.
-         *
-         * While getButtonClick(Button b) will only return it once.
-         *
-         * So you instance if you need to increase a variable once you would use getButtonClick(Button b),
-         * but if you need to drive a robot forward you would use getButtonPress(Button b).
-         * @param  b          ::ButtonEnum to read.
-         * @return            getButtonPress(ButtonEnum b) will return a true as long as a button is held down, while getButtonClick(ButtonEnum b) will return true once for each button press.
-         */
-        bool getButtonPress(ButtonEnum b);
-        bool getButtonClick(ButtonEnum b);
-        /**@}*/
-
-        /** @name Wii Controller functions */
-
-        /** Call this to start the paring sequence with a controller */
-        void pair(void) {
-                if(pBtd)
-                        pBtd->pairWithWiimote();
-        };
-        /**
-         * Used to read the joystick of the Nunchuck.
-         * @param  a Either ::HatX or ::HatY.
-         * @return   Return the analog value in the range from approximately 25-230.
-         */
-        uint8_t getAnalogHat(HatEnum a);
-        /**
-         * Used to read the joystick of the Wii U Pro Controller.
-         * @param  a Either ::LeftHatX, ::LeftHatY, ::RightHatX or ::RightHatY.
-         * @return   Return the analog value in the range from approximately 800-3200.
-         */
-        uint16_t getAnalogHat(AnalogHatEnum a);
-
-        /**
-         * Pitch calculated from the Wiimote. A complimentary filter is used if the Motion Plus is connected.
-         * @return Pitch in the range from 0-360.
-         */
-        double getPitch() {
-                if(motionPlusConnected)
-                        return compPitch;
-                return getWiimotePitch();
-        };
-
-        /**
-         * Roll calculated from the Wiimote. A complimentary filter is used if the Motion Plus is connected.
-         * @return Roll in the range from 0-360.
-         */
-        double getRoll() {
-                if(motionPlusConnected)
-                        return compRoll;
-                return getWiimoteRoll();
-        };
-
-        /**
-         * This is the yaw calculated by the gyro.
-         *
-         * <B>NOTE:</B> This angle will drift a lot and is only available if the Motion Plus extension is connected.
-         * @return The angle calculated using the gyro.
-         */
-        double getYaw() {
-                return gyroYaw;
-        };
-
-        /** Used to set all LEDs and rumble off. */
-        void setAllOff();
-        /** Turn off rumble. */
-        void setRumbleOff();
-        /** Turn on rumble. */
-        void setRumbleOn();
-        /** Toggle rumble. */
-        void setRumbleToggle();
-
-        /**
-         * Set LED value without using the ::LEDEnum.
-         * @param value See: ::LEDEnum.
-         */
-        void setLedRaw(uint8_t value);
-
-        /** Turn all LEDs off. */
-        void setLedOff() {
-                setLedRaw(0);
-        };
-        /**
-         * Turn the specific ::LEDEnum off.
-         * @param a The ::LEDEnum to turn off.
-         */
-        void setLedOff(LEDEnum a);
-        /**
-         * Turn the specific ::LEDEnum on.
-         * @param a The ::LEDEnum to turn on.
-         */
-        void setLedOn(LEDEnum a);
-        /**
-         * Toggle the specific ::LEDEnum.
-         * @param a The ::LEDEnum to toggle.
-         */
-        void setLedToggle(LEDEnum a);
-        /**
-         * This will set the LEDs, so the user can see which connections are active.
-         *
-         * The first ::LEDEnum indicate that the Wiimote is connected,
-         * the second ::LEDEnum indicate indicate that a Motion Plus is also connected
-         * the third ::LEDEnum will indicate that a Nunchuck controller is also connected.
-         */
-        void setLedStatus();
-
-        /**
-         * Return the battery level of the Wiimote.
-         * @return The battery level in the range 0-255.
-         */
-        uint8_t getBatteryLevel();
-
-        /**
-         * Return the Wiimote state.
-         * @return See: http://wiibrew.org/wiki/Wiimote#0x20:_Status.
-         */
-        uint8_t getWiiState() {
-                return wiiState;
-        };
-        /**@}*/
-
-        /**@{*/
-        /** Variable used to indicate if a Wiimote is connected. */
-        bool wiimoteConnected;
-        /** Variable used to indicate if a Nunchuck controller is connected. */
-        bool nunchuckConnected;
-        /** Variable used to indicate if a Nunchuck controller is connected. */
-        bool motionPlusConnected;
-        /** Variable used to indicate if a Wii U Pro controller is connected. */
-        bool wiiUProControllerConnected;
-        /** Variable used to indicate if a Wii Balance Board is connected. */
-        bool wiiBalanceBoardConnected;
-        /**@}*/
-
-        /* IMU Data, might be usefull if you need to do something more advanced than just calculating the angle */
-
-        /**@{*/
-
-        /** Pitch and roll calculated from the accelerometer inside the Wiimote. */
-        double getWiimotePitch() {
-                return (atan2(accYwiimote, accZwiimote) + PI) * RAD_TO_DEG;
-        };
-
-        double getWiimoteRoll() {
-                return (atan2(accXwiimote, accZwiimote) + PI) * RAD_TO_DEG;
-        };
-        /**@}*/
-
-        /**@{*/
-
-        /** Pitch and roll calculated from the accelerometer inside the Nunchuck. */
-        double getNunchuckPitch() {
-                return (atan2(accYnunchuck, accZnunchuck) + PI) * RAD_TO_DEG;
-        };
-
-        double getNunchuckRoll() {
-                return (atan2(accXnunchuck, accZnunchuck) + PI) * RAD_TO_DEG;
-        };
-        /**@}*/
-
-        /**@{*/
-        /** Accelerometer values used to calculate pitch and roll. */
-        int16_t accXwiimote, accYwiimote, accZwiimote;
-        int16_t accXnunchuck, accYnunchuck, accZnunchuck;
-        /**@}*/
-
-        /* Variables for the gyro inside the Motion Plus */
-        /** This is the pitch calculated by the gyro - use this to tune WII#pitchGyroScale. */
-        double gyroPitch;
-        /** This is the roll calculated by the gyro - use this to tune WII#rollGyroScale. */
-        double gyroRoll;
-        /** This is the yaw calculated by the gyro - use this to tune WII#yawGyroScale. */
-        double gyroYaw;
-
-        /**@{*/
-        /** The speed in deg/s from the gyro. */
-        double pitchGyroSpeed;
-        double rollGyroSpeed;
-        double yawGyroSpeed;
-        /**@}*/
-
-        /**@{*/
-        /** You might need to fine-tune these values. */
-        uint16_t pitchGyroScale;
-        uint16_t rollGyroScale;
-        uint16_t yawGyroScale;
-        /**@}*/
-
-        /**@{*/
-        /** Raw value read directly from the Motion Plus. */
-        int16_t gyroYawRaw;
-        int16_t gyroRollRaw;
-        int16_t gyroPitchRaw;
-        /**@}*/
-
-        /**@{*/
-        /** These values are set when the controller is first initialized. */
-        int16_t gyroYawZero;
-        int16_t gyroRollZero;
-        int16_t gyroPitchZero;
-        /**@}*/
-
-        /** @name Wii Balance Board functions */
-
-        /**
-         * Used to get the weight at the specific position on the Wii Balance Board.
-         * @param ::BalanceBoardEnum to read from.
-         * @return Returns the weight in kg.
-         */
-        float getWeight(BalanceBoardEnum pos);
-
-        /**
-         * Used to get total weight on the Wii Balance Board.
-         * @returnReturns the weight in kg.
-         */
-        float getTotalWeight();
-
-        /**
-         * Used to get the raw reading at the specific position on the Wii Balance Board.
-         * @param ::BalanceBoardEnum to read from.
-         * @return Returns the raw reading.
-         */
-        uint16_t getWeightRaw(BalanceBoardEnum pos) {
-                return wiiBalanceBoardRaw[pos];
-        };
-        /**@}*/
-
-#ifdef WIICAMERA
-        /** @name Wiimote IR camera functions
-         * You will have to set ::ENABLE_WII_IR_CAMERA in settings.h to 1 in order use the IR camera.
-         */
-        /** Initialises the camera as per the steps from: http://wiibrew.org/wiki/Wiimote#IR_Camera */
-        void IRinitialize();
-
-        /**
-         * IR object 1 x-position read from the Wii IR camera.
-         * @return The x-position of the object in the range 0-1023.
-         */
-        uint16_t getIRx1() {
-                return IR_object_x1;
-        };
-
-        /**
-         * IR object 1 y-position read from the Wii IR camera.
-         * @return The y-position of the object in the range 0-767.
-         */
-        uint16_t getIRy1() {
-                return IR_object_y1;
-        };
-
-        /**
-         * IR object 1 size read from the Wii IR camera.
-         * @return The size of the object in the range 0-15.
-         */
-        uint8_t getIRs1() {
-                return IR_object_s1;
-        };
-
-        /**
-         * IR object 2 x-position read from the Wii IR camera.
-         * @return The x-position of the object in the range 0-1023.
-         */
-        uint16_t getIRx2() {
-                return IR_object_x2;
-        };
-
-        /**
-         * IR object 2 y-position read from the Wii IR camera.
-         * @return The y-position of the object in the range 0-767.
-         */
-        uint16_t getIRy2() {
-                return IR_object_y2;
-        };
-
-        /**
-         * IR object 2 size read from the Wii IR camera.
-         * @return The size of the object in the range 0-15.
-         */
-        uint8_t getIRs2() {
-                return IR_object_s2;
-        };
-
-        /**
-         * IR object 3 x-position read from the Wii IR camera.
-         * @return The x-position of the object in the range 0-1023.
-         */
-        uint16_t getIRx3() {
-                return IR_object_x3;
-        };
-
-        /**
-         * IR object 3 y-position read from the Wii IR camera.
-         * @return The y-position of the object in the range 0-767.
-         */
-        uint16_t getIRy3() {
-                return IR_object_y3;
-        };
-
-        /**
-         * IR object 3 size read from the Wii IR camera.
-         * @return The size of the object in the range 0-15.
-         */
-        uint8_t getIRs3() {
-                return IR_object_s3;
-        };
-
-        /**
-         * IR object 4 x-position read from the Wii IR camera.
-         * @return The x-position of the object in the range 0-1023.
-         */
-        uint16_t getIRx4() {
-                return IR_object_x4;
-        };
-
-        /**
-         * IR object 4 y-position read from the Wii IR camera.
-         * @return The y-position of the object in the range 0-767.
-         */
-        uint16_t getIRy4() {
-                return IR_object_y4;
-        };
-
-        /**
-         * IR object 4 size read from the Wii IR camera.
-         * @return The size of the object in the range 0-15.
-         */
-        uint8_t getIRs4() {
-                return IR_object_s4;
-        };
-
-        /**
-         * Use this to check if the camera is enabled or not.
-         * If not call WII#IRinitialize to initialize the IR camera.
-         * @return     True if it's enabled, false if not.
-         */
-        bool isIRCameraEnabled() {
-                return (wiiState & 0x08);
-        };
-        /**@}*/
-#endif
-
-protected:
-        /** @name BluetoothService implementation */
-        /**
-         * Used to pass acldata to the services.
-         * @param ACLData Incoming acldata.
-         */
-        void ACLData(uint8_t* ACLData);
-        /** Used to run part of the state machine. */
-        void Run();
-        /** Use this to reset the service. */
-        void Reset();
-        /**
-         * Called when the controller is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        void onInit();
-        /**@}*/
-
-private:
-
-        void L2CAP_task(); // L2CAP state machine
-
-        /* Variables filled from HCI event management */
-        bool activeConnection; // Used to indicate if it's already has established a connection
-
-        /* Variables used by high level L2CAP task */
-        uint8_t l2cap_state;
-        uint8_t wii_event_flag; // Used for Wii flags
-
-        uint32_t ButtonState;
-        uint32_t OldButtonState;
-        uint32_t ButtonClickState;
-        uint16_t hatValues[4];
-
-        uint8_t HIDBuffer[3]; // Used to store HID commands
-
-        uint16_t stateCounter;
-        bool unknownExtensionConnected;
-        bool extensionConnected;
-        bool checkBatteryLevel; // Set to true when getBatteryLevel() is called otherwise if should be false
-        bool motionPlusInside; // True if it's a new Wiimote with the Motion Plus extension build into it
-
-        /* L2CAP Channels */
-        uint8_t control_scid[2]; // L2CAP source CID for HID_Control
-        uint8_t control_dcid[2]; // 0x0060
-        uint8_t interrupt_scid[2]; // L2CAP source CID for HID_Interrupt
-        uint8_t interrupt_dcid[2]; // 0x0061
-
-        /* HID Commands */
-        void HID_Command(uint8_t* data, uint8_t nbytes);
-        void setReportMode(bool continuous, uint8_t mode);
-
-        void writeData(uint32_t offset, uint8_t size, uint8_t* data);
-        void initExtension1();
-        void initExtension2();
-
-        void statusRequest(); // Used to update the Wiimote state and battery level
-
-        void readData(uint32_t offset, uint16_t size, bool EEPROM);
-        void readExtensionType();
-        void readCalData();
-        void readWiiBalanceBoardCalibration(); // Used by the library to read the Wii Balance Board calibration values
-
-        void checkMotionPresent(); // Used to see if a Motion Plus is connected to the Wiimote
-        void initMotionPlus();
-        void activateMotionPlus();
-
-        uint16_t wiiBalanceBoardRaw[4]; // Wii Balance Board raw values
-        uint16_t wiiBalanceBoardCal[3][4]; // Wii Balance Board calibration values
-
-        double compPitch; // Fusioned angle using a complimentary filter if the Motion Plus is connected
-        double compRoll; // Fusioned angle using a complimentary filter if the Motion Plus is connected
-
-        bool activateNunchuck;
-        bool motionValuesReset; // This bool is true when the gyro values has been reset
-        uint32_t timer;
-
-        uint8_t wiiState; // Stores the value in l2capinbuf[12] - (0x01: Battery is nearly empty), (0x02:  An Extension Controller is connected), (0x04: Speaker enabled), (0x08: IR enabled), (0x10: LED1, 0x20: LED2, 0x40: LED3, 0x80: LED4)
-        uint8_t batteryLevel;
-
-#ifdef WIICAMERA
-        /* Private function and variables for the readings from the IR Camera */
-        void enableIRCamera1(); // Sets bit 2 of output report 13
-        void enableIRCamera2(); // Sets bit 2 of output report 1A
-        void writeSensitivityBlock1();
-        void writeSensitivityBlock2();
-        void write0x08Value();
-        void setWiiModeNumber(uint8_t mode_number);
-
-        uint16_t IR_object_x1; // IR x position 10 bits
-        uint16_t IR_object_y1; // IR y position 10 bits
-        uint8_t IR_object_s1; // IR size value
-        uint16_t IR_object_x2;
-        uint16_t IR_object_y2;
-        uint8_t IR_object_s2;
-        uint16_t IR_object_x3; // IR x position 10 bits
-        uint16_t IR_object_y3; // IR y position 10 bits
-        uint8_t IR_object_s3; // IR size value
-        uint16_t IR_object_x4;
-        uint16_t IR_object_y4;
-        uint8_t IR_object_s4;
-#endif
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/WiiCameraReadme.md b/lib/usbhost/USB_Host_Shield_2.0/WiiCameraReadme.md
deleted file mode 100644
index 8577d73fb3..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/WiiCameraReadme.md
+++ /dev/null
@@ -1,13 +0,0 @@
-Please see <http://wiibrew.org/wiki/Wiimote#IR_Camera> for the complete capabilities of the Wii camera. The IR camera code was written based on the above website and with support from Kristian Lauszus.
-
-This library is large, if you run into memory problems when uploading to the Arduino, disable serial debugging.
-
-To enable the IR camera code, simply set ```ENABLE_WII_IR_CAMERA``` to 1 in [settings.h](settings.h).
-
-This library implements the following settings:
-
-* Report sensitivity mode: 00 00 00 00 00 00 90 00 41	 40 00	 Suggested by inio (high sensitivity)
-* Data Format: Extended mode (0x03).  Full mode is not working yet. The output reports 0x3e and 0x3f need tampering with
-	* In this mode the camera outputs x and y coordinates and a size dimension for the 4 brightest points.
-
-Again, read through <http://wiibrew.org/wiki/Wiimote#IR_Camera> to get an understanding of the camera and its settings.
diff --git a/lib/usbhost/USB_Host_Shield_2.0/XBOXOLD.cpp b/lib/usbhost/USB_Host_Shield_2.0/XBOXOLD.cpp
deleted file mode 100644
index 78e6e9a5f5..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/XBOXOLD.cpp
+++ /dev/null
@@ -1,337 +0,0 @@
-/* Copyright (C) 2013 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#include "XBOXOLD.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-//#define PRINTREPORT // Uncomment to print the report send by the Xbox controller
-
-/** Buttons on the controllers */
-const uint8_t XBOXOLD_BUTTONS[] PROGMEM = {
-        0x01, // UP
-        0x08, // RIGHT
-        0x02, // DOWN
-        0x04, // LEFT
-
-        0x20, // BACK
-        0x10, // START
-        0x40, // L3
-        0x80, // R3
-
-        // A, B, X, Y, BLACK, WHITE, L1, and R1 are analog buttons
-        4, // BLACK
-        5, // WHTIE
-        6, // L1
-        7, // R1
-
-        1, // B
-        0, // A
-        2, // X
-        3, // Y
-};
-
-XBOXOLD::XBOXOLD(USB *p) :
-pUsb(p), // pointer to USB class instance - mandatory
-bAddress(0), // device address - mandatory
-bPollEnable(false) { // don't start polling before dongle is connected
-        for(uint8_t i = 0; i < XBOX_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-        }
-
-        if(pUsb) // register in USB subsystem
-                pUsb->RegisterDeviceClass(this); //set devConfig[] entry
-}
-
-uint8_t XBOXOLD::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        uint8_t buf[sizeof (USB_DEVICE_DESCRIPTOR)];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint16_t PID;
-        uint16_t VID;
-
-        // get memory address of USB device address pool
-        AddressPool &addrPool = pUsb->GetAddressPool();
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nXBOXUSB Init"), 0x80);
-#endif
-        // check if address has already been assigned to an instance
-        if(bAddress) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress in use"), 0x80);
-#endif
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-        }
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        if(!p->epinfo) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nepinfo is null"), 0x80);
-#endif
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, sizeof (USB_DEVICE_DESCRIPTOR), (uint8_t*)buf); // Get device descriptor - addr, ep, nbytes, data
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        VID = udd->idVendor;
-        PID = udd->idProduct;
-
-        if((VID != XBOX_VID && VID != MADCATZ_VID && VID != JOYTECH_VID) || (PID != XBOX_OLD_PID1 && PID != XBOX_OLD_PID2 && PID != XBOX_OLD_PID3 && PID != XBOX_OLD_PID4)) // Check if VID and PID match
-                goto FailUnknownDevice;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nsetAddr: "), 0x80);
-                D_PrintHex<uint8_t > (rcode, 0x80);
-#endif
-                return rcode;
-        }
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nAddr: "), 0x80);
-        D_PrintHex<uint8_t > (bAddress, 0x80);
-#endif
-        //delay(300); // Spec says you should wait at least 200ms
-
-        p->lowspeed = false;
-
-        //get pointer to assigned address record
-        p = addrPool.GetUsbDevicePtr(bAddress);
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        // Assign epInfo to epinfo pointer - only EP0 is known
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        /* The application will work in reduced host mode, so we can save program and data
-           memory space. After verifying the VID we will use known values for the
-           configuration values for device, interface, endpoints and HID for the XBOX controllers */
-
-        /* Initialize data structures for endpoints of device */
-        epInfo[ XBOX_INPUT_PIPE ].epAddr = 0x01; // XBOX report endpoint
-        epInfo[ XBOX_INPUT_PIPE ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_INPUT_PIPE ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_INPUT_PIPE ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_INPUT_PIPE ].bmSndToggle = 0;
-        epInfo[ XBOX_INPUT_PIPE ].bmRcvToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE ].epAddr = 0x02; // XBOX output endpoint
-        epInfo[ XBOX_OUTPUT_PIPE ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_OUTPUT_PIPE ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_OUTPUT_PIPE ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_OUTPUT_PIPE ].bmSndToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE ].bmRcvToggle = 0;
-
-        rcode = pUsb->setEpInfoEntry(bAddress, 3, epInfo);
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        delay(200); // Give time for address change
-
-        rcode = pUsb->setConf(bAddress, epInfo[ XBOX_CONTROL_PIPE ].epAddr, 1);
-        if(rcode)
-                goto FailSetConfDescr;
-
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox Controller Connected\r\n"), 0x80);
-#endif
-        if(pFuncOnInit)
-                pFuncOnInit(); // Call the user function
-        XboxConnected = true;
-        bPollEnable = true;
-        return 0; // Successful configuration
-
-        /* Diagnostic messages */
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-#endif
-        goto Fail;
-
-FailUnknownDevice:
-#ifdef DEBUG_USB_HOST
-        NotifyFailUnknownDevice(VID, PID);
-#endif
-        rcode = USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-Fail:
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox Init Failed, error code: "), 0x80);
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-/* Performs a cleanup after failed Init() attempt */
-uint8_t XBOXOLD::Release() {
-        XboxConnected = false;
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-        bAddress = 0;
-        bPollEnable = false;
-        return 0;
-}
-
-uint8_t XBOXOLD::Poll() {
-        if(!bPollEnable)
-                return 0;
-        uint16_t BUFFER_SIZE = EP_MAXPKTSIZE;
-        pUsb->inTransfer(bAddress, epInfo[ XBOX_INPUT_PIPE ].epAddr, &BUFFER_SIZE, readBuf); // input on endpoint 1
-        readReport();
-#ifdef PRINTREPORT
-        printReport(BUFFER_SIZE); // Uncomment "#define PRINTREPORT" to print the report send by the Xbox controller
-#endif
-        return 0;
-}
-
-void XBOXOLD::readReport() {
-        ButtonState = readBuf[2];
-
-        for(uint8_t i = 0; i < sizeof (buttonValues); i++)
-                buttonValues[i] = readBuf[i + 4]; // A, B, X, Y, BLACK, WHITE, L1, and R1
-
-        hatValue[LeftHatX] = (int16_t)(((uint16_t)readBuf[12] << 8) | readBuf[13]);
-        hatValue[LeftHatY] = (int16_t)(((uint16_t)readBuf[14] << 8) | readBuf[15]);
-        hatValue[RightHatX] = (int16_t)(((uint16_t)readBuf[16] << 8) | readBuf[17]);
-        hatValue[RightHatY] = (int16_t)(((uint16_t)readBuf[18] << 8) | readBuf[19]);
-
-        //Notify(PSTR("\r\nButtonState"), 0x80);
-        //PrintHex<uint8_t>(ButtonState, 0x80);
-
-        if(ButtonState != OldButtonState || memcmp(buttonValues, oldButtonValues, sizeof (buttonValues)) != 0) {
-                ButtonClickState = ButtonState & ~OldButtonState; // Update click state variable
-                OldButtonState = ButtonState;
-
-                for(uint8_t i = 0; i < sizeof (buttonValues); i++) {
-                        if(oldButtonValues[i] == 0 && buttonValues[i] != 0)
-                                buttonClicked[i] = true; // Update A, B, X, Y, BLACK, WHITE, L1, and R1 click state
-                        oldButtonValues[i] = buttonValues[i];
-                }
-        }
-}
-
-void XBOXOLD::printReport(uint16_t length) { //Uncomment "#define PRINTREPORT" to print the report send by the Xbox controller
-#ifdef PRINTREPORT
-        if(readBuf == NULL)
-                return;
-        for(uint8_t i = 0; i < length; i++) {
-                D_PrintHex<uint8_t > (readBuf[i], 0x80);
-                Notify(PSTR(" "), 0x80);
-        }
-        Notify(PSTR("\r\n"), 0x80);
-#endif
-}
-
-uint8_t XBOXOLD::getButtonPress(ButtonEnum b) {
-        uint8_t button = pgm_read_byte(&XBOXOLD_BUTTONS[(uint8_t)b]);
-        if(b == A || b == B || b == X || b == Y || b == BLACK || b == WHITE || b == L1 || b == R1) // A, B, X, Y, BLACK, WHITE, L1, and R1 are analog buttons
-                return buttonValues[button]; // Analog buttons
-        return (ButtonState & button); // Digital buttons
-}
-
-bool XBOXOLD::getButtonClick(ButtonEnum b) {
-        uint8_t button = pgm_read_byte(&XBOXOLD_BUTTONS[(uint8_t)b]);
-        if(b == A || b == B || b == X || b == Y || b == BLACK || b == WHITE || b == L1 || b == R1) { // A, B, X, Y, BLACK, WHITE, L1, and R1 are analog buttons
-                if(buttonClicked[button]) {
-                        buttonClicked[button] = false;
-                        return true;
-                }
-                return false;
-        }
-
-        bool click = (ButtonClickState & button);
-        ButtonClickState &= ~button; // clear "click" event
-        return click;
-}
-
-int16_t XBOXOLD::getAnalogHat(AnalogHatEnum a) {
-        return hatValue[a];
-}
-
-/* Xbox Controller commands */
-void XBOXOLD::XboxCommand(uint8_t* data, uint16_t nbytes) {
-        //bmRequest = Host to device (0x00) | Class (0x20) | Interface (0x01) = 0x21, bRequest = Set Report (0x09), Report ID (0x00), Report Type (Output 0x02), interface (0x00), datalength, datalength, data)
-        pUsb->ctrlReq(bAddress, epInfo[XBOX_CONTROL_PIPE].epAddr, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, 0x00, 0x02, 0x00, nbytes, nbytes, data, NULL);
-}
-
-void XBOXOLD::setRumbleOn(uint8_t lValue, uint8_t rValue) {
-        uint8_t writeBuf[6];
-
-        writeBuf[0] = 0x00;
-        writeBuf[1] = 0x06;
-        writeBuf[2] = 0x00;
-        writeBuf[3] = rValue; // small weight
-        writeBuf[4] = 0x00;
-        writeBuf[5] = lValue; // big weight
-
-        XboxCommand(writeBuf, 6);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/XBOXOLD.h b/lib/usbhost/USB_Host_Shield_2.0/XBOXOLD.h
deleted file mode 100644
index 9a36b5ccac..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/XBOXOLD.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* Copyright (C) 2013 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _xboxold_h_
-#define _xboxold_h_
-
-#include "Usb.h"
-#include "hid.h"
-#include "controllerEnums.h"
-
-/* Data Xbox taken from descriptors */
-#define EP_MAXPKTSIZE       32 // Max size for data via USB
-
-/* Names we give to the 3 Xbox pipes */
-#define XBOX_CONTROL_PIPE    0
-#define XBOX_INPUT_PIPE      1
-#define XBOX_OUTPUT_PIPE     2
-
-// PID and VID of the different devices
-#define XBOX_VID                                0x045E // Microsoft Corporation
-#define MADCATZ_VID                             0x1BAD // For unofficial Mad Catz controllers
-#define JOYTECH_VID                             0x162E // For unofficial Joytech controllers
-
-#define XBOX_OLD_PID1                           0x0202 // Original Microsoft Xbox controller (US)
-#define XBOX_OLD_PID2                           0x0285 // Original Microsoft Xbox controller (Japan)
-#define XBOX_OLD_PID3                           0x0287 // Microsoft Microsoft Xbox Controller S
-#define XBOX_OLD_PID4                           0x0289 // Smaller Microsoft Xbox controller (US)
-
-#define XBOX_MAX_ENDPOINTS   3
-
-/** This class implements support for a the original Xbox controller via USB. */
-class XBOXOLD : public USBDeviceConfig {
-public:
-        /**
-         * Constructor for the XBOXOLD class.
-         * @param  pUsb   Pointer to USB class instance.
-         */
-        XBOXOLD(USB *pUsb);
-
-        /** @name USBDeviceConfig implementation */
-        /**
-         * Initialize the Xbox Controller.
-         * @param  parent   Hub number.
-         * @param  port     Port number on the hub.
-         * @param  lowspeed Speed of the device.
-         * @return          0 on success.
-         */
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        /**
-         * Release the USB device.
-         * @return 0 on success.
-         */
-        uint8_t Release();
-        /**
-         * Poll the USB Input endpoins and run the state machines.
-         * @return 0 on success.
-         */
-        uint8_t Poll();
-
-        /**
-         * Get the device address.
-         * @return The device address.
-         */
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        /**
-         * Used to check if the controller has been initialized.
-         * @return True if it's ready.
-         */
-        virtual bool isReady() {
-                return bPollEnable;
-        };
-
-        /**
-         * Used by the USB core to check what this driver support.
-         * @param  vid The device's VID.
-         * @param  pid The device's PID.
-         * @return     Returns true if the device's VID and PID matches this driver.
-         */
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return ((vid == XBOX_VID || vid == MADCATZ_VID || vid == JOYTECH_VID) && (pid == XBOX_OLD_PID1 || pid == XBOX_OLD_PID2 || pid == XBOX_OLD_PID3 || pid == XBOX_OLD_PID4));
-        };
-        /**@}*/
-
-        /** @name Xbox Controller functions */
-        /**
-         * getButtonPress(ButtonEnum b) will return true as long as the button is held down.
-         *
-         * While getButtonClick(ButtonEnum b) will only return it once.
-         *
-         * So you instance if you need to increase a variable once you would use getButtonClick(ButtonEnum b),
-         * but if you need to drive a robot forward you would use getButtonPress(ButtonEnum b).
-         * @param  b          ::ButtonEnum to read.
-         * @return            getButtonClick(ButtonEnum b) will return a bool, while getButtonPress(ButtonEnum b) will return a byte if reading ::L2 or ::R2.
-         */
-        uint8_t getButtonPress(ButtonEnum b);
-        bool getButtonClick(ButtonEnum b);
-        /**@}*/
-
-        /** @name Xbox Controller functions */
-        /**
-         * Return the analog value from the joysticks on the controller.
-         * @param  a          Either ::LeftHatX, ::LeftHatY, ::RightHatX or ::RightHatY.
-         * @return            Returns a signed 16-bit integer.
-         */
-        int16_t getAnalogHat(AnalogHatEnum a);
-
-        /** Turn rumble off the controller. */
-        void setRumbleOff() {
-                setRumbleOn(0, 0);
-        };
-        /**
-         * Turn rumble on.
-         * @param lValue     Left motor (big weight) inside the controller.
-         * @param rValue     Right motor (small weight) inside the controller.
-         */
-        void setRumbleOn(uint8_t lValue, uint8_t rValue);
-
-        /**
-         * Used to call your own function when the controller is successfully initialized.
-         * @param funcOnInit Function to call.
-         */
-        void attachOnInit(void (*funcOnInit)(void)) {
-                pFuncOnInit = funcOnInit;
-        };
-        /**@}*/
-
-        /** True if a Xbox controller is connected. */
-        bool XboxConnected;
-
-protected:
-        /** Pointer to USB class instance. */
-        USB *pUsb;
-        /** Device address. */
-        uint8_t bAddress;
-        /** Endpoint info structure. */
-        EpInfo epInfo[XBOX_MAX_ENDPOINTS];
-
-private:
-        /**
-         * Called when the controller is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        void (*pFuncOnInit)(void); // Pointer to function called in onInit()
-
-        bool bPollEnable;
-
-        /* Variables to store the digital buttons */
-        uint8_t ButtonState;
-        uint8_t OldButtonState;
-        uint8_t ButtonClickState;
-
-        /* Variables to store the analog buttons */
-        uint8_t buttonValues[8]; // A, B, X, Y, BLACK, WHITE, L1, and R1
-        uint8_t oldButtonValues[8];
-        bool buttonClicked[8];
-
-        int16_t hatValue[4]; // Joystick values
-
-        uint8_t readBuf[EP_MAXPKTSIZE]; // General purpose buffer for input data
-
-        void readReport(); // Read incoming data
-        void printReport(uint16_t length); // Print incoming date
-
-        /* Private commands */
-        void XboxCommand(uint8_t* data, uint16_t nbytes);
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/XBOXONE.cpp b/lib/usbhost/USB_Host_Shield_2.0/XBOXONE.cpp
deleted file mode 100644
index 2159c0528b..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/XBOXONE.cpp
+++ /dev/null
@@ -1,374 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-   Copyright (C) 2015 guruthree
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
-
- guruthree
- Web      :  https://github.com/guruthree/
- */
-
-#include "XBOXONE.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-//#define PRINTREPORT // Uncomment to print the report send by the Xbox ONE Controller
-
-XBOXONE::XBOXONE(USB *p) :
-pUsb(p), // pointer to USB class instance - mandatory
-bAddress(0), // device address - mandatory
-bPollEnable(false) { // don't start polling before dongle is connected
-        for(uint8_t i = 0; i < XBOX_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-        }
-
-        if(pUsb) // register in USB subsystem
-                pUsb->RegisterDeviceClass(this); //set devConfig[] entry
-}
-
-uint8_t XBOXONE::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        uint8_t buf[sizeof (USB_DEVICE_DESCRIPTOR)];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint16_t PID;
-        uint16_t VID;
-
-        // get memory address of USB device address pool
-        AddressPool &addrPool = pUsb->GetAddressPool();
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nXBOXONE Init"), 0x80);
-#endif
-        // check if address has already been assigned to an instance
-        if(bAddress) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress in use"), 0x80);
-#endif
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-        }
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        if(!p->epinfo) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nepinfo is null"), 0x80);
-#endif
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, sizeof (USB_DEVICE_DESCRIPTOR), (uint8_t*)buf); // Get device descriptor - addr, ep, nbytes, data
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        VID = udd->idVendor;
-        PID = udd->idProduct;
-
-        if(!VIDPIDOK(VID, PID)) // Check VID
-                goto FailUnknownDevice;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nsetAddr: "), 0x80);
-                D_PrintHex<uint8_t > (rcode, 0x80);
-#endif
-                return rcode;
-        }
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nAddr: "), 0x80);
-        D_PrintHex<uint8_t > (bAddress, 0x80);
-#endif
-        //delay(300); // Spec says you should wait at least 200ms
-
-        p->lowspeed = false;
-
-        //get pointer to assigned address record
-        p = addrPool.GetUsbDevicePtr(bAddress);
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        // Assign epInfo to epinfo pointer - only EP0 is known
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        /* The application will work in reduced host mode, so we can save program and data
-           memory space. After verifying the VID we will use known values for the
-           configuration values for device, interface, endpoints and HID for the XBOXONE Controllers */
-
-        /* Initialize data structures for endpoints of device */
-        epInfo[ XBOX_OUTPUT_PIPE ].epAddr = 0x01; // XBOX one output endpoint
-        epInfo[ XBOX_OUTPUT_PIPE ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_OUTPUT_PIPE ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_OUTPUT_PIPE ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_OUTPUT_PIPE ].bmSndToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE ].bmRcvToggle = 0;
-        epInfo[ XBOX_INPUT_PIPE ].epAddr = 0x01; // XBOX one input endpoint
-        epInfo[ XBOX_INPUT_PIPE ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_INPUT_PIPE ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_INPUT_PIPE ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_INPUT_PIPE ].bmSndToggle = 0;
-        epInfo[ XBOX_INPUT_PIPE ].bmRcvToggle = 0;
-
-        rcode = pUsb->setEpInfoEntry(bAddress, 3, epInfo);
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        delay(200); // Give time for address change
-
-        rcode = pUsb->setConf(bAddress, epInfo[ XBOX_CONTROL_PIPE ].epAddr, 1);
-        if(rcode)
-                goto FailSetConfDescr;
-
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox One Controller Connected\r\n"), 0x80);
-#endif
-
-        delay(200); // let things settle
-
-        // initialize the controller for input
-        writeBuf[0] = 0x05;
-        writeBuf[1] = 0x20;
-        rcode = XboxCommand(writeBuf, 2);
-        if (rcode)
-                goto Fail;
-
-        onInit();
-        XboxOneConnected = true;
-        bPollEnable = true;
-        return 0; // Successful configuration
-
-        /* Diagnostic messages */
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-#endif
-        goto Fail;
-
-FailUnknownDevice:
-#ifdef DEBUG_USB_HOST
-        NotifyFailUnknownDevice(VID, PID);
-#endif
-        rcode = USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-Fail:
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox One Init Failed, error code: "), 0x80);
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-/* Performs a cleanup after failed Init() attempt */
-uint8_t XBOXONE::Release() {
-        XboxOneConnected = false;
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-        bAddress = 0;
-        bPollEnable = false;
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox One Controller Disconnected\r\n"), 0x80);
-#endif
-        return 0;
-}
-
-uint8_t XBOXONE::Poll() {
-        if(!bPollEnable)
-                return 0;
-        uint16_t BUFFER_SIZE = EP_MAXPKTSIZE;
-        uint8_t rcode = pUsb->inTransfer(bAddress, epInfo[ XBOX_INPUT_PIPE ].epAddr, &BUFFER_SIZE, readBuf);
-        if (!rcode) {
-                readReport();
-#ifdef PRINTREPORT
-                printReport(); // Uncomment "#define PRINTREPORT" to print the report send by the Xbox ONE Controller
-#endif
-        }
-#ifdef DEBUG_USB_HOST
-                else if (rcode != 0x04) { // not a matter of no update to send
-                Notify(PSTR("\r\nXbox One Poll Failed, error code: "), 0x80);
-                NotifyFail(rcode);
-                }
-#endif
-        return rcode;
-}
-
-void XBOXONE::readReport() {
-        if(readBuf == NULL)
-                return;
-        if(readBuf[0] == 0x07) {
-                // The XBOX button has a separate message
-                if(readBuf[4] == 1)
-                        ButtonState |= XBOX_BUTTONS[XBOX];
-                else
-                        ButtonState &= ~XBOX_BUTTONS[XBOX];
-        }
-        if(readBuf[0] != 0x20) { // Check if it's the correct report, otherwise return - the controller also sends different status reports
-#ifdef EXTRADEBUG
-                Notify(PSTR("\r\nXbox Poll: "), 0x80);
-                D_PrintHex<uint8_t > (readBuf[0], 0x80); // 0x03 is a heart beat report!
-#endif
-                return;
-        }
-
-        uint16_t xbox = ButtonState & XBOX_BUTTONS[XBOX]; // Since the XBOX button is separate, save it and add it back in
-        // xbox button from before, dpad, abxy, start/back, sync, stick click, shoulder buttons
-        ButtonState = xbox | (((uint16_t)readBuf[5] & 0xF) << 8) | (readBuf[4] & 0xF0)  | (((uint16_t)readBuf[4] & 0x0C) << 10) | ((readBuf[4] & 0x01) << 3) | (((uint16_t)readBuf[5] & 0xC0) << 8) | ((readBuf[5] & 0x30) >> 4);
-
-        triggerValue[0] = (uint16_t)(((uint16_t)readBuf[7] << 8) | readBuf[6]);
-        triggerValue[1] = (uint16_t)(((uint16_t)readBuf[9] << 8) | readBuf[8]);
-
-        hatValue[LeftHatX] = (int16_t)(((uint16_t)readBuf[11] << 8) | readBuf[10]);
-        hatValue[LeftHatY] = (int16_t)(((uint16_t)readBuf[13] << 8) | readBuf[12]);
-        hatValue[RightHatX] = (int16_t)(((uint16_t)readBuf[15] << 8) | readBuf[14]);
-        hatValue[RightHatY] = (int16_t)(((uint16_t)readBuf[17] << 8) | readBuf[16]);
-
-        //Notify(PSTR("\r\nButtonState"), 0x80);
-        //PrintHex<uint16_t>(ButtonState, 0x80);
-
-        if(ButtonState != OldButtonState) {
-                ButtonClickState = ButtonState & ~OldButtonState; // Update click state variable
-                OldButtonState = ButtonState;
-        }
-
-        // Handle click detection for triggers
-        if(triggerValue[0] != 0 && triggerValueOld[0] == 0)
-            L2Clicked = true;
-        triggerValueOld[0] = triggerValue[0];
-        if(triggerValue[1] != 0 && triggerValueOld[1] == 0)
-            R2Clicked = true;
-        triggerValueOld[1] = triggerValue[1];
-}
-
-void XBOXONE::printReport() { //Uncomment "#define PRINTREPORT" to print the report send by the Xbox ONE Controller
-#ifdef PRINTREPORT
-        if(readBuf == NULL)
-                return;
-        for(uint8_t i = 0; i < XBOX_REPORT_BUFFER_SIZE; i++) {
-                D_PrintHex<uint8_t > (readBuf[i], 0x80);
-                Notify(PSTR(" "), 0x80);
-        }
-        Notify(PSTR("\r\n"), 0x80);
-#endif
-}
-
-uint16_t XBOXONE::getButtonPress(ButtonEnum b) {
-        if(b == L2) // These are analog buttons
-                return triggerValue[0];
-        else if(b == R2)
-                return triggerValue[1];
-        return (bool)(ButtonState & ((uint16_t)pgm_read_word(&XBOX_BUTTONS[(uint8_t)b])));
-}
-
-bool XBOXONE::getButtonClick(ButtonEnum b) {
-        if(b == L2) {
-                if(L2Clicked) {
-                        L2Clicked = false;
-                        return true;
-                }
-                return false;
-        } else if(b == R2) {
-                if(R2Clicked) {
-                        R2Clicked = false;
-                        return true;
-                }
-                return false;
-        }
-        uint16_t button = pgm_read_word(&XBOX_BUTTONS[(uint8_t)b]);
-        bool click = (ButtonClickState & button);
-        ButtonClickState &= ~button; // clear "click" event
-        return click;
-}
-
-int16_t XBOXONE::getAnalogHat(AnalogHatEnum a) {
-        return hatValue[a];
-}
-
-/* Xbox Controller commands */
-uint8_t XBOXONE::XboxCommand(uint8_t* data, uint16_t nbytes) {
-        uint8_t rcode = pUsb->outTransfer(bAddress, epInfo[ XBOX_OUTPUT_PIPE ].epAddr, nbytes, data);
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXboxCommand, Return: "), 0x80);
-        D_PrintHex<uint8_t > (rcode, 0x80);
-#endif
-        return rcode;
-}
-
-void XBOXONE::onInit() {
-        // a short buzz to show the controller is active
-        writeBuf[0] = 0x09;
-        writeBuf[1] = 0x08;
-        writeBuf[2] = 0x00;
-        writeBuf[3] = 0x09;
-        writeBuf[4] = 0x00;
-        writeBuf[5] = 0x0f;
-        writeBuf[6] = 0x04;
-        writeBuf[7] = 0x04;
-        writeBuf[8] = 0x20;
-        writeBuf[9] = 0x20;
-        writeBuf[10] = 0x80;
-        XboxCommand(writeBuf, 11);
-
-        if(pFuncOnInit)
-                pFuncOnInit(); // Call the user function
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/XBOXONE.h b/lib/usbhost/USB_Host_Shield_2.0/XBOXONE.h
deleted file mode 100644
index 11710fcf1a..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/XBOXONE.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-   Copyright (C) 2015 guruthree
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
-
- guruthree
- Web      :  https://github.com/guruthree/
- */
-
-
-#ifndef _xboxone_h_
-#define _xboxone_h_
-
-#include "Usb.h"
-#include "xboxEnums.h"
-
-/* Data Xbox ONE taken from descriptors */
-#define EP_MAXPKTSIZE       32 // max size for data via USB
-
-/* Names we give to the 3 XboxONE pipes */
-#define XBOX_CONTROL_PIPE    0
-#define XBOX_OUTPUT_PIPE     1
-#define XBOX_INPUT_PIPE      2
-
-// PID and VID of the different devices
-#define XBOX_VID                                0x045E // Microsoft Corporation
-#define XBOX_ONE_PID                            0x02D1 // Microsoft One Wired controller
-
-#define XBOX_REPORT_BUFFER_SIZE 14 // Size of the input report buffer
-
-#define XBOX_MAX_ENDPOINTS   3
-
-/** This class implements support for a Xbox ONE controller connected via USB. */
-class XBOXONE : public USBDeviceConfig {
-public:
-        /**
-         * Constructor for the XBOXONE class.
-         * @param  pUsb   Pointer to USB class instance.
-         */
-        XBOXONE(USB *pUsb);
-
-        /** @name USBDeviceConfig implementation */
-        /**
-         * Initialize the Xbox Controller.
-         * @param  parent   Hub number.
-         * @param  port     Port number on the hub.
-         * @param  lowspeed Speed of the device.
-         * @return          0 on success.
-         */
-        virtual uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        /**
-         * Release the USB device.
-         * @return 0 on success.
-         */
-        virtual uint8_t Release();
-        /**
-         * Poll the USB Input endpoins and run the state machines.
-         * @return 0 on success.
-         */
-        virtual uint8_t Poll();
-
-        /**
-         * Get the device address.
-         * @return The device address.
-         */
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        /**
-         * Used to check if the controller has been initialized.
-         * @return True if it's ready.
-         */
-        virtual bool isReady() {
-                return bPollEnable;
-        };
-
-        /**
-         * Used by the USB core to check what this driver support.
-         * @param  vid The device's VID.
-         * @param  pid The device's PID.
-         * @return     Returns true if the device's VID and PID matches this driver.
-         */
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return (vid == XBOX_VID && pid == XBOX_ONE_PID);
-        };
-        /**@}*/
-
-        /** @name Xbox Controller functions */
-        /**
-         * getButtonPress(ButtonEnum b) will return true as long as the button is held down.
-         *
-         * While getButtonClick(ButtonEnum b) will only return it once.
-         *
-         * So you instance if you need to increase a variable once you would use getButtonClick(ButtonEnum b),
-         * but if you need to drive a robot forward you would use getButtonPress(ButtonEnum b).
-         * @param  b          ::ButtonEnum to read.
-         * @return            getButtonClick(ButtonEnum b) will return a bool, while getButtonPress(ButtonEnum b) will return a word if reading ::L2 or ::R2.
-         */
-        uint16_t getButtonPress(ButtonEnum b);
-        bool getButtonClick(ButtonEnum b);
-
-        /**
-         * Return the analog value from the joysticks on the controller.
-         * @param  a          Either ::LeftHatX, ::LeftHatY, ::RightHatX or ::RightHatY.
-         * @return            Returns a signed 16-bit integer.
-         */
-        int16_t getAnalogHat(AnalogHatEnum a);
-
-        /**
-         * Used to call your own function when the controller is successfully initialized.
-         * @param funcOnInit Function to call.
-         */
-        void attachOnInit(void (*funcOnInit)(void)) {
-                pFuncOnInit = funcOnInit;
-        };
-        /**@}*/
-
-        /** True if a Xbox ONE controller is connected. */
-        bool XboxOneConnected;
-
-protected:
-        /** Pointer to USB class instance. */
-        USB *pUsb;
-        /** Device address. */
-        uint8_t bAddress;
-        /** Endpoint info structure. */
-        EpInfo epInfo[XBOX_MAX_ENDPOINTS];
-
-private:
-        /**
-         * Called when the controller is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         */
-        void onInit();
-        void (*pFuncOnInit)(void); // Pointer to function called in onInit()
-
-        bool bPollEnable;
-
-        /* Variables to store the buttons */
-        uint16_t ButtonState;
-        uint16_t OldButtonState;
-        uint16_t ButtonClickState;
-        int16_t hatValue[4];
-        uint16_t triggerValue[2];
-        uint16_t triggerValueOld[2];
-
-        bool L2Clicked; // These buttons are analog, so we use we use these bools to check if they where clicked or not
-        bool R2Clicked;
-
-        uint8_t readBuf[EP_MAXPKTSIZE]; // General purpose buffer for input data
-        uint8_t writeBuf[12]; // General purpose buffer for output data
-
-        void readReport(); // read incoming data
-        void printReport(); // print incoming date - Uncomment for debugging
-
-        /* Private commands */
-        uint8_t XboxCommand(uint8_t* data, uint16_t nbytes);
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/XBOXRECV.cpp b/lib/usbhost/USB_Host_Shield_2.0/XBOXRECV.cpp
deleted file mode 100644
index 41f1ff5816..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/XBOXRECV.cpp
+++ /dev/null
@@ -1,583 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
-
- getBatteryLevel and checkStatus functions made by timstamp.co.uk found using BusHound from Perisoft.net
- */
-
-#include "XBOXRECV.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-//#define PRINTREPORT // Uncomment to print the report send by the Xbox 360 Controller
-
-XBOXRECV::XBOXRECV(USB *p) :
-pUsb(p), // pointer to USB class instance - mandatory
-bAddress(0), // device address - mandatory
-bPollEnable(false) { // don't start polling before dongle is connected
-        for(uint8_t i = 0; i < XBOX_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-        }
-
-        if(pUsb) // register in USB subsystem
-                pUsb->RegisterDeviceClass(this); //set devConfig[] entry
-}
-
-uint8_t XBOXRECV::ConfigureDevice(uint8_t parent, uint8_t port, bool lowspeed) {
-        const uint8_t constBufSize = sizeof (USB_DEVICE_DESCRIPTOR);
-        uint8_t buf[constBufSize];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint16_t PID, VID;
-
-        AddressPool &addrPool = pUsb->GetAddressPool(); // Get memory address of USB device address pool
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nXBOXRECV Init"), 0x80);
-#endif
-
-        if(bAddress) { // Check if address has already been assigned to an instance
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress in use"), 0x80);
-#endif
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-        }
-
-        p = addrPool.GetUsbDevicePtr(0); // Get pointer to pseudo device with address 0 assigned
-
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        if(!p->epinfo) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nepinfo is null"), 0x80);
-#endif
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        oldep_ptr = p->epinfo; // Save old pointer to EP_RECORD of address 0
-        p->epinfo = epInfo; // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->lowspeed = lowspeed;
-
-        rcode = pUsb->getDevDescr(0, 0, constBufSize, (uint8_t*)buf); // Get device descriptor - addr, ep, nbytes, data
-
-        p->epinfo = oldep_ptr; // Restore p->epinfo
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        VID = udd->idVendor;
-        PID = udd->idProduct;
-
-        if((VID != XBOX_VID && VID != MADCATZ_VID && VID != JOYTECH_VID) || (PID != XBOX_WIRELESS_RECEIVER_PID && PID != XBOX_WIRELESS_RECEIVER_THIRD_PARTY_PID)) { // Check if it's a Xbox receiver using the Vendor ID and Product ID
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nYou'll need a wireless receiver for this libary to work"), 0x80);
-#endif
-                goto FailUnknownDevice;
-        }
-
-        bAddress = addrPool.AllocAddress(parent, false, port); // Allocate new address according to device class
-
-        if(!bAddress) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nOut of address space"), 0x80);
-#endif
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-        }
-
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0; // Extract Max Packet Size from device descriptor
-
-        delay(20); // Wait a little before resetting device
-
-        return USB_ERROR_CONFIG_REQUIRES_ADDITIONAL_RESET;
-
-        /* Diagnostic messages */
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr(rcode);
-#endif
-        if(rcode != hrJERR)
-                rcode = USB_ERROR_FailGetDevDescr;
-        goto Fail;
-
-FailUnknownDevice:
-#ifdef DEBUG_USB_HOST
-        NotifyFailUnknownDevice(VID, PID);
-#endif
-        rcode = USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-Fail:
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox 360 Init Failed, error code: "), 0x80);
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-};
-
-uint8_t XBOXRECV::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        uint8_t rcode;
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nBTD Init"), 0x80);
-#endif
-        UsbDevice *p = addrPool.GetUsbDevicePtr(bAddress); // Get pointer to assigned address record
-
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        delay(300); // Assign new address to the device
-
-        rcode = pUsb->setAddr(0, 0, bAddress); // Assign new address to the device
-        if(rcode) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nsetAddr: "), 0x80);
-                D_PrintHex<uint8_t > (rcode, 0x80);
-#endif
-                p->lowspeed = false;
-                goto Fail;
-        }
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nAddr: "), 0x80);
-        D_PrintHex<uint8_t > (bAddress, 0x80);
-#endif
-
-        p->lowspeed = false;
-
-        p = addrPool.GetUsbDevicePtr(bAddress); // Get pointer to assigned address record
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        p->lowspeed = lowspeed;
-
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo); // Assign epInfo to epinfo pointer - only EP0 is known
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        /* The application will work in reduced host mode, so we can save program and data
-           memory space. After verifying the VID we will use known values for the
-           configuration values for device, interface, endpoints and HID for the XBOX360 Wireless receiver */
-
-        /* Initialize data structures for endpoints of device */
-        epInfo[ XBOX_INPUT_PIPE_1 ].epAddr = 0x01; // XBOX 360 report endpoint - poll interval 1ms
-        epInfo[ XBOX_INPUT_PIPE_1 ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_INPUT_PIPE_1 ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_INPUT_PIPE_1 ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_INPUT_PIPE_1 ].bmSndToggle = 0;
-        epInfo[ XBOX_INPUT_PIPE_1 ].bmRcvToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE_1 ].epAddr = 0x01; // XBOX 360 output endpoint - poll interval 8ms
-        epInfo[ XBOX_OUTPUT_PIPE_1 ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_OUTPUT_PIPE_1 ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_OUTPUT_PIPE_1 ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_OUTPUT_PIPE_1 ].bmSndToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE_1 ].bmRcvToggle = 0;
-
-        epInfo[ XBOX_INPUT_PIPE_2 ].epAddr = 0x03; // XBOX 360 report endpoint - poll interval 1ms
-        epInfo[ XBOX_INPUT_PIPE_2 ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_INPUT_PIPE_2 ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_INPUT_PIPE_2 ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_INPUT_PIPE_2 ].bmSndToggle = 0;
-        epInfo[ XBOX_INPUT_PIPE_2 ].bmRcvToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE_2 ].epAddr = 0x03; // XBOX 360 output endpoint - poll interval 8ms
-        epInfo[ XBOX_OUTPUT_PIPE_2 ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_OUTPUT_PIPE_2 ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_OUTPUT_PIPE_2 ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_OUTPUT_PIPE_2 ].bmSndToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE_2 ].bmRcvToggle = 0;
-
-        epInfo[ XBOX_INPUT_PIPE_3 ].epAddr = 0x05; // XBOX 360 report endpoint - poll interval 1ms
-        epInfo[ XBOX_INPUT_PIPE_3 ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_INPUT_PIPE_3 ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_INPUT_PIPE_3 ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_INPUT_PIPE_3 ].bmSndToggle = 0;
-        epInfo[ XBOX_INPUT_PIPE_3 ].bmRcvToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE_3 ].epAddr = 0x05; // XBOX 360 output endpoint - poll interval 8ms
-        epInfo[ XBOX_OUTPUT_PIPE_3 ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_OUTPUT_PIPE_3 ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_OUTPUT_PIPE_3 ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_OUTPUT_PIPE_3 ].bmSndToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE_3 ].bmRcvToggle = 0;
-
-        epInfo[ XBOX_INPUT_PIPE_4 ].epAddr = 0x07; // XBOX 360 report endpoint - poll interval 1ms
-        epInfo[ XBOX_INPUT_PIPE_4 ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_INPUT_PIPE_4 ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_INPUT_PIPE_4 ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_INPUT_PIPE_4 ].bmSndToggle = 0;
-        epInfo[ XBOX_INPUT_PIPE_4 ].bmRcvToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE_4 ].epAddr = 0x07; // XBOX 360 output endpoint - poll interval 8ms
-        epInfo[ XBOX_OUTPUT_PIPE_4 ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_OUTPUT_PIPE_4 ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_OUTPUT_PIPE_4 ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_OUTPUT_PIPE_4 ].bmSndToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE_4 ].bmRcvToggle = 0;
-
-        rcode = pUsb->setEpInfoEntry(bAddress, 9, epInfo);
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        delay(200); //Give time for address change
-
-        rcode = pUsb->setConf(bAddress, epInfo[ XBOX_CONTROL_PIPE ].epAddr, 1);
-        if(rcode)
-                goto FailSetConfDescr;
-
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox Wireless Receiver Connected\r\n"), 0x80);
-#endif
-        XboxReceiverConnected = true;
-        bPollEnable = true;
-        checkStatusTimer = 0; // Reset timer
-        return 0; // Successful configuration
-
-        /* Diagnostic messages */
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-#endif
-
-Fail:
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox 360 Init Failed, error code: "), 0x80);
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-/* Performs a cleanup after failed Init() attempt */
-uint8_t XBOXRECV::Release() {
-        XboxReceiverConnected = false;
-        for(uint8_t i = 0; i < 4; i++)
-                Xbox360Connected[i] = 0x00;
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-        bAddress = 0;
-        bPollEnable = false;
-        return 0;
-}
-
-uint8_t XBOXRECV::Poll() {
-        if(!bPollEnable)
-                return 0;
-        if(!checkStatusTimer || ((millis() - checkStatusTimer) > 3000)) { // Run checkStatus every 3 seconds
-                checkStatusTimer = millis();
-                checkStatus();
-        }
-
-        uint8_t inputPipe;
-        uint16_t bufferSize;
-        for(uint8_t i = 0; i < 4; i++) {
-                if(i == 0)
-                        inputPipe = XBOX_INPUT_PIPE_1;
-                else if(i == 1)
-                        inputPipe = XBOX_INPUT_PIPE_2;
-                else if(i == 2)
-                        inputPipe = XBOX_INPUT_PIPE_3;
-                else
-                        inputPipe = XBOX_INPUT_PIPE_4;
-
-                bufferSize = EP_MAXPKTSIZE; // This is the maximum number of bytes we want to receive
-                pUsb->inTransfer(bAddress, epInfo[ inputPipe ].epAddr, &bufferSize, readBuf);
-                if(bufferSize > 0) { // The number of received bytes
-#ifdef EXTRADEBUG
-                        Notify(PSTR("Bytes Received: "), 0x80);
-                        D_PrintHex<uint16_t > (bufferSize, 0x80);
-                        Notify(PSTR("\r\n"), 0x80);
-#endif
-                        readReport(i);
-#ifdef PRINTREPORT
-                        printReport(i, bufferSize); // Uncomment "#define PRINTREPORT" to print the report send by the Xbox 360 Controller
-#endif
-                }
-        }
-        return 0;
-}
-
-void XBOXRECV::readReport(uint8_t controller) {
-        if(readBuf == NULL)
-                return;
-        // This report is send when a controller is connected and disconnected
-        if(readBuf[0] == 0x08 && readBuf[1] != Xbox360Connected[controller]) {
-                Xbox360Connected[controller] = readBuf[1];
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("Controller "), 0x80);
-                Notify(controller, 0x80);
-#endif
-                if(Xbox360Connected[controller]) {
-#ifdef DEBUG_USB_HOST
-                        const char* str = 0;
-                        switch(readBuf[1]) {
-                                case 0x80: str = PSTR(" as controller\r\n");
-                                        break;
-                                case 0x40: str = PSTR(" as headset\r\n");
-                                        break;
-                                case 0xC0: str = PSTR(" as controller+headset\r\n");
-                                        break;
-                        }
-                        Notify(PSTR(": connected"), 0x80);
-                        Notify(str, 0x80);
-#endif
-                        onInit(controller);
-                }
-#ifdef DEBUG_USB_HOST
-                else
-                        Notify(PSTR(": disconnected\r\n"), 0x80);
-#endif
-                return;
-        }
-        // Controller status report
-        if(readBuf[1] == 0x00 && readBuf[3] & 0x13 && readBuf[4] >= 0x22) {
-                controllerStatus[controller] = ((uint16_t)readBuf[3] << 8) | readBuf[4];
-                return;
-        }
-        if(readBuf[1] != 0x01) // Check if it's the correct report - the receiver also sends different status reports
-                return;
-
-        // A controller must be connected if it's sending data
-        if(!Xbox360Connected[controller])
-                Xbox360Connected[controller] |= 0x80;
-
-        ButtonState[controller] = (uint32_t)(readBuf[9] | ((uint16_t)readBuf[8] << 8) | ((uint32_t)readBuf[7] << 16) | ((uint32_t)readBuf[6] << 24));
-
-        hatValue[controller][LeftHatX] = (int16_t)(((uint16_t)readBuf[11] << 8) | readBuf[10]);
-        hatValue[controller][LeftHatY] = (int16_t)(((uint16_t)readBuf[13] << 8) | readBuf[12]);
-        hatValue[controller][RightHatX] = (int16_t)(((uint16_t)readBuf[15] << 8) | readBuf[14]);
-        hatValue[controller][RightHatY] = (int16_t)(((uint16_t)readBuf[17] << 8) | readBuf[16]);
-
-        //Notify(PSTR("\r\nButtonState: "), 0x80);
-        //PrintHex<uint32_t>(ButtonState[controller], 0x80);
-
-        if(ButtonState[controller] != OldButtonState[controller]) {
-                buttonStateChanged[controller] = true;
-                ButtonClickState[controller] = (ButtonState[controller] >> 16) & ((~OldButtonState[controller]) >> 16); // Update click state variable, but don't include the two trigger buttons L2 and R2
-                if(((uint8_t)OldButtonState[controller]) == 0 && ((uint8_t)ButtonState[controller]) != 0) // The L2 and R2 buttons are special as they are analog buttons
-                        R2Clicked[controller] = true;
-                if((uint8_t)(OldButtonState[controller] >> 8) == 0 && (uint8_t)(ButtonState[controller] >> 8) != 0)
-                        L2Clicked[controller] = true;
-                OldButtonState[controller] = ButtonState[controller];
-        }
-}
-
-void XBOXRECV::printReport(uint8_t controller, uint8_t nBytes) { //Uncomment "#define PRINTREPORT" to print the report send by the Xbox 360 Controller
-#ifdef PRINTREPORT
-        if(readBuf == NULL)
-                return;
-        Notify(PSTR("Controller "), 0x80);
-        Notify(controller, 0x80);
-        Notify(PSTR(": "), 0x80);
-        for(uint8_t i = 0; i < nBytes; i++) {
-                D_PrintHex<uint8_t > (readBuf[i], 0x80);
-                Notify(PSTR(" "), 0x80);
-        }
-        Notify(PSTR("\r\n"), 0x80);
-#endif
-}
-
-uint8_t XBOXRECV::getButtonPress(ButtonEnum b, uint8_t controller) {
-        if(b == L2) // These are analog buttons
-                return (uint8_t)(ButtonState[controller] >> 8);
-        else if(b == R2)
-                return (uint8_t)ButtonState[controller];
-        return (bool)(ButtonState[controller] & ((uint32_t)pgm_read_word(&XBOX_BUTTONS[(uint8_t)b]) << 16));
-}
-
-bool XBOXRECV::getButtonClick(ButtonEnum b, uint8_t controller) {
-        if(b == L2) {
-                if(L2Clicked[controller]) {
-                        L2Clicked[controller] = false;
-                        return true;
-                }
-                return false;
-        } else if(b == R2) {
-                if(R2Clicked[controller]) {
-                        R2Clicked[controller] = false;
-                        return true;
-                }
-                return false;
-        }
-        uint16_t button = pgm_read_word(&XBOX_BUTTONS[(uint8_t)b]);
-        bool click = (ButtonClickState[controller] & button);
-        ButtonClickState[controller] &= ~button; // clear "click" event
-        return click;
-}
-
-int16_t XBOXRECV::getAnalogHat(AnalogHatEnum a, uint8_t controller) {
-        return hatValue[controller][a];
-}
-
-bool XBOXRECV::buttonChanged(uint8_t controller) {
-        bool state = buttonStateChanged[controller];
-        buttonStateChanged[controller] = false;
-        return state;
-}
-
-/*
-ControllerStatus Breakdown
-ControllerStatus[controller] & 0x0001   // 0
-ControllerStatus[controller] & 0x0002   // normal batteries, no rechargeable battery pack
-ControllerStatus[controller] & 0x0004   // controller starting up / settling
-ControllerStatus[controller] & 0x0008   // headset adapter plugged in, but no headphones connected (mute?)
-ControllerStatus[controller] & 0x0010   // 0
-ControllerStatus[controller] & 0x0020   // 1
-ControllerStatus[controller] & 0x0040   // battery level (high bit)
-ControllerStatus[controller] & 0x0080   // battery level (low bit)
-ControllerStatus[controller] & 0x0100   // 1
-ControllerStatus[controller] & 0x0200   // 1
-ControllerStatus[controller] & 0x0400   // headset adapter plugged in
-ControllerStatus[controller] & 0x0800   // 0
-ControllerStatus[controller] & 0x1000   // 1
-ControllerStatus[controller] & 0x2000   // 0
-ControllerStatus[controller] & 0x4000   // 0
-ControllerStatus[controller] & 0x8000   // 0
- */
-uint8_t XBOXRECV::getBatteryLevel(uint8_t controller) {
-        return ((controllerStatus[controller] & 0x00C0) >> 6);
-}
-
-void XBOXRECV::XboxCommand(uint8_t controller, uint8_t* data, uint16_t nbytes) {
-#ifdef EXTRADEBUG
-        uint8_t rcode;
-#endif
-        uint8_t outputPipe;
-        switch(controller) {
-                case 0: outputPipe = XBOX_OUTPUT_PIPE_1;
-                        break;
-                case 1: outputPipe = XBOX_OUTPUT_PIPE_2;
-                        break;
-                case 2: outputPipe = XBOX_OUTPUT_PIPE_3;
-                        break;
-                case 3: outputPipe = XBOX_OUTPUT_PIPE_4;
-                        break;
-                default:
-                        return;
-        }
-#ifdef EXTRADEBUG
-        rcode =
-#endif
-                pUsb->outTransfer(bAddress, epInfo[ outputPipe ].epAddr, nbytes, data);
-#ifdef EXTRADEBUG
-        if(rcode)
-                Notify(PSTR("Error sending Xbox message\r\n"), 0x80);
-#endif
-}
-
-void XBOXRECV::disconnect(uint8_t controller) {
-        writeBuf[0] = 0x00;
-        writeBuf[1] = 0x00;
-        writeBuf[2] = 0x08;
-        writeBuf[3] = 0xC0;
-
-        XboxCommand(controller, writeBuf, 4);
-}
-
-void XBOXRECV::setLedRaw(uint8_t value, uint8_t controller) {
-        writeBuf[0] = 0x00;
-        writeBuf[1] = 0x00;
-        writeBuf[2] = 0x08;
-        writeBuf[3] = value | 0x40;
-
-        XboxCommand(controller, writeBuf, 4);
-}
-
-void XBOXRECV::setLedOn(LEDEnum led, uint8_t controller) {
-        if(led == OFF)
-                setLedRaw(0, controller);
-        else if(led != ALL) // All LEDs can't be on a the same time
-                setLedRaw(pgm_read_byte(&XBOX_LEDS[(uint8_t)led]) + 4, controller);
-}
-
-void XBOXRECV::setLedBlink(LEDEnum led, uint8_t controller) {
-        setLedRaw(pgm_read_byte(&XBOX_LEDS[(uint8_t)led]), controller);
-}
-
-void XBOXRECV::setLedMode(LEDModeEnum ledMode, uint8_t controller) { // This function is used to do some speciel LED stuff the controller supports
-        setLedRaw((uint8_t)ledMode, controller);
-}
-
-/* PC runs this at interval of approx 2 seconds
-Thanks to BusHound from Perisoft.net for the Windows USB Analysis output
-Found by timstamp.co.uk
- */
-void XBOXRECV::checkStatus() {
-        if(!bPollEnable)
-                return;
-        // Get controller info
-        writeBuf[0] = 0x08;
-        writeBuf[1] = 0x00;
-        writeBuf[2] = 0x0f;
-        writeBuf[3] = 0xc0;
-        for(uint8_t i = 0; i < 4; i++) {
-                XboxCommand(i, writeBuf, 4);
-        }
-        // Get battery status
-        writeBuf[0] = 0x00;
-        writeBuf[1] = 0x00;
-        writeBuf[2] = 0x00;
-        writeBuf[3] = 0x40;
-        for(uint8_t i = 0; i < 4; i++) {
-                if(Xbox360Connected[i])
-                        XboxCommand(i, writeBuf, 4);
-        }
-}
-
-void XBOXRECV::setRumbleOn(uint8_t lValue, uint8_t rValue, uint8_t controller) {
-        writeBuf[0] = 0x00;
-        writeBuf[1] = 0x01;
-        writeBuf[2] = 0x0f;
-        writeBuf[3] = 0xc0;
-        writeBuf[4] = 0x00;
-        writeBuf[5] = lValue; // big weight
-        writeBuf[6] = rValue; // small weight
-
-        XboxCommand(controller, writeBuf, 7);
-}
-
-void XBOXRECV::onInit(uint8_t controller) {
-        if(pFuncOnInit)
-                pFuncOnInit(); // Call the user function
-        else {
-                LEDEnum led;
-                if(controller == 0)
-                        led = LED1;
-                else if(controller == 1)
-                        led = LED2;
-                else if(controller == 2)
-                        led = LED3;
-                else
-                        led = LED4;
-                setLedOn(led, controller);
-        }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/XBOXRECV.h b/lib/usbhost/USB_Host_Shield_2.0/XBOXRECV.h
deleted file mode 100644
index 4f9214653c..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/XBOXRECV.h
+++ /dev/null
@@ -1,276 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
-
- getBatteryLevel and checkStatus functions made by timstamp.co.uk found using BusHound from Perisoft.net
- */
-
-#ifndef _xboxrecv_h_
-#define _xboxrecv_h_
-
-#include "Usb.h"
-#include "xboxEnums.h"
-
-/* Data Xbox 360 taken from descriptors */
-#define EP_MAXPKTSIZE       32 // max size for data via USB
-
-/* Names we give to the 9 Xbox360 pipes */
-#define XBOX_CONTROL_PIPE   0
-#define XBOX_INPUT_PIPE_1   1
-#define XBOX_OUTPUT_PIPE_1  2
-#define XBOX_INPUT_PIPE_2   3
-#define XBOX_OUTPUT_PIPE_2  4
-#define XBOX_INPUT_PIPE_3   5
-#define XBOX_OUTPUT_PIPE_3  6
-#define XBOX_INPUT_PIPE_4   7
-#define XBOX_OUTPUT_PIPE_4  8
-
-// PID and VID of the different devices
-#define XBOX_VID                                0x045E  // Microsoft Corporation
-#define MADCATZ_VID                             0x1BAD  // For unofficial Mad Catz receivers
-#define JOYTECH_VID                             0x162E  // For unofficial Joytech controllers
-
-#define XBOX_WIRELESS_RECEIVER_PID              0x0719  // Microsoft Wireless Gaming Receiver
-#define XBOX_WIRELESS_RECEIVER_THIRD_PARTY_PID  0x0291  // Third party Wireless Gaming Receiver
-
-#define XBOX_MAX_ENDPOINTS   9
-
-/**
- * This class implements support for a Xbox Wireless receiver.
- *
- * Up to four controllers can connect to one receiver, if more is needed one can use a second receiver via the USBHub class.
- */
-class XBOXRECV : public USBDeviceConfig {
-public:
-        /**
-         * Constructor for the XBOXRECV class.
-         * @param  pUsb   Pointer to USB class instance.
-         */
-        XBOXRECV(USB *pUsb);
-
-        /** @name USBDeviceConfig implementation */
-        /**
-         * Address assignment and basic initilization is done here.
-         * @param  parent   Hub number.
-         * @param  port     Port number on the hub.
-         * @param  lowspeed Speed of the device.
-         * @return          0 on success.
-         */
-        uint8_t ConfigureDevice(uint8_t parent, uint8_t port, bool lowspeed);
-        /**
-         * Initialize the Xbox wireless receiver.
-         * @param  parent   Hub number.
-         * @param  port     Port number on the hub.
-         * @param  lowspeed Speed of the device.
-         * @return          0 on success.
-         */
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        /**
-         * Release the USB device.
-         * @return 0 on success.
-         */
-        uint8_t Release();
-        /**
-         * Poll the USB Input endpoins and run the state machines.
-         * @return 0 on success.
-         */
-        uint8_t Poll();
-
-        /**
-         * Get the device address.
-         * @return The device address.
-         */
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        /**
-         * Used to check if the controller has been initialized.
-         * @return True if it's ready.
-         */
-        virtual bool isReady() {
-                return bPollEnable;
-        };
-
-        /**
-         * Used by the USB core to check what this driver support.
-         * @param  vid The device's VID.
-         * @param  pid The device's PID.
-         * @return     Returns true if the device's VID and PID matches this driver.
-         */
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return ((vid == XBOX_VID || vid == MADCATZ_VID || vid == JOYTECH_VID) && (pid == XBOX_WIRELESS_RECEIVER_PID || pid == XBOX_WIRELESS_RECEIVER_THIRD_PARTY_PID));
-        };
-        /**@}*/
-
-        /** @name Xbox Controller functions */
-        /**
-         * getButtonPress(uint8_t controller, ButtonEnum b) will return true as long as the button is held down.
-         *
-         * While getButtonClick(uint8_t controller, ButtonEnum b) will only return it once.
-         *
-         * So you instance if you need to increase a variable once you would use getButtonClick(uint8_t controller, ButtonEnum b),
-         * but if you need to drive a robot forward you would use getButtonPress(uint8_t controller, ButtonEnum b).
-         * @param  b          ::ButtonEnum to read.
-         * @param  controller The controller to read from. Default to 0.
-         * @return            getButtonClick(uint8_t controller, ButtonEnum b) will return a bool, while getButtonPress(uint8_t controller, ButtonEnum b) will return a byte if reading ::L2 or ::R2.
-         */
-        uint8_t getButtonPress(ButtonEnum b, uint8_t controller = 0);
-        bool getButtonClick(ButtonEnum b, uint8_t controller = 0);
-        /**@}*/
-
-        /** @name Xbox Controller functions */
-        /**
-         * Return the analog value from the joysticks on the controller.
-         * @param  a          Either ::LeftHatX, ::LeftHatY, ::RightHatX or ::RightHatY.
-         * @param  controller The controller to read from. Default to 0.
-         * @return            Returns a signed 16-bit integer.
-         */
-        int16_t getAnalogHat(AnalogHatEnum a, uint8_t controller = 0);
-
-        /**
-         * Used to disconnect any of the controllers.
-         * @param controller The controller to disconnect. Default to 0.
-         */
-        void disconnect(uint8_t controller = 0);
-
-        /**
-         * Turn rumble off and all the LEDs on the specific controller.
-         * @param  controller The controller to write to. Default to 0.
-         */
-        void setAllOff(uint8_t controller = 0) {
-                setRumbleOn(0, 0, controller);
-                setLedOff(controller);
-        };
-
-        /**
-         * Turn rumble off the specific controller.
-         * @param  controller The controller to write to. Default to 0.
-         */
-        void setRumbleOff(uint8_t controller = 0) {
-                setRumbleOn(0, 0, controller);
-        };
-        /**
-         * Turn rumble on.
-         * @param lValue     Left motor (big weight) inside the controller.
-         * @param rValue     Right motor (small weight) inside the controller.
-         * @param controller The controller to write to. Default to 0.
-         */
-        void setRumbleOn(uint8_t lValue, uint8_t rValue, uint8_t controller = 0);
-        /**
-         * Set LED value. Without using the ::LEDEnum or ::LEDModeEnum.
-         * @param value      See:
-         * setLedOff(uint8_t controller), setLedOn(uint8_t controller, LED l),
-         * setLedBlink(uint8_t controller, LED l), and setLedMode(uint8_t controller, LEDMode lm).
-         * @param controller The controller to write to. Default to 0.
-         */
-        void setLedRaw(uint8_t value, uint8_t controller = 0);
-
-        /**
-         * Turn all LEDs off the specific controller.
-         * @param controller The controller to write to. Default to 0.
-         */
-        void setLedOff(uint8_t controller = 0) {
-                setLedRaw(0, controller);
-        };
-        /**
-         * Turn on a LED by using ::LEDEnum.
-         * @param l          ::OFF, ::LED1, ::LED2, ::LED3 and ::LED4 is supported by the Xbox controller.
-         * @param controller The controller to write to. Default to 0.
-         */
-        void setLedOn(LEDEnum l, uint8_t controller = 0);
-        /**
-         * Turn on a LED by using ::LEDEnum.
-         * @param l          ::ALL, ::LED1, ::LED2, ::LED3 and ::LED4 is supported by the Xbox controller.
-         * @param controller The controller to write to. Default to 0.
-         */
-        void setLedBlink(LEDEnum l, uint8_t controller = 0);
-        /**
-         * Used to set special LED modes supported by the Xbox controller.
-         * @param lm         See ::LEDModeEnum.
-         * @param controller The controller to write to. Default to 0.
-         */
-        void setLedMode(LEDModeEnum lm, uint8_t controller = 0);
-        /**
-         * Used to get the battery level from the controller.
-         * @param  controller The controller to read from. Default to 0.
-         * @return            Returns the battery level as an integer in the range of 0-3.
-         */
-        uint8_t getBatteryLevel(uint8_t controller = 0);
-        /**
-         * Used to check if a button has changed.
-         * @param  controller The controller to read from. Default to 0.
-         * @return            True if a button has changed.
-         */
-        bool buttonChanged(uint8_t controller = 0);
-
-        /**
-         * Used to call your own function when the controller is successfully initialized.
-         * @param funcOnInit Function to call.
-         */
-        void attachOnInit(void (*funcOnInit)(void)) {
-                pFuncOnInit = funcOnInit;
-        };
-        /**@}*/
-
-        /** True if a wireless receiver is connected. */
-        bool XboxReceiverConnected;
-        /** Variable used to indicate if the XBOX 360 controller is successfully connected. */
-        uint8_t Xbox360Connected[4];
-
-protected:
-        /** Pointer to USB class instance. */
-        USB *pUsb;
-        /** Device address. */
-        uint8_t bAddress;
-        /** Endpoint info structure. */
-        EpInfo epInfo[XBOX_MAX_ENDPOINTS];
-
-private:
-        /**
-         * Called when the controller is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         * @param controller The initialized controller.
-         */
-        void onInit(uint8_t controller);
-        void (*pFuncOnInit)(void); // Pointer to function called in onInit()
-
-        bool bPollEnable;
-
-        /* Variables to store the buttons */
-        uint32_t ButtonState[4];
-        uint32_t OldButtonState[4];
-        uint16_t ButtonClickState[4];
-        int16_t hatValue[4][4];
-        uint16_t controllerStatus[4];
-        bool buttonStateChanged[4]; // True if a button has changed
-
-        bool L2Clicked[4]; // These buttons are analog, so we use we use these bools to check if they where clicked or not
-        bool R2Clicked[4];
-
-        uint32_t checkStatusTimer; // Timing for checkStatus() signals
-
-        uint8_t readBuf[EP_MAXPKTSIZE]; // General purpose buffer for input data
-        uint8_t writeBuf[7]; // General purpose buffer for output data
-
-        void readReport(uint8_t controller); // read incoming data
-        void printReport(uint8_t controller, uint8_t nBytes); // print incoming date - Uncomment for debugging
-
-        /* Private commands */
-        void XboxCommand(uint8_t controller, uint8_t* data, uint16_t nbytes);
-        void checkStatus();
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/XBOXUSB.cpp b/lib/usbhost/USB_Host_Shield_2.0/XBOXUSB.cpp
deleted file mode 100644
index ddece21b45..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/XBOXUSB.cpp
+++ /dev/null
@@ -1,361 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#include "XBOXUSB.h"
-// To enable serial debugging see "settings.h"
-//#define EXTRADEBUG // Uncomment to get even more debugging data
-//#define PRINTREPORT // Uncomment to print the report send by the Xbox 360 Controller
-
-XBOXUSB::XBOXUSB(USB *p) :
-pUsb(p), // pointer to USB class instance - mandatory
-bAddress(0), // device address - mandatory
-bPollEnable(false) { // don't start polling before dongle is connected
-        for(uint8_t i = 0; i < XBOX_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-        }
-
-        if(pUsb) // register in USB subsystem
-                pUsb->RegisterDeviceClass(this); //set devConfig[] entry
-}
-
-uint8_t XBOXUSB::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        uint8_t buf[sizeof (USB_DEVICE_DESCRIPTOR)];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint16_t PID;
-        uint16_t VID;
-
-        // get memory address of USB device address pool
-        AddressPool &addrPool = pUsb->GetAddressPool();
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nXBOXUSB Init"), 0x80);
-#endif
-        // check if address has already been assigned to an instance
-        if(bAddress) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress in use"), 0x80);
-#endif
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-        }
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nAddress not found"), 0x80);
-#endif
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        if(!p->epinfo) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nepinfo is null"), 0x80);
-#endif
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, sizeof (USB_DEVICE_DESCRIPTOR), (uint8_t*)buf); // Get device descriptor - addr, ep, nbytes, data
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        VID = udd->idVendor;
-        PID = udd->idProduct;
-
-        if(VID != XBOX_VID && VID != MADCATZ_VID && VID != JOYTECH_VID && VID != GAMESTOP_VID) // Check VID
-                goto FailUnknownDevice;
-        if(PID == XBOX_WIRELESS_PID) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nYou have plugged in a wireless Xbox 360 controller - it doesn't support USB communication"), 0x80);
-#endif
-                goto FailUnknownDevice;
-        } else if(PID == XBOX_WIRELESS_RECEIVER_PID || PID == XBOX_WIRELESS_RECEIVER_THIRD_PARTY_PID) {
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nThis library only supports Xbox 360 controllers via USB"), 0x80);
-#endif
-                goto FailUnknownDevice;
-        } else if(PID != XBOX_WIRED_PID && PID != MADCATZ_WIRED_PID && PID != GAMESTOP_WIRED_PID && PID != AFTERGLOW_WIRED_PID && PID != JOYTECH_WIRED_PID) // Check PID
-                goto FailUnknownDevice;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-#ifdef DEBUG_USB_HOST
-                Notify(PSTR("\r\nsetAddr: "), 0x80);
-                D_PrintHex<uint8_t > (rcode, 0x80);
-#endif
-                return rcode;
-        }
-#ifdef EXTRADEBUG
-        Notify(PSTR("\r\nAddr: "), 0x80);
-        D_PrintHex<uint8_t > (bAddress, 0x80);
-#endif
-        //delay(300); // Spec says you should wait at least 200ms
-
-        p->lowspeed = false;
-
-        //get pointer to assigned address record
-        p = addrPool.GetUsbDevicePtr(bAddress);
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        // Assign epInfo to epinfo pointer - only EP0 is known
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        /* The application will work in reduced host mode, so we can save program and data
-           memory space. After verifying the VID we will use known values for the
-           configuration values for device, interface, endpoints and HID for the XBOX360 Controllers */
-
-        /* Initialize data structures for endpoints of device */
-        epInfo[ XBOX_INPUT_PIPE ].epAddr = 0x01; // XBOX 360 report endpoint
-        epInfo[ XBOX_INPUT_PIPE ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_INPUT_PIPE ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_INPUT_PIPE ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_INPUT_PIPE ].bmSndToggle = 0;
-        epInfo[ XBOX_INPUT_PIPE ].bmRcvToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE ].epAddr = 0x02; // XBOX 360 output endpoint
-        epInfo[ XBOX_OUTPUT_PIPE ].epAttribs = USB_TRANSFER_TYPE_INTERRUPT;
-        epInfo[ XBOX_OUTPUT_PIPE ].bmNakPower = USB_NAK_NOWAIT; // Only poll once for interrupt endpoints
-        epInfo[ XBOX_OUTPUT_PIPE ].maxPktSize = EP_MAXPKTSIZE;
-        epInfo[ XBOX_OUTPUT_PIPE ].bmSndToggle = 0;
-        epInfo[ XBOX_OUTPUT_PIPE ].bmRcvToggle = 0;
-
-        rcode = pUsb->setEpInfoEntry(bAddress, 3, epInfo);
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        delay(200); // Give time for address change
-
-        rcode = pUsb->setConf(bAddress, epInfo[ XBOX_CONTROL_PIPE ].epAddr, 1);
-        if(rcode)
-                goto FailSetConfDescr;
-
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox 360 Controller Connected\r\n"), 0x80);
-#endif
-        onInit();
-        Xbox360Connected = true;
-        bPollEnable = true;
-        return 0; // Successful configuration
-
-        /* Diagnostic messages */
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-#endif
-        goto Fail;
-
-FailUnknownDevice:
-#ifdef DEBUG_USB_HOST
-        NotifyFailUnknownDevice(VID, PID);
-#endif
-        rcode = USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-Fail:
-#ifdef DEBUG_USB_HOST
-        Notify(PSTR("\r\nXbox 360 Init Failed, error code: "), 0x80);
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-/* Performs a cleanup after failed Init() attempt */
-uint8_t XBOXUSB::Release() {
-        Xbox360Connected = false;
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-        bAddress = 0;
-        bPollEnable = false;
-        return 0;
-}
-
-uint8_t XBOXUSB::Poll() {
-        if(!bPollEnable)
-                return 0;
-        uint16_t BUFFER_SIZE = EP_MAXPKTSIZE;
-        pUsb->inTransfer(bAddress, epInfo[ XBOX_INPUT_PIPE ].epAddr, &BUFFER_SIZE, readBuf); // input on endpoint 1
-        readReport();
-#ifdef PRINTREPORT
-        printReport(); // Uncomment "#define PRINTREPORT" to print the report send by the Xbox 360 Controller
-#endif
-        return 0;
-}
-
-void XBOXUSB::readReport() {
-        if(readBuf == NULL)
-                return;
-        if(readBuf[0] != 0x00 || readBuf[1] != 0x14) { // Check if it's the correct report - the controller also sends different status reports
-                return;
-        }
-
-        ButtonState = (uint32_t)(readBuf[5] | ((uint16_t)readBuf[4] << 8) | ((uint32_t)readBuf[3] << 16) | ((uint32_t)readBuf[2] << 24));
-
-        hatValue[LeftHatX] = (int16_t)(((uint16_t)readBuf[7] << 8) | readBuf[6]);
-        hatValue[LeftHatY] = (int16_t)(((uint16_t)readBuf[9] << 8) | readBuf[8]);
-        hatValue[RightHatX] = (int16_t)(((uint16_t)readBuf[11] << 8) | readBuf[10]);
-        hatValue[RightHatY] = (int16_t)(((uint16_t)readBuf[13] << 8) | readBuf[12]);
-
-        //Notify(PSTR("\r\nButtonState"), 0x80);
-        //PrintHex<uint32_t>(ButtonState, 0x80);
-
-        if(ButtonState != OldButtonState) {
-                ButtonClickState = (ButtonState >> 16) & ((~OldButtonState) >> 16); // Update click state variable, but don't include the two trigger buttons L2 and R2
-                if(((uint8_t)OldButtonState) == 0 && ((uint8_t)ButtonState) != 0) // The L2 and R2 buttons are special as they are analog buttons
-                        R2Clicked = true;
-                if((uint8_t)(OldButtonState >> 8) == 0 && (uint8_t)(ButtonState >> 8) != 0)
-                        L2Clicked = true;
-                OldButtonState = ButtonState;
-        }
-}
-
-void XBOXUSB::printReport() { //Uncomment "#define PRINTREPORT" to print the report send by the Xbox 360 Controller
-#ifdef PRINTREPORT
-        if(readBuf == NULL)
-                return;
-        for(uint8_t i = 0; i < XBOX_REPORT_BUFFER_SIZE; i++) {
-                D_PrintHex<uint8_t > (readBuf[i], 0x80);
-                Notify(PSTR(" "), 0x80);
-        }
-        Notify(PSTR("\r\n"), 0x80);
-#endif
-}
-
-uint8_t XBOXUSB::getButtonPress(ButtonEnum b) {
-        if(b == L2) // These are analog buttons
-                return (uint8_t)(ButtonState >> 8);
-        else if(b == R2)
-                return (uint8_t)ButtonState;
-        return (bool)(ButtonState & ((uint32_t)pgm_read_word(&XBOX_BUTTONS[(uint8_t)b]) << 16));
-}
-
-bool XBOXUSB::getButtonClick(ButtonEnum b) {
-        if(b == L2) {
-                if(L2Clicked) {
-                        L2Clicked = false;
-                        return true;
-                }
-                return false;
-        } else if(b == R2) {
-                if(R2Clicked) {
-                        R2Clicked = false;
-                        return true;
-                }
-                return false;
-        }
-        uint16_t button = pgm_read_word(&XBOX_BUTTONS[(uint8_t)b]);
-        bool click = (ButtonClickState & button);
-        ButtonClickState &= ~button; // clear "click" event
-        return click;
-}
-
-int16_t XBOXUSB::getAnalogHat(AnalogHatEnum a) {
-        return hatValue[a];
-}
-
-/* Xbox Controller commands */
-void XBOXUSB::XboxCommand(uint8_t* data, uint16_t nbytes) {
-        //bmRequest = Host to device (0x00) | Class (0x20) | Interface (0x01) = 0x21, bRequest = Set Report (0x09), Report ID (0x00), Report Type (Output 0x02), interface (0x00), datalength, datalength, data)
-        pUsb->ctrlReq(bAddress, epInfo[XBOX_CONTROL_PIPE].epAddr, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, 0x00, 0x02, 0x00, nbytes, nbytes, data, NULL);
-}
-
-void XBOXUSB::setLedRaw(uint8_t value) {
-        writeBuf[0] = 0x01;
-        writeBuf[1] = 0x03;
-        writeBuf[2] = value;
-
-        XboxCommand(writeBuf, 3);
-}
-
-void XBOXUSB::setLedOn(LEDEnum led) {
-        if(led == OFF)
-                setLedRaw(0);
-        else if(led != ALL) // All LEDs can't be on a the same time
-                setLedRaw(pgm_read_byte(&XBOX_LEDS[(uint8_t)led]) + 4);
-}
-
-void XBOXUSB::setLedBlink(LEDEnum led) {
-        setLedRaw(pgm_read_byte(&XBOX_LEDS[(uint8_t)led]));
-}
-
-void XBOXUSB::setLedMode(LEDModeEnum ledMode) { // This function is used to do some special LED stuff the controller supports
-        setLedRaw((uint8_t)ledMode);
-}
-
-void XBOXUSB::setRumbleOn(uint8_t lValue, uint8_t rValue) {
-        writeBuf[0] = 0x00;
-        writeBuf[1] = 0x08;
-        writeBuf[2] = 0x00;
-        writeBuf[3] = lValue; // big weight
-        writeBuf[4] = rValue; // small weight
-        writeBuf[5] = 0x00;
-        writeBuf[6] = 0x00;
-        writeBuf[7] = 0x00;
-
-        XboxCommand(writeBuf, 8);
-}
-
-void XBOXUSB::onInit() {
-        if(pFuncOnInit)
-                pFuncOnInit(); // Call the user function
-        else
-                setLedOn(LED1);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/XBOXUSB.h b/lib/usbhost/USB_Host_Shield_2.0/XBOXUSB.h
deleted file mode 100644
index 1ab37851a7..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/XBOXUSB.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _xboxusb_h_
-#define _xboxusb_h_
-
-#include "Usb.h"
-#include "hid.h"
-#include "xboxEnums.h"
-
-/* Data Xbox 360 taken from descriptors */
-#define EP_MAXPKTSIZE       32 // max size for data via USB
-
-/* Names we give to the 3 Xbox360 pipes */
-#define XBOX_CONTROL_PIPE    0
-#define XBOX_INPUT_PIPE      1
-#define XBOX_OUTPUT_PIPE     2
-
-// PID and VID of the different devices
-#define XBOX_VID                                0x045E // Microsoft Corporation
-#define MADCATZ_VID                             0x1BAD // For unofficial Mad Catz controllers
-#define JOYTECH_VID                             0x162E // For unofficial Joytech controllers
-#define GAMESTOP_VID                            0x0E6F // Gamestop controller
-
-#define XBOX_WIRED_PID                          0x028E // Microsoft 360 Wired controller
-#define XBOX_WIRELESS_PID                       0x028F // Wireless controller only support charging
-#define XBOX_WIRELESS_RECEIVER_PID              0x0719 // Microsoft Wireless Gaming Receiver
-#define XBOX_WIRELESS_RECEIVER_THIRD_PARTY_PID  0x0291 // Third party Wireless Gaming Receiver
-#define MADCATZ_WIRED_PID                       0xF016 // Mad Catz wired controller
-#define JOYTECH_WIRED_PID                       0xBEEF // For Joytech wired controller
-#define GAMESTOP_WIRED_PID                      0x0401 // Gamestop wired controller
-#define AFTERGLOW_WIRED_PID                     0x0213 // Afterglow wired controller - it uses the same VID as a Gamestop controller
-
-#define XBOX_REPORT_BUFFER_SIZE 14 // Size of the input report buffer
-
-#define XBOX_MAX_ENDPOINTS   3
-
-/** This class implements support for a Xbox wired controller via USB. */
-class XBOXUSB : public USBDeviceConfig {
-public:
-        /**
-         * Constructor for the XBOXUSB class.
-         * @param  pUsb   Pointer to USB class instance.
-         */
-        XBOXUSB(USB *pUsb);
-
-        /** @name USBDeviceConfig implementation */
-        /**
-         * Initialize the Xbox Controller.
-         * @param  parent   Hub number.
-         * @param  port     Port number on the hub.
-         * @param  lowspeed Speed of the device.
-         * @return          0 on success.
-         */
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        /**
-         * Release the USB device.
-         * @return 0 on success.
-         */
-        uint8_t Release();
-        /**
-         * Poll the USB Input endpoins and run the state machines.
-         * @return 0 on success.
-         */
-        uint8_t Poll();
-
-        /**
-         * Get the device address.
-         * @return The device address.
-         */
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        /**
-         * Used to check if the controller has been initialized.
-         * @return True if it's ready.
-         */
-        virtual bool isReady() {
-                return bPollEnable;
-        };
-
-        /**
-         * Used by the USB core to check what this driver support.
-         * @param  vid The device's VID.
-         * @param  pid The device's PID.
-         * @return     Returns true if the device's VID and PID matches this driver.
-         */
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return ((vid == XBOX_VID || vid == MADCATZ_VID || vid == JOYTECH_VID || vid == GAMESTOP_VID) && (pid == XBOX_WIRED_PID || pid == MADCATZ_WIRED_PID || pid == GAMESTOP_WIRED_PID || pid == AFTERGLOW_WIRED_PID || pid == JOYTECH_WIRED_PID));
-        };
-        /**@}*/
-
-        /** @name Xbox Controller functions */
-        /**
-         * getButtonPress(ButtonEnum b) will return true as long as the button is held down.
-         *
-         * While getButtonClick(ButtonEnum b) will only return it once.
-         *
-         * So you instance if you need to increase a variable once you would use getButtonClick(ButtonEnum b),
-         * but if you need to drive a robot forward you would use getButtonPress(ButtonEnum b).
-         * @param  b          ::ButtonEnum to read.
-         * @return            getButtonClick(ButtonEnum b) will return a bool, while getButtonPress(ButtonEnum b) will return a byte if reading ::L2 or ::R2.
-         */
-        uint8_t getButtonPress(ButtonEnum b);
-        bool getButtonClick(ButtonEnum b);
-        /**@}*/
-
-        /** @name Xbox Controller functions */
-        /**
-         * Return the analog value from the joysticks on the controller.
-         * @param  a          Either ::LeftHatX, ::LeftHatY, ::RightHatX or ::RightHatY.
-         * @return            Returns a signed 16-bit integer.
-         */
-        int16_t getAnalogHat(AnalogHatEnum a);
-
-        /** Turn rumble off and all the LEDs on the controller. */
-        void setAllOff() {
-                setRumbleOn(0, 0);
-                setLedRaw(0);
-        };
-
-        /** Turn rumble off the controller. */
-        void setRumbleOff() {
-                setRumbleOn(0, 0);
-        };
-        /**
-         * Turn rumble on.
-         * @param lValue     Left motor (big weight) inside the controller.
-         * @param rValue     Right motor (small weight) inside the controller.
-         */
-        void setRumbleOn(uint8_t lValue, uint8_t rValue);
-        /**
-         * Set LED value. Without using the ::LEDEnum or ::LEDModeEnum.
-         * @param value      See:
-         * setLedOff(), setLedOn(LEDEnum l),
-         * setLedBlink(LEDEnum l), and setLedMode(LEDModeEnum lm).
-         */
-        void setLedRaw(uint8_t value);
-
-        /** Turn all LEDs off the controller. */
-        void setLedOff() {
-                setLedRaw(0);
-        };
-        /**
-         * Turn on a LED by using ::LEDEnum.
-         * @param l          ::OFF, ::LED1, ::LED2, ::LED3 and ::LED4 is supported by the Xbox controller.
-         */
-        void setLedOn(LEDEnum l);
-        /**
-         * Turn on a LED by using ::LEDEnum.
-         * @param l          ::ALL, ::LED1, ::LED2, ::LED3 and ::LED4 is supported by the Xbox controller.
-         */
-        void setLedBlink(LEDEnum l);
-        /**
-         * Used to set special LED modes supported by the Xbox controller.
-         * @param lm         See ::LEDModeEnum.
-         */
-        void setLedMode(LEDModeEnum lm);
-
-        /**
-         * Used to call your own function when the controller is successfully initialized.
-         * @param funcOnInit Function to call.
-         */
-        void attachOnInit(void (*funcOnInit)(void)) {
-                pFuncOnInit = funcOnInit;
-        };
-        /**@}*/
-
-        /** True if a Xbox 360 controller is connected. */
-        bool Xbox360Connected;
-
-protected:
-        /** Pointer to USB class instance. */
-        USB *pUsb;
-        /** Device address. */
-        uint8_t bAddress;
-        /** Endpoint info structure. */
-        EpInfo epInfo[XBOX_MAX_ENDPOINTS];
-
-private:
-        /**
-         * Called when the controller is successfully initialized.
-         * Use attachOnInit(void (*funcOnInit)(void)) to call your own function.
-         * This is useful for instance if you want to set the LEDs in a specific way.
-         */
-        void onInit();
-        void (*pFuncOnInit)(void); // Pointer to function called in onInit()
-
-        bool bPollEnable;
-
-        /* Variables to store the buttons */
-        uint32_t ButtonState;
-        uint32_t OldButtonState;
-        uint16_t ButtonClickState;
-        int16_t hatValue[4];
-        uint16_t controllerStatus;
-
-        bool L2Clicked; // These buttons are analog, so we use we use these bools to check if they where clicked or not
-        bool R2Clicked;
-
-        uint8_t readBuf[EP_MAXPKTSIZE]; // General purpose buffer for input data
-        uint8_t writeBuf[8]; // General purpose buffer for output data
-
-        void readReport(); // read incoming data
-        void printReport(); // print incoming date - Uncomment for debugging
-
-        /* Private commands */
-        void XboxCommand(uint8_t* data, uint16_t nbytes);
-};
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/address.h b/lib/usbhost/USB_Host_Shield_2.0/address.h
deleted file mode 100644
index c3e1b3141f..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/address.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#if !defined(_usb_h_) || defined(__ADDRESS_H__)
-#error "Never include address.h directly; include Usb.h instead"
-#else
-#define __ADDRESS_H__
-
-
-
-/* NAK powers. To save space in endpoint data structure, amount of retries before giving up and returning 0x4 is stored in */
-/* bmNakPower as a power of 2. The actual nak_limit is then calculated as nak_limit = ( 2^bmNakPower - 1) */
-#define USB_NAK_MAX_POWER               15              //NAK binary order maximum value
-#define USB_NAK_DEFAULT                 14              //default 32K-1 NAKs before giving up
-#define USB_NAK_NOWAIT                  1               //Single NAK stops transfer
-#define USB_NAK_NONAK                   0               //Do not count NAKs, stop retrying after USB Timeout
-
-struct EpInfo {
-        uint8_t epAddr; // Endpoint address
-        uint8_t maxPktSize; // Maximum packet size
-
-        union {
-                uint8_t epAttribs;
-
-                struct {
-                        uint8_t bmSndToggle : 1; // Send toggle, when zero bmSNDTOG0, bmSNDTOG1 otherwise
-                        uint8_t bmRcvToggle : 1; // Send toggle, when zero bmRCVTOG0, bmRCVTOG1 otherwise
-                        uint8_t bmNakPower : 6; // Binary order for NAK_LIMIT value
-                } __attribute__((packed));
-        };
-} __attribute__((packed));
-
-//        7   6   5   4   3   2   1   0
-//  ---------------------------------
-//  |   | H | P | P | P | A | A | A |
-//  ---------------------------------
-//
-// H - if 1 the address is a hub address
-// P - parent hub address
-// A - device address / port number in case of hub
-//
-
-struct UsbDeviceAddress {
-
-        union {
-
-                struct {
-                        uint8_t bmAddress : 3; // device address/port number
-                        uint8_t bmParent : 3; // parent hub address
-                        uint8_t bmHub : 1; // hub flag
-                        uint8_t bmReserved : 1; // reserved, must be zero
-                } __attribute__((packed));
-                uint8_t devAddress;
-        };
-} __attribute__((packed));
-
-#define bmUSB_DEV_ADDR_ADDRESS          0x07
-#define bmUSB_DEV_ADDR_PARENT           0x38
-#define bmUSB_DEV_ADDR_HUB              0x40
-
-struct UsbDevice {
-        EpInfo *epinfo; // endpoint info pointer
-        UsbDeviceAddress address;
-        uint8_t epcount; // number of endpoints
-        bool lowspeed; // indicates if a device is the low speed one
-        //      uint8_t devclass; // device class
-} __attribute__((packed));
-
-class AddressPool {
-public:
-        virtual UsbDevice* GetUsbDevicePtr(uint8_t addr) = 0;
-        virtual uint8_t AllocAddress(uint8_t parent, bool is_hub = false, uint8_t port = 0) = 0;
-        virtual void FreeAddress(uint8_t addr) = 0;
-};
-
-typedef void (*UsbDeviceHandleFunc)(UsbDevice *pdev);
-
-#define ADDR_ERROR_INVALID_INDEX                0xFF
-#define ADDR_ERROR_INVALID_ADDRESS              0xFF
-
-template <const uint8_t MAX_DEVICES_ALLOWED>
-class AddressPoolImpl : public AddressPool {
-        EpInfo dev0ep; //Endpoint data structure used during enumeration for uninitialized device
-
-        uint8_t hubCounter; // hub counter is kept
-        // in order to avoid hub address duplication
-
-        UsbDevice thePool[MAX_DEVICES_ALLOWED];
-
-        // Initializes address pool entry
-
-        void InitEntry(uint8_t index) {
-                thePool[index].address.devAddress = 0;
-                thePool[index].epcount = 1;
-                thePool[index].lowspeed = 0;
-                thePool[index].epinfo = &dev0ep;
-        };
-
-        // Returns thePool index for a given address
-
-        uint8_t FindAddressIndex(uint8_t address = 0) {
-                for(uint8_t i = 1; i < MAX_DEVICES_ALLOWED; i++) {
-                        if(thePool[i].address.devAddress == address)
-                                return i;
-                }
-                return 0;
-        };
-
-        // Returns thePool child index for a given parent
-
-        uint8_t FindChildIndex(UsbDeviceAddress addr, uint8_t start = 1) {
-                for(uint8_t i = (start < 1 || start >= MAX_DEVICES_ALLOWED) ? 1 : start; i < MAX_DEVICES_ALLOWED; i++) {
-                        if(thePool[i].address.bmParent == addr.bmAddress)
-                                return i;
-                }
-                return 0;
-        };
-
-        // Frees address entry specified by index parameter
-
-        void FreeAddressByIndex(uint8_t index) {
-                // Zero field is reserved and should not be affected
-                if(index == 0)
-                        return;
-
-                UsbDeviceAddress uda = thePool[index].address;
-                // If a hub was switched off all port addresses should be freed
-                if(uda.bmHub == 1) {
-                        for(uint8_t i = 1; (i = FindChildIndex(uda, i));)
-                                FreeAddressByIndex(i);
-
-                        // If the hub had the last allocated address, hubCounter should be decremented
-                        if(hubCounter == uda.bmAddress)
-                                hubCounter--;
-                }
-                InitEntry(index);
-        }
-
-        // Initializes the whole address pool at once
-
-        void InitAllAddresses() {
-                for(uint8_t i = 1; i < MAX_DEVICES_ALLOWED; i++)
-                        InitEntry(i);
-
-                hubCounter = 0;
-        };
-
-public:
-
-        AddressPoolImpl() : hubCounter(0) {
-                // Zero address is reserved
-                InitEntry(0);
-
-                thePool[0].address.devAddress = 0;
-                thePool[0].epinfo = &dev0ep;
-                dev0ep.epAddr = 0;
-                dev0ep.maxPktSize = 8;
-                dev0ep.epAttribs = 0; //set DATA0/1 toggles to 0
-                dev0ep.bmNakPower = USB_NAK_MAX_POWER;
-
-                InitAllAddresses();
-        };
-
-        // Returns a pointer to a specified address entry
-
-        virtual UsbDevice* GetUsbDevicePtr(uint8_t addr) {
-                if(!addr)
-                        return thePool;
-
-                uint8_t index = FindAddressIndex(addr);
-
-                return (!index) ? NULL : thePool + index;
-        };
-
-        // Performs an operation specified by pfunc for each addressed device
-
-        void ForEachUsbDevice(UsbDeviceHandleFunc pfunc) {
-                if(!pfunc)
-                        return;
-
-                for(uint8_t i = 1; i < MAX_DEVICES_ALLOWED; i++)
-                        if(thePool[i].address.devAddress)
-                                pfunc(thePool + i);
-        };
-
-        // Allocates new address
-
-        virtual uint8_t AllocAddress(uint8_t parent, bool is_hub = false, uint8_t port = 0) {
-                /* if (parent != 0 && port == 0)
-                        USB_HOST_SERIAL.println("PRT:0"); */
-                UsbDeviceAddress _parent;
-                _parent.devAddress = parent;
-                if(_parent.bmReserved || port > 7)
-                        //if(parent > 127 || port > 7)
-                        return 0;
-
-                if(is_hub && hubCounter == 7)
-                        return 0;
-
-                // finds first empty address entry starting from one
-                uint8_t index = FindAddressIndex(0);
-
-                if(!index) // if empty entry is not found
-                        return 0;
-
-                if(_parent.devAddress == 0) {
-                        if(is_hub) {
-                                thePool[index].address.devAddress = 0x41;
-                                hubCounter++;
-                        } else
-                                thePool[index].address.devAddress = 1;
-
-                        return thePool[index].address.devAddress;
-                }
-
-                UsbDeviceAddress addr;
-                addr.devAddress = 0; // Ensure all bits are zero
-                addr.bmParent = _parent.bmAddress;
-                if(is_hub) {
-                        addr.bmHub = 1;
-                        addr.bmAddress = ++hubCounter;
-                } else {
-                        addr.bmHub = 0;
-                        addr.bmAddress = port;
-                }
-                thePool[index].address = addr;
-                /*
-                                USB_HOST_SERIAL.print("Addr:");
-                                USB_HOST_SERIAL.print(addr.bmHub, HEX);
-                                USB_HOST_SERIAL.print(".");
-                                USB_HOST_SERIAL.print(addr.bmParent, HEX);
-                                USB_HOST_SERIAL.print(".");
-                                USB_HOST_SERIAL.println(addr.bmAddress, HEX);
-                 */
-                return thePool[index].address.devAddress;
-        };
-
-        // Empties pool entry
-
-        virtual void FreeAddress(uint8_t addr) {
-                // if the root hub is disconnected all the addresses should be initialized
-                if(addr == 0x41) {
-                        InitAllAddresses();
-                        return;
-                }
-                uint8_t index = FindAddressIndex(addr);
-                FreeAddressByIndex(index);
-        };
-
-        // Returns number of hubs attached
-        // It can be rather helpfull to find out if there are hubs attached than getting the exact number of hubs.
-        //uint8_t GetNumHubs()
-        //{
-        //        return hubCounter;
-        //};
-        //uint8_t GetNumDevices()
-        //{
-        //        uint8_t counter = 0;
-
-        //        for (uint8_t i=1; i<MAX_DEVICES_ALLOWED; i++)
-        //                if (thePool[i].address != 0);
-        //                        counter ++;
-
-        //        return counter;
-        //};
-};
-
-#endif // __ADDRESS_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/adk.cpp b/lib/usbhost/USB_Host_Shield_2.0/adk.cpp
deleted file mode 100644
index 9e4e0c8d86..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/adk.cpp
+++ /dev/null
@@ -1,371 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-/* Google ADK interface */
-
-#include "adk.h"
-
-const uint8_t ADK::epDataInIndex = 1;
-const uint8_t ADK::epDataOutIndex = 2;
-
-ADK::ADK(USB *p, const char* manufacturer,
-        const char* model,
-        const char* description,
-        const char* version,
-        const char* uri,
-        const char* serial) :
-
-/* ADK ID Strings */
-manufacturer(manufacturer),
-model(model),
-description(description),
-version(version),
-uri(uri),
-serial(serial),
-pUsb(p), //pointer to USB class instance - mandatory
-bAddress(0), //device address - mandatory
-bConfNum(0), //configuration number
-bNumEP(1), //if config descriptor needs to be parsed
-ready(false) {
-        // initialize endpoint data structures
-        for(uint8_t i = 0; i < ADK_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-        }//for(uint8_t i=0; i<ADK_MAX_ENDPOINTS; i++...
-
-        // register in USB subsystem
-        if(pUsb) {
-                pUsb->RegisterDeviceClass(this); //set devConfig[] entry
-        }
-}
-
-uint8_t ADK::ConfigureDevice(uint8_t parent, uint8_t port, bool lowspeed) {
-        return Init(parent, port, lowspeed); // Just call Init. Yes, really!
-}
-
-/* Connection initialization of an Android phone */
-uint8_t ADK::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        uint8_t buf[sizeof (USB_DEVICE_DESCRIPTOR)];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        uint8_t num_of_conf; // number of configurations
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-
-        // get memory address of USB device address pool
-        AddressPool &addrPool = pUsb->GetAddressPool();
-
-        USBTRACE("\r\nADK Init");
-
-        // check if address has already been assigned to an instance
-        if(bAddress) {
-                USBTRACE("\r\nAddress in use");
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-        }
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p) {
-                USBTRACE("\r\nAddress not found");
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        if(!p->epinfo) {
-                USBTRACE("epinfo is null\r\n");
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, sizeof (USB_DEVICE_DESCRIPTOR), (uint8_t*)buf);
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode) {
-                goto FailGetDevDescr;
-        }
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        // Extract Max Packet Size from device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                //USBTRACE2("setAddr:",rcode);
-                return rcode;
-        }//if (rcode...
-
-        //USBTRACE2("\r\nAddr:", bAddress);
-        // Spec says you should wait at least 200ms.
-        //delay(300);
-
-        p->lowspeed = false;
-
-        //get pointer to assigned address record
-        p = addrPool.GetUsbDevicePtr(bAddress);
-        if(!p) {
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        p->lowspeed = lowspeed;
-
-        // Assign epInfo to epinfo pointer - only EP0 is known
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-        if(rcode) {
-                goto FailSetDevTblEntry;
-        }
-
-        //check if ADK device is already in accessory mode; if yes, configure and exit
-        if(udd->idVendor == ADK_VID &&
-                (udd->idProduct == ADK_PID || udd->idProduct == ADB_PID)) {
-                USBTRACE("\r\nAcc.mode device detected");
-                /* go through configurations, find first bulk-IN, bulk-OUT EP, fill epInfo and quit */
-                num_of_conf = udd->bNumConfigurations;
-
-                //USBTRACE2("\r\nNC:",num_of_conf);
-                for(uint8_t i = 0; i < num_of_conf; i++) {
-                        ConfigDescParser < 0, 0, 0, 0 > confDescrParser(this);
-                        delay(1);
-                        rcode = pUsb->getConfDescr(bAddress, 0, i, &confDescrParser);
-#if defined(XOOM)
-                        //added by Jaylen Scott Vanorden
-                        if(rcode) {
-                                USBTRACE2("\r\nGot 1st bad code for config: ", rcode);
-                                // Try once more
-                                rcode = pUsb->getConfDescr(bAddress, 0, i, &confDescrParser);
-                        }
-#endif
-                        if(rcode) {
-                                goto FailGetConfDescr;
-                        }
-                        if(bNumEP > 2) {
-                                break;
-                        }
-                } // for (uint8_t i=0; i<num_of_conf; i++...
-
-                if(bNumEP == 3) {
-                        // Assign epInfo to epinfo pointer - this time all 3 endpoins
-                        rcode = pUsb->setEpInfoEntry(bAddress, 3, epInfo);
-                        if(rcode) {
-                                goto FailSetDevTblEntry;
-                        }
-                }
-
-                // Set Configuration Value
-                rcode = pUsb->setConf(bAddress, 0, bConfNum);
-                if(rcode) {
-                        goto FailSetConfDescr;
-                }
-                /* print endpoint structure */
-                /*
-                USBTRACE("\r\nEndpoint Structure:");
-                USBTRACE("\r\nEP0:");
-                USBTRACE2("\r\nAddr: ", epInfo[0].epAddr);
-                USBTRACE2("\r\nMax.pkt.size: ", epInfo[0].maxPktSize);
-                USBTRACE2("\r\nAttr: ", epInfo[0].epAttribs);
-                USBTRACE("\r\nEpout:");
-                USBTRACE2("\r\nAddr: ", epInfo[epDataOutIndex].epAddr);
-                USBTRACE2("\r\nMax.pkt.size: ", epInfo[epDataOutIndex].maxPktSize);
-                USBTRACE2("\r\nAttr: ", epInfo[epDataOutIndex].epAttribs);
-                USBTRACE("\r\nEpin:");
-                USBTRACE2("\r\nAddr: ", epInfo[epDataInIndex].epAddr);
-                USBTRACE2("\r\nMax.pkt.size: ", epInfo[epDataInIndex].maxPktSize);
-                USBTRACE2("\r\nAttr: ", epInfo[epDataInIndex].epAttribs);
-                 */
-
-                USBTRACE("\r\nConfiguration successful");
-                ready = true;
-                return 0; //successful configuration
-        }//if( buf->idVendor == ADK_VID...
-
-        //probe device - get accessory protocol revision
-        {
-                uint16_t adkproto = -1;
-                delay(1);
-                rcode = getProto((uint8_t*) & adkproto);
-#if defined(XOOM)
-                //added by Jaylen Scott Vanorden
-                if(rcode) {
-                        USBTRACE2("\r\nGot 1st bad code for proto: ", rcode);
-                        // Try once more
-                        rcode = getProto((uint8_t*) & adkproto);
-                }
-#endif
-                if(rcode) {
-                        goto FailGetProto; //init fails
-                }
-                USBTRACE2("\r\nADK protocol rev. ", adkproto);
-        }
-
-        delay(100);
-
-        //sending ID strings
-        sendStr(ACCESSORY_STRING_MANUFACTURER, manufacturer);
-        delay(10);
-        sendStr(ACCESSORY_STRING_MODEL, model);
-        delay(10);
-        sendStr(ACCESSORY_STRING_DESCRIPTION, description);
-        delay(10);
-        sendStr(ACCESSORY_STRING_VERSION, version);
-        delay(10);
-        sendStr(ACCESSORY_STRING_URI, uri);
-        delay(10);
-        sendStr(ACCESSORY_STRING_SERIAL, serial);
-
-        delay(100);
-
-        //switch to accessory mode
-        //the Android phone will reset
-        rcode = switchAcc();
-        if(rcode) {
-                goto FailSwAcc; //init fails
-        }
-        rcode = USB_ERROR_CONFIG_REQUIRES_ADDITIONAL_RESET;
-        delay(100); // Give Android a chance to do its reset. This is a guess, and possibly could be lower.
-        goto SwAttempt; //switch to accessory mode attempted
-
-        /* diagnostic messages */
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr(rcode);
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry(rcode);
-        goto Fail;
-#endif
-
-FailGetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetConfDescr(rcode);
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr(rcode);
-        goto Fail;
-#endif
-
-FailGetProto:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("\r\ngetProto:");
-        goto Fail;
-#endif
-
-FailSwAcc:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("\r\nswAcc:");
-        goto Fail;
-#endif
-
-        //FailOnInit:
-        //        USBTRACE("OnInit:");
-        //        goto Fail;
-        //
-SwAttempt:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("\r\nAccessory mode switch attempt");
-Fail:
-#endif
-        //USBTRACE2("\r\nADK Init Failed, error code: ", rcode);
-        //NotifyFail(rcode);
-        Release();
-        return rcode;
-}
-
-/* Extracts bulk-IN and bulk-OUT endpoint information from config descriptor */
-void ADK::EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *pep) {
-        //ErrorMessage<uint8_t>(PSTR("Conf.Val"), conf);
-        //ErrorMessage<uint8_t>(PSTR("Iface Num"), iface);
-        //ErrorMessage<uint8_t>(PSTR("Alt.Set"), alt);
-
-        //added by Yuuichi Akagawa
-        if(bNumEP == 3) {
-                return;
-        }
-
-        bConfNum = conf;
-
-        if((pep->bmAttributes & 0x02) == 2) {
-                uint8_t index = ((pep->bEndpointAddress & 0x80) == 0x80) ? epDataInIndex : epDataOutIndex;
-                // Fill in the endpoint info structure
-                epInfo[index].epAddr = (pep->bEndpointAddress & 0x0F);
-                epInfo[index].maxPktSize = (uint8_t)pep->wMaxPacketSize;
-
-                bNumEP++;
-
-                //PrintEndpointDescriptor(pep);
-        }
-}
-
-/* Performs a cleanup after failed Init() attempt */
-uint8_t ADK::Release() {
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-
-        bNumEP = 1; //must have to be reset to 1
-
-        bAddress = 0;
-        ready = false;
-        return 0;
-}
-
-uint8_t ADK::RcvData(uint16_t *bytes_rcvd, uint8_t *dataptr) {
-        //USBTRACE2("\r\nAddr: ", bAddress );
-        //USBTRACE2("\r\nEP: ",epInfo[epDataInIndex].epAddr);
-        return pUsb->inTransfer(bAddress, epInfo[epDataInIndex].epAddr, bytes_rcvd, dataptr);
-}
-
-uint8_t ADK::SndData(uint16_t nbytes, uint8_t *dataptr) {
-        return pUsb->outTransfer(bAddress, epInfo[epDataOutIndex].epAddr, nbytes, dataptr);
-}
-
-void ADK::PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr) {
-        Notify(PSTR("Endpoint descriptor:"), 0x80);
-        Notify(PSTR("\r\nLength:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bLength, 0x80);
-        Notify(PSTR("\r\nType:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bDescriptorType, 0x80);
-        Notify(PSTR("\r\nAddress:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bEndpointAddress, 0x80);
-        Notify(PSTR("\r\nAttributes:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bmAttributes, 0x80);
-        Notify(PSTR("\r\nMaxPktSize:\t"), 0x80);
-        D_PrintHex<uint16_t > (ep_ptr->wMaxPacketSize, 0x80);
-        Notify(PSTR("\r\nPoll Intrv:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bInterval, 0x80);
-        Notify(PSTR("\r\n"), 0x80);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/adk.h b/lib/usbhost/USB_Host_Shield_2.0/adk.h
deleted file mode 100644
index 4a2920b88a..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/adk.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-/* Google ADK interface support header */
-
-#if !defined(_ADK_H_)
-#define _ADK_H_
-
-#include "Usb.h"
-
-#define ADK_VID   0x18D1
-#define ADK_PID   0x2D00
-#define ADB_PID   0x2D01
-
-#define XOOM  //enables repeating getProto() and getConf() attempts
-//necessary for slow devices such as Motorola XOOM
-//defined by default, can be commented out to save memory
-
-/* requests */
-
-#define ADK_GETPROTO      51  //check USB accessory protocol version
-#define ADK_SENDSTR       52  //send identifying string
-#define ADK_ACCSTART      53  //start device in accessory mode
-
-#define bmREQ_ADK_GET     USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_VENDOR|USB_SETUP_RECIPIENT_DEVICE
-#define bmREQ_ADK_SEND    USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_VENDOR|USB_SETUP_RECIPIENT_DEVICE
-
-#define ACCESSORY_STRING_MANUFACTURER   0
-#define ACCESSORY_STRING_MODEL          1
-#define ACCESSORY_STRING_DESCRIPTION    2
-#define ACCESSORY_STRING_VERSION        3
-#define ACCESSORY_STRING_URI            4
-#define ACCESSORY_STRING_SERIAL         5
-
-#define ADK_MAX_ENDPOINTS 3 //endpoint 0, bulk_IN, bulk_OUT
-
-class ADK;
-
-class ADK : public USBDeviceConfig, public UsbConfigXtracter {
-private:
-        /* ID strings */
-        const char* manufacturer;
-        const char* model;
-        const char* description;
-        const char* version;
-        const char* uri;
-        const char* serial;
-
-        /* ADK proprietary requests */
-        uint8_t getProto(uint8_t* adkproto);
-        uint8_t sendStr(uint8_t index, const char* str);
-        uint8_t switchAcc(void);
-
-protected:
-        static const uint8_t epDataInIndex; // DataIn endpoint index
-        static const uint8_t epDataOutIndex; // DataOUT endpoint index
-
-        /* mandatory members */
-        USB *pUsb;
-        uint8_t bAddress;
-        uint8_t bConfNum; // configuration number
-
-        uint8_t bNumEP; // total number of EP in the configuration
-        bool ready;
-
-        /* Endpoint data structure */
-        EpInfo epInfo[ADK_MAX_ENDPOINTS];
-
-        void PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr);
-
-public:
-        ADK(USB *pUsb, const char* manufacturer,
-                const char* model,
-                const char* description,
-                const char* version,
-                const char* uri,
-                const char* serial);
-
-        // Methods for receiving and sending data
-        uint8_t RcvData(uint16_t *nbytesptr, uint8_t *dataptr);
-        uint8_t SndData(uint16_t nbytes, uint8_t *dataptr);
-
-
-        // USBDeviceConfig implementation
-        uint8_t ConfigureDevice(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t Release();
-
-        virtual uint8_t Poll() {
-                return 0;
-        };
-
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        virtual bool isReady() {
-                return ready;
-        };
-
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return (vid == ADK_VID && (pid == ADK_PID || pid == ADB_PID));
-        };
-
-        //UsbConfigXtracter implementation
-        void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep);
-}; //class ADK : public USBDeviceConfig ...
-
-/* get ADK protocol version */
-
-/* returns 2 bytes in *adkproto */
-inline uint8_t ADK::getProto(uint8_t* adkproto) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_ADK_GET, ADK_GETPROTO, 0, 0, 0, 2, 2, adkproto, NULL));
-}
-
-/* send ADK string */
-inline uint8_t ADK::sendStr(uint8_t index, const char* str) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_ADK_SEND, ADK_SENDSTR, 0, 0, index, strlen(str) + 1, strlen(str) + 1, (uint8_t*)str, NULL));
-}
-
-/* switch to accessory mode */
-inline uint8_t ADK::switchAcc(void) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_ADK_SEND, ADK_ACCSTART, 0, 0, 0, 0, 0, NULL, NULL));
-}
-
-#endif // _ADK_H_
diff --git a/lib/usbhost/USB_Host_Shield_2.0/avrpins.h b/lib/usbhost/USB_Host_Shield_2.0/avrpins.h
deleted file mode 100644
index 4e60e3a229..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/avrpins.h
+++ /dev/null
@@ -1,1130 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-/* derived from Konstantin Chizhov's AVR port templates */
-
-#if !defined(_usb_h_) || defined(_avrpins_h_)
-#error "Never include avrpins.h directly; include Usb.h instead"
-#else
-#define _avrpins_h_
-
-#if defined(__AVR__)
-
-// pointers are 16 bits on AVR
-#define pgm_read_pointer(p) pgm_read_word(p)
-
-// Support for these boards needs to be manually activated in settings.h or in a makefile
-#if !defined(BOARD_MEGA_ADK) && defined(__AVR_ATmega2560__) && (USE_UHS_MEGA_ADK || defined(ARDUINO_AVR_ADK))
-#define BOARD_MEGA_ADK
-#elif !defined(BOARD_BLACK_WIDDOW) && USE_UHS_BLACK_WIDDOW
-#define BOARD_BLACK_WIDDOW
-#endif
-
-#ifdef PORTA
-#define USE_PORTA
-#endif
-#ifdef PORTB
-#define USE_PORTB
-#endif
-#ifdef PORTC
-#define USE_PORTC
-#endif
-#ifdef PORTD
-#define USE_PORTD
-#endif
-#ifdef PORTE
-#define USE_PORTE
-#endif
-#ifdef PORTF
-#define USE_PORTF
-#endif
-#ifdef PORTG
-#define USE_PORTG
-#endif
-#ifdef PORTH
-#define USE_PORTH
-#endif
-#ifdef PORTJ
-#define USE_PORTJ
-#endif
-#ifdef PORTK
-#define USE_PORTK
-#endif
-#ifdef PORTL
-#define USE_PORTL
-#endif
-#ifdef PORTQ
-#define USE_PORTQ
-#endif
-#ifdef PORTR
-#define USE_PORTR
-#endif
-
-#ifdef TCCR0A
-#define USE_TCCR0A
-#endif
-#ifdef TCCR1A
-#define USE_TCCR1A
-#endif
-#ifdef TCCR2A
-#define USE_TCCR2A
-#endif
-
-//Port definitions for AtTiny, AtMega families.
-
-#define MAKE_PORT(portName, ddrName, pinName, className, ID) \
-    class className{\
-    public:\
-      typedef uint8_t DataT;\
-    public:\
-      static void Write(DataT value){portName = value;}\
-      static void ClearAndSet(DataT clearMask, DataT value){portName = (portName & ~clearMask) | value;}\
-      static DataT Read(){return portName;}\
-      static void DirWrite(DataT value){ddrName = value;}\
-      static DataT DirRead(){return ddrName;}\
-      static void Set(DataT value){portName |= value;}\
-      static void Clear(DataT value){portName &= ~value;}\
-      static void Toggle(DataT value){portName ^= value;}\
-      static void DirSet(DataT value){ddrName |= value;}\
-      static void DirClear(DataT value){ddrName &= ~value;}\
-      static void DirToggle(DataT value){ddrName ^= value;}\
-      static DataT PinRead(){return pinName;}\
-      enum{Id = ID};\
-      enum{Width=sizeof(DataT)*8};\
-    };
-
-// TCCR registers to set/clear Arduino PWM
-#define MAKE_TCCR(TccrName, className) \
-    class className{\
-    public:\
-      typedef uint8_t DataT;\
-    public:\
-      static void Write(DataT value){TccrName = value;}\
-      static void ClearAndSet(DataT clearMask, DataT value){TccrName = (TccrName & ~clearMask) | value;}\
-      static DataT Read(){return TccrName;}\
-      static void Set(DataT value){TccrName |= value;}\
-      static void Clear(DataT value){TccrName &= ~value;}\
-      static void Toggle(DataT value){TccrName ^= value;}\
-      enum{Width=sizeof(DataT)*8};\
-    };
-
-#ifdef USE_PORTA
-
-MAKE_PORT(PORTA, DDRA, PINA, Porta, 'A')
-#endif
-#ifdef USE_PORTB
-MAKE_PORT(PORTB, DDRB, PINB, Portb, 'B')
-#endif
-#ifdef USE_PORTC
-MAKE_PORT(PORTC, DDRC, PINC, Portc, 'C')
-#endif
-#ifdef USE_PORTD
-MAKE_PORT(PORTD, DDRD, PIND, Portd, 'D')
-#endif
-#ifdef USE_PORTE
-MAKE_PORT(PORTE, DDRE, PINE, Porte, 'E')
-#endif
-#ifdef USE_PORTF
-MAKE_PORT(PORTF, DDRF, PINF, Portf, 'F')
-#endif
-#ifdef USE_PORTG
-MAKE_PORT(PORTG, DDRG, PING, Portg, 'G')
-#endif
-#ifdef USE_PORTH
-MAKE_PORT(PORTH, DDRH, PINH, Porth, 'H')
-#endif
-#ifdef USE_PORTJ
-MAKE_PORT(PORTJ, DDRJ, PINJ, Portj, 'J')
-#endif
-#ifdef USE_PORTK
-MAKE_PORT(PORTK, DDRK, PINK, Portk, 'K')
-#endif
-#ifdef USE_PORTL
-MAKE_PORT(PORTL, DDRL, PINL, Portl, 'L')
-#endif
-#ifdef USE_PORTQ
-MAKE_PORT(PORTQ, DDRQ, PINQ, Portq, 'Q')
-#endif
-#ifdef USE_PORTR
-MAKE_PORT(PORTR, DDRR, PINR, Portr, 'R')
-#endif
-
-#ifdef USE_TCCR0A
-MAKE_TCCR(TCCR0A, Tccr0a)
-#endif
-#ifdef USE_TCCR1A
-MAKE_TCCR(TCCR1A, Tccr1a)
-#endif
-#ifdef USE_TCCR2A
-MAKE_TCCR(TCCR2A, Tccr2a)
-#endif
-
-// this class represents one pin in a IO port.
-// It is fully static.
-template<typename PORT, uint8_t PIN>
-class TPin {
-        //    BOOST_STATIC_ASSERT(PIN < PORT::Width);
-public:
-        typedef PORT Port;
-
-        enum {
-                Number = PIN
-        };
-
-        static void Set() {
-                PORT::Set(1 << PIN);
-        }
-
-        static void Set(uint8_t val) {
-                if(val)
-                        Set();
-                else Clear();
-        }
-
-        static void SetDir(uint8_t val) {
-                if(val)
-                        SetDirWrite();
-                else SetDirRead();
-        }
-
-        static void Clear() {
-                PORT::Clear(1 << PIN);
-        }
-
-        static void Toggle() {
-                PORT::Toggle(1 << PIN);
-        }
-
-        static void SetDirRead() {
-                PORT::DirClear(1 << PIN);
-        }
-
-        static void SetDirWrite() {
-                PORT::DirSet(1 << PIN);
-        }
-
-        static uint8_t IsSet() {
-                return PORT::PinRead() & (uint8_t)(1 << PIN);
-        }
-
-        static void WaiteForSet() {
-                while(IsSet() == 0) {
-                }
-        }
-
-        static void WaiteForClear() {
-                while(IsSet()) {
-                }
-        }
-}; //class TPin...
-
-// this class represents one bit in TCCR port.
-// used to set/clear TCCRx bits
-// It is fully static.
-
-template<typename TCCR, uint8_t COM>
-class TCom {
-        //    BOOST_STATIC_ASSERT(PIN < PORT::Width);
-public:
-        typedef TCCR Tccr;
-
-        enum {
-                Com = COM
-        };
-
-        static void Set() {
-                TCCR::Set(1 << COM);
-        }
-
-        static void Clear() {
-                TCCR::Clear(1 << COM);
-        }
-
-        static void Toggle() {
-                TCCR::Toggle(1 << COM);
-        }
-}; //class TCom...
-
-//Short pin definitions
-#ifdef USE_PORTA
-typedef TPin<Porta, 0 > Pa0;
-typedef TPin<Porta, 1 > Pa1;
-typedef TPin<Porta, 2 > Pa2;
-typedef TPin<Porta, 3 > Pa3;
-typedef TPin<Porta, 4 > Pa4;
-typedef TPin<Porta, 5 > Pa5;
-typedef TPin<Porta, 6 > Pa6;
-typedef TPin<Porta, 7 > Pa7;
-#endif
-
-#ifdef USE_PORTB
-typedef TPin<Portb, 0 > Pb0;
-typedef TPin<Portb, 1 > Pb1;
-typedef TPin<Portb, 2 > Pb2;
-typedef TPin<Portb, 3 > Pb3;
-typedef TPin<Portb, 4 > Pb4;
-typedef TPin<Portb, 5 > Pb5;
-typedef TPin<Portb, 6 > Pb6;
-typedef TPin<Portb, 7 > Pb7;
-#endif
-
-#ifdef USE_PORTC
-typedef TPin<Portc, 0 > Pc0;
-typedef TPin<Portc, 1 > Pc1;
-typedef TPin<Portc, 2 > Pc2;
-typedef TPin<Portc, 3 > Pc3;
-typedef TPin<Portc, 4 > Pc4;
-typedef TPin<Portc, 5 > Pc5;
-typedef TPin<Portc, 6 > Pc6;
-typedef TPin<Portc, 7 > Pc7;
-#endif
-
-#ifdef USE_PORTD
-typedef TPin<Portd, 0 > Pd0;
-typedef TPin<Portd, 1 > Pd1;
-typedef TPin<Portd, 2 > Pd2;
-typedef TPin<Portd, 3 > Pd3;
-typedef TPin<Portd, 4 > Pd4;
-typedef TPin<Portd, 5 > Pd5;
-typedef TPin<Portd, 6 > Pd6;
-typedef TPin<Portd, 7 > Pd7;
-#endif
-
-#ifdef USE_PORTE
-typedef TPin<Porte, 0 > Pe0;
-typedef TPin<Porte, 1 > Pe1;
-typedef TPin<Porte, 2 > Pe2;
-typedef TPin<Porte, 3 > Pe3;
-typedef TPin<Porte, 4 > Pe4;
-typedef TPin<Porte, 5 > Pe5;
-typedef TPin<Porte, 6 > Pe6;
-typedef TPin<Porte, 7 > Pe7;
-#endif
-
-#ifdef USE_PORTF
-typedef TPin<Portf, 0 > Pf0;
-typedef TPin<Portf, 1 > Pf1;
-typedef TPin<Portf, 2 > Pf2;
-typedef TPin<Portf, 3 > Pf3;
-typedef TPin<Portf, 4 > Pf4;
-typedef TPin<Portf, 5 > Pf5;
-typedef TPin<Portf, 6 > Pf6;
-typedef TPin<Portf, 7 > Pf7;
-#endif
-
-#ifdef USE_PORTG
-typedef TPin<Portg, 0 > Pg0;
-typedef TPin<Portg, 1 > Pg1;
-typedef TPin<Portg, 2 > Pg2;
-typedef TPin<Portg, 3 > Pg3;
-typedef TPin<Portg, 4 > Pg4;
-typedef TPin<Portg, 5 > Pg5;
-typedef TPin<Portg, 6 > Pg6;
-typedef TPin<Portg, 7 > Pg7;
-#endif
-
-#ifdef USE_PORTH
-typedef TPin<Porth, 0 > Ph0;
-typedef TPin<Porth, 1 > Ph1;
-typedef TPin<Porth, 2 > Ph2;
-typedef TPin<Porth, 3 > Ph3;
-typedef TPin<Porth, 4 > Ph4;
-typedef TPin<Porth, 5 > Ph5;
-typedef TPin<Porth, 6 > Ph6;
-typedef TPin<Porth, 7 > Ph7;
-#endif
-
-#ifdef USE_PORTJ
-typedef TPin<Portj, 0 > Pj0;
-typedef TPin<Portj, 1 > Pj1;
-typedef TPin<Portj, 2 > Pj2;
-typedef TPin<Portj, 3 > Pj3;
-typedef TPin<Portj, 4 > Pj4;
-typedef TPin<Portj, 5 > Pj5;
-typedef TPin<Portj, 6 > Pj6;
-typedef TPin<Portj, 7 > Pj7;
-#endif
-
-#ifdef USE_PORTK
-typedef TPin<Portk, 0 > Pk0;
-typedef TPin<Portk, 1 > Pk1;
-typedef TPin<Portk, 2 > Pk2;
-typedef TPin<Portk, 3 > Pk3;
-typedef TPin<Portk, 4 > Pk4;
-typedef TPin<Portk, 5 > Pk5;
-typedef TPin<Portk, 6 > Pk6;
-typedef TPin<Portk, 7 > Pk7;
-#endif
-
-#ifdef USE_PORTL
-typedef TPin<Portl, 0 > Pl0;
-typedef TPin<Portl, 1 > Pl1;
-typedef TPin<Portl, 2 > Pl2;
-typedef TPin<Portl, 3 > Pl3;
-typedef TPin<Portl, 4 > Pl4;
-typedef TPin<Portl, 5 > Pl5;
-typedef TPin<Portl, 6 > Pl6;
-typedef TPin<Portl, 7 > Pl7;
-#endif
-
-#ifdef USE_PORTQ
-typedef TPin<Portq, 0 > Pq0;
-typedef TPin<Portq, 1 > Pq1;
-typedef TPin<Portq, 2 > Pq2;
-typedef TPin<Portq, 3 > Pq3;
-typedef TPin<Portq, 4 > Pq4;
-typedef TPin<Portq, 5 > Pq5;
-typedef TPin<Portq, 6 > Pq6;
-typedef TPin<Portq, 7 > Pq7;
-#endif
-
-#ifdef USE_PORTR
-typedef TPin<Portr, 0 > Pr0;
-typedef TPin<Portr, 1 > Pr1;
-typedef TPin<Portr, 2 > Pr2;
-typedef TPin<Portr, 3 > Pr3;
-typedef TPin<Portr, 4 > Pr4;
-typedef TPin<Portr, 5 > Pr5;
-typedef TPin<Portr, 6 > Pr6;
-typedef TPin<Portr, 7 > Pr7;
-#endif
-
-#ifdef USE_TCCR0A
-typedef TCom<Tccr0a, COM0A1> Tc0a; //P6
-typedef TCom<Tccr0a, COM0B1> Tc0b; //P5
-#endif
-
-#ifdef USE_TCCR1A
-typedef TCom<Tccr1a, COM1A1> Tc1a; //P9
-typedef TCom<Tccr1a, COM1B1> Tc1b; //P10
-#endif
-
-#ifdef USE_TCCR2A
-typedef TCom<Tccr2a, COM2A1> Tc2a; //P11
-typedef TCom<Tccr2a, COM2B1> Tc2b; //P3
-#endif
-
-template<typename Tp_pin, typename Tc_bit>
-class Tp_Tc {
-public:
-
-        static void SetDir(uint8_t val) {
-                if(val)
-                        SetDirWrite();
-                else SetDirRead();
-        }
-
-        static void SetDirRead() {
-                Tp_pin::SetDirRead(); //set pin direction
-                Tc_bit::Clear(); //disconnect pin from PWM
-        }
-
-        static void SetDirWrite() {
-                Tp_pin::SetDirWrite();
-                Tc_bit::Clear();
-        }
-};
-
-/* pin definitions for cases where it's necessary to clear compare output mode bits */
-
-//typedef Tp_Tc<Pd3, Tc2b> P3;  //Arduino pin 3
-//typedef Tp_Tc<Pd5, Tc0b> P5;  //Arduino pin 5
-//typedef Tp_Tc<Pd6, Tc0a> P6;  //Arduino pin 6
-//typedef Tp_Tc<Pb1, Tc1a> P9;  //Arduino pin 9
-//typedef Tp_Tc<Pb2, Tc1b> P10;  //Arduino pin 10
-//typedef Tp_Tc<Pb3, Tc2a> P11;  //Arduino pin 11
-
-/* Arduino pin definitions  */
-#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
-// "Mega" Arduino pin numbers
-
-#define P0  Pe0
-#define P1  Pe1
-#define P2  Pe4
-#define P3  Pe5
-#define P4  Pg5
-#define P5  Pe3
-#define P6  Ph3
-#define P7  Ph4
-
-#define P8  Ph5
-#define P9  Ph6
-#define P10  Pb4
-#define P11  Pb5
-#define P12  Pb6
-#define P13  Pb7
-
-#define P14  Pj1
-#define P15  Pj0
-#define P16  Ph1
-#define P17  Ph0
-#define P18  Pd3
-#define P19  Pd2
-#define P20  Pd1
-#define P21  Pd0
-
-#define P22 Pa0
-#define P23 Pa1
-#define P24 Pa2
-#define P25 Pa3
-#define P26 Pa4
-#define P27 Pa5
-#define P28 Pa6
-#define P29 Pa7
-#define P30 Pc7
-#define P31 Pc6
-#define P32 Pc5
-#define P33 Pc4
-#define P34 Pc3
-#define P35 Pc2
-#define P36 Pc1
-#define P37 Pc0
-
-#define P38 Pd7
-#define P39 Pg2
-#define P40 Pg1
-#define P41 Pg0
-#define P42 Pl7
-#define P43 Pl6
-#define P44 Pl5
-#define P45 Pl4
-#define P46 Pl3
-#define P47 Pl2
-#define P48 Pl1
-#define P49 Pl0
-#define P50 Pb3
-#define P51 Pb2
-#define P52 Pb1
-#define P53 Pb0
-
-#ifdef BOARD_MEGA_ADK // These pins are not broken out on the Arduino ADK
-#define P54 Pe6 // INT on Arduino ADK
-#define P55 Pj2 // MAX_RESET on Arduino ADK
-#endif
-
-// "Mega" pin numbers
-
-#elif defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__)
-// "Classic" Arduino pin numbers
-
-#define P0  Pd0
-#define P1  Pd1
-#define P2  Pd2
-#define P3  Pd3
-#define P4  Pd4
-#define P5  Pd5
-#define P6  Pd6
-#define P7  Pd7
-
-#define P8  Pb0
-#define P9  Pb1
-#define P10  Pb2
-#define P11  Pb3
-#define P12  Pb4
-#define P13  Pb5
-
-#define P14  Pc0
-#define P15  Pc1
-#define P16  Pc2
-#define P17  Pc3
-#define P18  Pc4
-#define P19  Pc5
-
-// "Classic" Arduino pin numbers
-
-#elif defined(CORE_TEENSY) && defined(__AVR_ATmega32U4__)
-// Teensy 2.0 pin numbers
-// http://www.pjrc.com/teensy/pinout.html
-#define P0  Pb0
-#define P1  Pb1
-#define P2  Pb2
-#define P3  Pb3
-#define P4  Pb7
-#define P5  Pd0
-#define P6  Pd1
-#define P7  Pd2
-#define P8  Pd3
-#define P9  Pc6
-#define P10 Pc7
-#define P11 Pd6
-#define P12 Pd7
-#define P13 Pb4
-#define P14 Pb5
-#define P15 Pb6
-#define P16 Pf7
-#define P17 Pf6
-#define P18 Pf5
-#define P19 Pf4
-#define P20 Pf1
-#define P21 Pf0
-#define P22 Pd4
-#define P23 Pd5
-#define P24 Pe6
-// Teensy 2.0
-
-#elif defined(__AVR_ATmega32U4__)
-// Arduino Leonardo pin numbers
-
-#define P0  Pd2 // D0 - PD2
-#define P1  Pd3 // D1 - PD3
-#define P2  Pd1 // D2 - PD1
-#define P3  Pd0 // D3 - PD0
-#define P4  Pd4 // D4 - PD4
-#define P5  Pc6 // D5 - PC6
-#define P6  Pd7 // D6 - PD7
-#define P7  Pe6 // D7 - PE6
-
-#define P8  Pb4 // D8 - PB4
-#define P9  Pb5 // D9 - PB5
-#define P10 Pb6 // D10 - PB6
-#define P11 Pb7 // D11 - PB7
-#define P12 Pd6 // D12 - PD6
-#define P13 Pc7 // D13 - PC7
-
-#define P14 Pb3 // D14 - MISO - PB3
-#define P15 Pb1 // D15 - SCK - PB1
-#define P16 Pb2 // D16 - MOSI - PB2
-#define P17 Pb0 // D17 - SS - PB0
-
-#define P18 Pf7 // D18 - A0 - PF7
-#define P19 Pf6 // D19 - A1 - PF6
-#define P20 Pf5 // D20 - A2 - PF5
-#define P21 Pf4 // D21 - A3 - PF4
-#define P22 Pf1 // D22 - A4 - PF1
-#define P23 Pf0 // D23 - A5 - PF0
-
-#define P24 Pd4 // D24 / D4 - A6 - PD4
-#define P25 Pd7 // D25 / D6 - A7 - PD7
-#define P26 Pb4 // D26 / D8 - A8 - PB4
-#define P27 Pb5 // D27 / D9 - A9 - PB5
-#define P28 Pb6 // D28 / D10 - A10 - PB6
-#define P29 Pd6 // D29 / D12 - A11 - PD6
-
-// Arduino Leonardo pin numbers
-
-#elif defined(CORE_TEENSY) && (defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__))
-// Teensy++ 1.0 and 2.0 pin numbers
-// http://www.pjrc.com/teensy/pinout.html
-#define P0  Pd0
-#define P1  Pd1
-#define P2  Pd2
-#define P3  Pd3
-#define P4  Pd4
-#define P5  Pd5
-#define P6  Pd6
-#define P7  Pd7
-#define P8  Pe0
-#define P9  Pe1
-#define P10 Pc0
-#define P11 Pc1
-#define P12 Pc2
-#define P13 Pc3
-#define P14 Pc4
-#define P15 Pc5
-#define P16 Pc6
-#define P17 Pc7
-#define P18 Pe6
-#define P19 Pe7
-#define P20 Pb0
-#define P21 Pb1
-#define P22 Pb2
-#define P23 Pb3
-#define P24 Pb4
-#define P25 Pb5
-#define P26 Pb6
-#define P27 Pb7
-#define P28 Pa0
-#define P29 Pa1
-#define P30 Pa2
-#define P31 Pa3
-#define P32 Pa4
-#define P33 Pa5
-#define P34 Pa6
-#define P35 Pa7
-#define P36 Pe4
-#define P37 Pe5
-#define P38 Pf0
-#define P39 Pf1
-#define P40 Pf2
-#define P41 Pf3
-#define P42 Pf4
-#define P43 Pf5
-#define P44 Pf6
-#define P45 Pf7
-// Teensy++ 1.0 and 2.0
-
-#elif defined(ARDUINO_AVR_BALANDUINO) && (defined(__AVR_ATmega644__) || defined(__AVR_ATmega1284P__))
-// Balanduino pin numbers
-// http://balanduino.net/
-#define P0  Pd0 /* 0  - PD0 */
-#define P1  Pd1 /* 1  - PD1 */
-
-#if BALANDUINO_REVISION < 13
-  #define P2  Pb2 /* 2  - PB2 */
-  #define P3  Pd6 /* 3  - PD6 */
-  #define P4  Pd7 /* 4  - PD7 */
-  #define P5  Pb3 /* 5  - PB3 */
-#else
-  #define P2  Pd2 /* 2  - PD2 */
-  #define P3  Pd3 /* 3  - PD3 */
-  #define P4  Pd6 /* 4  - PD6 */
-  #define P5  Pd7 /* 5  - PD7 */
-#endif
-
-#define P6  Pb4 /* 6  - PB4 */
-#define P7  Pa0 /* 7  - PA0 */
-#define P8  Pa1 /* 8  - PA1 */
-#define P9  Pa2 /* 9  - PA2 */
-#define P10 Pa3 /* 10 - PA3 */
-#define P11 Pa4 /* 11 - PA4 */
-#define P12 Pa5 /* 12 - PA5 */
-#define P13 Pc1 /* 13 - PC1 */
-#define P14 Pc0 /* 14 - PC0 */
-
-#if BALANDUINO_REVISION < 13
-  #define P15 Pd2 /* 15 - PD2 */
-  #define P16 Pd3 /* 16 - PD3 */
-#else
-  #define P15 Pb2 /* 15 - PB2 */
-  #define P16 Pb3 /* 16 - PB2 */
-#endif
-
-#define P17 Pd4 /* 17 - PD4 */
-#define P18 Pd5 /* 18 - PD5 */
-#define P19 Pc2 /* 19 - PC2 */
-#define P20 Pc3 /* 20 - PC3 */
-#define P21 Pc4 /* 21 - PC4 */
-#define P22 Pc5 /* 22 - PC5 */
-#define P23 Pc6 /* 23 - PC6 */
-#define P24 Pc7 /* 24 - PC7 */
-#define P25 Pb0 /* 25 - PB0 */
-#define P26 Pb1 /* 26 - PB1 */
-#define P27 Pb5 /* 27 - PB5 */
-#define P28 Pb6 /* 28 - PB6 */
-#define P29 Pb7 /* 29 - PB7 */
-#define P30 Pa6 /* 30 - PA6 */
-#define P31 Pa7 /* 31 - PA7 */
-// Balanduino
-
-#elif defined(__AVR_ATmega644__) || defined(__AVR_ATmega644P__) || defined(__AVR_ATmega1284__) || defined(__AVR_ATmega1284P__)
-// Sanguino pin numbers
-// Homepage: http://sanguino.cc/hardware
-// Hardware add-on: https://github.com/Lauszus/Sanguino
-#define P0  Pb0
-#define P1  Pb1
-#define P2  Pb2
-#define P3  Pb3
-#define P4  Pb4
-#define P5  Pb5
-#define P6  Pb6
-#define P7  Pb7
-#define P8  Pd0
-#define P9  Pd1
-#define P10 Pd2
-#define P11 Pd3
-#define P12 Pd4
-#define P13 Pd5
-#define P14 Pd6
-#define P15 Pd7
-#define P16 Pc0
-#define P17 Pc1
-#define P18 Pc2
-#define P19 Pc3
-#define P20 Pc4
-#define P21 Pc5
-#define P22 Pc6
-#define P23 Pc7
-#define P24 Pa0
-#define P25 Pa1
-#define P26 Pa2
-#define P27 Pa3
-#define P28 Pa4
-#define P29 Pa5
-#define P30 Pa6
-#define P31 Pa7
-// Sanguino
-
-#else
-#error "Please define board in avrpins.h"
-
-#endif // Arduino pin definitions
-
-#elif defined(__arm__)
-
-// pointers are 32 bits on ARM
-#define pgm_read_pointer(p) pgm_read_dword(p)
-
-#if defined(CORE_TEENSY) && (defined(__MK20DX128__) || defined(__MK20DX256__))
-
-#include "core_pins.h"
-#include "avr_emulation.h"
-
-#define GPIO_BITBAND_ADDR(reg, bit) (((uint32_t)&(reg) - 0x40000000) * 32 + (bit) * 4 + 0x42000000)
-#define GPIO_BITBAND_PTR(reg, bit) ((uint8_t *)GPIO_BITBAND_ADDR((reg), (bit)))
-
-#define MAKE_PIN(className, baseReg, pinNum, configReg) \
-class className { \
-public: \
-  static void Set() { \
-    *GPIO_BITBAND_PTR(baseReg, pinNum) = 1; \
-  } \
-  static void Clear() { \
-    *GPIO_BITBAND_PTR(baseReg, pinNum) = 0; \
-  } \
-  static void SetDirRead() { \
-    configReg = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1); \
-    *(GPIO_BITBAND_PTR(baseReg, pinNum) + 640) = 0; \
-  } \
-  static void SetDirWrite() { \
-    configReg = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1); \
-    *(GPIO_BITBAND_PTR(baseReg, pinNum) + 640) = 1; \
-  } \
-  static uint8_t IsSet() { \
-    return *(GPIO_BITBAND_PTR(baseReg, pinNum) + 512); \
-  } \
-};
-
-MAKE_PIN(P0, CORE_PIN0_PORTREG, CORE_PIN0_BIT, CORE_PIN0_CONFIG);
-MAKE_PIN(P1, CORE_PIN1_PORTREG, CORE_PIN1_BIT, CORE_PIN1_CONFIG);
-MAKE_PIN(P2, CORE_PIN2_PORTREG, CORE_PIN2_BIT, CORE_PIN2_CONFIG);
-MAKE_PIN(P3, CORE_PIN3_PORTREG, CORE_PIN3_BIT, CORE_PIN3_CONFIG);
-MAKE_PIN(P4, CORE_PIN4_PORTREG, CORE_PIN4_BIT, CORE_PIN4_CONFIG);
-MAKE_PIN(P5, CORE_PIN5_PORTREG, CORE_PIN5_BIT, CORE_PIN5_CONFIG);
-MAKE_PIN(P6, CORE_PIN6_PORTREG, CORE_PIN6_BIT, CORE_PIN6_CONFIG);
-MAKE_PIN(P7, CORE_PIN7_PORTREG, CORE_PIN7_BIT, CORE_PIN7_CONFIG);
-MAKE_PIN(P8, CORE_PIN8_PORTREG, CORE_PIN8_BIT, CORE_PIN8_CONFIG);
-MAKE_PIN(P9, CORE_PIN9_PORTREG, CORE_PIN9_BIT, CORE_PIN9_CONFIG);
-MAKE_PIN(P10, CORE_PIN10_PORTREG, CORE_PIN10_BIT, CORE_PIN10_CONFIG);
-MAKE_PIN(P11, CORE_PIN11_PORTREG, CORE_PIN11_BIT, CORE_PIN11_CONFIG);
-MAKE_PIN(P12, CORE_PIN12_PORTREG, CORE_PIN12_BIT, CORE_PIN12_CONFIG);
-MAKE_PIN(P13, CORE_PIN13_PORTREG, CORE_PIN13_BIT, CORE_PIN13_CONFIG);
-MAKE_PIN(P14, CORE_PIN14_PORTREG, CORE_PIN14_BIT, CORE_PIN14_CONFIG);
-MAKE_PIN(P15, CORE_PIN15_PORTREG, CORE_PIN15_BIT, CORE_PIN15_CONFIG);
-MAKE_PIN(P16, CORE_PIN16_PORTREG, CORE_PIN16_BIT, CORE_PIN16_CONFIG);
-MAKE_PIN(P17, CORE_PIN17_PORTREG, CORE_PIN17_BIT, CORE_PIN17_CONFIG);
-MAKE_PIN(P18, CORE_PIN18_PORTREG, CORE_PIN18_BIT, CORE_PIN18_CONFIG);
-MAKE_PIN(P19, CORE_PIN19_PORTREG, CORE_PIN19_BIT, CORE_PIN19_CONFIG);
-MAKE_PIN(P20, CORE_PIN20_PORTREG, CORE_PIN20_BIT, CORE_PIN20_CONFIG);
-MAKE_PIN(P21, CORE_PIN21_PORTREG, CORE_PIN21_BIT, CORE_PIN21_CONFIG);
-MAKE_PIN(P22, CORE_PIN22_PORTREG, CORE_PIN22_BIT, CORE_PIN22_CONFIG);
-MAKE_PIN(P23, CORE_PIN23_PORTREG, CORE_PIN23_BIT, CORE_PIN23_CONFIG);
-MAKE_PIN(P24, CORE_PIN24_PORTREG, CORE_PIN24_BIT, CORE_PIN24_CONFIG);
-MAKE_PIN(P25, CORE_PIN25_PORTREG, CORE_PIN25_BIT, CORE_PIN25_CONFIG);
-MAKE_PIN(P26, CORE_PIN26_PORTREG, CORE_PIN26_BIT, CORE_PIN26_CONFIG);
-MAKE_PIN(P27, CORE_PIN27_PORTREG, CORE_PIN27_BIT, CORE_PIN27_CONFIG);
-MAKE_PIN(P28, CORE_PIN28_PORTREG, CORE_PIN28_BIT, CORE_PIN28_CONFIG);
-MAKE_PIN(P29, CORE_PIN29_PORTREG, CORE_PIN29_BIT, CORE_PIN29_CONFIG);
-MAKE_PIN(P30, CORE_PIN30_PORTREG, CORE_PIN30_BIT, CORE_PIN30_CONFIG);
-MAKE_PIN(P31, CORE_PIN31_PORTREG, CORE_PIN31_BIT, CORE_PIN31_CONFIG);
-MAKE_PIN(P32, CORE_PIN32_PORTREG, CORE_PIN32_BIT, CORE_PIN32_CONFIG);
-MAKE_PIN(P33, CORE_PIN33_PORTREG, CORE_PIN33_BIT, CORE_PIN33_CONFIG);
-
-#undef MAKE_PIN
-
-#elif defined(ARDUINO_SAM_DUE) && defined(__SAM3X8E__)
-
-// SetDirRead:
-//   Disable interrupts
-//   Disable the pull up resistor
-//   Set to INPUT
-//   Enable PIO
-
-// SetDirWrite:
-//   Disable interrupts
-//   Disable the pull up resistor
-//   Set to OUTPUT
-//   Enable PIO
-
-#define MAKE_PIN(className, pio, pinMask) \
-class className { \
-public: \
-  static void Set() { \
-    pio->PIO_SODR = pinMask; \
-  } \
-  static void Clear() { \
-    pio->PIO_CODR = pinMask; \
-  } \
-  static void SetDirRead() { \
-    pio->PIO_IDR = pinMask ; \
-    pio->PIO_PUDR = pinMask; \
-    pio->PIO_ODR = pinMask; \
-    pio->PIO_PER = pinMask; \
-  } \
-  static void SetDirWrite() { \
-    pio->PIO_IDR = pinMask ; \
-    pio->PIO_PUDR = pinMask; \
-    pio->PIO_OER = pinMask; \
-    pio->PIO_PER = pinMask; \
-  } \
-  static uint8_t IsSet() { \
-    return pio->PIO_PDSR & pinMask; \
-  } \
-};
-
-// See: http://arduino.cc/en/Hacking/PinMappingSAM3X and variant.cpp
-
-MAKE_PIN(P0, PIOA, PIO_PA8);
-MAKE_PIN(P1, PIOA, PIO_PA9);
-MAKE_PIN(P2, PIOB, PIO_PB25);
-MAKE_PIN(P3, PIOC, PIO_PC28);
-MAKE_PIN(P4, PIOC, PIO_PC26);
-MAKE_PIN(P5, PIOC, PIO_PC25);
-MAKE_PIN(P6, PIOC, PIO_PC24);
-MAKE_PIN(P7, PIOC, PIO_PC23);
-MAKE_PIN(P8, PIOC, PIO_PC22);
-MAKE_PIN(P9, PIOC, PIO_PC21);
-MAKE_PIN(P10, PIOC, PIO_PC29);
-MAKE_PIN(P11, PIOD, PIO_PD7);
-MAKE_PIN(P12, PIOD, PIO_PD8);
-MAKE_PIN(P13, PIOB, PIO_PB27);
-MAKE_PIN(P14, PIOD, PIO_PD4);
-MAKE_PIN(P15, PIOD, PIO_PD5);
-MAKE_PIN(P16, PIOA, PIO_PA13);
-MAKE_PIN(P17, PIOA, PIO_PA12);
-MAKE_PIN(P18, PIOA, PIO_PA11);
-MAKE_PIN(P19, PIOA, PIO_PA10);
-MAKE_PIN(P20, PIOB, PIO_PB12);
-MAKE_PIN(P21, PIOB, PIO_PB13);
-MAKE_PIN(P22, PIOB, PIO_PB26);
-MAKE_PIN(P23, PIOA, PIO_PA14);
-MAKE_PIN(P24, PIOA, PIO_PA15);
-MAKE_PIN(P25, PIOD, PIO_PD0);
-MAKE_PIN(P26, PIOD, PIO_PD1);
-MAKE_PIN(P27, PIOD, PIO_PD2);
-MAKE_PIN(P28, PIOD, PIO_PD3);
-MAKE_PIN(P29, PIOD, PIO_PD6);
-MAKE_PIN(P30, PIOD, PIO_PD9);
-MAKE_PIN(P31, PIOA, PIO_PA7);
-MAKE_PIN(P32, PIOD, PIO_PD10);
-MAKE_PIN(P33, PIOC, PIO_PC1);
-MAKE_PIN(P34, PIOC, PIO_PC2);
-MAKE_PIN(P35, PIOC, PIO_PC3);
-MAKE_PIN(P36, PIOC, PIO_PC4);
-MAKE_PIN(P37, PIOC, PIO_PC5);
-MAKE_PIN(P38, PIOC, PIO_PC6);
-MAKE_PIN(P39, PIOC, PIO_PC7);
-MAKE_PIN(P40, PIOC, PIO_PC8);
-MAKE_PIN(P41, PIOC, PIO_PC9);
-MAKE_PIN(P42, PIOA, PIO_PA19);
-MAKE_PIN(P43, PIOA, PIO_PA20);
-MAKE_PIN(P44, PIOC, PIO_PC19);
-MAKE_PIN(P45, PIOC, PIO_PC18);
-MAKE_PIN(P46, PIOC, PIO_PC17);
-MAKE_PIN(P47, PIOC, PIO_PC16);
-MAKE_PIN(P48, PIOC, PIO_PC15);
-MAKE_PIN(P49, PIOC, PIO_PC14);
-MAKE_PIN(P50, PIOC, PIO_PC13);
-MAKE_PIN(P51, PIOC, PIO_PC12);
-MAKE_PIN(P52, PIOB, PIO_PB21);
-MAKE_PIN(P53, PIOB, PIO_PB14);
-MAKE_PIN(P54, PIOA, PIO_PA16);
-MAKE_PIN(P55, PIOA, PIO_PA24);
-MAKE_PIN(P56, PIOA, PIO_PA23);
-MAKE_PIN(P57, PIOA, PIO_PA22);
-MAKE_PIN(P58, PIOA, PIO_PA6);
-MAKE_PIN(P59, PIOA, PIO_PA4);
-MAKE_PIN(P60, PIOA, PIO_PA3);
-MAKE_PIN(P61, PIOA, PIO_PA2);
-MAKE_PIN(P62, PIOB, PIO_PB17);
-MAKE_PIN(P63, PIOB, PIO_PB18);
-MAKE_PIN(P64, PIOB, PIO_PB19);
-MAKE_PIN(P65, PIOB, PIO_PB20);
-MAKE_PIN(P66, PIOB, PIO_PB15);
-MAKE_PIN(P67, PIOB, PIO_PB16);
-MAKE_PIN(P68, PIOA, PIO_PA1);
-MAKE_PIN(P69, PIOA, PIO_PA0);
-MAKE_PIN(P70, PIOA, PIO_PA17);
-MAKE_PIN(P71, PIOA, PIO_PA18);
-MAKE_PIN(P72, PIOC, PIO_PC30);
-MAKE_PIN(P73, PIOA, PIO_PA21);
-MAKE_PIN(P74, PIOA, PIO_PA25); // MISO
-MAKE_PIN(P75, PIOA, PIO_PA26); // MOSI
-MAKE_PIN(P76, PIOA, PIO_PA27); // CLK
-MAKE_PIN(P77, PIOA, PIO_PA28);
-MAKE_PIN(P78, PIOB, PIO_PB23); // Unconnected
-
-#undef MAKE_PIN
-
-#elif defined(RBL_NRF51822)
-
-#define MAKE_PIN(className, pin) \
-class className { \
-public: \
-    static void Set() { \
-        nrf_gpio_pin_set(pin); \
-    } \
-    static void Clear() { \
-        nrf_gpio_pin_clear(pin); \
-    } \
-    static void SetDirRead() { \
-        nrf_gpio_cfg_input(pin, NRF_GPIO_PIN_NOPULL); \
-    } \
-    static void SetDirWrite() { \
-        nrf_gpio_cfg_output(pin); \
-    } \
-    static uint8_t IsSet() { \
-        return (uint8_t)nrf_gpio_pin_read(pin); \
-    } \
-};
-
-// See: pin_transform.c in RBL nRF51822 SDK
-MAKE_PIN(P0, Pin_nRF51822_to_Arduino(D0));
-MAKE_PIN(P1, Pin_nRF51822_to_Arduino(D1));
-MAKE_PIN(P2, Pin_nRF51822_to_Arduino(D2));
-MAKE_PIN(P3, Pin_nRF51822_to_Arduino(D3));
-MAKE_PIN(P4, Pin_nRF51822_to_Arduino(D4));
-MAKE_PIN(P5, Pin_nRF51822_to_Arduino(D5));
-MAKE_PIN(P6, Pin_nRF51822_to_Arduino(D6));
-MAKE_PIN(P7, Pin_nRF51822_to_Arduino(D7));
-MAKE_PIN(P8, Pin_nRF51822_to_Arduino(D8));
-MAKE_PIN(P9, Pin_nRF51822_to_Arduino(D9)); // INT
-MAKE_PIN(P10, Pin_nRF51822_to_Arduino(D10)); // SS
-MAKE_PIN(P11, Pin_nRF51822_to_Arduino(D11));
-MAKE_PIN(P12, Pin_nRF51822_to_Arduino(D12));
-MAKE_PIN(P13, Pin_nRF51822_to_Arduino(D13));
-MAKE_PIN(P14, Pin_nRF51822_to_Arduino(D14));
-MAKE_PIN(P15, Pin_nRF51822_to_Arduino(D15));
-MAKE_PIN(P17, Pin_nRF51822_to_Arduino(D17)); // MISO
-MAKE_PIN(P18, Pin_nRF51822_to_Arduino(D18)); // MOSI
-MAKE_PIN(P16, Pin_nRF51822_to_Arduino(D16)); // CLK
-MAKE_PIN(P19, Pin_nRF51822_to_Arduino(D19));
-MAKE_PIN(P20, Pin_nRF51822_to_Arduino(D20));
-MAKE_PIN(P21, Pin_nRF51822_to_Arduino(D21));
-MAKE_PIN(P22, Pin_nRF51822_to_Arduino(D22));
-MAKE_PIN(P23, Pin_nRF51822_to_Arduino(D23));
-MAKE_PIN(P24, Pin_nRF51822_to_Arduino(D24));
-
-#undef MAKE_PIN
-
-#else
-#error "Please define board in avrpins.h"
-
-#endif
-
-#elif defined(__ARDUINO_X86__) // Intel Galileo, Intel Galileo 2 and Intel Edison
-
-#include <avr/pgmspace.h>
-
-// Pointers are 32 bits on x86
-#define pgm_read_pointer(p) pgm_read_dword(p)
-
-#if PLATFORM_ID == 0xE1 // Edison platform id
-#define pinToFastPin(pin) 1 // As far as I can tell all pins can be used as fast pins
-#endif
-
-// Pin 2 and 3 on the Intel Galileo supports a higher rate,
-// so it is recommended to use one of these as the SS pin.
-
-#define MAKE_PIN(className, pin) \
-class className { \
-public: \
-  static void Set() { \
-    fastDigitalWrite(pin, HIGH); \
-  } \
-  static void Clear() { \
-    fastDigitalWrite(pin, LOW); \
-  } \
-  static void SetDirRead() { \
-    if (pinToFastPin(pin)) \
-      pinMode(pin, INPUT_FAST); \
-    else \
-      pinMode(pin, INPUT); \
-  } \
-  static void SetDirWrite() { \
-    if (pinToFastPin(pin)) \
-      pinMode(pin, OUTPUT_FAST); \
-    else \
-      pinMode(pin, OUTPUT); \
-  } \
-  static uint8_t IsSet() { \
-    return fastDigitalRead(pin); \
-  } \
-};
-
-MAKE_PIN(P0, 0);
-MAKE_PIN(P1, 1);
-MAKE_PIN(P2, 2);
-MAKE_PIN(P3, 3);
-MAKE_PIN(P4, 4);
-MAKE_PIN(P5, 5);
-MAKE_PIN(P6, 6);
-MAKE_PIN(P7, 7);
-MAKE_PIN(P8, 8);
-MAKE_PIN(P9, 9);
-MAKE_PIN(P10, 10);
-MAKE_PIN(P11, 11);
-MAKE_PIN(P12, 12);
-MAKE_PIN(P13, 13);
-MAKE_PIN(P14, 14); // A0
-MAKE_PIN(P15, 15); // A1
-MAKE_PIN(P16, 16); // A2
-MAKE_PIN(P17, 17); // A3
-MAKE_PIN(P18, 18); // A4
-MAKE_PIN(P19, 19); // A5
-
-#undef MAKE_PIN
-
-#elif defined(__MIPSEL__)
-// MIPSEL (MIPS architecture using a little endian byte order)
-
-// MIPS size_t = 4
-#define pgm_read_pointer(p) pgm_read_dword(p)
-
-#define MAKE_PIN(className, pin) \
-class className { \
-public: \
-  static void Set() { \
-    digitalWrite(pin, HIGH);\
-  } \
-  static void Clear() { \
-    digitalWrite(pin, LOW); \
-  } \
-  static void SetDirRead() { \
-    pinMode(pin, INPUT); \
-  } \
-  static void SetDirWrite() { \
-    pinMode(pin, OUTPUT); \
-  } \
-  static uint8_t IsSet() { \
-    return digitalRead(pin); \
-  } \
-};
-
-// 0 .. 13 - Digital pins
-MAKE_PIN(P0, 0); // RX
-MAKE_PIN(P1, 1); // TX
-MAKE_PIN(P2, 2); //
-MAKE_PIN(P3, 3); //
-MAKE_PIN(P4, 4); //
-MAKE_PIN(P5, 5); //
-MAKE_PIN(P6, 6); //
-MAKE_PIN(P7, 7); //
-MAKE_PIN(P8, 8); //
-MAKE_PIN(P9, 9); //
-MAKE_PIN(P10, 10); //
-MAKE_PIN(P11, 11); //
-MAKE_PIN(P12, 12); //
-MAKE_PIN(P13, 13); //
-
-#undef MAKE_PIN
-
-#else
-#error "Please define board in avrpins.h"
-
-#endif
-
-#endif //_avrpins_h_
diff --git a/lib/usbhost/USB_Host_Shield_2.0/cdc_XR21B1411.cpp b/lib/usbhost/USB_Host_Shield_2.0/cdc_XR21B1411.cpp
deleted file mode 100644
index 74df8c3bdd..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/cdc_XR21B1411.cpp
+++ /dev/null
@@ -1,211 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#include "cdc_XR21B1411.h"
-
-XR21B1411::XR21B1411(USB *p, CDCAsyncOper *pasync) :
-ACM(p, pasync) {
-        // Is this needed??
-        _enhanced_status = enhanced_features(); // Set up features
-}
-
-uint8_t XR21B1411::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        const uint8_t constBufSize = sizeof (USB_DEVICE_DESCRIPTOR);
-
-        uint8_t buf[constBufSize];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint8_t num_of_conf; // number of configurations
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-
-        USBTRACE("XR Init\r\n");
-
-        if(bAddress)
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        if(!p->epinfo) {
-                USBTRACE("epinfo\r\n");
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, constBufSize, (uint8_t*)buf);
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from the device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                USBTRACE2("setAddr:", rcode);
-                return rcode;
-        }
-
-        USBTRACE2("Addr:", bAddress);
-
-        p->lowspeed = false;
-
-        p = addrPool.GetUsbDevicePtr(bAddress);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        num_of_conf = udd->bNumConfigurations;
-
-        if((((udd->idVendor != 0x2890U) || (udd->idProduct != 0x0201U)) && ((udd->idVendor != 0x04e2U) || (udd->idProduct != 0x1411U))))
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        USBTRACE2("NC:", num_of_conf);
-
-        for(uint8_t i = 0; i < num_of_conf; i++) {
-                ConfigDescParser< USB_CLASS_COM_AND_CDC_CTRL,
-                        CDC_SUBCLASS_ACM,
-                        CDC_PROTOCOL_ITU_T_V_250,
-                        CP_MASK_COMPARE_CLASS |
-                        CP_MASK_COMPARE_SUBCLASS |
-                        CP_MASK_COMPARE_PROTOCOL > CdcControlParser(this);
-
-                ConfigDescParser<USB_CLASS_CDC_DATA, 0, 0,
-                        CP_MASK_COMPARE_CLASS> CdcDataParser(this);
-
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &CdcControlParser);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &CdcDataParser);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                if(bNumEP > 1)
-                        break;
-        } // for
-
-        if(bNumEP < 4)
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, bNumEP, epInfo);
-
-        USBTRACE2("Conf:", bConfNum);
-
-        // Set Configuration Value
-        rcode = pUsb->setConf(bAddress, 0, bConfNum);
-
-        if(rcode)
-                goto FailSetConfDescr;
-
-        // Set up features status
-        _enhanced_status = enhanced_features();
-        half_duplex(false);
-        autoflowRTS(false);
-        autoflowDSR(false);
-        autoflowXON(false);
-        wide(false); // Always false, because this is only available in custom mode.
-
-        rcode = pAsync->OnInit(this);
-
-        if(rcode)
-                goto FailOnInit;
-
-        USBTRACE("XR configured\r\n");
-
-        ready = true;
-
-        //bPollEnable = true;
-
-        //USBTRACE("Poll enabled\r\n");
-        return 0;
-
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailGetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetConfDescr();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-        goto Fail;
-#endif
-
-FailOnInit:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("OnInit:");
-#endif
-
-#ifdef DEBUG_USB_HOST
-Fail:
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/cdc_XR21B1411.h b/lib/usbhost/USB_Host_Shield_2.0/cdc_XR21B1411.h
deleted file mode 100644
index c32627544f..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/cdc_XR21B1411.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/* Copyright (C) 2015 Andrew J. Kroll
-   and
-   Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(__CDC_XR21B1411_H__)
-#define __CDC_XR21B1411_H__
-
-#include "cdcacm.h"
-
-#define XR_REG_CUSTOM_DRIVER                    (0x020DU) // DRIVER SELECT
-#define XR_REG_CUSTOM_DRIVER_ACTIVE             (0x0001U) // 0: CDC 1: CUSTOM
-
-#define XR_REG_ACM_FLOW_CTL                     (0x0216U) // FLOW CONTROL REGISTER CDCACM MODE
-#define XR_REG_FLOW_CTL                         (0x0C06U) // FLOW CONTROL REGISTER CUSTOM MODE
-#define XR_REG_FLOW_CTL_HALF_DPLX               (0x0008U) // 0:FULL DUPLEX 1:HALF DUPLEX
-#define XR_REG_FLOW_CTL_MODE_MASK               (0x0007U) // MODE BITMASK
-#define XR_REG_FLOW_CTL_NONE                    (0x0000U) // NO FLOW CONTROL
-#define XR_REG_FLOW_CTL_HW                      (0x0001U) // HARDWARE FLOW CONTROL
-#define XR_REG_FLOW_CTL_SW                      (0x0002U) // SOFTWARE FLOW CONTROL
-#define XR_REG_FLOW_CTL_MMMRX                   (0x0003U) // MULTIDROP RX UPON ADDRESS MATCH
-#define XR_REG_FLOW_CTL_MMMRXTX                 (0x0004U) // MULTIDROP RX/TX UPON ADDRESS MATCH
-
-#define XR_REG_ACM_GPIO_MODE                    (0x0217U) // GPIO MODE REGISTER IN CDCACM MODE
-#define XR_REG_GPIO_MODE                        (0x0C0CU) // GPIO MODE REGISTER IN CUSTOM MODE
-#define XR_REG_GPIO_MODE_GPIO                   (0x0000U) // ALL GPIO PINS ACM PROGRAMMABLE
-#define XR_REG_GPIO_MODE_FC_RTSCTS              (0x0001U) // AUTO RTSCTS HW FC (GPIO 4/5)
-#define XR_REG_GPIO_MODE_FC_DTRDSR              (0x0002U) // AUTO DTRDSR HW FC (GPIO 2/3)
-#define XR_REG_GPIO_MODE_ATE                    (0x0003U) // AUTO TRANSCEIVER ENABLE DURING TX (GPIO 5)
-#define XR_REG_GPIO_MODE_ATE_ADDRESS            (0x0004U) // AUTO TRANSCEIVER ENABLE ON ADDRESS MATCH (GPIO 5)
-
-#define XR_REG_ACM_GPIO_DIR                     (0x0218U) // GPIO DIRECTION REGISTER CDCACM MODE, 0:IN 1:OUT
-#define XR_REG_GPIO_DIR                         (0x0C0DU) // GPIO DIRECTION REGISTER CUSTOM MODE, 0:IN 1:OUT
-
-#define XR_REG_ACM_GPIO_INT                     (0x0219U) // GPIO PIN CHANGE INTERRUPT ENABLE CDCACM MODE, 0: ENABLED 1: DISABLED
-#define XR_REG_GPIO_INT                         (0x0C11U) // GPIO PIN CHANGE INTERRUPT ENABLE CUSTOM MODE, 0: ENABLED 1: DISABLED
-#define XR_REG_GPIO_MASK                        (0x001FU) // GPIO REGISTERS BITMASK
-
-#define XR_REG_UART_ENABLE                      (0x0C00U) // UART I/O ENABLE REGISTER
-#define XR_REG_UART_ENABLE_RX                   (0x0002U) // 0:DISABLED 1:ENABLED
-#define XR_REG_UART_ENABLE_TX                   (0x0001U) // 0:DISABLED 1:ENABLED
-
-#define XR_REG_ERROR_STATUS                     (0x0C09U) // ERROR STATUS REGISTER
-#define XR_REG_ERROR_STATUS_MASK                (0x00F8U) // ERROR STATUS BITMASK
-#define XR_REG_ERROR_STATUS_ERROR               (0x0078U) // ERROR STATUS ERROR BITMASK
-#define XR_REG_ERROR_STATUS_BREAK               (0x0008U) // BREAK ERROR HAS BEEN DETECTED
-#define XR_REG_ERROR_STATUS_FRAME               (0x0010U) // FRAMING ERROR HAS BEEN DETECTED
-#define XR_REG_ERROR_STATUS_PARITY              (0x0020U) // PARITY ERROR HAS BEEN DETECTED
-#define XR_REG_ERROR_STATUS_OVERRUN             (0x0040U) // RX OVERRUN ERROR HAS BEEN DETECTED
-#define XR_REG_ERROR_STATUS_BREAK_STATUS        (0x0080U) // BREAK CONDITION IS CURRENTLY BEING DETECTED
-
-#define XR_REG_TX_BREAK                         (0x0C0AU) // TRANSMIT BREAK. 0X0001-0XFFE TIME IN MS, 0X0000 STOP, 0X0FFF BREAK ON
-
-#define XR_REG_XCVR_EN_DELAY                    (0x0C0BU) // TURN-ARROUND DELAY IN BIT-TIMES 0X0000-0X000F
-
-#define XR_REG_GPIO_SET                         (0x0C0EU) // 1:SET GPIO PIN
-
-#define XR_REG_GPIO_CLR                         (0x0C0FU) // 1:CLEAR GPIO PIN
-
-#define XR_REG_GPIO_STATUS                      (0x0C10U) // READ GPIO PINS
-
-#define XR_REG_CUSTOMISED_INT                   (0x0C12U) // 0:STANDARD 1:CUSTOM SEE DATA SHEET
-
-#define XR_REG_PIN_PULLUP_ENABLE                (0x0C14U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
-
-#define XR_REG_PIN_PULLDOWN_ENABLE              (0x0C15U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
-
-#define XR_REG_LOOPBACK                         (0x0C16U) // 0:DISABLE 1:ENABLE, SEE DATA SHEET
-
-#define XR_REG_RX_FIFO_LATENCY                  (0x0CC2U) // FIFO LATENCY REGISTER
-#define XR_REG_RX_FIFO_LATENCY_ENABLE           (0x0001U) //
-
-#define XR_REG_WIDE_MODE                        (0x0D02U)
-#define XR_REG_WIDE_MODE_ENABLE                 (0x0001U)
-
-#define XR_REG_XON_CHAR                         (0x0C07U)
-#define XR_REG_XOFF_CHAR                        (0x0C08U)
-
-#define XR_REG_TX_FIFO_RESET                    (0x0C80U) // 1: RESET, SELF-CLEARING
-#define XR_REG_TX_FIFO_COUNT                    (0x0C81U) // READ-ONLY
-#define XR_REG_RX_FIFO_RESET                    (0x0CC0U) // 1: RESET, SELF-CLEARING
-#define XR_REG_RX_FIFO_COUNT                    (0x0CC1U) // READ-ONLY
-
-#define XR_WRITE_REQUEST_TYPE                   (0x40U)
-
-#define XR_READ_REQUEST_TYPE                    (0xC0U)
-
-#define XR_MAX_ENDPOINTS                        4
-
-class XR21B1411 : public ACM {
-protected:
-
-public:
-        XR21B1411(USB *pusb, CDCAsyncOper *pasync);
-
-        /**
-         * Used by the USB core to check what this driver support.
-         * @param  vid The device's VID.
-         * @param  pid The device's PID.
-         * @return     Returns true if the device's VID and PID matches this driver.
-         */
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return (((vid == 0x2890U) && (pid == 0x0201U)) || ((vid == 0x04e2U) && (pid == 0x1411U)));
-        };
-
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-
-        virtual tty_features enhanced_features(void) {
-                tty_features rv;
-                rv.enhanced = true;
-                rv.autoflow_RTS = true;
-                rv.autoflow_DSR = true;
-                rv.autoflow_XON = true;
-                rv.half_duplex = true;
-                rv.wide = true;
-                return rv;
-        };
-
-        uint8_t read_register(uint16_t reg, uint16_t *val) {
-                return (pUsb->ctrlReq(bAddress, 0, XR_READ_REQUEST_TYPE, 1, 0, 0, reg, 2, 2, (uint8_t *)val, NULL));
-        }
-
-        uint8_t write_register(uint16_t reg, uint16_t val) {
-                return (pUsb->ctrlReq(bAddress, 0, XR_WRITE_REQUEST_TYPE, 0, BGRAB0(val), BGRAB1(val), reg, 0, 0, NULL, NULL));
-        }
-
-
-        ////////////////////////////////////////////////////////////////////////
-        // The following methods set the CDC-ACM defaults.
-        ////////////////////////////////////////////////////////////////////////
-
-        virtual void autoflowRTS(bool s) {
-                uint16_t val;
-                uint8_t rval;
-                rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
-                if(!rval) {
-                        if(s) {
-                                val &= XR_REG_FLOW_CTL_HALF_DPLX;
-                                val |= XR_REG_FLOW_CTL_HW;
-                        } else {
-                                val &= XR_REG_FLOW_CTL_HALF_DPLX;
-                        }
-                        rval = write_register(XR_REG_ACM_FLOW_CTL, val);
-                        if(!rval) {
-                                rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
-                                if(!rval) {
-                                        // ACM commands apply the new settings.
-                                        LINE_CODING LCT;
-                                        rval = GetLineCoding(&LCT);
-                                        if(!rval) {
-                                                rval = SetLineCoding(&LCT);
-                                                if(!rval) {
-                                                        _enhanced_status.autoflow_XON = false;
-                                                        _enhanced_status.autoflow_DSR = false;
-                                                        _enhanced_status.autoflow_RTS = s;
-                                                }
-                                        }
-                                }
-                        }
-                }
-        };
-
-        virtual void autoflowDSR(bool s) {
-                uint16_t val;
-                uint8_t rval;
-                rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
-                if(!rval) {
-                        if(s) {
-                                val &= XR_REG_FLOW_CTL_HALF_DPLX;
-                                val |= XR_REG_FLOW_CTL_HW;
-                        } else {
-                                val &= XR_REG_FLOW_CTL_HALF_DPLX;
-                        }
-                        rval = write_register(XR_REG_ACM_FLOW_CTL, val);
-                        if(!rval) {
-                                if(s) {
-                                        rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_FC_DTRDSR);
-                                } else {
-                                        rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
-                                }
-                                if(!rval) {
-                                        // ACM commands apply the new settings.
-                                        LINE_CODING LCT;
-                                        rval = GetLineCoding(&LCT);
-                                        if(!rval) {
-                                                rval = SetLineCoding(&LCT);
-                                                if(!rval) {
-                                                        _enhanced_status.autoflow_XON = false;
-                                                        _enhanced_status.autoflow_RTS = false;
-                                                        _enhanced_status.autoflow_DSR = s;
-                                                }
-                                        }
-                                }
-                        }
-                }
-        };
-
-        virtual void autoflowXON(bool s) {
-                // NOTE: hardware defaults to the normal XON/XOFF
-                uint16_t val;
-                uint8_t rval;
-                rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
-                if(!rval) {
-                        if(s) {
-                                val &= XR_REG_FLOW_CTL_HALF_DPLX;
-                                val |= XR_REG_FLOW_CTL_SW;
-                        } else {
-                                val &= XR_REG_FLOW_CTL_HALF_DPLX;
-                        }
-                        rval = write_register(XR_REG_ACM_FLOW_CTL, val);
-                        if(!rval) {
-                                rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
-                                if(!rval) {
-                                        // ACM commands apply the new settings.
-                                        LINE_CODING LCT;
-                                        rval = GetLineCoding(&LCT);
-                                        if(!rval) {
-                                                rval = SetLineCoding(&LCT);
-                                                if(!rval) {
-                                                        _enhanced_status.autoflow_RTS = false;
-                                                        _enhanced_status.autoflow_DSR = false;
-                                                        _enhanced_status.autoflow_XON = s;
-                                                }
-                                        }
-                                }
-                        }
-                }
-        };
-
-        virtual void half_duplex(bool s) {
-                uint16_t val;
-                uint8_t rval;
-                rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
-                if(!rval) {
-                        if(s) {
-                                val |= XR_REG_FLOW_CTL_HALF_DPLX;
-                        } else {
-                                val &= XR_REG_FLOW_CTL_MODE_MASK;
-                        }
-                        rval = write_register(XR_REG_ACM_FLOW_CTL, val);
-                        if(!rval) {
-                                // ACM commands apply the new settings.
-                                LINE_CODING LCT;
-                                rval = GetLineCoding(&LCT);
-                                if(!rval) {
-                                        rval = SetLineCoding(&LCT);
-                                        if(!rval) {
-                                                _enhanced_status.half_duplex = s;
-                                        }
-                                }
-                        }
-                }
-        };
-
-
-
-};
-
-#endif // __CDCPROLIFIC_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/cdcacm.cpp b/lib/usbhost/USB_Host_Shield_2.0/cdcacm.cpp
deleted file mode 100644
index 2cd2c9a82d..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/cdcacm.cpp
+++ /dev/null
@@ -1,331 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#include "cdcacm.h"
-
-const uint8_t ACM::epDataInIndex = 1;
-const uint8_t ACM::epDataOutIndex = 2;
-const uint8_t ACM::epInterruptInIndex = 3;
-
-ACM::ACM(USB *p, CDCAsyncOper *pasync) :
-pUsb(p),
-pAsync(pasync),
-bAddress(0),
-bControlIface(0),
-bDataIface(0),
-bNumEP(1),
-qNextPollTime(0),
-bPollEnable(false),
-ready(false) {
-        _enhanced_status = enhanced_features(); // Set up features
-        for(uint8_t i = 0; i < ACM_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i == epDataInIndex) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-
-        }
-        if(pUsb)
-                pUsb->RegisterDeviceClass(this);
-}
-
-uint8_t ACM::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-
-        const uint8_t constBufSize = sizeof (USB_DEVICE_DESCRIPTOR);
-
-        uint8_t buf[constBufSize];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint8_t num_of_conf; // number of configurations
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-
-        USBTRACE("ACM Init\r\n");
-
-        if(bAddress)
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        if(!p->epinfo) {
-                USBTRACE("epinfo\r\n");
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, constBufSize, (uint8_t*)buf);
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from the device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                USBTRACE2("setAddr:", rcode);
-                return rcode;
-        }
-
-        USBTRACE2("Addr:", bAddress);
-
-        p->lowspeed = false;
-
-        p = addrPool.GetUsbDevicePtr(bAddress);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        num_of_conf = udd->bNumConfigurations;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        USBTRACE2("NC:", num_of_conf);
-
-        for(uint8_t i = 0; i < num_of_conf; i++) {
-                ConfigDescParser< USB_CLASS_COM_AND_CDC_CTRL,
-                        CDC_SUBCLASS_ACM,
-                        CDC_PROTOCOL_ITU_T_V_250,
-                        CP_MASK_COMPARE_CLASS |
-                        CP_MASK_COMPARE_SUBCLASS |
-                        CP_MASK_COMPARE_PROTOCOL > CdcControlParser(this);
-
-                ConfigDescParser<USB_CLASS_CDC_DATA, 0, 0,
-                        CP_MASK_COMPARE_CLASS> CdcDataParser(this);
-
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &CdcControlParser);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &CdcDataParser);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                if(bNumEP > 1)
-                        break;
-        } // for
-
-        if(bNumEP < 4)
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, bNumEP, epInfo);
-
-        USBTRACE2("Conf:", bConfNum);
-
-        // Set Configuration Value
-        rcode = pUsb->setConf(bAddress, 0, bConfNum);
-
-        if(rcode)
-                goto FailSetConfDescr;
-
-        // Set up features status
-        _enhanced_status = enhanced_features();
-        half_duplex(false);
-        autoflowRTS(false);
-        autoflowDSR(false);
-        autoflowXON(false);
-        wide(false); // Always false, because this is only available in custom mode.
-        rcode = pAsync->OnInit(this);
-
-        if(rcode)
-                goto FailOnInit;
-
-        USBTRACE("ACM configured\r\n");
-
-        ready = true;
-
-        //bPollEnable = true;
-
-        //USBTRACE("Poll enabled\r\n");
-        return 0;
-
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailGetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetConfDescr();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-        goto Fail;
-#endif
-
-FailOnInit:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("OnInit:");
-#endif
-
-#ifdef DEBUG_USB_HOST
-Fail:
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-void ACM::EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *pep) {
-        //ErrorMessage<uint8_t > (PSTR("Conf.Val"), conf);
-        //ErrorMessage<uint8_t > (PSTR("Iface Num"), iface);
-        //ErrorMessage<uint8_t > (PSTR("Alt.Set"), alt);
-
-        bConfNum = conf;
-
-        uint8_t index;
-
-        if((pep->bmAttributes & 0x03) == 3 && (pep->bEndpointAddress & 0x80) == 0x80)
-                index = epInterruptInIndex;
-        else
-                if((pep->bmAttributes & 0x02) == 2)
-                index = ((pep->bEndpointAddress & 0x80) == 0x80) ? epDataInIndex : epDataOutIndex;
-        else
-                return;
-
-        // Fill in the endpoint info structure
-        epInfo[index].epAddr = (pep->bEndpointAddress & 0x0F);
-        epInfo[index].maxPktSize = (uint8_t)pep->wMaxPacketSize;
-        epInfo[index].epAttribs = 0;
-
-        bNumEP++;
-
-        PrintEndpointDescriptor(pep);
-}
-
-uint8_t ACM::Release() {
-        ready = false;
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-
-        bControlIface = 0;
-        bDataIface = 0;
-        bNumEP = 1;
-
-        bAddress = 0;
-        qNextPollTime = 0;
-        bPollEnable = false;
-        return 0;
-}
-
-uint8_t ACM::Poll() {
-        uint8_t rcode = 0;
-
-        if(!bPollEnable)
-                return 0;
-
-        return rcode;
-}
-
-uint8_t ACM::RcvData(uint16_t *bytes_rcvd, uint8_t *dataptr) {
-        return pUsb->inTransfer(bAddress, epInfo[epDataInIndex].epAddr, bytes_rcvd, dataptr);
-}
-
-uint8_t ACM::SndData(uint16_t nbytes, uint8_t *dataptr) {
-        return pUsb->outTransfer(bAddress, epInfo[epDataOutIndex].epAddr, nbytes, dataptr);
-}
-
-uint8_t ACM::SetCommFeature(uint16_t fid, uint8_t nbytes, uint8_t *dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_CDCOUT, CDC_SET_COMM_FEATURE, (fid & 0xff), (fid >> 8), bControlIface, nbytes, nbytes, dataptr, NULL));
-}
-
-uint8_t ACM::GetCommFeature(uint16_t fid, uint8_t nbytes, uint8_t *dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_CDCIN, CDC_GET_COMM_FEATURE, (fid & 0xff), (fid >> 8), bControlIface, nbytes, nbytes, dataptr, NULL));
-}
-
-uint8_t ACM::ClearCommFeature(uint16_t fid) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_CDCOUT, CDC_CLEAR_COMM_FEATURE, (fid & 0xff), (fid >> 8), bControlIface, 0, 0, NULL, NULL));
-}
-
-uint8_t ACM::SetLineCoding(const LINE_CODING *dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_CDCOUT, CDC_SET_LINE_CODING, 0x00, 0x00, bControlIface, sizeof (LINE_CODING), sizeof (LINE_CODING), (uint8_t*)dataptr, NULL));
-}
-
-uint8_t ACM::GetLineCoding(LINE_CODING *dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_CDCIN, CDC_GET_LINE_CODING, 0x00, 0x00, bControlIface, sizeof (LINE_CODING), sizeof (LINE_CODING), (uint8_t*)dataptr, NULL));
-}
-
-uint8_t ACM::SetControlLineState(uint8_t state) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_CDCOUT, CDC_SET_CONTROL_LINE_STATE, state, 0, bControlIface, 0, 0, NULL, NULL));
-}
-
-uint8_t ACM::SendBreak(uint16_t duration) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_CDCOUT, CDC_SEND_BREAK, (duration & 0xff), (duration >> 8), bControlIface, 0, 0, NULL, NULL));
-}
-
-void ACM::PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr) {
-        Notify(PSTR("Endpoint descriptor:"), 0x80);
-        Notify(PSTR("\r\nLength:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bLength, 0x80);
-        Notify(PSTR("\r\nType:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bDescriptorType, 0x80);
-        Notify(PSTR("\r\nAddress:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bEndpointAddress, 0x80);
-        Notify(PSTR("\r\nAttributes:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bmAttributes, 0x80);
-        Notify(PSTR("\r\nMaxPktSize:\t"), 0x80);
-        D_PrintHex<uint16_t > (ep_ptr->wMaxPacketSize, 0x80);
-        Notify(PSTR("\r\nPoll Intrv:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bInterval, 0x80);
-        Notify(PSTR("\r\n"), 0x80);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/cdcacm.h b/lib/usbhost/USB_Host_Shield_2.0/cdcacm.h
deleted file mode 100644
index 2a38524d8c..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/cdcacm.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(__CDCACM_H__)
-#define __CDCACM_H__
-
-#include "Usb.h"
-
-#define bmREQ_CDCOUT                    USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
-#define bmREQ_CDCIN                     USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
-
-// CDC Subclass Constants
-#define CDC_SUBCLASS_DLCM               0x01    // Direct Line Control Model
-#define CDC_SUBCLASS_ACM                0x02    // Abstract Control Model
-#define CDC_SUBCLASS_TCM                0x03    // Telephone Control Model
-#define CDC_SUBCLASS_MCCM               0x04    // Multi Channel Control Model
-#define CDC_SUBCLASS_CAPI               0x05    // CAPI Control Model
-#define CDC_SUBCLASS_ETHERNET           0x06    // Ethernet Network Control Model
-#define CDC_SUBCLASS_ATM                0x07    // ATM Network Control Model
-#define CDC_SUBCLASS_WIRELESS_HANDSET   0x08    // Wireless Handset Control Model
-#define CDC_SUBCLASS_DEVICE_MANAGEMENT  0x09    // Device Management
-#define CDC_SUBCLASS_MOBILE_DIRECT_LINE 0x0A    // Mobile Direct Line Model
-#define CDC_SUBCLASS_OBEX               0x0B    // OBEX
-#define CDC_SUBCLASS_ETHERNET_EMU       0x0C    // Ethernet Emulation Model
-
-// Communication Interface Class Control Protocol Codes
-#define CDC_PROTOCOL_ITU_T_V_250        0x01    // AT Commands defined by ITU-T V.250
-#define CDC_PROTOCOL_PCCA_101           0x02    // AT Commands defined by PCCA-101
-#define CDC_PROTOCOL_PCCA_101_O         0x03    // AT Commands defined by PCCA-101 & Annex O
-#define CDC_PROTOCOL_GSM_7_07           0x04    // AT Commands defined by GSM 7.07
-#define CDC_PROTOCOL_3GPP_27_07         0x05    // AT Commands defined by 3GPP 27.007
-#define CDC_PROTOCOL_C_S0017_0          0x06    // AT Commands defined by TIA for CDMA
-#define CDC_PROTOCOL_USB_EEM            0x07    // Ethernet Emulation Model
-
-// CDC Commands defined by CDC 1.2
-#define CDC_SEND_ENCAPSULATED_COMMAND   0x00
-#define CDC_GET_ENCAPSULATED_RESPONSE   0x01
-
-// CDC Commands defined by PSTN 1.2
-#define CDC_SET_COMM_FEATURE            0x02
-#define CDC_GET_COMM_FEATURE            0x03
-#define CDC_CLEAR_COMM_FEATURE          0x04
-#define CDC_SET_AUX_LINE_STATE          0x10
-#define CDC_SET_HOOK_STATE              0x11
-#define CDC_PULSE_SETUP                 0x12
-#define CDC_SEND_PULSE                  0x13
-#define CDC_SET_PULSE_TIME              0x14
-#define CDC_RING_AUX_JACK               0x15
-#define CDC_SET_LINE_CODING             0x20
-#define CDC_GET_LINE_CODING             0x21
-#define CDC_SET_CONTROL_LINE_STATE      0x22
-#define CDC_SEND_BREAK                  0x23
-#define CDC_SET_RINGER_PARMS            0x30
-#define CDC_GET_RINGER_PARMS            0x31
-#define CDC_SET_OPERATION_PARMS         0x32
-#define CDC_GET_OPERATION_PARMS         0x33
-#define CDC_SET_LINE_PARMS              0x34
-#define CDC_GET_LINE_PARMS              0x35
-#define CDC_DIAL_DIGITS                 0x36
-
-//Class-Specific Notification Codes
-#define NETWORK_CONNECTION              0x00
-#define RESPONSE_AVAILABLE              0x01
-#define AUX_JACK_HOOK_STATE             0x08
-#define RING_DETECT                     0x09
-#define SERIAL_STATE                    0x20
-#define CALL_STATE_CHANGE               0x28
-#define LINE_STATE_CHANGE               0x29
-#define CONNECTION_SPEED_CHANGE         0x2a
-
-// CDC Functional Descriptor Structures
-
-typedef struct {
-        uint8_t bFunctionLength;
-        uint8_t bDescriptorType;
-        uint8_t bDescriptorSubtype;
-        uint8_t bmCapabilities;
-        uint8_t bDataInterface;
-} CALL_MGMNT_FUNC_DESCR;
-
-typedef struct {
-        uint8_t bFunctionLength;
-        uint8_t bDescriptorType;
-        uint8_t bDescriptorSubtype;
-        uint8_t bmCapabilities;
-} ACM_FUNC_DESCR, DLM_FUNC_DESCR, TEL_OPER_MODES_FUNC_DESCR,
-TEL_CALL_STATE_REP_CPBL_FUNC_DESCR;
-
-typedef struct {
-        uint8_t bFunctionLength;
-        uint8_t bDescriptorType;
-        uint8_t bDescriptorSubtype;
-        uint8_t bRingerVolSteps;
-        uint8_t bNumRingerPatterns;
-} TEL_RINGER_FUNC_DESCR;
-
-typedef struct {
-        uint32_t dwDTERate; // Data Terminal Rate in bits per second
-        uint8_t bCharFormat; // 0 - 1 stop bit, 1 - 1.5 stop bits, 2 - 2 stop bits
-        uint8_t bParityType; // 0 - None, 1 - Odd, 2 - Even, 3 - Mark, 4 - Space
-        uint8_t bDataBits; // Data bits (5, 6, 7, 8 or 16)
-} LINE_CODING;
-
-typedef struct {
-        uint8_t bmRequestType; // 0xa1 for class-specific notifications
-        uint8_t bNotification;
-        uint16_t wValue;
-        uint16_t wIndex;
-        uint16_t wLength;
-        uint16_t bmState; //UART state bitmap for SERIAL_STATE, other notifications variable length
-} CLASS_NOTIFICATION;
-
-class ACM;
-
-class CDCAsyncOper {
-public:
-
-        virtual uint8_t OnInit(ACM *pacm) {
-                return 0;
-        };
-        //virtual void OnDataRcvd(ACM *pacm, uint8_t nbytes, uint8_t *dataptr) = 0;
-        //virtual void OnDisconnected(ACM *pacm) = 0;
-};
-
-/**
- * This structure is used to report the extended capabilities of the connected device.
- * It is also used to report the current status.
- * Regular CDC-ACM reports all as false.
- */
-typedef struct {
-
-        union {
-                uint8_t tty;
-
-                struct {
-                        bool enhanced : 1; // Do we have the ability to set/clear any features?
-                        // Status and 8th bit in data stream.
-                        // Presence only indicates feature is available, but this isn't used for CDC-ACM.
-                        bool wide : 1;
-                        bool autoflow_RTS : 1; // Has autoflow on RTS/CTS
-                        bool autoflow_DSR : 1; // Has autoflow on DTR/DSR
-                        bool autoflow_XON : 1; // Has autoflow  XON/XOFF
-                        bool half_duplex : 1;  // Has half-duplex capability.
-                } __attribute__((packed));
-        };
-} tty_features;
-
-#define ACM_MAX_ENDPOINTS               4
-
-class ACM : public USBDeviceConfig, public UsbConfigXtracter {
-protected:
-        static const uint8_t epDataInIndex; // DataIn endpoint index
-        static const uint8_t epDataOutIndex; // DataOUT endpoint index
-        static const uint8_t epInterruptInIndex; // InterruptIN  endpoint index
-
-        USB *pUsb;
-        CDCAsyncOper *pAsync;
-        uint8_t bAddress;
-        uint8_t bConfNum; // configuration number
-        uint8_t bControlIface; // Control interface value
-        uint8_t bDataIface; // Data interface value
-        uint8_t bNumEP; // total number of EP in the configuration
-        uint32_t qNextPollTime; // next poll time
-        volatile bool bPollEnable; // poll enable flag
-        volatile bool ready; //device ready indicator
-        tty_features _enhanced_status; // current status
-
-        EpInfo epInfo[ACM_MAX_ENDPOINTS];
-
-        void PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr);
-
-public:
-        ACM(USB *pusb, CDCAsyncOper *pasync);
-
-        uint8_t SetCommFeature(uint16_t fid, uint8_t nbytes, uint8_t *dataptr);
-        uint8_t GetCommFeature(uint16_t fid, uint8_t nbytes, uint8_t *dataptr);
-        uint8_t ClearCommFeature(uint16_t fid);
-        uint8_t SetLineCoding(const LINE_CODING *dataptr);
-        uint8_t GetLineCoding(LINE_CODING *dataptr);
-        uint8_t SetControlLineState(uint8_t state);
-        uint8_t SendBreak(uint16_t duration);
-        uint8_t GetNotif(uint16_t *bytes_rcvd, uint8_t *dataptr);
-
-        // Methods for receiving and sending data
-        uint8_t RcvData(uint16_t *nbytesptr, uint8_t *dataptr);
-        uint8_t SndData(uint16_t nbytes, uint8_t *dataptr);
-
-        // USBDeviceConfig implementation
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t Release();
-        uint8_t Poll();
-
-        bool available(void) {
-                return false;
-        };
-
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        virtual bool isReady() {
-                return ready;
-        };
-
-        virtual tty_features enhanced_status(void) {
-                return _enhanced_status;
-        };
-
-        virtual tty_features enhanced_features(void) {
-                tty_features rv;
-                rv.enhanced = false;
-                rv.autoflow_RTS = false;
-                rv.autoflow_DSR = false;
-                rv.autoflow_XON = false;
-                rv.half_duplex = false;
-                rv.wide = false;
-                return rv;
-        };
-
-        virtual void autoflowRTS(bool s) {
-        };
-
-        virtual void autoflowDSR(bool s) {
-        };
-
-        virtual void autoflowXON(bool s) {
-        };
-
-        virtual void half_duplex(bool s) {
-        };
-
-        virtual void wide(bool s) {
-        };
-
-        // UsbConfigXtracter implementation
-        void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep);
-};
-
-#endif // __CDCACM_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/cdcftdi.cpp b/lib/usbhost/USB_Host_Shield_2.0/cdcftdi.cpp
deleted file mode 100644
index 80d21d16ec..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/cdcftdi.cpp
+++ /dev/null
@@ -1,334 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#include "cdcftdi.h"
-
-const uint8_t FTDI::epDataInIndex = 1;
-const uint8_t FTDI::epDataOutIndex = 2;
-const uint8_t FTDI::epInterruptInIndex = 3;
-
-FTDI::FTDI(USB *p, FTDIAsyncOper *pasync) :
-pAsync(pasync),
-pUsb(p),
-bAddress(0),
-bNumEP(1),
-wFTDIType(0) {
-        for(uint8_t i = 0; i < FTDI_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i==epDataInIndex) ? USB_NAK_NOWAIT: USB_NAK_MAX_POWER;
-        }
-        if(pUsb)
-                pUsb->RegisterDeviceClass(this);
-}
-
-uint8_t FTDI::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        const uint8_t constBufSize = sizeof (USB_DEVICE_DESCRIPTOR);
-
-        uint8_t buf[constBufSize];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-
-        uint8_t num_of_conf; // number of configurations
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-
-        USBTRACE("FTDI Init\r\n");
-
-        if(bAddress)
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        if(!p->epinfo) {
-                USBTRACE("epinfo\r\n");
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, sizeof (USB_DEVICE_DESCRIPTOR), buf);
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode)
-                goto FailGetDevDescr;
-        if(udd->idVendor != FTDI_VID || udd->idProduct != FTDI_PID)
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        // Save type of FTDI chip
-        wFTDIType = udd->bcdDevice;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from the device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                USBTRACE2("setAddr:", rcode);
-                return rcode;
-        }
-
-        USBTRACE2("Addr:", bAddress);
-
-        p->lowspeed = false;
-
-        p = addrPool.GetUsbDevicePtr(bAddress);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        num_of_conf = udd->bNumConfigurations;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        USBTRACE2("NC:", num_of_conf);
-
-        for(uint8_t i = 0; i < num_of_conf; i++) {
-                HexDumper<USBReadParser, uint16_t, uint16_t> HexDump;
-                ConfigDescParser < 0xFF, 0xFF, 0xFF, CP_MASK_COMPARE_ALL> confDescrParser(this);
-
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &HexDump);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &confDescrParser);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                if(bNumEP > 1)
-                        break;
-        } // for
-
-        if(bNumEP < 2)
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        USBTRACE2("NumEP:", bNumEP);
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, bNumEP, epInfo);
-
-        USBTRACE2("Conf:", bConfNum);
-
-        // Set Configuration Value
-        rcode = pUsb->setConf(bAddress, 0, bConfNum);
-
-        if(rcode)
-                goto FailSetConfDescr;
-
-        rcode = pAsync->OnInit(this);
-
-        if(rcode)
-                goto FailOnInit;
-
-        USBTRACE("FTDI configured\r\n");
-
-        bPollEnable = true;
-        return 0;
-
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailGetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetConfDescr();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-        goto Fail;
-#endif
-
-FailOnInit:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("OnInit:");
-
-Fail:
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-void FTDI::EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *pep) {
-        ErrorMessage<uint8_t > (PSTR("Conf.Val"), conf);
-        ErrorMessage<uint8_t > (PSTR("Iface Num"), iface);
-        ErrorMessage<uint8_t > (PSTR("Alt.Set"), alt);
-
-        bConfNum = conf;
-
-        uint8_t index;
-
-        if((pep->bmAttributes & 0x03) == 3 && (pep->bEndpointAddress & 0x80) == 0x80)
-                index = epInterruptInIndex;
-        else
-                if((pep->bmAttributes & 0x02) == 2)
-                index = ((pep->bEndpointAddress & 0x80) == 0x80) ? epDataInIndex : epDataOutIndex;
-        else
-                return;
-
-        // Fill in the endpoint info structure
-        epInfo[index].epAddr = (pep->bEndpointAddress & 0x0F);
-        epInfo[index].maxPktSize = (uint8_t)pep->wMaxPacketSize;
-        epInfo[index].epAttribs = 0;
-
-        bNumEP++;
-
-        PrintEndpointDescriptor(pep);
-}
-
-uint8_t FTDI::Release() {
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-
-        bAddress = 0;
-        bNumEP = 1;
-        qNextPollTime = 0;
-        bPollEnable = false;
-        return pAsync->OnRelease(this);
-}
-
-uint8_t FTDI::Poll() {
-        uint8_t rcode = 0;
-
-        //if (!bPollEnable)
-        //      return 0;
-
-        //if (qNextPollTime <= millis())
-        //{
-        //      USB_HOST_SERIAL.println(bAddress, HEX);
-
-        //      qNextPollTime = millis() + 100;
-        //}
-        return rcode;
-}
-
-uint8_t FTDI::SetBaudRate(uint32_t baud) {
-        uint16_t baud_value, baud_index = 0;
-        uint32_t divisor3;
-
-        divisor3 = 48000000 / 2 / baud; // divisor shifted 3 bits to the left
-
-        if(wFTDIType == FT232AM) {
-                if((divisor3 & 0x7) == 7)
-                        divisor3++; // round x.7/8 up to x+1
-
-                baud_value = divisor3 >> 3;
-                divisor3 &= 0x7;
-
-                if(divisor3 == 1) baud_value |= 0xc000;
-                else // 0.125
-                        if(divisor3 >= 4) baud_value |= 0x4000;
-                else // 0.5
-                        if(divisor3 != 0) baud_value |= 0x8000; // 0.25
-                if(baud_value == 1) baud_value = 0; /* special case for maximum baud rate */
-        } else {
-                static const unsigned char divfrac [8] = {0, 3, 2, 0, 1, 1, 2, 3};
-                static const unsigned char divindex[8] = {0, 0, 0, 1, 0, 1, 1, 1};
-
-                baud_value = divisor3 >> 3;
-                baud_value |= divfrac [divisor3 & 0x7] << 14;
-                baud_index = divindex[divisor3 & 0x7];
-
-                /* Deal with special cases for highest baud rates. */
-                if(baud_value == 1) baud_value = 0;
-                else // 1.0
-                        if(baud_value == 0x4001) baud_value = 1; // 1.5
-        }
-        USBTRACE2("baud_value:", baud_value);
-        USBTRACE2("baud_index:", baud_index);
-        return pUsb->ctrlReq(bAddress, 0, bmREQ_FTDI_OUT, FTDI_SIO_SET_BAUD_RATE, baud_value & 0xff, baud_value >> 8, baud_index, 0, 0, NULL, NULL);
-}
-
-uint8_t FTDI::SetModemControl(uint16_t signal) {
-        return pUsb->ctrlReq(bAddress, 0, bmREQ_FTDI_OUT, FTDI_SIO_MODEM_CTRL, signal & 0xff, signal >> 8, 0, 0, 0, NULL, NULL);
-}
-
-uint8_t FTDI::SetFlowControl(uint8_t protocol, uint8_t xon, uint8_t xoff) {
-        return pUsb->ctrlReq(bAddress, 0, bmREQ_FTDI_OUT, FTDI_SIO_SET_FLOW_CTRL, xon, xoff, protocol << 8, 0, 0, NULL, NULL);
-}
-
-uint8_t FTDI::SetData(uint16_t databm) {
-        return pUsb->ctrlReq(bAddress, 0, bmREQ_FTDI_OUT, FTDI_SIO_SET_DATA, databm & 0xff, databm >> 8, 0, 0, 0, NULL, NULL);
-}
-
-uint8_t FTDI::RcvData(uint16_t *bytes_rcvd, uint8_t *dataptr) {
-        return pUsb->inTransfer(bAddress, epInfo[epDataInIndex].epAddr, bytes_rcvd, dataptr);
-}
-
-uint8_t FTDI::SndData(uint16_t nbytes, uint8_t *dataptr) {
-        return pUsb->outTransfer(bAddress, epInfo[epDataOutIndex].epAddr, nbytes, dataptr);
-}
-
-void FTDI::PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr) {
-        Notify(PSTR("Endpoint descriptor:"), 0x80);
-        Notify(PSTR("\r\nLength:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bLength, 0x80);
-        Notify(PSTR("\r\nType:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bDescriptorType, 0x80);
-        Notify(PSTR("\r\nAddress:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bEndpointAddress, 0x80);
-        Notify(PSTR("\r\nAttributes:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bmAttributes, 0x80);
-        Notify(PSTR("\r\nMaxPktSize:\t"), 0x80);
-        D_PrintHex<uint16_t > (ep_ptr->wMaxPacketSize, 0x80);
-        Notify(PSTR("\r\nPoll Intrv:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bInterval, 0x80);
-        Notify(PSTR("\r\n"), 0x80);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/cdcftdi.h b/lib/usbhost/USB_Host_Shield_2.0/cdcftdi.h
deleted file mode 100644
index b731252629..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/cdcftdi.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(__CDCFTDI_H__)
-#define __CDCFTDI_H__
-
-#include "Usb.h"
-
-#define bmREQ_FTDI_OUT  0x40
-#define bmREQ_FTDI_IN   0xc0
-
-//#define bmREQ_FTDI_OUT                USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
-//#define bmREQ_FTDI_IN         USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
-
-#define FTDI_VID                        0x0403  // FTDI VID
-#define FTDI_PID                        0x6001  // FTDI PID
-
-#define FT232AM                         0x0200
-#define FT232BM                         0x0400
-#define FT2232                          0x0500
-#define FT232R                          0x0600
-
-// Commands
-#define FTDI_SIO_RESET                  0 /* Reset the port */
-#define FTDI_SIO_MODEM_CTRL             1 /* Set the modem control register */
-#define FTDI_SIO_SET_FLOW_CTRL          2 /* Set flow control register */
-#define FTDI_SIO_SET_BAUD_RATE          3 /* Set baud rate */
-#define FTDI_SIO_SET_DATA               4 /* Set the data characteristics of the port */
-#define FTDI_SIO_GET_MODEM_STATUS       5 /* Retrieve current value of modem status register */
-#define FTDI_SIO_SET_EVENT_CHAR         6 /* Set the event character */
-#define FTDI_SIO_SET_ERROR_CHAR         7 /* Set the error character */
-
-#define FTDI_SIO_RESET_SIO              0
-#define FTDI_SIO_RESET_PURGE_RX         1
-#define FTDI_SIO_RESET_PURGE_TX         2
-
-#define FTDI_SIO_SET_DATA_PARITY_NONE   (0x0 << 8 )
-#define FTDI_SIO_SET_DATA_PARITY_ODD    (0x1 << 8 )
-#define FTDI_SIO_SET_DATA_PARITY_EVEN   (0x2 << 8 )
-#define FTDI_SIO_SET_DATA_PARITY_MARK   (0x3 << 8 )
-#define FTDI_SIO_SET_DATA_PARITY_SPACE  (0x4 << 8 )
-#define FTDI_SIO_SET_DATA_STOP_BITS_1   (0x0 << 11)
-#define FTDI_SIO_SET_DATA_STOP_BITS_15  (0x1 << 11)
-#define FTDI_SIO_SET_DATA_STOP_BITS_2   (0x2 << 11)
-#define FTDI_SIO_SET_BREAK              (0x1 << 14)
-
-#define FTDI_SIO_SET_DTR_MASK           0x1
-#define FTDI_SIO_SET_DTR_HIGH           ( 1 | ( FTDI_SIO_SET_DTR_MASK  << 8))
-#define FTDI_SIO_SET_DTR_LOW            ( 0 | ( FTDI_SIO_SET_DTR_MASK  << 8))
-#define FTDI_SIO_SET_RTS_MASK           0x2
-#define FTDI_SIO_SET_RTS_HIGH           ( 2 | ( FTDI_SIO_SET_RTS_MASK << 8 ))
-#define FTDI_SIO_SET_RTS_LOW            ( 0 | ( FTDI_SIO_SET_RTS_MASK << 8 ))
-
-#define FTDI_SIO_DISABLE_FLOW_CTRL      0x0
-#define FTDI_SIO_RTS_CTS_HS             (0x1 << 8)
-#define FTDI_SIO_DTR_DSR_HS             (0x2 << 8)
-#define FTDI_SIO_XON_XOFF_HS            (0x4 << 8)
-
-#define FTDI_SIO_CTS_MASK               0x10
-#define FTDI_SIO_DSR_MASK               0x20
-#define FTDI_SIO_RI_MASK                0x40
-#define FTDI_SIO_RLSD_MASK              0x80
-
-class FTDI;
-
-class FTDIAsyncOper {
-public:
-
-        virtual uint8_t OnInit(FTDI *pftdi) {
-                return 0;
-        };
-
-        virtual uint8_t OnRelease(FTDI *pftdi) {
-                return 0;
-        };
-};
-
-
-// Only single port chips are currently supported by the library,
-//              so only three endpoints are allocated.
-#define FTDI_MAX_ENDPOINTS              3
-
-class FTDI : public USBDeviceConfig, public UsbConfigXtracter {
-        static const uint8_t epDataInIndex; // DataIn endpoint index
-        static const uint8_t epDataOutIndex; // DataOUT endpoint index
-        static const uint8_t epInterruptInIndex; // InterruptIN  endpoint index
-
-        FTDIAsyncOper *pAsync;
-        USB *pUsb;
-        uint8_t bAddress;
-        uint8_t bConfNum; // configuration number
-        uint8_t bNumIface; // number of interfaces in the configuration
-        uint8_t bNumEP; // total number of EP in the configuration
-        uint32_t qNextPollTime; // next poll time
-        bool bPollEnable; // poll enable flag
-        uint16_t wFTDIType; // Type of FTDI chip
-
-        EpInfo epInfo[FTDI_MAX_ENDPOINTS];
-
-        void PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr);
-
-public:
-        FTDI(USB *pusb, FTDIAsyncOper *pasync);
-
-        uint8_t SetBaudRate(uint32_t baud);
-        uint8_t SetModemControl(uint16_t control);
-        uint8_t SetFlowControl(uint8_t protocol, uint8_t xon = 0x11, uint8_t xoff = 0x13);
-        uint8_t SetData(uint16_t databm);
-
-        // Methods for recieving and sending data
-        uint8_t RcvData(uint16_t *bytes_rcvd, uint8_t *dataptr);
-        uint8_t SndData(uint16_t nbytes, uint8_t *dataptr);
-
-        // USBDeviceConfig implementation
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t Release();
-        uint8_t Poll();
-
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        // UsbConfigXtracter implementation
-        void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep);
-
-        virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
-                return (vid == FTDI_VID && pid == FTDI_PID);
-        }
-
-};
-
-#endif // __CDCFTDI_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/cdcprolific.cpp b/lib/usbhost/USB_Host_Shield_2.0/cdcprolific.cpp
deleted file mode 100644
index eceb1df9f3..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/cdcprolific.cpp
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#include "cdcprolific.h"
-
-PL2303::PL2303(USB *p, CDCAsyncOper *pasync) :
-ACM(p, pasync),
-wPLType(0) {
-}
-
-uint8_t PL2303::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        const uint8_t constBufSize = sizeof (USB_DEVICE_DESCRIPTOR);
-
-        uint8_t buf[constBufSize];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint8_t num_of_conf; // number of configurations
-#ifdef PL2303_COMPAT
-        enum pl2303_type pltype = unknown;
-#endif
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-
-        USBTRACE("PL Init\r\n");
-
-        if(bAddress)
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        if(!p->epinfo) {
-                USBTRACE("epinfo\r\n");
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, sizeof (USB_DEVICE_DESCRIPTOR), (uint8_t*)buf);
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        if(udd->idVendor != PL_VID && CHECK_PID(udd->idProduct))
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        /* determine chip variant */
-#ifdef PL2303_COMPAT
-        if(udd->bDeviceClass == 0x02 )
-                pltype = type_0;
-        else if(udd->bMaxPacketSize0 == 0x40 )
-                pltype = rev_HX;
-        else if(udd->bDeviceClass == 0x00)
-                pltype = type_1;
-        else if(udd->bDeviceClass == 0xff)
-                pltype = type_1;
-#endif
-
-        // Save type of PL chip
-        wPLType = udd->bcdDevice;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from the device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                USBTRACE2("setAddr:", rcode);
-                return rcode;
-        }
-
-        USBTRACE2("Addr:", bAddress);
-
-        p->lowspeed = false;
-
-        p = addrPool.GetUsbDevicePtr(bAddress);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        num_of_conf = udd->bNumConfigurations;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        USBTRACE2("NC:", num_of_conf);
-
-        for(uint8_t i = 0; i < num_of_conf; i++) {
-                HexDumper<USBReadParser, uint16_t, uint16_t> HexDump;
-                ConfigDescParser < 0xFF, 0, 0, CP_MASK_COMPARE_CLASS> confDescrParser(this);
-
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &HexDump);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &confDescrParser);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                if(bNumEP > 1)
-                        break;
-        } // for
-
-        if(bNumEP < 2)
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, bNumEP, epInfo);
-
-        USBTRACE2("Conf:", bConfNum);
-
-        // Set Configuration Value
-        rcode = pUsb->setConf(bAddress, 0, bConfNum);
-
-        if(rcode)
-                goto FailSetConfDescr;
-
-#ifdef PL2303_COMPAT
-        /* Shamanic dance - sending Prolific init data as-is */
-        vendorRead( 0x84, 0x84, 0, buf );
-        vendorWrite( 0x04, 0x04, 0 );
-        vendorRead( 0x84, 0x84, 0, buf );
-        vendorRead( 0x83, 0x83, 0, buf );
-        vendorRead( 0x84, 0x84, 0, buf );
-        vendorWrite( 0x04, 0x04, 1 );
-        vendorRead( 0x84, 0x84, 0, buf);
-        vendorRead( 0x83, 0x83, 0, buf);
-        vendorWrite( 0, 0, 1 );
-        vendorWrite( 1, 0, 0 );
-        if( pltype == rev_HX ) {
-                vendorWrite( 2, 0, 0x44 );
-                vendorWrite( 0x06, 0x06, 0 ); // From W7 init
-        }
-        else {
-                vendorWrite( 2, 0, 0x24 );
-        }
-        /* Shamanic dance end */
-#endif
-        /* Calling post-init callback */
-        rcode = pAsync->OnInit(this);
-
-        if(rcode)
-                goto FailOnInit;
-
-        USBTRACE("PL configured\r\n");
-
-        //bPollEnable = true;
-        ready = true;
-        return 0;
-
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailGetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetConfDescr();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-        goto Fail;
-#endif
-
-FailOnInit:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("OnInit:");
-#endif
-
-#ifdef DEBUG_USB_HOST
-Fail:
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-//uint8_t PL::Poll()
-//{
-//      uint8_t rcode = 0;
-//
-//      //if (!bPollEnable)
-//      //      return 0;
-//
-//      //if (qNextPollTime <= millis())
-//      //{
-//      //      USB_HOST_SERIAL.println(bAddress, HEX);
-//
-//      //      qNextPollTime = millis() + 100;
-//      //}
-//      return rcode;
-//}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/cdcprolific.h b/lib/usbhost/USB_Host_Shield_2.0/cdcprolific.h
deleted file mode 100644
index 4991466410..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/cdcprolific.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(__CDCPROLIFIC_H__)
-#define __CDCPROLIFIC_H__
-
-#include "cdcacm.h"
-
-//#define PL2303_COMPAT // Uncomment it if you have compatibility problems
-
-#define PL_VID                                  0x067B
-#define CHECK_PID(pid)                          ( pid != 0x2303 && pid != 0x0609 )
-
-//#define PL_PID                                0x0609
-
-#define PROLIFIC_REV_H                          0x0202
-#define PROLIFIC_REV_X                          0x0300
-#define PROLIFIC_REV_HX_CHIP_D                  0x0400
-#define PROLIFIC_REV_1                          0x0001
-
-#define kXOnChar                                '\x11'
-#define kXOffChar                               '\x13'
-
-#define SPECIAL_SHIFT                           (5)
-#define SPECIAL_MASK                            ((1<<SPECIAL_SHIFT) - 1)
-#define STATE_ALL                               ( PD_RS232_S_MASK | PD_S_MASK )
-#define FLOW_RX_AUTO                            ( PD_RS232_A_RFR | PD_RS232_A_DTR | PD_RS232_A_RXO )
-#define FLOW_TX_AUTO                            ( PD_RS232_A_CTS | PD_RS232_A_DSR | PD_RS232_A_TXO | PD_RS232_A_DCD )
-#define CAN_BE_AUTO                             ( FLOW_RX_AUTO | FLOW_TX_AUTO )
-#define CAN_NOTIFY                              ( PD_RS232_N_MASK )
-#define EXTERNAL_MASK                           ( PD_S_MASK | (PD_RS232_S_MASK & ~PD_RS232_S_LOOP) )
-#define INTERNAL_DELAY                          ( PD_RS232_S_LOOP )
-#define DEFAULT_AUTO                            ( PD_RS232_A_DTR | PD_RS232_A_RFR | PD_RS232_A_CTS | PD_RS232_A_DSR )
-#define DEFAULT_NOTIFY                          0x00
-#define DEFAULT_STATE                           ( PD_S_TX_ENABLE | PD_S_RX_ENABLE | PD_RS232_A_TXO | PD_RS232_A_RXO )
-
-#define CONTINUE_SEND                           1
-#define PAUSE_SEND                              2
-
-#define kRxAutoFlow                             ((UInt32)( PD_RS232_A_RFR | PD_RS232_A_DTR | PD_RS232_A_RXO ))
-#define kTxAutoFlow                             ((UInt32)( PD_RS232_A_CTS | PD_RS232_A_DSR | PD_RS232_A_TXO | PD_RS232_A_DCD ))
-#define kControl_StateMask                      ((UInt32)( PD_RS232_S_CTS | PD_RS232_S_DSR | PD_RS232_S_CAR | PD_RS232_S_RI  ))
-#define kRxQueueState                           ((UInt32)( PD_S_RXQ_EMPTY | PD_S_RXQ_LOW_WATER | PD_S_RXQ_HIGH_WATER | PD_S_RXQ_FULL ))
-#define kTxQueueState                           ((UInt32)( PD_S_TXQ_EMPTY | PD_S_TXQ_LOW_WATER | PD_S_TXQ_HIGH_WATER | PD_S_TXQ_FULL ))
-
-#define kCONTROL_DTR                            0x01
-#define kCONTROL_RTS                            0x02
-
-#define kStateTransientMask                     0x74
-#define kBreakError                             0x04
-#define kFrameError                             0x10
-#define kParityError                            0x20
-#define kOverrunError                           0x40
-
-#define kCTS                                    0x80
-#define kDSR                                    0x02
-#define kRI                                     0x08
-#define kDCD                                    0x01
-#define kHandshakeInMask                        ((UInt32)( PD_RS232_S_CTS | PD_RS232_S_DSR | PD_RS232_S_CAR | PD_RS232_S_RI  ))
-
-#define VENDOR_WRITE_REQUEST_TYPE               0x40
-#define VENDOR_WRITE_REQUEST                    0x01
-
-#define VENDOR_READ_REQUEST_TYPE                0xc0
-#define VENDOR_READ_REQUEST                     0x01
-
-// Device Configuration Registers (DCR0, DCR1, DCR2)
-#define SET_DCR0                                0x00
-#define GET_DCR0                                0x80
-#define DCR0_INIT                               0x01
-#define DCR0_INIT_H                             0x41
-#define DCR0_INIT_X                             0x61
-
-#define SET_DCR1                                0x01
-#define GET_DCR1                                0x81
-#define DCR1_INIT_H                             0x80
-#define DCR1_INIT_X                             0x00
-
-#define SET_DCR2                                0x02
-#define GET_DCR2                                0x82
-#define DCR2_INIT_H                             0x24
-#define DCR2_INIT_X                             0x44
-
-// On-chip Data Buffers:
-#define RESET_DOWNSTREAM_DATA_PIPE              0x08
-#define RESET_UPSTREAM_DATA_PIPE                0x09
-
-
-#define PL_MAX_ENDPOINTS                        4
-
-enum tXO_State {
-        kXOnSent = -2,
-        kXOffSent = -1,
-        kXO_Idle = 0,
-        kXOffNeeded = 1,
-        kXOnNeeded = 2
-};
-
-enum pl2303_type {
-        unknown,
-        type_0, /* don't know the difference between type 0 and */
-        type_1, /* type 1, until someone from prolific tells us... */
-        rev_X,
-        rev_HX, /* HX version of the pl2303 chip */
-        rev_H
-};
-
-
-class PL2303 : public ACM {
-        uint16_t wPLType; // Type of chip
-
-public:
-        PL2303(USB *pusb, CDCAsyncOper *pasync);
-
-        // USBDeviceConfig implementation
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        //virtual uint8_t Release();
-        //virtual uint8_t Poll();
-        //virtual uint8_t GetAddress() { return bAddress; };
-
-        //// UsbConfigXtracter implementation
-        //virtual void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep);
-
-#ifdef PL2303_COMPAT
-private:
-        /* Prolific proprietary requests */
-        uint8_t vendorRead( uint8_t val_lo, uint8_t val_hi, uint16_t index, uint8_t* buf );
-        uint8_t vendorWrite( uint8_t val_lo, uint8_t val_hi, uint8_t index );
-#endif
-};
-
-#ifdef PL2303_COMPAT
-/* vendor read request */
-inline uint8_t PL2303::vendorRead( uint8_t val_lo, uint8_t val_hi, uint16_t index, uint8_t* buf )
-{
-        return( pUsb->ctrlReq(bAddress, 0, VENDOR_READ_REQUEST_TYPE, VENDOR_READ_REQUEST, val_lo, val_hi, index, 1, 1, buf, NULL ));
-}
-
-/* vendor write request */
-inline uint8_t PL2303::vendorWrite( uint8_t val_lo, uint8_t val_hi, uint8_t index )
-{
-        return( pUsb->ctrlReq(bAddress, 0, VENDOR_WRITE_REQUEST_TYPE, VENDOR_WRITE_REQUEST, val_lo, val_hi, index, 0, 0, NULL, NULL ));
-}
-#endif
-
-#endif // __CDCPROLIFIC_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/confdescparser.h b/lib/usbhost/USB_Host_Shield_2.0/confdescparser.h
deleted file mode 100644
index a6806f2ea7..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/confdescparser.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(_usb_h_) || defined(__CONFDESCPARSER_H__)
-#error "Never include confdescparser.h directly; include Usb.h instead"
-#else
-
-#define __CONFDESCPARSER_H__
-
-class UsbConfigXtracter {
-public:
-        //virtual void ConfigXtract(const USB_CONFIGURATION_DESCRIPTOR *conf) = 0;
-        //virtual void InterfaceXtract(uint8_t conf, const USB_INTERFACE_DESCRIPTOR *iface) = 0;
-
-        virtual void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep) {
-        };
-};
-
-#define CP_MASK_COMPARE_CLASS                   1
-#define CP_MASK_COMPARE_SUBCLASS                2
-#define CP_MASK_COMPARE_PROTOCOL                4
-#define CP_MASK_COMPARE_ALL                     7
-
-// Configuration Descriptor Parser Class Template
-
-template <const uint8_t CLASS_ID, const uint8_t SUBCLASS_ID, const uint8_t PROTOCOL_ID, const uint8_t MASK>
-class ConfigDescParser : public USBReadParser {
-        UsbConfigXtracter *theXtractor;
-        MultiValueBuffer theBuffer;
-        MultiByteValueParser valParser;
-        ByteSkipper theSkipper;
-        uint8_t varBuffer[16 /*sizeof(USB_CONFIGURATION_DESCRIPTOR)*/];
-
-        uint8_t stateParseDescr; // ParseDescriptor state
-
-        uint8_t dscrLen; // Descriptor length
-        uint8_t dscrType; // Descriptor type
-
-        bool isGoodInterface; // Apropriate interface flag
-        uint8_t confValue; // Configuration value
-        uint8_t protoValue; // Protocol value
-        uint8_t ifaceNumber; // Interface number
-        uint8_t ifaceAltSet; // Interface alternate settings
-
-        bool UseOr;
-        bool ParseDescriptor(uint8_t **pp, uint16_t *pcntdn);
-        void PrintHidDescriptor(const USB_HID_DESCRIPTOR *pDesc);
-
-public:
-
-        void SetOR(void) {
-                UseOr = true;
-        }
-        ConfigDescParser(UsbConfigXtracter *xtractor);
-        void Parse(const uint16_t len, const uint8_t *pbuf, const uint16_t &offset);
-};
-
-template <const uint8_t CLASS_ID, const uint8_t SUBCLASS_ID, const uint8_t PROTOCOL_ID, const uint8_t MASK>
-ConfigDescParser<CLASS_ID, SUBCLASS_ID, PROTOCOL_ID, MASK>::ConfigDescParser(UsbConfigXtracter *xtractor) :
-theXtractor(xtractor),
-stateParseDescr(0),
-dscrLen(0),
-dscrType(0),
-UseOr(false) {
-        theBuffer.pValue = varBuffer;
-        valParser.Initialize(&theBuffer);
-        theSkipper.Initialize(&theBuffer);
-};
-
-template <const uint8_t CLASS_ID, const uint8_t SUBCLASS_ID, const uint8_t PROTOCOL_ID, const uint8_t MASK>
-void ConfigDescParser<CLASS_ID, SUBCLASS_ID, PROTOCOL_ID, MASK>::Parse(const uint16_t len, const uint8_t *pbuf, const uint16_t &offset) {
-        uint16_t cntdn = (uint16_t)len;
-        uint8_t *p = (uint8_t*)pbuf;
-
-        while(cntdn)
-                if(!ParseDescriptor(&p, &cntdn))
-                        return;
-}
-
-/* Parser for the configuration descriptor. Takes values for class, subclass, protocol fields in interface descriptor and
-  compare masks for them. When the match is found, calls EndpointXtract passing buffer containing endpoint descriptor */
-template <const uint8_t CLASS_ID, const uint8_t SUBCLASS_ID, const uint8_t PROTOCOL_ID, const uint8_t MASK>
-bool ConfigDescParser<CLASS_ID, SUBCLASS_ID, PROTOCOL_ID, MASK>::ParseDescriptor(uint8_t **pp, uint16_t *pcntdn) {
-        USB_CONFIGURATION_DESCRIPTOR* ucd = reinterpret_cast<USB_CONFIGURATION_DESCRIPTOR*>(varBuffer);
-        USB_INTERFACE_DESCRIPTOR* uid = reinterpret_cast<USB_INTERFACE_DESCRIPTOR*>(varBuffer);
-        switch(stateParseDescr) {
-                case 0:
-                        theBuffer.valueSize = 2;
-                        valParser.Initialize(&theBuffer);
-                        stateParseDescr = 1;
-                case 1:
-                        if(!valParser.Parse(pp, pcntdn))
-                                return false;
-                        dscrLen = *((uint8_t*)theBuffer.pValue);
-                        dscrType = *((uint8_t*)theBuffer.pValue + 1);
-                        stateParseDescr = 2;
-                case 2:
-                        // This is a sort of hack. Assuming that two bytes are all ready in the buffer
-                        //      the pointer is positioned two bytes ahead in order for the rest of descriptor
-                        //      to be read right after the size and the type fields.
-                        // This should be used carefully. varBuffer should be used directly to handle data
-                        //      in the buffer.
-                        theBuffer.pValue = varBuffer + 2;
-                        stateParseDescr = 3;
-                case 3:
-                        switch(dscrType) {
-                                case USB_DESCRIPTOR_INTERFACE:
-                                        isGoodInterface = false;
-                                case USB_DESCRIPTOR_CONFIGURATION:
-                                        theBuffer.valueSize = sizeof (USB_CONFIGURATION_DESCRIPTOR) - 2;
-                                        break;
-                                case USB_DESCRIPTOR_ENDPOINT:
-                                        theBuffer.valueSize = sizeof (USB_ENDPOINT_DESCRIPTOR) - 2;
-                                        break;
-                                case HID_DESCRIPTOR_HID:
-                                        theBuffer.valueSize = dscrLen - 2;
-                                        break;
-                        }
-                        valParser.Initialize(&theBuffer);
-                        stateParseDescr = 4;
-                case 4:
-                        switch(dscrType) {
-                                case USB_DESCRIPTOR_CONFIGURATION:
-                                        if(!valParser.Parse(pp, pcntdn))
-                                                return false;
-                                        confValue = ucd->bConfigurationValue;
-                                        break;
-                                case USB_DESCRIPTOR_INTERFACE:
-                                        if(!valParser.Parse(pp, pcntdn))
-                                                return false;
-                                        if((MASK & CP_MASK_COMPARE_CLASS) && uid->bInterfaceClass != CLASS_ID)
-                                                break;
-                                        if((MASK & CP_MASK_COMPARE_SUBCLASS) && uid->bInterfaceSubClass != SUBCLASS_ID)
-                                                break;
-                                        if(UseOr) {
-                                                if((!((MASK & CP_MASK_COMPARE_PROTOCOL) && uid->bInterfaceProtocol)))
-                                                        break;
-                                        } else {
-                                                if((MASK & CP_MASK_COMPARE_PROTOCOL) && uid->bInterfaceProtocol != PROTOCOL_ID)
-                                                        break;
-                                        }
-                                        isGoodInterface = true;
-                                        ifaceNumber = uid->bInterfaceNumber;
-                                        ifaceAltSet = uid->bAlternateSetting;
-                                        protoValue = uid->bInterfaceProtocol;
-                                        break;
-                                case USB_DESCRIPTOR_ENDPOINT:
-                                        if(!valParser.Parse(pp, pcntdn))
-                                                return false;
-                                        if(isGoodInterface)
-                                                if(theXtractor)
-                                                        theXtractor->EndpointXtract(confValue, ifaceNumber, ifaceAltSet, protoValue, (USB_ENDPOINT_DESCRIPTOR*)varBuffer);
-                                        break;
-                                        //case HID_DESCRIPTOR_HID:
-                                        //      if (!valParser.Parse(pp, pcntdn))
-                                        //              return false;
-                                        //      PrintHidDescriptor((const USB_HID_DESCRIPTOR*)varBuffer);
-                                        //      break;
-                                default:
-                                        if(!theSkipper.Skip(pp, pcntdn, dscrLen - 2))
-                                                return false;
-                        }
-                        theBuffer.pValue = varBuffer;
-                        stateParseDescr = 0;
-        }
-        return true;
-}
-
-template <const uint8_t CLASS_ID, const uint8_t SUBCLASS_ID, const uint8_t PROTOCOL_ID, const uint8_t MASK>
-void ConfigDescParser<CLASS_ID, SUBCLASS_ID, PROTOCOL_ID, MASK>::PrintHidDescriptor(const USB_HID_DESCRIPTOR *pDesc) {
-        Notify(PSTR("\r\n\r\nHID Descriptor:\r\n"), 0x80);
-        Notify(PSTR("bDescLength:\t\t"), 0x80);
-        PrintHex<uint8_t > (pDesc->bLength, 0x80);
-
-        Notify(PSTR("\r\nbDescriptorType:\t"), 0x80);
-        PrintHex<uint8_t > (pDesc->bDescriptorType, 0x80);
-
-        Notify(PSTR("\r\nbcdHID:\t\t\t"), 0x80);
-        PrintHex<uint16_t > (pDesc->bcdHID, 0x80);
-
-        Notify(PSTR("\r\nbCountryCode:\t\t"), 0x80);
-        PrintHex<uint8_t > (pDesc->bCountryCode, 0x80);
-
-        Notify(PSTR("\r\nbNumDescriptors:\t"), 0x80);
-        PrintHex<uint8_t > (pDesc->bNumDescriptors, 0x80);
-
-        for(uint8_t i = 0; i < pDesc->bNumDescriptors; i++) {
-                HID_CLASS_DESCRIPTOR_LEN_AND_TYPE *pLT = (HID_CLASS_DESCRIPTOR_LEN_AND_TYPE*)&(pDesc->bDescrType);
-
-                Notify(PSTR("\r\nbDescrType:\t\t"), 0x80);
-                PrintHex<uint8_t > (pLT[i].bDescrType, 0x80);
-
-                Notify(PSTR("\r\nwDescriptorLength:\t"), 0x80);
-                PrintHex<uint16_t > (pLT[i].wDescriptorLength, 0x80);
-        }
-        Notify(PSTR("\r\n"), 0x80);
-}
-
-
-#endif // __CONFDESCPARSER_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/controllerEnums.h b/lib/usbhost/USB_Host_Shield_2.0/controllerEnums.h
deleted file mode 100644
index 0169c763c1..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/controllerEnums.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/* Copyright (C) 2013 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _controllerenums_h
-#define _controllerenums_h
-
-/**
- * This header file is used to store different enums for the controllers,
- * This is necessary so all the different libraries can be used at once.
- */
-
-/** Enum used to turn on the LEDs on the different controllers. */
-enum LEDEnum {
-        OFF = 0,
-        LED1 = 1,
-        LED2 = 2,
-        LED3 = 3,
-        LED4 = 4,
-
-        LED5 = 5,
-        LED6 = 6,
-        LED7 = 7,
-        LED8 = 8,
-        LED9 = 9,
-        LED10 = 10,
-        /** Used to blink all LEDs on the Xbox controller */
-        ALL = 5,
-};
-
-/** Used to set the colors of the Move and PS4 controller. */
-enum ColorsEnum {
-        /** r = 255, g = 0, b = 0 */
-        Red = 0xFF0000,
-        /** r = 0, g = 255, b = 0 */
-        Green = 0xFF00,
-        /** r = 0, g = 0, b = 255 */
-        Blue = 0xFF,
-
-        /** r = 255, g = 235, b = 4 */
-        Yellow = 0xFFEB04,
-        /** r = 0, g = 255, b = 255 */
-        Lightblue = 0xFFFF,
-        /** r = 255, g = 0, b = 255 */
-        Purble = 0xFF00FF,
-
-        /** r = 255, g = 255, b = 255 */
-        White = 0xFFFFFF,
-        /** r = 0, g = 0, b = 0 */
-        Off = 0x00,
-};
-
-enum RumbleEnum {
-        RumbleHigh = 0x10,
-        RumbleLow = 0x20,
-};
-
-/** This enum is used to read all the different buttons on the different controllers */
-enum ButtonEnum {
-        /**@{*/
-        /** These buttons are available on all the the controllers */
-        UP = 0,
-        RIGHT = 1,
-        DOWN = 2,
-        LEFT = 3,
-        /**@}*/
-
-        /**@{*/
-        /** Wii buttons */
-        PLUS = 5,
-        TWO = 6,
-        ONE = 7,
-        MINUS = 8,
-        HOME = 9,
-        Z = 10,
-        C = 11,
-        B = 12,
-        A = 13,
-        /**@}*/
-
-        /**@{*/
-        /** These are only available on the Wii U Pro Controller */
-        L = 16,
-        R = 17,
-        ZL = 18,
-        ZR = 19,
-        /**@}*/
-
-        /**@{*/
-        /** PS3 controllers buttons */
-        SELECT = 4,
-        START = 5,
-        L3 = 6,
-        R3 = 7,
-
-        L2 = 8,
-        R2 = 9,
-        L1 = 10,
-        R1 = 11,
-        TRIANGLE = 12,
-        CIRCLE = 13,
-        CROSS = 14,
-        SQUARE = 15,
-
-        PS = 16,
-
-        MOVE = 17, // Covers 12 bits - we only need to read the top 8
-        T = 18, // Covers 12 bits - we only need to read the top 8
-        /**@}*/
-
-        /** PS4 controllers buttons - SHARE and OPTIONS are present instead of SELECT and START */
-        SHARE = 4,
-        OPTIONS = 5,
-        TOUCHPAD = 17,
-        /**@}*/
-
-        /**@{*/
-        /** Xbox buttons */
-        BACK = 4,
-        X = 14,
-        Y = 15,
-        XBOX = 16,
-        SYNC = 17,
-        BLACK = 8, // Available on the original Xbox controller
-        WHITE = 9, // Available on the original Xbox controller
-        /**@}*/
-
-        /** PS Buzz controllers */
-        RED = 0,
-        YELLOW = 1,
-        GREEN = 2,
-        ORANGE = 3,
-        BLUE = 4,
-        /**@}*/
-};
-
-/** Joysticks on the PS3 and Xbox controllers. */
-enum AnalogHatEnum {
-        /** Left joystick x-axis */
-        LeftHatX = 0,
-        /** Left joystick y-axis */
-        LeftHatY = 1,
-        /** Right joystick x-axis */
-        RightHatX = 2,
-        /** Right joystick y-axis */
-        RightHatY = 3,
-};
-
-/**
- * Sensors inside the Sixaxis Dualshock 3, Move controller and PS4 controller.
- * <B>Note:</B> that the location is shifted 9 when it's connected via USB on the PS3 controller.
- */
-enum SensorEnum {
-        /** Accelerometer values */
-        aX = 50, aY = 52, aZ = 54,
-        /** Gyro z-axis */
-        gZ = 56,
-        gX, gY, // These are not available on the PS3 controller
-
-        /** Accelerometer x-axis */
-        aXmove = 28,
-        /** Accelerometer z-axis */
-        aZmove = 30,
-        /** Accelerometer y-axis */
-        aYmove = 32,
-
-        /** Gyro x-axis */
-        gXmove = 40,
-        /** Gyro z-axis */
-        gZmove = 42,
-        /** Gyro y-axis */
-        gYmove = 44,
-
-        /** Temperature sensor */
-        tempMove = 46,
-
-        /** Magnetometer x-axis */
-        mXmove = 47,
-        /** Magnetometer z-axis */
-        mZmove = 49,
-        /** Magnetometer y-axis */
-        mYmove = 50,
-};
-
-/** Used to get the angle calculated using the PS3 controller and PS4 controller. */
-enum AngleEnum {
-        Pitch = 0x01,
-        Roll = 0x02,
-};
-
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/BTHID/BTHID.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/BTHID/BTHID.ino
deleted file mode 100644
index 919a56468b..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/BTHID/BTHID.ino
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- Example sketch for the HID Bluetooth library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <BTHID.h>
-#include <usbhub.h>
-#include "KeyboardParser.h"
-#include "MouseParser.h"
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-
-/* You can create the instance of the class in two ways */
-// This will start an inquiry and then pair with your device - you only have to do this once
-// If you are using a Bluetooth keyboard, then you should type in the password on the keypad and then press enter
-BTHID bthid(&Btd, PAIR, "0000");
-
-// After that you can simply create the instance like so and then press any button on the device
-//BTHID hid(&Btd);
-
-KbdRptParser keyboardPrs;
-MouseRptParser mousePrs;
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); // Halt
-  }
-
-  bthid.SetReportParser(KEYBOARD_PARSER_ID, (HIDReportParser*)&keyboardPrs);
-  bthid.SetReportParser(MOUSE_PARSER_ID, (HIDReportParser*)&mousePrs);
-
-  // If "Boot Protocol Mode" does not work, then try "Report Protocol Mode"
-  // If that does not work either, then uncomment PRINTREPORT in BTHID.cpp to see the raw report
-  bthid.setProtocolMode(HID_BOOT_PROTOCOL); // Boot Protocol Mode
-  //bthid.setProtocolMode(HID_RPT_PROTOCOL); // Report Protocol Mode
-
-  Serial.print(F("\r\nHID Bluetooth Library Started"));
-}
-void loop() {
-  Usb.Task();
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/BTHID/KeyboardParser.h b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/BTHID/KeyboardParser.h
deleted file mode 100644
index c5394331da..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/BTHID/KeyboardParser.h
+++ /dev/null
@@ -1,105 +0,0 @@
-#ifndef __kbdrptparser_h_
-#define __kbdrptparser_h_
-
-class KbdRptParser : public KeyboardReportParser {
-  protected:
-    virtual uint8_t HandleLockingKeys(HID *hid, uint8_t key);
-    virtual void OnControlKeysChanged(uint8_t before, uint8_t after);
-    virtual void OnKeyDown(uint8_t mod, uint8_t key);
-    virtual void OnKeyUp(uint8_t mod, uint8_t key);
-    virtual void OnKeyPressed(uint8_t key);
-
-  private:
-    void PrintKey(uint8_t mod, uint8_t key);
-};
-
-uint8_t KbdRptParser::HandleLockingKeys(HID *hid, uint8_t key) {
-  uint8_t old_keys = kbdLockingKeys.bLeds;
-
-  switch (key) {
-    case UHS_HID_BOOT_KEY_NUM_LOCK:
-      Serial.println(F("Num lock"));
-      kbdLockingKeys.kbdLeds.bmNumLock = ~kbdLockingKeys.kbdLeds.bmNumLock;
-      break;
-    case UHS_HID_BOOT_KEY_CAPS_LOCK:
-      Serial.println(F("Caps lock"));
-      kbdLockingKeys.kbdLeds.bmCapsLock = ~kbdLockingKeys.kbdLeds.bmCapsLock;
-      break;
-    case UHS_HID_BOOT_KEY_SCROLL_LOCK:
-      Serial.println(F("Scroll lock"));
-      kbdLockingKeys.kbdLeds.bmScrollLock = ~kbdLockingKeys.kbdLeds.bmScrollLock;
-      break;
-  }
-
-  if (old_keys != kbdLockingKeys.bLeds && hid) {
-    BTHID *pBTHID = reinterpret_cast<BTHID *> (hid); // A cast the other way around is done in BTHID.cpp
-    pBTHID->setLeds(kbdLockingKeys.bLeds); // Update the LEDs on the keyboard
-  }
-
-  return 0;
-};
-
-void KbdRptParser::PrintKey(uint8_t m, uint8_t key) {
-  MODIFIERKEYS mod;
-  *((uint8_t*)&mod) = m;
-  Serial.print((mod.bmLeftCtrl == 1) ? F("C") : F(" "));
-  Serial.print((mod.bmLeftShift == 1) ? F("S") : F(" "));
-  Serial.print((mod.bmLeftAlt == 1) ? F("A") : F(" "));
-  Serial.print((mod.bmLeftGUI == 1) ? F("G") : F(" "));
-
-  Serial.print(F(" >"));
-  PrintHex<uint8_t>(key, 0x80);
-  Serial.print(F("< "));
-
-  Serial.print((mod.bmRightCtrl == 1) ? F("C") : F(" "));
-  Serial.print((mod.bmRightShift == 1) ? F("S") : F(" "));
-  Serial.print((mod.bmRightAlt == 1) ? F("A") : F(" "));
-  Serial.println((mod.bmRightGUI == 1) ? F("G") : F(" "));
-};
-
-void KbdRptParser::OnKeyDown(uint8_t mod, uint8_t key) {
-  Serial.print(F("DN "));
-  PrintKey(mod, key);
-  uint8_t c = OemToAscii(mod, key);
-
-  if (c)
-    OnKeyPressed(c);
-};
-
-void KbdRptParser::OnControlKeysChanged(uint8_t before, uint8_t after) {
-  MODIFIERKEYS beforeMod;
-  *((uint8_t*)&beforeMod) = before;
-
-  MODIFIERKEYS afterMod;
-  *((uint8_t*)&afterMod) = after;
-
-  if (beforeMod.bmLeftCtrl != afterMod.bmLeftCtrl)
-    Serial.println(F("LeftCtrl changed"));
-  if (beforeMod.bmLeftShift != afterMod.bmLeftShift)
-    Serial.println(F("LeftShift changed"));
-  if (beforeMod.bmLeftAlt != afterMod.bmLeftAlt)
-    Serial.println(F("LeftAlt changed"));
-  if (beforeMod.bmLeftGUI != afterMod.bmLeftGUI)
-    Serial.println(F("LeftGUI changed"));
-
-  if (beforeMod.bmRightCtrl != afterMod.bmRightCtrl)
-    Serial.println(F("RightCtrl changed"));
-  if (beforeMod.bmRightShift != afterMod.bmRightShift)
-    Serial.println(F("RightShift changed"));
-  if (beforeMod.bmRightAlt != afterMod.bmRightAlt)
-    Serial.println(F("RightAlt changed"));
-  if (beforeMod.bmRightGUI != afterMod.bmRightGUI)
-    Serial.println(F("RightGUI changed"));
-};
-
-void KbdRptParser::OnKeyUp(uint8_t mod, uint8_t key) {
-  Serial.print(F("UP "));
-  PrintKey(mod, key);
-};
-
-void KbdRptParser::OnKeyPressed(uint8_t key) {
-  Serial.print(F("ASCII: "));
-  Serial.println((char)key);
-};
-
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/BTHID/MouseParser.h b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/BTHID/MouseParser.h
deleted file mode 100644
index a9245ded99..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/BTHID/MouseParser.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __mouserptparser_h__
-#define __mouserptparser_h__
-
-class MouseRptParser : public MouseReportParser {
-  protected:
-    virtual void OnMouseMove(MOUSEINFO *mi);
-    virtual void OnLeftButtonUp(MOUSEINFO *mi);
-    virtual void OnLeftButtonDown(MOUSEINFO *mi);
-    virtual void OnRightButtonUp(MOUSEINFO *mi);
-    virtual void OnRightButtonDown(MOUSEINFO *mi);
-    virtual void OnMiddleButtonUp(MOUSEINFO *mi);
-    virtual void OnMiddleButtonDown(MOUSEINFO *mi);
-};
-
-void MouseRptParser::OnMouseMove(MOUSEINFO *mi) {
-  Serial.print(F("dx="));
-  Serial.print(mi->dX, DEC);
-  Serial.print(F(" dy="));
-  Serial.println(mi->dY, DEC);
-};
-
-void MouseRptParser::OnLeftButtonUp(MOUSEINFO *mi) {
-  Serial.println(F("L Butt Up"));
-};
-
-void MouseRptParser::OnLeftButtonDown(MOUSEINFO *mi) {
-  Serial.println(F("L Butt Dn"));
-};
-
-void MouseRptParser::OnRightButtonUp(MOUSEINFO *mi) {
-  Serial.println(F("R Butt Up"));
-};
-
-void MouseRptParser::OnRightButtonDown(MOUSEINFO *mi) {
-  Serial.println(F("R Butt Dn"));
-};
-
-void MouseRptParser::OnMiddleButtonUp(MOUSEINFO *mi) {
-  Serial.println(F("M Butt Up"));
-};
-
-void MouseRptParser::OnMiddleButtonDown(MOUSEINFO *mi) {
-  Serial.println(F("M Butt Dn"));
-};
-
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS3BT/PS3BT.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS3BT/PS3BT.ino
deleted file mode 100644
index b896734405..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS3BT/PS3BT.ino
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- Example sketch for the PS3 Bluetooth library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <PS3BT.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-/* You can create the instance of the class in two ways */
-PS3BT PS3(&Btd); // This will just create the instance
-//PS3BT PS3(&Btd, 0x00, 0x15, 0x83, 0x3D, 0x0A, 0x57); // This will also store the bluetooth address - this can be obtained from the dongle when running the sketch
-
-bool printTemperature;
-bool printAngle;
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nPS3 Bluetooth Library Started"));
-}
-void loop() {
-  Usb.Task();
-
-  if (PS3.PS3Connected || PS3.PS3NavigationConnected) {
-    if (PS3.getAnalogHat(LeftHatX) > 137 || PS3.getAnalogHat(LeftHatX) < 117 || PS3.getAnalogHat(LeftHatY) > 137 || PS3.getAnalogHat(LeftHatY) < 117 || PS3.getAnalogHat(RightHatX) > 137 || PS3.getAnalogHat(RightHatX) < 117 || PS3.getAnalogHat(RightHatY) > 137 || PS3.getAnalogHat(RightHatY) < 117) {
-      Serial.print(F("\r\nLeftHatX: "));
-      Serial.print(PS3.getAnalogHat(LeftHatX));
-      Serial.print(F("\tLeftHatY: "));
-      Serial.print(PS3.getAnalogHat(LeftHatY));
-      if (PS3.PS3Connected) { // The Navigation controller only have one joystick
-        Serial.print(F("\tRightHatX: "));
-        Serial.print(PS3.getAnalogHat(RightHatX));
-        Serial.print(F("\tRightHatY: "));
-        Serial.print(PS3.getAnalogHat(RightHatY));
-      }
-    }
-
-    // Analog button values can be read from almost all buttons
-    if (PS3.getAnalogButton(L2) || PS3.getAnalogButton(R2)) {
-      Serial.print(F("\r\nL2: "));
-      Serial.print(PS3.getAnalogButton(L2));
-      if (PS3.PS3Connected) {
-        Serial.print(F("\tR2: "));
-        Serial.print(PS3.getAnalogButton(R2));
-      }
-    }
-    if (PS3.getButtonClick(PS)) {
-      Serial.print(F("\r\nPS"));
-      PS3.disconnect();
-    }
-    else {
-      if (PS3.getButtonClick(TRIANGLE))
-        Serial.print(F("\r\nTraingle"));
-      if (PS3.getButtonClick(CIRCLE))
-        Serial.print(F("\r\nCircle"));
-      if (PS3.getButtonClick(CROSS))
-        Serial.print(F("\r\nCross"));
-      if (PS3.getButtonClick(SQUARE))
-        Serial.print(F("\r\nSquare"));
-
-      if (PS3.getButtonClick(UP)) {
-        Serial.print(F("\r\nUp"));
-        if (PS3.PS3Connected) {
-          PS3.setLedOff();
-          PS3.setLedOn(LED4);
-        }
-      }
-      if (PS3.getButtonClick(RIGHT)) {
-        Serial.print(F("\r\nRight"));
-        if (PS3.PS3Connected) {
-          PS3.setLedOff();
-          PS3.setLedOn(LED1);
-        }
-      }
-      if (PS3.getButtonClick(DOWN)) {
-        Serial.print(F("\r\nDown"));
-        if (PS3.PS3Connected) {
-          PS3.setLedOff();
-          PS3.setLedOn(LED2);
-        }
-      }
-      if (PS3.getButtonClick(LEFT)) {
-        Serial.print(F("\r\nLeft"));
-        if (PS3.PS3Connected) {
-          PS3.setLedOff();
-          PS3.setLedOn(LED3);
-        }
-      }
-
-      if (PS3.getButtonClick(L1))
-        Serial.print(F("\r\nL1"));
-      if (PS3.getButtonClick(L3))
-        Serial.print(F("\r\nL3"));
-      if (PS3.getButtonClick(R1))
-        Serial.print(F("\r\nR1"));
-      if (PS3.getButtonClick(R3))
-        Serial.print(F("\r\nR3"));
-
-      if (PS3.getButtonClick(SELECT)) {
-        Serial.print(F("\r\nSelect - "));
-        PS3.printStatusString();
-      }
-      if (PS3.getButtonClick(START)) {
-        Serial.print(F("\r\nStart"));
-        printAngle = !printAngle;
-      }
-    }
-#if 0 // Set this to 1 in order to see the angle of the controller
-    if (printAngle) {
-      Serial.print(F("\r\nPitch: "));
-      Serial.print(PS3.getAngle(Pitch));
-      Serial.print(F("\tRoll: "));
-      Serial.print(PS3.getAngle(Roll));
-    }
-#endif
-  }
-#if 0 // Set this to 1 in order to enable support for the Playstation Move controller
-  else if (PS3.PS3MoveConnected) {
-    if (PS3.getAnalogButton(T)) {
-      Serial.print(F("\r\nT: "));
-      Serial.print(PS3.getAnalogButton(T));
-    }
-    if (PS3.getButtonClick(PS)) {
-      Serial.print(F("\r\nPS"));
-      PS3.disconnect();
-    }
-    else {
-      if (PS3.getButtonClick(SELECT)) {
-        Serial.print(F("\r\nSelect"));
-        printTemperature = !printTemperature;
-      }
-      if (PS3.getButtonClick(START)) {
-        Serial.print(F("\r\nStart"));
-        printAngle = !printAngle;
-      }
-      if (PS3.getButtonClick(TRIANGLE)) {
-        Serial.print(F("\r\nTriangle"));
-        PS3.moveSetBulb(Red);
-      }
-      if (PS3.getButtonClick(CIRCLE)) {
-        Serial.print(F("\r\nCircle"));
-        PS3.moveSetBulb(Green);
-      }
-      if (PS3.getButtonClick(SQUARE)) {
-        Serial.print(F("\r\nSquare"));
-        PS3.moveSetBulb(Blue);
-      }
-      if (PS3.getButtonClick(CROSS)) {
-        Serial.print(F("\r\nCross"));
-        PS3.moveSetBulb(Yellow);
-      }
-      if (PS3.getButtonClick(MOVE)) {
-        PS3.moveSetBulb(Off);
-        Serial.print(F("\r\nMove"));
-        Serial.print(F(" - "));
-        PS3.printStatusString();
-      }
-    }
-    if (printAngle) {
-      Serial.print(F("\r\nPitch: "));
-      Serial.print(PS3.getAngle(Pitch));
-      Serial.print(F("\tRoll: "));
-      Serial.print(PS3.getAngle(Roll));
-    }
-    else if (printTemperature) {
-      Serial.print(F("\r\nTemperature: "));
-      Serial.print(PS3.getTemperature());
-    }
-  }
-#endif
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS3Multi/PS3Multi.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS3Multi/PS3Multi.ino
deleted file mode 100644
index 5ebfd7819c..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS3Multi/PS3Multi.ino
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- Example sketch for the PS3 Bluetooth library - developed by Kristian Lauszus
- This example show how one can use multiple controllers with the library
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <PS3BT.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-PS3BT *PS3[2]; // We will use this pointer to store the two instance, you can easily make it larger if you like, but it will use a lot of RAM!
-const uint8_t length = sizeof(PS3) / sizeof(PS3[0]); // Get the lenght of the array
-bool printAngle[length];
-bool oldControllerState[length];
-
-void setup() {
-  for (uint8_t i = 0; i < length; i++) {
-    PS3[i] = new PS3BT(&Btd); // Create the instances
-    PS3[i]->attachOnInit(onInit); // onInit() is called upon a new connection - you can call the function whatever you like
-  }
-
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nPS3 Bluetooth Library Started"));
-}
-void loop() {
-  Usb.Task();
-
-  for (uint8_t i = 0; i < length; i++) {
-    if (PS3[i]->PS3Connected || PS3[i]->PS3NavigationConnected) {
-      if (PS3[i]->getAnalogHat(LeftHatX) > 137 || PS3[i]->getAnalogHat(LeftHatX) < 117 || PS3[i]->getAnalogHat(LeftHatY) > 137 || PS3[i]->getAnalogHat(LeftHatY) < 117 || PS3[i]->getAnalogHat(RightHatX) > 137 || PS3[i]->getAnalogHat(RightHatX) < 117 || PS3[i]->getAnalogHat(RightHatY) > 137 || PS3[i]->getAnalogHat(RightHatY) < 117) {
-        Serial.print(F("\r\nLeftHatX: "));
-        Serial.print(PS3[i]->getAnalogHat(LeftHatX));
-        Serial.print(F("\tLeftHatY: "));
-        Serial.print(PS3[i]->getAnalogHat(LeftHatY));
-        if (PS3[i]->PS3Connected) { // The Navigation controller only have one joystick
-          Serial.print(F("\tRightHatX: "));
-          Serial.print(PS3[i]->getAnalogHat(RightHatX));
-          Serial.print(F("\tRightHatY: "));
-          Serial.print(PS3[i]->getAnalogHat(RightHatY));
-        }
-      }
-      //Analog button values can be read from almost all buttons
-      if (PS3[i]->getAnalogButton(L2) || PS3[i]->getAnalogButton(R2)) {
-        Serial.print(F("\r\nL2: "));
-        Serial.print(PS3[i]->getAnalogButton(L2));
-        if (PS3[i]->PS3Connected) {
-          Serial.print(F("\tR2: "));
-          Serial.print(PS3[i]->getAnalogButton(R2));
-        }
-      }
-      if (PS3[i]->getButtonClick(PS)) {
-        Serial.print(F("\r\nPS"));
-        PS3[i]->disconnect();
-        oldControllerState[i] = false; // Reset value
-      }
-      else {
-        if (PS3[i]->getButtonClick(TRIANGLE))
-          Serial.print(F("\r\nTraingle"));
-        if (PS3[i]->getButtonClick(CIRCLE))
-          Serial.print(F("\r\nCircle"));
-        if (PS3[i]->getButtonClick(CROSS))
-          Serial.print(F("\r\nCross"));
-        if (PS3[i]->getButtonClick(SQUARE))
-          Serial.print(F("\r\nSquare"));
-
-        if (PS3[i]->getButtonClick(UP)) {
-          Serial.print(F("\r\nUp"));
-          if (PS3[i]->PS3Connected) {
-            PS3[i]->setLedOff();
-            PS3[i]->setLedOn(LED4);
-          }
-        }
-        if (PS3[i]->getButtonClick(RIGHT)) {
-          Serial.print(F("\r\nRight"));
-          if (PS3[i]->PS3Connected) {
-            PS3[i]->setLedOff();
-            PS3[i]->setLedOn(LED1);
-          }
-        }
-        if (PS3[i]->getButtonClick(DOWN)) {
-          Serial.print(F("\r\nDown"));
-          if (PS3[i]->PS3Connected) {
-            PS3[i]->setLedOff();
-            PS3[i]->setLedOn(LED2);
-          }
-        }
-        if (PS3[i]->getButtonClick(LEFT)) {
-          Serial.print(F("\r\nLeft"));
-          if (PS3[i]->PS3Connected) {
-            PS3[i]->setLedOff();
-            PS3[i]->setLedOn(LED3);
-          }
-        }
-
-        if (PS3[i]->getButtonClick(L1))
-          Serial.print(F("\r\nL1"));
-        if (PS3[i]->getButtonClick(L3))
-          Serial.print(F("\r\nL3"));
-        if (PS3[i]->getButtonClick(R1))
-          Serial.print(F("\r\nR1"));
-        if (PS3[i]->getButtonClick(R3))
-          Serial.print(F("\r\nR3"));
-
-        if (PS3[i]->getButtonClick(SELECT)) {
-          Serial.print(F("\r\nSelect - "));
-          PS3[i]->printStatusString();
-        }
-        if (PS3[i]->getButtonClick(START)) {
-          Serial.print(F("\r\nStart"));
-          printAngle[i] = !printAngle[i];
-        }
-      }
-      if (printAngle[i]) {
-        Serial.print(F("\r\nPitch: "));
-        Serial.print(PS3[i]->getAngle(Pitch));
-        Serial.print(F("\tRoll: "));
-        Serial.print(PS3[i]->getAngle(Roll));
-      }
-    }
-    /* I have removed the PS3 Move code as an Uno will run out of RAM if it's included */
-    //else if(PS3[i]->PS3MoveConnected) {
-  }
-}
-
-void onInit() {
-  for (uint8_t i = 0; i < length; i++) {
-    if ((PS3[i]->PS3Connected || PS3[i]->PS3NavigationConnected) && !oldControllerState[i]) {
-      oldControllerState[i] = true; // Used to check which is the new controller
-      PS3[i]->setLedOn((LEDEnum)(i + 1)); // Cast directly to LEDEnum - see: "controllerEnums.h"
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS3SPP/PS3SPP.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS3SPP/PS3SPP.ino
deleted file mode 100644
index 8f234cbd8d..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS3SPP/PS3SPP.ino
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- Example sketch for the Bluetooth library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
-
- This example show how one can combine all the difference Bluetooth services in one single code.
- Note:
- You will need a Arduino Mega 1280/2560 to run this sketch,
- as a normal Arduino (Uno, Duemilanove etc.) doesn't have enough SRAM and FLASH
- */
-
-#include <PS3BT.h>
-#include <SPP.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-
-/* You can create the instances of the bluetooth services in two ways */
-SPP SerialBT(&Btd); // This will set the name to the defaults: "Arduino" and the pin to "0000"
-//SPP SerialBTBT(&Btd,"Lauszus's Arduino","0000"); // You can also set the name and pin like so
-PS3BT PS3(&Btd); // This will just create the instance
-//PS3BT PS3(&Btd, 0x00, 0x15, 0x83, 0x3D, 0x0A, 0x57); // This will also store the bluetooth address - this can be obtained from the dongle when running the sketch
-
-bool firstMessage = true;
-String output = ""; // We will store the data in this string
-
-void setup() {
-  Serial.begin(115200); // This wil lprint the debugging from the libraries
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nBluetooth Library Started"));
-  output.reserve(200); // Reserve 200 bytes for the output string
-}
-void loop() {
-  Usb.Task(); // The SPP data is actually not send until this is called, one could call SerialBT.send() directly as well
-
-  if (SerialBT.connected) {
-    if (firstMessage) {
-      firstMessage = false;
-      SerialBT.println(F("Hello from Arduino")); // Send welcome message
-    }
-    if (Serial.available())
-      SerialBT.write(Serial.read());
-    if (SerialBT.available())
-      Serial.write(SerialBT.read());
-  }
-  else
-    firstMessage = true;
-
-  if (PS3.PS3Connected || PS3.PS3NavigationConnected) {
-    output = ""; // Reset output string
-    if (PS3.getAnalogHat(LeftHatX) > 137 || PS3.getAnalogHat(LeftHatX) < 117 || PS3.getAnalogHat(LeftHatY) > 137 || PS3.getAnalogHat(LeftHatY) < 117 || PS3.getAnalogHat(RightHatX) > 137 || PS3.getAnalogHat(RightHatX) < 117 || PS3.getAnalogHat(RightHatY) > 137 || PS3.getAnalogHat(RightHatY) < 117) {
-      output += "LeftHatX: ";
-      output += PS3.getAnalogHat(LeftHatX);
-      output += "\tLeftHatY: ";
-      output += PS3.getAnalogHat(LeftHatY);
-      if (PS3.PS3Connected) { // The Navigation controller only have one joystick
-        output += "\tRightHatX: ";
-        output += PS3.getAnalogHat(RightHatX);
-        output += "\tRightHatY: ";
-        output += PS3.getAnalogHat(RightHatY);
-      }
-    }
-    //Analog button values can be read from almost all buttons
-    if (PS3.getAnalogButton(L2) || PS3.getAnalogButton(R2)) {
-      if (output != "")
-        output += "\r\n";
-      output += "L2: ";
-      output += PS3.getAnalogButton(L2);
-      if (PS3.PS3Connected) {
-        output += "\tR2: ";
-        output += PS3.getAnalogButton(R2);
-      }
-    }
-    if (output != "") {
-      Serial.println(output);
-      if (SerialBT.connected)
-        SerialBT.println(output);
-      output = ""; // Reset output string
-    }
-    if (PS3.getButtonClick(PS)) {
-      output += " - PS";
-      PS3.disconnect();
-    }
-    else {
-      if (PS3.getButtonClick(TRIANGLE))
-        output += " - Traingle";
-      if (PS3.getButtonClick(CIRCLE))
-        output += " - Circle";
-      if (PS3.getButtonClick(CROSS))
-        output += " - Cross";
-      if (PS3.getButtonClick(SQUARE))
-        output += " - Square";
-
-      if (PS3.getButtonClick(UP)) {
-        output += " - Up";
-        if (PS3.PS3Connected) {
-          PS3.setLedOff();
-          PS3.setLedOn(LED4);
-        }
-      }
-      if (PS3.getButtonClick(RIGHT)) {
-        output += " - Right";
-        if (PS3.PS3Connected) {
-          PS3.setLedOff();
-          PS3.setLedOn(LED1);
-        }
-      }
-      if (PS3.getButtonClick(DOWN)) {
-        output += " - Down";
-        if (PS3.PS3Connected) {
-          PS3.setLedOff();
-          PS3.setLedOn(LED2);
-        }
-      }
-      if (PS3.getButtonClick(LEFT)) {
-        output += " - Left";
-        if (PS3.PS3Connected) {
-          PS3.setLedOff();
-          PS3.setLedOn(LED3);
-        }
-      }
-
-      if (PS3.getButtonClick(L1))
-        output += " - L1";
-      if (PS3.getButtonClick(L3))
-        output += " - L3";
-      if (PS3.getButtonClick(R1))
-        output += " - R1";
-      if (PS3.getButtonClick(R3))
-        output += " - R3";
-
-      if (PS3.getButtonClick(SELECT)) {
-        output += " - Select";
-      }
-      if (PS3.getButtonClick(START))
-        output += " - Start";
-
-      if (output != "") {
-        String string = "PS3 Controller" + output;
-        Serial.println(string);
-        if (SerialBT.connected)
-          SerialBT.println(string);
-      }
-    }
-    delay(10);
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS4BT/PS4BT.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS4BT/PS4BT.ino
deleted file mode 100644
index c3ba696bd1..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/PS4BT/PS4BT.ino
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- Example sketch for the PS4 Bluetooth library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <PS4BT.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-
-/* You can create the instance of the PS4BT class in two ways */
-// This will start an inquiry and then pair with the PS4 controller - you only have to do this once
-// You will need to hold down the PS and Share button at the same time, the PS4 controller will then start to blink rapidly indicating that it is in paring mode
-PS4BT PS4(&Btd, PAIR);
-
-// After that you can simply create the instance like so and then press the PS button on the device
-//PS4BT PS4(&Btd);
-
-bool printAngle, printTouch;
-uint8_t oldL2Value, oldR2Value;
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); // Halt
-  }
-  Serial.print(F("\r\nPS4 Bluetooth Library Started"));
-}
-void loop() {
-  Usb.Task();
-
-  if (PS4.connected()) {
-    if (PS4.getAnalogHat(LeftHatX) > 137 || PS4.getAnalogHat(LeftHatX) < 117 || PS4.getAnalogHat(LeftHatY) > 137 || PS4.getAnalogHat(LeftHatY) < 117 || PS4.getAnalogHat(RightHatX) > 137 || PS4.getAnalogHat(RightHatX) < 117 || PS4.getAnalogHat(RightHatY) > 137 || PS4.getAnalogHat(RightHatY) < 117) {
-      Serial.print(F("\r\nLeftHatX: "));
-      Serial.print(PS4.getAnalogHat(LeftHatX));
-      Serial.print(F("\tLeftHatY: "));
-      Serial.print(PS4.getAnalogHat(LeftHatY));
-      Serial.print(F("\tRightHatX: "));
-      Serial.print(PS4.getAnalogHat(RightHatX));
-      Serial.print(F("\tRightHatY: "));
-      Serial.print(PS4.getAnalogHat(RightHatY));
-    }
-
-    if (PS4.getAnalogButton(L2) || PS4.getAnalogButton(R2)) { // These are the only analog buttons on the PS4 controller
-      Serial.print(F("\r\nL2: "));
-      Serial.print(PS4.getAnalogButton(L2));
-      Serial.print(F("\tR2: "));
-      Serial.print(PS4.getAnalogButton(R2));
-    }
-    if (PS4.getAnalogButton(L2) != oldL2Value || PS4.getAnalogButton(R2) != oldR2Value) // Only write value if it's different
-      PS4.setRumbleOn(PS4.getAnalogButton(L2), PS4.getAnalogButton(R2));
-    oldL2Value = PS4.getAnalogButton(L2);
-    oldR2Value = PS4.getAnalogButton(R2);
-
-    if (PS4.getButtonClick(PS)) {
-      Serial.print(F("\r\nPS"));
-      PS4.disconnect();
-    }
-    else {
-      if (PS4.getButtonClick(TRIANGLE)) {
-        Serial.print(F("\r\nTraingle"));
-        PS4.setRumbleOn(RumbleLow);
-      }
-      if (PS4.getButtonClick(CIRCLE)) {
-        Serial.print(F("\r\nCircle"));
-        PS4.setRumbleOn(RumbleHigh);
-      }
-      if (PS4.getButtonClick(CROSS)) {
-        Serial.print(F("\r\nCross"));
-        PS4.setLedFlash(10, 10); // Set it to blink rapidly
-      }
-      if (PS4.getButtonClick(SQUARE)) {
-        Serial.print(F("\r\nSquare"));
-        PS4.setLedFlash(0, 0); // Turn off blinking
-      }
-
-      if (PS4.getButtonClick(UP)) {
-        Serial.print(F("\r\nUp"));
-        PS4.setLed(Red);
-      } if (PS4.getButtonClick(RIGHT)) {
-        Serial.print(F("\r\nRight"));
-        PS4.setLed(Blue);
-      } if (PS4.getButtonClick(DOWN)) {
-        Serial.print(F("\r\nDown"));
-        PS4.setLed(Yellow);
-      } if (PS4.getButtonClick(LEFT)) {
-        Serial.print(F("\r\nLeft"));
-        PS4.setLed(Green);
-      }
-
-      if (PS4.getButtonClick(L1))
-        Serial.print(F("\r\nL1"));
-      if (PS4.getButtonClick(L3))
-        Serial.print(F("\r\nL3"));
-      if (PS4.getButtonClick(R1))
-        Serial.print(F("\r\nR1"));
-      if (PS4.getButtonClick(R3))
-        Serial.print(F("\r\nR3"));
-
-      if (PS4.getButtonClick(SHARE))
-        Serial.print(F("\r\nShare"));
-      if (PS4.getButtonClick(OPTIONS)) {
-        Serial.print(F("\r\nOptions"));
-        printAngle = !printAngle;
-      }
-      if (PS4.getButtonClick(TOUCHPAD)) {
-        Serial.print(F("\r\nTouchpad"));
-        printTouch = !printTouch;
-      }
-
-      if (printAngle) { // Print angle calculated using the accelerometer only
-        Serial.print(F("\r\nPitch: "));
-        Serial.print(PS4.getAngle(Pitch));
-        Serial.print(F("\tRoll: "));
-        Serial.print(PS4.getAngle(Roll));
-      }
-
-      if (printTouch) { // Print the x, y coordinates of the touchpad
-        if (PS4.isTouching(0) || PS4.isTouching(1)) // Print newline and carriage return if any of the fingers are touching the touchpad
-          Serial.print(F("\r\n"));
-        for (uint8_t i = 0; i < 2; i++) { // The touchpad track two fingers
-          if (PS4.isTouching(i)) { // Print the position of the finger if it is touching the touchpad
-            Serial.print(F("X")); Serial.print(i + 1); Serial.print(F(": "));
-            Serial.print(PS4.getX(i));
-            Serial.print(F("\tY")); Serial.print(i + 1); Serial.print(F(": "));
-            Serial.print(PS4.getY(i));
-            Serial.print(F("\t"));
-          }
-        }
-      }
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/SPP/SPP.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/SPP/SPP.ino
deleted file mode 100644
index 8fb9c4eca2..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/SPP/SPP.ino
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- Example sketch for the RFCOMM/SPP Bluetooth library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <SPP.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-/* You can create the instance of the class in two ways */
-SPP SerialBT(&Btd); // This will set the name to the defaults: "Arduino" and the pin to "0000"
-//SPP SerialBT(&Btd, "Lauszus's Arduino", "1234"); // You can also set the name and pin like so
-
-bool firstMessage = true;
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nSPP Bluetooth Library Started"));
-}
-void loop() {
-  Usb.Task(); // The SPP data is actually not send until this is called, one could call SerialBT.send() directly as well
-
-  if (SerialBT.connected) {
-    if (firstMessage) {
-      firstMessage = false;
-      SerialBT.println(F("Hello from Arduino")); // Send welcome message
-    }
-    if (Serial.available())
-      SerialBT.write(Serial.read());
-    if (SerialBT.available())
-      Serial.write(SerialBT.read());
-  }
-  else
-    firstMessage = true;
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/SPPMulti/SPPMulti.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/SPPMulti/SPPMulti.ino
deleted file mode 100644
index df521d8e17..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/SPPMulti/SPPMulti.ino
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- Example sketch for the RFCOMM/SPP Bluetooth library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <SPP.h>
-#include <usbhub.h>
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-
-const uint8_t length = 2; // Set the number of instances here
-SPP *SerialBT[length]; // We will use this pointer to store the instances, you can easily make it larger if you like, but it will use a lot of RAM!
-
-bool firstMessage[length] = { true }; // Set all to true
-
-void setup() {
-  for (uint8_t i = 0; i < length; i++)
-    SerialBT[i] = new SPP(&Btd); // This will set the name to the default: "Arduino" and the pin to "0000" for all connections
-
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); // Halt
-  }
-  Serial.print(F("\r\nSPP Bluetooth Library Started"));
-}
-
-void loop() {
-  Usb.Task(); // The SPP data is actually not send until this is called, one could call SerialBT.send() directly as well
-
-  for (uint8_t i = 0; i < length; i++) {
-    if (SerialBT[i]->connected) {
-      if (firstMessage[i]) {
-        firstMessage[i] = false;
-        SerialBT[i]->println(F("Hello from Arduino")); // Send welcome message
-      }
-      if (SerialBT[i]->available())
-        Serial.write(SerialBT[i]->read());
-    }
-    else
-      firstMessage[i] = true;
-  }
-
-  // Set the connection you want to send to using the first character
-  // For instance "0Hello World" would send "Hello World" to connection 0
-  if (Serial.available()) {
-    delay(10); // Wait for the rest of the data to arrive
-    uint8_t id = Serial.read() - '0'; // Convert from ASCII
-    if (id < length && SerialBT[id]->connected) { // Make sure that the id is valid and make sure that a device is actually connected
-      while (Serial.available()) // Check if data is available
-        SerialBT[id]->write(Serial.read()); // Send the data
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/Wii/Wii.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/Wii/Wii.ino
deleted file mode 100644
index b193568163..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/Wii/Wii.ino
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- Example sketch for the Wiimote Bluetooth library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <Wii.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-/* You can create the instance of the class in two ways */
-WII Wii(&Btd, PAIR); // This will start an inquiry and then pair with your Wiimote - you only have to do this once
-//WII Wii(&Btd); // After that you can simply create the instance like so and then press any button on the Wiimote
-
-bool printAngle;
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nWiimote Bluetooth Library Started"));
-}
-void loop() {
-  Usb.Task();
-  if (Wii.wiimoteConnected) {
-    if (Wii.getButtonClick(HOME)) { // You can use getButtonPress to see if the button is held down
-      Serial.print(F("\r\nHOME"));
-      Wii.disconnect();
-    }
-    else {
-      if (Wii.getButtonClick(LEFT)) {
-        Wii.setLedOff();
-        Wii.setLedOn(LED1);
-        Serial.print(F("\r\nLeft"));
-      }
-      if (Wii.getButtonClick(RIGHT)) {
-        Wii.setLedOff();
-        Wii.setLedOn(LED3);
-        Serial.print(F("\r\nRight"));
-      }
-      if (Wii.getButtonClick(DOWN)) {
-        Wii.setLedOff();
-        Wii.setLedOn(LED4);
-        Serial.print(F("\r\nDown"));
-      }
-      if (Wii.getButtonClick(UP)) {
-        Wii.setLedOff();
-        Wii.setLedOn(LED2);
-        Serial.print(F("\r\nUp"));
-      }
-
-      if (Wii.getButtonClick(PLUS))
-        Serial.print(F("\r\nPlus"));
-      if (Wii.getButtonClick(MINUS))
-        Serial.print(F("\r\nMinus"));
-
-      if (Wii.getButtonClick(ONE))
-        Serial.print(F("\r\nOne"));
-      if (Wii.getButtonClick(TWO))
-        Serial.print(F("\r\nTwo"));
-
-      if (Wii.getButtonClick(A)) {
-        printAngle = !printAngle;
-        Serial.print(F("\r\nA"));
-      }
-      if (Wii.getButtonClick(B)) {
-        Wii.setRumbleToggle();
-        Serial.print(F("\r\nB"));
-      }
-    }
-#if 0 // Set this to 1 in order to see the angle of the controllers
-    if (printAngle) {
-      Serial.print(F("\r\nPitch: "));
-      Serial.print(Wii.getPitch());
-      Serial.print(F("\tRoll: "));
-      Serial.print(Wii.getRoll());
-      if (Wii.motionPlusConnected) {
-        Serial.print(F("\tYaw: "));
-        Serial.print(Wii.getYaw());
-      }
-      if (Wii.nunchuckConnected) {
-        Serial.print(F("\tNunchuck Pitch: "));
-        Serial.print(Wii.getNunchuckPitch());
-        Serial.print(F("\tNunchuck Roll: "));
-        Serial.print(Wii.getNunchuckRoll());
-      }
-    }
-#endif
-  }
-#if 0 // Set this to 1 if you are using a Nunchuck controller
-  if (Wii.nunchuckConnected) {
-    if (Wii.getButtonClick(Z))
-      Serial.print(F("\r\nZ"));
-    if (Wii.getButtonClick(C))
-      Serial.print(F("\r\nC"));
-    if (Wii.getAnalogHat(HatX) > 137 ||  Wii.getAnalogHat(HatX) < 117 || Wii.getAnalogHat(HatY) > 137 || Wii.getAnalogHat(HatY) < 117) {
-      Serial.print(F("\r\nHatX: "));
-      Serial.print(Wii.getAnalogHat(HatX));
-      Serial.print(F("\tHatY: "));
-      Serial.print(Wii.getAnalogHat(HatY));
-    }
-  }
-#endif
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiBalanceBoard/WiiBalanceBoard.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiBalanceBoard/WiiBalanceBoard.ino
deleted file mode 100644
index 18c5b411ef..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiBalanceBoard/WiiBalanceBoard.ino
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- Example sketch for the Wii Balance Board Bluetooth library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <Wii.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-/* You can create the instance of the class in two ways */
-WII Wii(&Btd, PAIR); // This will start an inquiry and then pair with your Wii Balance Board - you only have to do this once
-//WII Wii(&Btd); // After that you can simply create the instance like so and then press the power button on the Wii Balance Board
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nWii Balance Board Bluetooth Library Started"));
-}
-void loop() {
-  Usb.Task();
-  if (Wii.wiiBalanceBoardConnected) {
-    Serial.print(F("\r\nWeight: "));
-    for (uint8_t i = 0; i < 4; i++) {
-      Serial.print(Wii.getWeight((BalanceBoardEnum)i));
-      Serial.print(F("\t"));
-    }
-    Serial.print(F("Total Weight: "));
-    Serial.print(Wii.getTotalWeight());
-    if (Wii.getButtonClick(A)) {
-      Serial.print(F("\r\nA"));
-      //Wii.setLedToggle(LED1); // The Wii Balance Board has one LED as well
-      Wii.disconnect();
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiIRCamera/WiiIRCamera.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiIRCamera/WiiIRCamera.ino
deleted file mode 100644
index 573b8bd48c..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiIRCamera/WiiIRCamera.ino
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
-Example sketch for the Wii libary showing the IR camera functionality. This example
-is for the Bluetooth Wii library developed for the USB shield from Circuits@Home
-
-Created by Allan Glover and Kristian Lauszus.
-Contact Kristian:  http://blog.tkjelectronics.dk/ or send an email at kristianl@tkjelectronics.com.
-Contact Allan at adglover9.81@gmail.com
-
-To test the Wiimote IR camera, you will need access to an IR source. Sunlight will work but is not ideal.
-The simpleist solution is to use the Wii sensor bar, i.e. emitter bar, supplied by the Wii system.
-Otherwise, wire up a IR LED yourself.
-*/
-
-#include <Wii.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-#ifndef WIICAMERA // Used to check if WIICAMERA is defined
-#error "Please set ENABLE_WII_IR_CAMERA to 1 in settings.h"
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-/* You can create the instance of the class in two ways */
-WII Wii(&Btd, PAIR); // This will start an inquiry and then pair with your Wiimote - you only have to do this once
-//WII Wii(&Btd); // After the Wiimote pairs once with the line of code above, you can simply create the instance like so and re upload and then press any button on the Wiimote
-
-bool printAngle;
-uint8_t printObjects;
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nWiimote Bluetooth Library Started"));
-}
-
-void loop() {
-  Usb.Task();
-  if (Wii.wiimoteConnected) {
-    if (Wii.getButtonClick(HOME)) { // You can use getButtonPress to see if the button is held down
-      Serial.print(F("\r\nHOME"));
-      Wii.disconnect();
-    }
-    else {
-      if (Wii.getButtonClick(ONE))
-        Wii.IRinitialize(); // Run the initialisation sequence
-      if (Wii.getButtonClick(MINUS) || Wii.getButtonClick(PLUS)) {
-        if (!Wii.isIRCameraEnabled())
-          Serial.print(F("\r\nEnable IR camera first"));
-        else {
-          if (Wii.getButtonPress(MINUS)) { // getButtonClick will only return true once
-            if (printObjects > 0)
-              printObjects--;
-          }
-          else {
-            if (printObjects < 4)
-              printObjects++;
-          }
-          Serial.print(F("\r\nTracking "));
-          Serial.print(printObjects);
-          Serial.print(F(" objects"));
-        }
-      }
-      if (Wii.getButtonClick(A)) {
-        printAngle = !printAngle;
-        Serial.print(F("\r\nA"));
-      }
-      if (Wii.getButtonClick(B)) {
-        Serial.print(F("\r\nBattery level: "));
-        Serial.print(Wii.getBatteryLevel()); // You can get the battery level as well
-      }
-    }
-    if (printObjects > 0) {
-      if (Wii.getIRx1() != 0x3FF || Wii.getIRy1() != 0x3FF || Wii.getIRs1() != 0) { // Only print if the IR camera is actually seeing something
-        Serial.print(F("\r\nx1: "));
-        Serial.print(Wii.getIRx1());
-        Serial.print(F("\ty1: "));
-        Serial.print(Wii.getIRy1());
-        Serial.print(F("\ts1:"));
-        Serial.print(Wii.getIRs1());
-      }
-      if (printObjects > 1) {
-        if (Wii.getIRx2() != 0x3FF || Wii.getIRy2() != 0x3FF || Wii.getIRs2() != 0) {
-          Serial.print(F("\r\nx2: "));
-          Serial.print(Wii.getIRx2());
-          Serial.print(F("\ty2: "));
-          Serial.print(Wii.getIRy2());
-          Serial.print(F("\ts2:"));
-          Serial.print(Wii.getIRs2());
-        }
-        if (printObjects > 2) {
-          if (Wii.getIRx3() != 0x3FF || Wii.getIRy3() != 0x3FF || Wii.getIRs3() != 0) {
-            Serial.print(F("\r\nx3: "));
-            Serial.print(Wii.getIRx3());
-            Serial.print(F("\ty3: "));
-            Serial.print(Wii.getIRy3());
-            Serial.print(F("\ts3:"));
-            Serial.print(Wii.getIRs3());
-          }
-          if (printObjects > 3) {
-            if (Wii.getIRx4() != 0x3FF || Wii.getIRy4() != 0x3FF || Wii.getIRs4() != 0) {
-              Serial.print(F("\r\nx4: "));
-              Serial.print(Wii.getIRx4());
-              Serial.print(F("\ty4: "));
-              Serial.print(Wii.getIRy4());
-              Serial.print(F("\ts4:"));
-              Serial.print(Wii.getIRs4());
-            }
-          }
-        }
-      }
-    }
-    if (printAngle) { // There is no extension bytes available, so the MotionPlus or Nunchuck can't be read
-      Serial.print(F("\r\nPitch: "));
-      Serial.print(Wii.getPitch());
-      Serial.print(F("\tRoll: "));
-      Serial.print(Wii.getRoll());
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiMulti/WiiMulti.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiMulti/WiiMulti.ino
deleted file mode 100644
index 07c6f13d2b..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiMulti/WiiMulti.ino
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- Example sketch for the Wiimote Bluetooth library - developed by Kristian Lauszus
- This example show how one can use multiple controllers with the library
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <Wii.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-WII *Wii[2]; // We will use this pointer to store the two instance, you can easily make it larger if you like, but it will use a lot of RAM!
-const uint8_t length = sizeof(Wii) / sizeof(Wii[0]); // Get the lenght of the array
-bool printAngle[length];
-bool oldControllerState[length];
-
-void setup() {
-  for (uint8_t i = 0; i < length; i++) {
-    Wii[i] = new WII(&Btd); // You will have to pair each controller with the dongle before you can define the instances like so, just add PAIR as the second argument
-    Wii[i]->attachOnInit(onInit); // onInit() is called upon a new connection - you can call the function whatever you like
-  }
-
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nWiimote Bluetooth Library Started"));
-}
-void loop() {
-  Usb.Task();
-
-  for (uint8_t i = 0; i < length; i++) {
-    if (Wii[i]->wiimoteConnected) {
-      if (Wii[i]->getButtonClick(HOME)) { // You can use getButtonPress to see if the button is held down
-        Serial.print(F("\r\nHOME"));
-        Wii[i]->disconnect();
-        oldControllerState[i] = false; // Reset value
-      }
-      else {
-        if (Wii[i]->getButtonClick(LEFT)) {
-          Wii[i]->setLedOff();
-          Wii[i]->setLedOn(LED1);
-          Serial.print(F("\r\nLeft"));
-        }
-        if (Wii[i]->getButtonClick(RIGHT)) {
-          Wii[i]->setLedOff();
-          Wii[i]->setLedOn(LED3);
-          Serial.print(F("\r\nRight"));
-        }
-        if (Wii[i]->getButtonClick(DOWN)) {
-          Wii[i]->setLedOff();
-          Wii[i]->setLedOn(LED4);
-          Serial.print(F("\r\nDown"));
-        }
-        if (Wii[i]->getButtonClick(UP)) {
-          Wii[i]->setLedOff();
-          Wii[i]->setLedOn(LED2);
-          Serial.print(F("\r\nUp"));
-        }
-
-        if (Wii[i]->getButtonClick(PLUS))
-          Serial.print(F("\r\nPlus"));
-        if (Wii[i]->getButtonClick(MINUS))
-          Serial.print(F("\r\nMinus"));
-
-        if (Wii[i]->getButtonClick(ONE))
-          Serial.print(F("\r\nOne"));
-        if (Wii[i]->getButtonClick(TWO))
-          Serial.print(F("\r\nTwo"));
-
-        if (Wii[i]->getButtonClick(A)) {
-          printAngle[i] = !printAngle[i];
-          Serial.print(F("\r\nA"));
-        }
-        if (Wii[i]->getButtonClick(B)) {
-          Wii[i]->setRumbleToggle();
-          Serial.print(F("\r\nB"));
-        }
-      }
-      if (printAngle[i]) {
-        Serial.print(F("\r\nPitch: "));
-        Serial.print(Wii[i]->getPitch());
-        Serial.print(F("\tRoll: "));
-        Serial.print(Wii[i]->getRoll());
-        if (Wii[i]->motionPlusConnected) {
-          Serial.print(F("\tYaw: "));
-          Serial.print(Wii[i]->getYaw());
-        }
-        if (Wii[i]->nunchuckConnected) {
-          Serial.print(F("\tNunchuck Pitch: "));
-          Serial.print(Wii[i]->getNunchuckPitch());
-          Serial.print(F("\tNunchuck Roll: "));
-          Serial.print(Wii[i]->getNunchuckRoll());
-        }
-      }
-    }
-    if (Wii[i]->nunchuckConnected) {
-      if (Wii[i]->getButtonClick(Z))
-        Serial.print(F("\r\nZ"));
-      if (Wii[i]->getButtonClick(C))
-        Serial.print(F("\r\nC"));
-      if (Wii[i]->getAnalogHat(HatX) > 137 ||  Wii[i]->getAnalogHat(HatX) < 117 || Wii[i]->getAnalogHat(HatY) > 137 || Wii[i]->getAnalogHat(HatY) < 117) {
-        Serial.print(F("\r\nHatX: "));
-        Serial.print(Wii[i]->getAnalogHat(HatX));
-        Serial.print(F("\tHatY: "));
-        Serial.print(Wii[i]->getAnalogHat(HatY));
-      }
-    }
-  }
-}
-
-void onInit() {
-  for (uint8_t i = 0; i < length; i++) {
-    if (Wii[i]->wiimoteConnected && !oldControllerState[i]) {
-      oldControllerState[i] = true; // Used to check which is the new controller
-      Wii[i]->setLedOn((LEDEnum)(i + 1)); // Cast directly to LEDEnum - see: "controllerEnums.h"
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiUProController/WiiUProController.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiUProController/WiiUProController.ino
deleted file mode 100644
index ab35a27479..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Bluetooth/WiiUProController/WiiUProController.ino
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- Example sketch for the Wiimote Bluetooth library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <Wii.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub Hub1(&Usb); // Some dongles have a hub inside
-
-BTD Btd(&Usb); // You have to create the Bluetooth Dongle instance like so
-/* You can create the instance of the class in two ways */
-WII Wii(&Btd, PAIR); // This will start an inquiry and then pair with your Wiimote - you only have to do this once
-//WII Wii(&Btd); // After that you can simply create the instance like so and then press any button on the Wiimote
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nWiimote Bluetooth Library Started"));
-}
-void loop() {
-  Usb.Task();
-  if (Wii.wiiUProControllerConnected) {
-    if (Wii.getButtonClick(HOME)) { // You can use getButtonPress to see if the button is held down
-      Serial.print(F("\r\nHome"));
-      Wii.disconnect();
-    }
-    else {
-      if (Wii.getButtonClick(LEFT)) {
-        Wii.setLedOff();
-        Wii.setLedOn(LED1);
-        Serial.print(F("\r\nLeft"));
-      }
-      if (Wii.getButtonClick(RIGHT)) {
-        Wii.setLedOff();
-        Wii.setLedOn(LED3);
-        Serial.print(F("\r\nRight"));
-      }
-      if (Wii.getButtonClick(DOWN)) {
-        Wii.setLedOff();
-        Wii.setLedOn(LED4);
-        Serial.print(F("\r\nDown"));
-      }
-      if (Wii.getButtonClick(UP)) {
-        Wii.setLedOff();
-        Wii.setLedOn(LED2);
-        Serial.print(F("\r\nUp"));
-      }
-
-      if (Wii.getButtonClick(PLUS))
-        Serial.print(F("\r\nPlus"));
-      if (Wii.getButtonClick(MINUS))
-        Serial.print(F("\r\nMinus"));
-
-      if (Wii.getButtonClick(A))
-        Serial.print(F("\r\nA"));
-      if (Wii.getButtonClick(B)) {
-        Wii.setRumbleToggle();
-        Serial.print(F("\r\nB"));
-      }
-      if (Wii.getButtonClick(X))
-        Serial.print(F("\r\nX"));
-      if (Wii.getButtonClick(Y))
-        Serial.print(F("\r\nY"));
-
-      if (Wii.getButtonClick(L))
-        Serial.print(F("\r\nL"));
-      if (Wii.getButtonClick(R))
-        Serial.print(F("\r\nR"));
-      if (Wii.getButtonClick(ZL))
-        Serial.print(F("\r\nZL"));
-      if (Wii.getButtonClick(ZR))
-        Serial.print(F("\r\nZR"));
-      if (Wii.getButtonClick(L3))
-        Serial.print(F("\r\nL3"));
-      if (Wii.getButtonClick(R3))
-        Serial.print(F("\r\nR3"));
-    }
-    if (Wii.getAnalogHat(LeftHatX) > 2200 || Wii.getAnalogHat(LeftHatX) < 1800 || Wii.getAnalogHat(LeftHatY) > 2200 || Wii.getAnalogHat(LeftHatY) < 1800 || Wii.getAnalogHat(RightHatX) > 2200 ||  Wii.getAnalogHat(RightHatX) < 1800 || Wii.getAnalogHat(RightHatY) > 2200 || Wii.getAnalogHat(RightHatY) < 1800) {
-      Serial.print(F("\r\nLeftHatX: "));
-      Serial.print(Wii.getAnalogHat(LeftHatX));
-      Serial.print(F("\tLeftHatY: "));
-      Serial.print(Wii.getAnalogHat(LeftHatY));
-      Serial.print(F("\tRightHatX: "));
-      Serial.print(Wii.getAnalogHat(RightHatX));
-      Serial.print(F("\tRightHatY: "));
-      Serial.print(Wii.getAnalogHat(RightHatY));
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDBootKbd/USBHIDBootKbd.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDBootKbd/USBHIDBootKbd.ino
deleted file mode 100644
index 48b33abfd2..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDBootKbd/USBHIDBootKbd.ino
+++ /dev/null
@@ -1,129 +0,0 @@
-#include <hidboot.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class KbdRptParser : public KeyboardReportParser
-{
-    void PrintKey(uint8_t mod, uint8_t key);
-
-  protected:
-    void OnControlKeysChanged(uint8_t before, uint8_t after);
-
-    void OnKeyDown	(uint8_t mod, uint8_t key);
-    void OnKeyUp	(uint8_t mod, uint8_t key);
-    void OnKeyPressed(uint8_t key);
-};
-
-void KbdRptParser::PrintKey(uint8_t m, uint8_t key)
-{
-  MODIFIERKEYS mod;
-  *((uint8_t*)&mod) = m;
-  Serial.print((mod.bmLeftCtrl   == 1) ? "C" : " ");
-  Serial.print((mod.bmLeftShift  == 1) ? "S" : " ");
-  Serial.print((mod.bmLeftAlt    == 1) ? "A" : " ");
-  Serial.print((mod.bmLeftGUI    == 1) ? "G" : " ");
-
-  Serial.print(" >");
-  PrintHex<uint8_t>(key, 0x80);
-  Serial.print("< ");
-
-  Serial.print((mod.bmRightCtrl   == 1) ? "C" : " ");
-  Serial.print((mod.bmRightShift  == 1) ? "S" : " ");
-  Serial.print((mod.bmRightAlt    == 1) ? "A" : " ");
-  Serial.println((mod.bmRightGUI    == 1) ? "G" : " ");
-};
-
-void KbdRptParser::OnKeyDown(uint8_t mod, uint8_t key)
-{
-  Serial.print("DN ");
-  PrintKey(mod, key);
-  uint8_t c = OemToAscii(mod, key);
-
-  if (c)
-    OnKeyPressed(c);
-}
-
-void KbdRptParser::OnControlKeysChanged(uint8_t before, uint8_t after) {
-
-  MODIFIERKEYS beforeMod;
-  *((uint8_t*)&beforeMod) = before;
-
-  MODIFIERKEYS afterMod;
-  *((uint8_t*)&afterMod) = after;
-
-  if (beforeMod.bmLeftCtrl != afterMod.bmLeftCtrl) {
-    Serial.println("LeftCtrl changed");
-  }
-  if (beforeMod.bmLeftShift != afterMod.bmLeftShift) {
-    Serial.println("LeftShift changed");
-  }
-  if (beforeMod.bmLeftAlt != afterMod.bmLeftAlt) {
-    Serial.println("LeftAlt changed");
-  }
-  if (beforeMod.bmLeftGUI != afterMod.bmLeftGUI) {
-    Serial.println("LeftGUI changed");
-  }
-
-  if (beforeMod.bmRightCtrl != afterMod.bmRightCtrl) {
-    Serial.println("RightCtrl changed");
-  }
-  if (beforeMod.bmRightShift != afterMod.bmRightShift) {
-    Serial.println("RightShift changed");
-  }
-  if (beforeMod.bmRightAlt != afterMod.bmRightAlt) {
-    Serial.println("RightAlt changed");
-  }
-  if (beforeMod.bmRightGUI != afterMod.bmRightGUI) {
-    Serial.println("RightGUI changed");
-  }
-
-}
-
-void KbdRptParser::OnKeyUp(uint8_t mod, uint8_t key)
-{
-  Serial.print("UP ");
-  PrintKey(mod, key);
-}
-
-void KbdRptParser::OnKeyPressed(uint8_t key)
-{
-  Serial.print("ASCII: ");
-  Serial.println((char)key);
-};
-
-USB     Usb;
-//USBHub     Hub(&Usb);
-HIDBoot<HID_PROTOCOL_KEYBOARD>    HidKeyboard(&Usb);
-
-uint32_t next_time;
-
-KbdRptParser Prs;
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-    Serial.println("OSC did not start.");
-
-  delay( 200 );
-
-  next_time = millis() + 5000;
-
-  HidKeyboard.SetReportParser(0, (HIDReportParser*)&Prs);
-}
-
-void loop()
-{
-  Usb.Task();
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDBootKbdAndMouse/USBHIDBootKbdAndMouse.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDBootKbdAndMouse/USBHIDBootKbdAndMouse.ino
deleted file mode 100644
index 5fc8c96fc9..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDBootKbdAndMouse/USBHIDBootKbdAndMouse.ino
+++ /dev/null
@@ -1,178 +0,0 @@
-#include <hidboot.h>
-#include <usbhub.h>
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class MouseRptParser : public MouseReportParser
-{
-  protected:
-    void OnMouseMove(MOUSEINFO *mi);
-    void OnLeftButtonUp(MOUSEINFO *mi);
-    void OnLeftButtonDown(MOUSEINFO *mi);
-    void OnRightButtonUp(MOUSEINFO *mi);
-    void OnRightButtonDown(MOUSEINFO *mi);
-    void OnMiddleButtonUp(MOUSEINFO *mi);
-    void OnMiddleButtonDown(MOUSEINFO *mi);
-};
-void MouseRptParser::OnMouseMove(MOUSEINFO *mi)
-{
-  Serial.print("dx=");
-  Serial.print(mi->dX, DEC);
-  Serial.print(" dy=");
-  Serial.println(mi->dY, DEC);
-};
-void MouseRptParser::OnLeftButtonUp	(MOUSEINFO *mi)
-{
-  Serial.println("L Butt Up");
-};
-void MouseRptParser::OnLeftButtonDown	(MOUSEINFO *mi)
-{
-  Serial.println("L Butt Dn");
-};
-void MouseRptParser::OnRightButtonUp	(MOUSEINFO *mi)
-{
-  Serial.println("R Butt Up");
-};
-void MouseRptParser::OnRightButtonDown	(MOUSEINFO *mi)
-{
-  Serial.println("R Butt Dn");
-};
-void MouseRptParser::OnMiddleButtonUp	(MOUSEINFO *mi)
-{
-  Serial.println("M Butt Up");
-};
-void MouseRptParser::OnMiddleButtonDown	(MOUSEINFO *mi)
-{
-  Serial.println("M Butt Dn");
-};
-
-class KbdRptParser : public KeyboardReportParser
-{
-    void PrintKey(uint8_t mod, uint8_t key);
-
-  protected:
-    void OnControlKeysChanged(uint8_t before, uint8_t after);
-    void OnKeyDown	(uint8_t mod, uint8_t key);
-    void OnKeyUp	(uint8_t mod, uint8_t key);
-    void OnKeyPressed(uint8_t key);
-};
-
-void KbdRptParser::PrintKey(uint8_t m, uint8_t key)
-{
-  MODIFIERKEYS mod;
-  *((uint8_t*)&mod) = m;
-  Serial.print((mod.bmLeftCtrl   == 1) ? "C" : " ");
-  Serial.print((mod.bmLeftShift  == 1) ? "S" : " ");
-  Serial.print((mod.bmLeftAlt    == 1) ? "A" : " ");
-  Serial.print((mod.bmLeftGUI    == 1) ? "G" : " ");
-
-  Serial.print(" >");
-  PrintHex<uint8_t>(key, 0x80);
-  Serial.print("< ");
-
-  Serial.print((mod.bmRightCtrl   == 1) ? "C" : " ");
-  Serial.print((mod.bmRightShift  == 1) ? "S" : " ");
-  Serial.print((mod.bmRightAlt    == 1) ? "A" : " ");
-  Serial.println((mod.bmRightGUI    == 1) ? "G" : " ");
-};
-
-void KbdRptParser::OnKeyDown(uint8_t mod, uint8_t key)
-{
-  Serial.print("DN ");
-  PrintKey(mod, key);
-  uint8_t c = OemToAscii(mod, key);
-
-  if (c)
-    OnKeyPressed(c);
-}
-
-void KbdRptParser::OnControlKeysChanged(uint8_t before, uint8_t after) {
-
-  MODIFIERKEYS beforeMod;
-  *((uint8_t*)&beforeMod) = before;
-
-  MODIFIERKEYS afterMod;
-  *((uint8_t*)&afterMod) = after;
-
-  if (beforeMod.bmLeftCtrl != afterMod.bmLeftCtrl) {
-    Serial.println("LeftCtrl changed");
-  }
-  if (beforeMod.bmLeftShift != afterMod.bmLeftShift) {
-    Serial.println("LeftShift changed");
-  }
-  if (beforeMod.bmLeftAlt != afterMod.bmLeftAlt) {
-    Serial.println("LeftAlt changed");
-  }
-  if (beforeMod.bmLeftGUI != afterMod.bmLeftGUI) {
-    Serial.println("LeftGUI changed");
-  }
-
-  if (beforeMod.bmRightCtrl != afterMod.bmRightCtrl) {
-    Serial.println("RightCtrl changed");
-  }
-  if (beforeMod.bmRightShift != afterMod.bmRightShift) {
-    Serial.println("RightShift changed");
-  }
-  if (beforeMod.bmRightAlt != afterMod.bmRightAlt) {
-    Serial.println("RightAlt changed");
-  }
-  if (beforeMod.bmRightGUI != afterMod.bmRightGUI) {
-    Serial.println("RightGUI changed");
-  }
-
-}
-
-void KbdRptParser::OnKeyUp(uint8_t mod, uint8_t key)
-{
-  Serial.print("UP ");
-  PrintKey(mod, key);
-}
-
-void KbdRptParser::OnKeyPressed(uint8_t key)
-{
-  Serial.print("ASCII: ");
-  Serial.println((char)key);
-};
-
-USB     Usb;
-USBHub     Hub(&Usb);
-
-HIDBoot < HID_PROTOCOL_KEYBOARD | HID_PROTOCOL_MOUSE > HidComposite(&Usb);
-HIDBoot<HID_PROTOCOL_KEYBOARD>    HidKeyboard(&Usb);
-HIDBoot<HID_PROTOCOL_MOUSE>    HidMouse(&Usb);
-
-//uint32_t next_time;
-
-KbdRptParser KbdPrs;
-MouseRptParser MousePrs;
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-    Serial.println("OSC did not start.");
-
-  delay( 200 );
-
-  //next_time = millis() + 5000;
-
-  HidComposite.SetReportParser(0, (HIDReportParser*)&KbdPrs);
-  HidComposite.SetReportParser(1, (HIDReportParser*)&MousePrs);
-  HidKeyboard.SetReportParser(0, (HIDReportParser*)&KbdPrs);
-  HidMouse.SetReportParser(0, (HIDReportParser*)&MousePrs);
-}
-
-void loop()
-{
-  Usb.Task();
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDBootMouse/USBHIDBootMouse.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDBootMouse/USBHIDBootMouse.ino
deleted file mode 100644
index 53102512bd..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDBootMouse/USBHIDBootMouse.ino
+++ /dev/null
@@ -1,83 +0,0 @@
-#include <hidboot.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class MouseRptParser : public MouseReportParser
-{
-protected:
-	void OnMouseMove	(MOUSEINFO *mi);
-	void OnLeftButtonUp	(MOUSEINFO *mi);
-	void OnLeftButtonDown	(MOUSEINFO *mi);
-	void OnRightButtonUp	(MOUSEINFO *mi);
-	void OnRightButtonDown	(MOUSEINFO *mi);
-	void OnMiddleButtonUp	(MOUSEINFO *mi);
-	void OnMiddleButtonDown	(MOUSEINFO *mi);
-};
-void MouseRptParser::OnMouseMove(MOUSEINFO *mi)
-{
-    Serial.print("dx=");
-    Serial.print(mi->dX, DEC);
-    Serial.print(" dy=");
-    Serial.println(mi->dY, DEC);
-};
-void MouseRptParser::OnLeftButtonUp	(MOUSEINFO *mi)
-{
-    Serial.println("L Butt Up");
-};
-void MouseRptParser::OnLeftButtonDown	(MOUSEINFO *mi)
-{
-    Serial.println("L Butt Dn");
-};
-void MouseRptParser::OnRightButtonUp	(MOUSEINFO *mi)
-{
-    Serial.println("R Butt Up");
-};
-void MouseRptParser::OnRightButtonDown	(MOUSEINFO *mi)
-{
-    Serial.println("R Butt Dn");
-};
-void MouseRptParser::OnMiddleButtonUp	(MOUSEINFO *mi)
-{
-    Serial.println("M Butt Up");
-};
-void MouseRptParser::OnMiddleButtonDown	(MOUSEINFO *mi)
-{
-    Serial.println("M Butt Dn");
-};
-
-USB     Usb;
-USBHub     Hub(&Usb);
-HIDBoot<HID_PROTOCOL_MOUSE>    HidMouse(&Usb);
-
-uint32_t next_time;
-
-MouseRptParser                               Prs;
-
-void setup()
-{
-    Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-    while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-    Serial.println("Start");
-
-    if (Usb.Init() == -1)
-        Serial.println("OSC did not start.");
-
-    delay( 200 );
-
-    next_time = millis() + 5000;
-
-    HidMouse.SetReportParser(0,(HIDReportParser*)&Prs);
-}
-
-void loop()
-{
-  Usb.Task();
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDJoystick/USBHIDJoystick.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDJoystick/USBHIDJoystick.ino
deleted file mode 100644
index 956441d67a..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDJoystick/USBHIDJoystick.ino
+++ /dev/null
@@ -1,38 +0,0 @@
-#include <hid.h>
-#include <hiduniversal.h>
-#include <usbhub.h>
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-#include "hidjoystickrptparser.h"
-
-USB Usb;
-USBHub Hub(&Usb);
-HIDUniversal Hid(&Usb);
-JoystickEvents JoyEvents;
-JoystickReportParser Joy(&JoyEvents);
-
-void setup() {
-        Serial.begin(115200);
-#if !defined(__MIPSEL__)
-        while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-        Serial.println("Start");
-
-        if (Usb.Init() == -1)
-                Serial.println("OSC did not start.");
-
-        delay(200);
-
-        if (!Hid.SetReportParser(0, &Joy))
-                ErrorMessage<uint8_t > (PSTR("SetReportParser"), 1);
-}
-
-void loop() {
-        Usb.Task();
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDJoystick/hidjoystickrptparser.cpp b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDJoystick/hidjoystickrptparser.cpp
deleted file mode 100644
index 083b95cac5..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDJoystick/hidjoystickrptparser.cpp
+++ /dev/null
@@ -1,84 +0,0 @@
-#include "hidjoystickrptparser.h"
-
-JoystickReportParser::JoystickReportParser(JoystickEvents *evt) :
-joyEvents(evt),
-oldHat(0xDE),
-oldButtons(0) {
-        for (uint8_t i = 0; i < RPT_GEMEPAD_LEN; i++)
-                oldPad[i] = 0xD;
-}
-
-void JoystickReportParser::Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf) {
-        bool match = true;
-
-        // Checking if there are changes in report since the method was last called
-        for (uint8_t i = 0; i < RPT_GEMEPAD_LEN; i++)
-                if (buf[i] != oldPad[i]) {
-                        match = false;
-                        break;
-                }
-
-        // Calling Game Pad event handler
-        if (!match && joyEvents) {
-                joyEvents->OnGamePadChanged((const GamePadEventData*)buf);
-
-                for (uint8_t i = 0; i < RPT_GEMEPAD_LEN; i++) oldPad[i] = buf[i];
-        }
-
-        uint8_t hat = (buf[5] & 0xF);
-
-        // Calling Hat Switch event handler
-        if (hat != oldHat && joyEvents) {
-                joyEvents->OnHatSwitch(hat);
-                oldHat = hat;
-        }
-
-        uint16_t buttons = (0x0000 | buf[6]);
-        buttons <<= 4;
-        buttons |= (buf[5] >> 4);
-        uint16_t changes = (buttons ^ oldButtons);
-
-        // Calling Button Event Handler for every button changed
-        if (changes) {
-                for (uint8_t i = 0; i < 0x0C; i++) {
-                        uint16_t mask = (0x0001 << i);
-
-                        if (((mask & changes) > 0) && joyEvents)
-                                if ((buttons & mask) > 0)
-                                        joyEvents->OnButtonDn(i + 1);
-                                else
-                                        joyEvents->OnButtonUp(i + 1);
-                }
-                oldButtons = buttons;
-        }
-}
-
-void JoystickEvents::OnGamePadChanged(const GamePadEventData *evt) {
-        Serial.print("X1: ");
-        PrintHex<uint8_t > (evt->X, 0x80);
-        Serial.print("\tY1: ");
-        PrintHex<uint8_t > (evt->Y, 0x80);
-        Serial.print("\tX2: ");
-        PrintHex<uint8_t > (evt->Z1, 0x80);
-        Serial.print("\tY2: ");
-        PrintHex<uint8_t > (evt->Z2, 0x80);
-        Serial.print("\tRz: ");
-        PrintHex<uint8_t > (evt->Rz, 0x80);
-        Serial.println("");
-}
-
-void JoystickEvents::OnHatSwitch(uint8_t hat) {
-        Serial.print("Hat Switch: ");
-        PrintHex<uint8_t > (hat, 0x80);
-        Serial.println("");
-}
-
-void JoystickEvents::OnButtonUp(uint8_t but_id) {
-        Serial.print("Up: ");
-        Serial.println(but_id, DEC);
-}
-
-void JoystickEvents::OnButtonDn(uint8_t but_id) {
-        Serial.print("Dn: ");
-        Serial.println(but_id, DEC);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDJoystick/hidjoystickrptparser.h b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDJoystick/hidjoystickrptparser.h
deleted file mode 100644
index 733b8f8da8..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHIDJoystick/hidjoystickrptparser.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#if !defined(__HIDJOYSTICKRPTPARSER_H__)
-#define __HIDJOYSTICKRPTPARSER_H__
-
-#include <hid.h>
-
-struct GamePadEventData {
-        uint8_t X, Y, Z1, Z2, Rz;
-};
-
-class JoystickEvents {
-public:
-        virtual void OnGamePadChanged(const GamePadEventData *evt);
-        virtual void OnHatSwitch(uint8_t hat);
-        virtual void OnButtonUp(uint8_t but_id);
-        virtual void OnButtonDn(uint8_t but_id);
-};
-
-#define RPT_GEMEPAD_LEN		5
-
-class JoystickReportParser : public HIDReportParser {
-        JoystickEvents *joyEvents;
-
-        uint8_t oldPad[RPT_GEMEPAD_LEN];
-        uint8_t oldHat;
-        uint16_t oldButtons;
-
-public:
-        JoystickReportParser(JoystickEvents *evt);
-
-        virtual void Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf);
-};
-
-#endif // __HIDJOYSTICKRPTPARSER_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHID_desc/USBHID_desc.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHID_desc/USBHID_desc.ino
deleted file mode 100644
index 85cfc19a2e..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHID_desc/USBHID_desc.ino
+++ /dev/null
@@ -1,77 +0,0 @@
-#include <hid.h>
-#include <hiduniversal.h>
-#include <hidescriptorparser.h>
-#include <usbhub.h>
-#include "pgmstrings.h"
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class HIDUniversal2 : public HIDUniversal
-{
-public:
-    HIDUniversal2(USB *usb) : HIDUniversal(usb) {};
-
-protected:
-    uint8_t OnInitSuccessful();
-};
-
-uint8_t HIDUniversal2::OnInitSuccessful()
-{
-    uint8_t    rcode;
-
-    HexDumper<USBReadParser, uint16_t, uint16_t>    Hex;
-    ReportDescParser                                Rpt;
-
-    if ((rcode = GetReportDescr(0, &Hex)))
-        goto FailGetReportDescr1;
-
-    if ((rcode = GetReportDescr(0, &Rpt)))
-	goto FailGetReportDescr2;
-
-    return 0;
-
-FailGetReportDescr1:
-    USBTRACE("GetReportDescr1:");
-    goto Fail;
-
-FailGetReportDescr2:
-    USBTRACE("GetReportDescr2:");
-    goto Fail;
-
-Fail:
-    Serial.println(rcode, HEX);
-    Release();
-    return rcode;
-}
-
-USB Usb;
-//USBHub Hub(&Usb);
-HIDUniversal2 Hid(&Usb);
-UniversalReportParser Uni;
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-      Serial.println("OSC did not start.");
-
-  delay( 200 );
-
-  if (!Hid.SetReportParser(0, &Uni))
-      ErrorMessage<uint8_t>(PSTR("SetReportParser"), 1  );
-}
-
-void loop()
-{
-    Usb.Task();
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHID_desc/pgmstrings.h b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHID_desc/pgmstrings.h
deleted file mode 100644
index bdb0077ecc..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/USBHID_desc/pgmstrings.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#if !defined(__PGMSTRINGS_H__)
-#define __PGMSTRINGS_H__
-
-#define LOBYTE(x) ((char*)(&(x)))[0]
-#define HIBYTE(x) ((char*)(&(x)))[1]
-#define BUFSIZE 256    //buffer size
- 
-
-/* Print strings in Program Memory */
-const char Gen_Error_str[] PROGMEM = "\r\nRequest error. Error code:\t"; 
-const char Dev_Header_str[] PROGMEM ="\r\nDevice descriptor: ";
-const char Dev_Length_str[] PROGMEM ="\r\nDescriptor Length:\t";
-const char Dev_Type_str[] PROGMEM ="\r\nDescriptor type:\t";
-const char Dev_Version_str[] PROGMEM ="\r\nUSB version:\t\t";
-const char Dev_Class_str[] PROGMEM ="\r\nDevice class:\t\t";
-const char Dev_Subclass_str[] PROGMEM ="\r\nDevice Subclass:\t";
-const char Dev_Protocol_str[] PROGMEM ="\r\nDevice Protocol:\t";
-const char Dev_Pktsize_str[] PROGMEM ="\r\nMax.packet size:\t";
-const char Dev_Vendor_str[] PROGMEM ="\r\nVendor  ID:\t\t";
-const char Dev_Product_str[] PROGMEM ="\r\nProduct ID:\t\t";
-const char Dev_Revision_str[] PROGMEM ="\r\nRevision ID:\t\t";
-const char Dev_Mfg_str[] PROGMEM ="\r\nMfg.string index:\t";
-const char Dev_Prod_str[] PROGMEM ="\r\nProd.string index:\t";
-const char Dev_Serial_str[] PROGMEM ="\r\nSerial number index:\t";
-const char Dev_Nconf_str[] PROGMEM ="\r\nNumber of conf.:\t";
-const char Conf_Trunc_str[] PROGMEM ="Total length truncated to 256 bytes";
-const char Conf_Header_str[] PROGMEM ="\r\nConfiguration descriptor:";
-const char Conf_Totlen_str[] PROGMEM ="\r\nTotal length:\t\t";
-const char Conf_Nint_str[] PROGMEM ="\r\nNum.intf:\t\t";
-const char Conf_Value_str[] PROGMEM ="\r\nConf.value:\t\t";
-const char Conf_String_str[] PROGMEM ="\r\nConf.string:\t\t";
-const char Conf_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char Conf_Pwr_str[] PROGMEM ="\r\nMax.pwr:\t\t";
-const char Int_Header_str[] PROGMEM ="\r\n\r\nInterface descriptor:";
-const char Int_Number_str[] PROGMEM ="\r\nIntf.number:\t\t";
-const char Int_Alt_str[] PROGMEM ="\r\nAlt.:\t\t\t";
-const char Int_Endpoints_str[] PROGMEM ="\r\nEndpoints:\t\t";
-const char Int_Class_str[] PROGMEM ="\r\nIntf. Class:\t\t";
-const char Int_Subclass_str[] PROGMEM ="\r\nIntf. Subclass:\t\t";
-const char Int_Protocol_str[] PROGMEM ="\r\nIntf. Protocol:\t\t";
-const char Int_String_str[] PROGMEM ="\r\nIntf.string:\t\t";
-const char End_Header_str[] PROGMEM ="\r\n\r\nEndpoint descriptor:";
-const char End_Address_str[] PROGMEM ="\r\nEndpoint address:\t";
-const char End_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char End_Pktsize_str[] PROGMEM ="\r\nMax.pkt size:\t\t";
-const char End_Interval_str[] PROGMEM ="\r\nPolling interval:\t";
-const char Unk_Header_str[] PROGMEM = "\r\nUnknown descriptor:";
-const char Unk_Length_str[] PROGMEM ="\r\nLength:\t\t";
-const char Unk_Type_str[] PROGMEM ="\r\nType:\t\t";
-const char Unk_Contents_str[] PROGMEM ="\r\nContents:\t";
- 
-#endif // __PGMSTRINGS_H__
\ No newline at end of file
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/le3dp/le3dp.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/le3dp/le3dp.ino
deleted file mode 100644
index 837d7f5a70..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/le3dp/le3dp.ino
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Simplified Logitech Extreme 3D Pro Joystick Report Parser */
-
-#include <hid.h>
-#include <hiduniversal.h>
-#include <usbhub.h>
-
-#include "le3dp_rptparser.h"
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB                                             Usb;
-USBHub                                          Hub(&Usb);
-HIDUniversal                                    Hid(&Usb);
-JoystickEvents                                  JoyEvents;
-JoystickReportParser                            Joy(&JoyEvents);
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-      Serial.println("OSC did not start.");
-
-  delay( 200 );
-
-  if (!Hid.SetReportParser(0, &Joy))
-      ErrorMessage<uint8_t>(PSTR("SetReportParser"), 1  );
-}
-
-void loop()
-{
-    Usb.Task();
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/le3dp/le3dp_rptparser.cpp b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/le3dp/le3dp_rptparser.cpp
deleted file mode 100644
index baece13b2c..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/le3dp/le3dp_rptparser.cpp
+++ /dev/null
@@ -1,43 +0,0 @@
-#include "le3dp_rptparser.h"
-
-JoystickReportParser::JoystickReportParser(JoystickEvents *evt) :
-	joyEvents(evt)
-{}
-
-void JoystickReportParser::Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf)
-{
-	bool match = true;
-
-	// Checking if there are changes in report since the method was last called
-	for (uint8_t i=0; i<RPT_GAMEPAD_LEN; i++) {
-		if( buf[i] != oldPad[i] ) {
-			match = false;
-			break;
-		}
-  }
-  	// Calling Game Pad event handler
-	if (!match && joyEvents) {
-		joyEvents->OnGamePadChanged((const GamePadEventData*)buf);
-
-		for (uint8_t i=0; i<RPT_GAMEPAD_LEN; i++) oldPad[i] = buf[i];
-	}
-}
-
-void JoystickEvents::OnGamePadChanged(const GamePadEventData *evt)
-{
-	Serial.print("X: ");
-	PrintHex<uint16_t>(evt->x, 0x80);
-	Serial.print(" Y: ");
-	PrintHex<uint16_t>(evt->y, 0x80);
-	Serial.print(" Hat Switch: ");
-	PrintHex<uint8_t>(evt->hat, 0x80);
-	Serial.print(" Twist: ");
-	PrintHex<uint8_t>(evt->twist, 0x80);
-	Serial.print(" Slider: ");
-	PrintHex<uint8_t>(evt->slider, 0x80);
-  Serial.print(" Buttons A: ");
-	PrintHex<uint8_t>(evt->buttons_a, 0x80);
-	Serial.print(" Buttons B: ");
-	PrintHex<uint8_t>(evt->buttons_b, 0x80);
-	Serial.println("");
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/le3dp/le3dp_rptparser.h b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/le3dp/le3dp_rptparser.h
deleted file mode 100644
index 2400364e65..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/le3dp/le3dp_rptparser.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#if !defined(__HIDJOYSTICKRPTPARSER_H__)
-#define __HIDJOYSTICKRPTPARSER_H__
-
-#include <hid.h>
-
-struct GamePadEventData
-{
-  union { //axes and hut switch
-    uint32_t axes;
-    struct {
-      uint32_t x : 10;
-      uint32_t y : 10;
-      uint32_t hat : 4;
-      uint32_t twist : 8;      
-    };
-  };
-  uint8_t buttons_a;
-  uint8_t slider;
-  uint8_t buttons_b;
-};
-
-class JoystickEvents
-{
-public:
-	virtual void OnGamePadChanged(const GamePadEventData *evt);
-};
-
-#define RPT_GAMEPAD_LEN	sizeof(GamePadEventData)/sizeof(uint8_t)
-
-class JoystickReportParser : public HIDReportParser
-{
-	JoystickEvents		*joyEvents;
-
-  uint8_t oldPad[RPT_GAMEPAD_LEN];
-
-public:
-	JoystickReportParser(JoystickEvents *evt);
-
-	virtual void Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf);
-};
-
-#endif // __HIDJOYSTICKRPTPARSER_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/scale/scale.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/scale/scale.ino
deleted file mode 100644
index f26ff964da..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/scale/scale.ino
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Digital Scale Output. Written for Stamps.com Model 510  */
-/* 5lb Digital Scale; any HID scale with Usage page 0x8d should work */
-
-#include <hid.h>
-#include <hiduniversal.h>
-#include <usbhub.h>
-
-#include "scale_rptparser.h"
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB                                             Usb;
-USBHub                                          Hub(&Usb);
-HIDUniversal                                    Hid(&Usb);
-Max_LCD                                       LCD(&Usb);
-ScaleEvents                                  ScaleEvents(&LCD);
-ScaleReportParser                            Scale(&ScaleEvents);
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-      Serial.println("OSC did not start.");
-
-    // set up the LCD's number of rows and columns:
-    LCD.begin(16, 2);
-    LCD.clear();
-    LCD.home();
-    LCD.setCursor(0,0);
-    LCD.write('R');
-
-  delay( 200 );
-
-  if (!Hid.SetReportParser(0, &Scale))
-      ErrorMessage<uint8_t>(PSTR("SetReportParser"), 1  );
-}
-
-void loop()
-{
-    Usb.Task();
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/scale/scale_rptparser.cpp b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/scale/scale_rptparser.cpp
deleted file mode 100644
index 01ed980cfb..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/scale/scale_rptparser.cpp
+++ /dev/null
@@ -1,150 +0,0 @@
-/* Parser for standard HID scale (usage page 0x8d) data input report (ID 3) */ 
-#include "scale_rptparser.h"
-
-const char* UNITS[13] = {
-    "units",        // unknown unit
-    "mg",           // milligram
-    "g",            // gram
-    "kg",           // kilogram
-    "cd",           // carat
-    "taels",        // lian
-    "gr",           // grain
-    "dwt",          // pennyweight
-    "tonnes",       // metric tons
-    "tons",         // avoir ton
-    "ozt",          // troy ounce
-    "oz",           // ounce
-    "lbs"           // pound
-};
-
-ScaleReportParser::ScaleReportParser(ScaleEvents *evt) :
-	scaleEvents(evt)
-{}
-
-void ScaleReportParser::Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf)
-{
-	bool match = true;
-
-	// Checking if there are changes in report since the method was last called
-	for (uint8_t i=0; i<RPT_SCALE_LEN; i++) {
-		if( buf[i] != oldScale[i] ) {
-			match = false;
-			break;
-		}
-  }
-  	// Calling Game Pad event handler
-	if (!match && scaleEvents) {
-		scaleEvents->OnScaleChanged((const ScaleEventData*)buf);
-
-		for (uint8_t i=0; i<RPT_SCALE_LEN; i++) oldScale[i] = buf[i];
-	}
-}
-
-ScaleEvents::ScaleEvents( Max_LCD* pLCD ) :
-	
-	pLcd( pLCD )
-
-{}
-
-void ScaleEvents::LcdPrint( const char* str )
-{
-	
-	while( *str ) {
-		
-		pLcd->write(	*str++ );
-		
-	}
-}
-
-void ScaleEvents::OnScaleChanged(const ScaleEventData *evt)
-{
-	
-	pLcd->clear();
-  pLcd->home();
-  pLcd->setCursor(0,0);
-	
-	if( evt->reportID != 3 ) {
-		
-		const char inv_report[]="Invalid report!";
-		
-		Serial.println(inv_report);
-		LcdPrint(inv_report);
-		
-		return;
-		
-	}//if( evt->reportID != 3...
-	
-	switch( evt->status ) {
-		
-		case REPORT_FAULT: 
-			Serial.println(F("Report fault"));
-			break;
-			
-		case ZEROED:
-			Serial.println(F("Scale zero set"));
-			break;
-			
-		case WEIGHING: {
-			
-			const char progress[] = "Weighing...";
-			Serial.println(progress);
-			LcdPrint(progress);
-			break;
-		}
-		
-		case WEIGHT_VALID: {
-			
-			char buf[10];
-      double weight = evt->weight * pow( 10, evt->exp );
-      
-      	
-                        
-      	Serial.print(F("Weight: "));
-				Serial.print( weight );
-				Serial.print(F(" "));
-				Serial.println( UNITS[ evt->unit ]);
-				
-				LcdPrint("Weight: ");
-				dtostrf( weight, 4, 2, buf );
-				LcdPrint( buf ); 
-				LcdPrint( UNITS[ evt->unit ]);
-			
-			break;
-			
-		}//case WEIGHT_VALID...
-			
-		case WEIGHT_NEGATIVE: {
-			
-			const char negweight[] = "Negative weight";
-			Serial.println(negweight);
-			LcdPrint(negweight);
-			break;
-		}
-			
-		case OVERWEIGHT: {
-		
-			const char overweight[] = "Max.weight reached";
-			Serial.println(overweight);
-			LcdPrint( overweight );
-			break;
-		}
-		
-		case CALIBRATE_ME:
-			
-			Serial.println(F("Scale calibration required"));
-			break;
-			
-		case ZERO_ME:
-			
-			Serial.println(F("Scale zeroing required"));
-			break;
-			
-		default:
-			
-			Serial.print(F("Undefined status code: "));
-			Serial.println( evt->status );
-			break;	
-			
-	}//switch( evt->status...
-
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/scale/scale_rptparser.h b/lib/usbhost/USB_Host_Shield_2.0/examples/HID/scale/scale_rptparser.h
deleted file mode 100644
index 57fbb033bf..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/HID/scale/scale_rptparser.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#if !defined(__SCALERPTPARSER_H__)
-#define __SCALERPTPARSER_H__
-
-#include <max_LCD.h>
-#include <hid.h>
-
-/* Scale status constants */
-#define REPORT_FAULT 0x01
-#define ZEROED 0x02
-#define WEIGHING 0x03
-#define WEIGHT_VALID 0x04
-#define WEIGHT_NEGATIVE 0x05
-#define OVERWEIGHT 0x06
-#define CALIBRATE_ME 0x07
-#define ZERO_ME 0x08
-
-/* input data report */
-struct ScaleEventData
-{
-  uint8_t reportID;	//must be 3
-  uint8_t status;
-  uint8_t unit;
-  int8_t exp;			//scale factor for the weight
-  uint16_t weight;	//
-};
-
-class ScaleEvents
-{
-
-	Max_LCD*	pLcd;
-
-	void LcdPrint( const char* str );
-
-public:
-
-	ScaleEvents( Max_LCD* pLCD );
-
-	virtual void OnScaleChanged(const ScaleEventData *evt);
-};
-
-#define RPT_SCALE_LEN	sizeof(ScaleEventData)/sizeof(uint8_t)
-
-class ScaleReportParser : public HIDReportParser
-{
-	ScaleEvents		*scaleEvents;
-
-  uint8_t oldScale[RPT_SCALE_LEN];
-
-public:
-	ScaleReportParser(ScaleEvents *evt);
-
-	virtual void Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf);
-};
-
-#endif // __SCALERPTPARSER_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/PS3USB/PS3USB.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/PS3USB/PS3USB.ino
deleted file mode 100644
index a53dcfbe61..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/PS3USB/PS3USB.ino
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- Example sketch for the PS3 USB library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <PS3USB.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-/* You can create the instance of the class in two ways */
-PS3USB PS3(&Usb); // This will just create the instance
-//PS3USB PS3(&Usb,0x00,0x15,0x83,0x3D,0x0A,0x57); // This will also store the bluetooth address - this can be obtained from the dongle when running the sketch
-
-bool printAngle;
-uint8_t state = 0;
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nPS3 USB Library Started"));
-}
-void loop() {
-  Usb.Task();
-
-  if (PS3.PS3Connected || PS3.PS3NavigationConnected) {
-    if (PS3.getAnalogHat(LeftHatX) > 137 || PS3.getAnalogHat(LeftHatX) < 117 || PS3.getAnalogHat(LeftHatY) > 137 || PS3.getAnalogHat(LeftHatY) < 117 || PS3.getAnalogHat(RightHatX) > 137 || PS3.getAnalogHat(RightHatX) < 117 || PS3.getAnalogHat(RightHatY) > 137 || PS3.getAnalogHat(RightHatY) < 117) {
-      Serial.print(F("\r\nLeftHatX: "));
-      Serial.print(PS3.getAnalogHat(LeftHatX));
-      Serial.print(F("\tLeftHatY: "));
-      Serial.print(PS3.getAnalogHat(LeftHatY));
-      if (PS3.PS3Connected) { // The Navigation controller only have one joystick
-        Serial.print(F("\tRightHatX: "));
-        Serial.print(PS3.getAnalogHat(RightHatX));
-        Serial.print(F("\tRightHatY: "));
-        Serial.print(PS3.getAnalogHat(RightHatY));
-      }
-    }
-    // Analog button values can be read from almost all buttons
-    if (PS3.getAnalogButton(L2) || PS3.getAnalogButton(R2)) {
-      Serial.print(F("\r\nL2: "));
-      Serial.print(PS3.getAnalogButton(L2));
-      if (!PS3.PS3NavigationConnected) {
-        Serial.print(F("\tR2: "));
-        Serial.print(PS3.getAnalogButton(R2));
-      }
-    }
-    if (PS3.getButtonClick(PS))
-      Serial.print(F("\r\nPS"));
-
-    if (PS3.getButtonClick(TRIANGLE))
-      Serial.print(F("\r\nTraingle"));
-    if (PS3.getButtonClick(CIRCLE))
-      Serial.print(F("\r\nCircle"));
-    if (PS3.getButtonClick(CROSS))
-      Serial.print(F("\r\nCross"));
-    if (PS3.getButtonClick(SQUARE))
-      Serial.print(F("\r\nSquare"));
-
-    if (PS3.getButtonClick(UP)) {
-      Serial.print(F("\r\nUp"));
-      PS3.setLedOff();
-      PS3.setLedOn(LED4);
-    }
-    if (PS3.getButtonClick(RIGHT)) {
-      Serial.print(F("\r\nRight"));
-      PS3.setLedOff();
-      PS3.setLedOn(LED1);
-    }
-    if (PS3.getButtonClick(DOWN)) {
-      Serial.print(F("\r\nDown"));
-      PS3.setLedOff();
-      PS3.setLedOn(LED2);
-    }
-    if (PS3.getButtonClick(LEFT)) {
-      Serial.print(F("\r\nLeft"));
-      PS3.setLedOff();
-      PS3.setLedOn(LED3);
-    }
-
-    if (PS3.getButtonClick(L1))
-      Serial.print(F("\r\nL1"));
-    if (PS3.getButtonClick(L3))
-      Serial.print(F("\r\nL3"));
-    if (PS3.getButtonClick(R1))
-      Serial.print(F("\r\nR1"));
-    if (PS3.getButtonClick(R3))
-      Serial.print(F("\r\nR3"));
-
-    if (PS3.getButtonClick(SELECT)) {
-      Serial.print(F("\r\nSelect - "));
-      PS3.printStatusString();
-    }
-    if (PS3.getButtonClick(START)) {
-      Serial.print(F("\r\nStart"));
-      printAngle = !printAngle;
-    }
-    if (printAngle) {
-      Serial.print(F("\r\nPitch: "));
-      Serial.print(PS3.getAngle(Pitch));
-      Serial.print(F("\tRoll: "));
-      Serial.print(PS3.getAngle(Roll));
-    }
-  }
-  else if (PS3.PS3MoveConnected) { // One can only set the color of the bulb, set the rumble, set and get the bluetooth address and calibrate the magnetometer via USB
-    if (state == 0) {
-      PS3.moveSetRumble(0);
-      PS3.moveSetBulb(Off);
-    } else if (state == 1) {
-      PS3.moveSetRumble(75);
-      PS3.moveSetBulb(Red);
-    } else if (state == 2) {
-      PS3.moveSetRumble(125);
-      PS3.moveSetBulb(Green);
-    } else if (state == 3) {
-      PS3.moveSetRumble(150);
-      PS3.moveSetBulb(Blue);
-    } else if (state == 4) {
-      PS3.moveSetRumble(175);
-      PS3.moveSetBulb(Yellow);
-    } else if (state == 5) {
-      PS3.moveSetRumble(200);
-      PS3.moveSetBulb(Lightblue);
-    } else if (state == 6) {
-      PS3.moveSetRumble(225);
-      PS3.moveSetBulb(Purble);
-    } else if (state == 7) {
-      PS3.moveSetRumble(250);
-      PS3.moveSetBulb(White);
-    }
-
-    state++;
-    if (state > 7)
-      state = 0;
-    delay(1000);
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/PS4USB/PS4USB.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/PS4USB/PS4USB.ino
deleted file mode 100644
index d0d76790ec..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/PS4USB/PS4USB.ino
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- Example sketch for the PS4 USB library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <PS4USB.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-PS4USB PS4(&Usb);
-
-bool printAngle, printTouch;
-uint8_t oldL2Value, oldR2Value;
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); // Halt
-  }
-  Serial.print(F("\r\nPS4 USB Library Started"));
-}
-
-void loop() {
-  Usb.Task();
-
-  if (PS4.connected()) {
-    if (PS4.getAnalogHat(LeftHatX) > 137 || PS4.getAnalogHat(LeftHatX) < 117 || PS4.getAnalogHat(LeftHatY) > 137 || PS4.getAnalogHat(LeftHatY) < 117 || PS4.getAnalogHat(RightHatX) > 137 || PS4.getAnalogHat(RightHatX) < 117 || PS4.getAnalogHat(RightHatY) > 137 || PS4.getAnalogHat(RightHatY) < 117) {
-      Serial.print(F("\r\nLeftHatX: "));
-      Serial.print(PS4.getAnalogHat(LeftHatX));
-      Serial.print(F("\tLeftHatY: "));
-      Serial.print(PS4.getAnalogHat(LeftHatY));
-      Serial.print(F("\tRightHatX: "));
-      Serial.print(PS4.getAnalogHat(RightHatX));
-      Serial.print(F("\tRightHatY: "));
-      Serial.print(PS4.getAnalogHat(RightHatY));
-    }
-
-    if (PS4.getAnalogButton(L2) || PS4.getAnalogButton(R2)) { // These are the only analog buttons on the PS4 controller
-      Serial.print(F("\r\nL2: "));
-      Serial.print(PS4.getAnalogButton(L2));
-      Serial.print(F("\tR2: "));
-      Serial.print(PS4.getAnalogButton(R2));
-    }
-    if (PS4.getAnalogButton(L2) != oldL2Value || PS4.getAnalogButton(R2) != oldR2Value) // Only write value if it's different
-      PS4.setRumbleOn(PS4.getAnalogButton(L2), PS4.getAnalogButton(R2));
-    oldL2Value = PS4.getAnalogButton(L2);
-    oldR2Value = PS4.getAnalogButton(R2);
-
-    if (PS4.getButtonClick(PS))
-      Serial.print(F("\r\nPS"));
-    if (PS4.getButtonClick(TRIANGLE)) {
-      Serial.print(F("\r\nTraingle"));
-      PS4.setRumbleOn(RumbleLow);
-    }
-    if (PS4.getButtonClick(CIRCLE)) {
-      Serial.print(F("\r\nCircle"));
-      PS4.setRumbleOn(RumbleHigh);
-    }
-    if (PS4.getButtonClick(CROSS)) {
-      Serial.print(F("\r\nCross"));
-      PS4.setLedFlash(10, 10); // Set it to blink rapidly
-    }
-    if (PS4.getButtonClick(SQUARE)) {
-      Serial.print(F("\r\nSquare"));
-      PS4.setLedFlash(0, 0); // Turn off blinking
-    }
-
-    if (PS4.getButtonClick(UP)) {
-      Serial.print(F("\r\nUp"));
-      PS4.setLed(Red);
-    } if (PS4.getButtonClick(RIGHT)) {
-      Serial.print(F("\r\nRight"));
-      PS4.setLed(Blue);
-    } if (PS4.getButtonClick(DOWN)) {
-      Serial.print(F("\r\nDown"));
-      PS4.setLed(Yellow);
-    } if (PS4.getButtonClick(LEFT)) {
-      Serial.print(F("\r\nLeft"));
-      PS4.setLed(Green);
-    }
-
-    if (PS4.getButtonClick(L1))
-      Serial.print(F("\r\nL1"));
-    if (PS4.getButtonClick(L3))
-      Serial.print(F("\r\nL3"));
-    if (PS4.getButtonClick(R1))
-      Serial.print(F("\r\nR1"));
-    if (PS4.getButtonClick(R3))
-      Serial.print(F("\r\nR3"));
-
-    if (PS4.getButtonClick(SHARE))
-      Serial.print(F("\r\nShare"));
-    if (PS4.getButtonClick(OPTIONS)) {
-      Serial.print(F("\r\nOptions"));
-      printAngle = !printAngle;
-    }
-    if (PS4.getButtonClick(TOUCHPAD)) {
-      Serial.print(F("\r\nTouchpad"));
-      printTouch = !printTouch;
-    }
-
-    if (printAngle) { // Print angle calculated using the accelerometer only
-      Serial.print(F("\r\nPitch: "));
-      Serial.print(PS4.getAngle(Pitch));
-      Serial.print(F("\tRoll: "));
-      Serial.print(PS4.getAngle(Roll));
-    }
-
-    if (printTouch) { // Print the x, y coordinates of the touchpad
-      if (PS4.isTouching(0) || PS4.isTouching(1)) // Print newline and carriage return if any of the fingers are touching the touchpad
-        Serial.print(F("\r\n"));
-      for (uint8_t i = 0; i < 2; i++) { // The touchpad track two fingers
-        if (PS4.isTouching(i)) { // Print the position of the finger if it is touching the touchpad
-          Serial.print(F("X")); Serial.print(i + 1); Serial.print(F(": "));
-          Serial.print(PS4.getX(i));
-          Serial.print(F("\tY")); Serial.print(i + 1); Serial.print(F(": "));
-          Serial.print(PS4.getY(i));
-          Serial.print(F("\t"));
-        }
-      }
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/PSBuzz/PSBuzz.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/PSBuzz/PSBuzz.ino
deleted file mode 100644
index 6ee462c1eb..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/PSBuzz/PSBuzz.ino
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- Example sketch for the Playstation Buzz library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <PSBuzz.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-PSBuzz Buzz(&Usb);
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); // Halt
-  }
-  Serial.println(F("\r\nPS Buzz Library Started"));
-}
-
-void loop() {
-  Usb.Task();
-
-  if (Buzz.connected()) {
-    for (uint8_t i = 0; i < 4; i++) {
-      if (Buzz.getButtonClick(RED, i)) {
-        Buzz.setLedToggle(i); // Toggle the LED
-        Serial.println(F("RED"));
-      }
-      if (Buzz.getButtonClick(YELLOW, i))
-        Serial.println(F("YELLOW"));
-      if (Buzz.getButtonClick(GREEN, i))
-        Serial.println(F("GREEN"));
-      if (Buzz.getButtonClick(ORANGE, i))
-        Serial.println(F("ORANGE"));
-      if (Buzz.getButtonClick(BLUE, i))
-        Serial.println(F("BLUE"));
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/USB_desc/USB_desc.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/USB_desc/USB_desc.ino
deleted file mode 100644
index acfe57d374..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/USB_desc/USB_desc.ino
+++ /dev/null
@@ -1,349 +0,0 @@
-#include <usbhub.h>
-
-#include "pgmstrings.h"
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB     Usb;
-//USBHub  Hub1(&Usb);
-//USBHub  Hub2(&Usb);
-//USBHub  Hub3(&Usb);
-//USBHub  Hub4(&Usb);
-//USBHub  Hub5(&Usb);
-//USBHub  Hub6(&Usb);
-//USBHub  Hub7(&Usb);
-
-uint32_t next_time;
-
-void PrintAllAddresses(UsbDevice *pdev)
-{
-  UsbDeviceAddress adr;
-  adr.devAddress = pdev->address.devAddress;
-  Serial.print("\r\nAddr:");
-  Serial.print(adr.devAddress, HEX);
-  Serial.print("(");
-  Serial.print(adr.bmHub, HEX);
-  Serial.print(".");
-  Serial.print(adr.bmParent, HEX);
-  Serial.print(".");
-  Serial.print(adr.bmAddress, HEX);
-  Serial.println(")");
-}
-
-void PrintAddress(uint8_t addr)
-{
-  UsbDeviceAddress adr;
-  adr.devAddress = addr;
-  Serial.print("\r\nADDR:\t");
-  Serial.println(adr.devAddress, HEX);
-  Serial.print("DEV:\t");
-  Serial.println(adr.bmAddress, HEX);
-  Serial.print("PRNT:\t");
-  Serial.println(adr.bmParent, HEX);
-  Serial.print("HUB:\t");
-  Serial.println(adr.bmHub, HEX);
-}
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-    Serial.println("OSC did not start.");
-
-  delay( 200 );
-
-  next_time = millis() + 10000;
-}
-
-byte getdevdescr( byte addr, byte &num_conf );
-
-void PrintDescriptors(uint8_t addr)
-{
-  uint8_t rcode = 0;
-  byte num_conf = 0;
-
-  rcode = getdevdescr( (byte)addr, num_conf );
-  if ( rcode )
-  {
-    printProgStr(Gen_Error_str);
-    print_hex( rcode, 8 );
-  }
-  Serial.print("\r\n");
-
-  for (int i = 0; i < num_conf; i++)
-  {
-    rcode = getconfdescr( addr, i );                 // get configuration descriptor
-    if ( rcode )
-    {
-      printProgStr(Gen_Error_str);
-      print_hex(rcode, 8);
-    }
-    Serial.println("\r\n");
-  }
-}
-
-void PrintAllDescriptors(UsbDevice *pdev)
-{
-  Serial.println("\r\n");
-  print_hex(pdev->address.devAddress, 8);
-  Serial.println("\r\n--");
-  PrintDescriptors( pdev->address.devAddress );
-}
-
-void loop()
-{
-  Usb.Task();
-
-  if ( Usb.getUsbTaskState() == USB_STATE_RUNNING )
-  {
-    //if (millis() >= next_time)
-    {
-      Usb.ForEachUsbDevice(&PrintAllDescriptors);
-      Usb.ForEachUsbDevice(&PrintAllAddresses);
-
-      while ( 1 );                          //stop
-    }
-  }
-}
-
-byte getdevdescr( byte addr, byte &num_conf )
-{
-  USB_DEVICE_DESCRIPTOR buf;
-  byte rcode;
-  rcode = Usb.getDevDescr( addr, 0, 0x12, ( uint8_t *)&buf );
-  if ( rcode ) {
-    return ( rcode );
-  }
-  printProgStr(Dev_Header_str);
-  printProgStr(Dev_Length_str);
-  print_hex( buf.bLength, 8 );
-  printProgStr(Dev_Type_str);
-  print_hex( buf.bDescriptorType, 8 );
-  printProgStr(Dev_Version_str);
-  print_hex( buf.bcdUSB, 16 );
-  printProgStr(Dev_Class_str);
-  print_hex( buf.bDeviceClass, 8 );
-  printProgStr(Dev_Subclass_str);
-  print_hex( buf.bDeviceSubClass, 8 );
-  printProgStr(Dev_Protocol_str);
-  print_hex( buf.bDeviceProtocol, 8 );
-  printProgStr(Dev_Pktsize_str);
-  print_hex( buf.bMaxPacketSize0, 8 );
-  printProgStr(Dev_Vendor_str);
-  print_hex( buf.idVendor, 16 );
-  printProgStr(Dev_Product_str);
-  print_hex( buf.idProduct, 16 );
-  printProgStr(Dev_Revision_str);
-  print_hex( buf.bcdDevice, 16 );
-  printProgStr(Dev_Mfg_str);
-  print_hex( buf.iManufacturer, 8 );
-  printProgStr(Dev_Prod_str);
-  print_hex( buf.iProduct, 8 );
-  printProgStr(Dev_Serial_str);
-  print_hex( buf.iSerialNumber, 8 );
-  printProgStr(Dev_Nconf_str);
-  print_hex( buf.bNumConfigurations, 8 );
-  num_conf = buf.bNumConfigurations;
-  return ( 0 );
-}
-
-void printhubdescr(uint8_t *descrptr, uint8_t addr)
-{
-  HubDescriptor  *pHub = (HubDescriptor*) descrptr;
-  uint8_t        len = *((uint8_t*)descrptr);
-
-  printProgStr(PSTR("\r\n\r\nHub Descriptor:\r\n"));
-  printProgStr(PSTR("bDescLength:\t\t"));
-  Serial.println(pHub->bDescLength, HEX);
-
-  printProgStr(PSTR("bDescriptorType:\t"));
-  Serial.println(pHub->bDescriptorType, HEX);
-
-  printProgStr(PSTR("bNbrPorts:\t\t"));
-  Serial.println(pHub->bNbrPorts, HEX);
-
-  printProgStr(PSTR("LogPwrSwitchMode:\t"));
-  Serial.println(pHub->LogPwrSwitchMode, BIN);
-
-  printProgStr(PSTR("CompoundDevice:\t\t"));
-  Serial.println(pHub->CompoundDevice, BIN);
-
-  printProgStr(PSTR("OverCurrentProtectMode:\t"));
-  Serial.println(pHub->OverCurrentProtectMode, BIN);
-
-  printProgStr(PSTR("TTThinkTime:\t\t"));
-  Serial.println(pHub->TTThinkTime, BIN);
-
-  printProgStr(PSTR("PortIndicatorsSupported:"));
-  Serial.println(pHub->PortIndicatorsSupported, BIN);
-
-  printProgStr(PSTR("Reserved:\t\t"));
-  Serial.println(pHub->Reserved, HEX);
-
-  printProgStr(PSTR("bPwrOn2PwrGood:\t\t"));
-  Serial.println(pHub->bPwrOn2PwrGood, HEX);
-
-  printProgStr(PSTR("bHubContrCurrent:\t"));
-  Serial.println(pHub->bHubContrCurrent, HEX);
-
-  for (uint8_t i = 7; i < len; i++)
-    print_hex(descrptr[i], 8);
-
-  //for (uint8_t i=1; i<=pHub->bNbrPorts; i++)
-  //    PrintHubPortStatus(&Usb, addr, i, 1);
-}
-
-byte getconfdescr( byte addr, byte conf )
-{
-  uint8_t buf[ BUFSIZE ];
-  uint8_t* buf_ptr = buf;
-  byte rcode;
-  byte descr_length;
-  byte descr_type;
-  unsigned int total_length;
-  rcode = Usb.getConfDescr( addr, 0, 4, conf, buf );  //get total length
-  LOBYTE( total_length ) = buf[ 2 ];
-  HIBYTE( total_length ) = buf[ 3 ];
-  if ( total_length > 256 ) {   //check if total length is larger than buffer
-    printProgStr(Conf_Trunc_str);
-    total_length = 256;
-  }
-  rcode = Usb.getConfDescr( addr, 0, total_length, conf, buf ); //get the whole descriptor
-  while ( buf_ptr < buf + total_length ) { //parsing descriptors
-    descr_length = *( buf_ptr );
-    descr_type = *( buf_ptr + 1 );
-    switch ( descr_type ) {
-      case ( USB_DESCRIPTOR_CONFIGURATION ):
-        printconfdescr( buf_ptr );
-        break;
-      case ( USB_DESCRIPTOR_INTERFACE ):
-        printintfdescr( buf_ptr );
-        break;
-      case ( USB_DESCRIPTOR_ENDPOINT ):
-        printepdescr( buf_ptr );
-        break;
-      case 0x29:
-        printhubdescr( buf_ptr, addr );
-        break;
-      default:
-        printunkdescr( buf_ptr );
-        break;
-    }//switch( descr_type
-    buf_ptr = ( buf_ptr + descr_length );    //advance buffer pointer
-  }//while( buf_ptr <=...
-  return ( rcode );
-}
-/* prints hex numbers with leading zeroes */
-// copyright, Peter H Anderson, Baltimore, MD, Nov, '07
-// source: http://www.phanderson.com/arduino/arduino_display.html
-void print_hex(int v, int num_places)
-{
-  int mask = 0, n, num_nibbles, digit;
-
-  for (n = 1; n <= num_places; n++) {
-    mask = (mask << 1) | 0x0001;
-  }
-  v = v & mask; // truncate v to specified number of places
-
-  num_nibbles = num_places / 4;
-  if ((num_places % 4) != 0) {
-    ++num_nibbles;
-  }
-  do {
-    digit = ((v >> (num_nibbles - 1) * 4)) & 0x0f;
-    Serial.print(digit, HEX);
-  }
-  while (--num_nibbles);
-}
-/* function to print configuration descriptor */
-void printconfdescr( uint8_t* descr_ptr )
-{
-  USB_CONFIGURATION_DESCRIPTOR* conf_ptr = ( USB_CONFIGURATION_DESCRIPTOR* )descr_ptr;
-  printProgStr(Conf_Header_str);
-  printProgStr(Conf_Totlen_str);
-  print_hex( conf_ptr->wTotalLength, 16 );
-  printProgStr(Conf_Nint_str);
-  print_hex( conf_ptr->bNumInterfaces, 8 );
-  printProgStr(Conf_Value_str);
-  print_hex( conf_ptr->bConfigurationValue, 8 );
-  printProgStr(Conf_String_str);
-  print_hex( conf_ptr->iConfiguration, 8 );
-  printProgStr(Conf_Attr_str);
-  print_hex( conf_ptr->bmAttributes, 8 );
-  printProgStr(Conf_Pwr_str);
-  print_hex( conf_ptr->bMaxPower, 8 );
-  return;
-}
-/* function to print interface descriptor */
-void printintfdescr( uint8_t* descr_ptr )
-{
-  USB_INTERFACE_DESCRIPTOR* intf_ptr = ( USB_INTERFACE_DESCRIPTOR* )descr_ptr;
-  printProgStr(Int_Header_str);
-  printProgStr(Int_Number_str);
-  print_hex( intf_ptr->bInterfaceNumber, 8 );
-  printProgStr(Int_Alt_str);
-  print_hex( intf_ptr->bAlternateSetting, 8 );
-  printProgStr(Int_Endpoints_str);
-  print_hex( intf_ptr->bNumEndpoints, 8 );
-  printProgStr(Int_Class_str);
-  print_hex( intf_ptr->bInterfaceClass, 8 );
-  printProgStr(Int_Subclass_str);
-  print_hex( intf_ptr->bInterfaceSubClass, 8 );
-  printProgStr(Int_Protocol_str);
-  print_hex( intf_ptr->bInterfaceProtocol, 8 );
-  printProgStr(Int_String_str);
-  print_hex( intf_ptr->iInterface, 8 );
-  return;
-}
-/* function to print endpoint descriptor */
-void printepdescr( uint8_t* descr_ptr )
-{
-  USB_ENDPOINT_DESCRIPTOR* ep_ptr = ( USB_ENDPOINT_DESCRIPTOR* )descr_ptr;
-  printProgStr(End_Header_str);
-  printProgStr(End_Address_str);
-  print_hex( ep_ptr->bEndpointAddress, 8 );
-  printProgStr(End_Attr_str);
-  print_hex( ep_ptr->bmAttributes, 8 );
-  printProgStr(End_Pktsize_str);
-  print_hex( ep_ptr->wMaxPacketSize, 16 );
-  printProgStr(End_Interval_str);
-  print_hex( ep_ptr->bInterval, 8 );
-
-  return;
-}
-/*function to print unknown descriptor */
-void printunkdescr( uint8_t* descr_ptr )
-{
-  byte length = *descr_ptr;
-  byte i;
-  printProgStr(Unk_Header_str);
-  printProgStr(Unk_Length_str);
-  print_hex( *descr_ptr, 8 );
-  printProgStr(Unk_Type_str);
-  print_hex( *(descr_ptr + 1 ), 8 );
-  printProgStr(Unk_Contents_str);
-  descr_ptr += 2;
-  for ( i = 0; i < length; i++ ) {
-    print_hex( *descr_ptr, 8 );
-    descr_ptr++;
-  }
-}
-
-
-/* Print a string from Program Memory directly to save RAM */
-void printProgStr(const char* str)
-{
-  char c;
-  if (!str) return;
-  while ((c = pgm_read_byte(str++)))
-    Serial.print(c);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/USB_desc/pgmstrings.h b/lib/usbhost/USB_Host_Shield_2.0/examples/USB_desc/pgmstrings.h
deleted file mode 100644
index bdb0077ecc..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/USB_desc/pgmstrings.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#if !defined(__PGMSTRINGS_H__)
-#define __PGMSTRINGS_H__
-
-#define LOBYTE(x) ((char*)(&(x)))[0]
-#define HIBYTE(x) ((char*)(&(x)))[1]
-#define BUFSIZE 256    //buffer size
- 
-
-/* Print strings in Program Memory */
-const char Gen_Error_str[] PROGMEM = "\r\nRequest error. Error code:\t"; 
-const char Dev_Header_str[] PROGMEM ="\r\nDevice descriptor: ";
-const char Dev_Length_str[] PROGMEM ="\r\nDescriptor Length:\t";
-const char Dev_Type_str[] PROGMEM ="\r\nDescriptor type:\t";
-const char Dev_Version_str[] PROGMEM ="\r\nUSB version:\t\t";
-const char Dev_Class_str[] PROGMEM ="\r\nDevice class:\t\t";
-const char Dev_Subclass_str[] PROGMEM ="\r\nDevice Subclass:\t";
-const char Dev_Protocol_str[] PROGMEM ="\r\nDevice Protocol:\t";
-const char Dev_Pktsize_str[] PROGMEM ="\r\nMax.packet size:\t";
-const char Dev_Vendor_str[] PROGMEM ="\r\nVendor  ID:\t\t";
-const char Dev_Product_str[] PROGMEM ="\r\nProduct ID:\t\t";
-const char Dev_Revision_str[] PROGMEM ="\r\nRevision ID:\t\t";
-const char Dev_Mfg_str[] PROGMEM ="\r\nMfg.string index:\t";
-const char Dev_Prod_str[] PROGMEM ="\r\nProd.string index:\t";
-const char Dev_Serial_str[] PROGMEM ="\r\nSerial number index:\t";
-const char Dev_Nconf_str[] PROGMEM ="\r\nNumber of conf.:\t";
-const char Conf_Trunc_str[] PROGMEM ="Total length truncated to 256 bytes";
-const char Conf_Header_str[] PROGMEM ="\r\nConfiguration descriptor:";
-const char Conf_Totlen_str[] PROGMEM ="\r\nTotal length:\t\t";
-const char Conf_Nint_str[] PROGMEM ="\r\nNum.intf:\t\t";
-const char Conf_Value_str[] PROGMEM ="\r\nConf.value:\t\t";
-const char Conf_String_str[] PROGMEM ="\r\nConf.string:\t\t";
-const char Conf_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char Conf_Pwr_str[] PROGMEM ="\r\nMax.pwr:\t\t";
-const char Int_Header_str[] PROGMEM ="\r\n\r\nInterface descriptor:";
-const char Int_Number_str[] PROGMEM ="\r\nIntf.number:\t\t";
-const char Int_Alt_str[] PROGMEM ="\r\nAlt.:\t\t\t";
-const char Int_Endpoints_str[] PROGMEM ="\r\nEndpoints:\t\t";
-const char Int_Class_str[] PROGMEM ="\r\nIntf. Class:\t\t";
-const char Int_Subclass_str[] PROGMEM ="\r\nIntf. Subclass:\t\t";
-const char Int_Protocol_str[] PROGMEM ="\r\nIntf. Protocol:\t\t";
-const char Int_String_str[] PROGMEM ="\r\nIntf.string:\t\t";
-const char End_Header_str[] PROGMEM ="\r\n\r\nEndpoint descriptor:";
-const char End_Address_str[] PROGMEM ="\r\nEndpoint address:\t";
-const char End_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char End_Pktsize_str[] PROGMEM ="\r\nMax.pkt size:\t\t";
-const char End_Interval_str[] PROGMEM ="\r\nPolling interval:\t";
-const char Unk_Header_str[] PROGMEM = "\r\nUnknown descriptor:";
-const char Unk_Length_str[] PROGMEM ="\r\nLength:\t\t";
-const char Unk_Type_str[] PROGMEM ="\r\nType:\t\t";
-const char Unk_Contents_str[] PROGMEM ="\r\nContents:\t";
- 
-#endif // __PGMSTRINGS_H__
\ No newline at end of file
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXOLD/XBOXOLD.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXOLD/XBOXOLD.ino
deleted file mode 100644
index 64a3ed6120..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXOLD/XBOXOLD.ino
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- Example sketch for the original Xbox library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <XBOXOLD.h>
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-USBHub  Hub1(&Usb); // The controller has a built in hub, so this instance is needed
-XBOXOLD Xbox(&Usb);
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); // halt
-  }
-  Serial.print(F("\r\nXBOX Library Started"));
-}
-void loop() {
-  Usb.Task();
-  if (Xbox.XboxConnected) {
-    if (Xbox.getButtonPress(BLACK) || Xbox.getButtonPress(WHITE)) {
-      Serial.print("BLACK: ");
-      Serial.print(Xbox.getButtonPress(BLACK));
-      Serial.print("\tWHITE: ");
-      Serial.println(Xbox.getButtonPress(WHITE));
-      Xbox.setRumbleOn(Xbox.getButtonPress(BLACK), Xbox.getButtonPress(WHITE));
-    } else
-      Xbox.setRumbleOn(0, 0);
-
-    if (Xbox.getAnalogHat(LeftHatX) > 7500 || Xbox.getAnalogHat(LeftHatX) < -7500 || Xbox.getAnalogHat(LeftHatY) > 7500 || Xbox.getAnalogHat(LeftHatY) < -7500 || Xbox.getAnalogHat(RightHatX) > 7500 || Xbox.getAnalogHat(RightHatX) < -7500 || Xbox.getAnalogHat(RightHatY) > 7500 || Xbox.getAnalogHat(RightHatY) < -7500) {
-      if (Xbox.getAnalogHat(LeftHatX) > 7500 || Xbox.getAnalogHat(LeftHatX) < -7500) {
-        Serial.print(F("LeftHatX: "));
-        Serial.print(Xbox.getAnalogHat(LeftHatX));
-        Serial.print("\t");
-      }
-      if (Xbox.getAnalogHat(LeftHatY) > 7500 || Xbox.getAnalogHat(LeftHatY) < -7500) {
-        Serial.print(F("LeftHatY: "));
-        Serial.print(Xbox.getAnalogHat(LeftHatY));
-        Serial.print("\t");
-      }
-      if (Xbox.getAnalogHat(RightHatX) > 7500 || Xbox.getAnalogHat(RightHatX) < -7500) {
-        Serial.print(F("RightHatX: "));
-        Serial.print(Xbox.getAnalogHat(RightHatX));
-        Serial.print("\t");
-      }
-      if (Xbox.getAnalogHat(RightHatY) > 7500 || Xbox.getAnalogHat(RightHatY) < -7500) {
-        Serial.print(F("RightHatY: "));
-        Serial.print(Xbox.getAnalogHat(RightHatY));
-      }
-      Serial.println();
-    }
-
-    if (Xbox.getButtonClick(UP))
-      Serial.println(F("Up"));
-    if (Xbox.getButtonClick(DOWN))
-      Serial.println(F("Down"));
-    if (Xbox.getButtonClick(LEFT))
-      Serial.println(F("Left"));
-    if (Xbox.getButtonClick(RIGHT))
-      Serial.println(F("Right"));
-
-    if (Xbox.getButtonClick(START))
-      Serial.println(F("Start"));
-    if (Xbox.getButtonClick(BACK))
-      Serial.println(F("Back"));
-    if (Xbox.getButtonClick(L3))
-      Serial.println(F("L3"));
-    if (Xbox.getButtonClick(R3))
-      Serial.println(F("R3"));
-
-    if (Xbox.getButtonPress(A)) {
-      Serial.print(F("A: "));
-      Serial.println(Xbox.getButtonPress(A));
-    }
-    if (Xbox.getButtonPress(B)) {
-      Serial.print(F("B: "));
-      Serial.println(Xbox.getButtonPress(B));
-    }
-    if (Xbox.getButtonPress(X)) {
-      Serial.print(F("X: "));
-      Serial.println(Xbox.getButtonPress(X));
-    }
-    if (Xbox.getButtonPress(Y)) {
-      Serial.print(F("Y: "));
-      Serial.println(Xbox.getButtonPress(Y));
-    }
-    if (Xbox.getButtonPress(L1)) {
-      Serial.print(F("L1: "));
-      Serial.println(Xbox.getButtonPress(L1));
-    }
-    if (Xbox.getButtonPress(R1)) {
-      Serial.print(F("R1: "));
-      Serial.println(Xbox.getButtonPress(R1));
-    }
-  }
-  delay(1);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXONE/XBOXONE.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXONE/XBOXONE.ino
deleted file mode 100644
index 9526f53d19..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXONE/XBOXONE.ino
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- Example sketch for the Xbox ONE USB library - by guruthree, based on work by
- Kristian Lauszus.
- */
-
-#include <XBOXONE.h>
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#endif
-
-USB Usb;
-XBOXONE Xbox(&Usb);
-
-void setup() {
-  Serial.begin(115200);
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nXBOX USB Library Started"));
-}
-void loop() {
-  Usb.Task();
-  if (Xbox.XboxOneConnected) {
-    if (Xbox.getAnalogHat(LeftHatX) > 7500 || Xbox.getAnalogHat(LeftHatX) < -7500 || Xbox.getAnalogHat(LeftHatY) > 7500 || Xbox.getAnalogHat(LeftHatY) < -7500 || Xbox.getAnalogHat(RightHatX) > 7500 || Xbox.getAnalogHat(RightHatX) < -7500 || Xbox.getAnalogHat(RightHatY) > 7500 || Xbox.getAnalogHat(RightHatY) < -7500) {
-      if (Xbox.getAnalogHat(LeftHatX) > 7500 || Xbox.getAnalogHat(LeftHatX) < -7500) {
-        Serial.print(F("LeftHatX: "));
-        Serial.print(Xbox.getAnalogHat(LeftHatX));
-        Serial.print("\t");
-      }
-      if (Xbox.getAnalogHat(LeftHatY) > 7500 || Xbox.getAnalogHat(LeftHatY) < -7500) {
-        Serial.print(F("LeftHatY: "));
-        Serial.print(Xbox.getAnalogHat(LeftHatY));
-        Serial.print("\t");
-      }
-      if (Xbox.getAnalogHat(RightHatX) > 7500 || Xbox.getAnalogHat(RightHatX) < -7500) {
-        Serial.print(F("RightHatX: "));
-        Serial.print(Xbox.getAnalogHat(RightHatX));
-        Serial.print("\t");
-      }
-      if (Xbox.getAnalogHat(RightHatY) > 7500 || Xbox.getAnalogHat(RightHatY) < -7500) {
-        Serial.print(F("RightHatY: "));
-        Serial.print(Xbox.getAnalogHat(RightHatY));
-      }
-      Serial.println();
-    }
-
-    if (Xbox.getButtonPress(L2) > 0 || Xbox.getButtonPress(R2) > 0) {
-      if (Xbox.getButtonPress(L2) > 0) {
-        Serial.print(F("L2: "));
-        Serial.print(Xbox.getButtonPress(L2));
-        Serial.print("\t");
-      }
-      if (Xbox.getButtonPress(R2) > 0) {
-        Serial.print(F("R2: "));
-        Serial.print(Xbox.getButtonPress(R2));
-        Serial.print("\t");
-      }
-      Serial.println();
-    }
-
-    if (Xbox.getButtonClick(UP))
-      Serial.println(F("Up"));
-    if (Xbox.getButtonClick(DOWN))
-      Serial.println(F("Down"));
-    if (Xbox.getButtonClick(LEFT))
-      Serial.println(F("Left"));
-    if (Xbox.getButtonClick(RIGHT))
-      Serial.println(F("Right"));
-
-    if (Xbox.getButtonClick(START))
-      Serial.println(F("Start"));
-    if (Xbox.getButtonClick(BACK))
-      Serial.println(F("Back"));
-    if (Xbox.getButtonClick(XBOX))
-      Serial.println(F("Xbox"));
-    if (Xbox.getButtonClick(SYNC))
-      Serial.println(F("Sync"));
-
-    if (Xbox.getButtonClick(L1))
-      Serial.println(F("L1"));
-    if (Xbox.getButtonClick(R1))
-      Serial.println(F("R1"));
-    if (Xbox.getButtonClick(L2))
-      Serial.println(F("L2"));
-    if (Xbox.getButtonClick(R2))
-      Serial.println(F("R2"));
-    if (Xbox.getButtonClick(L3))
-      Serial.println(F("L3"));
-    if (Xbox.getButtonClick(R3))
-      Serial.println(F("R3"));
-
-
-    if (Xbox.getButtonClick(A))
-      Serial.println(F("A"));
-    if (Xbox.getButtonClick(B))
-      Serial.println(F("B"));
-    if (Xbox.getButtonClick(X))
-      Serial.println(F("X"));
-    if (Xbox.getButtonClick(Y))
-      Serial.println(F("Y"));
-  }
-  delay(1);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXRECV/XBOXRECV.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXRECV/XBOXRECV.ino
deleted file mode 100644
index 491b287e44..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXRECV/XBOXRECV.ino
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- Example sketch for the Xbox Wireless Reciver library - developed by Kristian Lauszus
- It supports up to four controllers wirelessly
- For more information see the blog post: http://blog.tkjelectronics.dk/2012/12/xbox-360-receiver-added-to-the-usb-host-library/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <XBOXRECV.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-XBOXRECV Xbox(&Usb);
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nXbox Wireless Receiver Library Started"));
-}
-void loop() {
-  Usb.Task();
-  if (Xbox.XboxReceiverConnected) {
-    for (uint8_t i = 0; i < 4; i++) {
-      if (Xbox.Xbox360Connected[i]) {
-        if (Xbox.getButtonPress(L2, i) || Xbox.getButtonPress(R2, i)) {
-          Serial.print("L2: ");
-          Serial.print(Xbox.getButtonPress(L2, i));
-          Serial.print("\tR2: ");
-          Serial.println(Xbox.getButtonPress(R2, i));
-          Xbox.setRumbleOn(Xbox.getButtonPress(L2, i), Xbox.getButtonPress(R2, i), i);
-        }
-
-        if (Xbox.getAnalogHat(LeftHatX, i) > 7500 || Xbox.getAnalogHat(LeftHatX, i) < -7500 || Xbox.getAnalogHat(LeftHatY, i) > 7500 || Xbox.getAnalogHat(LeftHatY, i) < -7500 || Xbox.getAnalogHat(RightHatX, i) > 7500 || Xbox.getAnalogHat(RightHatX, i) < -7500 || Xbox.getAnalogHat(RightHatY, i) > 7500 || Xbox.getAnalogHat(RightHatY, i) < -7500) {
-          if (Xbox.getAnalogHat(LeftHatX, i) > 7500 || Xbox.getAnalogHat(LeftHatX, i) < -7500) {
-            Serial.print(F("LeftHatX: "));
-            Serial.print(Xbox.getAnalogHat(LeftHatX, i));
-            Serial.print("\t");
-          }
-          if (Xbox.getAnalogHat(LeftHatY, i) > 7500 || Xbox.getAnalogHat(LeftHatY, i) < -7500) {
-            Serial.print(F("LeftHatY: "));
-            Serial.print(Xbox.getAnalogHat(LeftHatY, i));
-            Serial.print("\t");
-          }
-          if (Xbox.getAnalogHat(RightHatX, i) > 7500 || Xbox.getAnalogHat(RightHatX, i) < -7500) {
-            Serial.print(F("RightHatX: "));
-            Serial.print(Xbox.getAnalogHat(RightHatX, i));
-            Serial.print("\t");
-          }
-          if (Xbox.getAnalogHat(RightHatY, i) > 7500 || Xbox.getAnalogHat(RightHatY, i) < -7500) {
-            Serial.print(F("RightHatY: "));
-            Serial.print(Xbox.getAnalogHat(RightHatY, i));
-          }
-          Serial.println();
-        }
-
-        if (Xbox.getButtonClick(UP, i)) {
-          Xbox.setLedOn(LED1, i);
-          Serial.println(F("Up"));
-        }
-        if (Xbox.getButtonClick(DOWN, i)) {
-          Xbox.setLedOn(LED4, i);
-          Serial.println(F("Down"));
-        }
-        if (Xbox.getButtonClick(LEFT, i)) {
-          Xbox.setLedOn(LED3, i);
-          Serial.println(F("Left"));
-        }
-        if (Xbox.getButtonClick(RIGHT, i)) {
-          Xbox.setLedOn(LED2, i);
-          Serial.println(F("Right"));
-        }
-
-        if (Xbox.getButtonClick(START, i)) {
-          Xbox.setLedMode(ALTERNATING, i);
-          Serial.println(F("Start"));
-        }
-        if (Xbox.getButtonClick(BACK, i)) {
-          Xbox.setLedBlink(ALL, i);
-          Serial.println(F("Back"));
-        }
-        if (Xbox.getButtonClick(L3, i))
-          Serial.println(F("L3"));
-        if (Xbox.getButtonClick(R3, i))
-          Serial.println(F("R3"));
-
-        if (Xbox.getButtonClick(L1, i))
-          Serial.println(F("L1"));
-        if (Xbox.getButtonClick(R1, i))
-          Serial.println(F("R1"));
-        if (Xbox.getButtonClick(XBOX, i)) {
-          Xbox.setLedMode(ROTATING, i);
-          Serial.print(F("Xbox (Battery: "));
-          Serial.print(Xbox.getBatteryLevel(i)); // The battery level in the range 0-3
-          Serial.println(F(")"));
-        }
-        if (Xbox.getButtonClick(SYNC, i)) {
-          Serial.println(F("Sync"));
-          Xbox.disconnect(i);
-        }
-
-        if (Xbox.getButtonClick(A, i))
-          Serial.println(F("A"));
-        if (Xbox.getButtonClick(B, i))
-          Serial.println(F("B"));
-        if (Xbox.getButtonClick(X, i))
-          Serial.println(F("X"));
-        if (Xbox.getButtonClick(Y, i))
-          Serial.println(F("Y"));
-      }
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXUSB/XBOXUSB.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXUSB/XBOXUSB.ino
deleted file mode 100644
index 8a5691c6e1..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/Xbox/XBOXUSB/XBOXUSB.ino
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- Example sketch for the Xbox 360 USB library - developed by Kristian Lauszus
- For more information visit my blog: http://blog.tkjelectronics.dk/ or
- send me an e-mail:  kristianl@tkjelectronics.com
- */
-
-#include <XBOXUSB.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-XBOXUSB Xbox(&Usb);
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print(F("\r\nOSC did not start"));
-    while (1); //halt
-  }
-  Serial.print(F("\r\nXBOX USB Library Started"));
-}
-void loop() {
-  Usb.Task();
-  if (Xbox.Xbox360Connected) {
-    if (Xbox.getButtonPress(L2) || Xbox.getButtonPress(R2)) {
-      Serial.print("L2: ");
-      Serial.print(Xbox.getButtonPress(L2));
-      Serial.print("\tR2: ");
-      Serial.println(Xbox.getButtonPress(R2));
-      Xbox.setRumbleOn(Xbox.getButtonPress(L2), Xbox.getButtonPress(R2));
-    } else
-      Xbox.setRumbleOn(0, 0);
-
-    if (Xbox.getAnalogHat(LeftHatX) > 7500 || Xbox.getAnalogHat(LeftHatX) < -7500 || Xbox.getAnalogHat(LeftHatY) > 7500 || Xbox.getAnalogHat(LeftHatY) < -7500 || Xbox.getAnalogHat(RightHatX) > 7500 || Xbox.getAnalogHat(RightHatX) < -7500 || Xbox.getAnalogHat(RightHatY) > 7500 || Xbox.getAnalogHat(RightHatY) < -7500) {
-      if (Xbox.getAnalogHat(LeftHatX) > 7500 || Xbox.getAnalogHat(LeftHatX) < -7500) {
-        Serial.print(F("LeftHatX: "));
-        Serial.print(Xbox.getAnalogHat(LeftHatX));
-        Serial.print("\t");
-      }
-      if (Xbox.getAnalogHat(LeftHatY) > 7500 || Xbox.getAnalogHat(LeftHatY) < -7500) {
-        Serial.print(F("LeftHatY: "));
-        Serial.print(Xbox.getAnalogHat(LeftHatY));
-        Serial.print("\t");
-      }
-      if (Xbox.getAnalogHat(RightHatX) > 7500 || Xbox.getAnalogHat(RightHatX) < -7500) {
-        Serial.print(F("RightHatX: "));
-        Serial.print(Xbox.getAnalogHat(RightHatX));
-        Serial.print("\t");
-      }
-      if (Xbox.getAnalogHat(RightHatY) > 7500 || Xbox.getAnalogHat(RightHatY) < -7500) {
-        Serial.print(F("RightHatY: "));
-        Serial.print(Xbox.getAnalogHat(RightHatY));
-      }
-      Serial.println();
-    }
-
-    if (Xbox.getButtonClick(UP)) {
-      Xbox.setLedOn(LED1);
-      Serial.println(F("Up"));
-    }
-    if (Xbox.getButtonClick(DOWN)) {
-      Xbox.setLedOn(LED4);
-      Serial.println(F("Down"));
-    }
-    if (Xbox.getButtonClick(LEFT)) {
-      Xbox.setLedOn(LED3);
-      Serial.println(F("Left"));
-    }
-    if (Xbox.getButtonClick(RIGHT)) {
-      Xbox.setLedOn(LED2);
-      Serial.println(F("Right"));
-    }
-
-    if (Xbox.getButtonClick(START)) {
-      Xbox.setLedMode(ALTERNATING);
-      Serial.println(F("Start"));
-    }
-    if (Xbox.getButtonClick(BACK)) {
-      Xbox.setLedBlink(ALL);
-      Serial.println(F("Back"));
-    }
-    if (Xbox.getButtonClick(L3))
-      Serial.println(F("L3"));
-    if (Xbox.getButtonClick(R3))
-      Serial.println(F("R3"));
-
-    if (Xbox.getButtonClick(L1))
-      Serial.println(F("L1"));
-    if (Xbox.getButtonClick(R1))
-      Serial.println(F("R1"));
-    if (Xbox.getButtonClick(XBOX)) {
-      Xbox.setLedMode(ROTATING);
-      Serial.println(F("Xbox"));
-    }
-
-    if (Xbox.getButtonClick(A))
-      Serial.println(F("A"));
-    if (Xbox.getButtonClick(B))
-      Serial.println(F("B"));
-    if (Xbox.getButtonClick(X))
-      Serial.println(F("X"));
-    if (Xbox.getButtonClick(Y))
-      Serial.println(F("Y"));
-  }
-  delay(1);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/acm/acm_terminal/acm_terminal.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/acm/acm_terminal/acm_terminal.ino
deleted file mode 100644
index f509cda890..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/acm/acm_terminal/acm_terminal.ino
+++ /dev/null
@@ -1,100 +0,0 @@
-#include <cdcacm.h>
-#include <usbhub.h>
-
-#include "pgmstrings.h"
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class ACMAsyncOper : public CDCAsyncOper
-{
-public:
-    uint8_t OnInit(ACM *pacm);
-};
-
-uint8_t ACMAsyncOper::OnInit(ACM *pacm)
-{
-    uint8_t rcode;
-    // Set DTR = 1 RTS=1
-    rcode = pacm->SetControlLineState(3);
-
-    if (rcode)
-    {
-        ErrorMessage<uint8_t>(PSTR("SetControlLineState"), rcode);
-        return rcode;
-    }
-
-    LINE_CODING	lc;
-    lc.dwDTERate	= 115200;
-    lc.bCharFormat	= 0;
-    lc.bParityType	= 0;
-    lc.bDataBits	= 8;
-
-    rcode = pacm->SetLineCoding(&lc);
-
-    if (rcode)
-        ErrorMessage<uint8_t>(PSTR("SetLineCoding"), rcode);
-
-    return rcode;
-}
-
-USB     Usb;
-//USBHub     Hub(&Usb);
-ACMAsyncOper  AsyncOper;
-ACM           Acm(&Usb, &AsyncOper);
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-      Serial.println("OSCOKIRQ failed to assert");
-
-  delay( 200 );
-}
-
-void loop()
-{
-    Usb.Task();
-
-    if( Acm.isReady()) {
-       uint8_t rcode;
-
-       /* reading the keyboard */
-       if(Serial.available()) {
-         uint8_t data= Serial.read();
-         /* sending to the phone */
-         rcode = Acm.SndData(1, &data);
-         if (rcode)
-            ErrorMessage<uint8_t>(PSTR("SndData"), rcode);
-       }//if(Serial.available()...
-
-       delay(50);
-
-        /* reading the phone */
-        /* buffer size must be greater or equal to max.packet size */
-        /* it it set to 64 (largest possible max.packet size) here, can be tuned down
-        for particular endpoint */
-        uint8_t  buf[64];
-        uint16_t rcvd = 64;
-        rcode = Acm.RcvData(&rcvd, buf);
-         if (rcode && rcode != hrNAK)
-            ErrorMessage<uint8_t>(PSTR("Ret"), rcode);
-
-            if( rcvd ) { //more than zero bytes received
-              for(uint16_t i=0; i < rcvd; i++ ) {
-                Serial.print((char)buf[i]); //printing on the screen
-              }
-            }
-        delay(10);
-    }//if( Usb.getUsbTaskState() == USB_STATE_RUNNING..
-}
-
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/acm/acm_terminal/pgmstrings.h b/lib/usbhost/USB_Host_Shield_2.0/examples/acm/acm_terminal/pgmstrings.h
deleted file mode 100644
index bdb0077ecc..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/acm/acm_terminal/pgmstrings.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#if !defined(__PGMSTRINGS_H__)
-#define __PGMSTRINGS_H__
-
-#define LOBYTE(x) ((char*)(&(x)))[0]
-#define HIBYTE(x) ((char*)(&(x)))[1]
-#define BUFSIZE 256    //buffer size
- 
-
-/* Print strings in Program Memory */
-const char Gen_Error_str[] PROGMEM = "\r\nRequest error. Error code:\t"; 
-const char Dev_Header_str[] PROGMEM ="\r\nDevice descriptor: ";
-const char Dev_Length_str[] PROGMEM ="\r\nDescriptor Length:\t";
-const char Dev_Type_str[] PROGMEM ="\r\nDescriptor type:\t";
-const char Dev_Version_str[] PROGMEM ="\r\nUSB version:\t\t";
-const char Dev_Class_str[] PROGMEM ="\r\nDevice class:\t\t";
-const char Dev_Subclass_str[] PROGMEM ="\r\nDevice Subclass:\t";
-const char Dev_Protocol_str[] PROGMEM ="\r\nDevice Protocol:\t";
-const char Dev_Pktsize_str[] PROGMEM ="\r\nMax.packet size:\t";
-const char Dev_Vendor_str[] PROGMEM ="\r\nVendor  ID:\t\t";
-const char Dev_Product_str[] PROGMEM ="\r\nProduct ID:\t\t";
-const char Dev_Revision_str[] PROGMEM ="\r\nRevision ID:\t\t";
-const char Dev_Mfg_str[] PROGMEM ="\r\nMfg.string index:\t";
-const char Dev_Prod_str[] PROGMEM ="\r\nProd.string index:\t";
-const char Dev_Serial_str[] PROGMEM ="\r\nSerial number index:\t";
-const char Dev_Nconf_str[] PROGMEM ="\r\nNumber of conf.:\t";
-const char Conf_Trunc_str[] PROGMEM ="Total length truncated to 256 bytes";
-const char Conf_Header_str[] PROGMEM ="\r\nConfiguration descriptor:";
-const char Conf_Totlen_str[] PROGMEM ="\r\nTotal length:\t\t";
-const char Conf_Nint_str[] PROGMEM ="\r\nNum.intf:\t\t";
-const char Conf_Value_str[] PROGMEM ="\r\nConf.value:\t\t";
-const char Conf_String_str[] PROGMEM ="\r\nConf.string:\t\t";
-const char Conf_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char Conf_Pwr_str[] PROGMEM ="\r\nMax.pwr:\t\t";
-const char Int_Header_str[] PROGMEM ="\r\n\r\nInterface descriptor:";
-const char Int_Number_str[] PROGMEM ="\r\nIntf.number:\t\t";
-const char Int_Alt_str[] PROGMEM ="\r\nAlt.:\t\t\t";
-const char Int_Endpoints_str[] PROGMEM ="\r\nEndpoints:\t\t";
-const char Int_Class_str[] PROGMEM ="\r\nIntf. Class:\t\t";
-const char Int_Subclass_str[] PROGMEM ="\r\nIntf. Subclass:\t\t";
-const char Int_Protocol_str[] PROGMEM ="\r\nIntf. Protocol:\t\t";
-const char Int_String_str[] PROGMEM ="\r\nIntf.string:\t\t";
-const char End_Header_str[] PROGMEM ="\r\n\r\nEndpoint descriptor:";
-const char End_Address_str[] PROGMEM ="\r\nEndpoint address:\t";
-const char End_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char End_Pktsize_str[] PROGMEM ="\r\nMax.pkt size:\t\t";
-const char End_Interval_str[] PROGMEM ="\r\nPolling interval:\t";
-const char Unk_Header_str[] PROGMEM = "\r\nUnknown descriptor:";
-const char Unk_Length_str[] PROGMEM ="\r\nLength:\t\t";
-const char Unk_Type_str[] PROGMEM ="\r\nType:\t\t";
-const char Unk_Contents_str[] PROGMEM ="\r\nContents:\t";
- 
-#endif // __PGMSTRINGS_H__
\ No newline at end of file
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/ArduinoBlinkLED/ArduinoBlinkLED.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/adk/ArduinoBlinkLED/ArduinoBlinkLED.ino
deleted file mode 100644
index d59b9bb3dc..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/ArduinoBlinkLED/ArduinoBlinkLED.ino
+++ /dev/null
@@ -1,89 +0,0 @@
-// The source for the Android application can be found at the following link: https://github.com/Lauszus/ArduinoBlinkLED
-// The code for the Android application is heavily based on this guide: http://allaboutee.com/2011/12/31/arduino-adk-board-blink-an-led-with-your-phone-code-and-explanation/ by Miguel
-#include <adk.h>
-
-//
-// CAUTION! WARNING! ATTENTION! VORSICHT! ADVARSEL! ¡CUIDADO! ВНИМАНИЕ!
-//
-// Pin 13 is occupied by the SCK pin on various Arduino boards,
-// including Uno, Duemilanove, etc., so use a different pin for those boards.
-//
-// CAUTION! WARNING! ATTENTION! VORSICHT! ADVARSEL! ¡CUIDADO! ВНИМАНИЕ!
-//
-#if defined(LED_BUILTIN)
-#define LED LED_BUILTIN // Use built in LED
-#else
-#define LED 9 // Set to something here that makes sense for your board.
-#endif
-
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-ADK adk(&Usb, "TKJElectronics", // Manufacturer Name
-              "ArduinoBlinkLED", // Model Name
-              "Example sketch for the USB Host Shield", // Description (user-visible string)
-              "1.0", // Version
-              "http://www.tkjelectronics.dk/uploads/ArduinoBlinkLED.apk", // URL (web page to visit if no installed apps support the accessory)
-              "123456789"); // Serial Number (optional)
-
-uint32_t timer;
-bool connected;
-
-void setup() {
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  if (Usb.Init() == -1) {
-    Serial.print("\r\nOSCOKIRQ failed to assert");
-    while (1); // halt
-  }
-  pinMode(LED, OUTPUT);
-  Serial.print("\r\nArduino Blink LED Started");
-}
-
-void loop() {
-  Usb.Task();
-
-  if (adk.isReady()) {
-    if (!connected) {
-      connected = true;
-      Serial.print(F("\r\nConnected to accessory"));
-    }
-
-    uint8_t msg[1];
-    uint16_t len = sizeof(msg);
-    uint8_t rcode = adk.RcvData(&len, msg);
-    if (rcode && rcode != hrNAK) {
-      Serial.print(F("\r\nData rcv: "));
-      Serial.print(rcode, HEX);
-    } else if (len > 0) {
-      Serial.print(F("\r\nData Packet: "));
-      Serial.print(msg[0]);
-      digitalWrite(LED, msg[0] ? HIGH : LOW);
-    }
-
-    if (millis() - timer >= 1000) { // Send data every 1s
-      timer = millis();
-      rcode = adk.SndData(sizeof(timer), (uint8_t*)&timer);
-      if (rcode && rcode != hrNAK) {
-        Serial.print(F("\r\nData send: "));
-        Serial.print(rcode, HEX);
-      } else if (rcode != hrNAK) {
-        Serial.print(F("\r\nTimer: "));
-        Serial.print(timer);
-      }
-    }
-  } else {
-    if (connected) {
-      connected = false;
-      Serial.print(F("\r\nDisconnected from accessory"));
-      digitalWrite(LED, LOW);
-    }
-  }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/adk_barcode/adk_barcode.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/adk/adk_barcode/adk_barcode.ino
deleted file mode 100644
index a308ff0f83..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/adk_barcode/adk_barcode.ino
+++ /dev/null
@@ -1,91 +0,0 @@
-/**/
-/* A sketch demonstrating data exchange between two USB devices - a HID barcode scanner and ADK-compatible Android phone */
-/**/
-#include <adk.h>
-#include <hidboot.h>
-#include <usbhub.h>
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-USBHub Hub1(&Usb);
-USBHub Hub2(&Usb);
-HIDBoot<HID_PROTOCOL_KEYBOARD> Keyboard(&Usb);
-
-ADK adk(&Usb,"Circuits@Home, ltd.",
-            "USB Host Shield",
-            "Arduino Terminal for Android",
-            "1.0",
-            "http://www.circuitsathome.com",
-            "0000000000000001");
-
-
-class KbdRptParser : public KeyboardReportParser
-{
-
-protected:
-	void OnKeyDown	(uint8_t mod, uint8_t key);
-	void OnKeyPressed(uint8_t key);
-};
-
-void KbdRptParser::OnKeyDown(uint8_t mod, uint8_t key)
-{
-    uint8_t c = OemToAscii(mod, key);
-
-    if (c)
-        OnKeyPressed(c);
-}
-
-/* what to do when symbol arrives */
-void KbdRptParser::OnKeyPressed(uint8_t key)
-{
-const char* new_line = "\n";
-uint8_t rcode;
-uint8_t keylcl;
-
- if( adk.isReady() == false ) {
-   return;
- }
-
-  keylcl = key;
-
-  if( keylcl == 0x13 ) {
-    rcode = adk.SndData( strlen( new_line ), (uint8_t *)new_line );
-  }
-  else {
-    rcode = adk.SndData( 1, &keylcl );
-  }
-
-  Serial.print((char) keylcl );
-  Serial.print(" : ");
-  Serial.println( keylcl, HEX );
-};
-
-KbdRptParser Prs;
-
-void setup()
-{
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("\r\nADK demo start");
-
-  if (Usb.Init() == -1) {
-    Serial.println("OSCOKIRQ failed to assert");
-    while(1); //halt
-  }//if (Usb.Init() == -1...
-
-  Keyboard.SetReportParser(0, (HIDReportParser*)&Prs);
-
-  delay( 200 );
-}
-
-void loop()
-{
-  Usb.Task();
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/demokit_20/demokit_20.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/adk/demokit_20/demokit_20.ino
deleted file mode 100644
index f65adf57bb..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/demokit_20/demokit_20.ino
+++ /dev/null
@@ -1,103 +0,0 @@
-#include <adk.h>
-#include <usbhub.h>
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-USBHub hub0(&Usb);
-USBHub hub1(&Usb);
-ADK adk(&Usb,"Google, Inc.",
-            "DemoKit",
-            "DemoKit Arduino Board",
-            "1.0",
-            "http://www.android.com",
-            "0000000012345678");
-uint8_t  b, b1;
-
-
-#define  LED1_RED       3
-#define  BUTTON1        2
-
-void init_buttons()
-{
-	pinMode(BUTTON1, INPUT);
-
-	// enable the internal pullups
-	digitalWrite(BUTTON1, HIGH);
-}
-
-void init_leds()
-{
-	digitalWrite(LED1_RED, 0);
-
-	pinMode(LED1_RED, OUTPUT);
-}
-
-void setup()
-{
-	Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-	Serial.println("\r\nADK demo start");
-
-        if (Usb.Init() == -1) {
-          Serial.println("OSCOKIRQ failed to assert");
-        while(1); //halt
-        }//if (Usb.Init() == -1...
-
-
-	init_leds();
-	init_buttons();
-	b1 = digitalRead(BUTTON1);
-}
-
-void loop()
-{
-  uint8_t rcode;
-  uint8_t msg[3] = { 0x00 };
-   Usb.Task();
-
-   if( adk.isReady() == false ) {
-     analogWrite(LED1_RED, 255);
-     return;
-   }
-   uint16_t len = sizeof(msg);
-
-   rcode = adk.RcvData(&len, msg);
-   if( rcode ) {
-     USBTRACE2("Data rcv. :", rcode );
-   }
-   if(len > 0) {
-     USBTRACE("\r\nData Packet.");
-    // assumes only one command per packet
-    if (msg[0] == 0x2) {
-      switch( msg[1] ) {
-        case 0:
-          analogWrite(LED1_RED, 255 - msg[2]);
-          break;
-      }//switch( msg[1]...
-    }//if (msg[0] == 0x2...
-   }//if( len > 0...
-
-   msg[0] = 0x1;
-
-   b = digitalRead(BUTTON1);
-   if (b != b1) {
-     USBTRACE("\r\nButton state changed");
-     msg[1] = 0;
-     msg[2] = b ? 0 : 1;
-     rcode = adk.SndData( 3, msg );
-     if( rcode ) {
-       USBTRACE2("Button send: ", rcode );
-     }
-     b1 = b;
-    }//if (b != b1...
-
-
-      delay( 10 );
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/term_test/term_test.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/adk/term_test/term_test.ino
deleted file mode 100644
index db681c3b50..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/term_test/term_test.ino
+++ /dev/null
@@ -1,65 +0,0 @@
-#include <adk.h>
-#include <usbhub.h>
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-//USBHub     Hub(&Usb);
-
-ADK adk(&Usb,"Circuits@Home, ltd.",
-            "USB Host Shield",
-            "Arduino Terminal for Android",
-            "1.0",
-            "http://www.circuitsathome.com",
-            "0000000000000001");
-
-void setup()
-{
-	Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-	Serial.println("\r\nADK demo start");
-
-        if (Usb.Init() == -1) {
-          Serial.println("OSCOKIRQ failed to assert");
-        while(1); //halt
-        }//if (Usb.Init() == -1...
-}
-
-void loop()
-{
-  uint8_t rcode;
-  uint8_t msg[64] = { 0x00 };
-  const char* recv = "Received: ";
-
-   Usb.Task();
-
-   if( adk.isReady() == false ) {
-     return;
-   }
-   uint16_t len = 64;
-
-   rcode = adk.RcvData(&len, msg);
-   if( rcode & ( rcode != hrNAK )) {
-     USBTRACE2("Data rcv. :", rcode );
-   }
-   if(len > 0) {
-     USBTRACE("\r\nData Packet.");
-
-    for( uint8_t i = 0; i < len; i++ ) {
-      Serial.print((char)msg[i]);
-    }
-    /* sending back what was received */
-    rcode = adk.SndData( strlen( recv ), (uint8_t *)recv );
-    rcode = adk.SndData( strlen(( char * )msg ), msg );
-
-   }//if( len > 0 )...
-
-   delay( 1000 );
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/term_time/term_time.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/adk/term_time/term_time.ino
deleted file mode 100644
index a3f1dbc8cb..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/adk/term_time/term_time.ino
+++ /dev/null
@@ -1,50 +0,0 @@
-#include <adk.h>
-#include <usbhub.h>
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-
-ADK adk(&Usb,"Circuits@Home, ltd.",
-            "USB Host Shield",
-            "Arduino Terminal for Android",
-            "1.0",
-            "http://www.circuitsathome.com",
-            "0000000000000001");
-
-void setup()
-{
-	Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-	Serial.println("\r\nADK demo start");
-
-        if (Usb.Init() == -1) {
-          Serial.println("OSCOKIRQ failed to assert");
-        while(1); //halt
-        }//if (Usb.Init() == -1...
-}
-
-void loop()
-{
-  uint8_t buf[ 12 ] = { 0 }; //buffer to convert unsigned long to ASCII
-  const char* sec_ela = " seconds elapsed\r";
-  uint8_t rcode;
-
-   Usb.Task();
-   if( adk.isReady() == false ) {
-     return;
-   }
-
-    ultoa( millis()/1000, (char *)buf, 10 );
-
-    rcode = adk.SndData( strlen((char *)buf), buf );
-    rcode = adk.SndData( strlen( sec_ela), (uint8_t *)sec_ela );
-
-      delay( 1000 );
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/board_qc/board_qc.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/board_qc/board_qc.ino
deleted file mode 100644
index 573c3ce083..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/board_qc/board_qc.ino
+++ /dev/null
@@ -1,259 +0,0 @@
-/* USB Host Shield 2.0 board quality control routine */
-/* To see the output set your terminal speed to 115200 */
-/* for GPIO test to pass you need to connect GPIN0 to GPOUT7, GPIN1 to GPOUT6, etc. */
-/* otherwise press any key after getting GPIO error to complete the test */
-/**/
-#include <usbhub.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <../../../../hardware/pic32/libraries/SPI/SPI.h> // Hack to use the SPI library
-#include <SPI.h> // Hack to use the SPI library
-#endif
-
-/* variables */
-uint8_t rcode;
-uint8_t usbstate;
-uint8_t laststate;
-//uint8_t buf[sizeof(USB_DEVICE_DESCRIPTOR)];
-USB_DEVICE_DESCRIPTOR buf;
-
-/* objects */
-USB Usb;
-//USBHub hub(&Usb);
-
-void setup() {
-        laststate = 0;
-        Serial.begin(115200);
-#if !defined(__MIPSEL__)
-        while(!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-        E_Notify(PSTR("\r\nCircuits At Home 2011"), 0x80);
-        E_Notify(PSTR("\r\nUSB Host Shield Quality Control Routine"), 0x80);
-        /* SPI quick test - check revision register */
-        E_Notify(PSTR("\r\nReading REVISION register... Die revision "), 0x80);
-        Usb.Init(); // Initializes SPI, we don't care about the return value here
-        {
-                uint8_t tmpbyte = Usb.regRd(rREVISION);
-                switch(tmpbyte) {
-                        case( 0x01): //rev.01
-                                E_Notify(PSTR("01"), 0x80);
-                                break;
-                        case( 0x12): //rev.02
-                                E_Notify(PSTR("02"), 0x80);
-                                break;
-                        case( 0x13): //rev.03
-                                E_Notify(PSTR("03"), 0x80);
-                                break;
-                        default:
-                                E_Notify(PSTR("invalid. Value returned: "), 0x80);
-                                print_hex(tmpbyte, 8);
-                                halt55();
-                                break;
-                }//switch( tmpbyte...
-        }//check revision register
-        /* SPI long test */
-        {
-                E_Notify(PSTR("\r\nSPI long test. Transfers 1MB of data. Each dot is 64K"), 0x80);
-                uint8_t sample_wr = 0;
-                uint8_t sample_rd = 0;
-                uint8_t gpinpol_copy = Usb.regRd(rGPINPOL);
-                for(uint8_t i = 0; i < 16; i++) {
-                        for(uint16_t j = 0; j < 65535; j++) {
-                                Usb.regWr(rGPINPOL, sample_wr);
-                                sample_rd = Usb.regRd(rGPINPOL);
-                                if(sample_rd != sample_wr) {
-                                        E_Notify(PSTR("\r\nTest failed.  "), 0x80);
-                                        E_Notify(PSTR("Value written: "), 0x80);
-                                        print_hex(sample_wr, 8);
-                                        E_Notify(PSTR(" read: "), 0x80);
-                                        print_hex(sample_rd, 8);
-                                        halt55();
-                                }//if( sample_rd != sample_wr..
-                                sample_wr++;
-                        }//for( uint16_t j...
-                        E_Notify(PSTR("."), 0x80);
-                }//for( uint8_t i...
-                Usb.regWr(rGPINPOL, gpinpol_copy);
-                E_Notify(PSTR(" SPI long test passed"), 0x80);
-        }//SPI long test
-        /* GPIO test */
-        /* in order to simplify board layout, GPIN pins on text fixture are connected to GPOUT */
-        /* in reverse order, i.e, GPIN0 is connected to GPOUT7, GPIN1 to GPOUT6, etc. */
-        {
-                uint8_t tmpbyte;
-                E_Notify(PSTR("\r\nGPIO test. Connect GPIN0 to GPOUT7, GPIN1 to GPOUT6, and so on"), 0x80);
-                for(uint8_t sample_gpio = 0; sample_gpio < 255; sample_gpio++) {
-                        Usb.gpioWr(sample_gpio);
-                        tmpbyte = Usb.gpioRd();
-                        /* bit reversing code copied vetbatim from http://graphics.stanford.edu/~seander/bithacks.html#BitReverseObvious */
-                        tmpbyte = ((tmpbyte * 0x0802LU & 0x22110LU) | (tmpbyte * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16;
-                        if(sample_gpio != tmpbyte) {
-                                E_Notify(PSTR("\r\nTest failed. Value written: "), 0x80);
-                                print_hex(sample_gpio, 8);
-                                E_Notify(PSTR(" Value read: "), 0x80);
-                                print_hex(tmpbyte, 8);
-                                E_Notify(PSTR(" "), 0x80);
-                                press_any_key();
-                                break;
-                        }//if( sample_gpio != tmpbyte...
-                }//for( uint8_t sample_gpio...
-                E_Notify(PSTR("\r\nGPIO test passed."), 0x80);
-        }//GPIO test
-        /* PLL test. Stops/starts MAX3421E oscillator several times */
-        {
-                E_Notify(PSTR("\r\nPLL test. 100 chip resets will be performed"), 0x80);
-                /* check current state of the oscillator */
-                if(!(Usb.regRd(rUSBIRQ) & bmOSCOKIRQ)) { //wrong state - should be on
-                        E_Notify(PSTR("\r\nCurrent oscillator state unexpected."), 0x80);
-                        press_any_key();
-                }
-                /* Restart oscillator */
-                E_Notify(PSTR("\r\nResetting oscillator\r\n"), 0x80);
-                for(uint16_t i = 0; i < 100; i++) {
-                        E_Notify(PSTR("\rReset number "), 0x80);
-                        Serial.print(i, DEC);
-                        Usb.regWr(rUSBCTL, bmCHIPRES); //reset
-                        if(Usb.regRd(rUSBIRQ) & bmOSCOKIRQ) { //wrong state - should be off
-                                E_Notify(PSTR("\r\nCurrent oscillator state unexpected."), 0x80);
-                                halt55();
-                        }
-                        Usb.regWr(rUSBCTL, 0x00); //release from reset
-                        uint16_t j = 0;
-                        for(j = 1; j < 65535; j++) { //tracking off to on time
-                                if(Usb.regRd(rUSBIRQ) & bmOSCOKIRQ) {
-                                        E_Notify(PSTR(" Time to stabilize - "), 0x80);
-                                        Serial.print(j, DEC);
-                                        E_Notify(PSTR(" cycles\r\n"), 0x80);
-                                        break;
-                                }
-                        }//for( uint16_t j = 0; j < 65535; j++
-                        if(j == 0) {
-                                E_Notify(PSTR("PLL failed to stabilize"), 0x80);
-                                press_any_key();
-                        }
-                }//for( uint8_t i = 0; i < 255; i++
-
-        }//PLL test
-        /* initializing USB stack */
-        if(Usb.Init() == -1) {
-                E_Notify(PSTR("\r\nOSCOKIRQ failed to assert"), 0x80);
-                halt55();
-        }
-        E_Notify(PSTR("\r\nChecking USB device communication.\r\n"), 0x80);
-}
-
-void loop() {
-        delay(200);
-        Usb.Task();
-        usbstate = Usb.getUsbTaskState();
-        if(usbstate != laststate) {
-                laststate = usbstate;
-                /**/
-                switch(usbstate) {
-                        case( USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE):
-                                E_Notify(PSTR("\r\nWaiting for device..."), 0x80);
-                                break;
-                        case( USB_ATTACHED_SUBSTATE_RESET_DEVICE):
-                                E_Notify(PSTR("\r\nDevice connected. Resetting..."), 0x80);
-                                break;
-                        case( USB_ATTACHED_SUBSTATE_WAIT_SOF):
-                                E_Notify(PSTR("\r\nReset complete. Waiting for the first SOF..."), 0x80);
-                                break;
-                        case( USB_ATTACHED_SUBSTATE_GET_DEVICE_DESCRIPTOR_SIZE):
-                                E_Notify(PSTR("\r\nSOF generation started. Enumerating device..."), 0x80);
-                                break;
-                        case( USB_STATE_ADDRESSING):
-                                E_Notify(PSTR("\r\nSetting device address..."), 0x80);
-                                break;
-                        case( USB_STATE_RUNNING):
-                                E_Notify(PSTR("\r\nGetting device descriptor"), 0x80);
-                                rcode = Usb.getDevDescr(1, 0, sizeof (USB_DEVICE_DESCRIPTOR), (uint8_t*) & buf);
-
-                                if(rcode) {
-                                        E_Notify(PSTR("\r\nError reading device descriptor. Error code "), 0x80);
-                                        print_hex(rcode, 8);
-                                } else {
-                                        /**/
-                                        E_Notify(PSTR("\r\nDescriptor Length:\t"), 0x80);
-                                        print_hex(buf.bLength, 8);
-                                        E_Notify(PSTR("\r\nDescriptor type:\t"), 0x80);
-                                        print_hex(buf.bDescriptorType, 8);
-                                        E_Notify(PSTR("\r\nUSB version:\t\t"), 0x80);
-                                        print_hex(buf.bcdUSB, 16);
-                                        E_Notify(PSTR("\r\nDevice class:\t\t"), 0x80);
-                                        print_hex(buf.bDeviceClass, 8);
-                                        E_Notify(PSTR("\r\nDevice Subclass:\t"), 0x80);
-                                        print_hex(buf.bDeviceSubClass, 8);
-                                        E_Notify(PSTR("\r\nDevice Protocol:\t"), 0x80);
-                                        print_hex(buf.bDeviceProtocol, 8);
-                                        E_Notify(PSTR("\r\nMax.packet size:\t"), 0x80);
-                                        print_hex(buf.bMaxPacketSize0, 8);
-                                        E_Notify(PSTR("\r\nVendor  ID:\t\t"), 0x80);
-                                        print_hex(buf.idVendor, 16);
-                                        E_Notify(PSTR("\r\nProduct ID:\t\t"), 0x80);
-                                        print_hex(buf.idProduct, 16);
-                                        E_Notify(PSTR("\r\nRevision ID:\t\t"), 0x80);
-                                        print_hex(buf.bcdDevice, 16);
-                                        E_Notify(PSTR("\r\nMfg.string index:\t"), 0x80);
-                                        print_hex(buf.iManufacturer, 8);
-                                        E_Notify(PSTR("\r\nProd.string index:\t"), 0x80);
-                                        print_hex(buf.iProduct, 8);
-                                        E_Notify(PSTR("\r\nSerial number index:\t"), 0x80);
-                                        print_hex(buf.iSerialNumber, 8);
-                                        E_Notify(PSTR("\r\nNumber of conf.:\t"), 0x80);
-                                        print_hex(buf.bNumConfigurations, 8);
-                                        /**/
-                                        E_Notify(PSTR("\r\n\nAll tests passed. Press RESET to restart test"), 0x80);
-                                        while(1);
-                                }
-                                break;
-                        case( USB_STATE_ERROR):
-                                E_Notify(PSTR("\r\nUSB state machine reached error state"), 0x80);
-                                break;
-
-                        default:
-                                break;
-                }//switch( usbstate...
-        }
-}//loop()...
-
-/* constantly transmits 0x55 via SPI to aid probing */
-void halt55() {
-
-        E_Notify(PSTR("\r\nUnrecoverable error - test halted!!"), 0x80);
-        E_Notify(PSTR("\r\n0x55 pattern is transmitted via SPI"), 0x80);
-        E_Notify(PSTR("\r\nPress RESET to restart test"), 0x80);
-
-        while(1) {
-                Usb.regWr(0x55, 0x55);
-        }
-}
-
-/* prints hex numbers with leading zeroes */
-void print_hex(int v, int num_places) {
-        int mask = 0, n, num_nibbles, digit;
-
-        for(n = 1; n <= num_places; n++) {
-                mask = (mask << 1) | 0x0001;
-        }
-        v = v & mask; // truncate v to specified number of places
-
-        num_nibbles = num_places / 4;
-        if((num_places % 4) != 0) {
-                ++num_nibbles;
-        }
-        do {
-                digit = ((v >> (num_nibbles - 1) * 4)) & 0x0f;
-                Serial.print(digit, HEX);
-        } while(--num_nibbles);
-}
-
-/* prints "Press any key" and returns when key is pressed */
-void press_any_key() {
-        E_Notify(PSTR("\r\nPress any key to continue..."), 0x80);
-        while(Serial.available() <= 0); //wait for input
-        Serial.read(); //empty input buffer
-        return;
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/cdc_XR21B1411/XR_terminal/XR_terminal.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/cdc_XR21B1411/XR_terminal/XR_terminal.ino
deleted file mode 100644
index 0173a08b50..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/cdc_XR21B1411/XR_terminal/XR_terminal.ino
+++ /dev/null
@@ -1,83 +0,0 @@
-#include <cdc_XR21B1411.h>
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class ACMAsyncOper : public CDCAsyncOper
-{
-public:
-    uint8_t OnInit(ACM *pacm);
-};
-
-uint8_t ACMAsyncOper::OnInit(ACM *pacm)
-{
-    uint8_t rcode;
-    // Set DTR = 1 RTS=1
-    rcode = pacm->SetControlLineState(3);
-
-    if (rcode)
-    {
-        ErrorMessage<uint8_t>(PSTR("SetControlLineState"), rcode);
-        return rcode;
-    }
-
-    LINE_CODING	lc;
-    lc.dwDTERate	= 115200;
-    lc.bCharFormat	= 0;
-    lc.bParityType	= 0;
-    lc.bDataBits	= 8;
-
-    rcode = pacm->SetLineCoding(&lc);
-
-    if (rcode)
-        ErrorMessage<uint8_t>(PSTR("SetLineCoding"), rcode);
-
-    return rcode;
-}
-
-USB     Usb;
-ACMAsyncOper  AsyncOper;
-XR21B1411     Acm(&Usb, &AsyncOper);
-
-void setup() {
-        Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-        while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-        Serial.println("\r\n\r\nStart");
-
-        if (Usb.Init() == -1) Serial.println("OSCOKIRQ failed to assert");
-}
-
-void loop() {
-        Usb.Task();
-        if( Acm.isReady()) {
-                uint8_t rcode;
-                uint8_t  buf[1];
-                uint16_t rcvd = 1;
-
-                /* read keyboard */
-                if(Serial.available()) {
-                         uint8_t data = Serial.read();
-                         /* send */
-                         rcode = Acm.SndData(1, &data);
-                         if (rcode)
-                                 ErrorMessage<uint8_t>(PSTR("SndData"), rcode);
-                 }
-                
-                /* read XR serial */
-                rcode = Acm.RcvData(&rcvd, buf);
-                if (rcode && rcode != hrNAK)
-                        ErrorMessage<uint8_t>(PSTR("Ret"), rcode);
-
-                if( rcvd ) { //more than zero bytes received
-                        for(uint16_t i=0; i < rcvd; i++ ) {
-                                Serial.print((char)buf[i]);
-                        }
-                }
-        }
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/ftdi/USBFTDILoopback/USBFTDILoopback.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/ftdi/USBFTDILoopback/USBFTDILoopback.ino
deleted file mode 100644
index 5be7adc2f3..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/ftdi/USBFTDILoopback/USBFTDILoopback.ino
+++ /dev/null
@@ -1,98 +0,0 @@
-#include <cdcftdi.h>
-#include <usbhub.h>
-
-#include "pgmstrings.h"
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class FTDIAsync : public FTDIAsyncOper
-{
-public:
-    uint8_t OnInit(FTDI *pftdi);
-};
-
-uint8_t FTDIAsync::OnInit(FTDI *pftdi)
-{
-    uint8_t rcode = 0;
-
-    rcode = pftdi->SetBaudRate(115200);
-
-    if (rcode)
-    {
-        ErrorMessage<uint8_t>(PSTR("SetBaudRate"), rcode);
-        return rcode;
-    }
-    rcode = pftdi->SetFlowControl(FTDI_SIO_DISABLE_FLOW_CTRL);
-
-    if (rcode)
-        ErrorMessage<uint8_t>(PSTR("SetFlowControl"), rcode);
-
-    return rcode;
-}
-
-USB              Usb;
-//USBHub         Hub(&Usb);
-FTDIAsync        FtdiAsync;
-FTDI             Ftdi(&Usb, &FtdiAsync);
-
-uint32_t next_time;
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-      Serial.println("OSC did not start.");
-
-  delay( 200 );
-
-  next_time = millis() + 5000;
-}
-
-void loop()
-{
-    Usb.Task();
-
-    if( Usb.getUsbTaskState() == USB_STATE_RUNNING )
-    {
-        uint8_t  rcode;
-        char strbuf[] = "DEADBEEF";
-        //char strbuf[] = "The quick brown fox jumps over the lazy dog";
-        //char strbuf[] = "This string contains 61 character to demonstrate FTDI buffers"; //add one symbol to it to see some garbage
-        Serial.print(".");
-
-        rcode = Ftdi.SndData(strlen(strbuf), (uint8_t*)strbuf);
-
-	if (rcode)
-            ErrorMessage<uint8_t>(PSTR("SndData"), rcode);
-
-        delay(50);
-
-        uint8_t  buf[64];
-
-        for (uint8_t i=0; i<64; i++)
-            buf[i] = 0;
-
-        uint16_t rcvd = 64;
-        rcode = Ftdi.RcvData(&rcvd, buf);
-
-        if (rcode && rcode != hrNAK)
-            ErrorMessage<uint8_t>(PSTR("Ret"), rcode);
-
-        // The device reserves the first two bytes of data
-        //   to contain the current values of the modem and line status registers.
-        if (rcvd > 2)
-            Serial.print((char*)(buf+2));
-
-        delay(10);
-    }
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/ftdi/USBFTDILoopback/pgmstrings.h b/lib/usbhost/USB_Host_Shield_2.0/examples/ftdi/USBFTDILoopback/pgmstrings.h
deleted file mode 100644
index bdb0077ecc..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/ftdi/USBFTDILoopback/pgmstrings.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#if !defined(__PGMSTRINGS_H__)
-#define __PGMSTRINGS_H__
-
-#define LOBYTE(x) ((char*)(&(x)))[0]
-#define HIBYTE(x) ((char*)(&(x)))[1]
-#define BUFSIZE 256    //buffer size
- 
-
-/* Print strings in Program Memory */
-const char Gen_Error_str[] PROGMEM = "\r\nRequest error. Error code:\t"; 
-const char Dev_Header_str[] PROGMEM ="\r\nDevice descriptor: ";
-const char Dev_Length_str[] PROGMEM ="\r\nDescriptor Length:\t";
-const char Dev_Type_str[] PROGMEM ="\r\nDescriptor type:\t";
-const char Dev_Version_str[] PROGMEM ="\r\nUSB version:\t\t";
-const char Dev_Class_str[] PROGMEM ="\r\nDevice class:\t\t";
-const char Dev_Subclass_str[] PROGMEM ="\r\nDevice Subclass:\t";
-const char Dev_Protocol_str[] PROGMEM ="\r\nDevice Protocol:\t";
-const char Dev_Pktsize_str[] PROGMEM ="\r\nMax.packet size:\t";
-const char Dev_Vendor_str[] PROGMEM ="\r\nVendor  ID:\t\t";
-const char Dev_Product_str[] PROGMEM ="\r\nProduct ID:\t\t";
-const char Dev_Revision_str[] PROGMEM ="\r\nRevision ID:\t\t";
-const char Dev_Mfg_str[] PROGMEM ="\r\nMfg.string index:\t";
-const char Dev_Prod_str[] PROGMEM ="\r\nProd.string index:\t";
-const char Dev_Serial_str[] PROGMEM ="\r\nSerial number index:\t";
-const char Dev_Nconf_str[] PROGMEM ="\r\nNumber of conf.:\t";
-const char Conf_Trunc_str[] PROGMEM ="Total length truncated to 256 bytes";
-const char Conf_Header_str[] PROGMEM ="\r\nConfiguration descriptor:";
-const char Conf_Totlen_str[] PROGMEM ="\r\nTotal length:\t\t";
-const char Conf_Nint_str[] PROGMEM ="\r\nNum.intf:\t\t";
-const char Conf_Value_str[] PROGMEM ="\r\nConf.value:\t\t";
-const char Conf_String_str[] PROGMEM ="\r\nConf.string:\t\t";
-const char Conf_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char Conf_Pwr_str[] PROGMEM ="\r\nMax.pwr:\t\t";
-const char Int_Header_str[] PROGMEM ="\r\n\r\nInterface descriptor:";
-const char Int_Number_str[] PROGMEM ="\r\nIntf.number:\t\t";
-const char Int_Alt_str[] PROGMEM ="\r\nAlt.:\t\t\t";
-const char Int_Endpoints_str[] PROGMEM ="\r\nEndpoints:\t\t";
-const char Int_Class_str[] PROGMEM ="\r\nIntf. Class:\t\t";
-const char Int_Subclass_str[] PROGMEM ="\r\nIntf. Subclass:\t\t";
-const char Int_Protocol_str[] PROGMEM ="\r\nIntf. Protocol:\t\t";
-const char Int_String_str[] PROGMEM ="\r\nIntf.string:\t\t";
-const char End_Header_str[] PROGMEM ="\r\n\r\nEndpoint descriptor:";
-const char End_Address_str[] PROGMEM ="\r\nEndpoint address:\t";
-const char End_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char End_Pktsize_str[] PROGMEM ="\r\nMax.pkt size:\t\t";
-const char End_Interval_str[] PROGMEM ="\r\nPolling interval:\t";
-const char Unk_Header_str[] PROGMEM = "\r\nUnknown descriptor:";
-const char Unk_Length_str[] PROGMEM ="\r\nLength:\t\t";
-const char Unk_Type_str[] PROGMEM ="\r\nType:\t\t";
-const char Unk_Contents_str[] PROGMEM ="\r\nContents:\t";
- 
-#endif // __PGMSTRINGS_H__
\ No newline at end of file
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/hub_demo/hub_demo.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/hub_demo/hub_demo.ino
deleted file mode 100644
index d8b2d4bb72..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/hub_demo/hub_demo.ino
+++ /dev/null
@@ -1,345 +0,0 @@
-#include <usbhub.h>
-#include "pgmstrings.h"
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB     Usb;
-USBHub  Hub1(&Usb);
-USBHub  Hub2(&Usb);
-USBHub  Hub3(&Usb);
-USBHub  Hub4(&Usb);
-
-uint32_t next_time;
-
-void PrintAllAddresses(UsbDevice *pdev)
-{
-  UsbDeviceAddress adr;
-  adr.devAddress = pdev->address.devAddress;
-  Serial.print("\r\nAddr:");
-  Serial.print(adr.devAddress, HEX);
-  Serial.print("(");
-  Serial.print(adr.bmHub, HEX);
-  Serial.print(".");
-  Serial.print(adr.bmParent, HEX);
-  Serial.print(".");
-  Serial.print(adr.bmAddress, HEX);
-  Serial.println(")");
-}
-
-void PrintAddress(uint8_t addr)
-{
-  UsbDeviceAddress adr;
-  adr.devAddress = addr;
-  Serial.print("\r\nADDR:\t");
-  Serial.println(adr.devAddress, HEX);
-  Serial.print("DEV:\t");
-  Serial.println(adr.bmAddress, HEX);
-  Serial.print("PRNT:\t");
-  Serial.println(adr.bmParent, HEX);
-  Serial.print("HUB:\t");
-  Serial.println(adr.bmHub, HEX);
-}
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-    Serial.println("OSC did not start.");
-
-  delay( 200 );
-
-  next_time = millis() + 10000;
-}
-
-byte getdevdescr( byte addr, byte &num_conf );
-
-void PrintDescriptors(uint8_t addr)
-{
-  uint8_t rcode = 0;
-  byte num_conf = 0;
-
-  rcode = getdevdescr( (byte)addr, num_conf );
-  if ( rcode )
-  {
-    printProgStr(Gen_Error_str);
-    print_hex( rcode, 8 );
-  }
-  Serial.print("\r\n");
-
-  for (int i = 0; i < num_conf; i++)
-  {
-    rcode = getconfdescr( addr, i );                 // get configuration descriptor
-    if ( rcode )
-    {
-      printProgStr(Gen_Error_str);
-      print_hex(rcode, 8);
-    }
-    Serial.println("\r\n");
-  }
-}
-
-void PrintAllDescriptors(UsbDevice *pdev)
-{
-  Serial.println("\r\n");
-  print_hex(pdev->address.devAddress, 8);
-  Serial.println("\r\n--");
-  PrintDescriptors( pdev->address.devAddress );
-}
-
-void loop()
-{
-  Usb.Task();
-
-  if ( Usb.getUsbTaskState() == USB_STATE_RUNNING )
-  {
-    if ((millis() - next_time) >= 0L)
-    {
-      Usb.ForEachUsbDevice(&PrintAllDescriptors);
-      Usb.ForEachUsbDevice(&PrintAllAddresses);
-
-      while ( 1 );                          //stop
-    }
-  }
-}
-
-byte getdevdescr( byte addr, byte &num_conf )
-{
-  USB_DEVICE_DESCRIPTOR buf;
-  byte rcode;
-  rcode = Usb.getDevDescr( addr, 0, 0x12, ( uint8_t *)&buf );
-  if ( rcode ) {
-    return ( rcode );
-  }
-  printProgStr(Dev_Header_str);
-  printProgStr(Dev_Length_str);
-  print_hex( buf.bLength, 8 );
-  printProgStr(Dev_Type_str);
-  print_hex( buf.bDescriptorType, 8 );
-  printProgStr(Dev_Version_str);
-  print_hex( buf.bcdUSB, 16 );
-  printProgStr(Dev_Class_str);
-  print_hex( buf.bDeviceClass, 8 );
-  printProgStr(Dev_Subclass_str);
-  print_hex( buf.bDeviceSubClass, 8 );
-  printProgStr(Dev_Protocol_str);
-  print_hex( buf.bDeviceProtocol, 8 );
-  printProgStr(Dev_Pktsize_str);
-  print_hex( buf.bMaxPacketSize0, 8 );
-  printProgStr(Dev_Vendor_str);
-  print_hex( buf.idVendor, 16 );
-  printProgStr(Dev_Product_str);
-  print_hex( buf.idProduct, 16 );
-  printProgStr(Dev_Revision_str);
-  print_hex( buf.bcdDevice, 16 );
-  printProgStr(Dev_Mfg_str);
-  print_hex( buf.iManufacturer, 8 );
-  printProgStr(Dev_Prod_str);
-  print_hex( buf.iProduct, 8 );
-  printProgStr(Dev_Serial_str);
-  print_hex( buf.iSerialNumber, 8 );
-  printProgStr(Dev_Nconf_str);
-  print_hex( buf.bNumConfigurations, 8 );
-  num_conf = buf.bNumConfigurations;
-  return ( 0 );
-}
-
-void printhubdescr(uint8_t *descrptr, uint8_t addr)
-{
-  HubDescriptor  *pHub = (HubDescriptor*) descrptr;
-  uint8_t        len = *((uint8_t*)descrptr);
-
-  printProgStr(PSTR("\r\n\r\nHub Descriptor:\r\n"));
-  printProgStr(PSTR("bDescLength:\t\t"));
-  Serial.println(pHub->bDescLength, HEX);
-
-  printProgStr(PSTR("bDescriptorType:\t"));
-  Serial.println(pHub->bDescriptorType, HEX);
-
-  printProgStr(PSTR("bNbrPorts:\t\t"));
-  Serial.println(pHub->bNbrPorts, HEX);
-
-  printProgStr(PSTR("LogPwrSwitchMode:\t"));
-  Serial.println(pHub->LogPwrSwitchMode, BIN);
-
-  printProgStr(PSTR("CompoundDevice:\t\t"));
-  Serial.println(pHub->CompoundDevice, BIN);
-
-  printProgStr(PSTR("OverCurrentProtectMode:\t"));
-  Serial.println(pHub->OverCurrentProtectMode, BIN);
-
-  printProgStr(PSTR("TTThinkTime:\t\t"));
-  Serial.println(pHub->TTThinkTime, BIN);
-
-  printProgStr(PSTR("PortIndicatorsSupported:"));
-  Serial.println(pHub->PortIndicatorsSupported, BIN);
-
-  printProgStr(PSTR("Reserved:\t\t"));
-  Serial.println(pHub->Reserved, HEX);
-
-  printProgStr(PSTR("bPwrOn2PwrGood:\t\t"));
-  Serial.println(pHub->bPwrOn2PwrGood, HEX);
-
-  printProgStr(PSTR("bHubContrCurrent:\t"));
-  Serial.println(pHub->bHubContrCurrent, HEX);
-
-  for (uint8_t i = 7; i < len; i++)
-    print_hex(descrptr[i], 8);
-
-  //for (uint8_t i=1; i<=pHub->bNbrPorts; i++)
-  //    PrintHubPortStatus(&Usb, addr, i, 1);
-}
-
-byte getconfdescr( byte addr, byte conf )
-{
-  uint8_t buf[ BUFSIZE ];
-  uint8_t* buf_ptr = buf;
-  byte rcode;
-  byte descr_length;
-  byte descr_type;
-  unsigned int total_length;
-  rcode = Usb.getConfDescr( addr, 0, 4, conf, buf );  //get total length
-  LOBYTE( total_length ) = buf[ 2 ];
-  HIBYTE( total_length ) = buf[ 3 ];
-  if ( total_length > 256 ) {   //check if total length is larger than buffer
-    printProgStr(Conf_Trunc_str);
-    total_length = 256;
-  }
-  rcode = Usb.getConfDescr( addr, 0, total_length, conf, buf ); //get the whole descriptor
-  while ( buf_ptr < buf + total_length ) { //parsing descriptors
-    descr_length = *( buf_ptr );
-    descr_type = *( buf_ptr + 1 );
-    switch ( descr_type ) {
-      case ( USB_DESCRIPTOR_CONFIGURATION ):
-        printconfdescr( buf_ptr );
-        break;
-      case ( USB_DESCRIPTOR_INTERFACE ):
-        printintfdescr( buf_ptr );
-        break;
-      case ( USB_DESCRIPTOR_ENDPOINT ):
-        printepdescr( buf_ptr );
-        break;
-      case 0x29:
-        printhubdescr( buf_ptr, addr );
-        break;
-      default:
-        printunkdescr( buf_ptr );
-        break;
-    }//switch( descr_type
-    buf_ptr = ( buf_ptr + descr_length );    //advance buffer pointer
-  }//while( buf_ptr <=...
-  return ( rcode );
-}
-/* prints hex numbers with leading zeroes */
-// copyright, Peter H Anderson, Baltimore, MD, Nov, '07
-// source: http://www.phanderson.com/arduino/arduino_display.html
-void print_hex(int v, int num_places)
-{
-  int mask = 0, n, num_nibbles, digit;
-
-  for (n = 1; n <= num_places; n++) {
-    mask = (mask << 1) | 0x0001;
-  }
-  v = v & mask; // truncate v to specified number of places
-
-  num_nibbles = num_places / 4;
-  if ((num_places % 4) != 0) {
-    ++num_nibbles;
-  }
-  do {
-    digit = ((v >> (num_nibbles - 1) * 4)) & 0x0f;
-    Serial.print(digit, HEX);
-  }
-  while (--num_nibbles);
-}
-/* function to print configuration descriptor */
-void printconfdescr( uint8_t* descr_ptr )
-{
-  USB_CONFIGURATION_DESCRIPTOR* conf_ptr = ( USB_CONFIGURATION_DESCRIPTOR* )descr_ptr;
-  printProgStr(Conf_Header_str);
-  printProgStr(Conf_Totlen_str);
-  print_hex( conf_ptr->wTotalLength, 16 );
-  printProgStr(Conf_Nint_str);
-  print_hex( conf_ptr->bNumInterfaces, 8 );
-  printProgStr(Conf_Value_str);
-  print_hex( conf_ptr->bConfigurationValue, 8 );
-  printProgStr(Conf_String_str);
-  print_hex( conf_ptr->iConfiguration, 8 );
-  printProgStr(Conf_Attr_str);
-  print_hex( conf_ptr->bmAttributes, 8 );
-  printProgStr(Conf_Pwr_str);
-  print_hex( conf_ptr->bMaxPower, 8 );
-  return;
-}
-/* function to print interface descriptor */
-void printintfdescr( uint8_t* descr_ptr )
-{
-  USB_INTERFACE_DESCRIPTOR* intf_ptr = ( USB_INTERFACE_DESCRIPTOR* )descr_ptr;
-  printProgStr(Int_Header_str);
-  printProgStr(Int_Number_str);
-  print_hex( intf_ptr->bInterfaceNumber, 8 );
-  printProgStr(Int_Alt_str);
-  print_hex( intf_ptr->bAlternateSetting, 8 );
-  printProgStr(Int_Endpoints_str);
-  print_hex( intf_ptr->bNumEndpoints, 8 );
-  printProgStr(Int_Class_str);
-  print_hex( intf_ptr->bInterfaceClass, 8 );
-  printProgStr(Int_Subclass_str);
-  print_hex( intf_ptr->bInterfaceSubClass, 8 );
-  printProgStr(Int_Protocol_str);
-  print_hex( intf_ptr->bInterfaceProtocol, 8 );
-  printProgStr(Int_String_str);
-  print_hex( intf_ptr->iInterface, 8 );
-  return;
-}
-/* function to print endpoint descriptor */
-void printepdescr( uint8_t* descr_ptr )
-{
-  USB_ENDPOINT_DESCRIPTOR* ep_ptr = ( USB_ENDPOINT_DESCRIPTOR* )descr_ptr;
-  printProgStr(End_Header_str);
-  printProgStr(End_Address_str);
-  print_hex( ep_ptr->bEndpointAddress, 8 );
-  printProgStr(End_Attr_str);
-  print_hex( ep_ptr->bmAttributes, 8 );
-  printProgStr(End_Pktsize_str);
-  print_hex( ep_ptr->wMaxPacketSize, 16 );
-  printProgStr(End_Interval_str);
-  print_hex( ep_ptr->bInterval, 8 );
-
-  return;
-}
-/*function to print unknown descriptor */
-void printunkdescr( uint8_t* descr_ptr )
-{
-  byte length = *descr_ptr;
-  byte i;
-  printProgStr(Unk_Header_str);
-  printProgStr(Unk_Length_str);
-  print_hex( *descr_ptr, 8 );
-  printProgStr(Unk_Type_str);
-  print_hex( *(descr_ptr + 1 ), 8 );
-  printProgStr(Unk_Contents_str);
-  descr_ptr += 2;
-  for ( i = 0; i < length; i++ ) {
-    print_hex( *descr_ptr, 8 );
-    descr_ptr++;
-  }
-}
-
-
-/* Print a string from Program Memory directly to save RAM */
-void printProgStr(const char* str)
-{
-  char c;
-  if (!str) return;
-  while ((c = pgm_read_byte(str++)))
-    Serial.print(c);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/hub_demo/pgmstrings.h b/lib/usbhost/USB_Host_Shield_2.0/examples/hub_demo/pgmstrings.h
deleted file mode 100644
index bdb0077ecc..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/hub_demo/pgmstrings.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#if !defined(__PGMSTRINGS_H__)
-#define __PGMSTRINGS_H__
-
-#define LOBYTE(x) ((char*)(&(x)))[0]
-#define HIBYTE(x) ((char*)(&(x)))[1]
-#define BUFSIZE 256    //buffer size
- 
-
-/* Print strings in Program Memory */
-const char Gen_Error_str[] PROGMEM = "\r\nRequest error. Error code:\t"; 
-const char Dev_Header_str[] PROGMEM ="\r\nDevice descriptor: ";
-const char Dev_Length_str[] PROGMEM ="\r\nDescriptor Length:\t";
-const char Dev_Type_str[] PROGMEM ="\r\nDescriptor type:\t";
-const char Dev_Version_str[] PROGMEM ="\r\nUSB version:\t\t";
-const char Dev_Class_str[] PROGMEM ="\r\nDevice class:\t\t";
-const char Dev_Subclass_str[] PROGMEM ="\r\nDevice Subclass:\t";
-const char Dev_Protocol_str[] PROGMEM ="\r\nDevice Protocol:\t";
-const char Dev_Pktsize_str[] PROGMEM ="\r\nMax.packet size:\t";
-const char Dev_Vendor_str[] PROGMEM ="\r\nVendor  ID:\t\t";
-const char Dev_Product_str[] PROGMEM ="\r\nProduct ID:\t\t";
-const char Dev_Revision_str[] PROGMEM ="\r\nRevision ID:\t\t";
-const char Dev_Mfg_str[] PROGMEM ="\r\nMfg.string index:\t";
-const char Dev_Prod_str[] PROGMEM ="\r\nProd.string index:\t";
-const char Dev_Serial_str[] PROGMEM ="\r\nSerial number index:\t";
-const char Dev_Nconf_str[] PROGMEM ="\r\nNumber of conf.:\t";
-const char Conf_Trunc_str[] PROGMEM ="Total length truncated to 256 bytes";
-const char Conf_Header_str[] PROGMEM ="\r\nConfiguration descriptor:";
-const char Conf_Totlen_str[] PROGMEM ="\r\nTotal length:\t\t";
-const char Conf_Nint_str[] PROGMEM ="\r\nNum.intf:\t\t";
-const char Conf_Value_str[] PROGMEM ="\r\nConf.value:\t\t";
-const char Conf_String_str[] PROGMEM ="\r\nConf.string:\t\t";
-const char Conf_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char Conf_Pwr_str[] PROGMEM ="\r\nMax.pwr:\t\t";
-const char Int_Header_str[] PROGMEM ="\r\n\r\nInterface descriptor:";
-const char Int_Number_str[] PROGMEM ="\r\nIntf.number:\t\t";
-const char Int_Alt_str[] PROGMEM ="\r\nAlt.:\t\t\t";
-const char Int_Endpoints_str[] PROGMEM ="\r\nEndpoints:\t\t";
-const char Int_Class_str[] PROGMEM ="\r\nIntf. Class:\t\t";
-const char Int_Subclass_str[] PROGMEM ="\r\nIntf. Subclass:\t\t";
-const char Int_Protocol_str[] PROGMEM ="\r\nIntf. Protocol:\t\t";
-const char Int_String_str[] PROGMEM ="\r\nIntf.string:\t\t";
-const char End_Header_str[] PROGMEM ="\r\n\r\nEndpoint descriptor:";
-const char End_Address_str[] PROGMEM ="\r\nEndpoint address:\t";
-const char End_Attr_str[] PROGMEM ="\r\nAttr.:\t\t\t";
-const char End_Pktsize_str[] PROGMEM ="\r\nMax.pkt size:\t\t";
-const char End_Interval_str[] PROGMEM ="\r\nPolling interval:\t";
-const char Unk_Header_str[] PROGMEM = "\r\nUnknown descriptor:";
-const char Unk_Length_str[] PROGMEM ="\r\nLength:\t\t";
-const char Unk_Type_str[] PROGMEM ="\r\nType:\t\t";
-const char Unk_Contents_str[] PROGMEM ="\r\nContents:\t";
- 
-#endif // __PGMSTRINGS_H__
\ No newline at end of file
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/max_LCD/max_LCD.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/max_LCD/max_LCD.ino
deleted file mode 100644
index 6603ab90db..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/max_LCD/max_LCD.ino
+++ /dev/null
@@ -1,29 +0,0 @@
-// Just a copy of the HelloWorld example bundled with the LiquidCrystal library in the Arduino IDE
-
-// HD44780 compatible LCD display via MAX3421E GPOUT support header
-// pinout: D[4-7] -> GPOUT[4-7], RS-> GPOUT[2], E ->GPOUT[3]
-
-#include <max_LCD.h>
-
-// Satisfy IDE, which only needs to see the include statment in the ino.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-USB Usb;
-Max_LCD lcd(&Usb);
-
-void setup() {
-  // Set up the LCD's number of columns and rows:
-  lcd.begin(16, 2);
-  // Print a message to the LCD.
-  lcd.print("Hello, World!");
-}
-
-void loop() {
-  // Set the cursor to column 0, line 1 (note: line 1 is the second row, since counting begins with 0):
-  lcd.setCursor(0, 1);
-  // Print the number of seconds since reset:
-  lcd.print(millis() / 1000);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_gprs_terminal/pl2303_gprs_terminal.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_gprs_terminal/pl2303_gprs_terminal.ino
deleted file mode 100644
index 7c4c9f6cbe..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_gprs_terminal/pl2303_gprs_terminal.ino
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Arduino terminal for PL2303 USB to serial converter and DealeXtreme GPRS modem. */
-/* USB support */
-#include <usbhub.h>
-/* CDC support */
-#include <cdcacm.h>
-#include <cdcprolific.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class PLAsyncOper : public CDCAsyncOper
-{
-public:
-    uint8_t OnInit(ACM *pacm);
-};
-
-uint8_t PLAsyncOper::OnInit(ACM *pacm)
-{
-    uint8_t rcode;
-
-    // Set DTR = 1
-    rcode = pacm->SetControlLineState(1);
-
-    if (rcode)
-    {
-        ErrorMessage<uint8_t>(PSTR("SetControlLineState"), rcode);
-        return rcode;
-    }
-
-    LINE_CODING	lc;
-    //lc.dwDTERate	= 9600;
-    lc.dwDTERate = 115200;
-    lc.bCharFormat	= 0;
-    lc.bParityType	= 0;
-    lc.bDataBits	= 8;
-
-    rcode = pacm->SetLineCoding(&lc);
-
-    if (rcode)
-        ErrorMessage<uint8_t>(PSTR("SetLineCoding"), rcode);
-
-    return rcode;
-}
-USB     Usb;
-//USBHub     Hub(&Usb);
-PLAsyncOper  AsyncOper;
-PL2303       Pl(&Usb, &AsyncOper);
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-      Serial.println("OSCOKIRQ failed to assert");
-
-  delay( 200 );
-}
-
-void loop()
-{
-    Usb.Task();
-
-    if( Usb.getUsbTaskState() == USB_STATE_RUNNING )
-    {
-       uint8_t rcode;
-
-       /* reading the keyboard */
-       if(Serial.available()) {
-         uint8_t data= Serial.read();
-
-         /* sending to the phone */
-         rcode = Pl.SndData(1, &data);
-         if (rcode)
-            ErrorMessage<uint8_t>(PSTR("SndData"), rcode);
-       }//if(Serial.available()...
-
-        /* reading the converter */
-        /* buffer size must be greater or equal to max.packet size */
-        /* it it set to 64 (largest possible max.packet size) here, can be tuned down
-        for particular endpoint */
-        uint8_t  buf[64];
-        uint16_t rcvd = 64;
-        rcode = Pl.RcvData(&rcvd, buf);
-         if (rcode && rcode != hrNAK)
-           ErrorMessage<uint8_t>(PSTR("Ret"), rcode);
-
-           if( rcvd ) { //more than zero bytes received
-             for(uint16_t i=0; i < rcvd; i++ ) {
-               Serial.print((char)buf[i]); //printing on the screen
-             }
-           }//if( rcvd ...
-    }//if( Usb.getUsbTaskState() == USB_STATE_RUNNING..
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_gps/pl2303_gps.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_gps/pl2303_gps.ino
deleted file mode 100644
index e8c8a02230..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_gps/pl2303_gps.ino
+++ /dev/null
@@ -1,88 +0,0 @@
-/* USB Host to PL2303-based USB GPS unit interface */
-/* Navibee GM720 receiver - Sirf Star III */
-/* USB support */
-#include <usbhub.h>
-/* CDC support */
-#include <cdcacm.h>
-#include <cdcprolific.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class PLAsyncOper : public CDCAsyncOper {
-public:
-        uint8_t OnInit(ACM *pacm);
-};
-
-uint8_t PLAsyncOper::OnInit(ACM *pacm) {
-        uint8_t rcode;
-
-        // Set DTR = 1
-        rcode = pacm->SetControlLineState(1);
-
-        if(rcode) {
-                ErrorMessage<uint8_t>(PSTR("SetControlLineState"), rcode);
-                return rcode;
-        }
-
-        LINE_CODING lc;
-        lc.dwDTERate = 4800; //default serial speed of GPS unit
-        lc.bCharFormat = 0;
-        lc.bParityType = 0;
-        lc.bDataBits = 8;
-
-        rcode = pacm->SetLineCoding(&lc);
-
-        if(rcode)
-                ErrorMessage<uint8_t>(PSTR("SetLineCoding"), rcode);
-
-        return rcode;
-}
-
-USB Usb;
-USBHub Hub(&Usb);
-PLAsyncOper AsyncOper;
-PL2303 Pl(&Usb, &AsyncOper);
-uint32_t read_delay;
-#define READ_DELAY 100
-
-void setup() {
-        Serial.begin(115200);
-#if !defined(__MIPSEL__)
-        while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-        Serial.println("Start");
-
-        if(Usb.Init() == -1)
-                Serial.println("OSCOKIRQ failed to assert");
-
-        delay(200);
-}
-
-void loop() {
-        uint8_t rcode;
-        uint8_t buf[64]; //serial buffer equals Max.packet size of bulk-IN endpoint
-        uint16_t rcvd = 64;
-
-        Usb.Task();
-
-        if(Pl.isReady()) {
-                /* reading the GPS */
-                if((long)(millis() - read_delay) >= 0L) {
-                        read_delay += READ_DELAY;
-                        rcode = Pl.RcvData(&rcvd, buf);
-                        if(rcode && rcode != hrNAK)
-                                ErrorMessage<uint8_t>(PSTR("Ret"), rcode);
-                        if(rcvd) { //more than zero bytes received
-                                for(uint16_t i = 0; i < rcvd; i++) {
-                                        Serial.print((char)buf[i]); //printing on the screen
-                                }//for( uint16_t i=0; i < rcvd; i++...
-                        }//if( rcvd
-                }//if( read_delay > millis()...
-        }//if( Usb.getUsbTaskState() == USB_STATE_RUNNING..
-}
-
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_tinygps/pl2303_tinygps.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_tinygps/pl2303_tinygps.ino
deleted file mode 100644
index d527eabe00..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_tinygps/pl2303_tinygps.ino
+++ /dev/null
@@ -1,217 +0,0 @@
-/* USB Host to PL2303-based USB GPS unit interface */
-/* Navibee GM720 receiver - Sirf Star III */
-/* Mikal Hart's TinyGPS library */
-/* test_with_gps_device library example modified for PL2302 access */
-
-/* USB support */
-#include <usbhub.h>
-
-/* CDC support */
-#include <cdcacm.h>
-#include <cdcprolific.h>
-
-#include <TinyGPS.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-/* This sample code demonstrates the normal use of a TinyGPS object.
-    Modified to be used with USB Host Shield Library r2.0
-    and USB Host Shield 2.0
-*/
-
-class PLAsyncOper : public CDCAsyncOper
-{
-public:
-    uint8_t OnInit(ACM *pacm);
-};
-
-uint8_t PLAsyncOper::OnInit(ACM *pacm)
-{
-    uint8_t rcode;
-
-    // Set DTR = 1
-    rcode = pacm->SetControlLineState(1);
-
-    if (rcode) {
-        ErrorMessage<uint8_t>(PSTR("SetControlLineState"), rcode);
-        return rcode;
-    }
-
-    LINE_CODING lc;
-    lc.dwDTERate  = 4800;   //default serial speed of GPS unit
-    lc.bCharFormat  = 0;
-    lc.bParityType  = 0;
-    lc.bDataBits  = 8;
-
-    rcode = pacm->SetLineCoding(&lc);
-
-    if (rcode) {
-        ErrorMessage<uint8_t>(PSTR("SetLineCoding"), rcode);
-    }
-
-    return rcode;
-}
-
-USB     Usb;
-//USBHub     Hub(&Usb);
-PLAsyncOper  AsyncOper;
-PL2303       Pl(&Usb, &AsyncOper);
-TinyGPS gps;
-
-void gpsdump(TinyGPS &gps);
-bool feedgps();
-void printFloat(double f, int digits = 2);
-
-void setup()
-{
-
-  Serial.begin(115200);
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-
-  Serial.print("Testing TinyGPS library v. "); Serial.println(TinyGPS::library_version());
-  Serial.println("by Mikal Hart");
-  Serial.println();
-  Serial.print("Sizeof(gpsobject) = "); Serial.println(sizeof(TinyGPS));
-  Serial.println();
-  /* USB Initialization */
-  if (Usb.Init() == -1) {
-      Serial.println("OSCOKIRQ failed to assert");
-  }
-
-  delay( 200 );
-}
-
-void loop()
-{
-  Usb.Task();
-
-  if( Pl.isReady()) {
-
-    bool newdata = false;
-    unsigned long start = millis();
-
-    // Every 5 seconds we print an update
-    while (millis() - start < 5000) {
-      if( feedgps()) {
-        newdata = true;
-      }
-    }//while (millis()...
-
-    if (newdata) {
-      Serial.println("Acquired Data");
-      Serial.println("-------------");
-      gpsdump(gps);
-      Serial.println("-------------");
-      Serial.println();
-    }//if( newdata...
-  }//if( Usb.getUsbTaskState() == USB_STATE_RUNNING...
-}
-
-void printFloat(double number, int digits)
-{
-  // Handle negative numbers
-  if (number < 0.0)
-  {
-     Serial.print('-');
-     number = -number;
-  }
-
-  // Round correctly so that print(1.999, 2) prints as "2.00"
-  double rounding = 0.5;
-  for (uint8_t i=0; i<digits; ++i)
-    rounding /= 10.0;
-
-  number += rounding;
-
-  // Extract the integer part of the number and print it
-  unsigned long int_part = (unsigned long)number;
-  double remainder = number - (double)int_part;
-  Serial.print(int_part);
-
-  // Print the decimal point, but only if there are digits beyond
-  if (digits > 0)
-    Serial.print(".");
-
-  // Extract digits from the remainder one at a time
-  while (digits-- > 0)
-  {
-    remainder *= 10.0;
-    int toPrint = int(remainder);
-    Serial.print(toPrint);
-    remainder -= toPrint;
-  }
-}
-
-void gpsdump(TinyGPS &gps)
-{
-  long lat, lon;
-  float flat, flon;
-  unsigned long age, date, time, chars;
-  int year;
-  byte month, day, hour, minute, second, hundredths;
-  unsigned short sentences, failed;
-
-  gps.get_position(&lat, &lon, &age);
-  Serial.print("Lat/Long(10^-5 deg): "); Serial.print(lat); Serial.print(", "); Serial.print(lon);
-  Serial.print(" Fix age: "); Serial.print(age); Serial.println("ms.");
-
-  feedgps(); // If we don't feed the gps during this long routine, we may drop characters and get checksum errors
-
-  gps.f_get_position(&flat, &flon, &age);
-  Serial.print("Lat/Long(float): "); printFloat(flat, 5); Serial.print(", "); printFloat(flon, 5);
-  Serial.print(" Fix age: "); Serial.print(age); Serial.println("ms.");
-
-  feedgps();
-
-  gps.get_datetime(&date, &time, &age);
-  Serial.print("Date(ddmmyy): "); Serial.print(date); Serial.print(" Time(hhmmsscc): "); Serial.print(time);
-  Serial.print(" Fix age: "); Serial.print(age); Serial.println("ms.");
-
-  feedgps();
-
-  gps.crack_datetime(&year, &month, &day, &hour, &minute, &second, &hundredths, &age);
-  Serial.print("Date: "); Serial.print(static_cast<int>(month)); Serial.print("/"); Serial.print(static_cast<int>(day)); Serial.print("/"); Serial.print(year);
-  Serial.print("  Time: "); Serial.print(static_cast<int>(hour)); Serial.print(":"); Serial.print(static_cast<int>(minute)); Serial.print(":"); Serial.print(static_cast<int>(second)); Serial.print("."); Serial.print(static_cast<int>(hundredths));
-  Serial.print("  Fix age: ");  Serial.print(age); Serial.println("ms.");
-
-  feedgps();
-
-  Serial.print("Alt(cm): "); Serial.print(gps.altitude()); Serial.print(" Course(10^-2 deg): "); Serial.print(gps.course()); Serial.print(" Speed(10^-2 knots): "); Serial.println(gps.speed());
-  Serial.print("Alt(float): "); printFloat(gps.f_altitude()); Serial.print(" Course(float): "); printFloat(gps.f_course()); Serial.println();
-  Serial.print("Speed(knots): "); printFloat(gps.f_speed_knots()); Serial.print(" (mph): ");  printFloat(gps.f_speed_mph());
-  Serial.print(" (mps): "); printFloat(gps.f_speed_mps()); Serial.print(" (kmph): "); printFloat(gps.f_speed_kmph()); Serial.println();
-
-  feedgps();
-
-  gps.stats(&chars, &sentences, &failed);
-  Serial.print("Stats: characters: "); Serial.print(chars); Serial.print(" sentences: "); Serial.print(sentences); Serial.print(" failed checksum: "); Serial.println(failed);
-}
-
-bool feedgps()
-{
-  uint8_t rcode;
-  uint8_t  buf[64];    //serial buffer equals Max.packet size of bulk-IN endpoint
-  uint16_t rcvd = 64;
-    {
-        /* reading the GPS */
-        rcode = Pl.RcvData(&rcvd, buf);
-         if (rcode && rcode != hrNAK)
-            ErrorMessage<uint8_t>(PSTR("Ret"), rcode);
-            rcode = false;
-            if( rcvd ) { //more than zero bytes received
-              for( uint16_t i=0; i < rcvd; i++ ) {
-                if( gps.encode((char)buf[i])) { //feed a character to gps object
-                  rcode = true;
-                }//if( gps.encode(buf[i]...
-              }//for( uint16_t i=0; i < rcvd; i++...
-            }//if( rcvd...
-    }
-  return( rcode );
-}
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_xbee_terminal/pl2303_xbee_terminal.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_xbee_terminal/pl2303_xbee_terminal.ino
deleted file mode 100644
index 67b7dab603..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/pl2303/pl2303_xbee_terminal/pl2303_xbee_terminal.ino
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Arduino terminal for PL2303 USB to serial converter and XBee radio. */
-/* Inserts linefeed after carriage return in data sent to and received from Xbee */
-/* USB support */
-#include <usbhub.h>
-/* CDC support */
-#include <cdcacm.h>
-#include <cdcprolific.h>
-
-// Satisfy the IDE, which needs to see the include statment in the ino too.
-#ifdef dobogusinclude
-#include <spi4teensy3.h>
-#include <SPI.h>
-#endif
-
-class PLAsyncOper : public CDCAsyncOper
-{
-public:
-    uint8_t OnInit(ACM *pacm);
-};
-
-uint8_t PLAsyncOper::OnInit(ACM *pacm)
-{
-    uint8_t rcode;
-
-    // Set DTR = 1
-    rcode = pacm->SetControlLineState(1);
-
-    if (rcode)
-    {
-        ErrorMessage<uint8_t>(PSTR("SetControlLineState"), rcode);
-        return rcode;
-    }
-
-    LINE_CODING	lc;
-    lc.dwDTERate	= 115200;
-    lc.bCharFormat	= 0;
-    lc.bParityType	= 0;
-    lc.bDataBits	= 8;
-
-    rcode = pacm->SetLineCoding(&lc);
-
-    if (rcode)
-        ErrorMessage<uint8_t>(PSTR("SetLineCoding"), rcode);
-
-    return rcode;
-}
-USB     Usb;
-//USBHub     Hub(&Usb);
-PLAsyncOper  AsyncOper;
-PL2303       Pl(&Usb, &AsyncOper);
-
-void setup()
-{
-  Serial.begin( 115200 );
-#if !defined(__MIPSEL__)
-  while (!Serial); // Wait for serial port to connect - used on Leonardo, Teensy and other boards with built-in USB CDC serial connection
-#endif
-  Serial.println("Start");
-
-  if (Usb.Init() == -1)
-      Serial.println("OSCOKIRQ failed to assert");
-
-  delay( 200 );
-}
-
-void loop()
-{
-    Usb.Task();
-
-    if( Usb.getUsbTaskState() == USB_STATE_RUNNING )
-    {
-       uint8_t rcode;
-
-       /* reading the keyboard */
-       if(Serial.available()) {
-         uint8_t data= Serial.read();
-
-         if ( data == '\r' ) {
-           Serial.print("\r\n");  //insert linefeed
-         }
-         else {
-           Serial.print( data );  //echo back to the screen
-         }
-
-         /* sending to the phone */
-         rcode = Pl.SndData(1, &data);
-         if (rcode)
-            ErrorMessage<uint8_t>(PSTR("SndData"), rcode);
-       }//if(Serial.available()...
-
-       delay(50);
-
-        /* reading the converter */
-        /* buffer size must be greater or equal to max.packet size */
-        /* it it set to 64 (largest possible max.packet size) here, can be tuned down
-        for particular endpoint */
-        uint8_t  buf[64];
-        uint16_t rcvd = 64;
-        rcode = Pl.RcvData(&rcvd, buf);
-         if (rcode && rcode != hrNAK)
-            ErrorMessage<uint8_t>(PSTR("Ret"), rcode);
-
-            if( rcvd ) { //more than zero bytes received
-              for(uint16_t i=0; i < rcvd; i++ ) {
-                if( buf[i] =='\r' ) {
-                  Serial.print("\r\n");  //insert linefeed
-                }
-                else {
-                  Serial.print((char)buf[i]); //printing on the screen
-                }
-              }
-            }
-        delay(10);
-    }//if( Usb.getUsbTaskState() == USB_STATE_RUNNING..
-}
-
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/testusbhostFAT/Makefile b/lib/usbhost/USB_Host_Shield_2.0/examples/testusbhostFAT/Makefile
deleted file mode 100644
index 8a12ddc047..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/testusbhostFAT/Makefile
+++ /dev/null
@@ -1,64 +0,0 @@
-#
-# These are set for a mega 1280 + quadram plus my serial patch.
-# If you lack quadram, or want to disable LFN, just change _FS_TINY=1 _USE_LFN=0
-#
-# If your board is a mega 2560 comment out the following two lines
-BOARD = mega
-
-BOARD_SUB = mega.menu.cpu.atmega1280
-PROGRAMMER = arduino
-
-# ...and then uncomment out the following two lines
-#BOARD_SUB = mega.menu.cpu.atmega2560
-#PROGRAMMER = wiring
-
-#BOARD = teensypp2
-#BOARD = teensy3
-#BOARD = teensy31
-
-# set your Arduino tty port here
-PORT = /dev/ttyUSB0
-
-EXTRA_FLAGS = -D _USE_LFN=3
-
-# change to 0 if you have quadram to take advantage of caching FAT
-EXTRA_FLAGS += -D _FS_TINY=1
-
-
-EXTRA_FLAGS += -D _MAX_SS=512
-
-
-# Don't worry if you don't have external RAM, xmem2 detects this situation.
-# You *WILL* be wanting to get some kind of external ram on your mega in order to
-# do anything that is intense.
-EXTRA_FLAGS += -D EXT_RAM_STACK=1
-EXTRA_FLAGS += -D EXT_RAM_HEAP=1
-
-
-# These are no longer needed for the demo to work.
-# In the event you need more ram, uncomment these 3 lines.
-#EXTRA_FLAGS += -D DISABLE_SERIAL1
-#EXTRA_FLAGS += -D DISABLE_SERIAL2
-#EXTRA_FLAGS += -D DISABLE_SERIAL3
-
-#
-# Advanced debug on Serial3
-#
-
-# uncomment the next two to enable debug on Serial3
-EXTRA_FLAGS += -D USB_HOST_SERIAL=Serial3
-#EXTRA_FLAGS += -D DEBUG_USB_HOST
-
-# The following are the libraries used.
-LIB_DIRS += ../../
-LIB_DIRS += ../testusbhostFAT/xmem2
-LIB_DIRS += ../testusbhostFAT/generic_storage
-LIB_DIRS += ../testusbhostFAT/RTClib
-LIB_DIRS += $(ARD_HOME)/libraries/Wire
-LIB_DIRS += $(ARD_HOME)/libraries/Wire/utility
-LIB_DIRS += $(ARD_HOME)/hardware/arduino/$(BUILD_ARCH)/libraries/Wire
-LIB_DIRS += $(ARD_HOME)/hardware/arduino/$(BUILD_ARCH)/libraries/Wire/utility
-LIB_DIRS += $(ARD_HOME)/hardware/arduino/$(BUILD_ARCH)/libraries/SPI
-
-# And finally, the part that brings everything together for you.
-include Arduino_Makefile_master/_Makefile.master
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/testusbhostFAT/README.md b/lib/usbhost/USB_Host_Shield_2.0/examples/testusbhostFAT/README.md
deleted file mode 100644
index 0f2a734a65..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/testusbhostFAT/README.md
+++ /dev/null
@@ -1,29 +0,0 @@
-This small sketch tests the USB host shield mass storage library.
-
-__Note:__ This will not run a Arduino Uno due to the limited ram available in the ATmega328p.
-
-The Arduino Mega (ATmega1280) and the Arduino Mega 2560 (ATmega2560) are confirmed to work with this test code.
-
-To compile this example you will need the following libraries as well:
-
-* [xmem2](https://github.com/xxxajk/xmem2)
-* [generic_storage FATfs](https://github.com/xxxajk/generic_storage)
-* [RTClib](https://github.com/xxxajk/RTClib)
-
-The following shield is recommended for larger projects: <https://www.rugged-circuits.com/new-products/quadram>.
-
-You may use the bundled [Makefile](Makefile) to compile the code instead of the Arduino IDE if you have problems or want a smaller binary. The master makefile is bundled as a submodule, but can also be downloaded manually at the following link: <https://github.com/xxxajk/Arduino_Makefile_master>.
-
-To download the USB Host library and all the needed libraries for this test.
-
-Run the following command in a terminal application:
-
-```
-git clone --recursive https://github.com/felis/USB_Host_Shield_2.0
-```
-
-If you want to update all the submodules run:
-
-```
-git submodule foreach --recursive git pull origin master
-```
diff --git a/lib/usbhost/USB_Host_Shield_2.0/examples/testusbhostFAT/testusbhostFAT.ino b/lib/usbhost/USB_Host_Shield_2.0/examples/testusbhostFAT/testusbhostFAT.ino
deleted file mode 100644
index e8b9cd3592..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/examples/testusbhostFAT/testusbhostFAT.ino
+++ /dev/null
@@ -1,736 +0,0 @@
-/*
- * Mega + USB storage + optional DS1307 + optional expansion RAM + funky status LED,
- * Includes interactive debug level setting, and supports hot-plug.
- *
- * IMPORTANT! PLEASE USE Arduino 1.0.5 or better!
- * Older versions HAVE MAJOR BUGS AND WILL NOT WORK AT ALL!
- * Use of gcc-avr and lib-c that is newer than the Arduino version is even better.
- * If you experience random crashes, use make.
- * The options that the IDE use can generate bad code and cause the AVR to crash.
- *
- * This sketch requires the following libraries:
- * https://github.com/felis/USB_Host_Shield_2.0 Install as 'USB_Host_Shield_2_0'
- * https://github.com/xxxajk/xmem2 Install as 'xmem', provides memory services.
- * https://github.com/xxxajk/generic_storage provides access to FAT file system.
- * https://github.com/xxxajk/RTClib provides access to DS1307, or fake clock.
- *
- * Optional, to use the Makefile (Recommended! See above!):
- * https://github.com/xxxajk/Arduino_Makefile_master
- *
- */
-
-/////////////////////////////////////////////////////////////
-// Please Note:                                            //
-// This section is for info with the Arduino IDE ONLY.     //
-// Unfortunately due to short sightedness of the Arduino   //
-// code team, that you must set the following in the       //
-// respective libraries.                                   //
-// Changing them here will have _NO_ effect!               //
-/////////////////////////////////////////////////////////////
-
-// Uncomment to enable debugging
-//#define DEBUG_USB_HOST
-// This is where stderr/USB debugging goes to
-//#define USB_HOST_SERIAL Serial3
-
-// If you have external memory, setting this to 0 enables FAT table caches.
-// The 0 setting is recommended only if you have external memory.
-//#define _FS_TINY 1
-
-//#define _USE_LFN 3
-//#define _MAX_SS 512
-
-
-/////////////////////////////////////////////////////////////
-// End of Arduino IDE specific information                 //
-/////////////////////////////////////////////////////////////
-
-// You can set this to 0 if you are not using a USB hub.
-// It will save a little bit of flash and RAM.
-// Set to 1 if you want to use a hub.
-#define WANT_HUB_TEST 1
-
-// this is for XMEM2
-#define EXT_RAM_STACK 1
-#define EXT_RAM_HEAP 1
-#define LOAD_XMEM
-
-#if defined(CORE_TEENSY) && !defined(_AVR_)
-#include <xmem.h>
-#include <spi4teensy3.h>
-#endif
-
-#if defined(__AVR__)
-#include <xmem.h>
-#include <SPI.h>
-#elif defined(ARDUINO_ARCH_SAM)
-#include <SPI.h>
-#endif
-
-#if WANT_HUB_TEST
-#include <usbhub.h>
-#endif
-#include <Wire.h>
-#define LOAD_RTCLIB
-#include <RTClib.h>
-#include <masstorage.h>
-#include <Storage.h>
-#include <PCpartition/PCPartition.h>
-#include <avr/interrupt.h>
-#include <FAT/FAT.h>
-#include <stdio.h>
-#if defined(__AVR__)
-static FILE tty_stdio;
-static FILE tty_stderr;
-volatile uint32_t LEDnext_time; // fade timeout
-volatile uint32_t HEAPnext_time; // when to print out next heap report
-volatile int brightness = 0; // how bright the LED is
-volatile int fadeAmount = 80; // how many points to fade the LED by
-#endif
-
-USB Usb;
-
-volatile uint8_t current_state = 1;
-volatile uint8_t last_state = 0;
-volatile bool fatready = false;
-volatile bool partsready = false;
-volatile bool notified = false;
-volatile bool runtest = false;
-volatile bool usbon = false;
-volatile uint32_t usbon_time;
-volatile bool change = false;
-volatile bool reportlvl = false;
-int cpart = 0;
-PCPartition *PT;
-
-#if WANT_HUB_TEST
-#define MAX_HUBS 1
-USBHub *Hubs[MAX_HUBS];
-#endif
-
-static PFAT *Fats[_VOLUMES];
-static part_t parts[_VOLUMES];
-static storage_t sto[_VOLUMES];
-
-/*make sure this is a power of two. */
-#define mbxs 128
-static uint8_t My_Buff_x[mbxs]; /* File read buffer */
-
-#if defined(__AVR__)
-
-#define prescale1       ((1 << WGM12) | (1 << CS10))
-#define prescale8       ((1 << WGM12) | (1 << CS11))
-#define prescale64      ((1 << WGM12) | (1 << CS10) | (1 << CS11))
-#define prescale256     ((1 << WGM12) | (1 << CS12))
-#define prescale1024    ((1 << WGM12) | (1 << CS12) | (1 << CS10))
-
-extern "C" {
-         extern unsigned int freeHeap();
-}
-static int tty_stderr_putc(char c, FILE *t) {
-        USB_HOST_SERIAL.write(c);
-        return 0;
-}
-
-static int __attribute__((unused)) tty_stderr_flush(FILE *t) {
-        USB_HOST_SERIAL.flush();
-        return 0;
-}
-
-static int tty_std_putc(char c, FILE *t) {
-        Serial.write(c);
-        return 0;
-}
-
-static int tty_std_getc(FILE *t) {
-        while(!Serial.available());
-        return Serial.read();
-}
-
-static int __attribute__((unused)) tty_std_flush(FILE *t) {
-        Serial.flush();
-        return 0;
-}
-
-#else
-// Supposedly the DUE has stdio already pointing to serial...
-#if !defined(ARDUINO_ARCH_SAM)
-// But newlib needs this...
-extern "C" {
-        int _write(int fd, const char *ptr, int len) {
-                int j;
-                for(j = 0; j < len; j++) {
-                        if(fd == 1)
-                                Serial.write(*ptr++);
-                        else if(fd == 2)
-                                USB_HOST_SERIAL.write(*ptr++);
-                }
-                return len;
-        }
-
-        int _read(int fd, char *ptr, int len) {
-                if(len > 0 && fd == 0) {
-                        while(!Serial.available());
-                        *ptr = Serial.read();
-                        return 1;
-                }
-                return 0;
-        }
-
-#include <sys/stat.h>
-
-        int _fstat(int fd, struct stat *st) {
-                memset(st, 0, sizeof (*st));
-                st->st_mode = S_IFCHR;
-                st->st_blksize = 1024;
-                return 0;
-        }
-
-        int _isatty(int fd) {
-                return (fd < 3) ? 1 : 0;
-        }
-}
-#endif // !defined(ARDUINO_ARCH_SAM)
-#endif
-
-void setup() {
-        bool serr = false;
-        for(int i = 0; i < _VOLUMES; i++) {
-                Fats[i] = NULL;
-                sto[i].private_data = new pvt_t;
-                ((pvt_t *)sto[i].private_data)->B = 255; // impossible
-        }
-        // Set this to higher values to enable more debug information
-        // minimum 0x00, maximum 0xff
-        UsbDEBUGlvl = 0x81;
-
-#if !defined(CORE_TEENSY) && defined(__AVR__)
-        // make LED pin as an output:
-        pinMode(LED_BUILTIN, OUTPUT);
-        pinMode(2, OUTPUT);
-        // Ensure TX is off
-        _SFR_BYTE(UCSR0B) &= ~_BV(TXEN0);
-        // Initialize 'debug' serial port
-        USB_HOST_SERIAL.begin(115200);
-        // Do not start primary Serial port if already started.
-        if(bit_is_clear(UCSR0B, TXEN0)) {
-                Serial.begin(115200);
-                serr = true;
-        }
-
-
-        // Blink LED
-        delay(500);
-        analogWrite(LED_BUILTIN, 255);
-        delay(500);
-        analogWrite(LED_BUILTIN, 0);
-        delay(500);
-#else
-        while(!Serial);
-        Serial.begin(115200); // On the Teensy 3.x we get a delay at least!
-#endif
-#if defined(__AVR__)
-        // Set up stdio/stderr
-        tty_stdio.put = tty_std_putc;
-        tty_stdio.get = tty_std_getc;
-        tty_stdio.flags = _FDEV_SETUP_RW;
-        tty_stdio.udata = 0;
-
-        tty_stderr.put = tty_stderr_putc;
-        tty_stderr.get = NULL;
-        tty_stderr.flags = _FDEV_SETUP_WRITE;
-        tty_stderr.udata = 0;
-
-        stdout = &tty_stdio;
-        stdin = &tty_stdio;
-        stderr = &tty_stderr;
-#endif
-        printf_P(PSTR("\r\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nStart\r\n"));
-        printf_P(PSTR("Current UsbDEBUGlvl %02x\r\n"), UsbDEBUGlvl);
-        printf_P(PSTR("'+' and '-' increase/decrease by 0x01\r\n"));
-        printf_P(PSTR("'.' and ',' increase/decrease by 0x10\r\n"));
-        printf_P(PSTR("'t' will run a 10MB write/read test and print out the time it took.\r\n"));
-        printf_P(PSTR("'e' will toggle vbus off for a few moments.\r\n\r\n"));
-        printf_P(PSTR("Long filename support: "
-#if _USE_LFN
-                "Enabled"
-#else
-                "Disabled"
-#endif
-                "\r\n"));
-        if(serr) {
-                fprintf_P(stderr, PSTR("\r\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nStart\r\n"));
-                fprintf_P(stderr, PSTR("Current UsbDEBUGlvl %02x\r\n"), UsbDEBUGlvl);
-                fprintf_P(stderr, PSTR("Long filename support: "
-#if _USE_LFN
-                        "Enabled"
-#else
-                        "Disabled"
-#endif
-                        "\r\n"));
-        }
-
-#if !defined(CORE_TEENSY) && defined(__AVR__)
-        analogWrite(LED_BUILTIN, 255);
-        delay(500);
-        analogWrite(LED_BUILTIN, 0);
-        delay(500);
-        analogWrite(LED_BUILTIN, 255);
-        delay(500);
-        analogWrite(LED_BUILTIN, 0);
-        delay(500);
-        analogWrite(LED_BUILTIN, 255);
-        delay(500);
-        analogWrite(LED_BUILTIN, 0);
-        delay(500);
-
-        LEDnext_time = millis() + 1;
-#if EXT_RAM
-        printf_P(PSTR("Total EXT RAM banks %i\r\n"), xmem::getTotalBanks());
-#endif
-        printf_P(PSTR("Available heap: %u Bytes\r\n"), freeHeap());
-        printf_P(PSTR("SP %x\r\n"), (uint8_t *)(SP));
-#endif
-
-        // Even though I'm not going to actually be deleting,
-        // I want to be able to have slightly more control.
-        // Besides, it is easier to initialize stuff...
-#if WANT_HUB_TEST
-        for(int i = 0; i < MAX_HUBS; i++) {
-                Hubs[i] = new USBHub(&Usb);
-#if defined(__AVR__)
-                printf_P(PSTR("Available heap: %u Bytes\r\n"), freeHeap());
-#endif
-        }
-#endif
-        // Initialize generic storage. This must be done before USB starts.
-        Init_Generic_Storage();
-
-        while(Usb.Init(1000) == -1) {
-                printf_P(PSTR("No USB HOST Shield?\r\n"));
-                Notify(PSTR("OSC did not start."), 0x40);
-        }
-
-#if !defined(CORE_TEENSY) && defined(__AVR__)
-        cli();
-        TCCR3A = 0;
-        TCCR3B = 0;
-        // (0.01/(1/((16 *(10^6)) / 8))) - 1 = 19999
-        OCR3A = 19999;
-        TCCR3B |= prescale8;
-        TIMSK3 |= (1 << OCIE1A);
-        sei();
-
-        HEAPnext_time = millis() + 10000;
-#endif
-#if defined(__AVR__)
-        HEAPnext_time = millis() + 10000;
-#endif
-}
-
-void serialEvent() {
-        // Adjust UsbDEBUGlvl level on-the-fly.
-        // + to increase, - to decrease, * to display current level.
-        // . to increase by 16, , to decrease by 16
-        // e to flick VBUS
-        // * to report debug level
-        if(Serial.available()) {
-                int inByte = Serial.read();
-                switch(inByte) {
-                        case '+':
-                                if(UsbDEBUGlvl < 0xff) UsbDEBUGlvl++;
-                                reportlvl = true;
-                                break;
-                        case '-':
-                                if(UsbDEBUGlvl > 0x00) UsbDEBUGlvl--;
-                                reportlvl = true;
-                                break;
-                        case '.':
-                                if(UsbDEBUGlvl < 0xf0) UsbDEBUGlvl += 16;
-                                reportlvl = true;
-                                break;
-                        case ',':
-                                if(UsbDEBUGlvl > 0x0f) UsbDEBUGlvl -= 16;
-                                reportlvl = true;
-                                break;
-                        case '*':
-                                reportlvl = true;
-                                break;
-                        case 't':
-                                runtest = true;
-                                break;
-                        case 'e':
-                                change = true;
-                                usbon = false;
-                                break;
-                }
-        }
-}
-
-#if !defined(CORE_TEENSY) && defined(__AVR__)
-// ALL teensy versions LACK PWM ON LED
-
-ISR(TIMER3_COMPA_vect) {
-        if((long)(millis() - LEDnext_time) >= 0L) {
-                LEDnext_time = millis() + 30;
-
-                // set the brightness of LED
-                analogWrite(LED_BUILTIN, brightness);
-
-                // change the brightness for next time through the loop:
-                brightness = brightness + fadeAmount;
-
-                // reverse the direction of the fading at the ends of the fade:
-                if(brightness <= 0) {
-                        brightness = 0;
-                        fadeAmount = -fadeAmount;
-                }
-                if(brightness >= 255) {
-                        brightness = 255;
-                        fadeAmount = -fadeAmount;
-                }
-        }
-}
-#endif
-
-bool isfat(uint8_t t) {
-        return (t == 0x01 || t == 0x04 || t == 0x06 || t == 0x0b || t == 0x0c || t == 0x0e || t == 0x1);
-}
-
-void die(FRESULT rc) {
-        printf_P(PSTR("Failed with rc=%u.\r\n"), rc);
-        //for (;;);
-}
-
-void loop() {
-        FIL My_File_Object_x; /* File object */
-
-#if defined(__AVR__)
-        // Print a heap status report about every 10 seconds.
-        if((long)(millis() - HEAPnext_time) >= 0L) {
-                if(UsbDEBUGlvl > 0x50) {
-                        printf_P(PSTR("Available heap: %u Bytes\r\n"), freeHeap());
-                }
-                HEAPnext_time = millis() + 10000;
-        }
-        TCCR3B = 0;
-#endif
-#if defined(CORE_TEENSY)
-        // Teensy suffers here, oh well...
-        serialEvent();
-#endif
-        // Horrid! This sort of thing really belongs in an ISR, not here!
-        // We also will be needing to test each hub port, we don't do this yet!
-        if(!change && !usbon && (long)(millis() - usbon_time) >= 0L) {
-                change = true;
-                usbon = true;
-        }
-
-        if(change) {
-                change = false;
-                if(usbon) {
-                        Usb.vbusPower(vbus_on);
-                        printf_P(PSTR("VBUS on\r\n"));
-                } else {
-                        Usb.vbusPower(vbus_off);
-                        usbon_time = millis() + 2000;
-                }
-        }
-        Usb.Task();
-        current_state = Usb.getUsbTaskState();
-        if(current_state != last_state) {
-                if(UsbDEBUGlvl > 0x50)
-                        printf_P(PSTR("USB state = %x\r\n"), current_state);
-#if !defined(CORE_TEENSY) && defined(__AVR__)
-                if(current_state == USB_STATE_RUNNING) {
-                        fadeAmount = 30;
-                }
-#endif
-                if(current_state == USB_DETACHED_SUBSTATE_WAIT_FOR_DEVICE) {
-#if !defined(CORE_TEENSY) && defined(__AVR__)
-                        fadeAmount = 80;
-#endif
-                        partsready = false;
-                        for(int i = 0; i < cpart; i++) {
-                                if(Fats[i] != NULL)
-                                        delete Fats[i];
-                                Fats[i] = NULL;
-                        }
-                        fatready = false;
-                        notified = false;
-                        cpart = 0;
-                }
-                last_state = current_state;
-        }
-
-        // only do any of this if usb is on
-        if(usbon) {
-                if(partsready && !fatready) {
-                        if(cpart > 0) fatready = true;
-                }
-                // This is horrible, and needs to be moved elsewhere!
-                for(int B = 0; B < MAX_USB_MS_DRIVERS; B++) {
-                        if((!partsready) && (UHS_USB_BulkOnly[B]->GetAddress())) {
-
-                                // Build a list.
-                                int ML = UHS_USB_BulkOnly[B]->GetbMaxLUN();
-                                //printf("MAXLUN = %i\r\n", ML);
-                                ML++;
-                                for(int i = 0; i < ML; i++) {
-                                        if(UHS_USB_BulkOnly[B]->LUNIsGood(i)) {
-                                                partsready = true;
-                                                ((pvt_t *)(sto[i].private_data))->lun = i;
-                                                ((pvt_t *)(sto[i].private_data))->B = B;
-                                                sto[i].Reads = *UHS_USB_BulkOnly_Read;
-                                                sto[i].Writes = *UHS_USB_BulkOnly_Write;
-                                                sto[i].Status = *UHS_USB_BulkOnly_Status;
-                                                sto[i].Initialize = *UHS_USB_BulkOnly_Initialize;
-                                                sto[i].Commit = *UHS_USB_BulkOnly_Commit;
-                                                sto[i].TotalSectors = UHS_USB_BulkOnly[B]->GetCapacity(i);
-                                                sto[i].SectorSize = UHS_USB_BulkOnly[B]->GetSectorSize(i);
-                                                printf_P(PSTR("LUN:\t\t%u\r\n"), i);
-                                                printf_P(PSTR("Total Sectors:\t%08lx\t%lu\r\n"), sto[i].TotalSectors, sto[i].TotalSectors);
-                                                printf_P(PSTR("Sector Size:\t%04x\t\t%u\r\n"), sto[i].SectorSize, sto[i].SectorSize);
-                                                // get the partition data...
-                                                PT = new PCPartition;
-
-                                                if(!PT->Init(&sto[i])) {
-                                                        part_t *apart;
-                                                        for(int j = 0; j < 4; j++) {
-                                                                apart = PT->GetPart(j);
-                                                                if(apart != NULL && apart->type != 0x00) {
-                                                                        memcpy(&(parts[cpart]), apart, sizeof (part_t));
-                                                                        printf_P(PSTR("Partition %u type %#02x\r\n"), j, parts[cpart].type);
-                                                                        // for now
-                                                                        if(isfat(parts[cpart].type)) {
-                                                                                Fats[cpart] = new PFAT(&sto[i], cpart, parts[cpart].firstSector);
-                                                                                //int r = Fats[cpart]->Good();
-                                                                                if(Fats[cpart]->MountStatus()) {
-                                                                                        delete Fats[cpart];
-                                                                                        Fats[cpart] = NULL;
-                                                                                } else cpart++;
-                                                                        }
-                                                                }
-                                                        }
-                                                } else {
-                                                        // try superblock
-                                                        Fats[cpart] = new PFAT(&sto[i], cpart, 0);
-                                                        //int r = Fats[cpart]->Good();
-                                                        if(Fats[cpart]->MountStatus()) {
-                                                                //printf_P(PSTR("Superblock error %x\r\n"), r);
-                                                                delete Fats[cpart];
-                                                                Fats[cpart] = NULL;
-                                                        } else cpart++;
-
-                                                }
-                                                delete PT;
-                                        } else {
-                                                sto[i].Writes = NULL;
-                                                sto[i].Reads = NULL;
-                                                sto[i].Initialize = NULL;
-                                                sto[i].TotalSectors = 0UL;
-                                                sto[i].SectorSize = 0;
-                                        }
-                                }
-
-                        }
-                }
-
-                if(fatready) {
-                        if(Fats[0] != NULL) {
-                                struct Pvt * p;
-                                p = ((struct Pvt *)(Fats[0]->storage->private_data));
-                                if(!UHS_USB_BulkOnly[p->B]->LUNIsGood(p->lun)) {
-                                        // media change
-#if !defined(CORE_TEENSY) && defined(__AVR__)
-                                        fadeAmount = 80;
-#endif
-                                        partsready = false;
-                                        for(int i = 0; i < cpart; i++) {
-                                                if(Fats[i] != NULL)
-                                                        delete Fats[i];
-                                                Fats[cpart] = NULL;
-                                        }
-                                        fatready = false;
-                                        notified = false;
-                                        cpart = 0;
-                                }
-
-                        }
-                }
-                if(fatready) {
-                        FRESULT rc; /* Result code */
-                        UINT bw, br, i;
-                        if(!notified) {
-#if !defined(CORE_TEENSY) && defined(__AVR__)
-                                fadeAmount = 5;
-#endif
-                                notified = true;
-                                FATFS *fs = NULL;
-                                for(int zz = 0; zz < _VOLUMES; zz++) {
-                                        if(Fats[zz]->volmap == 0) fs = Fats[zz]->ffs;
-                                }
-                                printf_P(PSTR("\r\nOpen an existing file (message.txt).\r\n"));
-                                rc = f_open(&My_File_Object_x, "0:/MESSAGE.TXT", FA_READ);
-                                if(rc) printf_P(PSTR("Error %i, message.txt not found.\r\n"), rc);
-                                else {
-                                        printf_P(PSTR("\r\nType the file content.\r\n"));
-                                        for(;;) {
-                                                rc = f_read(&My_File_Object_x, My_Buff_x, mbxs, &br); /* Read a chunk of file */
-                                                if(rc || !br) break; /* Error or end of file */
-                                                for(i = 0; i < br; i++) {
-                                                        /* Type the data */
-                                                        if(My_Buff_x[i] == '\n')
-                                                                Serial.write('\r');
-                                                        if(My_Buff_x[i] != '\r')
-                                                                Serial.write(My_Buff_x[i]);
-                                                        Serial.flush();
-                                                }
-                                        }
-                                        if(rc) {
-                                                f_close(&My_File_Object_x);
-                                                goto out;
-                                        }
-
-                                        printf_P(PSTR("\r\nClose the file.\r\n"));
-                                        rc = f_close(&My_File_Object_x);
-                                        if(rc) goto out;
-                                }
-                                printf_P(PSTR("\r\nCreate a new file (hello.txt).\r\n"));
-                                rc = f_open(&My_File_Object_x, "0:/Hello.TxT", FA_WRITE | FA_CREATE_ALWAYS);
-                                if(rc) {
-                                        die(rc);
-                                        goto outdir;
-                                }
-                                printf_P(PSTR("\r\nWrite a text data. (Hello world!)\r\n"));
-                                rc = f_write(&My_File_Object_x, "Hello world!\r\n", 14, &bw);
-                                if(rc) {
-                                        goto out;
-                                }
-                                printf_P(PSTR("%u bytes written.\r\n"), bw);
-
-                                printf_P(PSTR("\r\nClose the file.\r\n"));
-                                rc = f_close(&My_File_Object_x);
-                                if(rc) {
-                                        die(rc);
-                                        goto out;
-                                }
-outdir:{
-#if _USE_LFN
-                                        char lfn[_MAX_LFN + 1];
-                                        FILINFO My_File_Info_Object_x; /* File information object */
-                                        My_File_Info_Object_x.lfname = lfn;
-#endif
-                                        DIR My_Dir_Object_x; /* Directory object */
-                                        printf_P(PSTR("\r\nOpen root directory.\r\n"));
-                                        rc = f_opendir(&My_Dir_Object_x, "0:/");
-                                        if(rc) {
-                                                die(rc);
-                                                goto out;
-                                        }
-
-                                        printf_P(PSTR("\r\nDirectory listing...\r\n"));
-#if defined(__AVR__)
-                                        printf_P(PSTR("Available heap: %u Bytes\r\n"), freeHeap());
-#endif
-                                        for(;;) {
-#if _USE_LFN
-                                                My_File_Info_Object_x.lfsize = _MAX_LFN;
-#endif
-
-                                                rc = f_readdir(&My_Dir_Object_x, &My_File_Info_Object_x); /* Read a directory item */
-                                                if(rc || !My_File_Info_Object_x.fname[0]) break; /* Error or end of dir */
-
-                                                if(My_File_Info_Object_x.fattrib & AM_DIR) {
-                                                        Serial.write('d');
-                                                } else {
-                                                        Serial.write('-');
-                                                }
-                                                Serial.write('r');
-
-                                                if(My_File_Info_Object_x.fattrib & AM_RDO) {
-                                                        Serial.write('-');
-                                                } else {
-                                                        Serial.write('w');
-                                                }
-                                                if(My_File_Info_Object_x.fattrib & AM_HID) {
-                                                        Serial.write('h');
-                                                } else {
-                                                        Serial.write('-');
-                                                }
-
-                                                if(My_File_Info_Object_x.fattrib & AM_SYS) {
-                                                        Serial.write('s');
-                                                } else {
-                                                        Serial.write('-');
-                                                }
-
-                                                if(My_File_Info_Object_x.fattrib & AM_ARC) {
-                                                        Serial.write('a');
-                                                } else {
-                                                        Serial.write('-');
-                                                }
-
-#if _USE_LFN
-                                                if(*My_File_Info_Object_x.lfname)
-                                                        printf_P(PSTR(" %8lu  %s (%s)\r\n"), My_File_Info_Object_x.fsize, My_File_Info_Object_x.fname, My_File_Info_Object_x.lfname);
-                                                else
-#endif
-                                                        printf_P(PSTR(" %8lu  %s\r\n"), My_File_Info_Object_x.fsize, &(My_File_Info_Object_x.fname[0]));
-                                        }
-                                }
-out:
-                                if(rc) die(rc);
-
-                                DISK_IOCTL(fs->drv, CTRL_COMMIT, 0);
-                                printf_P(PSTR("\r\nTest completed.\r\n"));
-
-                        }
-
-                        if(runtest) {
-                                ULONG ii, wt, rt, start, end;
-                                FATFS *fs = NULL;
-                                for(int zz = 0; zz < _VOLUMES; zz++) {
-                                        if(Fats[zz]->volmap == 0) fs = Fats[zz]->ffs;
-                                }
-                                runtest = false;
-                                f_unlink("0:/10MB.bin");
-                                printf_P(PSTR("\r\nCreate a new 10MB test file (10MB.bin).\r\n"));
-                                rc = f_open(&My_File_Object_x, "0:/10MB.bin", FA_WRITE | FA_CREATE_ALWAYS);
-                                if(rc) goto failed;
-                                for(bw = 0; bw < mbxs; bw++) My_Buff_x[bw] = bw & 0xff;
-                                fflush(stdout);
-                                start = millis();
-                                while(start == millis());
-                                for(ii = 10485760LU / mbxs; ii > 0LU; ii--) {
-                                        rc = f_write(&My_File_Object_x, My_Buff_x, mbxs, &bw);
-                                        if(rc || !bw) goto failed;
-                                }
-                                rc = f_close(&My_File_Object_x);
-                                if(rc) goto failed;
-                                end = millis();
-                                wt = (end - start) - 1;
-                                printf_P(PSTR("Time to write 10485760 bytes: %lu ms (%lu sec) \r\n"), wt, (500 + wt) / 1000UL);
-                                rc = f_open(&My_File_Object_x, "0:/10MB.bin", FA_READ);
-                                fflush(stdout);
-                                start = millis();
-                                while(start == millis());
-                                if(rc) goto failed;
-                                for(;;) {
-                                        rc = f_read(&My_File_Object_x, My_Buff_x, mbxs, &bw); /* Read a chunk of file */
-                                        if(rc || !bw) break; /* Error or end of file */
-                                }
-                                end = millis();
-                                if(rc) goto failed;
-                                rc = f_close(&My_File_Object_x);
-                                if(rc) goto failed;
-                                rt = (end - start) - 1;
-                                printf_P(PSTR("Time to read 10485760 bytes: %lu ms (%lu sec)\r\nDelete test file\r\n"), rt, (500 + rt) / 1000UL);
-failed:
-                                if(rc) die(rc);
-                                DISK_IOCTL(fs->drv, CTRL_COMMIT, 0);
-                                printf_P(PSTR("10MB timing test finished.\r\n"));
-                        }
-                }
-        }
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/gpl2.txt b/lib/usbhost/USB_Host_Shield_2.0/gpl2.txt
deleted file mode 100644
index 5b6e7c66c2..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/gpl2.txt
+++ /dev/null
@@ -1,340 +0,0 @@
-		    GNU GENERAL PUBLIC LICENSE
-		       Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-			    Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-License is intended to guarantee your freedom to share and change free
-software--to make sure the software is free for all its users.  This
-General Public License applies to most of the Free Software
-Foundation's software and to any other program whose authors commit to
-using it.  (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.)  You can apply it to
-your programs, too.
-
-  When we speak of free software, we are referring to freedom, not
-price.  Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
-in new free programs; and that you know you can do these things.
-
-  To protect your rights, we need to make restrictions that forbid
-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if you
-distribute copies of the software, or if you modify it.
-
-  For example, if you distribute copies of such a program, whether
-gratis or for a fee, you must give the recipients all the rights that
-you have.  You must make sure that they, too, receive or can get the
-source code.  And you must show them these terms so they know their
-rights.
-
-  We protect your rights with two steps: (1) copyright the software, and
-(2) offer you this license which gives you legal permission to copy,
-distribute and/or modify the software.
-
-  Also, for each author's protection and ours, we want to make certain
-that everyone understands that there is no warranty for this free
-software.  If the software is modified by someone else and passed on, we
-want its recipients to know that what they have is not the original, so
-that any problems introduced by others will not reflect on the original
-authors' reputations.
-
-  Finally, any free program is threatened constantly by software
-patents.  We wish to avoid the danger that redistributors of a free
-program will individually obtain patent licenses, in effect making the
-program proprietary.  To prevent this, we have made it clear that any
-patent must be licensed for everyone's free use or not licensed at all.
-
-  The precise terms and conditions for copying, distribution and
-modification follow.
-
-		    GNU GENERAL PUBLIC LICENSE
-   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
-
-  0. This License applies to any program or other work which contains
-a notice placed by the copyright holder saying it may be distributed
-under the terms of this General Public License.  The "Program", below,
-refers to any such program or work, and a "work based on the Program"
-means either the Program or any derivative work under copyright law:
-that is to say, a work containing the Program or a portion of it,
-either verbatim or with modifications and/or translated into another
-language.  (Hereinafter, translation is included without limitation in
-the term "modification".)  Each licensee is addressed as "you".
-
-Activities other than copying, distribution and modification are not
-covered by this License; they are outside its scope.  The act of
-running the Program is not restricted, and the output from the Program
-is covered only if its contents constitute a work based on the
-Program (independent of having been made by running the Program).
-Whether that is true depends on what the Program does.
-
-  1. You may copy and distribute verbatim copies of the Program's
-source code as you receive it, in any medium, provided that you
-conspicuously and appropriately publish on each copy an appropriate
-copyright notice and disclaimer of warranty; keep intact all the
-notices that refer to this License and to the absence of any warranty;
-and give any other recipients of the Program a copy of this License
-along with the Program.
-
-You may charge a fee for the physical act of transferring a copy, and
-you may at your option offer warranty protection in exchange for a fee.
-
-  2. You may modify your copy or copies of the Program or any portion
-of it, thus forming a work based on the Program, and copy and
-distribute such modifications or work under the terms of Section 1
-above, provided that you also meet all of these conditions:
-
-    a) You must cause the modified files to carry prominent notices
-    stating that you changed the files and the date of any change.
-
-    b) You must cause any work that you distribute or publish, that in
-    whole or in part contains or is derived from the Program or any
-    part thereof, to be licensed as a whole at no charge to all third
-    parties under the terms of this License.
-
-    c) If the modified program normally reads commands interactively
-    when run, you must cause it, when started running for such
-    interactive use in the most ordinary way, to print or display an
-    announcement including an appropriate copyright notice and a
-    notice that there is no warranty (or else, saying that you provide
-    a warranty) and that users may redistribute the program under
-    these conditions, and telling the user how to view a copy of this
-    License.  (Exception: if the Program itself is interactive but
-    does not normally print such an announcement, your work based on
-    the Program is not required to print an announcement.)
-
-These requirements apply to the modified work as a whole.  If
-identifiable sections of that work are not derived from the Program,
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-sections when you distribute them as separate works.  But when you
-distribute the same sections as part of a whole which is a work based
-on the Program, the distribution of the whole must be on the terms of
-this License, whose permissions for other licensees extend to the
-entire whole, and thus to each and every part regardless of who wrote it.
-
-Thus, it is not the intent of this section to claim rights or contest
-your rights to work written entirely by you; rather, the intent is to
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-
-In addition, mere aggregation of another work not based on the Program
-with the Program (or with a work based on the Program) on a volume of
-a storage or distribution medium does not bring the other work under
-the scope of this License.
-
-  3. You may copy and distribute the Program (or a work based on it,
-under Section 2) in object code or executable form under the terms of
-Sections 1 and 2 above provided that you also do one of the following:
-
-    a) Accompany it with the complete corresponding machine-readable
-    source code, which must be distributed under the terms of Sections
-    1 and 2 above on a medium customarily used for software interchange; or,
-
-    b) Accompany it with a written offer, valid for at least three
-    years, to give any third party, for a charge no more than your
-    cost of physically performing source distribution, a complete
-    machine-readable copy of the corresponding source code, to be
-    distributed under the terms of Sections 1 and 2 above on a medium
-    customarily used for software interchange; or,
-
-    c) Accompany it with the information you received as to the offer
-    to distribute corresponding source code.  (This alternative is
-    allowed only for noncommercial distribution and only if you
-    received the program in object code or executable form with such
-    an offer, in accord with Subsection b above.)
-
-The source code for a work means the preferred form of the work for
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-associated interface definition files, plus the scripts used to
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-anything that is normally distributed (in either source or binary
-form) with the major components (compiler, kernel, and so on) of the
-operating system on which the executable runs, unless that component
-itself accompanies the executable.
-
-If distribution of executable or object code is made by offering
-access to copy from a designated place, then offering equivalent
-access to copy the source code from the same place counts as
-distribution of the source code, even though third parties are not
-compelled to copy the source along with the object code.
-
-  4. You may not copy, modify, sublicense, or distribute the Program
-except as expressly provided under this License.  Any attempt
-otherwise to copy, modify, sublicense or distribute the Program is
-void, and will automatically terminate your rights under this License.
-However, parties who have received copies, or rights, from you under
-this License will not have their licenses terminated so long as such
-parties remain in full compliance.
-
-  5. You are not required to accept this License, since you have not
-signed it.  However, nothing else grants you permission to modify or
-distribute the Program or its derivative works.  These actions are
-prohibited by law if you do not accept this License.  Therefore, by
-modifying or distributing the Program (or any work based on the
-Program), you indicate your acceptance of this License to do so, and
-all its terms and conditions for copying, distributing or modifying
-the Program or works based on it.
-
-  6. Each time you redistribute the Program (or any work based on the
-Program), the recipient automatically receives a license from the
-original licensor to copy, distribute or modify the Program subject to
-these terms and conditions.  You may not impose any further
-restrictions on the recipients' exercise of the rights granted herein.
-You are not responsible for enforcing compliance by third parties to
-this License.
-
-  7. If, as a consequence of a court judgment or allegation of patent
-infringement or for any other reason (not limited to patent issues),
-conditions are imposed on you (whether by court order, agreement or
-otherwise) that contradict the conditions of this License, they do not
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-distribute so as to satisfy simultaneously your obligations under this
-License and any other pertinent obligations, then as a consequence you
-may not distribute the Program at all.  For example, if a patent
-license would not permit royalty-free redistribution of the Program by
-all those who receive copies directly or indirectly through you, then
-the only way you could satisfy both it and this License would be to
-refrain entirely from distribution of the Program.
-
-If any portion of this section is held invalid or unenforceable under
-any particular circumstance, the balance of the section is intended to
-apply and the section as a whole is intended to apply in other
-circumstances.
-
-It is not the purpose of this section to induce you to infringe any
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-integrity of the free software distribution system, which is
-implemented by public license practices.  Many people have made
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-through that system in reliance on consistent application of that
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-to distribute software through any other system and a licensee cannot
-impose that choice.
-
-This section is intended to make thoroughly clear what is believed to
-be a consequence of the rest of this License.
-
-  8. If the distribution and/or use of the Program is restricted in
-certain countries either by patents or by copyrighted interfaces, the
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-may add an explicit geographical distribution limitation excluding
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-  9. The Free Software Foundation may publish revised and/or new versions
-of the General Public License from time to time.  Such new versions will
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-address new problems or concerns.
-
-Each version is given a distinguishing version number.  If the Program
-specifies a version number of this License which applies to it and "any
-later version", you have the option of following the terms and conditions
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-Software Foundation.  If the Program does not specify a version number of
-this License, you may choose any version ever published by the Free Software
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-  10. If you wish to incorporate parts of the Program into other free
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-of preserving the free status of all derivatives of our free software and
-of promoting the sharing and reuse of software generally.
-
-			    NO WARRANTY
-
-  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
-FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
-OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
-PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
-OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
-TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
-PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
-REPAIR OR CORRECTION.
-
-  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
-REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
-INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
-OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
-TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
-YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
-PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES.
-
-		     END OF TERMS AND CONDITIONS
-
-	    How to Apply These Terms to Your New Programs
-
-  If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
-  To do so, attach the following notices to the program.  It is safest
-to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-    <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) <year>  <name of author>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-
-Also add information on how to contact you by electronic and paper mail.
-
-If the program is interactive, make it output a short notice like this
-when it starts in an interactive mode:
-
-    Gnomovision version 69, Copyright (C) year name of author
-    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-    This is free software, and you are welcome to redistribute it
-    under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License.  Of course, the commands you use may
-be called something other than `show w' and `show c'; they could even be
-mouse-clicks or menu items--whatever suits your program.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the program, if
-necessary.  Here is a sample; alter the names:
-
-  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
-  `Gnomovision' (which makes passes at compilers) written by James Hacker.
-
-  <signature of Ty Coon>, 1 April 1989
-  Ty Coon, President of Vice
-
-This General Public License does not permit incorporating your program into
-proprietary programs.  If your program is a subroutine library, you may
-consider it more useful to permit linking proprietary applications with the
-library.  If this is what you want to do, use the GNU Library General
-Public License instead of this License.
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hexdump.h b/lib/usbhost/USB_Host_Shield_2.0/hexdump.h
deleted file mode 100644
index ffa7248b7d..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hexdump.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(_usb_h_) || defined(__HEXDUMP_H__)
-#error "Never include hexdump.h directly; include Usb.h instead"
-#else
-#define __HEXDUMP_H__
-
-extern int UsbDEBUGlvl;
-
-template <class BASE_CLASS, class LEN_TYPE, class OFFSET_TYPE>
-class HexDumper : public BASE_CLASS {
-        uint8_t byteCount;
-        OFFSET_TYPE byteTotal;
-
-public:
-
-        HexDumper() : byteCount(0), byteTotal(0) {
-        };
-
-        void Initialize() {
-                byteCount = 0;
-                byteTotal = 0;
-        };
-
-        void Parse(const LEN_TYPE len, const uint8_t *pbuf, const OFFSET_TYPE &offset);
-};
-
-template <class BASE_CLASS, class LEN_TYPE, class OFFSET_TYPE>
-void HexDumper<BASE_CLASS, LEN_TYPE, OFFSET_TYPE>::Parse(const LEN_TYPE len, const uint8_t *pbuf, const OFFSET_TYPE &offset) {
-        if(UsbDEBUGlvl >= 0x80) { // Fully bypass this block of code if we do not debug.
-                for(LEN_TYPE j = 0; j < len; j++, byteCount++, byteTotal++) {
-                        if(!byteCount) {
-                                PrintHex<OFFSET_TYPE > (byteTotal, 0x80);
-                                E_Notify(PSTR(": "), 0x80);
-                        }
-                        PrintHex<uint8_t > (pbuf[j], 0x80);
-                        E_Notify(PSTR(" "), 0x80);
-
-                        if(byteCount == 15) {
-                                E_Notify(PSTR("\r\n"), 0x80);
-                                byteCount = 0xFF;
-                        }
-                }
-        }
-}
-
-#endif // __HEXDUMP_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hid.cpp b/lib/usbhost/USB_Host_Shield_2.0/hid.cpp
deleted file mode 100644
index e4c7721a3e..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hid.cpp
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#include "hid.h"
-
-//get HID report descriptor
-
-/* WRONG! Endpoint is _ALWAYS_ ZERO for HID! We want the _INTERFACE_ value here!
-uint8_t HID::GetReportDescr(uint8_t ep, USBReadParser *parser) {
-        const uint8_t constBufLen = 64;
-        uint8_t buf[constBufLen];
-
-        uint8_t rcode = pUsb->ctrlReq(bAddress, ep, bmREQ_HID_REPORT, USB_REQUEST_GET_DESCRIPTOR, 0x00,
-                HID_DESCRIPTOR_REPORT, 0x0000, 128, constBufLen, buf, (USBReadParser*)parser);
-
-        //return ((rcode != hrSTALL) ? rcode : 0);
-        return rcode;
-}
- */
-uint8_t HID::GetReportDescr(uint16_t wIndex, USBReadParser *parser) {
-        const uint8_t constBufLen = 64;
-        uint8_t buf[constBufLen];
-
-        uint8_t rcode = pUsb->ctrlReq(bAddress, 0x00, bmREQ_HID_REPORT, USB_REQUEST_GET_DESCRIPTOR, 0x00,
-                HID_DESCRIPTOR_REPORT, wIndex, 128, constBufLen, buf, (USBReadParser*)parser);
-
-        //return ((rcode != hrSTALL) ? rcode : 0);
-        return rcode;
-}
-
-//uint8_t HID::getHidDescr( uint8_t ep, uint16_t nbytes, uint8_t* dataptr )
-//{
-//    return( pUsb->ctrlReq( bAddress, ep, bmREQ_GET_DESCR, USB_REQUEST_GET_DESCRIPTOR, 0x00, HID_DESCRIPTOR_HID, 0x0000, nbytes, dataptr ));
-//}
-
-uint8_t HID::SetReport(uint8_t ep, uint8_t iface, uint8_t report_type, uint8_t report_id, uint16_t nbytes, uint8_t* dataptr) {
-        return ( pUsb->ctrlReq(bAddress, ep, bmREQ_HID_OUT, HID_REQUEST_SET_REPORT, report_id, report_type, iface, nbytes, nbytes, dataptr, NULL));
-}
-
-uint8_t HID::GetReport(uint8_t ep, uint8_t iface, uint8_t report_type, uint8_t report_id, uint16_t nbytes, uint8_t* dataptr) {
-        return ( pUsb->ctrlReq(bAddress, ep, bmREQ_HID_IN, HID_REQUEST_GET_REPORT, report_id, report_type, iface, nbytes, nbytes, dataptr, NULL));
-}
-
-uint8_t HID::GetIdle(uint8_t iface, uint8_t reportID, uint8_t* dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_HID_IN, HID_REQUEST_GET_IDLE, reportID, 0, iface, 0x0001, 0x0001, dataptr, NULL));
-}
-
-uint8_t HID::SetIdle(uint8_t iface, uint8_t reportID, uint8_t duration) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_HID_OUT, HID_REQUEST_SET_IDLE, reportID, duration, iface, 0x0000, 0x0000, NULL, NULL));
-}
-
-uint8_t HID::SetProtocol(uint8_t iface, uint8_t protocol) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_HID_OUT, HID_REQUEST_SET_PROTOCOL, protocol, 0x00, iface, 0x0000, 0x0000, NULL, NULL));
-}
-
-uint8_t HID::GetProtocol(uint8_t iface, uint8_t* dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_HID_IN, HID_REQUEST_GET_PROTOCOL, 0x00, 0x00, iface, 0x0001, 0x0001, dataptr, NULL));
-}
-
-void HID::PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr) {
-        Notify(PSTR("Endpoint descriptor:"), 0x80);
-        Notify(PSTR("\r\nLength:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bLength, 0x80);
-        Notify(PSTR("\r\nType:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bDescriptorType, 0x80);
-        Notify(PSTR("\r\nAddress:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bEndpointAddress, 0x80);
-        Notify(PSTR("\r\nAttributes:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bmAttributes, 0x80);
-        Notify(PSTR("\r\nMaxPktSize:\t"), 0x80);
-        D_PrintHex<uint16_t > (ep_ptr->wMaxPacketSize, 0x80);
-        Notify(PSTR("\r\nPoll Intrv:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bInterval, 0x80);
-}
-
-void HID::PrintHidDescriptor(const USB_HID_DESCRIPTOR *pDesc) {
-        Notify(PSTR("\r\n\r\nHID Descriptor:\r\n"), 0x80);
-        Notify(PSTR("bDescLength:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (pDesc->bLength, 0x80);
-
-        Notify(PSTR("\r\nbDescriptorType:\t"), 0x80);
-        D_PrintHex<uint8_t > (pDesc->bDescriptorType, 0x80);
-
-        Notify(PSTR("\r\nbcdHID:\t\t\t"), 0x80);
-        D_PrintHex<uint16_t > (pDesc->bcdHID, 0x80);
-
-        Notify(PSTR("\r\nbCountryCode:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (pDesc->bCountryCode, 0x80);
-
-        Notify(PSTR("\r\nbNumDescriptors:\t"), 0x80);
-        D_PrintHex<uint8_t > (pDesc->bNumDescriptors, 0x80);
-
-        Notify(PSTR("\r\nbDescrType:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (pDesc->bDescrType, 0x80);
-
-        Notify(PSTR("\r\nwDescriptorLength:\t"), 0x80);
-        D_PrintHex<uint16_t > (pDesc->wDescriptorLength, 0x80);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hid.h b/lib/usbhost/USB_Host_Shield_2.0/hid.h
deleted file mode 100644
index 72942ebc92..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hid.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(__HID_H__)
-#define __HID_H__
-
-#include "Usb.h"
-#include "hidusagestr.h"
-
-#define MAX_REPORT_PARSERS                      2
-#define HID_MAX_HID_CLASS_DESCRIPTORS           5
-
-#define DATA_SIZE_MASK                          0x03
-#define TYPE_MASK                               0x0C
-#define TAG_MASK                                0xF0
-
-#define DATA_SIZE_0                             0x00
-#define DATA_SIZE_1                             0x01
-#define DATA_SIZE_2                             0x02
-#define DATA_SIZE_4                             0x03
-
-#define TYPE_MAIN                               0x00
-#define TYPE_GLOBAL                             0x04
-#define TYPE_LOCAL                              0x08
-
-#define TAG_MAIN_INPUT                          0x80
-#define TAG_MAIN_OUTPUT                         0x90
-#define TAG_MAIN_COLLECTION                     0xA0
-#define TAG_MAIN_FEATURE                        0xB0
-#define TAG_MAIN_ENDCOLLECTION                  0xC0
-
-#define TAG_GLOBAL_USAGEPAGE                    0x00
-#define TAG_GLOBAL_LOGICALMIN                   0x10
-#define TAG_GLOBAL_LOGICALMAX                   0x20
-#define TAG_GLOBAL_PHYSMIN                      0x30
-#define TAG_GLOBAL_PHYSMAX                      0x40
-#define TAG_GLOBAL_UNITEXP                      0x50
-#define TAG_GLOBAL_UNIT                         0x60
-#define TAG_GLOBAL_REPORTSIZE                   0x70
-#define TAG_GLOBAL_REPORTID                     0x80
-#define TAG_GLOBAL_REPORTCOUNT                  0x90
-#define TAG_GLOBAL_PUSH                         0xA0
-#define TAG_GLOBAL_POP                          0xB0
-
-#define TAG_LOCAL_USAGE                         0x00
-#define TAG_LOCAL_USAGEMIN                      0x10
-#define TAG_LOCAL_USAGEMAX                      0x20
-
-/* HID requests */
-#define bmREQ_HID_OUT                           USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
-#define bmREQ_HID_IN                            USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
-#define bmREQ_HID_REPORT                        USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_STANDARD|USB_SETUP_RECIPIENT_INTERFACE
-
-/* HID constants. Not part of chapter 9 */
-/* Class-Specific Requests */
-#define HID_REQUEST_GET_REPORT                  0x01
-#define HID_REQUEST_GET_IDLE                    0x02
-#define HID_REQUEST_GET_PROTOCOL                0x03
-#define HID_REQUEST_SET_REPORT                  0x09
-#define HID_REQUEST_SET_IDLE                    0x0A
-#define HID_REQUEST_SET_PROTOCOL                0x0B
-
-/* Class Descriptor Types */
-#define HID_DESCRIPTOR_HID                      0x21
-#define HID_DESCRIPTOR_REPORT                   0x22
-#define HID_DESRIPTOR_PHY                       0x23
-
-/* Protocol Selection */
-#define HID_BOOT_PROTOCOL                       0x00
-#define HID_RPT_PROTOCOL                        0x01
-
-/* HID Interface Class Code */
-#define HID_INTF                                0x03
-
-/* HID Interface Class SubClass Codes */
-#define HID_BOOT_INTF_SUBCLASS                  0x01
-
-/* HID Interface Class Protocol Codes */
-#define HID_PROTOCOL_NONE                       0x00
-#define HID_PROTOCOL_KEYBOARD                   0x01
-#define HID_PROTOCOL_MOUSE                      0x02
-
-#define HID_ITEM_TYPE_MAIN                      0
-#define HID_ITEM_TYPE_GLOBAL                    1
-#define HID_ITEM_TYPE_LOCAL                     2
-#define HID_ITEM_TYPE_RESERVED                  3
-
-#define HID_LONG_ITEM_PREFIX                    0xfe    // Long item prefix value
-
-#define bmHID_MAIN_ITEM_TAG                     0xfc    // Main item tag mask
-
-#define bmHID_MAIN_ITEM_INPUT                   0x80    // Main item Input tag value
-#define bmHID_MAIN_ITEM_OUTPUT                  0x90    // Main item Output tag value
-#define bmHID_MAIN_ITEM_FEATURE                 0xb0    // Main item Feature tag value
-#define bmHID_MAIN_ITEM_COLLECTION              0xa0    // Main item Collection tag value
-#define bmHID_MAIN_ITEM_END_COLLECTION          0xce    // Main item End Collection tag value
-
-#define HID_MAIN_ITEM_COLLECTION_PHYSICAL       0
-#define HID_MAIN_ITEM_COLLECTION_APPLICATION    1
-#define HID_MAIN_ITEM_COLLECTION_LOGICAL        2
-#define HID_MAIN_ITEM_COLLECTION_REPORT         3
-#define HID_MAIN_ITEM_COLLECTION_NAMED_ARRAY    4
-#define HID_MAIN_ITEM_COLLECTION_USAGE_SWITCH   5
-#define HID_MAIN_ITEM_COLLECTION_USAGE_MODIFIER 6
-
-struct HidItemPrefix {
-        uint8_t bSize : 2;
-        uint8_t bType : 2;
-        uint8_t bTag : 4;
-};
-
-struct MainItemIOFeature {
-        uint8_t bmIsConstantOrData : 1;
-        uint8_t bmIsArrayOrVariable : 1;
-        uint8_t bmIsRelativeOrAbsolute : 1;
-        uint8_t bmIsWrapOrNoWrap : 1;
-        uint8_t bmIsNonLonearOrLinear : 1;
-        uint8_t bmIsNoPreferedOrPrefered : 1;
-        uint8_t bmIsNullOrNoNull : 1;
-        uint8_t bmIsVolatileOrNonVolatile : 1;
-};
-
-class HID;
-
-class HIDReportParser {
-public:
-        virtual void Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf) = 0;
-};
-
-class HID : public USBDeviceConfig, public UsbConfigXtracter {
-protected:
-        USB *pUsb; // USB class instance pointer
-        uint8_t bAddress; // address
-
-protected:
-        static const uint8_t epInterruptInIndex = 1; // InterruptIN  endpoint index
-        static const uint8_t epInterruptOutIndex = 2; // InterruptOUT endpoint index
-
-        static const uint8_t maxHidInterfaces = 3;
-        static const uint8_t maxEpPerInterface = 2;
-        static const uint8_t totalEndpoints = (maxHidInterfaces * maxEpPerInterface + 1);
-
-        void PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr);
-        void PrintHidDescriptor(const USB_HID_DESCRIPTOR *pDesc);
-
-        virtual HIDReportParser* GetReportParser(uint8_t id) {
-                return NULL;
-        };
-
-public:
-
-        HID(USB *pusb) : pUsb(pusb) {
-        };
-
-        const USB* GetUsb() {
-                return pUsb;
-        };
-
-        virtual bool SetReportParser(uint8_t id, HIDReportParser *prs) {
-                return false;
-        };
-
-        uint8_t SetProtocol(uint8_t iface, uint8_t protocol);
-        uint8_t GetProtocol(uint8_t iface, uint8_t* dataptr);
-        uint8_t GetIdle(uint8_t iface, uint8_t reportID, uint8_t* dataptr);
-        uint8_t SetIdle(uint8_t iface, uint8_t reportID, uint8_t duration);
-
-        uint8_t GetReportDescr(uint16_t wIndex, USBReadParser *parser = NULL);
-
-        uint8_t GetHidDescr(uint8_t ep, uint16_t nbytes, uint8_t* dataptr);
-        uint8_t GetReport(uint8_t ep, uint8_t iface, uint8_t report_type, uint8_t report_id, uint16_t nbytes, uint8_t* dataptr);
-        uint8_t SetReport(uint8_t ep, uint8_t iface, uint8_t report_type, uint8_t report_id, uint16_t nbytes, uint8_t* dataptr);
-};
-
-#endif // __HID_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hidboot.cpp b/lib/usbhost/USB_Host_Shield_2.0/hidboot.cpp
deleted file mode 100644
index 280b2f9788..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hidboot.cpp
+++ /dev/null
@@ -1,201 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#include "hidboot.h"
-
-void MouseReportParser::Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf) {
-        MOUSEINFO *pmi = (MOUSEINFO*)buf;
-        // Future:
-        // bool event;
-
-#if 0
-        if (prevState.mouseInfo.bmLeftButton == 0 && pmi->bmLeftButton == 1)
-                OnLeftButtonDown(pmi);
-
-        if (prevState.mouseInfo.bmLeftButton == 1 && pmi->bmLeftButton == 0)
-                OnLeftButtonUp(pmi);
-
-        if (prevState.mouseInfo.bmRightButton == 0 && pmi->bmRightButton == 1)
-                OnRightButtonDown(pmi);
-
-        if (prevState.mouseInfo.bmRightButton == 1 && pmi->bmRightButton == 0)
-                OnRightButtonUp(pmi);
-
-        if (prevState.mouseInfo.bmMiddleButton == 0 && pmi->bmMiddleButton == 1)
-                OnMiddleButtonDown(pmi);
-
-        if (prevState.mouseInfo.bmMiddleButton == 1 && pmi->bmMiddleButton == 0)
-                OnMiddleButtonUp(pmi);
-
-        if (prevState.mouseInfo.dX != pmi->dX || prevState.mouseInfo.dY != pmi->dY)
-                OnMouseMove(pmi);
-
-        if (len > sizeof (MOUSEINFO))
-                for (uint8_t i = 0; i<sizeof (MOUSEINFO); i++)
-                        prevState.bInfo[i] = buf[i];
-#else
-        //
-        // Optimization idea:
-        //
-        // 1: Don't pass the structure on every event. Buttons would not need it.
-        // 2: Only pass x/y values in the movement routine.
-        //
-        // These two changes (with the ones I have made) will save extra flash.
-        // The only "bad" thing is that it could break old code.
-        //
-        // Future thoughts:
-        //
-        // The extra space gained can be used for a generic mouse event that can be called
-        // when there are _ANY_ changes. This one you _MAY_ want to pass everything, however the
-        // sketch could already have noted these facts to support drag/drop scroll wheel stuff, etc.
-        //
-
-        // Why do we need to pass the structure for buttons?
-        // The function call not enough of a hint for what is happening?
-        if(prevState.mouseInfo.bmLeftButton != pmi->bmLeftButton ) {
-                if(pmi->bmLeftButton) {
-                        OnLeftButtonDown(pmi);
-                } else {
-                        OnLeftButtonUp(pmi);
-                }
-                // Future:
-                // event = true;
-        }
-
-        if(prevState.mouseInfo.bmRightButton != pmi->bmRightButton) {
-                if(pmi->bmRightButton) {
-                        OnRightButtonDown(pmi);
-                } else {
-                        OnRightButtonUp(pmi);
-                }
-                // Future:
-                // event = true;
-        }
-
-        if(prevState.mouseInfo.bmMiddleButton != pmi->bmMiddleButton) {
-                if(pmi->bmMiddleButton) {
-                        OnMiddleButtonDown(pmi);
-                } else {
-                        OnMiddleButtonUp(pmi);
-                }
-                // Future:
-                // event = true;
-        }
-
-        //
-        // Scroll wheel(s), are not part of the spec, but we could support it.
-        // Logitech wireless keyboard and mouse combo reports scroll wheel in byte 4
-        // We wouldn't even need to save this information.
-        //if(len > 3) {
-        //}
-        //
-
-        // Mice only report motion when they actually move!
-        // Why not just pass the x/y values to simplify things??
-        if(pmi->dX || pmi->dY) {
-                OnMouseMove(pmi);
-                // Future:
-                // event = true;
-        }
-
-        //
-        // Future:
-        // Provide a callback that operates on the gathered events from above.
-        //
-        // if(event) OnMouse();
-        //
-
-        // Only the first byte matters (buttons). We do NOT need to save position info.
-        prevState.bInfo[0] = buf[0];
-#endif
-
-};
-
-void KeyboardReportParser::Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf) {
-        // On error - return
-        if (buf[2] == 1)
-                return;
-
-        //KBDINFO       *pki = (KBDINFO*)buf;
-
-        // provide event for changed control key state
-        if (prevState.bInfo[0x00] != buf[0x00]) {
-                OnControlKeysChanged(prevState.bInfo[0x00], buf[0x00]);
-        }
-
-        for (uint8_t i = 2; i < 8; i++) {
-                bool down = false;
-                bool up = false;
-
-                for (uint8_t j = 2; j < 8; j++) {
-                        if (buf[i] == prevState.bInfo[j] && buf[i] != 1)
-                                down = true;
-                        if (buf[j] == prevState.bInfo[i] && prevState.bInfo[i] != 1)
-                                up = true;
-                }
-                if (!down) {
-                        HandleLockingKeys(hid, buf[i]);
-                        OnKeyDown(*buf, buf[i]);
-                }
-                if (!up)
-                        OnKeyUp(prevState.bInfo[0], prevState.bInfo[i]);
-        }
-        for (uint8_t i = 0; i < 8; i++)
-                prevState.bInfo[i] = buf[i];
-};
-
-const uint8_t KeyboardReportParser::numKeys[10] PROGMEM = {'!', '@', '#', '$', '%', '^', '&', '*', '(', ')'};
-const uint8_t KeyboardReportParser::symKeysUp[12] PROGMEM = {'_', '+', '{', '}', '|', '~', ':', '"', '~', '<', '>', '?'};
-const uint8_t KeyboardReportParser::symKeysLo[12] PROGMEM = {'-', '=', '[', ']', '\\', ' ', ';', '\'', '`', ',', '.', '/'};
-const uint8_t KeyboardReportParser::padKeys[5] PROGMEM = {'/', '*', '-', '+', 0x13};
-
-uint8_t KeyboardReportParser::OemToAscii(uint8_t mod, uint8_t key) {
-        uint8_t shift = (mod & 0x22);
-
-        // [a-z]
-        if (VALUE_WITHIN(key, 0x04, 0x1d)) {
-                // Upper case letters
-                if ((kbdLockingKeys.kbdLeds.bmCapsLock == 0 && shift) ||
-                        (kbdLockingKeys.kbdLeds.bmCapsLock == 1 && shift == 0))
-                        return (key - 4 + 'A');
-
-                        // Lower case letters
-                else
-                        return (key - 4 + 'a');
-        }// Numbers
-        else if (VALUE_WITHIN(key, 0x1e, 0x27)) {
-                if (shift)
-                        return ((uint8_t)pgm_read_byte(&getNumKeys()[key - 0x1e]));
-                else
-                        return ((key == UHS_HID_BOOT_KEY_ZERO) ? '0' : key - 0x1e + '1');
-        }// Keypad Numbers
-        else if(VALUE_WITHIN(key, 0x59, 0x61)) {
-                if(kbdLockingKeys.kbdLeds.bmNumLock == 1)
-                        return (key - 0x59 + '1');
-        } else if(VALUE_WITHIN(key, 0x2d, 0x38))
-                return ((shift) ? (uint8_t)pgm_read_byte(&getSymKeysUp()[key - 0x2d]) : (uint8_t)pgm_read_byte(&getSymKeysLo()[key - 0x2d]));
-        else if(VALUE_WITHIN(key, 0x54, 0x58))
-                return (uint8_t)pgm_read_byte(&getPadKeys()[key - 0x54]);
-        else {
-                switch(key) {
-                        case UHS_HID_BOOT_KEY_SPACE: return (0x20);
-                        case UHS_HID_BOOT_KEY_ENTER: return (0x13);
-                        case UHS_HID_BOOT_KEY_ZERO2: return ((kbdLockingKeys.kbdLeds.bmNumLock == 1) ? '0': 0);
-                        case UHS_HID_BOOT_KEY_PERIOD: return ((kbdLockingKeys.kbdLeds.bmNumLock == 1) ? '.': 0);
-                }
-        }
-        return ( 0);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hidboot.h b/lib/usbhost/USB_Host_Shield_2.0/hidboot.h
deleted file mode 100644
index fb63ec5e59..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hidboot.h
+++ /dev/null
@@ -1,618 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(__HIDBOOT_H__)
-#define __HIDBOOT_H__
-
-#include "hid.h"
-
-#define UHS_HID_BOOT_KEY_ZERO           0x27
-#define UHS_HID_BOOT_KEY_ENTER          0x28
-#define UHS_HID_BOOT_KEY_SPACE          0x2c
-#define UHS_HID_BOOT_KEY_CAPS_LOCK      0x39
-#define UHS_HID_BOOT_KEY_SCROLL_LOCK    0x47
-#define UHS_HID_BOOT_KEY_NUM_LOCK       0x53
-#define UHS_HID_BOOT_KEY_ZERO2          0x62
-#define UHS_HID_BOOT_KEY_PERIOD         0x63
-
-// Don't worry, GCC will optimize the result to a final value.
-#define bitsEndpoints(p) ((((p) & HID_PROTOCOL_KEYBOARD)? 2 : 0) | (((p) & HID_PROTOCOL_MOUSE)? 1 : 0))
-#define totalEndpoints(p) ((bitsEndpoints(p) == 3) ? 3 : 2)
-#define epMUL(p) ((((p) & HID_PROTOCOL_KEYBOARD)? 1 : 0) + (((p) & HID_PROTOCOL_MOUSE)? 1 : 0))
-
-// Already defined in hid.h
-// #define HID_MAX_HID_CLASS_DESCRIPTORS 5
-
-struct MOUSEINFO {
-
-        struct {
-                uint8_t bmLeftButton : 1;
-                uint8_t bmRightButton : 1;
-                uint8_t bmMiddleButton : 1;
-                uint8_t bmDummy : 5;
-        };
-        int8_t dX;
-        int8_t dY;
-};
-
-class MouseReportParser : public HIDReportParser {
-
-        union {
-                MOUSEINFO mouseInfo;
-                uint8_t bInfo[sizeof (MOUSEINFO)];
-        } prevState;
-
-public:
-        void Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf);
-
-protected:
-
-        virtual void OnMouseMove(MOUSEINFO *mi) {
-        };
-
-        virtual void OnLeftButtonUp(MOUSEINFO *mi) {
-        };
-
-        virtual void OnLeftButtonDown(MOUSEINFO *mi) {
-        };
-
-        virtual void OnRightButtonUp(MOUSEINFO *mi) {
-        };
-
-        virtual void OnRightButtonDown(MOUSEINFO *mi) {
-        };
-
-        virtual void OnMiddleButtonUp(MOUSEINFO *mi) {
-        };
-
-        virtual void OnMiddleButtonDown(MOUSEINFO *mi) {
-        };
-};
-
-struct MODIFIERKEYS {
-        uint8_t bmLeftCtrl : 1;
-        uint8_t bmLeftShift : 1;
-        uint8_t bmLeftAlt : 1;
-        uint8_t bmLeftGUI : 1;
-        uint8_t bmRightCtrl : 1;
-        uint8_t bmRightShift : 1;
-        uint8_t bmRightAlt : 1;
-        uint8_t bmRightGUI : 1;
-};
-
-struct KBDINFO {
-
-        struct {
-                uint8_t bmLeftCtrl : 1;
-                uint8_t bmLeftShift : 1;
-                uint8_t bmLeftAlt : 1;
-                uint8_t bmLeftGUI : 1;
-                uint8_t bmRightCtrl : 1;
-                uint8_t bmRightShift : 1;
-                uint8_t bmRightAlt : 1;
-                uint8_t bmRightGUI : 1;
-        };
-        uint8_t bReserved;
-        uint8_t Keys[6];
-};
-
-struct KBDLEDS {
-        uint8_t bmNumLock : 1;
-        uint8_t bmCapsLock : 1;
-        uint8_t bmScrollLock : 1;
-        uint8_t bmCompose : 1;
-        uint8_t bmKana : 1;
-        uint8_t bmReserved : 3;
-};
-
-class KeyboardReportParser : public HIDReportParser {
-        static const uint8_t numKeys[10];
-        static const uint8_t symKeysUp[12];
-        static const uint8_t symKeysLo[12];
-        static const uint8_t padKeys[5];
-
-protected:
-
-        union {
-                KBDINFO kbdInfo;
-                uint8_t bInfo[sizeof (KBDINFO)];
-        } prevState;
-
-        union {
-                KBDLEDS kbdLeds;
-                uint8_t bLeds;
-        } kbdLockingKeys;
-
-        uint8_t OemToAscii(uint8_t mod, uint8_t key);
-
-public:
-
-        KeyboardReportParser() {
-                kbdLockingKeys.bLeds = 0;
-        };
-
-        void Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf);
-
-protected:
-
-        virtual uint8_t HandleLockingKeys(HID* hid, uint8_t key) {
-                uint8_t old_keys = kbdLockingKeys.bLeds;
-
-                switch(key) {
-                        case UHS_HID_BOOT_KEY_NUM_LOCK:
-                                kbdLockingKeys.kbdLeds.bmNumLock = ~kbdLockingKeys.kbdLeds.bmNumLock;
-                                break;
-                        case UHS_HID_BOOT_KEY_CAPS_LOCK:
-                                kbdLockingKeys.kbdLeds.bmCapsLock = ~kbdLockingKeys.kbdLeds.bmCapsLock;
-                                break;
-                        case UHS_HID_BOOT_KEY_SCROLL_LOCK:
-                                kbdLockingKeys.kbdLeds.bmScrollLock = ~kbdLockingKeys.kbdLeds.bmScrollLock;
-                                break;
-                }
-
-                if(old_keys != kbdLockingKeys.bLeds && hid)
-                        return (hid->SetReport(0, 0/*hid->GetIface()*/, 2, 0, 1, &kbdLockingKeys.bLeds));
-
-                return 0;
-        };
-
-        virtual void OnControlKeysChanged(uint8_t before, uint8_t after) {
-        };
-
-        virtual void OnKeyDown(uint8_t mod, uint8_t key) {
-        };
-
-        virtual void OnKeyUp(uint8_t mod, uint8_t key) {
-        };
-
-        virtual const uint8_t *getNumKeys() {
-                return numKeys;
-        };
-
-        virtual const uint8_t *getSymKeysUp() {
-                return symKeysUp;
-        };
-
-        virtual const uint8_t *getSymKeysLo() {
-                return symKeysLo;
-        };
-
-        virtual const uint8_t *getPadKeys() {
-                return padKeys;
-        };
-};
-
-template <const uint8_t BOOT_PROTOCOL>
-class HIDBoot : public HID //public USBDeviceConfig, public UsbConfigXtracter
-{
-        EpInfo epInfo[totalEndpoints(BOOT_PROTOCOL)];
-        HIDReportParser *pRptParser[epMUL(BOOT_PROTOCOL)];
-
-        uint8_t bConfNum; // configuration number
-        uint8_t bIfaceNum; // Interface Number
-        uint8_t bNumIface; // number of interfaces in the configuration
-        uint8_t bNumEP; // total number of EP in the configuration
-        uint32_t qNextPollTime; // next poll time
-        bool bPollEnable; // poll enable flag
-        uint8_t bInterval; // largest interval
-
-        void Initialize();
-
-        virtual HIDReportParser* GetReportParser(uint8_t id) {
-                return pRptParser[id];
-        };
-
-public:
-        HIDBoot(USB *p);
-
-        virtual bool SetReportParser(uint8_t id, HIDReportParser *prs) {
-                pRptParser[id] = prs;
-                return true;
-        };
-
-        // USBDeviceConfig implementation
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t Release();
-        uint8_t Poll();
-
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        virtual bool isReady() {
-                return bPollEnable;
-        };
-
-        // UsbConfigXtracter implementation
-        // Method should be defined here if virtual.
-        virtual void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep);
-
-        virtual bool DEVCLASSOK(uint8_t klass) {
-                return (klass == USB_CLASS_HID);
-        }
-
-        virtual bool DEVSUBCLASSOK(uint8_t subklass) {
-                return (subklass == BOOT_PROTOCOL);
-        }
-};
-
-template <const uint8_t BOOT_PROTOCOL>
-HIDBoot<BOOT_PROTOCOL>::HIDBoot(USB *p) :
-HID(p),
-qNextPollTime(0),
-bPollEnable(false) {
-        Initialize();
-
-        for(int i = 0; i < epMUL(BOOT_PROTOCOL); i++) {
-                pRptParser[i] = NULL;
-        }
-        if(pUsb)
-                pUsb->RegisterDeviceClass(this);
-}
-
-template <const uint8_t BOOT_PROTOCOL>
-void HIDBoot<BOOT_PROTOCOL>::Initialize() {
-        for(int i = 0; i < totalEndpoints(BOOT_PROTOCOL); i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-        }
-        bNumEP = 1;
-        bNumIface = 0;
-        bConfNum = 0;
-}
-
-template <const uint8_t BOOT_PROTOCOL>
-uint8_t HIDBoot<BOOT_PROTOCOL>::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        const uint8_t constBufSize = sizeof (USB_DEVICE_DESCRIPTOR);
-
-        uint8_t buf[constBufSize];
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint8_t len = 0;
-        //uint16_t cd_len = 0;
-
-        uint8_t num_of_conf; // number of configurations
-        //uint8_t num_of_intf; // number of interfaces
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-
-        USBTRACE("BM Init\r\n");
-        //USBTRACE2("totalEndpoints:", (uint8_t) (totalEndpoints(BOOT_PROTOCOL)));
-        //USBTRACE2("epMUL:", epMUL(BOOT_PROTOCOL));
-
-        if(bAddress)
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-
-        bInterval = 0;
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        if(!p->epinfo) {
-                USBTRACE("epinfo\r\n");
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, 8, (uint8_t*)buf);
-
-        if(!rcode)
-                len = (buf[0] > constBufSize) ? constBufSize : buf[0];
-
-        if(rcode) {
-                // Restore p->epinfo
-                p->epinfo = oldep_ptr;
-
-                goto FailGetDevDescr;
-        }
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from the device descriptor
-        epInfo[0].maxPktSize = (uint8_t)((USB_DEVICE_DESCRIPTOR*)buf)->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                USBTRACE2("setAddr:", rcode);
-                return rcode;
-        }
-        //delay(2); //per USB 2.0 sect.9.2.6.3
-
-        USBTRACE2("Addr:", bAddress);
-
-        p->lowspeed = false;
-
-        p = addrPool.GetUsbDevicePtr(bAddress);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        if(len)
-                rcode = pUsb->getDevDescr(bAddress, 0, len, (uint8_t*)buf);
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        num_of_conf = ((USB_DEVICE_DESCRIPTOR*)buf)->bNumConfigurations;
-
-        USBTRACE2("NC:", num_of_conf);
-
-        // GCC will optimize unused stuff away.
-        if((BOOT_PROTOCOL & (HID_PROTOCOL_KEYBOARD | HID_PROTOCOL_MOUSE)) == (HID_PROTOCOL_KEYBOARD | HID_PROTOCOL_MOUSE)) {
-                USBTRACE("HID_PROTOCOL_KEYBOARD AND MOUSE\r\n");
-                ConfigDescParser<
-                        USB_CLASS_HID,
-                        HID_BOOT_INTF_SUBCLASS,
-                        HID_PROTOCOL_KEYBOARD | HID_PROTOCOL_MOUSE,
-                        CP_MASK_COMPARE_ALL > confDescrParser(this);
-                confDescrParser.SetOR(); // Use the OR variant.
-                for(uint8_t i = 0; i < num_of_conf; i++) {
-                        pUsb->getConfDescr(bAddress, 0, i, &confDescrParser);
-                        if(bNumEP == (uint8_t)(totalEndpoints(BOOT_PROTOCOL)))
-                                break;
-                }
-        } else {
-                // GCC will optimize unused stuff away.
-                if(BOOT_PROTOCOL & HID_PROTOCOL_KEYBOARD) {
-                        USBTRACE("HID_PROTOCOL_KEYBOARD\r\n");
-                        for(uint8_t i = 0; i < num_of_conf; i++) {
-                                ConfigDescParser<
-                                        USB_CLASS_HID,
-                                        HID_BOOT_INTF_SUBCLASS,
-                                        HID_PROTOCOL_KEYBOARD,
-                                        CP_MASK_COMPARE_ALL> confDescrParserA(this);
-
-                                pUsb->getConfDescr(bAddress, 0, i, &confDescrParserA);
-                                if(bNumEP == (uint8_t)(totalEndpoints(BOOT_PROTOCOL)))
-                                        break;
-                        }
-                }
-
-                // GCC will optimize unused stuff away.
-                if(BOOT_PROTOCOL & HID_PROTOCOL_MOUSE) {
-                        USBTRACE("HID_PROTOCOL_MOUSE\r\n");
-                        for(uint8_t i = 0; i < num_of_conf; i++) {
-                                ConfigDescParser<
-                                        USB_CLASS_HID,
-                                        HID_BOOT_INTF_SUBCLASS,
-                                        HID_PROTOCOL_MOUSE,
-                                        CP_MASK_COMPARE_ALL> confDescrParserB(this);
-
-                                pUsb->getConfDescr(bAddress, 0, i, &confDescrParserB);
-                                if(bNumEP == ((uint8_t)(totalEndpoints(BOOT_PROTOCOL))))
-                                        break;
-
-                        }
-                }
-        }
-        USBTRACE2("bNumEP:", bNumEP);
-
-        if(bNumEP != (uint8_t)(totalEndpoints(BOOT_PROTOCOL))) {
-                rcode = USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-                goto Fail;
-        }
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, bNumEP, epInfo);
-        //USBTRACE2("setEpInfoEntry returned ", rcode);
-        USBTRACE2("Cnf:", bConfNum);
-
-        delay(1000);
-
-        // Set Configuration Value
-        rcode = pUsb->setConf(bAddress, 0, bConfNum);
-
-        if(rcode)
-                goto FailSetConfDescr;
-
-        delay(1000);
-
-        USBTRACE2("bIfaceNum:", bIfaceNum);
-        USBTRACE2("bNumIface:", bNumIface);
-
-        // Yes, mouse wants SetProtocol and SetIdle too!
-        for(uint8_t i = 0; i < epMUL(BOOT_PROTOCOL); i++) {
-                USBTRACE2("\r\nInterface:", i);
-                rcode = SetProtocol(i, HID_BOOT_PROTOCOL);
-                if(rcode) goto FailSetProtocol;
-                USBTRACE2("PROTOCOL SET HID_BOOT rcode:", rcode);
-                rcode = SetIdle(i, 0, 0);
-                USBTRACE2("SET_IDLE rcode:", rcode);
-                // if(rcode) goto FailSetIdle; This can fail.
-                // Get the RPIPE and just throw it away.
-                SinkParser<USBReadParser, uint16_t, uint16_t> sink;
-                rcode = GetReportDescr(i, &sink);
-                USBTRACE2("RPIPE rcode:", rcode);
-        }
-
-        // Get RPIPE and throw it away.
-
-        if(BOOT_PROTOCOL & HID_PROTOCOL_KEYBOARD) {
-                // Wake keyboard interface by twinkling up to 5 LEDs that are in the spec.
-                // kana, compose, scroll, caps, num
-                rcode = 0x20; // Reuse rcode.
-                while(rcode) {
-                        rcode >>= 1;
-                        // Ignore any error returned, we don't care if LED is not supported
-                        SetReport(0, 0, 2, 0, 1, &rcode); // Eventually becomes zero (All off)
-                        delay(25);
-                }
-        }
-        USBTRACE("BM configured\r\n");
-
-        bPollEnable = true;
-        return 0;
-
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-        //FailSetDevTblEntry:
-        //#ifdef DEBUG_USB_HOST
-        //        NotifyFailSetDevTblEntry();
-        //        goto Fail;
-        //#endif
-
-        //FailGetConfDescr:
-        //#ifdef DEBUG_USB_HOST
-        //        NotifyFailGetConfDescr();
-        //        goto Fail;
-        //#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-        goto Fail;
-#endif
-
-FailSetProtocol:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("SetProto:");
-        goto Fail;
-#endif
-
-        //FailSetIdle:
-        //#ifdef DEBUG_USB_HOST
-        //        USBTRACE("SetIdle:");
-        //#endif
-
-Fail:
-#ifdef DEBUG_USB_HOST
-        NotifyFail(rcode);
-#endif
-        Release();
-
-        return rcode;
-}
-
-template <const uint8_t BOOT_PROTOCOL>
-void HIDBoot<BOOT_PROTOCOL>::EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *pep) {
-
-        // If the first configuration satisfies, the others are not considered.
-        //if(bNumEP > 1 && conf != bConfNum)
-        if(bNumEP == totalEndpoints(BOOT_PROTOCOL))
-                return;
-
-        bConfNum = conf;
-        bIfaceNum = iface;
-
-        if((pep->bmAttributes & 0x03) == 3 && (pep->bEndpointAddress & 0x80) == 0x80) {
-                if(pep->bInterval > bInterval) bInterval = pep->bInterval;
-
-                // Fill in the endpoint info structure
-                epInfo[bNumEP].epAddr = (pep->bEndpointAddress & 0x0F);
-                epInfo[bNumEP].maxPktSize = (uint8_t)pep->wMaxPacketSize;
-                epInfo[bNumEP].epAttribs = 0;
-                epInfo[bNumEP].bmNakPower = USB_NAK_NOWAIT;
-                bNumEP++;
-
-        }
-}
-
-template <const uint8_t BOOT_PROTOCOL>
-uint8_t HIDBoot<BOOT_PROTOCOL>::Release() {
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-
-        bConfNum = 0;
-        bIfaceNum = 0;
-        bNumEP = 1;
-        bAddress = 0;
-        qNextPollTime = 0;
-        bPollEnable = false;
-
-        return 0;
-}
-
-template <const uint8_t BOOT_PROTOCOL>
-uint8_t HIDBoot<BOOT_PROTOCOL>::Poll() {
-        uint8_t rcode = 0;
-
-        if(bPollEnable && ((long)(millis() - qNextPollTime) >= 0L)) {
-
-                // To-do: optimize manually, using the for loop only if needed.
-                for(int i = 0; i < epMUL(BOOT_PROTOCOL); i++) {
-                        const uint16_t const_buff_len = 16;
-                        uint8_t buf[const_buff_len];
-
-                        USBTRACE3("(hidboot.h) i=", i, 0x81);
-                        USBTRACE3("(hidboot.h) epInfo[epInterruptInIndex + i].epAddr=", epInfo[epInterruptInIndex + i].epAddr, 0x81);
-                        USBTRACE3("(hidboot.h) epInfo[epInterruptInIndex + i].maxPktSize=", epInfo[epInterruptInIndex + i].maxPktSize, 0x81);
-                        uint16_t read = (uint16_t)epInfo[epInterruptInIndex + i].maxPktSize;
-
-                        rcode = pUsb->inTransfer(bAddress, epInfo[epInterruptInIndex + i].epAddr, &read, buf);
-                        // SOME buggy dongles report extra keys (like sleep) using a 2 byte packet on the wrong endpoint.
-                        // Since keyboard and mice must report at least 3 bytes, we ignore the extra data.
-                        if(!rcode && read > 2) {
-                                if(pRptParser[i])
-                                        pRptParser[i]->Parse((HID*)this, 0, (uint8_t)read, buf);
-#ifdef DEBUG_USB_HOST
-                                // We really don't care about errors and anomalies unless we are debugging.
-                        } else {
-                                if(rcode != hrNAK) {
-                                        USBTRACE3("(hidboot.h) Poll:", rcode, 0x81);
-                                }
-                                if(!rcode && read) {
-                                        USBTRACE3("(hidboot.h) Strange read count: ", read, 0x80);
-                                        USBTRACE3("(hidboot.h) Interface:", i, 0x80);
-                                }
-                        }
-
-                        if(!rcode && read && (UsbDEBUGlvl > 0x7f)) {
-                                for(uint8_t i = 0; i < read; i++) {
-                                        PrintHex<uint8_t > (buf[i], 0x80);
-                                        USBTRACE1(" ", 0x80);
-                                }
-                                if(read)
-                                        USBTRACE1("\r\n", 0x80);
-#endif
-                        }
-
-                }
-                qNextPollTime = millis() + bInterval;
-        }
-        return rcode;
-}
-
-#endif // __HIDBOOTMOUSE_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hidescriptorparser.cpp b/lib/usbhost/USB_Host_Shield_2.0/hidescriptorparser.cpp
deleted file mode 100644
index e4491b4e97..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hidescriptorparser.cpp
+++ /dev/null
@@ -1,1588 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#include "hidescriptorparser.h"
-
-const char * const ReportDescParserBase::usagePageTitles0[] PROGMEM = {
-        pstrUsagePageGenericDesktopControls,
-        pstrUsagePageSimulationControls,
-        pstrUsagePageVRControls,
-        pstrUsagePageSportControls,
-        pstrUsagePageGameControls,
-        pstrUsagePageGenericDeviceControls,
-        pstrUsagePageKeyboardKeypad,
-        pstrUsagePageLEDs,
-        pstrUsagePageButton,
-        pstrUsagePageOrdinal,
-        pstrUsagePageTelephone,
-        pstrUsagePageConsumer,
-        pstrUsagePageDigitizer,
-        pstrUsagePagePID,
-        pstrUsagePageUnicode
-};
-
-const char * const ReportDescParserBase::usagePageTitles1[] PROGMEM = {
-        pstrUsagePageBarCodeScanner,
-        pstrUsagePageScale,
-        pstrUsagePageMSRDevices,
-        pstrUsagePagePointOfSale,
-        pstrUsagePageCameraControl,
-        pstrUsagePageArcade
-};
-const char * const ReportDescParserBase::genDesktopTitles0[] PROGMEM = {
-        pstrUsagePointer,
-        pstrUsageMouse,
-        pstrUsageJoystick,
-        pstrUsageGamePad,
-        pstrUsageKeyboard,
-        pstrUsageKeypad,
-        pstrUsageMultiAxisController,
-        pstrUsageTabletPCSystemControls
-
-};
-const char * const ReportDescParserBase::genDesktopTitles1[] PROGMEM = {
-        pstrUsageX,
-        pstrUsageY,
-        pstrUsageZ,
-        pstrUsageRx,
-        pstrUsageRy,
-        pstrUsageRz,
-        pstrUsageSlider,
-        pstrUsageDial,
-        pstrUsageWheel,
-        pstrUsageHatSwitch,
-        pstrUsageCountedBuffer,
-        pstrUsageByteCount,
-        pstrUsageMotionWakeup,
-        pstrUsageStart,
-        pstrUsageSelect,
-        pstrUsagePageReserved,
-        pstrUsageVx,
-        pstrUsageVy,
-        pstrUsageVz,
-        pstrUsageVbrx,
-        pstrUsageVbry,
-        pstrUsageVbrz,
-        pstrUsageVno,
-        pstrUsageFeatureNotification,
-        pstrUsageResolutionMultiplier
-};
-const char * const ReportDescParserBase::genDesktopTitles2[] PROGMEM = {
-        pstrUsageSystemControl,
-        pstrUsageSystemPowerDown,
-        pstrUsageSystemSleep,
-        pstrUsageSystemWakeup,
-        pstrUsageSystemContextMenu,
-        pstrUsageSystemMainMenu,
-        pstrUsageSystemAppMenu,
-        pstrUsageSystemMenuHelp,
-        pstrUsageSystemMenuExit,
-        pstrUsageSystemMenuSelect,
-        pstrUsageSystemMenuRight,
-        pstrUsageSystemMenuLeft,
-        pstrUsageSystemMenuUp,
-        pstrUsageSystemMenuDown,
-        pstrUsageSystemColdRestart,
-        pstrUsageSystemWarmRestart,
-        pstrUsageDPadUp,
-        pstrUsageDPadDown,
-        pstrUsageDPadRight,
-        pstrUsageDPadLeft
-};
-const char * const ReportDescParserBase::genDesktopTitles3[] PROGMEM = {
-        pstrUsageSystemDock,
-        pstrUsageSystemUndock,
-        pstrUsageSystemSetup,
-        pstrUsageSystemBreak,
-        pstrUsageSystemDebuggerBreak,
-        pstrUsageApplicationBreak,
-        pstrUsageApplicationDebuggerBreak,
-        pstrUsageSystemSpeakerMute,
-        pstrUsageSystemHibernate
-};
-const char * const ReportDescParserBase::genDesktopTitles4[] PROGMEM = {
-        pstrUsageSystemDisplayInvert,
-        pstrUsageSystemDisplayInternal,
-        pstrUsageSystemDisplayExternal,
-        pstrUsageSystemDisplayBoth,
-        pstrUsageSystemDisplayDual,
-        pstrUsageSystemDisplayToggleIntExt,
-        pstrUsageSystemDisplaySwapPriSec,
-        pstrUsageSystemDisplayLCDAutoscale
-};
-const char * const ReportDescParserBase::simuTitles0[] PROGMEM = {
-        pstrUsageFlightSimulationDevice,
-        pstrUsageAutomobileSimulationDevice,
-        pstrUsageTankSimulationDevice,
-        pstrUsageSpaceshipSimulationDevice,
-        pstrUsageSubmarineSimulationDevice,
-        pstrUsageSailingSimulationDevice,
-        pstrUsageMotocicleSimulationDevice,
-        pstrUsageSportsSimulationDevice,
-        pstrUsageAirplaneSimulationDevice,
-        pstrUsageHelicopterSimulationDevice,
-        pstrUsageMagicCarpetSimulationDevice,
-        pstrUsageBicycleSimulationDevice
-};
-const char * const ReportDescParserBase::simuTitles1[] PROGMEM = {
-        pstrUsageFlightControlStick,
-        pstrUsageFlightStick,
-        pstrUsageCyclicControl,
-        pstrUsageCyclicTrim,
-        pstrUsageFlightYoke,
-        pstrUsageTrackControl
-};
-const char * const ReportDescParserBase::simuTitles2[] PROGMEM = {
-        pstrUsageAileron,
-        pstrUsageAileronTrim,
-        pstrUsageAntiTorqueControl,
-        pstrUsageAutopilotEnable,
-        pstrUsageChaffRelease,
-        pstrUsageCollectiveControl,
-        pstrUsageDiveBrake,
-        pstrUsageElectronicCountermeasures,
-        pstrUsageElevator,
-        pstrUsageElevatorTrim,
-        pstrUsageRudder,
-        pstrUsageThrottle,
-        pstrUsageFlightCommunications,
-        pstrUsageFlareRelease,
-        pstrUsageLandingGear,
-        pstrUsageToeBrake,
-        pstrUsageTrigger,
-        pstrUsageWeaponsArm,
-        pstrUsageWeaponsSelect,
-        pstrUsageWingFlaps,
-        pstrUsageAccelerator,
-        pstrUsageBrake,
-        pstrUsageClutch,
-        pstrUsageShifter,
-        pstrUsageSteering,
-        pstrUsageTurretDirection,
-        pstrUsageBarrelElevation,
-        pstrUsageDivePlane,
-        pstrUsageBallast,
-        pstrUsageBicycleCrank,
-        pstrUsageHandleBars,
-        pstrUsageFrontBrake,
-        pstrUsageRearBrake
-};
-const char * const ReportDescParserBase::vrTitles0[] PROGMEM = {
-        pstrUsageBelt,
-        pstrUsageBodySuit,
-        pstrUsageFlexor,
-        pstrUsageGlove,
-        pstrUsageHeadTracker,
-        pstrUsageHeadMountedDisplay,
-        pstrUsageHandTracker,
-        pstrUsageOculometer,
-        pstrUsageVest,
-        pstrUsageAnimatronicDevice
-};
-const char * const ReportDescParserBase::vrTitles1[] PROGMEM = {
-        pstrUsageStereoEnable,
-        pstrUsageDisplayEnable
-};
-const char * const ReportDescParserBase::sportsCtrlTitles0[] PROGMEM = {
-        pstrUsageBaseballBat,
-        pstrUsageGolfClub,
-        pstrUsageRowingMachine,
-        pstrUsageTreadmill
-};
-const char * const ReportDescParserBase::sportsCtrlTitles1[] PROGMEM = {
-        pstrUsageOar,
-        pstrUsageSlope,
-        pstrUsageRate,
-        pstrUsageStickSpeed,
-        pstrUsageStickFaceAngle,
-        pstrUsageStickHeelToe,
-        pstrUsageStickFollowThough,
-        pstrUsageStickTempo,
-        pstrUsageStickType,
-        pstrUsageStickHeight
-};
-const char * const ReportDescParserBase::sportsCtrlTitles2[] PROGMEM = {
-        pstrUsagePutter,
-        pstrUsage1Iron,
-        pstrUsage2Iron,
-        pstrUsage3Iron,
-        pstrUsage4Iron,
-        pstrUsage5Iron,
-        pstrUsage6Iron,
-        pstrUsage7Iron,
-        pstrUsage8Iron,
-        pstrUsage9Iron,
-        pstrUsage10Iron,
-        pstrUsage11Iron,
-        pstrUsageSandWedge,
-        pstrUsageLoftWedge,
-        pstrUsagePowerWedge,
-        pstrUsage1Wood,
-        pstrUsage3Wood,
-        pstrUsage5Wood,
-        pstrUsage7Wood,
-        pstrUsage9Wood
-};
-const char * const ReportDescParserBase::gameTitles0[] PROGMEM = {
-        pstrUsage3DGameController,
-        pstrUsagePinballDevice,
-        pstrUsageGunDevice
-};
-const char * const ReportDescParserBase::gameTitles1[] PROGMEM = {
-        pstrUsagePointOfView,
-        pstrUsageTurnRightLeft,
-        pstrUsagePitchForwardBackward,
-        pstrUsageRollRightLeft,
-        pstrUsageMoveRightLeft,
-        pstrUsageMoveForwardBackward,
-        pstrUsageMoveUpDown,
-        pstrUsageLeanRightLeft,
-        pstrUsageLeanForwardBackward,
-        pstrUsageHeightOfPOV,
-        pstrUsageFlipper,
-        pstrUsageSecondaryFlipper,
-        pstrUsageBump,
-        pstrUsageNewGame,
-        pstrUsageShootBall,
-        pstrUsagePlayer,
-        pstrUsageGunBolt,
-        pstrUsageGunClip,
-        pstrUsageGunSelector,
-        pstrUsageGunSingleShot,
-        pstrUsageGunBurst,
-        pstrUsageGunAutomatic,
-        pstrUsageGunSafety,
-        pstrUsageGamepadFireJump,
-        pstrUsageGamepadTrigger
-};
-const char * const ReportDescParserBase::genDevCtrlTitles[] PROGMEM = {
-        pstrUsageBatteryStrength,
-        pstrUsageWirelessChannel,
-        pstrUsageWirelessID,
-        pstrUsageDiscoverWirelessControl,
-        pstrUsageSecurityCodeCharEntered,
-        pstrUsageSecurityCodeCharErased,
-        pstrUsageSecurityCodeCleared
-};
-const char * const ReportDescParserBase::ledTitles[] PROGMEM = {
-        pstrUsageNumLock,
-        pstrUsageCapsLock,
-        pstrUsageScrollLock,
-        pstrUsageCompose,
-        pstrUsageKana,
-        pstrUsagePower,
-        pstrUsageShift,
-        pstrUsageDoNotDisturb,
-        pstrUsageMute,
-        pstrUsageToneEnable,
-        pstrUsageHighCutFilter,
-        pstrUsageLowCutFilter,
-        pstrUsageEqualizerEnable,
-        pstrUsageSoundFieldOn,
-        pstrUsageSurroundOn,
-        pstrUsageRepeat,
-        pstrUsageStereo,
-        pstrUsageSamplingRateDetect,
-        pstrUsageSpinning,
-        pstrUsageCAV,
-        pstrUsageCLV,
-        pstrUsageRecordingFormatDetect,
-        pstrUsageOffHook,
-        pstrUsageRing,
-        pstrUsageMessageWaiting,
-        pstrUsageDataMode,
-        pstrUsageBatteryOperation,
-        pstrUsageBatteryOK,
-        pstrUsageBatteryLow,
-        pstrUsageSpeaker,
-        pstrUsageHeadSet,
-        pstrUsageHold,
-        pstrUsageMicrophone,
-        pstrUsageCoverage,
-        pstrUsageNightMode,
-        pstrUsageSendCalls,
-        pstrUsageCallPickup,
-        pstrUsageConference,
-        pstrUsageStandBy,
-        pstrUsageCameraOn,
-        pstrUsageCameraOff,
-        pstrUsageOnLine,
-        pstrUsageOffLine,
-        pstrUsageBusy,
-        pstrUsageReady,
-        pstrUsagePaperOut,
-        pstrUsagePaperJam,
-        pstrUsageRemote,
-        pstrUsageForward,
-        pstrUsageReverse,
-        pstrUsageStop,
-        pstrUsageRewind,
-        pstrUsageFastForward,
-        pstrUsagePlay,
-        pstrUsagePause,
-        pstrUsageRecord,
-        pstrUsageError,
-        pstrUsageSelectedIndicator,
-        pstrUsageInUseIndicator,
-        pstrUsageMultiModeIndicator,
-        pstrUsageIndicatorOn,
-        pstrUsageIndicatorFlash,
-        pstrUsageIndicatorSlowBlink,
-        pstrUsageIndicatorFastBlink,
-        pstrUsageIndicatorOff,
-        pstrUsageFlashOnTime,
-        pstrUsageSlowBlinkOnTime,
-        pstrUsageSlowBlinkOffTime,
-        pstrUsageFastBlinkOnTime,
-        pstrUsageFastBlinkOffTime,
-        pstrUsageIndicatorColor,
-        pstrUsageIndicatorRed,
-        pstrUsageIndicatorGreen,
-        pstrUsageIndicatorAmber,
-        pstrUsageGenericIndicator,
-        pstrUsageSystemSuspend,
-        pstrUsageExternalPowerConnected
-};
-const char * const ReportDescParserBase::telTitles0 [] PROGMEM = {
-        pstrUsagePhone,
-        pstrUsageAnsweringMachine,
-        pstrUsageMessageControls,
-        pstrUsageHandset,
-        pstrUsageHeadset,
-        pstrUsageTelephonyKeyPad,
-        pstrUsageProgrammableButton
-};
-const char * const ReportDescParserBase::telTitles1 [] PROGMEM = {
-        pstrUsageHookSwitch,
-        pstrUsageFlash,
-        pstrUsageFeature,
-        pstrUsageHold,
-        pstrUsageRedial,
-        pstrUsageTransfer,
-        pstrUsageDrop,
-        pstrUsagePark,
-        pstrUsageForwardCalls,
-        pstrUsageAlternateFunction,
-        pstrUsageLine,
-        pstrUsageSpeakerPhone,
-        pstrUsageConference,
-        pstrUsageRingEnable,
-        pstrUsageRingSelect,
-        pstrUsagePhoneMute,
-        pstrUsageCallerID,
-        pstrUsageSend
-};
-const char * const ReportDescParserBase::telTitles2 [] PROGMEM = {
-        pstrUsageSpeedDial,
-        pstrUsageStoreNumber,
-        pstrUsageRecallNumber,
-        pstrUsagePhoneDirectory
-};
-const char * const ReportDescParserBase::telTitles3 [] PROGMEM = {
-        pstrUsageVoiceMail,
-        pstrUsageScreenCalls,
-        pstrUsageDoNotDisturb,
-        pstrUsageMessage,
-        pstrUsageAnswerOnOff
-};
-const char * const ReportDescParserBase::telTitles4 [] PROGMEM = {
-        pstrUsageInsideDialTone,
-        pstrUsageOutsideDialTone,
-        pstrUsageInsideRingTone,
-        pstrUsageOutsideRingTone,
-        pstrUsagePriorityRingTone,
-        pstrUsageInsideRingback,
-        pstrUsagePriorityRingback,
-        pstrUsageLineBusyTone,
-        pstrUsageReorderTone,
-        pstrUsageCallWaitingTone,
-        pstrUsageConfirmationTone1,
-        pstrUsageConfirmationTone2,
-        pstrUsageTonesOff,
-        pstrUsageOutsideRingback,
-        pstrUsageRinger
-};
-const char * const ReportDescParserBase::telTitles5 [] PROGMEM = {
-        pstrUsagePhoneKey0,
-        pstrUsagePhoneKey1,
-        pstrUsagePhoneKey2,
-        pstrUsagePhoneKey3,
-        pstrUsagePhoneKey4,
-        pstrUsagePhoneKey5,
-        pstrUsagePhoneKey6,
-        pstrUsagePhoneKey7,
-        pstrUsagePhoneKey8,
-        pstrUsagePhoneKey9,
-        pstrUsagePhoneKeyStar,
-        pstrUsagePhoneKeyPound,
-        pstrUsagePhoneKeyA,
-        pstrUsagePhoneKeyB,
-        pstrUsagePhoneKeyC,
-        pstrUsagePhoneKeyD
-};
-const char * const ReportDescParserBase::consTitles0[] PROGMEM = {
-        pstrUsageConsumerControl,
-        pstrUsageNumericKeyPad,
-        pstrUsageProgrammableButton,
-        pstrUsageMicrophone,
-        pstrUsageHeadphone,
-        pstrUsageGraphicEqualizer
-};
-const char * const ReportDescParserBase::consTitles1[] PROGMEM = {
-        pstrUsagePlus10,
-        pstrUsagePlus100,
-        pstrUsageAMPM
-};
-const char * const ReportDescParserBase::consTitles2[] PROGMEM = {
-        pstrUsagePower,
-        pstrUsageReset,
-        pstrUsageSleep,
-        pstrUsageSleepAfter,
-        pstrUsageSleepMode,
-        pstrUsageIllumination,
-        pstrUsageFunctionButtons
-
-};
-const char * const ReportDescParserBase::consTitles3[] PROGMEM = {
-        pstrUsageMenu,
-        pstrUsageMenuPick,
-        pstrUsageMenuUp,
-        pstrUsageMenuDown,
-        pstrUsageMenuLeft,
-        pstrUsageMenuRight,
-        pstrUsageMenuEscape,
-        pstrUsageMenuValueIncrease,
-        pstrUsageMenuValueDecrease
-};
-const char * const ReportDescParserBase::consTitles4[] PROGMEM = {
-        pstrUsageDataOnScreen,
-        pstrUsageClosedCaption,
-        pstrUsageClosedCaptionSelect,
-        pstrUsageVCRTV,
-        pstrUsageBroadcastMode,
-        pstrUsageSnapshot,
-        pstrUsageStill
-};
-const char * const ReportDescParserBase::consTitles5[] PROGMEM = {
-        pstrUsageSelection,
-        pstrUsageAssignSelection,
-        pstrUsageModeStep,
-        pstrUsageRecallLast,
-        pstrUsageEnterChannel,
-        pstrUsageOrderMovie,
-        pstrUsageChannel,
-        pstrUsageMediaSelection,
-        pstrUsageMediaSelectComputer,
-        pstrUsageMediaSelectTV,
-        pstrUsageMediaSelectWWW,
-        pstrUsageMediaSelectDVD,
-        pstrUsageMediaSelectTelephone,
-        pstrUsageMediaSelectProgramGuide,
-        pstrUsageMediaSelectVideoPhone,
-        pstrUsageMediaSelectGames,
-        pstrUsageMediaSelectMessages,
-        pstrUsageMediaSelectCD,
-        pstrUsageMediaSelectVCR,
-        pstrUsageMediaSelectTuner,
-        pstrUsageQuit,
-        pstrUsageHelp,
-        pstrUsageMediaSelectTape,
-        pstrUsageMediaSelectCable,
-        pstrUsageMediaSelectSatellite,
-        pstrUsageMediaSelectSecurity,
-        pstrUsageMediaSelectHome,
-        pstrUsageMediaSelectCall,
-        pstrUsageChannelIncrement,
-        pstrUsageChannelDecrement,
-        pstrUsageMediaSelectSAP,
-        pstrUsagePageReserved,
-        pstrUsageVCRPlus,
-        pstrUsageOnce,
-        pstrUsageDaily,
-        pstrUsageWeekly,
-        pstrUsageMonthly
-};
-const char * const ReportDescParserBase::consTitles6[] PROGMEM = {
-        pstrUsagePlay,
-        pstrUsagePause,
-        pstrUsageRecord,
-        pstrUsageFastForward,
-        pstrUsageRewind,
-        pstrUsageScanNextTrack,
-        pstrUsageScanPreviousTrack,
-        pstrUsageStop,
-        pstrUsageEject,
-        pstrUsageRandomPlay,
-        pstrUsageSelectDisk,
-        pstrUsageEnterDisk,
-        pstrUsageRepeat,
-        pstrUsageTracking,
-        pstrUsageTrackNormal,
-        pstrUsageSlowTracking,
-        pstrUsageFrameForward,
-        pstrUsageFrameBackwards,
-        pstrUsageMark,
-        pstrUsageClearMark,
-        pstrUsageRepeatFromMark,
-        pstrUsageReturnToMark,
-        pstrUsageSearchMarkForward,
-        pstrUsageSearchMarkBackwards,
-        pstrUsageCounterReset,
-        pstrUsageShowCounter,
-        pstrUsageTrackingIncrement,
-        pstrUsageTrackingDecrement,
-        pstrUsageStopEject,
-        pstrUsagePlayPause,
-        pstrUsagePlaySkip
-};
-const char * const ReportDescParserBase::consTitles7[] PROGMEM = {
-        pstrUsageVolume,
-        pstrUsageBalance,
-        pstrUsageMute,
-        pstrUsageBass,
-        pstrUsageTreble,
-        pstrUsageBassBoost,
-        pstrUsageSurroundMode,
-        pstrUsageLoudness,
-        pstrUsageMPX,
-        pstrUsageVolumeIncrement,
-        pstrUsageVolumeDecrement
-};
-const char * const ReportDescParserBase::consTitles8[] PROGMEM = {
-        pstrUsageSpeedSelect,
-        pstrUsagePlaybackSpeed,
-        pstrUsageStandardPlay,
-        pstrUsageLongPlay,
-        pstrUsageExtendedPlay,
-        pstrUsageSlow
-};
-const char * const ReportDescParserBase::consTitles9[] PROGMEM = {
-        pstrUsageFanEnable,
-        pstrUsageFanSpeed,
-        pstrUsageLightEnable,
-        pstrUsageLightIlluminationLevel,
-        pstrUsageClimateControlEnable,
-        pstrUsageRoomTemperature,
-        pstrUsageSecurityEnable,
-        pstrUsageFireAlarm,
-        pstrUsagePoliceAlarm,
-        pstrUsageProximity,
-        pstrUsageMotion,
-        pstrUsageDuresAlarm,
-        pstrUsageHoldupAlarm,
-        pstrUsageMedicalAlarm
-};
-const char * const ReportDescParserBase::consTitlesA[] PROGMEM = {
-        pstrUsageBalanceRight,
-        pstrUsageBalanceLeft,
-        pstrUsageBassIncrement,
-        pstrUsageBassDecrement,
-        pstrUsageTrebleIncrement,
-        pstrUsageTrebleDecrement
-};
-const char * const ReportDescParserBase::consTitlesB[] PROGMEM = {
-        pstrUsageSpeakerSystem,
-        pstrUsageChannelLeft,
-        pstrUsageChannelRight,
-        pstrUsageChannelCenter,
-        pstrUsageChannelFront,
-        pstrUsageChannelCenterFront,
-        pstrUsageChannelSide,
-        pstrUsageChannelSurround,
-        pstrUsageChannelLowFreqEnhancement,
-        pstrUsageChannelTop,
-        pstrUsageChannelUnknown
-};
-const char * const ReportDescParserBase::consTitlesC[] PROGMEM = {
-        pstrUsageSubChannel,
-        pstrUsageSubChannelIncrement,
-        pstrUsageSubChannelDecrement,
-        pstrUsageAlternateAudioIncrement,
-        pstrUsageAlternateAudioDecrement
-};
-const char * const ReportDescParserBase::consTitlesD[] PROGMEM = {
-        pstrUsageApplicationLaunchButtons,
-        pstrUsageALLaunchButtonConfigTool,
-        pstrUsageALProgrammableButton,
-        pstrUsageALConsumerControlConfig,
-        pstrUsageALWordProcessor,
-        pstrUsageALTextEditor,
-        pstrUsageALSpreadsheet,
-        pstrUsageALGraphicsEditor,
-        pstrUsageALPresentationApp,
-        pstrUsageALDatabaseApp,
-        pstrUsageALEmailReader,
-        pstrUsageALNewsreader,
-        pstrUsageALVoicemail,
-        pstrUsageALContactsAddressBook,
-        pstrUsageALCalendarSchedule,
-        pstrUsageALTaskProjectManager,
-        pstrUsageALLogJournalTimecard,
-        pstrUsageALCheckbookFinance,
-        pstrUsageALCalculator,
-        pstrUsageALAVCapturePlayback,
-        pstrUsageALLocalMachineBrowser,
-        pstrUsageALLANWANBrow,
-        pstrUsageALInternetBrowser,
-        pstrUsageALRemoteNetISPConnect,
-        pstrUsageALNetworkConference,
-        pstrUsageALNetworkChat,
-        pstrUsageALTelephonyDialer,
-        pstrUsageALLogon,
-        pstrUsageALLogoff,
-        pstrUsageALLogonLogoff,
-        pstrUsageALTermLockScrSav,
-        pstrUsageALControlPannel,
-        pstrUsageALCommandLineProcessorRun,
-        pstrUsageALProcessTaskManager,
-        pstrUsageALSelectTaskApplication,
-        pstrUsageALNextTaskApplication,
-        pstrUsageALPreviousTaskApplication,
-        pstrUsageALPreemptiveHaltTaskApp,
-        pstrUsageALIntegratedHelpCenter,
-        pstrUsageALDocuments,
-        pstrUsageALThesaurus,
-        pstrUsageALDictionary,
-        pstrUsageALDesktop,
-        pstrUsageALSpellCheck,
-        pstrUsageALGrammarCheck,
-        pstrUsageALWirelessStatus,
-        pstrUsageALKeyboardLayout,
-        pstrUsageALVirusProtection,
-        pstrUsageALEncryption,
-        pstrUsageALScreenSaver,
-        pstrUsageALAlarms,
-        pstrUsageALClock,
-        pstrUsageALFileBrowser,
-        pstrUsageALPowerStatus,
-        pstrUsageALImageBrowser,
-        pstrUsageALAudioBrowser,
-        pstrUsageALMovieBrowser,
-        pstrUsageALDigitalRightsManager,
-        pstrUsageALDigitalWallet,
-        pstrUsagePageReserved,
-        pstrUsageALInstantMessaging,
-        pstrUsageALOEMFeaturesBrowser,
-        pstrUsageALOEMHelp,
-        pstrUsageALOnlineCommunity,
-        pstrUsageALEntertainmentContentBrow,
-        pstrUsageALOnlineShoppingBrowser,
-        pstrUsageALSmartCardInfoHelp,
-        pstrUsageALMarketMonitorFinBrowser,
-        pstrUsageALCustomCorpNewsBrowser,
-        pstrUsageALOnlineActivityBrowser,
-        pstrUsageALResearchSearchBrowser,
-        pstrUsageALAudioPlayer
-};
-const char * const ReportDescParserBase::consTitlesE[] PROGMEM = {
-        pstrUsageGenericGUIAppControls,
-        pstrUsageACNew,
-        pstrUsageACOpen,
-        pstrUsageACClose,
-        pstrUsageACExit,
-        pstrUsageACMaximize,
-        pstrUsageACMinimize,
-        pstrUsageACSave,
-        pstrUsageACPrint,
-        pstrUsageACProperties,
-        pstrUsageACUndo,
-        pstrUsageACCopy,
-        pstrUsageACCut,
-        pstrUsageACPaste,
-        pstrUsageACSelectAll,
-        pstrUsageACFind,
-        pstrUsageACFindAndReplace,
-        pstrUsageACSearch,
-        pstrUsageACGoto,
-        pstrUsageACHome,
-        pstrUsageACBack,
-        pstrUsageACForward,
-        pstrUsageACStop,
-        pstrUsageACRefresh,
-        pstrUsageACPreviousLink,
-        pstrUsageACNextLink,
-        pstrUsageACBookmarks,
-        pstrUsageACHistory,
-        pstrUsageACSubscriptions,
-        pstrUsageACZoomIn,
-        pstrUsageACZoomOut,
-        pstrUsageACZoom,
-        pstrUsageACFullScreenView,
-        pstrUsageACNormalView,
-        pstrUsageACViewToggle,
-        pstrUsageACScrollUp,
-        pstrUsageACScrollDown,
-        pstrUsageACScroll,
-        pstrUsageACPanLeft,
-        pstrUsageACPanRight,
-        pstrUsageACPan,
-        pstrUsageACNewWindow,
-        pstrUsageACTileHoriz,
-        pstrUsageACTileVert,
-        pstrUsageACFormat,
-        pstrUsageACEdit,
-        pstrUsageACBold,
-        pstrUsageACItalics,
-        pstrUsageACUnderline,
-        pstrUsageACStrikethrough,
-        pstrUsageACSubscript,
-        pstrUsageACSuperscript,
-        pstrUsageACAllCaps,
-        pstrUsageACRotate,
-        pstrUsageACResize,
-        pstrUsageACFlipHorizontal,
-        pstrUsageACFlipVertical,
-        pstrUsageACMirrorHorizontal,
-        pstrUsageACMirrorVertical,
-        pstrUsageACFontSelect,
-        pstrUsageACFontColor,
-        pstrUsageACFontSize,
-        pstrUsageACJustifyLeft,
-        pstrUsageACJustifyCenterH,
-        pstrUsageACJustifyRight,
-        pstrUsageACJustifyBlockH,
-        pstrUsageACJustifyTop,
-        pstrUsageACJustifyCenterV,
-        pstrUsageACJustifyBottom,
-        pstrUsageACJustifyBlockV,
-        pstrUsageACIndentDecrease,
-        pstrUsageACIndentIncrease,
-        pstrUsageACNumberedList,
-        pstrUsageACRestartNumbering,
-        pstrUsageACBulletedList,
-        pstrUsageACPromote,
-        pstrUsageACDemote,
-        pstrUsageACYes,
-        pstrUsageACNo,
-        pstrUsageACCancel,
-        pstrUsageACCatalog,
-        pstrUsageACBuyChkout,
-        pstrUsageACAddToCart,
-        pstrUsageACExpand,
-        pstrUsageACExpandAll,
-        pstrUsageACCollapse,
-        pstrUsageACCollapseAll,
-        pstrUsageACPrintPreview,
-        pstrUsageACPasteSpecial,
-        pstrUsageACInsertMode,
-        pstrUsageACDelete,
-        pstrUsageACLock,
-        pstrUsageACUnlock,
-        pstrUsageACProtect,
-        pstrUsageACUnprotect,
-        pstrUsageACAttachComment,
-        pstrUsageACDeleteComment,
-        pstrUsageACViewComment,
-        pstrUsageACSelectWord,
-        pstrUsageACSelectSentence,
-        pstrUsageACSelectParagraph,
-        pstrUsageACSelectColumn,
-        pstrUsageACSelectRow,
-        pstrUsageACSelectTable,
-        pstrUsageACSelectObject,
-        pstrUsageACRedoRepeat,
-        pstrUsageACSort,
-        pstrUsageACSortAscending,
-        pstrUsageACSortDescending,
-        pstrUsageACFilter,
-        pstrUsageACSetClock,
-        pstrUsageACViewClock,
-        pstrUsageACSelectTimeZone,
-        pstrUsageACEditTimeZone,
-        pstrUsageACSetAlarm,
-        pstrUsageACClearAlarm,
-        pstrUsageACSnoozeAlarm,
-        pstrUsageACResetAlarm,
-        pstrUsageACSyncronize,
-        pstrUsageACSendReceive,
-        pstrUsageACSendTo,
-        pstrUsageACReply,
-        pstrUsageACReplyAll,
-        pstrUsageACForwardMessage,
-        pstrUsageACSend,
-        pstrUsageACAttachFile,
-        pstrUsageACUpload,
-        pstrUsageACDownload,
-        pstrUsageACSetBorders,
-        pstrUsageACInsertRow,
-        pstrUsageACInsertColumn,
-        pstrUsageACInsertFile,
-        pstrUsageACInsertPicture,
-        pstrUsageACInsertObject,
-        pstrUsageACInsertSymbol,
-        pstrUsageACSaveAndClose,
-        pstrUsageACRename,
-        pstrUsageACMerge,
-        pstrUsageACSplit,
-        pstrUsageACDistributeHorizontaly,
-        pstrUsageACDistributeVerticaly
-};
-const char * const ReportDescParserBase::digitTitles0[] PROGMEM = {
-        pstrUsageDigitizer,
-        pstrUsagePen,
-        pstrUsageLightPen,
-        pstrUsageTouchScreen,
-        pstrUsageTouchPad,
-        pstrUsageWhiteBoard,
-        pstrUsageCoordinateMeasuringMachine,
-        pstrUsage3DDigitizer,
-        pstrUsageStereoPlotter,
-        pstrUsageArticulatedArm,
-        pstrUsageArmature,
-        pstrUsageMultiplePointDigitizer,
-        pstrUsageFreeSpaceWand
-};
-const char * const ReportDescParserBase::digitTitles1[] PROGMEM = {
-        pstrUsageStylus,
-        pstrUsagePuck,
-        pstrUsageFinger
-
-};
-const char * const ReportDescParserBase::digitTitles2[] PROGMEM = {
-        pstrUsageTipPressure,
-        pstrUsageBarrelPressure,
-        pstrUsageInRange,
-        pstrUsageTouch,
-        pstrUsageUntouch,
-        pstrUsageTap,
-        pstrUsageQuality,
-        pstrUsageDataValid,
-        pstrUsageTransducerIndex,
-        pstrUsageTabletFunctionKeys,
-        pstrUsageProgramChangeKeys,
-        pstrUsageBatteryStrength,
-        pstrUsageInvert,
-        pstrUsageXTilt,
-        pstrUsageYTilt,
-        pstrUsageAzimuth,
-        pstrUsageAltitude,
-        pstrUsageTwist,
-        pstrUsageTipSwitch,
-        pstrUsageSecondaryTipSwitch,
-        pstrUsageBarrelSwitch,
-        pstrUsageEraser,
-        pstrUsageTabletPick
-};
-const char * const ReportDescParserBase::aplphanumTitles0[] PROGMEM = {
-        pstrUsageAlphanumericDisplay,
-        pstrUsageBitmappedDisplay
-};
-const char * const ReportDescParserBase::aplphanumTitles1[] PROGMEM = {
-        pstrUsageDisplayAttributesReport,
-        pstrUsageASCIICharacterSet,
-        pstrUsageDataReadBack,
-        pstrUsageFontReadBack,
-        pstrUsageDisplayControlReport,
-        pstrUsageClearDisplay,
-        pstrUsageDisplayEnable,
-        pstrUsageScreenSaverDelay,
-        pstrUsageScreenSaverEnable,
-        pstrUsageVerticalScroll,
-        pstrUsageHorizontalScroll,
-        pstrUsageCharacterReport,
-        pstrUsageDisplayData,
-        pstrUsageDisplayStatus,
-        pstrUsageStatusNotReady,
-        pstrUsageStatusReady,
-        pstrUsageErrorNotALoadableCharacter,
-        pstrUsageErrorFotDataCanNotBeRead,
-        pstrUsageCursorPositionReport,
-        pstrUsageRow,
-        pstrUsageColumn,
-        pstrUsageRows,
-        pstrUsageColumns,
-        pstrUsageCursorPixelPosition,
-        pstrUsageCursorMode,
-        pstrUsageCursorEnable,
-        pstrUsageCursorBlink,
-        pstrUsageFontReport,
-        pstrUsageFontData,
-        pstrUsageCharacterWidth,
-        pstrUsageCharacterHeight,
-        pstrUsageCharacterSpacingHorizontal,
-        pstrUsageCharacterSpacingVertical,
-        pstrUsageUnicodeCharset,
-        pstrUsageFont7Segment,
-        pstrUsage7SegmentDirectMap,
-        pstrUsageFont14Segment,
-        pstrUsage14SegmentDirectMap,
-        pstrUsageDisplayBrightness,
-        pstrUsageDisplayContrast,
-        pstrUsageCharacterAttribute,
-        pstrUsageAttributeReadback,
-        pstrUsageAttributeData,
-        pstrUsageCharAttributeEnhance,
-        pstrUsageCharAttributeUnderline,
-        pstrUsageCharAttributeBlink
-};
-const char * const ReportDescParserBase::aplphanumTitles2[] PROGMEM = {
-        pstrUsageBitmapSizeX,
-        pstrUsageBitmapSizeY,
-        pstrUsagePageReserved,
-        pstrUsageBitDepthFormat,
-        pstrUsageDisplayOrientation,
-        pstrUsagePaletteReport,
-        pstrUsagePaletteDataSize,
-        pstrUsagePaletteDataOffset,
-        pstrUsagePaletteData,
-        pstrUsageBlitReport,
-        pstrUsageBlitRectangleX1,
-        pstrUsageBlitRectangleY1,
-        pstrUsageBlitRectangleX2,
-        pstrUsageBlitRectangleY2,
-        pstrUsageBlitData,
-        pstrUsageSoftButton,
-        pstrUsageSoftButtonID,
-        pstrUsageSoftButtonSide,
-        pstrUsageSoftButtonOffset1,
-        pstrUsageSoftButtonOffset2,
-        pstrUsageSoftButtonReport
-};
-const char * const ReportDescParserBase::medInstrTitles0[] PROGMEM = {
-        pstrUsageVCRAcquisition,
-        pstrUsageFreezeThaw,
-        pstrUsageClipStore,
-        pstrUsageUpdate,
-        pstrUsageNext,
-        pstrUsageSave,
-        pstrUsagePrint,
-        pstrUsageMicrophoneEnable
-};
-const char * const ReportDescParserBase::medInstrTitles1[] PROGMEM = {
-        pstrUsageCine,
-        pstrUsageTransmitPower,
-        pstrUsageVolume,
-        pstrUsageFocus,
-        pstrUsageDepth
-};
-const char * const ReportDescParserBase::medInstrTitles2[] PROGMEM = {
-        pstrUsageSoftStepPrimary,
-        pstrUsageSoftStepSecondary
-};
-const char * const ReportDescParserBase::medInstrTitles3[] PROGMEM = {
-        pstrUsageZoomSelect,
-        pstrUsageZoomAdjust,
-        pstrUsageSpectralDopplerModeSelect,
-        pstrUsageSpectralDopplerModeAdjust,
-        pstrUsageColorDopplerModeSelect,
-        pstrUsageColorDopplerModeAdjust,
-        pstrUsageMotionModeSelect,
-        pstrUsageMotionModeAdjust,
-        pstrUsage2DModeSelect,
-        pstrUsage2DModeAdjust
-};
-const char * const ReportDescParserBase::medInstrTitles4[] PROGMEM = {
-        pstrUsageSoftControlSelect,
-        pstrUsageSoftControlAdjust
-};
-
-void ReportDescParserBase::Parse(const uint16_t len, const uint8_t *pbuf, const uint16_t &offset) {
-        uint16_t cntdn = (uint16_t)len;
-        uint8_t *p = (uint8_t*)pbuf;
-
-
-        totalSize = 0;
-
-        while(cntdn) {
-                //USB_HOST_SERIAL.println("");
-                //PrintHex<uint16_t>(offset + len - cntdn);
-                //USB_HOST_SERIAL.print(":");
-
-                ParseItem(&p, &cntdn);
-
-                //if (ParseItem(&p, &cntdn))
-                //        return;
-        }
-        //USBTRACE2("Total:", totalSize);
-}
-
-void ReportDescParserBase::PrintValue(uint8_t *p, uint8_t len) {
-        E_Notify(PSTR("("), 0x80);
-        for(; len; p++, len--)
-                PrintHex<uint8_t > (*p, 0x80);
-        E_Notify(PSTR(")"), 0x80);
-}
-
-void ReportDescParserBase::PrintByteValue(uint8_t data) {
-        E_Notify(PSTR("("), 0x80);
-        PrintHex<uint8_t > (data, 0x80);
-        E_Notify(PSTR(")"), 0x80);
-}
-
-void ReportDescParserBase::PrintItemTitle(uint8_t prefix) {
-        switch(prefix & (TYPE_MASK | TAG_MASK)) {
-                case (TYPE_GLOBAL | TAG_GLOBAL_PUSH):
-                        E_Notify(PSTR("\r\nPush"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_POP):
-                        E_Notify(PSTR("\r\nPop"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_USAGEPAGE):
-                        E_Notify(PSTR("\r\nUsage Page"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_LOGICALMIN):
-                        E_Notify(PSTR("\r\nLogical Min"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_LOGICALMAX):
-                        E_Notify(PSTR("\r\nLogical Max"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_PHYSMIN):
-                        E_Notify(PSTR("\r\nPhysical Min"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_PHYSMAX):
-                        E_Notify(PSTR("\r\nPhysical Max"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_UNITEXP):
-                        E_Notify(PSTR("\r\nUnit Exp"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_UNIT):
-                        E_Notify(PSTR("\r\nUnit"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_REPORTSIZE):
-                        E_Notify(PSTR("\r\nReport Size"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_REPORTCOUNT):
-                        E_Notify(PSTR("\r\nReport Count"), 0x80);
-                        break;
-                case (TYPE_GLOBAL | TAG_GLOBAL_REPORTID):
-                        E_Notify(PSTR("\r\nReport Id"), 0x80);
-                        break;
-                case (TYPE_LOCAL | TAG_LOCAL_USAGE):
-                        E_Notify(PSTR("\r\nUsage"), 0x80);
-                        break;
-                case (TYPE_LOCAL | TAG_LOCAL_USAGEMIN):
-                        E_Notify(PSTR("\r\nUsage Min"), 0x80);
-                        break;
-                case (TYPE_LOCAL | TAG_LOCAL_USAGEMAX):
-                        E_Notify(PSTR("\r\nUsage Max"), 0x80);
-                        break;
-                case (TYPE_MAIN | TAG_MAIN_COLLECTION):
-                        E_Notify(PSTR("\r\nCollection"), 0x80);
-                        break;
-                case (TYPE_MAIN | TAG_MAIN_ENDCOLLECTION):
-                        E_Notify(PSTR("\r\nEnd Collection"), 0x80);
-                        break;
-                case (TYPE_MAIN | TAG_MAIN_INPUT):
-                        E_Notify(PSTR("\r\nInput"), 0x80);
-                        break;
-                case (TYPE_MAIN | TAG_MAIN_OUTPUT):
-                        E_Notify(PSTR("\r\nOutput"), 0x80);
-                        break;
-                case (TYPE_MAIN | TAG_MAIN_FEATURE):
-                        E_Notify(PSTR("\r\nFeature"), 0x80);
-                        break;
-        } // switch (**pp & (TYPE_MASK | TAG_MASK))
-}
-
-uint8_t ReportDescParserBase::ParseItem(uint8_t **pp, uint16_t *pcntdn) {
-        //uint8_t ret = enErrorSuccess;
-        //reinterpret_cast<>(varBuffer);
-        switch(itemParseState) {
-                case 0:
-                        if(**pp == HID_LONG_ITEM_PREFIX)
-                                USBTRACE("\r\nLONG\r\n");
-                        else {
-                                uint8_t size = ((**pp) & DATA_SIZE_MASK);
-
-                                itemPrefix = (**pp);
-                                itemSize = 1 + ((size == DATA_SIZE_4) ? 4 : size);
-
-                                PrintItemTitle(itemPrefix);
-                        }
-                        (*pp)++;
-                        (*pcntdn)--;
-                        itemSize--;
-                        itemParseState = 1;
-
-                        if(!itemSize)
-                                break;
-
-                        if(!pcntdn)
-                                return enErrorIncomplete;
-                case 1:
-                        //USBTRACE2("\r\niSz:",itemSize);
-
-                        theBuffer.valueSize = itemSize;
-                        valParser.Initialize(&theBuffer);
-                        itemParseState = 2;
-                case 2:
-                        if(!valParser.Parse(pp, pcntdn))
-                                return enErrorIncomplete;
-                        itemParseState = 3;
-                case 3:
-                {
-                        uint8_t data = *((uint8_t*)varBuffer);
-
-                        switch(itemPrefix & (TYPE_MASK | TAG_MASK)) {
-                                case (TYPE_LOCAL | TAG_LOCAL_USAGE):
-                                        if(pfUsage) {
-                                                if(theBuffer.valueSize > 1) {
-                                                        uint16_t* ui16 = reinterpret_cast<uint16_t *>(varBuffer);
-                                                        pfUsage(*ui16);
-                                                } else
-                                                        pfUsage(data);
-                                        }
-                                        break;
-                                case (TYPE_GLOBAL | TAG_GLOBAL_REPORTSIZE):
-                                        rptSize = data;
-                                        PrintByteValue(data);
-                                        break;
-                                case (TYPE_GLOBAL | TAG_GLOBAL_REPORTCOUNT):
-                                        rptCount = data;
-                                        PrintByteValue(data);
-                                        break;
-                                case (TYPE_GLOBAL | TAG_GLOBAL_LOGICALMIN):
-                                case (TYPE_GLOBAL | TAG_GLOBAL_LOGICALMAX):
-                                case (TYPE_GLOBAL | TAG_GLOBAL_PHYSMIN):
-                                case (TYPE_GLOBAL | TAG_GLOBAL_PHYSMAX):
-                                case (TYPE_GLOBAL | TAG_GLOBAL_REPORTID):
-                                case (TYPE_LOCAL | TAG_LOCAL_USAGEMIN):
-                                case (TYPE_LOCAL | TAG_LOCAL_USAGEMAX):
-                                case (TYPE_GLOBAL | TAG_GLOBAL_UNITEXP):
-                                case (TYPE_GLOBAL | TAG_GLOBAL_UNIT):
-                                        PrintValue(varBuffer, theBuffer.valueSize);
-                                        break;
-                                case (TYPE_GLOBAL | TAG_GLOBAL_PUSH):
-                                case (TYPE_GLOBAL | TAG_GLOBAL_POP):
-                                        break;
-                                case (TYPE_GLOBAL | TAG_GLOBAL_USAGEPAGE):
-                                        SetUsagePage(data);
-                                        PrintUsagePage(data);
-                                        PrintByteValue(data);
-                                        break;
-                                case (TYPE_MAIN | TAG_MAIN_COLLECTION):
-                                case (TYPE_MAIN | TAG_MAIN_ENDCOLLECTION):
-                                        switch(data) {
-                                                case 0x00:
-                                                        E_Notify(PSTR(" Physical"), 0x80);
-                                                        break;
-                                                case 0x01:
-                                                        E_Notify(PSTR(" Application"), 0x80);
-                                                        break;
-                                                case 0x02:
-                                                        E_Notify(PSTR(" Logical"), 0x80);
-                                                        break;
-                                                case 0x03:
-                                                        E_Notify(PSTR(" Report"), 0x80);
-                                                        break;
-                                                case 0x04:
-                                                        E_Notify(PSTR(" Named Array"), 0x80);
-                                                        break;
-                                                case 0x05:
-                                                        E_Notify(PSTR(" Usage Switch"), 0x80);
-                                                        break;
-                                                case 0x06:
-                                                        E_Notify(PSTR(" Usage Modifier"), 0x80);
-                                                        break;
-                                                default:
-                                                        E_Notify(PSTR(" Vendor Defined("), 0x80);
-                                                        PrintHex<uint8_t > (data, 0x80);
-                                                        E_Notify(PSTR(")"), 0x80);
-                                        }
-                                        break;
-                                case (TYPE_MAIN | TAG_MAIN_INPUT):
-                                case (TYPE_MAIN | TAG_MAIN_OUTPUT):
-                                case (TYPE_MAIN | TAG_MAIN_FEATURE):
-                                        totalSize += (uint16_t)rptSize * (uint16_t)rptCount;
-                                        rptSize = 0;
-                                        rptCount = 0;
-                                        E_Notify(PSTR("("), 0x80);
-                                        PrintBin<uint8_t > (data, 0x80);
-                                        E_Notify(PSTR(")"), 0x80);
-                                        break;
-                        } // switch (**pp & (TYPE_MASK | TAG_MASK))
-                }
-        } // switch (itemParseState)
-        itemParseState = 0;
-        return enErrorSuccess;
-}
-
-ReportDescParserBase::UsagePageFunc ReportDescParserBase::usagePageFunctions[] /*PROGMEM*/ = {
-        &ReportDescParserBase::PrintGenericDesktopPageUsage,
-        &ReportDescParserBase::PrintSimulationControlsPageUsage,
-        &ReportDescParserBase::PrintVRControlsPageUsage,
-        &ReportDescParserBase::PrintSportsControlsPageUsage,
-        &ReportDescParserBase::PrintGameControlsPageUsage,
-        &ReportDescParserBase::PrintGenericDeviceControlsPageUsage,
-        NULL, // Keyboard/Keypad
-        &ReportDescParserBase::PrintLEDPageUsage,
-        &ReportDescParserBase::PrintButtonPageUsage,
-        &ReportDescParserBase::PrintOrdinalPageUsage,
-        &ReportDescParserBase::PrintTelephonyPageUsage,
-        &ReportDescParserBase::PrintConsumerPageUsage,
-        &ReportDescParserBase::PrintDigitizerPageUsage,
-        NULL, // Reserved
-        NULL, // PID
-        NULL // Unicode
-};
-
-void ReportDescParserBase::SetUsagePage(uint16_t page) {
-        pfUsage = NULL;
-
-        if(VALUE_BETWEEN(page, 0x00, 0x11)) {
-                pfUsage = (usagePageFunctions[page - 1]);
-
-        } else {
-                switch(page) {
-                        case 0x14:
-                                pfUsage = &ReportDescParserBase::PrintAlphanumDisplayPageUsage;
-                                break;
-                        case 0x40:
-                                pfUsage = &ReportDescParserBase::PrintMedicalInstrumentPageUsage;
-                                break;
-                }
-        }
-}
-
-void ReportDescParserBase::PrintUsagePage(uint16_t page) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(page, 0x00, 0x11, w, E_Notify, usagePageTitles0, 0x80)
-        else output_if_between(page, 0x8b, 0x92, w, E_Notify, usagePageTitles1, 0x80)
-        else if(VALUE_BETWEEN(page, 0x7f, 0x84))
-                E_Notify(pstrUsagePageMonitor, 0x80);
-        else if(VALUE_BETWEEN(page, 0x83, 0x8c))
-                E_Notify(pstrUsagePagePower, 0x80);
-        else if(page > 0xfeff /* && page <= 0xffff */)
-                E_Notify(pstrUsagePageVendorDefined, 0x80);
-        else
-                switch(page) {
-                        case 0x14:
-                                E_Notify(pstrUsagePageAlphaNumericDisplay, 0x80);
-                                break;
-                        case 0x40:
-                                E_Notify(pstrUsagePageMedicalInstruments, 0x80);
-                                break;
-                        default:
-                                E_Notify(pstrUsagePageUndefined, 0x80);
-                }
-}
-
-void ReportDescParserBase::PrintButtonPageUsage(uint16_t usage) {
-        E_Notify(pstrSpace, 0x80);
-        E_Notify(PSTR("Btn"), 0x80);
-        PrintHex<uint16_t > (usage, 0x80);
-        E_Notify(PSTR("\r\n"), 0x80);
-        //USB_HOST_SERIAL.print(usage, HEX);
-}
-
-void ReportDescParserBase::PrintOrdinalPageUsage(uint16_t usage) {
-        E_Notify(pstrSpace, 0x80);
-        E_Notify(PSTR("Inst"), 0x80);
-        // Sorry, HEX for now...
-        PrintHex<uint16_t > (usage, 0x80);
-        E_Notify(PSTR("\r\n"), 0x80);
-        //USB_HOST_SERIAL.print(usage, DEC);
-}
-
-void ReportDescParserBase::PrintGenericDesktopPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x0a, w, E_Notify, genDesktopTitles0, 0x80)
-        else output_if_between(usage, 0x2f, 0x49, w, E_Notify, genDesktopTitles1, 0x80)
-        else output_if_between(usage, 0x7f, 0x94, w, E_Notify, genDesktopTitles2, 0x80)
-        else output_if_between(usage, 0x9f, 0xa9, w, E_Notify, genDesktopTitles3, 0x80)
-        else output_if_between(usage, 0xaf, 0xb8, w, E_Notify, genDesktopTitles4, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintSimulationControlsPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x0d, w, E_Notify, simuTitles0, 0x80)
-        else output_if_between(usage, 0x1f, 0x26, w, E_Notify, simuTitles1, 0x80)
-        else output_if_between(usage, 0xaf, 0xd1, w, E_Notify, simuTitles2, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintVRControlsPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x0b, w, E_Notify, vrTitles0, 0x80)
-        else output_if_between(usage, 0x1f, 0x22, w, E_Notify, vrTitles1, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintSportsControlsPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x05, w, E_Notify, sportsCtrlTitles0, 0x80)
-        else output_if_between(usage, 0x2f, 0x3a, w, E_Notify, sportsCtrlTitles1, 0x80)
-        else output_if_between(usage, 0x4f, 0x64, w, E_Notify, sportsCtrlTitles2, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintGameControlsPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x04, w, E_Notify, gameTitles0, 0x80)
-        else output_if_between(usage, 0x1f, 0x3a, w, E_Notify, gameTitles1, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintGenericDeviceControlsPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x1f, 0x27, w, E_Notify, genDevCtrlTitles, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintLEDPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x4e, w, E_Notify, ledTitles, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintTelephonyPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x08, w, E_Notify, telTitles0, 0x80)
-        else output_if_between(usage, 0x1f, 0x32, w, E_Notify, telTitles1, 0x80)
-        else output_if_between(usage, 0x4f, 0x54, w, E_Notify, telTitles2, 0x80)
-        else output_if_between(usage, 0x6f, 0x75, w, E_Notify, telTitles3, 0x80)
-        else output_if_between(usage, 0x8f, 0x9f, w, E_Notify, telTitles4, 0x80)
-        else output_if_between(usage, 0xaf, 0xc0, w, E_Notify, telTitles5, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintConsumerPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x07, w, E_Notify, consTitles0, 0x80)
-        else output_if_between(usage, 0x1f, 0x23, w, E_Notify, consTitles1, 0x80)
-        else output_if_between(usage, 0x2f, 0x37, w, E_Notify, consTitles2, 0x80)
-        else output_if_between(usage, 0x3f, 0x49, w, E_Notify, consTitles3, 0x80)
-        else output_if_between(usage, 0x5f, 0x67, w, E_Notify, consTitles4, 0x80)
-        else output_if_between(usage, 0x7f, 0xa5, w, E_Notify, consTitles5, 0x80)
-        else output_if_between(usage, 0xaf, 0xcf, w, E_Notify, consTitles6, 0x80)
-        else output_if_between(usage, 0xdf, 0xeb, w, E_Notify, consTitles7, 0x80)
-        else output_if_between(usage, 0xef, 0xf6, w, E_Notify, consTitles8, 0x80)
-        else output_if_between(usage, 0xff, 0x10e, w, E_Notify, consTitles9, 0x80)
-        else output_if_between(usage, 0x14f, 0x156, w, E_Notify, consTitlesA, 0x80)
-        else output_if_between(usage, 0x15f, 0x16b, w, E_Notify, consTitlesB, 0x80)
-        else output_if_between(usage, 0x16f, 0x175, w, E_Notify, consTitlesC, 0x80)
-        else output_if_between(usage, 0x17f, 0x1c8, w, E_Notify, consTitlesD, 0x80)
-        else output_if_between(usage, 0x1ff, 0x29d, w, E_Notify, consTitlesE, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintDigitizerPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x0e, w, E_Notify, digitTitles0, 0x80)
-        else output_if_between(usage, 0x1f, 0x23, w, E_Notify, digitTitles1, 0x80)
-        else output_if_between(usage, 0x2f, 0x47, w, E_Notify, digitTitles2, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintAlphanumDisplayPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        output_if_between(usage, 0x00, 0x03, w, E_Notify, aplphanumTitles0, 0x80)
-        else output_if_between(usage, 0x1f, 0x4e, w, E_Notify, aplphanumTitles1, 0x80)
-        else output_if_between(usage, 0x7f, 0x96, w, E_Notify, digitTitles2, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-void ReportDescParserBase::PrintMedicalInstrumentPageUsage(uint16_t usage) {
-        const char * const * w;
-        E_Notify(pstrSpace, 0x80);
-
-        if(usage == 1) E_Notify(pstrUsageMedicalUltrasound, 0x80);
-        else if(usage == 0x70)
-                E_Notify(pstrUsageDepthGainCompensation, 0x80);
-        else output_if_between(usage, 0x1f, 0x28, w, E_Notify, medInstrTitles0, 0x80)
-        else output_if_between(usage, 0x3f, 0x45, w, E_Notify, medInstrTitles1, 0x80)
-        else output_if_between(usage, 0x5f, 0x62, w, E_Notify, medInstrTitles2, 0x80)
-        else output_if_between(usage, 0x7f, 0x8a, w, E_Notify, medInstrTitles3, 0x80)
-        else output_if_between(usage, 0x9f, 0xa2, w, E_Notify, medInstrTitles4, 0x80)
-        else E_Notify(pstrUsagePageUndefined, 0x80);
-}
-
-uint8_t ReportDescParser2::ParseItem(uint8_t **pp, uint16_t *pcntdn) {
-        //uint8_t ret = enErrorSuccess;
-
-        switch(itemParseState) {
-                case 0:
-                        if(**pp == HID_LONG_ITEM_PREFIX)
-                                USBTRACE("\r\nLONG\r\n");
-                        else {
-                                uint8_t size = ((**pp) & DATA_SIZE_MASK);
-                                itemPrefix = (**pp);
-                                itemSize = 1 + ((size == DATA_SIZE_4) ? 4 : size);
-                        }
-                        (*pp)++;
-                        (*pcntdn)--;
-                        itemSize--;
-                        itemParseState = 1;
-
-                        if(!itemSize)
-                                break;
-
-                        if(!pcntdn)
-                                return enErrorIncomplete;
-                case 1:
-                        theBuffer.valueSize = itemSize;
-                        valParser.Initialize(&theBuffer);
-                        itemParseState = 2;
-                case 2:
-                        if(!valParser.Parse(pp, pcntdn))
-                                return enErrorIncomplete;
-                        itemParseState = 3;
-                case 3:
-                {
-                        uint8_t data = *((uint8_t*)varBuffer);
-
-                        switch(itemPrefix & (TYPE_MASK | TAG_MASK)) {
-                                case (TYPE_LOCAL | TAG_LOCAL_USAGE):
-                                        if(pfUsage) {
-                                                if(theBuffer.valueSize > 1) {
-                                                        uint16_t* ui16 = reinterpret_cast<uint16_t *>(varBuffer);
-                                                        pfUsage(*ui16);
-                                                } else
-                                                        pfUsage(data);
-                                        }
-                                        break;
-                                case (TYPE_GLOBAL | TAG_GLOBAL_REPORTSIZE):
-                                        rptSize = data;
-                                        break;
-                                case (TYPE_GLOBAL | TAG_GLOBAL_REPORTCOUNT):
-                                        rptCount = data;
-                                        break;
-                                case (TYPE_GLOBAL | TAG_GLOBAL_REPORTID):
-                                        rptId = data;
-                                        break;
-                                case (TYPE_LOCAL | TAG_LOCAL_USAGEMIN):
-                                        useMin = data;
-                                        break;
-                                case (TYPE_LOCAL | TAG_LOCAL_USAGEMAX):
-                                        useMax = data;
-                                        break;
-                                case (TYPE_GLOBAL | TAG_GLOBAL_USAGEPAGE):
-                                        SetUsagePage(data);
-                                        break;
-                                case (TYPE_MAIN | TAG_MAIN_OUTPUT):
-                                case (TYPE_MAIN | TAG_MAIN_FEATURE):
-                                        rptSize = 0;
-                                        rptCount = 0;
-                                        useMin = 0;
-                                        useMax = 0;
-                                        break;
-                                case (TYPE_MAIN | TAG_MAIN_INPUT):
-                                        OnInputItem(data);
-
-                                        totalSize += (uint16_t)rptSize * (uint16_t)rptCount;
-
-                                        rptSize = 0;
-                                        rptCount = 0;
-                                        useMin = 0;
-                                        useMax = 0;
-                                        break;
-                        } // switch (**pp & (TYPE_MASK | TAG_MASK))
-                }
-        } // switch (itemParseState)
-        itemParseState = 0;
-        return enErrorSuccess;
-}
-
-void ReportDescParser2::OnInputItem(uint8_t itm) {
-        uint8_t byte_offset = (totalSize >> 3); // calculate offset to the next unhandled byte i = (int)(totalCount / 8);
-        uint32_t tmp = (byte_offset << 3);
-        uint8_t bit_offset = totalSize - tmp; // number of bits in the current byte already handled
-        uint8_t *p = pBuf + byte_offset; // current byte pointer
-
-        if(bit_offset)
-                *p >>= bit_offset;
-
-        uint8_t usage = useMin;
-
-        bool print_usemin_usemax = ((useMin < useMax) && ((itm & 3) == 2) && pfUsage) ? true : false;
-
-        uint8_t bits_of_byte = 8;
-
-        // for each field in field array defined by rptCount
-        for(uint8_t field = 0; field < rptCount; field++, usage++) {
-
-                union {
-                        uint8_t bResult[4];
-                        uint16_t wResult[2];
-                        uint32_t dwResult;
-                } result;
-
-                result.dwResult = 0;
-                uint8_t mask = 0;
-
-                if(print_usemin_usemax)
-                        pfUsage(usage);
-
-                // bits_left            - number of bits in the field(array of fields, depending on Report Count) left to process
-                // bits_of_byte         - number of bits in current byte left to process
-                // bits_to_copy         - number of bits to copy to result buffer
-
-                // for each bit in a field
-                for(uint8_t bits_left = rptSize, bits_to_copy = 0; bits_left;
-                        bits_left -= bits_to_copy) {
-                        bits_to_copy = (bits_left > bits_of_byte) ? bits_of_byte : bits_left;
-
-                        result.dwResult <<= bits_to_copy; // Result buffer is shifted by the number of bits to be copied into it
-
-                        uint8_t val = *p;
-
-                        val >>= (8 - bits_of_byte); // Shift by the number of bits already processed
-
-                        mask = 0;
-
-                        for(uint8_t j = bits_to_copy; j; j--) {
-                                mask <<= 1;
-                                mask |= 1;
-                        }
-
-                        result.bResult[0] = (result.bResult[0] | (val & mask));
-
-                        bits_of_byte -= bits_to_copy;
-
-                        if(bits_of_byte < 1) {
-                                bits_of_byte = 8;
-                                p++;
-                        }
-                }
-                PrintByteValue(result.dwResult);
-        }
-        E_Notify(PSTR("\r\n"), 0x80);
-}
-
-void UniversalReportParser::Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf) {
-        ReportDescParser2 prs(len, buf);
-
-        uint8_t ret = hid->GetReportDescr(0, &prs);
-
-        if(ret)
-                ErrorMessage<uint8_t > (PSTR("GetReportDescr-2"), ret);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hidescriptorparser.h b/lib/usbhost/USB_Host_Shield_2.0/hidescriptorparser.h
deleted file mode 100644
index f3b496ffa5..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hidescriptorparser.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(__HIDDESCRIPTORPARSER_H__)
-#define __HIDDESCRIPTORPARSER_H__
-
-#include "hid.h"
-
-class ReportDescParserBase : public USBReadParser {
-public:
-        typedef void (*UsagePageFunc)(uint16_t usage);
-
-        static void PrintGenericDesktopPageUsage(uint16_t usage);
-        static void PrintSimulationControlsPageUsage(uint16_t usage);
-        static void PrintVRControlsPageUsage(uint16_t usage);
-        static void PrintSportsControlsPageUsage(uint16_t usage);
-        static void PrintGameControlsPageUsage(uint16_t usage);
-        static void PrintGenericDeviceControlsPageUsage(uint16_t usage);
-        static void PrintLEDPageUsage(uint16_t usage);
-        static void PrintButtonPageUsage(uint16_t usage);
-        static void PrintOrdinalPageUsage(uint16_t usage);
-        static void PrintTelephonyPageUsage(uint16_t usage);
-        static void PrintConsumerPageUsage(uint16_t usage);
-        static void PrintDigitizerPageUsage(uint16_t usage);
-        static void PrintAlphanumDisplayPageUsage(uint16_t usage);
-        static void PrintMedicalInstrumentPageUsage(uint16_t usage);
-
-        static void PrintValue(uint8_t *p, uint8_t len);
-        static void PrintByteValue(uint8_t data);
-
-        static void PrintItemTitle(uint8_t prefix);
-
-        static const char * const usagePageTitles0[];
-        static const char * const usagePageTitles1[];
-        static const char * const genDesktopTitles0[];
-        static const char * const genDesktopTitles1[];
-        static const char * const genDesktopTitles2[];
-        static const char * const genDesktopTitles3[];
-        static const char * const genDesktopTitles4[];
-        static const char * const simuTitles0[];
-        static const char * const simuTitles1[];
-        static const char * const simuTitles2[];
-        static const char * const vrTitles0[];
-        static const char * const vrTitles1[];
-        static const char * const sportsCtrlTitles0[];
-        static const char * const sportsCtrlTitles1[];
-        static const char * const sportsCtrlTitles2[];
-        static const char * const gameTitles0[];
-        static const char * const gameTitles1[];
-        static const char * const genDevCtrlTitles[];
-        static const char * const ledTitles[];
-        static const char * const telTitles0[];
-        static const char * const telTitles1[];
-        static const char * const telTitles2[];
-        static const char * const telTitles3[];
-        static const char * const telTitles4[];
-        static const char * const telTitles5[];
-        static const char * const consTitles0[];
-        static const char * const consTitles1[];
-        static const char * const consTitles2[];
-        static const char * const consTitles3[];
-        static const char * const consTitles4[];
-        static const char * const consTitles5[];
-        static const char * const consTitles6[];
-        static const char * const consTitles7[];
-        static const char * const consTitles8[];
-        static const char * const consTitles9[];
-        static const char * const consTitlesA[];
-        static const char * const consTitlesB[];
-        static const char * const consTitlesC[];
-        static const char * const consTitlesD[];
-        static const char * const consTitlesE[];
-        static const char * const digitTitles0[];
-        static const char * const digitTitles1[];
-        static const char * const digitTitles2[];
-        static const char * const aplphanumTitles0[];
-        static const char * const aplphanumTitles1[];
-        static const char * const aplphanumTitles2[];
-        static const char * const medInstrTitles0[];
-        static const char * const medInstrTitles1[];
-        static const char * const medInstrTitles2[];
-        static const char * const medInstrTitles3[];
-        static const char * const medInstrTitles4[];
-
-protected:
-        static UsagePageFunc usagePageFunctions[];
-
-        MultiValueBuffer theBuffer;
-        MultiByteValueParser valParser;
-        ByteSkipper theSkipper;
-        uint8_t varBuffer[sizeof (USB_CONFIGURATION_DESCRIPTOR)];
-
-        uint8_t itemParseState; // Item parser state variable
-        uint8_t itemSize; // Item size
-        uint8_t itemPrefix; // Item prefix (first byte)
-        uint8_t rptSize; // Report Size
-        uint8_t rptCount; // Report Count
-
-        uint16_t totalSize; // Report size in bits
-
-        // Method should be defined here if virtual.
-        virtual uint8_t ParseItem(uint8_t **pp, uint16_t *pcntdn);
-
-        UsagePageFunc pfUsage;
-
-        static void PrintUsagePage(uint16_t page);
-        void SetUsagePage(uint16_t page);
-
-public:
-
-        ReportDescParserBase() :
-        itemParseState(0),
-        itemSize(0),
-        itemPrefix(0),
-        rptSize(0),
-        rptCount(0),
-        pfUsage(NULL) {
-                theBuffer.pValue = varBuffer;
-                valParser.Initialize(&theBuffer);
-                theSkipper.Initialize(&theBuffer);
-        };
-
-        void Parse(const uint16_t len, const uint8_t *pbuf, const uint16_t &offset);
-
-        enum {
-                enErrorSuccess = 0
-                , enErrorIncomplete // value or record is partialy read in buffer
-                , enErrorBufferTooSmall
-        };
-};
-
-class ReportDescParser : public ReportDescParserBase {
-};
-
-class ReportDescParser2 : public ReportDescParserBase {
-        uint8_t rptId; // Report ID
-        uint8_t useMin; // Usage Minimum
-        uint8_t useMax; // Usage Maximum
-        uint8_t fieldCount; // Number of field being currently processed
-
-        void OnInputItem(uint8_t itm); // Method which is called every time Input item is found
-
-        uint8_t *pBuf; // Report buffer pointer
-        uint8_t bLen; // Report length
-
-protected:
-        // Method should be defined here if virtual.
-        virtual uint8_t ParseItem(uint8_t **pp, uint16_t *pcntdn);
-
-public:
-
-        ReportDescParser2(uint16_t len, uint8_t *pbuf) :
-        ReportDescParserBase(), rptId(0), useMin(0), useMax(0), fieldCount(0), pBuf(pbuf), bLen(len) {
-        };
-};
-
-class UniversalReportParser : public HIDReportParser {
-public:
-        // Method should be defined here if virtual.
-        virtual void Parse(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf);
-};
-
-#endif // __HIDDESCRIPTORPARSER_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hiduniversal.cpp b/lib/usbhost/USB_Host_Shield_2.0/hiduniversal.cpp
deleted file mode 100644
index 395aa69e34..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hiduniversal.cpp
+++ /dev/null
@@ -1,425 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#include "hiduniversal.h"
-
-HIDUniversal::HIDUniversal(USB *p) :
-HID(p),
-qNextPollTime(0),
-pollInterval(0),
-bPollEnable(false),
-bHasReportId(false) {
-        Initialize();
-
-        if(pUsb)
-                pUsb->RegisterDeviceClass(this);
-}
-
-uint16_t HIDUniversal::GetHidClassDescrLen(uint8_t type, uint8_t num) {
-        for(uint8_t i = 0, n = 0; i < HID_MAX_HID_CLASS_DESCRIPTORS; i++) {
-                if(descrInfo[i].bDescrType == type) {
-                        if(n == num)
-                                return descrInfo[i].wDescriptorLength;
-                        n++;
-                }
-        }
-        return 0;
-}
-
-void HIDUniversal::Initialize() {
-        for(uint8_t i = 0; i < MAX_REPORT_PARSERS; i++) {
-                rptParsers[i].rptId = 0;
-                rptParsers[i].rptParser = NULL;
-        }
-        for(uint8_t i = 0; i < HID_MAX_HID_CLASS_DESCRIPTORS; i++) {
-                descrInfo[i].bDescrType = 0;
-                descrInfo[i].wDescriptorLength = 0;
-        }
-        for(uint8_t i = 0; i < maxHidInterfaces; i++) {
-                hidInterfaces[i].bmInterface = 0;
-                hidInterfaces[i].bmProtocol = 0;
-
-                for(uint8_t j = 0; j < maxEpPerInterface; j++)
-                        hidInterfaces[i].epIndex[j] = 0;
-        }
-        for(uint8_t i = 0; i < totalEndpoints; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-                epInfo[i].bmNakPower = (i) ? USB_NAK_NOWAIT : USB_NAK_MAX_POWER;
-        }
-        bNumEP = 1;
-        bNumIface = 0;
-        bConfNum = 0;
-        pollInterval = 0;
-
-        ZeroMemory(constBuffLen, prevBuf);
-}
-
-bool HIDUniversal::SetReportParser(uint8_t id, HIDReportParser *prs) {
-        for(uint8_t i = 0; i < MAX_REPORT_PARSERS; i++) {
-                if(rptParsers[i].rptId == 0 && rptParsers[i].rptParser == NULL) {
-                        rptParsers[i].rptId = id;
-                        rptParsers[i].rptParser = prs;
-                        return true;
-                }
-        }
-        return false;
-}
-
-HIDReportParser* HIDUniversal::GetReportParser(uint8_t id) {
-        if(!bHasReportId)
-                return ((rptParsers[0].rptParser) ? rptParsers[0].rptParser : NULL);
-
-        for(uint8_t i = 0; i < MAX_REPORT_PARSERS; i++) {
-                if(rptParsers[i].rptId == id)
-                        return rptParsers[i].rptParser;
-        }
-        return NULL;
-}
-
-uint8_t HIDUniversal::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        const uint8_t constBufSize = sizeof (USB_DEVICE_DESCRIPTOR);
-
-        uint8_t buf[constBufSize];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint8_t len = 0;
-
-        uint8_t num_of_conf; // number of configurations
-        //uint8_t num_of_intf; // number of interfaces
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-
-        USBTRACE("HU Init\r\n");
-
-        if(bAddress)
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        if(!p->epinfo) {
-                USBTRACE("epinfo\r\n");
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, 8, (uint8_t*)buf);
-
-        if(!rcode)
-                len = (buf[0] > constBufSize) ? constBufSize : buf[0];
-
-        if(rcode) {
-                // Restore p->epinfo
-                p->epinfo = oldep_ptr;
-
-                goto FailGetDevDescr;
-        }
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from the device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                USBTRACE2("setAddr:", rcode);
-                return rcode;
-        }
-
-        //delay(2); //per USB 2.0 sect.9.2.6.3
-
-        USBTRACE2("Addr:", bAddress);
-
-        p->lowspeed = false;
-
-        p = addrPool.GetUsbDevicePtr(bAddress);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        if(len)
-                rcode = pUsb->getDevDescr(bAddress, 0, len, (uint8_t*)buf);
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        VID = udd->idVendor; // Can be used by classes that inherits this class to check the VID and PID of the connected device
-        PID = udd->idProduct;
-
-        num_of_conf = udd->bNumConfigurations;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        USBTRACE2("NC:", num_of_conf);
-
-        for(uint8_t i = 0; i < num_of_conf; i++) {
-                //HexDumper<USBReadParser, uint16_t, uint16_t> HexDump;
-                ConfigDescParser<USB_CLASS_HID, 0, 0,
-                        CP_MASK_COMPARE_CLASS> confDescrParser(this);
-
-                //rcode = pUsb->getConfDescr(bAddress, 0, i, &HexDump);
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &confDescrParser);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                if(bNumEP > 1)
-                        break;
-        } // for
-
-        if(bNumEP < 2)
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, bNumEP, epInfo);
-
-        USBTRACE2("Cnf:", bConfNum);
-
-        // Set Configuration Value
-        rcode = pUsb->setConf(bAddress, 0, bConfNum);
-
-        if(rcode)
-                goto FailSetConfDescr;
-
-        for(uint8_t i = 0; i < bNumIface; i++) {
-                if(hidInterfaces[i].epIndex[epInterruptInIndex] == 0)
-                        continue;
-
-                rcode = SetIdle(hidInterfaces[i].bmInterface, 0, 0);
-
-                if(rcode && rcode != hrSTALL)
-                        goto FailSetIdle;
-        }
-
-        USBTRACE("HU configured\r\n");
-
-        OnInitSuccessful();
-
-        bPollEnable = true;
-        return 0;
-
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr();
-        goto Fail;
-#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailGetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetConfDescr();
-        goto Fail;
-#endif
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-        goto Fail;
-#endif
-
-
-FailSetIdle:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("SetIdle:");
-#endif
-
-#ifdef DEBUG_USB_HOST
-Fail:
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-HIDUniversal::HIDInterface* HIDUniversal::FindInterface(uint8_t iface, uint8_t alt, uint8_t proto) {
-        for(uint8_t i = 0; i < bNumIface && i < maxHidInterfaces; i++)
-                if(hidInterfaces[i].bmInterface == iface && hidInterfaces[i].bmAltSet == alt
-                        && hidInterfaces[i].bmProtocol == proto)
-                        return hidInterfaces + i;
-        return NULL;
-}
-
-void HIDUniversal::EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *pep) {
-        // If the first configuration satisfies, the others are not concidered.
-        if(bNumEP > 1 && conf != bConfNum)
-                return;
-
-        //ErrorMessage<uint8_t>(PSTR("\r\nConf.Val"), conf);
-        //ErrorMessage<uint8_t>(PSTR("Iface Num"), iface);
-        //ErrorMessage<uint8_t>(PSTR("Alt.Set"), alt);
-
-        bConfNum = conf;
-
-        uint8_t index = 0;
-        HIDInterface *piface = FindInterface(iface, alt, proto);
-
-        // Fill in interface structure in case of new interface
-        if(!piface) {
-                piface = hidInterfaces + bNumIface;
-                piface->bmInterface = iface;
-                piface->bmAltSet = alt;
-                piface->bmProtocol = proto;
-                bNumIface++;
-        }
-
-        if((pep->bmAttributes & 0x03) == 3 && (pep->bEndpointAddress & 0x80) == 0x80)
-                index = epInterruptInIndex;
-        else
-                index = epInterruptOutIndex;
-
-        if(index) {
-                // Fill in the endpoint info structure
-                epInfo[bNumEP].epAddr = (pep->bEndpointAddress & 0x0F);
-                epInfo[bNumEP].maxPktSize = (uint8_t)pep->wMaxPacketSize;
-                epInfo[bNumEP].epAttribs = 0;
-                epInfo[bNumEP].bmNakPower = USB_NAK_NOWAIT;
-
-                // Fill in the endpoint index list
-                piface->epIndex[index] = bNumEP; //(pep->bEndpointAddress & 0x0F);
-
-                if(pollInterval < pep->bInterval) // Set the polling interval as the largest polling interval obtained from endpoints
-                        pollInterval = pep->bInterval;
-
-                bNumEP++;
-        }
-        //PrintEndpointDescriptor(pep);
-}
-
-uint8_t HIDUniversal::Release() {
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-
-        bNumEP = 1;
-        bAddress = 0;
-        qNextPollTime = 0;
-        bPollEnable = false;
-        return 0;
-}
-
-bool HIDUniversal::BuffersIdentical(uint8_t len, uint8_t *buf1, uint8_t *buf2) {
-        for(uint8_t i = 0; i < len; i++)
-                if(buf1[i] != buf2[i])
-                        return false;
-        return true;
-}
-
-void HIDUniversal::ZeroMemory(uint8_t len, uint8_t *buf) {
-        for(uint8_t i = 0; i < len; i++)
-                buf[i] = 0;
-}
-
-void HIDUniversal::SaveBuffer(uint8_t len, uint8_t *src, uint8_t *dest) {
-        for(uint8_t i = 0; i < len; i++)
-                dest[i] = src[i];
-}
-
-uint8_t HIDUniversal::Poll() {
-        uint8_t rcode = 0;
-
-        if(!bPollEnable)
-                return 0;
-
-        if((long)(millis() - qNextPollTime) >= 0L) {
-                qNextPollTime = millis() + pollInterval;
-
-                uint8_t buf[constBuffLen];
-
-                for(uint8_t i = 0; i < bNumIface; i++) {
-                        uint8_t index = hidInterfaces[i].epIndex[epInterruptInIndex];
-                        uint16_t read = (uint16_t)epInfo[index].maxPktSize;
-
-                        ZeroMemory(constBuffLen, buf);
-
-                        uint8_t rcode = pUsb->inTransfer(bAddress, epInfo[index].epAddr, &read, buf);
-
-                        if(rcode) {
-                                if(rcode != hrNAK)
-                                        USBTRACE3("(hiduniversal.h) Poll:", rcode, 0x81);
-                                return rcode;
-                        }
-
-                        if(read > constBuffLen)
-                                read = constBuffLen;
-
-                        bool identical = BuffersIdentical(read, buf, prevBuf);
-
-                        SaveBuffer(read, buf, prevBuf);
-
-                        if(identical)
-                                return 0;
-#if 0
-                        Notify(PSTR("\r\nBuf: "), 0x80);
-
-                        for(uint8_t i = 0; i < read; i++) {
-                                D_PrintHex<uint8_t > (buf[i], 0x80);
-                                Notify(PSTR(" "), 0x80);
-                        }
-
-                        Notify(PSTR("\r\n"), 0x80);
-#endif
-                        ParseHIDData(this, bHasReportId, (uint8_t)read, buf);
-
-                        HIDReportParser *prs = GetReportParser(((bHasReportId) ? *buf : 0));
-
-                        if(prs)
-                                prs->Parse(this, bHasReportId, (uint8_t)read, buf);
-                }
-        }
-        return rcode;
-}
-
-// Send a report to interrupt out endpoint. This is NOT SetReport() request!
-uint8_t HIDUniversal::SndRpt(uint16_t nbytes, uint8_t *dataptr) {
-        return pUsb->outTransfer(bAddress, epInfo[epInterruptOutIndex].epAddr, nbytes, dataptr);
-}
\ No newline at end of file
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hiduniversal.h b/lib/usbhost/USB_Host_Shield_2.0/hiduniversal.h
deleted file mode 100644
index d7af384068..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hiduniversal.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#if !defined(__HIDUNIVERSAL_H__)
-#define __HIDUNIVERSAL_H__
-
-#include "hid.h"
-//#include "hidescriptorparser.h"
-
-class HIDUniversal : public HID {
-
-        struct ReportParser {
-                uint8_t rptId;
-                HIDReportParser *rptParser;
-        } rptParsers[MAX_REPORT_PARSERS];
-
-        // HID class specific descriptor type and length info obtained from HID descriptor
-        HID_CLASS_DESCRIPTOR_LEN_AND_TYPE descrInfo[HID_MAX_HID_CLASS_DESCRIPTORS];
-
-        // Returns HID class specific descriptor length by its type and order number
-        uint16_t GetHidClassDescrLen(uint8_t type, uint8_t num);
-
-        struct HIDInterface {
-                struct {
-                        uint8_t bmInterface : 3;
-                        uint8_t bmAltSet : 3;
-                        uint8_t bmProtocol : 2;
-                };
-                uint8_t epIndex[maxEpPerInterface];
-        };
-
-        uint8_t bConfNum; // configuration number
-        uint8_t bNumIface; // number of interfaces in the configuration
-        uint8_t bNumEP; // total number of EP in the configuration
-        uint32_t qNextPollTime; // next poll time
-        uint8_t pollInterval;
-        bool bPollEnable; // poll enable flag
-
-        static const uint16_t constBuffLen = 64; // event buffer length
-        uint8_t prevBuf[constBuffLen]; // previous event buffer
-
-        void Initialize();
-        HIDInterface* FindInterface(uint8_t iface, uint8_t alt, uint8_t proto);
-
-        void ZeroMemory(uint8_t len, uint8_t *buf);
-        bool BuffersIdentical(uint8_t len, uint8_t *buf1, uint8_t *buf2);
-        void SaveBuffer(uint8_t len, uint8_t *src, uint8_t *dest);
-
-protected:
-        EpInfo epInfo[totalEndpoints];
-        HIDInterface hidInterfaces[maxHidInterfaces];
-
-        bool bHasReportId;
-
-        uint16_t PID, VID; // PID and VID of connected device
-
-        // HID implementation
-        HIDReportParser* GetReportParser(uint8_t id);
-
-        virtual uint8_t OnInitSuccessful() {
-                return 0;
-        };
-
-        virtual void ParseHIDData(HID *hid, bool is_rpt_id, uint8_t len, uint8_t *buf) {
-                return;
-        };
-
-public:
-        HIDUniversal(USB *p);
-
-        // HID implementation
-        bool SetReportParser(uint8_t id, HIDReportParser *prs);
-
-        // USBDeviceConfig implementation
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t Release();
-        uint8_t Poll();
-
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        virtual bool isReady() {
-                return bPollEnable;
-        };
-
-        // UsbConfigXtracter implementation
-        void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep);
-
-        // Send report - do not mix with SetReport()!
-        uint8_t SndRpt(uint16_t nbytes, uint8_t *dataptr);
-};
-
-#endif // __HIDUNIVERSAL_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hidusagestr.h b/lib/usbhost/USB_Host_Shield_2.0/hidusagestr.h
deleted file mode 100644
index 5ef48f925b..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hidusagestr.h
+++ /dev/null
@@ -1,977 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined( __HIDUSAGESTR_H__)
-#define  __HIDUSAGESTR_H__
-
-#include "Usb.h"
-
-const char pstrSpace [] PROGMEM = " ";
-const char pstrCRLF [] PROGMEM = "\r\n";
-const char pstrSingleTab [] PROGMEM = "\t";
-const char pstrDoubleTab [] PROGMEM = "\t\t";
-const char pstrTripleTab [] PROGMEM = "\t\t\t";
-
-// Usage Page String Titles
-const char pstrUsagePageUndefined [] PROGMEM = "Undef";
-const char pstrUsagePageGenericDesktopControls [] PROGMEM = "Gen Desktop Ctrls";
-const char pstrUsagePageSimulationControls [] PROGMEM = "Simu Ctrls";
-const char pstrUsagePageVRControls [] PROGMEM = "VR Ctrls";
-const char pstrUsagePageSportControls [] PROGMEM = "Sport Ctrls";
-const char pstrUsagePageGameControls [] PROGMEM = "Game Ctrls";
-const char pstrUsagePageGenericDeviceControls [] PROGMEM = "Gen Dev Ctrls";
-const char pstrUsagePageKeyboardKeypad [] PROGMEM = "Kbrd/Keypad";
-const char pstrUsagePageLEDs [] PROGMEM = "LEDs";
-const char pstrUsagePageButton [] PROGMEM = "Button";
-const char pstrUsagePageOrdinal [] PROGMEM = "Ordinal";
-const char pstrUsagePageTelephone [] PROGMEM = "Tel";
-const char pstrUsagePageConsumer [] PROGMEM = "Consumer";
-const char pstrUsagePageDigitizer [] PROGMEM = "Digitizer";
-const char pstrUsagePagePID [] PROGMEM = "PID";
-const char pstrUsagePageUnicode [] PROGMEM = "Unicode";
-const char pstrUsagePageAlphaNumericDisplay [] PROGMEM = "Alpha Num Disp";
-const char pstrUsagePageMedicalInstruments [] PROGMEM = "Medical Instr";
-const char pstrUsagePageMonitor [] PROGMEM = "Monitor";
-const char pstrUsagePagePower [] PROGMEM = "Power";
-const char pstrUsagePageBarCodeScanner [] PROGMEM = "Bar Code Scan";
-const char pstrUsagePageScale [] PROGMEM = "Scale";
-const char pstrUsagePageMSRDevices [] PROGMEM = "Magn Stripe Read Dev";
-const char pstrUsagePagePointOfSale [] PROGMEM = "POS";
-const char pstrUsagePageCameraControl [] PROGMEM = "Cam Ctrl";
-const char pstrUsagePageArcade [] PROGMEM = "Arcade";
-const char pstrUsagePageReserved [] PROGMEM = "Reserved";
-const char pstrUsagePageVendorDefined [] PROGMEM = "Vendor Def";
-
-// Generic Desktop Controls Page
-const char pstrUsagePointer [] PROGMEM = "Pointer";
-const char pstrUsageMouse [] PROGMEM = "Mouse";
-const char pstrUsageJoystick [] PROGMEM = "Joystick";
-const char pstrUsageGamePad [] PROGMEM = "Game Pad";
-const char pstrUsageKeyboard [] PROGMEM = "Kbrd";
-const char pstrUsageKeypad [] PROGMEM = "Keypad";
-const char pstrUsageMultiAxisController [] PROGMEM = "Multi-axis Ctrl";
-const char pstrUsageTabletPCSystemControls [] PROGMEM = "Tablet PC Sys Ctrls";
-const char pstrUsageX [] PROGMEM = "X";
-const char pstrUsageY [] PROGMEM = "Y";
-const char pstrUsageZ [] PROGMEM = "Z";
-const char pstrUsageRx [] PROGMEM = "Rx";
-const char pstrUsageRy [] PROGMEM = "Ry";
-const char pstrUsageRz [] PROGMEM = "Rz";
-const char pstrUsageSlider [] PROGMEM = "Slider";
-const char pstrUsageDial [] PROGMEM = "Dial";
-const char pstrUsageWheel [] PROGMEM = "Wheel";
-const char pstrUsageHatSwitch [] PROGMEM = "Hat Switch";
-const char pstrUsageCountedBuffer [] PROGMEM = "Counted Buf";
-const char pstrUsageByteCount [] PROGMEM = "Byte Count";
-const char pstrUsageMotionWakeup [] PROGMEM = "Motion Wakeup";
-const char pstrUsageStart [] PROGMEM = "Start";
-const char pstrUsageSelect [] PROGMEM = "Sel";
-const char pstrUsageVx [] PROGMEM = "Vx";
-const char pstrUsageVy [] PROGMEM = "Vy";
-const char pstrUsageVz [] PROGMEM = "Vz";
-const char pstrUsageVbrx [] PROGMEM = "Vbrx";
-const char pstrUsageVbry [] PROGMEM = "Vbry";
-const char pstrUsageVbrz [] PROGMEM = "Vbrz";
-const char pstrUsageVno [] PROGMEM = "Vno";
-const char pstrUsageFeatureNotification [] PROGMEM = "Feature Notif";
-const char pstrUsageResolutionMultiplier [] PROGMEM = "Res Mult";
-const char pstrUsageSystemControl [] PROGMEM = "Sys Ctrl";
-const char pstrUsageSystemPowerDown [] PROGMEM = "Sys Pwr Down";
-const char pstrUsageSystemSleep [] PROGMEM = "Sys Sleep";
-const char pstrUsageSystemWakeup [] PROGMEM = "Sys Wakeup";
-const char pstrUsageSystemContextMenu [] PROGMEM = "Sys Context Menu";
-const char pstrUsageSystemMainMenu [] PROGMEM = "Sys Main Menu";
-const char pstrUsageSystemAppMenu [] PROGMEM = "Sys App Menu";
-const char pstrUsageSystemMenuHelp [] PROGMEM = "Sys Menu Help";
-const char pstrUsageSystemMenuExit [] PROGMEM = "Sys Menu Exit";
-const char pstrUsageSystemMenuSelect [] PROGMEM = "Sys Menu Select";
-const char pstrUsageSystemMenuRight [] PROGMEM = "Sys Menu Right";
-const char pstrUsageSystemMenuLeft [] PROGMEM = "Sys Menu Left";
-const char pstrUsageSystemMenuUp [] PROGMEM = "Sys Menu Up";
-const char pstrUsageSystemMenuDown [] PROGMEM = "Sys Menu Down";
-const char pstrUsageSystemColdRestart [] PROGMEM = "Sys Cold Restart";
-const char pstrUsageSystemWarmRestart [] PROGMEM = "Sys Warm Restart";
-const char pstrUsageDPadUp [] PROGMEM = "D-pad Up";
-const char pstrUsageDPadDown [] PROGMEM = "D-pad Down";
-const char pstrUsageDPadRight [] PROGMEM = "D-pad Right";
-const char pstrUsageDPadLeft [] PROGMEM = "D-pad Left";
-const char pstrUsageSystemDock [] PROGMEM = "Sys Dock";
-const char pstrUsageSystemUndock [] PROGMEM = "Sys Undock";
-const char pstrUsageSystemSetup [] PROGMEM = "Sys Setup";
-const char pstrUsageSystemBreak [] PROGMEM = "Sys Break";
-const char pstrUsageSystemDebuggerBreak [] PROGMEM = "Sys Dbg Brk";
-const char pstrUsageApplicationBreak [] PROGMEM = "App Break";
-const char pstrUsageApplicationDebuggerBreak [] PROGMEM = "App Dbg Brk";
-const char pstrUsageSystemSpeakerMute [] PROGMEM = "Sys Spk Mute";
-const char pstrUsageSystemHibernate [] PROGMEM = "Sys Hiber";
-const char pstrUsageSystemDisplayInvert [] PROGMEM = "Sys Disp Inv";
-const char pstrUsageSystemDisplayInternal [] PROGMEM = "Sys Disp Int";
-const char pstrUsageSystemDisplayExternal [] PROGMEM = "Sys Disp Ext";
-const char pstrUsageSystemDisplayBoth [] PROGMEM = "Sys Disp Both";
-const char pstrUsageSystemDisplayDual [] PROGMEM = "Sys Disp Dual";
-const char pstrUsageSystemDisplayToggleIntExt [] PROGMEM = "Sys Disp Tgl Int/Ext";
-const char pstrUsageSystemDisplaySwapPriSec [] PROGMEM = "Sys Disp Swap Pri/Sec";
-const char pstrUsageSystemDisplayLCDAutoscale [] PROGMEM = "Sys Disp LCD Autoscale";
-
-// Simulation Controls Page
-const char pstrUsageFlightSimulationDevice [] PROGMEM = "Flight Simu Dev";
-const char pstrUsageAutomobileSimulationDevice [] PROGMEM = "Auto Simu Dev";
-const char pstrUsageTankSimulationDevice [] PROGMEM = "Tank Simu Dev";
-const char pstrUsageSpaceshipSimulationDevice [] PROGMEM = "Space Simu Dev";
-const char pstrUsageSubmarineSimulationDevice [] PROGMEM = "Subm Simu Dev";
-const char pstrUsageSailingSimulationDevice [] PROGMEM = "Sail Simu Dev";
-const char pstrUsageMotocicleSimulationDevice [] PROGMEM = "Moto Simu Dev";
-const char pstrUsageSportsSimulationDevice [] PROGMEM = "Sport Simu Dev";
-const char pstrUsageAirplaneSimulationDevice [] PROGMEM = "Airp Simu Dev";
-const char pstrUsageHelicopterSimulationDevice [] PROGMEM = "Heli Simu Dev";
-const char pstrUsageMagicCarpetSimulationDevice [] PROGMEM = "Magic Carpet Simu Dev";
-const char pstrUsageBicycleSimulationDevice [] PROGMEM = "Bike Simu Dev";
-const char pstrUsageFlightControlStick [] PROGMEM = "Flight Ctrl Stick";
-const char pstrUsageFlightStick [] PROGMEM = "Flight Stick";
-const char pstrUsageCyclicControl [] PROGMEM = "Cyclic Ctrl";
-const char pstrUsageCyclicTrim [] PROGMEM = "Cyclic Trim";
-const char pstrUsageFlightYoke [] PROGMEM = "Flight Yoke";
-const char pstrUsageTrackControl [] PROGMEM = "Track Ctrl";
-const char pstrUsageAileron [] PROGMEM = "Aileron";
-const char pstrUsageAileronTrim [] PROGMEM = "Aileron Trim";
-const char pstrUsageAntiTorqueControl [] PROGMEM = "Anti-Torque Ctrl";
-const char pstrUsageAutopilotEnable [] PROGMEM = "Autopilot Enable";
-const char pstrUsageChaffRelease [] PROGMEM = "Chaff Release";
-const char pstrUsageCollectiveControl [] PROGMEM = "Collective Ctrl";
-const char pstrUsageDiveBrake [] PROGMEM = "Dive Brake";
-const char pstrUsageElectronicCountermeasures [] PROGMEM = "El Countermeasures";
-const char pstrUsageElevator [] PROGMEM = "Elevator";
-const char pstrUsageElevatorTrim [] PROGMEM = "Elevator Trim";
-const char pstrUsageRudder [] PROGMEM = "Rudder";
-const char pstrUsageThrottle [] PROGMEM = "Throttle";
-const char pstrUsageFlightCommunications [] PROGMEM = "Flight Comm";
-const char pstrUsageFlareRelease [] PROGMEM = "Flare Release";
-const char pstrUsageLandingGear [] PROGMEM = "Landing Gear";
-const char pstrUsageToeBrake [] PROGMEM = "Toe Brake";
-const char pstrUsageTrigger [] PROGMEM = "Trigger";
-const char pstrUsageWeaponsArm [] PROGMEM = "Weapons Arm";
-const char pstrUsageWeaponsSelect [] PROGMEM = "Weapons Sel";
-const char pstrUsageWingFlaps [] PROGMEM = "Wing Flaps";
-const char pstrUsageAccelerator [] PROGMEM = "Accel";
-const char pstrUsageBrake [] PROGMEM = "Brake";
-const char pstrUsageClutch [] PROGMEM = "Clutch";
-const char pstrUsageShifter [] PROGMEM = "Shifter";
-const char pstrUsageSteering [] PROGMEM = "Steering";
-const char pstrUsageTurretDirection [] PROGMEM = "Turret Dir";
-const char pstrUsageBarrelElevation [] PROGMEM = "Barrel Ele";
-const char pstrUsageDivePlane [] PROGMEM = "Dive Plane";
-const char pstrUsageBallast [] PROGMEM = "Ballast";
-const char pstrUsageBicycleCrank [] PROGMEM = "Bicycle Crank";
-const char pstrUsageHandleBars [] PROGMEM = "Handle Bars";
-const char pstrUsageFrontBrake [] PROGMEM = "Front Brake";
-const char pstrUsageRearBrake [] PROGMEM = "Rear Brake";
-
-// VR Controls Page
-const char pstrUsageBelt [] PROGMEM = "Belt";
-const char pstrUsageBodySuit [] PROGMEM = "Body Suit";
-const char pstrUsageFlexor [] PROGMEM = "Flexor";
-const char pstrUsageGlove [] PROGMEM = "Glove";
-const char pstrUsageHeadTracker [] PROGMEM = "Head Track";
-const char pstrUsageHeadMountedDisplay [] PROGMEM = "Head Disp";
-const char pstrUsageHandTracker [] PROGMEM = "Hand Track";
-const char pstrUsageOculometer [] PROGMEM = "Oculometer";
-const char pstrUsageVest [] PROGMEM = "Vest";
-const char pstrUsageAnimatronicDevice [] PROGMEM = "Animat Dev";
-const char pstrUsageStereoEnable [] PROGMEM = "Stereo Enbl";
-const char pstrUsageDisplayEnable [] PROGMEM = "Display Enbl";
-
-// Sport Controls Page
-const char pstrUsageBaseballBat [] PROGMEM = "Baseball Bat";
-const char pstrUsageGolfClub [] PROGMEM = "Golf Club";
-const char pstrUsageRowingMachine [] PROGMEM = "Rowing Mach";
-const char pstrUsageTreadmill [] PROGMEM = "Treadmill";
-const char pstrUsageOar [] PROGMEM = "Oar";
-const char pstrUsageSlope [] PROGMEM = "Slope";
-const char pstrUsageRate [] PROGMEM = "Rate";
-const char pstrUsageStickSpeed [] PROGMEM = "Stick Speed";
-const char pstrUsageStickFaceAngle [] PROGMEM = "Stick Face Ang";
-const char pstrUsageStickHeelToe [] PROGMEM = "Stick Heel/Toe";
-const char pstrUsageStickFollowThough [] PROGMEM = "Stick Flw Thru";
-const char pstrUsageStickTempo [] PROGMEM = "Stick Tempo";
-const char pstrUsageStickType [] PROGMEM = "Stick Type";
-const char pstrUsageStickHeight [] PROGMEM = "Stick Hght";
-const char pstrUsagePutter [] PROGMEM = "Putter";
-const char pstrUsage1Iron [] PROGMEM = "1 Iron";
-const char pstrUsage2Iron [] PROGMEM = "2 Iron";
-const char pstrUsage3Iron [] PROGMEM = "3 Iron";
-const char pstrUsage4Iron [] PROGMEM = "4 Iron";
-const char pstrUsage5Iron [] PROGMEM = "5 Iron";
-const char pstrUsage6Iron [] PROGMEM = "6 Iron";
-const char pstrUsage7Iron [] PROGMEM = "7 Iron";
-const char pstrUsage8Iron [] PROGMEM = "8 Iron";
-const char pstrUsage9Iron [] PROGMEM = "9 Iron";
-const char pstrUsage10Iron [] PROGMEM = "10 Iron";
-const char pstrUsage11Iron [] PROGMEM = "11 Iron";
-const char pstrUsageSandWedge [] PROGMEM = "Sand Wedge";
-const char pstrUsageLoftWedge [] PROGMEM = "Loft Wedge";
-const char pstrUsagePowerWedge [] PROGMEM = "Pwr Wedge";
-const char pstrUsage1Wood [] PROGMEM = "1 Wood";
-const char pstrUsage3Wood [] PROGMEM = "3 Wood";
-const char pstrUsage5Wood [] PROGMEM = "5 Wood";
-const char pstrUsage7Wood [] PROGMEM = "7 Wood";
-const char pstrUsage9Wood [] PROGMEM = "9 Wood";
-
-// Game Controls Page
-const char pstrUsage3DGameController [] PROGMEM = "3D Game Ctrl";
-const char pstrUsagePinballDevice [] PROGMEM = "Pinball Dev";
-const char pstrUsageGunDevice [] PROGMEM = "Gun Dev";
-const char pstrUsagePointOfView [] PROGMEM = "POV";
-const char pstrUsageTurnRightLeft [] PROGMEM = "Turn Right Left";
-const char pstrUsagePitchForwardBackward [] PROGMEM = "Pitch Fwd/Back";
-const char pstrUsageRollRightLeft [] PROGMEM = "Roll Right/Left";
-const char pstrUsageMoveRightLeft [] PROGMEM = "Move Right/Left";
-const char pstrUsageMoveForwardBackward [] PROGMEM = "Move Fwd/Back";
-const char pstrUsageMoveUpDown [] PROGMEM = "Move Up/Down";
-const char pstrUsageLeanRightLeft [] PROGMEM = "Lean Right/Left";
-const char pstrUsageLeanForwardBackward [] PROGMEM = "Lean Fwd/Back";
-const char pstrUsageHeightOfPOV [] PROGMEM = "Height of POV";
-const char pstrUsageFlipper [] PROGMEM = "Flipper";
-const char pstrUsageSecondaryFlipper [] PROGMEM = "Second Flipper";
-const char pstrUsageBump [] PROGMEM = "Bump";
-const char pstrUsageNewGame [] PROGMEM = "New Game";
-const char pstrUsageShootBall [] PROGMEM = "Shoot Ball";
-const char pstrUsagePlayer [] PROGMEM = "Player";
-const char pstrUsageGunBolt [] PROGMEM = "Gun Bolt";
-const char pstrUsageGunClip [] PROGMEM = "Gun Clip";
-const char pstrUsageGunSelector [] PROGMEM = "Gun Sel";
-const char pstrUsageGunSingleShot [] PROGMEM = "Gun Sngl Shot";
-const char pstrUsageGunBurst [] PROGMEM = "Gun Burst";
-const char pstrUsageGunAutomatic [] PROGMEM = "Gun Auto";
-const char pstrUsageGunSafety [] PROGMEM = "Gun Safety";
-const char pstrUsageGamepadFireJump [] PROGMEM = "Gamepad Fire/Jump";
-const char pstrUsageGamepadTrigger [] PROGMEM = "Gamepad Trig";
-
-// Generic Device Controls Page
-const char pstrUsageBatteryStrength [] PROGMEM = "Bat Strength";
-const char pstrUsageWirelessChannel [] PROGMEM = "Wireless Ch";
-const char pstrUsageWirelessID [] PROGMEM = "Wireless ID";
-const char pstrUsageDiscoverWirelessControl [] PROGMEM = "Discover Wireless Ctrl";
-const char pstrUsageSecurityCodeCharEntered [] PROGMEM = "Sec Code Char Entrd";
-const char pstrUsageSecurityCodeCharErased [] PROGMEM = "Sec Code Char Erased";
-const char pstrUsageSecurityCodeCleared [] PROGMEM = "Sec Code Cleared";
-
-// LED Page
-const char pstrUsageNumLock [] PROGMEM = "Num Lock";
-const char pstrUsageCapsLock [] PROGMEM = "Caps Lock";
-const char pstrUsageScrollLock [] PROGMEM = "Scroll Lock";
-const char pstrUsageCompose [] PROGMEM = "Compose";
-const char pstrUsageKana [] PROGMEM = "Kana";
-const char pstrUsagePower [] PROGMEM = "Pwr";
-const char pstrUsageShift [] PROGMEM = "Shift";
-const char pstrUsageDoNotDisturb [] PROGMEM = "DND";
-const char pstrUsageMute [] PROGMEM = "Mute";
-const char pstrUsageToneEnable [] PROGMEM = "Tone Enbl";
-const char pstrUsageHighCutFilter [] PROGMEM = "High Cut Fltr";
-const char pstrUsageLowCutFilter [] PROGMEM = "Low Cut Fltr";
-const char pstrUsageEqualizerEnable [] PROGMEM = "Eq Enbl";
-const char pstrUsageSoundFieldOn [] PROGMEM = "Sound Field On";
-const char pstrUsageSurroundOn [] PROGMEM = "Surround On";
-const char pstrUsageRepeat [] PROGMEM = "Repeat";
-const char pstrUsageStereo [] PROGMEM = "Stereo";
-const char pstrUsageSamplingRateDetect [] PROGMEM = "Smpl Rate Detect";
-const char pstrUsageSpinning [] PROGMEM = "Spinning";
-const char pstrUsageCAV [] PROGMEM = "CAV";
-const char pstrUsageCLV [] PROGMEM = "CLV";
-const char pstrUsageRecordingFormatDetect [] PROGMEM = "Rec Format Detect";
-const char pstrUsageOffHook [] PROGMEM = "Off Hook";
-const char pstrUsageRing [] PROGMEM = "Ring";
-const char pstrUsageMessageWaiting [] PROGMEM = "Msg Wait";
-const char pstrUsageDataMode [] PROGMEM = "Data Mode";
-const char pstrUsageBatteryOperation [] PROGMEM = "Bat Op";
-const char pstrUsageBatteryOK [] PROGMEM = "Bat OK";
-const char pstrUsageBatteryLow [] PROGMEM = "Bat Low";
-const char pstrUsageSpeaker [] PROGMEM = "Speaker";
-const char pstrUsageHeadSet [] PROGMEM = "Head Set";
-const char pstrUsageHold [] PROGMEM = "Hold";
-const char pstrUsageMicrophone [] PROGMEM = "Mic";
-const char pstrUsageCoverage [] PROGMEM = "Coverage";
-const char pstrUsageNightMode [] PROGMEM = "Night Mode";
-const char pstrUsageSendCalls [] PROGMEM = "Send Calls";
-const char pstrUsageCallPickup [] PROGMEM = "Call Pickup";
-const char pstrUsageConference [] PROGMEM = "Conf";
-const char pstrUsageStandBy [] PROGMEM = "Stand-by";
-const char pstrUsageCameraOn [] PROGMEM = "Cam On";
-const char pstrUsageCameraOff [] PROGMEM = "Cam Off";
-const char pstrUsageOnLine [] PROGMEM = "On-Line";
-const char pstrUsageOffLine [] PROGMEM = "Off-Line";
-const char pstrUsageBusy [] PROGMEM = "Busy";
-const char pstrUsageReady [] PROGMEM = "Ready";
-const char pstrUsagePaperOut [] PROGMEM = "Paper Out";
-const char pstrUsagePaperJam [] PROGMEM = "Paper Jam";
-const char pstrUsageRemote [] PROGMEM = "Remote";
-const char pstrUsageForward [] PROGMEM = "Fwd";
-const char pstrUsageReverse [] PROGMEM = "Rev";
-const char pstrUsageStop [] PROGMEM = "Stop";
-const char pstrUsageRewind [] PROGMEM = "Rewind";
-const char pstrUsageFastForward [] PROGMEM = "Fast Fwd";
-const char pstrUsagePlay [] PROGMEM = "Play";
-const char pstrUsagePause [] PROGMEM = "Pause";
-const char pstrUsageRecord [] PROGMEM = "Rec";
-const char pstrUsageError [] PROGMEM = "Error";
-const char pstrUsageSelectedIndicator [] PROGMEM = "Usage Sel Ind";
-const char pstrUsageInUseIndicator [] PROGMEM = "Usage In Use Ind";
-const char pstrUsageMultiModeIndicator [] PROGMEM = "Usage Multi Mode Ind";
-const char pstrUsageIndicatorOn [] PROGMEM = "Ind On";
-const char pstrUsageIndicatorFlash [] PROGMEM = "Ind Flash";
-const char pstrUsageIndicatorSlowBlink [] PROGMEM = "Ind Slow Blk";
-const char pstrUsageIndicatorFastBlink [] PROGMEM = "Ind Fast Blk";
-const char pstrUsageIndicatorOff [] PROGMEM = "Ind Off";
-const char pstrUsageFlashOnTime [] PROGMEM = "Flash On Time";
-const char pstrUsageSlowBlinkOnTime [] PROGMEM = "Slow Blk On Time";
-const char pstrUsageSlowBlinkOffTime [] PROGMEM = "Slow Blk Off Time";
-const char pstrUsageFastBlinkOnTime [] PROGMEM = "Fast Blk On Time";
-const char pstrUsageFastBlinkOffTime [] PROGMEM = "Fast Blk Off Time";
-const char pstrUsageIndicatorColor [] PROGMEM = "Usage Ind Color";
-const char pstrUsageIndicatorRed [] PROGMEM = "Ind Red";
-const char pstrUsageIndicatorGreen [] PROGMEM = "Ind Green";
-const char pstrUsageIndicatorAmber [] PROGMEM = "Ind Amber";
-const char pstrUsageGenericIndicator [] PROGMEM = "Gen Ind";
-const char pstrUsageSystemSuspend [] PROGMEM = "Sys Suspend";
-const char pstrUsageExternalPowerConnected [] PROGMEM = "Ext Pwr Conn";
-
-// Telephony Usage Page
-const char pstrUsagePhone [] PROGMEM = "Phone";
-const char pstrUsageAnsweringMachine [] PROGMEM = "Answ Mach";
-const char pstrUsageMessageControls [] PROGMEM = "Msg Ctrls";
-const char pstrUsageHandset [] PROGMEM = "Handset";
-const char pstrUsageHeadset [] PROGMEM = "Headset";
-const char pstrUsageTelephonyKeyPad [] PROGMEM = "Tel Key Pad";
-const char pstrUsageProgrammableButton [] PROGMEM = "Prog Button";
-const char pstrUsageHookSwitch [] PROGMEM = "Hook Sw";
-const char pstrUsageFlash [] PROGMEM = "Flash";
-const char pstrUsageFeature [] PROGMEM = "Feature";
-//const char pstrUsageHold [] PROGMEM = "Hold";
-const char pstrUsageRedial [] PROGMEM = "Redial";
-const char pstrUsageTransfer [] PROGMEM = "Transfer";
-const char pstrUsageDrop [] PROGMEM = "Drop";
-const char pstrUsagePark [] PROGMEM = "Park";
-const char pstrUsageForwardCalls [] PROGMEM = "Fwd Calls";
-const char pstrUsageAlternateFunction [] PROGMEM = "Alt Func";
-const char pstrUsageLine [] PROGMEM = "Line";
-const char pstrUsageSpeakerPhone [] PROGMEM = "Spk Phone";
-//const char pstrUsageConference [] PROGMEM = "Conference";
-const char pstrUsageRingEnable [] PROGMEM = "Ring Enbl";
-const char pstrUsageRingSelect [] PROGMEM = "Ring Sel";
-const char pstrUsagePhoneMute [] PROGMEM = "Phone Mute";
-const char pstrUsageCallerID [] PROGMEM = "Caller ID";
-const char pstrUsageSend [] PROGMEM = "Send";
-const char pstrUsageSpeedDial [] PROGMEM = "Speed Dial";
-const char pstrUsageStoreNumber [] PROGMEM = "Store Num";
-const char pstrUsageRecallNumber [] PROGMEM = "Recall Num";
-const char pstrUsagePhoneDirectory [] PROGMEM = "Phone Dir";
-const char pstrUsageVoiceMail [] PROGMEM = "Voice Mail";
-const char pstrUsageScreenCalls [] PROGMEM = "Screen Calls";
-//const char pstrUsageDoNotDisturb [] PROGMEM = "Do Not Disturb";
-const char pstrUsageMessage [] PROGMEM = "Msg";
-const char pstrUsageAnswerOnOff [] PROGMEM = "Answer On/Off";
-const char pstrUsageInsideDialTone [] PROGMEM = "Inside Dial Tone";
-const char pstrUsageOutsideDialTone [] PROGMEM = "Outside Dial Tone";
-const char pstrUsageInsideRingTone [] PROGMEM = "Inside Ring Tone";
-const char pstrUsageOutsideRingTone [] PROGMEM = "Outside Ring Tone";
-const char pstrUsagePriorityRingTone [] PROGMEM = "Prior Ring Tone";
-const char pstrUsageInsideRingback [] PROGMEM = "Inside Ringback";
-const char pstrUsagePriorityRingback [] PROGMEM = "Priority Ringback";
-const char pstrUsageLineBusyTone [] PROGMEM = "Ln Busy Tone";
-const char pstrUsageReorderTone [] PROGMEM = "Reorder Tone";
-const char pstrUsageCallWaitingTone [] PROGMEM = "Call Wait Tone";
-const char pstrUsageConfirmationTone1 [] PROGMEM = "Cnfrm Tone1";
-const char pstrUsageConfirmationTone2 [] PROGMEM = "Cnfrm Tone2";
-const char pstrUsageTonesOff [] PROGMEM = "Tones Off";
-const char pstrUsageOutsideRingback [] PROGMEM = "Outside Ringback";
-const char pstrUsageRinger [] PROGMEM = "Ringer";
-const char pstrUsagePhoneKey0 [] PROGMEM = "0";
-const char pstrUsagePhoneKey1 [] PROGMEM = "1";
-const char pstrUsagePhoneKey2 [] PROGMEM = "2";
-const char pstrUsagePhoneKey3 [] PROGMEM = "3";
-const char pstrUsagePhoneKey4 [] PROGMEM = "4";
-const char pstrUsagePhoneKey5 [] PROGMEM = "5";
-const char pstrUsagePhoneKey6 [] PROGMEM = "6";
-const char pstrUsagePhoneKey7 [] PROGMEM = "7";
-const char pstrUsagePhoneKey8 [] PROGMEM = "8";
-const char pstrUsagePhoneKey9 [] PROGMEM = "9";
-const char pstrUsagePhoneKeyStar [] PROGMEM = "*";
-const char pstrUsagePhoneKeyPound [] PROGMEM = "#";
-const char pstrUsagePhoneKeyA [] PROGMEM = "A";
-const char pstrUsagePhoneKeyB [] PROGMEM = "B";
-const char pstrUsagePhoneKeyC [] PROGMEM = "C";
-const char pstrUsagePhoneKeyD [] PROGMEM = "D";
-
-// Consumer Usage Page
-const char pstrUsageConsumerControl [] PROGMEM = "Consumer Ctrl";
-const char pstrUsageNumericKeyPad [] PROGMEM = "Num Key Pad";
-//const char pstrUsageProgrammableButton [] PROGMEM = "Prog Btn";
-//const char pstrUsageMicrophone [] PROGMEM = "Mic";
-const char pstrUsageHeadphone [] PROGMEM = "Headphone";
-const char pstrUsageGraphicEqualizer [] PROGMEM = "Graph Eq";
-const char pstrUsagePlus10 [] PROGMEM = "+10";
-const char pstrUsagePlus100 [] PROGMEM = "+100";
-const char pstrUsageAMPM [] PROGMEM = "AM/PM";
-//const char pstrUsagePower [] PROGMEM = "Pwr";
-const char pstrUsageReset [] PROGMEM = "Reset";
-const char pstrUsageSleep [] PROGMEM = "Sleep";
-const char pstrUsageSleepAfter [] PROGMEM = "Sleep After";
-const char pstrUsageSleepMode [] PROGMEM = "Sleep Mode";
-const char pstrUsageIllumination [] PROGMEM = "Illumin";
-const char pstrUsageFunctionButtons [] PROGMEM = "Func Btns";
-const char pstrUsageMenu [] PROGMEM = "Menu";
-const char pstrUsageMenuPick [] PROGMEM = "Menu Pick";
-const char pstrUsageMenuUp [] PROGMEM = "Menu Up";
-const char pstrUsageMenuDown [] PROGMEM = "Menu Down";
-const char pstrUsageMenuLeft [] PROGMEM = "Menu Left";
-const char pstrUsageMenuRight [] PROGMEM = "Menu Right";
-const char pstrUsageMenuEscape [] PROGMEM = "Menu Esc";
-const char pstrUsageMenuValueIncrease [] PROGMEM = "Menu Val Inc";
-const char pstrUsageMenuValueDecrease [] PROGMEM = "Menu Val Dec";
-const char pstrUsageDataOnScreen [] PROGMEM = "Data On Scr";
-const char pstrUsageClosedCaption [] PROGMEM = "Closed Cptn";
-const char pstrUsageClosedCaptionSelect [] PROGMEM = "Closed Cptn Sel";
-const char pstrUsageVCRTV [] PROGMEM = "VCR/TV";
-const char pstrUsageBroadcastMode [] PROGMEM = "Brdcast Mode";
-const char pstrUsageSnapshot [] PROGMEM = "Snapshot";
-const char pstrUsageStill [] PROGMEM = "Still";
-const char pstrUsageSelection [] PROGMEM = "Sel";
-const char pstrUsageAssignSelection [] PROGMEM = "Assign Sel";
-const char pstrUsageModeStep [] PROGMEM = "Mode Step";
-const char pstrUsageRecallLast [] PROGMEM = "Recall Last";
-const char pstrUsageEnterChannel [] PROGMEM = "Entr Channel";
-const char pstrUsageOrderMovie [] PROGMEM = "Ord Movie";
-const char pstrUsageChannel [] PROGMEM = "Channel";
-const char pstrUsageMediaSelection [] PROGMEM = "Med Sel";
-const char pstrUsageMediaSelectComputer [] PROGMEM = "Med Sel Comp";
-const char pstrUsageMediaSelectTV [] PROGMEM = "Med Sel TV";
-const char pstrUsageMediaSelectWWW [] PROGMEM = "Med Sel WWW";
-const char pstrUsageMediaSelectDVD [] PROGMEM = "Med Sel DVD";
-const char pstrUsageMediaSelectTelephone [] PROGMEM = "Med Sel Tel";
-const char pstrUsageMediaSelectProgramGuide [] PROGMEM = "Med Sel PG";
-const char pstrUsageMediaSelectVideoPhone [] PROGMEM = "Med Sel Vid";
-const char pstrUsageMediaSelectGames [] PROGMEM = "Med Sel Games";
-const char pstrUsageMediaSelectMessages [] PROGMEM = "Med Sel Msg";
-const char pstrUsageMediaSelectCD [] PROGMEM = "Med Sel CD";
-const char pstrUsageMediaSelectVCR [] PROGMEM = "Med Sel VCR";
-const char pstrUsageMediaSelectTuner [] PROGMEM = "Med Sel Tuner";
-const char pstrUsageQuit [] PROGMEM = "Quit";
-const char pstrUsageHelp [] PROGMEM = "Help";
-const char pstrUsageMediaSelectTape [] PROGMEM = "Med Sel Tape";
-const char pstrUsageMediaSelectCable [] PROGMEM = "Med Sel Cbl";
-const char pstrUsageMediaSelectSatellite [] PROGMEM = "Med Sel Sat";
-const char pstrUsageMediaSelectSecurity [] PROGMEM = "Med Sel Secur";
-const char pstrUsageMediaSelectHome [] PROGMEM = "Med Sel Home";
-const char pstrUsageMediaSelectCall [] PROGMEM = "Med Sel Call";
-const char pstrUsageChannelIncrement [] PROGMEM = "Ch Inc";
-const char pstrUsageChannelDecrement [] PROGMEM = "Ch Dec";
-const char pstrUsageMediaSelectSAP [] PROGMEM = "Med Sel SAP";
-const char pstrUsageVCRPlus [] PROGMEM = "VCR+";
-const char pstrUsageOnce [] PROGMEM = "Once";
-const char pstrUsageDaily [] PROGMEM = "Daily";
-const char pstrUsageWeekly [] PROGMEM = "Weekly";
-const char pstrUsageMonthly [] PROGMEM = "Monthly";
-//const char pstrUsagePlay [] PROGMEM = "Play";
-//const char pstrUsagePause [] PROGMEM = "Pause";
-//const char pstrUsageRecord [] PROGMEM = "Rec";
-//const char pstrUsageFastForward [] PROGMEM = "FF";
-//const char pstrUsageRewind [] PROGMEM = "Rewind";
-const char pstrUsageScanNextTrack [] PROGMEM = "Next Track";
-const char pstrUsageScanPreviousTrack [] PROGMEM = "Prev Track";
-//const char pstrUsageStop [] PROGMEM = "Stop";
-const char pstrUsageEject [] PROGMEM = "Eject";
-const char pstrUsageRandomPlay [] PROGMEM = "Random";
-const char pstrUsageSelectDisk [] PROGMEM = "Sel Disk";
-const char pstrUsageEnterDisk [] PROGMEM = "Ent Disk";
-//const char pstrUsageRepeat [] PROGMEM = "Repeat";
-const char pstrUsageTracking [] PROGMEM = "Tracking";
-const char pstrUsageTrackNormal [] PROGMEM = "Trk Norm";
-const char pstrUsageSlowTracking [] PROGMEM = "Slow Trk";
-const char pstrUsageFrameForward [] PROGMEM = "Frm Fwd";
-const char pstrUsageFrameBackwards [] PROGMEM = "Frm Back";
-const char pstrUsageMark [] PROGMEM = "Mark";
-const char pstrUsageClearMark [] PROGMEM = "Clr Mark";
-const char pstrUsageRepeatFromMark [] PROGMEM = "Rpt Mark";
-const char pstrUsageReturnToMark [] PROGMEM = "Ret to Mark";
-const char pstrUsageSearchMarkForward [] PROGMEM = "Search Mark Fwd";
-const char pstrUsageSearchMarkBackwards [] PROGMEM = "Search Mark Back";
-const char pstrUsageCounterReset [] PROGMEM = "Counter Reset";
-const char pstrUsageShowCounter [] PROGMEM = "Show Counter";
-const char pstrUsageTrackingIncrement [] PROGMEM = "Track Inc";
-const char pstrUsageTrackingDecrement [] PROGMEM = "Track Dec";
-const char pstrUsageStopEject [] PROGMEM = "Stop/Eject";
-const char pstrUsagePlayPause [] PROGMEM = "Play/Pause";
-const char pstrUsagePlaySkip [] PROGMEM = "Play/Skip";
-const char pstrUsageVolume [] PROGMEM = "Vol";
-const char pstrUsageBalance [] PROGMEM = "Balance";
-//const char pstrUsageMute [] PROGMEM = "Mute";
-const char pstrUsageBass [] PROGMEM = "Bass";
-const char pstrUsageTreble [] PROGMEM = "Treble";
-const char pstrUsageBassBoost [] PROGMEM = "Bass Boost";
-const char pstrUsageSurroundMode [] PROGMEM = "Surround";
-const char pstrUsageLoudness [] PROGMEM = "Loud";
-const char pstrUsageMPX [] PROGMEM = "MPX";
-const char pstrUsageVolumeIncrement [] PROGMEM = "Vol Inc";
-const char pstrUsageVolumeDecrement [] PROGMEM = "Vol Dec";
-const char pstrUsageSpeedSelect [] PROGMEM = "Speed";
-const char pstrUsagePlaybackSpeed [] PROGMEM = "Play Speed";
-const char pstrUsageStandardPlay [] PROGMEM = "Std Play";
-const char pstrUsageLongPlay [] PROGMEM = "Long Play";
-const char pstrUsageExtendedPlay [] PROGMEM = "Ext Play";
-const char pstrUsageSlow [] PROGMEM = "Slow";
-const char pstrUsageFanEnable [] PROGMEM = "Fan Enbl";
-const char pstrUsageFanSpeed [] PROGMEM = "Fan Speed";
-const char pstrUsageLightEnable [] PROGMEM = "Light Enbl";
-const char pstrUsageLightIlluminationLevel [] PROGMEM = "Light Illum Lev";
-const char pstrUsageClimateControlEnable [] PROGMEM = "Climate Enbl";
-const char pstrUsageRoomTemperature [] PROGMEM = "Room Temp";
-const char pstrUsageSecurityEnable [] PROGMEM = "Secur Enbl";
-const char pstrUsageFireAlarm [] PROGMEM = "Fire Alm";
-const char pstrUsagePoliceAlarm [] PROGMEM = "Police Alm";
-const char pstrUsageProximity [] PROGMEM = "Prox";
-const char pstrUsageMotion [] PROGMEM = "Motion";
-const char pstrUsageDuresAlarm [] PROGMEM = "Dures Alm";
-const char pstrUsageHoldupAlarm [] PROGMEM = "Holdup Alm";
-const char pstrUsageMedicalAlarm [] PROGMEM = "Med Alm";
-const char pstrUsageBalanceRight [] PROGMEM = "Balance Right";
-const char pstrUsageBalanceLeft [] PROGMEM = "Balance Left";
-const char pstrUsageBassIncrement [] PROGMEM = "Bass Inc";
-const char pstrUsageBassDecrement [] PROGMEM = "Bass Dec";
-const char pstrUsageTrebleIncrement [] PROGMEM = "Treble Inc";
-const char pstrUsageTrebleDecrement [] PROGMEM = "Treble Dec";
-const char pstrUsageSpeakerSystem [] PROGMEM = "Spk Sys";
-const char pstrUsageChannelLeft [] PROGMEM = "Ch Left";
-const char pstrUsageChannelRight [] PROGMEM = "Ch Right";
-const char pstrUsageChannelCenter [] PROGMEM = "Ch Center";
-const char pstrUsageChannelFront [] PROGMEM = "Ch Front";
-const char pstrUsageChannelCenterFront [] PROGMEM = "Ch Cntr Front";
-const char pstrUsageChannelSide [] PROGMEM = "Ch Side";
-const char pstrUsageChannelSurround [] PROGMEM = "Ch Surround";
-const char pstrUsageChannelLowFreqEnhancement [] PROGMEM = "Ch Low Freq Enh";
-const char pstrUsageChannelTop [] PROGMEM = "Ch Top";
-const char pstrUsageChannelUnknown [] PROGMEM = "Ch Unk";
-const char pstrUsageSubChannel [] PROGMEM = "Sub-ch";
-const char pstrUsageSubChannelIncrement [] PROGMEM = "Sub-ch Inc";
-const char pstrUsageSubChannelDecrement [] PROGMEM = "Sub-ch Dec";
-const char pstrUsageAlternateAudioIncrement [] PROGMEM = "Alt Aud Inc";
-const char pstrUsageAlternateAudioDecrement [] PROGMEM = "Alt Aud Dec";
-const char pstrUsageApplicationLaunchButtons [] PROGMEM = "App Launch Btns";
-const char pstrUsageALLaunchButtonConfigTool [] PROGMEM = "AL Launch Conf Tl";
-const char pstrUsageALProgrammableButton [] PROGMEM = "AL Pgm Btn";
-const char pstrUsageALConsumerControlConfig [] PROGMEM = "AL Cons Ctrl Cfg";
-const char pstrUsageALWordProcessor [] PROGMEM = "AL Word Proc";
-const char pstrUsageALTextEditor [] PROGMEM = "AL Txt Edtr";
-const char pstrUsageALSpreadsheet [] PROGMEM = "AL Sprdsheet";
-const char pstrUsageALGraphicsEditor [] PROGMEM = "AL Graph Edtr";
-const char pstrUsageALPresentationApp [] PROGMEM = "AL Present App";
-const char pstrUsageALDatabaseApp [] PROGMEM = "AL DB App";
-const char pstrUsageALEmailReader [] PROGMEM = "AL E-mail Rdr";
-const char pstrUsageALNewsreader [] PROGMEM = "AL Newsrdr";
-const char pstrUsageALVoicemail [] PROGMEM = "AL Voicemail";
-const char pstrUsageALContactsAddressBook [] PROGMEM = "AL Addr Book";
-const char pstrUsageALCalendarSchedule [] PROGMEM = "AL Clndr/Schdlr";
-const char pstrUsageALTaskProjectManager [] PROGMEM = "AL Task/Prj Mgr";
-const char pstrUsageALLogJournalTimecard [] PROGMEM = "AL Log/Jrnl/Tmcrd";
-const char pstrUsageALCheckbookFinance [] PROGMEM = "AL Chckbook/Fin";
-const char pstrUsageALCalculator [] PROGMEM = "AL Calc";
-const char pstrUsageALAVCapturePlayback [] PROGMEM = "AL A/V Capt/Play";
-const char pstrUsageALLocalMachineBrowser [] PROGMEM = "AL Loc Mach Brow";
-const char pstrUsageALLANWANBrow [] PROGMEM = "AL LAN/WAN Brow";
-const char pstrUsageALInternetBrowser [] PROGMEM = "AL I-net Brow";
-const char pstrUsageALRemoteNetISPConnect [] PROGMEM = "AL Rem Net Con";
-const char pstrUsageALNetworkConference [] PROGMEM = "AL Net Conf";
-const char pstrUsageALNetworkChat [] PROGMEM = "AL Net Chat";
-const char pstrUsageALTelephonyDialer [] PROGMEM = "AL Tel/Dial";
-const char pstrUsageALLogon [] PROGMEM = "AL Logon";
-const char pstrUsageALLogoff [] PROGMEM = "AL Logoff";
-const char pstrUsageALLogonLogoff [] PROGMEM = "AL Logon/Logoff";
-const char pstrUsageALTermLockScrSav [] PROGMEM = "AL Term Lock/Scr Sav";
-const char pstrUsageALControlPannel [] PROGMEM = "AL Ctrl Pan";
-const char pstrUsageALCommandLineProcessorRun [] PROGMEM = "AL Cmd/Run";
-const char pstrUsageALProcessTaskManager [] PROGMEM = "AL Task Mgr";
-const char pstrUsageALSelectTaskApplication [] PROGMEM = "AL Sel App";
-const char pstrUsageALNextTaskApplication [] PROGMEM = "AL Next App";
-const char pstrUsageALPreviousTaskApplication [] PROGMEM = "AL Prev App";
-const char pstrUsageALPreemptiveHaltTaskApp [] PROGMEM = "AL Prmpt Halt App";
-const char pstrUsageALIntegratedHelpCenter [] PROGMEM = "AL Hlp Cntr";
-const char pstrUsageALDocuments [] PROGMEM = "AL Docs";
-const char pstrUsageALThesaurus [] PROGMEM = "AL Thsrs";
-const char pstrUsageALDictionary [] PROGMEM = "AL Dict";
-const char pstrUsageALDesktop [] PROGMEM = "AL Desktop";
-const char pstrUsageALSpellCheck [] PROGMEM = "AL Spell Chk";
-const char pstrUsageALGrammarCheck [] PROGMEM = "AL Gram Chk";
-const char pstrUsageALWirelessStatus [] PROGMEM = "AL Wireless Sts";
-const char pstrUsageALKeyboardLayout [] PROGMEM = "AL Kbd Layout";
-const char pstrUsageALVirusProtection [] PROGMEM = "AL Vir Protect";
-const char pstrUsageALEncryption [] PROGMEM = "AL Encrypt";
-const char pstrUsageALScreenSaver [] PROGMEM = "AL Scr Sav";
-const char pstrUsageALAlarms [] PROGMEM = "AL Alarms";
-const char pstrUsageALClock [] PROGMEM = "AL Clock";
-const char pstrUsageALFileBrowser [] PROGMEM = "AL File Brow";
-const char pstrUsageALPowerStatus [] PROGMEM = "AL Pwr Sts";
-const char pstrUsageALImageBrowser [] PROGMEM = "AL Img Brow";
-const char pstrUsageALAudioBrowser [] PROGMEM = "AL Aud Brow";
-const char pstrUsageALMovieBrowser [] PROGMEM = "AL Mov Brow";
-const char pstrUsageALDigitalRightsManager [] PROGMEM = "AL Dig Rights Mgr";
-const char pstrUsageALDigitalWallet [] PROGMEM = "AL Dig Wallet";
-const char pstrUsageALInstantMessaging [] PROGMEM = "AL Inst Msg";
-const char pstrUsageALOEMFeaturesBrowser [] PROGMEM = "AL OEM Tips Brow";
-const char pstrUsageALOEMHelp [] PROGMEM = "AL OEM Hlp";
-const char pstrUsageALOnlineCommunity [] PROGMEM = "AL Online Com";
-const char pstrUsageALEntertainmentContentBrow [] PROGMEM = "AL Ent Cont Brow";
-const char pstrUsageALOnlineShoppingBrowser [] PROGMEM = "AL Online Shop Brow";
-const char pstrUsageALSmartCardInfoHelp [] PROGMEM = "AL SmartCard Inf";
-const char pstrUsageALMarketMonitorFinBrowser [] PROGMEM = "AL Market Brow";
-const char pstrUsageALCustomCorpNewsBrowser [] PROGMEM = "AL Cust Corp News Brow";
-const char pstrUsageALOnlineActivityBrowser [] PROGMEM = "AL Online Act Brow";
-const char pstrUsageALResearchSearchBrowser [] PROGMEM = "AL Search Brow";
-const char pstrUsageALAudioPlayer [] PROGMEM = "AL Aud Player";
-const char pstrUsageGenericGUIAppControls [] PROGMEM = "Gen GUI App Ctrl";
-const char pstrUsageACNew [] PROGMEM = "AC New";
-const char pstrUsageACOpen [] PROGMEM = "AC Open";
-const char pstrUsageACClose [] PROGMEM = "AC Close";
-const char pstrUsageACExit [] PROGMEM = "AC Exit";
-const char pstrUsageACMaximize [] PROGMEM = "AC Max";
-const char pstrUsageACMinimize [] PROGMEM = "AC Min";
-const char pstrUsageACSave [] PROGMEM = "AC Save";
-const char pstrUsageACPrint [] PROGMEM = "AC Print";
-const char pstrUsageACProperties [] PROGMEM = "AC Prop";
-const char pstrUsageACUndo [] PROGMEM = "AC Undo";
-const char pstrUsageACCopy [] PROGMEM = "AC Copy";
-const char pstrUsageACCut [] PROGMEM = "AC Cut";
-const char pstrUsageACPaste [] PROGMEM = "AC Paste";
-const char pstrUsageACSelectAll [] PROGMEM = "AC Sel All";
-const char pstrUsageACFind [] PROGMEM = "AC Find";
-const char pstrUsageACFindAndReplace [] PROGMEM = "AC Find/Replace";
-const char pstrUsageACSearch [] PROGMEM = "AC Search";
-const char pstrUsageACGoto [] PROGMEM = "AC Goto";
-const char pstrUsageACHome [] PROGMEM = "AC Home";
-const char pstrUsageACBack [] PROGMEM = "AC Back";
-const char pstrUsageACForward [] PROGMEM = "AC Fwd";
-const char pstrUsageACStop [] PROGMEM = "AC Stop";
-const char pstrUsageACRefresh [] PROGMEM = "AC Refresh";
-const char pstrUsageACPreviousLink [] PROGMEM = "AC Prev Link";
-const char pstrUsageACNextLink [] PROGMEM = "AC Next Link";
-const char pstrUsageACBookmarks [] PROGMEM = "AC Bkmarks";
-const char pstrUsageACHistory [] PROGMEM = "AC Hist";
-const char pstrUsageACSubscriptions [] PROGMEM = "AC Subscr";
-const char pstrUsageACZoomIn [] PROGMEM = "AC Zoom In";
-const char pstrUsageACZoomOut [] PROGMEM = "AC Zoom Out";
-const char pstrUsageACZoom [] PROGMEM = "AC Zoom";
-const char pstrUsageACFullScreenView [] PROGMEM = "AC Full Scr";
-const char pstrUsageACNormalView [] PROGMEM = "AC Norm View";
-const char pstrUsageACViewToggle [] PROGMEM = "AC View Tgl";
-const char pstrUsageACScrollUp [] PROGMEM = "AC Scroll Up";
-const char pstrUsageACScrollDown [] PROGMEM = "AC Scroll Down";
-const char pstrUsageACScroll [] PROGMEM = "AC Scroll";
-const char pstrUsageACPanLeft [] PROGMEM = "AC Pan Left";
-const char pstrUsageACPanRight [] PROGMEM = "AC Pan Right";
-const char pstrUsageACPan [] PROGMEM = "AC Pan";
-const char pstrUsageACNewWindow [] PROGMEM = "AC New Wnd";
-const char pstrUsageACTileHoriz [] PROGMEM = "AC Tile Horiz";
-const char pstrUsageACTileVert [] PROGMEM = "AC Tile Vert";
-const char pstrUsageACFormat [] PROGMEM = "AC Frmt";
-const char pstrUsageACEdit [] PROGMEM = "AC Edit";
-const char pstrUsageACBold [] PROGMEM = "AC Bold";
-const char pstrUsageACItalics [] PROGMEM = "AC Ital";
-const char pstrUsageACUnderline [] PROGMEM = "AC Under";
-const char pstrUsageACStrikethrough [] PROGMEM = "AC Strike";
-const char pstrUsageACSubscript [] PROGMEM = "AC Sub";
-const char pstrUsageACSuperscript [] PROGMEM = "AC Super";
-const char pstrUsageACAllCaps [] PROGMEM = "AC All Caps";
-const char pstrUsageACRotate [] PROGMEM = "AC Rotate";
-const char pstrUsageACResize [] PROGMEM = "AC Resize";
-const char pstrUsageACFlipHorizontal [] PROGMEM = "AC Flp H";
-const char pstrUsageACFlipVertical [] PROGMEM = "AC Flp V";
-const char pstrUsageACMirrorHorizontal [] PROGMEM = "AC Mir H";
-const char pstrUsageACMirrorVertical [] PROGMEM = "AC Mir V";
-const char pstrUsageACFontSelect [] PROGMEM = "AC Fnt Sel";
-const char pstrUsageACFontColor [] PROGMEM = "AC Fnt Clr";
-const char pstrUsageACFontSize [] PROGMEM = "AC Fnt Size";
-const char pstrUsageACJustifyLeft [] PROGMEM = "AC Just Left";
-const char pstrUsageACJustifyCenterH [] PROGMEM = "AC Just Cent H";
-const char pstrUsageACJustifyRight [] PROGMEM = "AC Just Right";
-const char pstrUsageACJustifyBlockH [] PROGMEM = "AC Just Block H";
-const char pstrUsageACJustifyTop [] PROGMEM = "AC Just Top";
-const char pstrUsageACJustifyCenterV [] PROGMEM = "AC Just Cent V";
-const char pstrUsageACJustifyBottom [] PROGMEM = "AC Just Bot";
-const char pstrUsageACJustifyBlockV [] PROGMEM = "AC Just Block V";
-const char pstrUsageACIndentDecrease [] PROGMEM = "AC Indent Dec";
-const char pstrUsageACIndentIncrease [] PROGMEM = "AC Indent Inc";
-const char pstrUsageACNumberedList [] PROGMEM = "AC Num List";
-const char pstrUsageACRestartNumbering [] PROGMEM = "AC Res Num";
-const char pstrUsageACBulletedList [] PROGMEM = "AC Blt List";
-const char pstrUsageACPromote [] PROGMEM = "AC Promote";
-const char pstrUsageACDemote [] PROGMEM = "AC Demote";
-const char pstrUsageACYes [] PROGMEM = "AC Yes";
-const char pstrUsageACNo [] PROGMEM = "AC No";
-const char pstrUsageACCancel [] PROGMEM = "AC Cancel";
-const char pstrUsageACCatalog [] PROGMEM = "AC Ctlg";
-const char pstrUsageACBuyChkout [] PROGMEM = "AC Buy";
-const char pstrUsageACAddToCart [] PROGMEM = "AC Add2Cart";
-const char pstrUsageACExpand [] PROGMEM = "AC Xpnd";
-const char pstrUsageACExpandAll [] PROGMEM = "AC Xpand All";
-const char pstrUsageACCollapse [] PROGMEM = "AC Collapse";
-const char pstrUsageACCollapseAll [] PROGMEM = "AC Collapse All";
-const char pstrUsageACPrintPreview [] PROGMEM = "AC Prn Prevw";
-const char pstrUsageACPasteSpecial [] PROGMEM = "AC Paste Spec";
-const char pstrUsageACInsertMode [] PROGMEM = "AC Ins Mode";
-const char pstrUsageACDelete [] PROGMEM = "AC Del";
-const char pstrUsageACLock [] PROGMEM = "AC Lock";
-const char pstrUsageACUnlock [] PROGMEM = "AC Unlock";
-const char pstrUsageACProtect [] PROGMEM = "AC Prot";
-const char pstrUsageACUnprotect [] PROGMEM = "AC Unprot";
-const char pstrUsageACAttachComment [] PROGMEM = "AC Attach Cmnt";
-const char pstrUsageACDeleteComment [] PROGMEM = "AC Del Cmnt";
-const char pstrUsageACViewComment [] PROGMEM = "AC View Cmnt";
-const char pstrUsageACSelectWord [] PROGMEM = "AC Sel Word";
-const char pstrUsageACSelectSentence [] PROGMEM = "AC Sel Sntc";
-const char pstrUsageACSelectParagraph [] PROGMEM = "AC Sel Para";
-const char pstrUsageACSelectColumn [] PROGMEM = "AC Sel Col";
-const char pstrUsageACSelectRow [] PROGMEM = "AC Sel Row";
-const char pstrUsageACSelectTable [] PROGMEM = "AC Sel Tbl";
-const char pstrUsageACSelectObject [] PROGMEM = "AC Sel Obj";
-const char pstrUsageACRedoRepeat [] PROGMEM = "AC Redo";
-const char pstrUsageACSort [] PROGMEM = "AC Sort";
-const char pstrUsageACSortAscending [] PROGMEM = "AC Sort Asc";
-const char pstrUsageACSortDescending [] PROGMEM = "AC Sort Desc";
-const char pstrUsageACFilter [] PROGMEM = "AC Filt";
-const char pstrUsageACSetClock [] PROGMEM = "AC Set Clk";
-const char pstrUsageACViewClock [] PROGMEM = "AC View Clk";
-const char pstrUsageACSelectTimeZone [] PROGMEM = "AC Sel Time Z";
-const char pstrUsageACEditTimeZone [] PROGMEM = "AC Edt Time Z";
-const char pstrUsageACSetAlarm [] PROGMEM = "AC Set Alm";
-const char pstrUsageACClearAlarm [] PROGMEM = "AC Clr Alm";
-const char pstrUsageACSnoozeAlarm [] PROGMEM = "AC Snz Alm";
-const char pstrUsageACResetAlarm [] PROGMEM = "AC Rst Alm";
-const char pstrUsageACSyncronize [] PROGMEM = "AC Sync";
-const char pstrUsageACSendReceive [] PROGMEM = "AC Snd/Rcv";
-const char pstrUsageACSendTo [] PROGMEM = "AC Snd To";
-const char pstrUsageACReply [] PROGMEM = "AC Reply";
-const char pstrUsageACReplyAll [] PROGMEM = "AC Reply All";
-const char pstrUsageACForwardMessage [] PROGMEM = "AC Fwd Msg";
-const char pstrUsageACSend [] PROGMEM = "AC Snd";
-const char pstrUsageACAttachFile [] PROGMEM = "AC Att File";
-const char pstrUsageACUpload [] PROGMEM = "AC Upld";
-const char pstrUsageACDownload [] PROGMEM = "AC Dnld";
-const char pstrUsageACSetBorders [] PROGMEM = "AC Set Brd";
-const char pstrUsageACInsertRow [] PROGMEM = "AC Ins Row";
-const char pstrUsageACInsertColumn [] PROGMEM = "AC Ins Col";
-const char pstrUsageACInsertFile [] PROGMEM = "AC Ins File";
-const char pstrUsageACInsertPicture [] PROGMEM = "AC Ins Pic";
-const char pstrUsageACInsertObject [] PROGMEM = "AC Ins Obj";
-const char pstrUsageACInsertSymbol [] PROGMEM = "AC Ins Sym";
-const char pstrUsageACSaveAndClose [] PROGMEM = "AC Sav&Cls";
-const char pstrUsageACRename [] PROGMEM = "AC Rename";
-const char pstrUsageACMerge [] PROGMEM = "AC Merge";
-const char pstrUsageACSplit [] PROGMEM = "AC Split";
-const char pstrUsageACDistributeHorizontaly [] PROGMEM = "AC Dist Hor";
-const char pstrUsageACDistributeVerticaly [] PROGMEM = "AC Dist Ver";
-
-// Digitaizers
-const char pstrUsageDigitizer [] PROGMEM = "Digitizer";
-const char pstrUsagePen [] PROGMEM = "Pen";
-const char pstrUsageLightPen [] PROGMEM = "Light Pen";
-const char pstrUsageTouchScreen [] PROGMEM = "Touch Scr";
-const char pstrUsageTouchPad [] PROGMEM = "Touch Pad";
-const char pstrUsageWhiteBoard [] PROGMEM = "White Brd";
-const char pstrUsageCoordinateMeasuringMachine [] PROGMEM = "Coord Meas Mach";
-const char pstrUsage3DDigitizer [] PROGMEM = "3D Dgtz";
-const char pstrUsageStereoPlotter [] PROGMEM = "Stereo Plot";
-const char pstrUsageArticulatedArm [] PROGMEM = "Art Arm";
-const char pstrUsageArmature [] PROGMEM = "Armature";
-const char pstrUsageMultiplePointDigitizer [] PROGMEM = "Multi Point Dgtz";
-const char pstrUsageFreeSpaceWand [] PROGMEM = "Free Space Wand";
-const char pstrUsageStylus [] PROGMEM = "Stylus";
-const char pstrUsagePuck [] PROGMEM = "Puck";
-const char pstrUsageFinger [] PROGMEM = "Finger";
-const char pstrUsageTipPressure [] PROGMEM = "Tip Press";
-const char pstrUsageBarrelPressure [] PROGMEM = "Brl Press";
-const char pstrUsageInRange [] PROGMEM = "In Range";
-const char pstrUsageTouch [] PROGMEM = "Touch";
-const char pstrUsageUntouch [] PROGMEM = "Untouch";
-const char pstrUsageTap [] PROGMEM = "Tap";
-const char pstrUsageQuality [] PROGMEM = "Qlty";
-const char pstrUsageDataValid [] PROGMEM = "Data Valid";
-const char pstrUsageTransducerIndex [] PROGMEM = "Transducer Ind";
-const char pstrUsageTabletFunctionKeys [] PROGMEM = "Tabl Func Keys";
-const char pstrUsageProgramChangeKeys [] PROGMEM = "Pgm Chng Keys";
-//const char pstrUsageBatteryStrength [] PROGMEM = "Bat Strength";
-const char pstrUsageInvert [] PROGMEM = "Invert";
-const char pstrUsageXTilt [] PROGMEM = "X Tilt";
-const char pstrUsageYTilt [] PROGMEM = "Y Tilt";
-const char pstrUsageAzimuth [] PROGMEM = "Azimuth";
-const char pstrUsageAltitude [] PROGMEM = "Altitude";
-const char pstrUsageTwist [] PROGMEM = "Twist";
-const char pstrUsageTipSwitch [] PROGMEM = "Tip Sw";
-const char pstrUsageSecondaryTipSwitch [] PROGMEM = "Scnd Tip Sw";
-const char pstrUsageBarrelSwitch [] PROGMEM = "Brl Sw";
-const char pstrUsageEraser [] PROGMEM = "Eraser";
-const char pstrUsageTabletPick [] PROGMEM = "Tbl Pick";
-
-// Alphanumeric Display Page
-const char pstrUsageAlphanumericDisplay [] PROGMEM = "Alphanum Disp";
-const char pstrUsageBitmappedDisplay [] PROGMEM = "Bmp Disp";
-const char pstrUsageDisplayAttributesReport [] PROGMEM = "Disp Attr Rpt";
-const char pstrUsageASCIICharacterSet [] PROGMEM = "ASCII chset";
-const char pstrUsageDataReadBack [] PROGMEM = "Data Rd Back";
-const char pstrUsageFontReadBack [] PROGMEM = "Fnt Rd Back";
-const char pstrUsageDisplayControlReport [] PROGMEM = "Disp Ctrl Rpt";
-const char pstrUsageClearDisplay [] PROGMEM = "Clr Disp";
-//const char pstrUsageDisplayEnable [] PROGMEM = "Disp Enbl";
-const char pstrUsageScreenSaverDelay [] PROGMEM = "Scr Sav Delay";
-const char pstrUsageScreenSaverEnable [] PROGMEM = "Scr Sav Enbl";
-const char pstrUsageVerticalScroll [] PROGMEM = "V Scroll";
-const char pstrUsageHorizontalScroll [] PROGMEM = "H Scroll";
-const char pstrUsageCharacterReport [] PROGMEM = "Char Rpt";
-const char pstrUsageDisplayData [] PROGMEM = "Disp Data";
-const char pstrUsageDisplayStatus [] PROGMEM = "Disp Stat";
-const char pstrUsageStatusNotReady [] PROGMEM = "Stat !Ready";
-const char pstrUsageStatusReady [] PROGMEM = "Stat Ready";
-const char pstrUsageErrorNotALoadableCharacter [] PROGMEM = "Err Not Ld Char";
-const char pstrUsageErrorFotDataCanNotBeRead [] PROGMEM = "Fnt Data Rd Err";
-const char pstrUsageCursorPositionReport [] PROGMEM = "Cur Pos Rpt";
-const char pstrUsageRow [] PROGMEM = "Row";
-const char pstrUsageColumn [] PROGMEM = "Col";
-const char pstrUsageRows [] PROGMEM = "Rows";
-const char pstrUsageColumns [] PROGMEM = "Cols";
-const char pstrUsageCursorPixelPosition [] PROGMEM = "Cur Pix Pos";
-const char pstrUsageCursorMode [] PROGMEM = "Cur Mode";
-const char pstrUsageCursorEnable [] PROGMEM = "Cur Enbl";
-const char pstrUsageCursorBlink [] PROGMEM = "Cur Blnk";
-const char pstrUsageFontReport [] PROGMEM = "Fnt Rpt";
-const char pstrUsageFontData [] PROGMEM = "Fnt Data";
-const char pstrUsageCharacterWidth [] PROGMEM = "Char Wdth";
-const char pstrUsageCharacterHeight [] PROGMEM = "Char Hght";
-const char pstrUsageCharacterSpacingHorizontal [] PROGMEM = "Char Space H";
-const char pstrUsageCharacterSpacingVertical [] PROGMEM = "Char Space V";
-const char pstrUsageUnicodeCharset [] PROGMEM = "Unicode Char";
-const char pstrUsageFont7Segment [] PROGMEM = "Fnt 7-seg";
-const char pstrUsage7SegmentDirectMap [] PROGMEM = "7-seg map";
-const char pstrUsageFont14Segment [] PROGMEM = "Fnt 14-seg";
-const char pstrUsage14SegmentDirectMap [] PROGMEM = "14-seg map";
-const char pstrUsageDisplayBrightness [] PROGMEM = "Disp Bright";
-const char pstrUsageDisplayContrast [] PROGMEM = "Disp Cntrst";
-const char pstrUsageCharacterAttribute [] PROGMEM = "Char Attr";
-const char pstrUsageAttributeReadback [] PROGMEM = "Attr Readbk";
-const char pstrUsageAttributeData [] PROGMEM = "Attr Data";
-const char pstrUsageCharAttributeEnhance [] PROGMEM = "Char Attr Enh";
-const char pstrUsageCharAttributeUnderline [] PROGMEM = "Char Attr Undl";
-const char pstrUsageCharAttributeBlink [] PROGMEM = "Char Attr Blnk";
-const char pstrUsageBitmapSizeX [] PROGMEM = "Bmp Size X";
-const char pstrUsageBitmapSizeY [] PROGMEM = "Bmp Size Y";
-const char pstrUsageBitDepthFormat [] PROGMEM = "Bit Dpth Fmt";
-const char pstrUsageDisplayOrientation [] PROGMEM = "Disp Ornt";
-const char pstrUsagePaletteReport [] PROGMEM = "Pal Rpt";
-const char pstrUsagePaletteDataSize [] PROGMEM = "Pal Data Size";
-const char pstrUsagePaletteDataOffset [] PROGMEM = "Pal Data Off";
-const char pstrUsagePaletteData [] PROGMEM = "Pal Data";
-const char pstrUsageBlitReport [] PROGMEM = "Blit Rpt";
-const char pstrUsageBlitRectangleX1 [] PROGMEM = "Blit Rect X1";
-const char pstrUsageBlitRectangleY1 [] PROGMEM = "Blit Rect Y1";
-const char pstrUsageBlitRectangleX2 [] PROGMEM = "Blit Rect X2";
-const char pstrUsageBlitRectangleY2 [] PROGMEM = "Blit Rect Y2";
-const char pstrUsageBlitData [] PROGMEM = "Blit Data";
-const char pstrUsageSoftButton [] PROGMEM = "Soft Btn";
-const char pstrUsageSoftButtonID [] PROGMEM = "Soft Btn ID";
-const char pstrUsageSoftButtonSide [] PROGMEM = "Soft Btn Side";
-const char pstrUsageSoftButtonOffset1 [] PROGMEM = "Soft Btn Off1";
-const char pstrUsageSoftButtonOffset2 [] PROGMEM = "Soft Btn Off2";
-const char pstrUsageSoftButtonReport [] PROGMEM = "Soft Btn Rpt";
-
-// Medical Instrument Page
-const char pstrUsageMedicalUltrasound [] PROGMEM = "Med Ultrasnd";
-const char pstrUsageVCRAcquisition [] PROGMEM = "VCR/Acq";
-const char pstrUsageFreezeThaw [] PROGMEM = "Freeze";
-const char pstrUsageClipStore [] PROGMEM = "Clip Store";
-const char pstrUsageUpdate [] PROGMEM = "Update";
-const char pstrUsageNext [] PROGMEM = "Next";
-const char pstrUsageSave [] PROGMEM = "Save";
-const char pstrUsagePrint [] PROGMEM = "Print";
-const char pstrUsageMicrophoneEnable [] PROGMEM = "Mic Enbl";
-const char pstrUsageCine [] PROGMEM = "Cine";
-const char pstrUsageTransmitPower [] PROGMEM = "Trans Pwr";
-//const char pstrUsageVolume [] PROGMEM = "Vol";
-const char pstrUsageFocus [] PROGMEM = "Focus";
-const char pstrUsageDepth [] PROGMEM = "Depth";
-const char pstrUsageSoftStepPrimary [] PROGMEM = "Soft Stp-Pri";
-const char pstrUsageSoftStepSecondary [] PROGMEM = "Soft Stp-Sec";
-const char pstrUsageDepthGainCompensation [] PROGMEM = "Dpth Gain Comp";
-const char pstrUsageZoomSelect [] PROGMEM = "Zoom Sel";
-const char pstrUsageZoomAdjust [] PROGMEM = "Zoom Adj";
-const char pstrUsageSpectralDopplerModeSelect [] PROGMEM = "Spec Dop Mode Sel";
-const char pstrUsageSpectralDopplerModeAdjust [] PROGMEM = "Spec Dop Mode Adj";
-const char pstrUsageColorDopplerModeSelect [] PROGMEM = "Color Dop Mode Sel";
-const char pstrUsageColorDopplerModeAdjust [] PROGMEM = "Color Dop Mode Adj";
-const char pstrUsageMotionModeSelect [] PROGMEM = "Motion Mode Sel";
-const char pstrUsageMotionModeAdjust [] PROGMEM = "Motion Mode Adj";
-const char pstrUsage2DModeSelect [] PROGMEM = "2D Mode Sel";
-const char pstrUsage2DModeAdjust [] PROGMEM = "2D Mode Adj";
-const char pstrUsageSoftControlSelect [] PROGMEM = "Soft Ctrl Sel";
-const char pstrUsageSoftControlAdjust [] PROGMEM = "Soft Ctrl Adj";
-
-//extern const char *usagePageTitles0[15];
-//const char *usagePageTitles1[];
-//const char *genDesktopTitles0[];
-//const char *genDesktopTitles1[];
-//const char *genDesktopTitles2[];
-//const char *genDesktopTitles3[];
-//const char *genDesktopTitles4[];
-//const char *simuTitles0[];
-//const char *simuTitles1[];
-//const char *simuTitles2[];
-//const char *vrTitles0[];
-//const char *vrTitles1[];
-//const char *sportsCtrlTitles0[];
-//const char *sportsCtrlTitles1[];
-//const char *sportsCtrlTitles2[];
-//const char *gameTitles0[];
-//const char *gameTitles1[];
-//const char *genDevCtrlTitles[];
-//const char *ledTitles[];
-//const char *telTitles0[];
-//const char *telTitles1[];
-//const char *telTitles2[];
-//const char *telTitles3[];
-//const char *telTitles4[];
-//const char *telTitles5[];
-//const char *consTitles0[];
-//const char *consTitles1[];
-//const char *consTitles2[];
-//const char *consTitles3[];
-//const char *consTitles4[];
-//const char *consTitles5[];
-//const char *consTitles6[];
-//const char *consTitles7[];
-//const char *consTitles8[];
-//const char *consTitles9[];
-//const char *consTitlesA[];
-//const char *consTitlesB[];
-//const char *consTitlesC[];
-//const char *consTitlesD[];
-//const char *consTitlesE[];
-//const char *digitTitles0[];
-//const char *digitTitles1[];
-//const char *digitTitles2[];
-//const char *aplphanumTitles0[];
-//const char *aplphanumTitles1[];
-//const char *aplphanumTitles2[];
-//const char *medInstrTitles0[];
-//const char *medInstrTitles1[];
-//const char *medInstrTitles2[];
-//const char *medInstrTitles3[];
-//const char *medInstrTitles4[];
-
-#endif //__HIDUSAGESTR_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/hidusagetitlearrays.cpp b/lib/usbhost/USB_Host_Shield_2.0/hidusagetitlearrays.cpp
deleted file mode 100644
index ee233002ca..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/hidusagetitlearrays.cpp
+++ /dev/null
@@ -1,1048 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(__HIDUSAGETITLEARRAYS_H__)
-#define __HIDUSAGETITLEARRAYS_H__
-
-#include "hidusagestr.h"
-
-// This is here why?
-
-//const char *usagePageTitles0[]	PROGMEM =
-//{
-//	pstrUsagePageGenericDesktopControls	,
-//	pstrUsagePageSimulationControls		,
-//	pstrUsagePageVRControls				,
-//	pstrUsagePageSportControls			,
-//	pstrUsagePageGameControls			,
-//	pstrUsagePageGenericDeviceControls	,
-//	pstrUsagePageKeyboardKeypad			,
-//	pstrUsagePageLEDs					,
-//	pstrUsagePageButton					,
-//	pstrUsagePageOrdinal				,
-//	pstrUsagePageTelephone				,
-//	pstrUsagePageConsumer				,
-//	pstrUsagePageDigitizer				,
-//	pstrUsagePagePID					,
-//	pstrUsagePageUnicode
-//};
-//
-//const char *usagePageTitles1[]	PROGMEM =
-//{
-//	pstrUsagePageBarCodeScanner			,
-//	pstrUsagePageScale					,
-//	pstrUsagePageMSRDevices				,
-//	pstrUsagePagePointOfSale			,
-//	pstrUsagePageCameraControl			,
-//	pstrUsagePageArcade
-//};
-//const char *genDesktopTitles0[] PROGMEM =
-//{
-//	pstrUsagePointer					,
-//	pstrUsageMouse						,
-//	pstrUsageJoystick					,
-//	pstrUsageGamePad					,
-//	pstrUsageKeyboard					,
-//	pstrUsageKeypad						,
-//	pstrUsageMultiAxisController		,
-//	pstrUsageTabletPCSystemControls
-//
-//};
-//const char *genDesktopTitles1[] PROGMEM =
-//{
-//	pstrUsageX							,
-//	pstrUsageY							,
-//	pstrUsageZ							,
-//	pstrUsageRx							,
-//	pstrUsageRy							,
-//	pstrUsageRz							,
-//	pstrUsageSlider						,
-//	pstrUsageDial						,
-//	pstrUsageWheel						,
-//	pstrUsageHatSwitch					,
-//	pstrUsageCountedBuffer				,
-//	pstrUsageByteCount					,
-//	pstrUsageMotionWakeup				,
-//	pstrUsageStart						,
-//	pstrUsageSelect						,
-//	pstrUsagePageReserved				,
-//	pstrUsageVx							,
-//	pstrUsageVy							,
-//	pstrUsageVz							,
-//	pstrUsageVbrx						,
-//	pstrUsageVbry						,
-//	pstrUsageVbrz						,
-//	pstrUsageVno						,
-//	pstrUsageFeatureNotification		,
-//	pstrUsageResolutionMultiplier
-//};
-//const char *genDesktopTitles2[] PROGMEM =
-//{
-//	pstrUsageSystemControl		,
-//	pstrUsageSystemPowerDown	,
-//	pstrUsageSystemSleep		,
-//	pstrUsageSystemWakeup		,
-//	pstrUsageSystemContextMenu	,
-//	pstrUsageSystemMainMenu		,
-//	pstrUsageSystemAppMenu		,
-//	pstrUsageSystemMenuHelp		,
-//	pstrUsageSystemMenuExit		,
-//	pstrUsageSystemMenuSelect	,
-//	pstrUsageSystemMenuRight	,
-//	pstrUsageSystemMenuLeft		,
-//	pstrUsageSystemMenuUp		,
-//	pstrUsageSystemMenuDown		,
-//	pstrUsageSystemColdRestart	,
-//	pstrUsageSystemWarmRestart	,
-//	pstrUsageDPadUp				,
-//	pstrUsageDPadDown			,
-//	pstrUsageDPadRight			,
-//	pstrUsageDPadLeft
-//};
-//const char *genDesktopTitles3[] PROGMEM =
-//{
-//	pstrUsageSystemDock				,
-//	pstrUsageSystemUndock			,
-//	pstrUsageSystemSetup			,
-//	pstrUsageSystemBreak			,
-//	pstrUsageSystemDebuggerBreak	,
-//	pstrUsageApplicationBreak		,
-//	pstrUsageApplicationDebuggerBreak,
-//	pstrUsageSystemSpeakerMute		,
-//	pstrUsageSystemHibernate
-//};
-//const char *genDesktopTitles4[] PROGMEM =
-//{
-//	pstrUsageSystemDisplayInvert		,
-//	pstrUsageSystemDisplayInternal		,
-//	pstrUsageSystemDisplayExternal		,
-//	pstrUsageSystemDisplayBoth			,
-//	pstrUsageSystemDisplayDual			,
-//	pstrUsageSystemDisplayToggleIntExt	,
-//	pstrUsageSystemDisplaySwapPriSec	,
-//	pstrUsageSystemDisplayLCDAutoscale
-//};
-//const char *simuTitles0[] PROGMEM =
-//{
-//	pstrUsageFlightSimulationDevice		,
-//	pstrUsageAutomobileSimulationDevice	,
-//	pstrUsageTankSimulationDevice		,
-//	pstrUsageSpaceshipSimulationDevice	,
-//	pstrUsageSubmarineSimulationDevice	,
-//	pstrUsageSailingSimulationDevice	,
-//	pstrUsageMotocicleSimulationDevice	,
-//	pstrUsageSportsSimulationDevice		,
-//	pstrUsageAirplaneSimulationDevice	,
-//	pstrUsageHelicopterSimulationDevice	,
-//	pstrUsageMagicCarpetSimulationDevice,
-//	pstrUsageBicycleSimulationDevice
-//};
-//const char *simuTitles1[] PROGMEM =
-//{
-//	pstrUsageFlightControlStick			,
-//	pstrUsageFlightStick				,
-//	pstrUsageCyclicControl				,
-//	pstrUsageCyclicTrim					,
-//	pstrUsageFlightYoke					,
-//	pstrUsageTrackControl
-//};
-//const char *simuTitles2[] PROGMEM =
-//{
-//	pstrUsageAileron					,
-//	pstrUsageAileronTrim				,
-//	pstrUsageAntiTorqueControl			,
-//	pstrUsageAutopilotEnable			,
-//	pstrUsageChaffRelease				,
-//	pstrUsageCollectiveControl			,
-//	pstrUsageDiveBrake					,
-//	pstrUsageElectronicCountermeasures	,
-//	pstrUsageElevator					,
-//	pstrUsageElevatorTrim				,
-//	pstrUsageRudder						,
-//	pstrUsageThrottle					,
-//	pstrUsageFlightCommunications		,
-//	pstrUsageFlareRelease				,
-//	pstrUsageLandingGear				,
-//	pstrUsageToeBrake					,
-//	pstrUsageTrigger					,
-//	pstrUsageWeaponsArm					,
-//	pstrUsageWeaponsSelect				,
-//	pstrUsageWingFlaps					,
-//	pstrUsageAccelerator				,
-//	pstrUsageBrake						,
-//	pstrUsageClutch						,
-//	pstrUsageShifter					,
-//	pstrUsageSteering					,
-//	pstrUsageTurretDirection			,
-//	pstrUsageBarrelElevation			,
-//	pstrUsageDivePlane					,
-//	pstrUsageBallast					,
-//	pstrUsageBicycleCrank				,
-//	pstrUsageHandleBars					,
-//	pstrUsageFrontBrake					,
-//	pstrUsageRearBrake
-//};
-//const char *vrTitles0[]	PROGMEM =
-//{
-//	pstrUsageBelt				,
-//	pstrUsageBodySuit			,
-//	pstrUsageFlexor				,
-//	pstrUsageGlove				,
-//	pstrUsageHeadTracker		,
-//	pstrUsageHeadMountedDisplay	,
-//	pstrUsageHandTracker		,
-//	pstrUsageOculometer			,
-//	pstrUsageVest				,
-//	pstrUsageAnimatronicDevice
-//};
-//const char *vrTitles1[]	PROGMEM =
-//{
-//	pstrUsageStereoEnable	,
-//	pstrUsageDisplayEnable
-//};
-//const char *sportsCtrlTitles0[]	PROGMEM =
-//{
-//	pstrUsageBaseballBat				,
-//	pstrUsageGolfClub					,
-//	pstrUsageRowingMachine				,
-//	pstrUsageTreadmill
-//};
-//const char *sportsCtrlTitles1[]	PROGMEM =
-//{
-//	pstrUsageOar						,
-//	pstrUsageSlope						,
-//	pstrUsageRate						,
-//	pstrUsageStickSpeed					,
-//	pstrUsageStickFaceAngle				,
-//	pstrUsageStickHeelToe				,
-//	pstrUsageStickFollowThough			,
-//	pstrUsageStickTempo					,
-//	pstrUsageStickType					,
-//	pstrUsageStickHeight
-//};
-//const char *sportsCtrlTitles2[]	PROGMEM =
-//{
-//	pstrUsagePutter						,
-//	pstrUsage1Iron						,
-//	pstrUsage2Iron						,
-//	pstrUsage3Iron						,
-//	pstrUsage4Iron						,
-//	pstrUsage5Iron						,
-//	pstrUsage6Iron						,
-//	pstrUsage7Iron						,
-//	pstrUsage8Iron						,
-//	pstrUsage9Iron						,
-//	pstrUsage10Iron						,
-//	pstrUsage11Iron						,
-//	pstrUsageSandWedge					,
-//	pstrUsageLoftWedge					,
-//	pstrUsagePowerWedge					,
-//	pstrUsage1Wood						,
-//	pstrUsage3Wood						,
-//	pstrUsage5Wood						,
-//	pstrUsage7Wood						,
-//	pstrUsage9Wood
-//};
-//const char *gameTitles0[] PROGMEM =
-//{
-//	pstrUsage3DGameController		,
-//	pstrUsagePinballDevice			,
-//	pstrUsageGunDevice
-//};
-//const char *gameTitles1[] PROGMEM =
-//{
-//	pstrUsagePointOfView			,
-//	pstrUsageTurnRightLeft			,
-//	pstrUsagePitchForwardBackward	,
-//	pstrUsageRollRightLeft			,
-//	pstrUsageMoveRightLeft			,
-//	pstrUsageMoveForwardBackward	,
-//	pstrUsageMoveUpDown				,
-//	pstrUsageLeanRightLeft			,
-//	pstrUsageLeanForwardBackward	,
-//	pstrUsageHeightOfPOV			,
-//	pstrUsageFlipper				,
-//	pstrUsageSecondaryFlipper		,
-//	pstrUsageBump					,
-//	pstrUsageNewGame				,
-//	pstrUsageShootBall				,
-//	pstrUsagePlayer					,
-//	pstrUsageGunBolt				,
-//	pstrUsageGunClip				,
-//	pstrUsageGunSelector			,
-//	pstrUsageGunSingleShot			,
-//	pstrUsageGunBurst				,
-//	pstrUsageGunAutomatic			,
-//	pstrUsageGunSafety				,
-//	pstrUsageGamepadFireJump		,
-//	pstrUsageGamepadTrigger
-//};
-//const char *genDevCtrlTitles[] PROGMEM =
-//{
-//	pstrUsageBatteryStrength,
-//	pstrUsageWirelessChannel,
-//	pstrUsageWirelessID,
-//	pstrUsageDiscoverWirelessControl,
-//	pstrUsageSecurityCodeCharEntered,
-//	pstrUsageSecurityCodeCharErased,
-//	pstrUsageSecurityCodeCleared
-//};
-//const char *ledTitles[] PROGMEM =
-//{
-//	pstrUsageNumLock						,
-//	pstrUsageCapsLock					,
-//	pstrUsageScrollLock					,
-//	pstrUsageCompose					,
-//	pstrUsageKana						,
-//	pstrUsagePower						,
-//	pstrUsageShift						,
-//	pstrUsageDoNotDisturb				,
-//	pstrUsageMute						,
-//	pstrUsageToneEnable					,
-//	pstrUsageHighCutFilter				,
-//	pstrUsageLowCutFilter				,
-//	pstrUsageEqualizerEnable			,
-//	pstrUsageSoundFieldOn				,
-//	pstrUsageSurroundOn					,
-//	pstrUsageRepeat						,
-//	pstrUsageStereo						,
-//	pstrUsageSamplingRateDetect			,
-//	pstrUsageSpinning					,
-//	pstrUsageCAV						,
-//	pstrUsageCLV						,
-//	pstrUsageRecordingFormatDetect		,
-//	pstrUsageOffHook					,
-//	pstrUsageRing						,
-//	pstrUsageMessageWaiting				,
-//	pstrUsageDataMode					,
-//	pstrUsageBatteryOperation			,
-//	pstrUsageBatteryOK					,
-//	pstrUsageBatteryLow					,
-//	pstrUsageSpeaker					,
-//	pstrUsageHeadSet					,
-//	pstrUsageHold						,
-//	pstrUsageMicrophone					,
-//	pstrUsageCoverage					,
-//	pstrUsageNightMode					,
-//	pstrUsageSendCalls					,
-//	pstrUsageCallPickup					,
-//	pstrUsageConference					,
-//	pstrUsageStandBy					,
-//	pstrUsageCameraOn					,
-//	pstrUsageCameraOff					,
-//	pstrUsageOnLine						,
-//	pstrUsageOffLine					,
-//	pstrUsageBusy						,
-//	pstrUsageReady						,
-//	pstrUsagePaperOut					,
-//	pstrUsagePaperJam					,
-//	pstrUsageRemote						,
-//	pstrUsageForward					,
-//	pstrUsageReverse					,
-//	pstrUsageStop						,
-//	pstrUsageRewind						,
-//	pstrUsageFastForward				,
-//	pstrUsagePlay						,
-//	pstrUsagePause						,
-//	pstrUsageRecord						,
-//	pstrUsageError						,
-//	pstrUsageSelectedIndicator			,
-//	pstrUsageInUseIndicator				,
-//	pstrUsageMultiModeIndicator			,
-//	pstrUsageIndicatorOn				,
-//	pstrUsageIndicatorFlash				,
-//	pstrUsageIndicatorSlowBlink			,
-//	pstrUsageIndicatorFastBlink			,
-//	pstrUsageIndicatorOff				,
-//	pstrUsageFlashOnTime				,
-//	pstrUsageSlowBlinkOnTime			,
-//	pstrUsageSlowBlinkOffTime			,
-//	pstrUsageFastBlinkOnTime			,
-//	pstrUsageFastBlinkOffTime			,
-//	pstrUsageIndicatorColor				,
-//	pstrUsageIndicatorRed				,
-//	pstrUsageIndicatorGreen				,
-//	pstrUsageIndicatorAmber				,
-//	pstrUsageGenericIndicator			,
-//	pstrUsageSystemSuspend				,
-//	pstrUsageExternalPowerConnected
-//};
-//const char *telTitles0			[] PROGMEM =
-//{
-//	pstrUsagePhone				,
-//	pstrUsageAnsweringMachine	,
-//	pstrUsageMessageControls	,
-//	pstrUsageHandset			,
-//	pstrUsageHeadset			,
-//	pstrUsageTelephonyKeyPad	,
-//	pstrUsageProgrammableButton
-//};
-//const char *telTitles1			[] PROGMEM =
-//{
-//	pstrUsageHookSwitch					,
-//	pstrUsageFlash						,
-//	pstrUsageFeature					,
-//	pstrUsageHold						,
-//	pstrUsageRedial						,
-//	pstrUsageTransfer					,
-//	pstrUsageDrop						,
-//	pstrUsagePark						,
-//	pstrUsageForwardCalls				,
-//	pstrUsageAlternateFunction			,
-//	pstrUsageLine						,
-//	pstrUsageSpeakerPhone				,
-//	pstrUsageConference				,
-//	pstrUsageRingEnable				,
-//	pstrUsageRingSelect				,
-//	pstrUsagePhoneMute				,
-//	pstrUsageCallerID				,
-//	pstrUsageSend
-//};
-//const char *telTitles2			[] PROGMEM =
-//{
-//	pstrUsageSpeedDial		,
-//	pstrUsageStoreNumber	,
-//	pstrUsageRecallNumber	,
-//	pstrUsagePhoneDirectory
-//};
-//const char *telTitles3			[] PROGMEM =
-//{
-//	pstrUsageVoiceMail		,
-//	pstrUsageScreenCalls	,
-//	pstrUsageDoNotDisturb	,
-//	pstrUsageMessage		,
-//	pstrUsageAnswerOnOff
-//};
-//const char *telTitles4			[] PROGMEM =
-//{
-//	pstrUsageInsideDialTone			,
-//	pstrUsageOutsideDialTone		,
-//	pstrUsageInsideRingTone			,
-//	pstrUsageOutsideRingTone		,
-//	pstrUsagePriorityRingTone		,
-//	pstrUsageInsideRingback			,
-//	pstrUsagePriorityRingback		,
-//	pstrUsageLineBusyTone			,
-//	pstrUsageReorderTone			,
-//	pstrUsageCallWaitingTone		,
-//	pstrUsageConfirmationTone1		,
-//	pstrUsageConfirmationTone2		,
-//	pstrUsageTonesOff				,
-//	pstrUsageOutsideRingback		,
-//	pstrUsageRinger
-//};
-//const char *telTitles5			[] PROGMEM =
-//{
-//	pstrUsagePhoneKey0		,
-//	pstrUsagePhoneKey1		,
-//	pstrUsagePhoneKey2		,
-//	pstrUsagePhoneKey3		,
-//	pstrUsagePhoneKey4		,
-//	pstrUsagePhoneKey5		,
-//	pstrUsagePhoneKey6		,
-//	pstrUsagePhoneKey7		,
-//	pstrUsagePhoneKey8		,
-//	pstrUsagePhoneKey9		,
-//	pstrUsagePhoneKeyStar	,
-//	pstrUsagePhoneKeyPound	,
-//	pstrUsagePhoneKeyA		,
-//	pstrUsagePhoneKeyB		,
-//	pstrUsagePhoneKeyC		,
-//	pstrUsagePhoneKeyD
-//};
-//const char *consTitles0[]	PROGMEM	=
-//{
-//	pstrUsageConsumerControl,
-//	pstrUsageNumericKeyPad,
-//	pstrUsageProgrammableButton,
-//	pstrUsageMicrophone,
-//	pstrUsageHeadphone,
-//	pstrUsageGraphicEqualizer
-//};
-//const char *consTitles1[]	PROGMEM	=
-//{
-//	pstrUsagePlus10	,
-//	pstrUsagePlus100,
-//	pstrUsageAMPM
-//};
-//const char *consTitles2[]	PROGMEM	=
-//{
-//	pstrUsagePower			,
-//	pstrUsageReset			,
-//	pstrUsageSleep			,
-//	pstrUsageSleepAfter		,
-//	pstrUsageSleepMode		,
-//	pstrUsageIllumination	,
-//	pstrUsageFunctionButtons
-//
-//};
-//const char *consTitles3[]	PROGMEM	=
-//{
-//	pstrUsageMenu			,
-//	pstrUsageMenuPick		,
-//	pstrUsageMenuUp			,
-//	pstrUsageMenuDown		,
-//	pstrUsageMenuLeft		,
-//	pstrUsageMenuRight		,
-//	pstrUsageMenuEscape		,
-//	pstrUsageMenuValueIncrease,
-//	pstrUsageMenuValueDecrease
-//};
-//const char *consTitles4[]	PROGMEM	=
-//{
-//	pstrUsageDataOnScreen		,
-//	pstrUsageClosedCaption		,
-//	pstrUsageClosedCaptionSelect,
-//	pstrUsageVCRTV				,
-//	pstrUsageBroadcastMode		,
-//	pstrUsageSnapshot			,
-//	pstrUsageStill
-//};
-//const char *consTitles5[]	PROGMEM	=
-//{
-//	pstrUsageSelection					,
-//	pstrUsageAssignSelection			,
-//	pstrUsageModeStep					,
-//	pstrUsageRecallLast					,
-//	pstrUsageEnterChannel				,
-//	pstrUsageOrderMovie					,
-//	pstrUsageChannel					,
-//	pstrUsageMediaSelection				,
-//	pstrUsageMediaSelectComputer		,
-//	pstrUsageMediaSelectTV				,
-//	pstrUsageMediaSelectWWW				,
-//	pstrUsageMediaSelectDVD				,
-//	pstrUsageMediaSelectTelephone		,
-//	pstrUsageMediaSelectProgramGuide	,
-//	pstrUsageMediaSelectVideoPhone		,
-//	pstrUsageMediaSelectGames			,
-//	pstrUsageMediaSelectMessages		,
-//	pstrUsageMediaSelectCD				,
-//	pstrUsageMediaSelectVCR				,
-//	pstrUsageMediaSelectTuner			,
-//	pstrUsageQuit						,
-//	pstrUsageHelp						,
-//	pstrUsageMediaSelectTape			,
-//	pstrUsageMediaSelectCable			,
-//	pstrUsageMediaSelectSatellite		,
-//	pstrUsageMediaSelectSecurity		,
-//	pstrUsageMediaSelectHome			,
-//	pstrUsageMediaSelectCall			,
-//	pstrUsageChannelIncrement			,
-//	pstrUsageChannelDecrement			,
-//	pstrUsageMediaSelectSAP				,
-//	pstrUsagePageReserved				,
-//	pstrUsageVCRPlus					,
-//	pstrUsageOnce						,
-//	pstrUsageDaily						,
-//	pstrUsageWeekly						,
-//	pstrUsageMonthly
-//};
-//const char *consTitles6[]	PROGMEM	=
-//{
-//	pstrUsagePlay					,
-//	pstrUsagePause					,
-//	pstrUsageRecord					,
-//	pstrUsageFastForward			,
-//	pstrUsageRewind					,
-//	pstrUsageScanNextTrack			,
-//	pstrUsageScanPreviousTrack		,
-//	pstrUsageStop					,
-//	pstrUsageEject					,
-//	pstrUsageRandomPlay				,
-//	pstrUsageSelectDisk				,
-//	pstrUsageEnterDisk				,
-//	pstrUsageRepeat					,
-//	pstrUsageTracking					,
-//	pstrUsageTrackNormal				,
-//	pstrUsageSlowTracking				,
-//	pstrUsageFrameForward				,
-//	pstrUsageFrameBackwards				,
-//	pstrUsageMark						,
-//	pstrUsageClearMark					,
-//	pstrUsageRepeatFromMark				,
-//	pstrUsageReturnToMark				,
-//	pstrUsageSearchMarkForward			,
-//	pstrUsageSearchMarkBackwards		,
-//	pstrUsageCounterReset				,
-//	pstrUsageShowCounter				,
-//	pstrUsageTrackingIncrement			,
-//	pstrUsageTrackingDecrement			,
-//	pstrUsageStopEject					,
-//	pstrUsagePlayPause					,
-//	pstrUsagePlaySkip
-//};
-//const char *consTitles7[]	PROGMEM	=
-//{
-//	pstrUsageVolume						,
-//	pstrUsageBalance					,
-//	pstrUsageMute						,
-//	pstrUsageBass						,
-//	pstrUsageTreble						,
-//	pstrUsageBassBoost					,
-//	pstrUsageSurroundMode				,
-//	pstrUsageLoudness					,
-//	pstrUsageMPX						,
-//	pstrUsageVolumeIncrement			,
-//	pstrUsageVolumeDecrement
-//};
-//const char *consTitles8[]	PROGMEM	=
-//{
-//	pstrUsageSpeedSelect				,
-//	pstrUsagePlaybackSpeed				,
-//	pstrUsageStandardPlay				,
-//	pstrUsageLongPlay					,
-//	pstrUsageExtendedPlay				,
-//	pstrUsageSlow
-//};
-//const char *consTitles9[]	PROGMEM	=
-//{
-//	pstrUsageFanEnable					,
-//	pstrUsageFanSpeed					,
-//	pstrUsageLightEnable				,
-//	pstrUsageLightIlluminationLevel		,
-//	pstrUsageClimateControlEnable		,
-//	pstrUsageRoomTemperature			,
-//	pstrUsageSecurityEnable				,
-//	pstrUsageFireAlarm					,
-//	pstrUsagePoliceAlarm				,
-//	pstrUsageProximity					,
-//	pstrUsageMotion						,
-//	pstrUsageDuresAlarm					,
-//	pstrUsageHoldupAlarm					,
-//	pstrUsageMedicalAlarm
-//};
-//const char *consTitlesA[]	PROGMEM	=
-//{
-//	pstrUsageBalanceRight				,
-//	pstrUsageBalanceLeft				,
-//	pstrUsageBassIncrement				,
-//	pstrUsageBassDecrement				,
-//	pstrUsageTrebleIncrement			,
-//	pstrUsageTrebleDecrement
-//};
-//const char *consTitlesB[]	PROGMEM	=
-//{
-//	pstrUsageSpeakerSystem				,
-//	pstrUsageChannelLeft				,
-//	pstrUsageChannelRight				,
-//	pstrUsageChannelCenter				,
-//	pstrUsageChannelFront				,
-//	pstrUsageChannelCenterFront			,
-//	pstrUsageChannelSide				,
-//	pstrUsageChannelSurround			,
-//	pstrUsageChannelLowFreqEnhancement	,
-//	pstrUsageChannelTop					,
-//	pstrUsageChannelUnknown
-//};
-//const char *consTitlesC[]	PROGMEM	=
-//{
-//	pstrUsageSubChannel					,
-//	pstrUsageSubChannelIncrement		,
-//	pstrUsageSubChannelDecrement		,
-//	pstrUsageAlternateAudioIncrement	,
-//	pstrUsageAlternateAudioDecrement
-//};
-//const char *consTitlesD[]	PROGMEM	=
-//{
-//	pstrUsageApplicationLaunchButtons	,
-//	pstrUsageALLaunchButtonConfigTool	,
-//	pstrUsageALProgrammableButton		,
-//	pstrUsageALConsumerControlConfig	,
-//	pstrUsageALWordProcessor			,
-//	pstrUsageALTextEditor				,
-//	pstrUsageALSpreadsheet				,
-//	pstrUsageALGraphicsEditor			,
-//	pstrUsageALPresentationApp			,
-//	pstrUsageALDatabaseApp				,
-//	pstrUsageALEmailReader				,
-//	pstrUsageALNewsreader				,
-//	pstrUsageALVoicemail				,
-//	pstrUsageALContactsAddressBook		,
-//	pstrUsageALCalendarSchedule			,
-//	pstrUsageALTaskProjectManager		,
-//	pstrUsageALLogJournalTimecard		,
-//	pstrUsageALCheckbookFinance			,
-//	pstrUsageALCalculator				,
-//	pstrUsageALAVCapturePlayback		,
-//	pstrUsageALLocalMachineBrowser		,
-//	pstrUsageALLANWANBrow				,
-//	pstrUsageALInternetBrowser			,
-//	pstrUsageALRemoteNetISPConnect		,
-//	pstrUsageALNetworkConference		,
-//	pstrUsageALNetworkChat				,
-//	pstrUsageALTelephonyDialer			,
-//	pstrUsageALLogon					,
-//	pstrUsageALLogoff					,
-//	pstrUsageALLogonLogoff				,
-//	pstrUsageALTermLockScrSav			,
-//	pstrUsageALControlPannel			,
-//	pstrUsageALCommandLineProcessorRun	,
-//	pstrUsageALProcessTaskManager		,
-//	pstrUsageALSelectTaskApplication	,
-//	pstrUsageALNextTaskApplication		,
-//	pstrUsageALPreviousTaskApplication	,
-//	pstrUsageALPreemptiveHaltTaskApp	,
-//	pstrUsageALIntegratedHelpCenter		,
-//	pstrUsageALDocuments				,
-//	pstrUsageALThesaurus				,
-//	pstrUsageALDictionary				,
-//	pstrUsageALDesktop					,
-//	pstrUsageALSpellCheck				,
-//	pstrUsageALGrammarCheck				,
-//	pstrUsageALWirelessStatus			,
-//	pstrUsageALKeyboardLayout			,
-//	pstrUsageALVirusProtection			,
-//	pstrUsageALEncryption				,
-//	pstrUsageALScreenSaver				,
-//	pstrUsageALAlarms					,
-//	pstrUsageALClock					,
-//	pstrUsageALFileBrowser				,
-//	pstrUsageALPowerStatus				,
-//	pstrUsageALImageBrowser				,
-//	pstrUsageALAudioBrowser				,
-//	pstrUsageALMovieBrowser				,
-//	pstrUsageALDigitalRightsManager		,
-//	pstrUsageALDigitalWallet			,
-//	pstrUsagePageReserved				,
-//	pstrUsageALInstantMessaging			,
-//	pstrUsageALOEMFeaturesBrowser		,
-//	pstrUsageALOEMHelp					,
-//	pstrUsageALOnlineCommunity			,
-//	pstrUsageALEntertainmentContentBrow	,
-//	pstrUsageALOnlineShoppingBrowser	,
-//	pstrUsageALSmartCardInfoHelp		,
-//	pstrUsageALMarketMonitorFinBrowser	,
-//	pstrUsageALCustomCorpNewsBrowser		,
-//	pstrUsageALOnlineActivityBrowser		,
-//	pstrUsageALResearchSearchBrowser		,
-//	pstrUsageALAudioPlayer
-//};
-//const char *consTitlesE[]	PROGMEM	=
-//{
-//	pstrUsageGenericGUIAppControls		,
-//	pstrUsageACNew						,
-//	pstrUsageACOpen						,
-//	pstrUsageACClose					,
-//	pstrUsageACExit						,
-//	pstrUsageACMaximize					,
-//	pstrUsageACMinimize					,
-//	pstrUsageACSave						,
-//	pstrUsageACPrint					,
-//	pstrUsageACProperties				,
-//	pstrUsageACUndo						,
-//	pstrUsageACCopy						,
-//	pstrUsageACCut						,
-//	pstrUsageACPaste					,
-//	pstrUsageACSelectAll				,
-//	pstrUsageACFind						,
-//	pstrUsageACFindAndReplace			,
-//	pstrUsageACSearch					,
-//	pstrUsageACGoto						,
-//	pstrUsageACHome						,
-//	pstrUsageACBack						,
-//	pstrUsageACForward					,
-//	pstrUsageACStop						,
-//	pstrUsageACRefresh					,
-//	pstrUsageACPreviousLink				,
-//	pstrUsageACNextLink					,
-//	pstrUsageACBookmarks				,
-//	pstrUsageACHistory					,
-//	pstrUsageACSubscriptions			,
-//	pstrUsageACZoomIn					,
-//	pstrUsageACZoomOut					,
-//	pstrUsageACZoom						,
-//	pstrUsageACFullScreenView			,
-//	pstrUsageACNormalView				,
-//	pstrUsageACViewToggle				,
-//	pstrUsageACScrollUp					,
-//	pstrUsageACScrollDown				,
-//	pstrUsageACScroll					,
-//	pstrUsageACPanLeft					,
-//	pstrUsageACPanRight					,
-//	pstrUsageACPan						,
-//	pstrUsageACNewWindow				,
-//	pstrUsageACTileHoriz				,
-//	pstrUsageACTileVert					,
-//	pstrUsageACFormat					,
-//	pstrUsageACEdit						,
-//	pstrUsageACBold						,
-//	pstrUsageACItalics					,
-//	pstrUsageACUnderline				,
-//	pstrUsageACStrikethrough			,
-//	pstrUsageACSubscript				,
-//	pstrUsageACSuperscript				,
-//	pstrUsageACAllCaps					,
-//	pstrUsageACRotate					,
-//	pstrUsageACResize					,
-//	pstrUsageACFlipHorizontal			,
-//	pstrUsageACFlipVertical				,
-//	pstrUsageACMirrorHorizontal			,
-//	pstrUsageACMirrorVertical			,
-//	pstrUsageACFontSelect				,
-//	pstrUsageACFontColor				,
-//	pstrUsageACFontSize					,
-//	pstrUsageACJustifyLeft				,
-//	pstrUsageACJustifyCenterH			,
-//	pstrUsageACJustifyRight				,
-//	pstrUsageACJustifyBlockH			,
-//	pstrUsageACJustifyTop				,
-//	pstrUsageACJustifyCenterV			,
-//	pstrUsageACJustifyBottom			,
-//	pstrUsageACJustifyBlockV			,
-//	pstrUsageACIndentDecrease			,
-//	pstrUsageACIndentIncrease			,
-//	pstrUsageACNumberedList				,
-//	pstrUsageACRestartNumbering			,
-//	pstrUsageACBulletedList				,
-//	pstrUsageACPromote					,
-//	pstrUsageACDemote					,
-//	pstrUsageACYes						,
-//	pstrUsageACNo						,
-//	pstrUsageACCancel					,
-//	pstrUsageACCatalog					,
-//	pstrUsageACBuyChkout				,
-//	pstrUsageACAddToCart				,
-//	pstrUsageACExpand					,
-//	pstrUsageACExpandAll				,
-//	pstrUsageACCollapse					,
-//	pstrUsageACCollapseAll				,
-//	pstrUsageACPrintPreview				,
-//	pstrUsageACPasteSpecial				,
-//	pstrUsageACInsertMode				,
-//	pstrUsageACDelete					,
-//	pstrUsageACLock						,
-//	pstrUsageACUnlock					,
-//	pstrUsageACProtect					,
-//	pstrUsageACUnprotect				,
-//	pstrUsageACAttachComment			,
-//	pstrUsageACDeleteComment			,
-//	pstrUsageACViewComment				,
-//	pstrUsageACSelectWord				,
-//	pstrUsageACSelectSentence			,
-//	pstrUsageACSelectParagraph			,
-//	pstrUsageACSelectColumn				,
-//	pstrUsageACSelectRow				,
-//	pstrUsageACSelectTable				,
-//	pstrUsageACSelectObject				,
-//	pstrUsageACRedoRepeat				,
-//	pstrUsageACSort						,
-//	pstrUsageACSortAscending			,
-//	pstrUsageACSortDescending			,
-//	pstrUsageACFilter					,
-//	pstrUsageACSetClock					,
-//	pstrUsageACViewClock				,
-//	pstrUsageACSelectTimeZone			,
-//	pstrUsageACEditTimeZone				,
-//	pstrUsageACSetAlarm					,
-//	pstrUsageACClearAlarm				,
-//	pstrUsageACSnoozeAlarm				,
-//	pstrUsageACResetAlarm				,
-//	pstrUsageACSyncronize				,
-//	pstrUsageACSendReceive				,
-//	pstrUsageACSendTo					,
-//	pstrUsageACReply					,
-//	pstrUsageACReplyAll					,
-//	pstrUsageACForwardMessage			,
-//	pstrUsageACSend						,
-//	pstrUsageACAttachFile				,
-//	pstrUsageACUpload					,
-//	pstrUsageACDownload					,
-//	pstrUsageACSetBorders				,
-//	pstrUsageACInsertRow				,
-//	pstrUsageACInsertColumn				,
-//	pstrUsageACInsertFile				,
-//	pstrUsageACInsertPicture			,
-//	pstrUsageACInsertObject				,
-//	pstrUsageACInsertSymbol				,
-//	pstrUsageACSaveAndClose				,
-//	pstrUsageACRename					,
-//	pstrUsageACMerge					,
-//	pstrUsageACSplit					,
-//	pstrUsageACDistributeHorizontaly	,
-//	pstrUsageACDistributeVerticaly
-//};
-//const char *digitTitles0[] PROGMEM =
-//{
-//	pstrUsageDigitizer					,
-//	pstrUsagePen						,
-//	pstrUsageLightPen					,
-//	pstrUsageTouchScreen				,
-//	pstrUsageTouchPad					,
-//	pstrUsageWhiteBoard					,
-//	pstrUsageCoordinateMeasuringMachine	,
-//	pstrUsage3DDigitizer				,
-//	pstrUsageStereoPlotter				,
-//	pstrUsageArticulatedArm				,
-//	pstrUsageArmature					,
-//	pstrUsageMultiplePointDigitizer		,
-//	pstrUsageFreeSpaceWand
-//};
-//const char *digitTitles1[] PROGMEM =
-//{
-//	pstrUsageStylus						,
-//	pstrUsagePuck						,
-//	pstrUsageFinger
-//
-//};
-//const char *digitTitles2[] PROGMEM =
-//{
-//	pstrUsageTipPressure			,
-//	pstrUsageBarrelPressure			,
-//	pstrUsageInRange				,
-//	pstrUsageTouch					,
-//	pstrUsageUntouch				,
-//	pstrUsageTap					,
-//	pstrUsageQuality				,
-//	pstrUsageDataValid				,
-//	pstrUsageTransducerIndex		,
-//	pstrUsageTabletFunctionKeys		,
-//	pstrUsageProgramChangeKeys		,
-//	pstrUsageBatteryStrength		,
-//	pstrUsageInvert					,
-//	pstrUsageXTilt					,
-//	pstrUsageYTilt					,
-//	pstrUsageAzimuth				,
-//	pstrUsageAltitude				,
-//	pstrUsageTwist					,
-//	pstrUsageTipSwitch				,
-//	pstrUsageSecondaryTipSwitch		,
-//	pstrUsageBarrelSwitch			,
-//	pstrUsageEraser					,
-//	pstrUsageTabletPick
-//};
-//const char *aplphanumTitles0[]	PROGMEM =
-//{
-//	pstrUsageAlphanumericDisplay,
-//	pstrUsageBitmappedDisplay
-//};
-//const char *aplphanumTitles1[]	PROGMEM =
-//{
-//	pstrUsageDisplayAttributesReport	,
-//	pstrUsageASCIICharacterSet			,
-//	pstrUsageDataReadBack				,
-//	pstrUsageFontReadBack				,
-//	pstrUsageDisplayControlReport		,
-//	pstrUsageClearDisplay				,
-//	pstrUsageDisplayEnable				,
-//	pstrUsageScreenSaverDelay			,
-//	pstrUsageScreenSaverEnable			,
-//	pstrUsageVerticalScroll				,
-//	pstrUsageHorizontalScroll			,
-//	pstrUsageCharacterReport			,
-//	pstrUsageDisplayData				,
-//	pstrUsageDisplayStatus				,
-//	pstrUsageStatusNotReady				,
-//	pstrUsageStatusReady				,
-//	pstrUsageErrorNotALoadableCharacter	,
-//	pstrUsageErrorFotDataCanNotBeRead	,
-//	pstrUsageCursorPositionReport		,
-//	pstrUsageRow						,
-//	pstrUsageColumn						,
-//	pstrUsageRows						,
-//	pstrUsageColumns					,
-//	pstrUsageCursorPixelPosition		,
-//	pstrUsageCursorMode					,
-//	pstrUsageCursorEnable				,
-//	pstrUsageCursorBlink				,
-//	pstrUsageFontReport					,
-//	pstrUsageFontData					,
-//	pstrUsageCharacterWidth				,
-//	pstrUsageCharacterHeight			,
-//	pstrUsageCharacterSpacingHorizontal	,
-//	pstrUsageCharacterSpacingVertical	,
-//	pstrUsageUnicodeCharset				,
-//	pstrUsageFont7Segment				,
-//	pstrUsage7SegmentDirectMap			,
-//	pstrUsageFont14Segment				,
-//	pstrUsage14SegmentDirectMap			,
-//	pstrUsageDisplayBrightness			,
-//	pstrUsageDisplayContrast			,
-//	pstrUsageCharacterAttribute			,
-//	pstrUsageAttributeReadback			,
-//	pstrUsageAttributeData				,
-//	pstrUsageCharAttributeEnhance		,
-//	pstrUsageCharAttributeUnderline		,
-//	pstrUsageCharAttributeBlink
-//};
-//const char *aplphanumTitles2[]	PROGMEM =
-//{
-//	pstrUsageBitmapSizeX				,
-//	pstrUsageBitmapSizeY				,
-//	pstrUsagePageReserved				,
-//	pstrUsageBitDepthFormat				,
-//	pstrUsageDisplayOrientation			,
-//	pstrUsagePaletteReport				,
-//	pstrUsagePaletteDataSize			,
-//	pstrUsagePaletteDataOffset			,
-//	pstrUsagePaletteData				,
-//	pstrUsageBlitReport					,
-//	pstrUsageBlitRectangleX1			,
-//	pstrUsageBlitRectangleY1			,
-//	pstrUsageBlitRectangleX2			,
-//	pstrUsageBlitRectangleY2			,
-//	pstrUsageBlitData					,
-//	pstrUsageSoftButton					,
-//	pstrUsageSoftButtonID				,
-//	pstrUsageSoftButtonSide				,
-//	pstrUsageSoftButtonOffset1			,
-//	pstrUsageSoftButtonOffset2			,
-//	pstrUsageSoftButtonReport
-//};
-//const char *medInstrTitles0[] PROGMEM =
-//{
-//	pstrUsageVCRAcquisition				,
-//	pstrUsageFreezeThaw					,
-//	pstrUsageClipStore					,
-//	pstrUsageUpdate						,
-//	pstrUsageNext						,
-//	pstrUsageSave						,
-//	pstrUsagePrint						,
-//	pstrUsageMicrophoneEnable
-//};
-//const char *medInstrTitles1[] PROGMEM =
-//{
-//	pstrUsageCine						,
-//	pstrUsageTransmitPower				,
-//	pstrUsageVolume						,
-//	pstrUsageFocus						,
-//	pstrUsageDepth
-//};
-//const char *medInstrTitles2[] PROGMEM =
-//{
-//	pstrUsageSoftStepPrimary		,
-//	pstrUsageSoftStepSecondary
-//};
-//const char *medInstrTitles3[] PROGMEM =
-//{
-//	pstrUsageZoomSelect					,
-//	pstrUsageZoomAdjust					,
-//	pstrUsageSpectralDopplerModeSelect	,
-//	pstrUsageSpectralDopplerModeAdjust	,
-//	pstrUsageColorDopplerModeSelect		,
-//	pstrUsageColorDopplerModeAdjust		,
-//	pstrUsageMotionModeSelect			,
-//	pstrUsageMotionModeAdjust			,
-//	pstrUsage2DModeSelect				,
-//	pstrUsage2DModeAdjust
-//};
-//const char *medInstrTitles4[] PROGMEM =
-//{
-//	pstrUsageSoftControlSelect			,
-//	pstrUsageSoftControlAdjust
-//};
-
-#endif // __HIDUSAGETITLEARRAYS_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/keywords.txt b/lib/usbhost/USB_Host_Shield_2.0/keywords.txt
deleted file mode 100644
index f4e19cd133..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/keywords.txt
+++ /dev/null
@@ -1,371 +0,0 @@
-####################################################
-# Syntax Coloring Map For USB Library
-####################################################
-
-####################################################
-# Datatypes (KEYWORD1)
-####################################################
-
-USB	KEYWORD1
-USBHub	KEYWORD1
-
-####################################################
-# Syntax Coloring Map For BTD (Bluetooth) Library
-####################################################
-
-####################################################
-# Datatypes (KEYWORD1)
-####################################################
-
-BTD	KEYWORD1
-
-####################################################
-# Methods and Functions (KEYWORD2)
-####################################################
-Task	KEYWORD2
-
-####################################################
-# Syntax Coloring Map For PS3/PS4 Bluetooth/USB Library
-####################################################
-
-####################################################
-# Datatypes (KEYWORD1)
-####################################################
-
-PS3BT	KEYWORD1
-PS3USB	KEYWORD1
-PS4BT	KEYWORD1
-PS4USB	KEYWORD1
-
-####################################################
-# Methods and Functions (KEYWORD2)
-####################################################
-setBdaddr	KEYWORD2
-getBdaddr	KEYWORD2
-setMoveBdaddr	KEYWORD2
-getMoveBdaddr	KEYWORD2
-getMoveCalibration	KEYWORD2
-
-getButtonPress	KEYWORD2
-getButtonClick	KEYWORD2
-getAnalogButton	KEYWORD2
-getAnalogHat	KEYWORD2
-getSensor	KEYWORD2
-getAngle	KEYWORD2
-get9DOFValues	KEYWORD2
-getStatus	KEYWORD2
-printStatusString	KEYWORD2
-getTemperature	KEYWORD2
-disconnect	KEYWORD2
-
-setAllOff	KEYWORD2
-setRumbleOff	KEYWORD2
-setRumbleOn	KEYWORD2
-setLedOff	KEYWORD2
-setLedOn	KEYWORD2
-setLedToggle	KEYWORD2
-setLedFlash	KEYWORD2
-moveSetBulb	KEYWORD2
-moveSetRumble	KEYWORD2
-
-attachOnInit	KEYWORD2
-
-PS3Connected	KEYWORD2
-PS3MoveConnected	KEYWORD2
-PS3NavigationConnected	KEYWORD2
-
-isReady	KEYWORD2
-watingForConnection	KEYWORD2
-
-isTouching	KEYWORD2
-getX	KEYWORD2
-getY	KEYWORD2
-getTouchCounter	KEYWORD2
-
-getUsbStatus    KEYWORD2
-getAudioStatus  KEYWORD2
-getMicStatus    KEYWORD2
-
-####################################################
-# Constants and enums (LITERAL1)
-####################################################
-OFF	LITERAL1
-LED1	LITERAL1
-LED2	LITERAL1
-LED3	LITERAL1
-LED4	LITERAL1
-LED5	LITERAL1
-LED6	LITERAL1
-LED7	LITERAL1
-LED8	LITERAL1
-LED9	LITERAL1
-LED10	LITERAL1
-
-Red	LITERAL1
-Green	LITERAL1
-Blue	LITERAL1
-Yellow	LITERAL1
-Lightblue	LITERAL1
-Purble	LITERAL1
-White	LITERAL1
-Off	LITERAL1
-
-SELECT	LITERAL1
-L3	LITERAL1
-R3	LITERAL1
-START	LITERAL1
-UP	LITERAL1
-RIGHT	LITERAL1
-DOWN	LITERAL1
-LEFT	LITERAL1
-L2	LITERAL1
-R2	LITERAL1
-L1	LITERAL1
-R1	LITERAL1
-TRIANGLE	LITERAL1
-CIRCLE	LITERAL1
-CROSS	LITERAL1
-SQUARE	LITERAL1
-PS	LITERAL1
-MOVE	LITERAL1
-T	LITERAL1
-
-SHARE	LITERAL1
-OPTIONS	LITERAL1
-TOUCHPAD	LITERAL1
-
-LeftHatX	LITERAL1
-LeftHatY	LITERAL1
-RightHatX	LITERAL1
-RightHatY	LITERAL1
-
-aX	LITERAL1
-aY	LITERAL1
-aZ	LITERAL1
-gX	LITERAL1
-gY	LITERAL1
-gZ	LITERAL1
-aXmove	LITERAL1
-aYmove	LITERAL1
-aZmove	LITERAL1
-gXmove	LITERAL1
-gYmove	LITERAL1
-gZmove	LITERAL1
-tempMove	LITERAL1
-mXmove	LITERAL1
-mZmove	LITERAL1
-mYmove	LITERAL1
-
-Pitch	LITERAL1
-Roll	LITERAL1
-
-Plugged	LITERAL1
-Unplugged	LITERAL1
-Charging	LITERAL1
-NotCharging	LITERAL1
-Shutdown	LITERAL1
-Dying	LITERAL1
-Low	LITERAL1
-High	LITERAL1
-Full	LITERAL1
-MoveCharging	LITERAL1
-MoveNotCharging	LITERAL1
-MoveShutdown	LITERAL1
-MoveDying	LITERAL1
-MoveLow	LITERAL1
-MoveHigh	LITERAL1
-MoveFull	LITERAL1
-CableRumble	LITERAL1
-Cable	LITERAL1
-BluetoothRumble	LITERAL1
-Bluetooth	LITERAL1
-
-RumbleHigh	LITERAL1
-RumbleLow	LITERAL1
-
-####################################################
-# Syntax Coloring Map For Xbox 360 Libraries
-####################################################
-
-####################################################
-# Datatypes (KEYWORD1)
-####################################################
-
-XBOXUSB	KEYWORD1
-XBOXONE	KEYWORD1
-XBOXOLD	KEYWORD1
-XBOXRECV	KEYWORD1
-
-####################################################
-# Methods and Functions (KEYWORD2)
-####################################################
-
-setLedRaw	KEYWORD2
-setLedBlink	KEYWORD2
-setLedMode	KEYWORD2
-getBatteryLevel	KEYWORD2
-buttonChanged	KEYWORD2
-
-XboxReceiverConnected	KEYWORD2
-Xbox360Connected	KEYWORD2
-XboxOneConnected	KEYWORD2
-
-####################################################
-# Constants and enums (LITERAL1)
-####################################################
-
-ALL	LITERAL1
-
-ROTATING	LITERAL1
-FASTBLINK	LITERAL1
-SLOWBLINK	LITERAL1
-ALTERNATING	LITERAL1
-
-BACK	LITERAL1
-
-XBOX	LITERAL1
-SYNC	LITERAL1
-
-BLACK	LITERAL1
-WHITE	LITERAL1
-
-A	LITERAL1
-B	LITERAL1
-X	LITERAL1
-Y	LITERAL1
-
-####################################################
-# Syntax Coloring Map For RFCOMM/SPP Library
-####################################################
-
-####################################################
-# Datatypes (KEYWORD1)
-####################################################
-
-SPP	KEYWORD1
-
-####################################################
-# Methods and Functions (KEYWORD2)
-####################################################
-
-connected	KEYWORD2
-discard	KEYWORD2
-
-####################################################
-# Syntax Coloring Map For Wiimote Library
-####################################################
-
-####################################################
-# Datatypes (KEYWORD1)
-####################################################
-
-WII	KEYWORD1
-
-####################################################
-# Methods and Functions (KEYWORD2)
-####################################################
-
-wiimoteConnected	KEYWORD2
-nunchuckConnected	KEYWORD2
-motionPlusConnected	KEYWORD2
-wiiUProControllerConnected	KEYWORD2
-wiiBalanceBoardConnected	KEYWORD2
-setRumbleToggle	KEYWORD2
-getPitch	KEYWORD2
-getRoll	KEYWORD2
-getYaw	KEYWORD2
-getWiimotePitch	KEYWORD2
-getWiimoteRoll	KEYWORD2
-getNunchuckPitch	KEYWORD2
-getNunchuckRoll	KEYWORD2
-PAIR	KEYWORD2
-statusRequest	KEYWORD2
-getBatteryLevel	KEYWORD2
-getWiiState	KEYWORD2
-getWeight	KEYWORD2
-getTotalWeight	KEYWORD2
-getWeightRaw	KEYWORD2
-
-####################################################
-# Constants and enums (LITERAL1)
-####################################################
-
-PLUS	LITERAL1
-MINUS	LITERAL1
-ONE	LITERAL1
-TWO	LITERAL1
-HOME	LITERAL1
-Z	LITERAL1
-C	LITERAL1
-L	LITERAL1
-R	LITERAL1
-ZL	LITERAL1
-ZR	LITERAL1
-HatX	LITERAL1
-HatY	LITERAL1
-TopRight	LITERAL1
-BotRight	LITERAL1
-TopLeft	LITERAL1
-BotLeft	LITERAL1
-
-####################################################
-# Methods and Functions for the IR Camera
-####################################################
-
-IRinitialize	KEYWORD2
-isIRCameraEnabled	KEYWORD2
-getIRx1	KEYWORD2
-getIRy1	KEYWORD2
-getIRs1	KEYWORD2
-getIRx2	KEYWORD2
-getIRy2	KEYWORD2
-getIRs2	KEYWORD2
-getIRx3	KEYWORD2
-getIRy3	KEYWORD2
-getIRs3	KEYWORD2
-getIRx4	KEYWORD2
-getIRy4	KEYWORD2
-getIRs4	KEYWORD2
-
-####################################################
-# Syntax Coloring Map For BTHID Library
-####################################################
-
-####################################################
-# Datatypes (KEYWORD1)
-####################################################
-
-BTHID	KEYWORD1
-
-####################################################
-# Methods and Functions (KEYWORD2)
-####################################################
-SetReportParser	KEYWORD2
-setProtocolMode	KEYWORD2
-
-####################################################
-# Syntax Coloring Map For PS Buzz Library
-####################################################
-
-####################################################
-# Datatypes (KEYWORD1)
-####################################################
-
-PSBuzz	KEYWORD1
-
-####################################################
-# Methods and Functions (KEYWORD2)
-####################################################
-
-setLedOnAll	KEYWORD2
-setLedOffAll	KEYWORD2
-
-####################################################
-# Constants and enums (LITERAL1)
-####################################################
-
-RED	LITERAL1
-YELLOW	LITERAL1
-GREEN	LITERAL1
-ORANGE	LITERAL1
-BLUE	LITERAL1
diff --git a/lib/usbhost/USB_Host_Shield_2.0/library.json b/lib/usbhost/USB_Host_Shield_2.0/library.json
deleted file mode 100644
index 1d649b1e13..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/library.json
+++ /dev/null
@@ -1,47 +0,0 @@
-{
-  "name": "USB-Host-Shield-20",
-  "keywords": "usb, host, ftdi, adk, acm, pl2303, hid, bluetooth, spp, ps3, ps4, buzz, xbox, wii, mass storage",
-  "description": "Revision 2.0 of MAX3421E-based USB Host Shield Library",
-  "authors":
-  [
-    {
-      "name": "Oleg Mazurov",
-      "email": "mazurov@circuitsathome.com",
-      "url": "http://www.circuitsathome.com",
-      "maintainer": true
-    },
-    {
-      "name": "Alexei Glushchenko",
-      "email": "alex-gl@mail.ru"
-    },
-    {
-      "name": "Kristian Lauszus",
-      "email": "kristianl@tkjelectronics.com",
-      "url": "http://tkjelectronics.com",
-      "maintainer": true
-    },
-    {
-      "name": "Andrew Kroll",
-      "email": "xxxajk@gmail.com",
-      "maintainer": true
-    }
-  ],
-  "repository":
-  {
-    "type": "git",
-    "url": "https://github.com/felis/USB_Host_Shield_2.0.git"
-  },
-  "examples":
-  [
-  	"examples/*/*.ino",
-  	"examples/*/*/*.ino"
-  ],
-  "frameworks": "arduino",
-  "platforms":
-  [
-    "atmelavr",
-    "teensy",
-    "atmelsam",
-    "nordicnrf51"
-  ]
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/library.properties b/lib/usbhost/USB_Host_Shield_2.0/library.properties
deleted file mode 100644
index 7881b05e9d..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/library.properties
+++ /dev/null
@@ -1,9 +0,0 @@
-name=USB Host Shield Library 2.0
-version=1.1.0
-author=Oleg Mazurov (Circuits@Home) <mazurov@circuitsathome.com>, Kristian Lauszus (TKJ Electronics) <kristianl@tkjelectronics.com>, Andrew Kroll <xxxajk@gmail.com>, Alexei Glushchenko (Circuits@Home) <alex-gl@mail.ru>
-maintainer=Oleg Mazurov (Circuits@Home) <mazurov@circuitsathome.com>, Kristian Lauszus (TKJ Electronics) <kristianl@tkjelectronics.com>, Andrew Kroll <xxxajk@gmail.com>
-sentence=Revision 2.0 of MAX3421E-based USB Host Shield Library.
-paragraph=Supports HID devices, FTDI, ADK, ACM, PL2303, Bluetooth HID devices, SPP communication and mass storage devices. Furthermore it supports PS3, PS4, PS Buzz, Wii and Xbox controllers.
-category=Other
-url=https://github.com/felis/USB_Host_Shield_2.0
-architectures=*
\ No newline at end of file
diff --git a/lib/usbhost/USB_Host_Shield_2.0/macros.h b/lib/usbhost/USB_Host_Shield_2.0/macros.h
deleted file mode 100644
index e14a711fab..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/macros.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#if !defined(_usb_h_) || defined(MACROS_H)
-#error "Never include macros.h directly; include Usb.h instead"
-#else
-#define MACROS_H
-
-////////////////////////////////////////////////////////////////////////////////
-// HANDY MACROS
-////////////////////////////////////////////////////////////////////////////////
-
-#define VALUE_BETWEEN(v,l,h) (((v)>(l)) && ((v)<(h)))
-#define VALUE_WITHIN(v,l,h) (((v)>=(l)) && ((v)<=(h)))
-#define output_pgm_message(wa,fp,mp,el) wa = &mp, fp((char *)pgm_read_pointer(wa), el)
-#define output_if_between(v,l,h,wa,fp,mp,el) if(VALUE_BETWEEN(v,l,h)) output_pgm_message(wa,fp,mp[v-(l+1)],el);
-
-#define SWAP(a, b) (((a) ^= (b)), ((b) ^= (a)), ((a) ^= (b)))
-#ifndef __BYTE_GRABBING_DEFINED__
-#define __BYTE_GRABBING_DEFINED__ 1
-#ifdef BROKEN_OPTIMIZER_LITTLE_ENDIAN
-// Note: Use this if your compiler generates horrible assembler!
-#define BGRAB0(__usi__)  (((uint8_t *)&(__usi__))[0])
-#define BGRAB1(__usi__)  (((uint8_t *)&(__usi__))[1])
-#define BGRAB2(__usi__)  (((uint8_t *)&(__usi__))[2])
-#define BGRAB3(__usi__)  (((uint8_t *)&(__usi__))[3])
-#define BGRAB4(__usi__)  (((uint8_t *)&(__usi__))[4])
-#define BGRAB5(__usi__)  (((uint8_t *)&(__usi__))[5])
-#define BGRAB6(__usi__)  (((uint8_t *)&(__usi__))[6])
-#define BGRAB7(__usi__)  (((uint8_t *)&(__usi__))[7])
-#else
-// Note: The cast alone to uint8_t is actually enough.
-// GCC throws out the "& 0xff", and the size is no different.
-// Some compilers need it.
-#define BGRAB0(__usi__)  ((uint8_t)((__usi__) & 0xff ))
-#define BGRAB1(__usi__)  ((uint8_t)(((__usi__) >> 8) & 0xff))
-#define BGRAB2(__usi__)  ((uint8_t)(((__usi__) >> 16) & 0xff))
-#define BGRAB3(__usi__)  ((uint8_t)(((__usi__) >> 24) & 0xff))
-#define BGRAB4(__usi__)  ((uint8_t)(((__usi__) >> 32) & 0xff))
-#define BGRAB5(__usi__)  ((uint8_t)(((__usi__) >> 40) & 0xff))
-#define BGRAB6(__usi__)  ((uint8_t)(((__usi__) >> 48) & 0xff))
-#define BGRAB7(__usi__)  ((uint8_t)(((__usi__) >> 56) & 0xff))
-#endif
-#define BOVER1(__usi__)  ((uint16_t)(__usi__) << 8)
-#define BOVER2(__usi__)  ((uint32_t)(__usi__) << 16)
-#define BOVER3(__usi__)  ((uint32_t)(__usi__) << 24)
-#define BOVER4(__usi__)  ((uint64_t)(__usi__) << 32)
-#define BOVER5(__usi__)  ((uint64_t)(__usi__) << 40)
-#define BOVER6(__usi__)  ((uint64_t)(__usi__) << 48)
-#define BOVER7(__usi__)  ((uint64_t)(__usi__) << 56)
-
-// These are the smallest and fastest ways I have found so far in pure C/C++.
-#define BMAKE16(__usc1__,__usc0__) ((uint16_t)((uint16_t)(__usc0__) | (uint16_t)BOVER1(__usc1__)))
-#define BMAKE32(__usc3__,__usc2__,__usc1__,__usc0__) ((uint32_t)((uint32_t)(__usc0__) | (uint32_t)BOVER1(__usc1__) | (uint32_t)BOVER2(__usc2__) | (uint32_t)BOVER3(__usc3__)))
-#define BMAKE64(__usc7__,__usc6__,__usc5__,__usc4__,__usc3__,__usc2__,__usc1__,__usc0__) ((uint64_t)((uint64_t)__usc0__ | (uint64_t)BOVER1(__usc1__) | (uint64_t)BOVER2(__usc2__) | (uint64_t)BOVER3(__usc3__) | (uint64_t)BOVER4(__usc4__) | (uint64_t)BOVER5(__usc5__) | (uint64_t)BOVER6(__usc6__) | (uint64_t)BOVER1(__usc7__)))
-#endif
-
-/*
- * Debug macros: Strings are stored in progmem (flash) instead of RAM.
- */
-#define USBTRACE(s) (Notify(PSTR(s), 0x80))
-#define USBTRACE1(s,l) (Notify(PSTR(s), l))
-#define USBTRACE2(s,r) (Notify(PSTR(s), 0x80), D_PrintHex((r), 0x80), Notify(PSTR("\r\n"), 0x80))
-#define USBTRACE3(s,r,l) (Notify(PSTR(s), l), D_PrintHex((r), l), Notify(PSTR("\r\n"), l))
-
-
-#endif /* MACROS_H */
-
diff --git a/lib/usbhost/USB_Host_Shield_2.0/masstorage.cpp b/lib/usbhost/USB_Host_Shield_2.0/masstorage.cpp
deleted file mode 100644
index 9299f71a43..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/masstorage.cpp
+++ /dev/null
@@ -1,1266 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#include "masstorage.h"
-
-const uint8_t BulkOnly::epDataInIndex = 1;
-const uint8_t BulkOnly::epDataOutIndex = 2;
-const uint8_t BulkOnly::epInterruptInIndex = 3;
-
-////////////////////////////////////////////////////////////////////////////////
-
-// Interface code
-
-////////////////////////////////////////////////////////////////////////////////
-
-/**
- * Get the capacity of the media
- *
- * @param lun Logical Unit Number
- * @return media capacity
- */
-uint32_t BulkOnly::GetCapacity(uint8_t lun) {
-        if(LUNOk[lun])
-                return CurrentCapacity[lun];
-        return 0LU;
-}
-
-/**
- * Get the sector (block) size used on the media
- *
- * @param lun Logical Unit Number
- * @return media sector size
- */
-uint16_t BulkOnly::GetSectorSize(uint8_t lun) {
-        if(LUNOk[lun])
-                return CurrentSectorSize[lun];
-        return 0U;
-}
-
-/**
- * Test if LUN is ready for use
- *
- * @param lun Logical Unit Number
- * @return true if LUN is ready for use
- */
-bool BulkOnly::LUNIsGood(uint8_t lun) {
-        return LUNOk[lun];
-}
-
-/**
- * Test if LUN is write protected
- *
- * @param lun Logical Unit Number
- * @return cached status of write protect switch
- */
-bool BulkOnly::WriteProtected(uint8_t lun) {
-        return WriteOk[lun];
-}
-
-/**
- * Wrap and execute a SCSI CDB with length of 6
- *
- * @param cdb CDB to execute
- * @param buf_size Size of expected transaction
- * @param buf Buffer
- * @param dir MASS_CMD_DIR_IN | MASS_CMD_DIR_OUT
- * @return
- */
-uint8_t BulkOnly::SCSITransaction6(CDB6_t *cdb, uint16_t buf_size, void *buf, uint8_t dir) {
-        // promote buf_size to 32bits.
-        CommandBlockWrapper cbw = CommandBlockWrapper(++dCBWTag, (uint32_t)buf_size, cdb, dir);
-        //SetCurLUN(cdb->LUN);
-        return (HandleSCSIError(Transaction(&cbw, buf_size, buf)));
-}
-
-/**
- * Wrap and execute a SCSI CDB with length of 10
- *
- * @param cdb CDB to execute
- * @param buf_size Size of expected transaction
- * @param buf Buffer
- * @param dir MASS_CMD_DIR_IN | MASS_CMD_DIR_OUT
- * @return
- */
-uint8_t BulkOnly::SCSITransaction10(CDB10_t *cdb, uint16_t buf_size, void *buf, uint8_t dir) {
-        // promote buf_size to 32bits.
-        CommandBlockWrapper cbw = CommandBlockWrapper(++dCBWTag, (uint32_t)buf_size, cdb, dir);
-        //SetCurLUN(cdb->LUN);
-        return (HandleSCSIError(Transaction(&cbw, buf_size, buf)));
-}
-
-/**
- * Lock or Unlock the tray or door on device.
- * Caution: Some devices with buggy firmware will lock up.
- *
- * @param lun Logical Unit Number
- * @param lock 1 to lock, 0 to unlock
- * @return
- */
-uint8_t BulkOnly::LockMedia(uint8_t lun, uint8_t lock) {
-        Notify(PSTR("\r\nLockMedia\r\n"), 0x80);
-        Notify(PSTR("---------\r\n"), 0x80);
-
-        CDB6_t cdb = CDB6_t(SCSI_CMD_PREVENT_REMOVAL, lun, (uint8_t)0, lock);
-        return SCSITransaction6(&cdb, (uint16_t)0, NULL, (uint8_t)MASS_CMD_DIR_IN);
-}
-
-/**
- * Media control, for spindle motor and media tray or door.
- * This includes CDROM, TAPE and anything with a media loader.
- *
- * @param lun Logical Unit Number
- * @param ctl 0x00 Stop Motor, 0x01 Start Motor, 0x02 Eject Media, 0x03 Load Media
- * @return 0 on success
- */
-uint8_t BulkOnly::MediaCTL(uint8_t lun, uint8_t ctl) {
-        Notify(PSTR("\r\nMediaCTL\r\n"), 0x80);
-        Notify(PSTR("-----------------\r\n"), 0x80);
-
-        uint8_t rcode = MASS_ERR_UNIT_NOT_READY;
-        if(bAddress) {
-                CDB6_t cdb = CDB6_t(SCSI_CMD_START_STOP_UNIT, lun, ctl & 0x03, 0);
-                rcode = SCSITransaction6(&cdb, (uint16_t)0, NULL, (uint8_t)MASS_CMD_DIR_OUT);
-        } else {
-                SetCurLUN(lun);
-        }
-        return rcode;
-}
-
-/**
- * Read data from media
- *
- * @param lun Logical Unit Number
- * @param addr LBA address on media to read
- * @param bsize size of a block (we should probably use the cached size)
- * @param blocks how many blocks to read
- * @param buf memory that is able to hold the requested data
- * @return 0 on success
- */
-uint8_t BulkOnly::Read(uint8_t lun, uint32_t addr, uint16_t bsize, uint8_t blocks, uint8_t *buf) {
-        if(!LUNOk[lun]) return MASS_ERR_NO_MEDIA;
-        Notify(PSTR("\r\nRead LUN:\t"), 0x80);
-        D_PrintHex<uint8_t > (lun, 0x90);
-        Notify(PSTR("\r\nLBA:\t\t"), 0x90);
-        D_PrintHex<uint32_t > (addr, 0x90);
-        Notify(PSTR("\r\nblocks:\t\t"), 0x90);
-        D_PrintHex<uint8_t > (blocks, 0x90);
-        Notify(PSTR("\r\nblock size:\t"), 0x90);
-        D_PrintHex<uint16_t > (bsize, 0x90);
-        Notify(PSTR("\r\n---------\r\n"), 0x80);
-        CDB10_t cdb = CDB10_t(SCSI_CMD_READ_10, lun, blocks, addr);
-
-again:
-        uint8_t er = SCSITransaction10(&cdb, ((uint16_t)bsize * blocks), buf, (uint8_t)MASS_CMD_DIR_IN);
-
-        if(er == MASS_ERR_STALL) {
-                MediaCTL(lun, 1);
-                delay(150);
-                if(!TestUnitReady(lun)) goto again;
-        }
-        return er;
-}
-
-/**
- * Write data to media
- *
- * @param lun Logical Unit Number
- * @param addr LBA address on media to write
- * @param bsize size of a block (we should probably use the cached size)
- * @param blocks how many blocks to write
- * @param buf memory that contains the data to write
- * @return 0 on success
- */
-uint8_t BulkOnly::Write(uint8_t lun, uint32_t addr, uint16_t bsize, uint8_t blocks, const uint8_t * buf) {
-        if(!LUNOk[lun]) return MASS_ERR_NO_MEDIA;
-        if(!WriteOk[lun]) return MASS_ERR_WRITE_PROTECTED;
-        Notify(PSTR("\r\nWrite LUN:\t"), 0x80);
-        D_PrintHex<uint8_t > (lun, 0x90);
-        Notify(PSTR("\r\nLBA:\t\t"), 0x90);
-        D_PrintHex<uint32_t > (addr, 0x90);
-        Notify(PSTR("\r\nblocks:\t\t"), 0x90);
-        D_PrintHex<uint8_t > (blocks, 0x90);
-        Notify(PSTR("\r\nblock size:\t"), 0x90);
-        D_PrintHex<uint16_t > (bsize, 0x90);
-        Notify(PSTR("\r\n---------\r\n"), 0x80);
-        CDB10_t cdb = CDB10_t(SCSI_CMD_WRITE_10, lun, blocks, addr);
-
-again:
-        uint8_t er = SCSITransaction10(&cdb, ((uint16_t)bsize * blocks), (void*)buf, (uint8_t)MASS_CMD_DIR_OUT);
-
-        if(er == MASS_ERR_WRITE_STALL) {
-                MediaCTL(lun, 1);
-                delay(150);
-                if(!TestUnitReady(lun)) goto again;
-        }
-        return er;
-}
-
-// End of user functions, the remaining code below is driver internals.
-// Only developer serviceable parts below!
-
-////////////////////////////////////////////////////////////////////////////////
-
-// Main driver code
-
-////////////////////////////////////////////////////////////////////////////////
-
-BulkOnly::BulkOnly(USB *p) :
-pUsb(p),
-bAddress(0),
-bIface(0),
-bNumEP(1),
-qNextPollTime(0),
-bPollEnable(false),
-//dCBWTag(0),
-bLastUsbError(0) {
-        ClearAllEP();
-        dCBWTag = 0;
-        if(pUsb)
-                pUsb->RegisterDeviceClass(this);
-}
-
-/**
- * USB_ERROR_CONFIG_REQUIRES_ADDITIONAL_RESET == success
- * We need to standardize either the rcode, or change the API to return values
- * so a signal that additional actions are required can be produced.
- * Some of these codes do exist already.
- *
- * TECHNICAL: We could do most of this code elsewhere, with the exception of checking the class instance.
- * Doing so would save some program memory when using multiple drivers.
- *
- * @param parent USB address of parent
- * @param port address of port on parent
- * @param lowspeed true if device is low speed
- * @return
- */
-uint8_t BulkOnly::ConfigureDevice(uint8_t parent, uint8_t port, bool lowspeed) {
-
-        const uint8_t constBufSize = sizeof (USB_DEVICE_DESCRIPTOR);
-
-        uint8_t buf[constBufSize];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        USBTRACE("MS ConfigureDevice\r\n");
-        ClearAllEP();
-        AddressPool &addrPool = pUsb->GetAddressPool();
-
-
-        if(bAddress)
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-
-        // <TECHNICAL>
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-        if(!p) {
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-        }
-
-        if(!p->epinfo) {
-                USBTRACE("epinfo\r\n");
-                return USB_ERROR_EPINFO_IS_NULL;
-        }
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, constBufSize, (uint8_t*)buf);
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(rcode) {
-                goto FailGetDevDescr;
-        }
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from the device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-        // Steal and abuse from epInfo structure to save on memory.
-        epInfo[1].epAddr = udd->bNumConfigurations;
-        // </TECHNICAL>
-        return USB_ERROR_CONFIG_REQUIRES_ADDITIONAL_RESET;
-
-FailGetDevDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetDevDescr(rcode);
-#endif
-        rcode = USB_ERROR_FailGetDevDescr;
-
-        Release();
-        return rcode;
-};
-
-/**
- *
- * @param parent (not used)
- * @param port (not used)
- * @param lowspeed true if device is low speed
- * @return 0 for success
- */
-uint8_t BulkOnly::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        uint8_t rcode;
-        uint8_t num_of_conf = epInfo[1].epAddr; // number of configurations
-        epInfo[1].epAddr = 0;
-        USBTRACE("MS Init\r\n");
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-        UsbDevice *p = addrPool.GetUsbDevicePtr(bAddress);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        // Assign new address to the device
-        delay(2000);
-        rcode = pUsb->setAddr(0, 0, bAddress);
-
-        if(rcode) {
-                p->lowspeed = false;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                USBTRACE2("setAddr:", rcode);
-                return rcode;
-        }
-
-        USBTRACE2("Addr:", bAddress);
-
-        p->lowspeed = false;
-
-        p = addrPool.GetUsbDevicePtr(bAddress);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        p->lowspeed = lowspeed;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, 1, epInfo);
-
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        USBTRACE2("NC:", num_of_conf);
-
-        for(uint8_t i = 0; i < num_of_conf; i++) {
-                ConfigDescParser< USB_CLASS_MASS_STORAGE,
-                        MASS_SUBCLASS_SCSI,
-                        MASS_PROTO_BBB,
-                        CP_MASK_COMPARE_CLASS |
-                        CP_MASK_COMPARE_SUBCLASS |
-                        CP_MASK_COMPARE_PROTOCOL > BulkOnlyParser(this);
-
-                rcode = pUsb->getConfDescr(bAddress, 0, i, &BulkOnlyParser);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-
-                if(bNumEP > 1)
-                        break;
-        }
-
-        if(bNumEP < 3)
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        // Assign epInfo to epinfo pointer
-        pUsb->setEpInfoEntry(bAddress, bNumEP, epInfo);
-
-        USBTRACE2("Conf:", bConfNum);
-
-        // Set Configuration Value
-        rcode = pUsb->setConf(bAddress, 0, bConfNum);
-
-        if(rcode)
-                goto FailSetConfDescr;
-
-        //Linux does a 1sec delay after this.
-        delay(1000);
-
-        rcode = GetMaxLUN(&bMaxLUN);
-        if(rcode)
-                goto FailGetMaxLUN;
-
-        if(bMaxLUN >= MASS_MAX_SUPPORTED_LUN) bMaxLUN = MASS_MAX_SUPPORTED_LUN - 1;
-        ErrorMessage<uint8_t > (PSTR("MaxLUN"), bMaxLUN);
-
-        delay(1000); // Delay a bit for slow firmware.
-
-        for(uint8_t lun = 0; lun <= bMaxLUN; lun++) {
-                InquiryResponse response;
-                rcode = Inquiry(lun, sizeof (InquiryResponse), (uint8_t*) & response);
-                if(rcode) {
-                        ErrorMessage<uint8_t > (PSTR("Inquiry"), rcode);
-                } else {
-#if 0
-                        printf("LUN %i `", lun);
-                        uint8_t *buf = response.VendorID;
-                        for(int i = 0; i < 28; i++) printf("%c", buf[i]);
-                        printf("'\r\nQualifier %1.1X ", response.PeripheralQualifier);
-                        printf("Device type %2.2X ", response.DeviceType);
-                        printf("RMB %1.1X ", response.Removable);
-                        printf("SSCS %1.1X ", response.SCCS);
-                        uint8_t sv = response.Version;
-                        printf("SCSI version %2.2X\r\nDevice conforms to ", sv);
-                        switch(sv) {
-                                case 0:
-                                        printf("No specific");
-                                        break;
-                                case 1:
-                                        printf("ANSI X3.131-1986 (ANSI 1)");
-                                        break;
-                                case 2:
-                                        printf("ANSI X3.131-1994 (ANSI 2)");
-                                        break;
-                                case 3:
-                                        printf("ANSI INCITS 301-1997 (SPC)");
-                                        break;
-                                case 4:
-                                        printf("ANSI INCITS 351-2001 (SPC-2)");
-                                        break;
-                                case 5:
-                                        printf("ANSI INCITS 408-2005 (SPC-4)");
-                                        break;
-                                case 6:
-                                        printf("T10/1731-D (SPC-4)");
-                                        break;
-                                default:
-                                        printf("unknown");
-                        }
-                        printf(" standards.\r\n");
-#endif
-                        uint8_t tries = 0xf0;
-                        while((rcode = TestUnitReady(lun))) {
-                                if(rcode == 0x08) break; // break on no media, this is OK to do.
-                                // try to lock media and spin up
-                                if(tries < 14) {
-                                        LockMedia(lun, 1);
-                                        MediaCTL(lun, 1); // I actually have a USB stick that needs this!
-                                } else delay(2 * (tries + 1));
-                                tries++;
-                                if(!tries) break;
-                        }
-                        if(!rcode) {
-                                delay(1000);
-                                LUNOk[lun] = CheckLUN(lun);
-                                if(!LUNOk[lun]) LUNOk[lun] = CheckLUN(lun);
-                        }
-                }
-        }
-
-
-        CheckMedia();
-
-        rcode = OnInit();
-
-        if(rcode)
-                goto FailOnInit;
-
-#ifdef DEBUG_USB_HOST
-        USBTRACE("MS configured\r\n\r\n");
-#endif
-
-        bPollEnable = true;
-
-        //USBTRACE("Poll enabled\r\n");
-        return 0;
-
-FailSetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetConfDescr();
-        goto Fail;
-#endif
-
-FailOnInit:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("OnInit:");
-        goto Fail;
-#endif
-
-FailGetMaxLUN:
-#ifdef DEBUG_USB_HOST
-        USBTRACE("GetMaxLUN:");
-        goto Fail;
-#endif
-
-        //#ifdef DEBUG_USB_HOST
-        //FailInvalidSectorSize:
-        //        USBTRACE("Sector Size is NOT VALID: ");
-        //        goto Fail;
-        //#endif
-
-FailSetDevTblEntry:
-#ifdef DEBUG_USB_HOST
-        NotifyFailSetDevTblEntry();
-        goto Fail;
-#endif
-
-FailGetConfDescr:
-#ifdef DEBUG_USB_HOST
-        NotifyFailGetConfDescr();
-#endif
-
-#ifdef DEBUG_USB_HOST
-Fail:
-        NotifyFail(rcode);
-#endif
-        Release();
-        return rcode;
-}
-
-/**
- * For driver use only.
- *
- * @param conf
- * @param iface
- * @param alt
- * @param proto
- * @param pep
- */
-void BulkOnly::EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR * pep) {
-        ErrorMessage<uint8_t > (PSTR("Conf.Val"), conf);
-        ErrorMessage<uint8_t > (PSTR("Iface Num"), iface);
-        ErrorMessage<uint8_t > (PSTR("Alt.Set"), alt);
-
-        bConfNum = conf;
-
-        uint8_t index;
-
-#if 1
-        if((pep->bmAttributes & 0x02) == 2) {
-                index = ((pep->bEndpointAddress & 0x80) == 0x80) ? epDataInIndex : epDataOutIndex;
-                // Fill in the endpoint info structure
-                epInfo[index].epAddr = (pep->bEndpointAddress & 0x0F);
-                epInfo[index].maxPktSize = (uint8_t)pep->wMaxPacketSize;
-                epInfo[index].epAttribs = 0;
-
-                bNumEP++;
-
-                PrintEndpointDescriptor(pep);
-
-        }
-#else
-        if((pep->bmAttributes & 0x03) == 3 && (pep->bEndpointAddress & 0x80) == 0x80)
-                index = epInterruptInIndex;
-        else
-                if((pep->bmAttributes & 0x02) == 2)
-                index = ((pep->bEndpointAddress & 0x80) == 0x80) ? epDataInIndex : epDataOutIndex;
-        else
-                return;
-
-        // Fill in the endpoint info structure
-        epInfo[index].epAddr = (pep->bEndpointAddress & 0x0F);
-        epInfo[index].maxPktSize = (uint8_t)pep->wMaxPacketSize;
-        epInfo[index].epAttribs = 0;
-
-        bNumEP++;
-
-        PrintEndpointDescriptor(pep);
-#endif
-}
-
-/**
- * For driver use only.
- *
- * @return
- */
-uint8_t BulkOnly::Release() {
-        ClearAllEP();
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-        return 0;
-}
-
-/**
- * For driver use only.
- *
- * @param lun Logical Unit Number
- * @return true if LUN is ready for use.
- */
-bool BulkOnly::CheckLUN(uint8_t lun) {
-        uint8_t rcode;
-        Capacity capacity;
-        for(uint8_t i = 0; i < 8; i++) capacity.data[i] = 0;
-
-        rcode = ReadCapacity10(lun, (uint8_t*)capacity.data);
-        if(rcode) {
-                //printf(">>>>>>>>>>>>>>>>ReadCapacity returned %i\r\n", rcode);
-                return false;
-        }
-        ErrorMessage<uint8_t > (PSTR(">>>>>>>>>>>>>>>>CAPACITY OK ON LUN"), lun);
-        for(uint8_t i = 0; i < 8 /*sizeof (Capacity)*/; i++)
-                D_PrintHex<uint8_t > (capacity.data[i], 0x80);
-        Notify(PSTR("\r\n\r\n"), 0x80);
-        // Only 512/1024/2048/4096 are valid values!
-        uint32_t c = BMAKE32(capacity.data[4], capacity.data[5], capacity.data[6], capacity.data[7]);
-        if(c != 0x0200LU && c != 0x0400LU && c != 0x0800LU && c != 0x1000LU) {
-                return false;
-        }
-        // Store capacity information.
-        CurrentSectorSize[lun] = (uint16_t)(c); // & 0xFFFF);
-
-        CurrentCapacity[lun] = BMAKE32(capacity.data[0], capacity.data[1], capacity.data[2], capacity.data[3]) + 1;
-        if(CurrentCapacity[lun] == /*0xffffffffLU */ 0x01LU || CurrentCapacity[lun] == 0x00LU) {
-                // Buggy firmware will report 0xffffffff or 0 for no media
-                if(CurrentCapacity[lun])
-                        ErrorMessage<uint8_t > (PSTR(">>>>>>>>>>>>>>>>BUGGY FIRMWARE. CAPACITY FAIL ON LUN"), lun);
-                return false;
-        }
-        delay(20);
-        Page3F(lun);
-        if(!TestUnitReady(lun)) return true;
-        return false;
-}
-
-/**
- * For driver use only.
- *
- * Scan for media change on all LUNs
- */
-void BulkOnly::CheckMedia() {
-        for(uint8_t lun = 0; lun <= bMaxLUN; lun++) {
-                if(TestUnitReady(lun)) {
-                        LUNOk[lun] = false;
-                        continue;
-                }
-                if(!LUNOk[lun])
-                        LUNOk[lun] = CheckLUN(lun);
-        }
-#if 0
-        printf("}}}}}}}}}}}}}}}}STATUS ");
-        for(uint8_t lun = 0; lun <= bMaxLUN; lun++) {
-                if(LUNOk[lun])
-                        printf("#");
-                else printf(".");
-        }
-        printf("\r\n");
-#endif
-        qNextPollTime = millis() + 2000;
-}
-
-/**
- * For driver use only.
- *
- * @return
- */
-uint8_t BulkOnly::Poll() {
-        //uint8_t rcode = 0;
-
-        if(!bPollEnable)
-                return 0;
-
-        if((long)(millis() - qNextPollTime) >= 0L) {
-                CheckMedia();
-        }
-        //rcode = 0;
-
-        return 0;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-
-
-// SCSI code
-
-
-////////////////////////////////////////////////////////////////////////////////
-
-/**
- * For driver use only.
- *
- * @param plun
- * @return
- */
-uint8_t BulkOnly::GetMaxLUN(uint8_t *plun) {
-        uint8_t ret = pUsb->ctrlReq(bAddress, 0, bmREQ_MASSIN, MASS_REQ_GET_MAX_LUN, 0, 0, bIface, 1, 1, plun, NULL);
-
-        if(ret == hrSTALL)
-                *plun = 0;
-
-        return 0;
-}
-
-/**
- * For driver use only. Used during Driver Init
- *
- * @param lun Logical Unit Number
- * @param bsize
- * @param buf
- * @return
- */
-uint8_t BulkOnly::Inquiry(uint8_t lun, uint16_t bsize, uint8_t *buf) {
-        Notify(PSTR("\r\nInquiry\r\n"), 0x80);
-        Notify(PSTR("---------\r\n"), 0x80);
-
-        CDB6_t cdb = CDB6_t(SCSI_CMD_INQUIRY, lun, 0LU, (uint8_t)bsize, 0);
-        uint8_t rc = SCSITransaction6(&cdb, bsize, buf, (uint8_t)MASS_CMD_DIR_IN);
-
-        return rc;
-}
-
-/**
- * For driver use only.
- *
- * @param lun Logical Unit Number
- * @return
- */
-uint8_t BulkOnly::TestUnitReady(uint8_t lun) {
-        //SetCurLUN(lun);
-        if(!bAddress)
-                return MASS_ERR_UNIT_NOT_READY;
-
-        Notify(PSTR("\r\nTestUnitReady\r\n"), 0x80);
-        Notify(PSTR("-----------------\r\n"), 0x80);
-
-        CDB6_t cdb = CDB6_t(SCSI_CMD_TEST_UNIT_READY, lun, (uint8_t)0, 0);
-        return SCSITransaction6(&cdb, 0, NULL, (uint8_t)MASS_CMD_DIR_IN);
-
-}
-
-/**
- * For driver use only.
- *
- * @param lun Logical Unit Number
- * @param pc
- * @param page
- * @param subpage
- * @param len
- * @param pbuf
- * @return
- */
-uint8_t BulkOnly::ModeSense6(uint8_t lun, uint8_t pc, uint8_t page, uint8_t subpage, uint8_t len, uint8_t * pbuf) {
-        Notify(PSTR("\r\rModeSense\r\n"), 0x80);
-        Notify(PSTR("------------\r\n"), 0x80);
-
-        CDB6_t cdb = CDB6_t(SCSI_CMD_TEST_UNIT_READY, lun, (uint32_t)((((pc << 6) | page) << 8) | subpage), len, 0);
-        return SCSITransaction6(&cdb, len, pbuf, (uint8_t)MASS_CMD_DIR_IN);
-}
-
-/**
- * For driver use only.
- *
- * @param lun Logical Unit Number
- * @param bsize
- * @param buf
- * @return
- */
-uint8_t BulkOnly::ReadCapacity10(uint8_t lun, uint8_t *buf) {
-        Notify(PSTR("\r\nReadCapacity\r\n"), 0x80);
-        Notify(PSTR("---------------\r\n"), 0x80);
-
-        CDB10_t cdb = CDB10_t(SCSI_CMD_READ_CAPACITY_10, lun);
-        return SCSITransaction10(&cdb, 8, buf, (uint8_t)MASS_CMD_DIR_IN);
-}
-
-/**
- * For driver use only.
- *
- * Page 3F contains write protect status.
- *
- * @param lun Logical Unit Number to test.
- * @return Write protect switch status.
- */
-uint8_t BulkOnly::Page3F(uint8_t lun) {
-        uint8_t buf[192];
-        for(int i = 0; i < 192; i++) {
-                buf[i] = 0x00;
-        }
-        WriteOk[lun] = true;
-        uint8_t rc = ModeSense6(lun, 0, 0x3f, 0, 192, buf);
-        if(!rc) {
-                WriteOk[lun] = ((buf[2] & 0x80) == 0);
-                Notify(PSTR("Mode Sense: "), 0x80);
-                for(int i = 0; i < 4; i++) {
-                        D_PrintHex<uint8_t > (buf[i], 0x80);
-                        Notify(PSTR(" "), 0x80);
-                }
-                Notify(PSTR("\r\n"), 0x80);
-        }
-        return rc;
-}
-
-/**
- * For driver use only.
- *
- * @param lun Logical Unit Number
- * @param size
- * @param buf
- * @return
- */
-uint8_t BulkOnly::RequestSense(uint8_t lun, uint16_t size, uint8_t *buf) {
-        Notify(PSTR("\r\nRequestSense\r\n"), 0x80);
-        Notify(PSTR("----------------\r\n"), 0x80);
-
-        CDB6_t cdb = CDB6_t(SCSI_CMD_REQUEST_SENSE, lun, 0LU, (uint8_t)size, 0);
-        CommandBlockWrapper cbw = CommandBlockWrapper(++dCBWTag, (uint32_t)size, &cdb, (uint8_t)MASS_CMD_DIR_IN);
-        //SetCurLUN(lun);
-        return Transaction(&cbw, size, buf);
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-
-
-// USB code
-
-
-////////////////////////////////////////////////////////////////////////////////
-
-/**
- * For driver use only.
- *
- * @param index
- * @return
- */
-uint8_t BulkOnly::ClearEpHalt(uint8_t index) {
-        if(index == 0)
-                return 0;
-
-        uint8_t ret = 0;
-
-        while((ret = (pUsb->ctrlReq(bAddress, 0, USB_SETUP_HOST_TO_DEVICE | USB_SETUP_TYPE_STANDARD | USB_SETUP_RECIPIENT_ENDPOINT, USB_REQUEST_CLEAR_FEATURE, USB_FEATURE_ENDPOINT_HALT, 0, ((index == epDataInIndex) ? (0x80 | epInfo[index].epAddr) : epInfo[index].epAddr), 0, 0, NULL, NULL)) == 0x01))
-                delay(6);
-
-        if(ret) {
-                ErrorMessage<uint8_t > (PSTR("ClearEpHalt"), ret);
-                ErrorMessage<uint8_t > (PSTR("EP"), ((index == epDataInIndex) ? (0x80 | epInfo[index].epAddr) : epInfo[index].epAddr));
-                return ret;
-        }
-        epInfo[index].bmSndToggle = 0;
-        epInfo[index].bmRcvToggle = 0;
-        // epAttribs = 0;
-        return 0;
-}
-
-/**
- * For driver use only.
- *
- */
-void BulkOnly::Reset() {
-        while(pUsb->ctrlReq(bAddress, 0, bmREQ_MASSOUT, MASS_REQ_BOMSR, 0, 0, bIface, 0, 0, NULL, NULL) == 0x01) delay(6);
-}
-
-/**
- * For driver use only.
- *
- * @return 0 if successful
- */
-uint8_t BulkOnly::ResetRecovery() {
-        Notify(PSTR("\r\nResetRecovery\r\n"), 0x80);
-        Notify(PSTR("-----------------\r\n"), 0x80);
-
-        delay(6);
-        Reset();
-        delay(6);
-        ClearEpHalt(epDataInIndex);
-        delay(6);
-        bLastUsbError = ClearEpHalt(epDataOutIndex);
-        delay(6);
-        return bLastUsbError;
-}
-
-/**
- * For driver use only.
- *
- * Clear all EP data and clear all LUN status
- */
-void BulkOnly::ClearAllEP() {
-        for(uint8_t i = 0; i < MASS_MAX_ENDPOINTS; i++) {
-                epInfo[i].epAddr = 0;
-                epInfo[i].maxPktSize = (i) ? 0 : 8;
-                epInfo[i].epAttribs = 0;
-
-                epInfo[i].bmNakPower = USB_NAK_DEFAULT;
-        }
-
-        for(uint8_t i = 0; i < MASS_MAX_SUPPORTED_LUN; i++) {
-                LUNOk[i] = false;
-                WriteOk[i] = false;
-                CurrentCapacity[i] = 0lu;
-                CurrentSectorSize[i] = 0;
-        }
-
-        bIface = 0;
-        bNumEP = 1;
-        bAddress = 0;
-        qNextPollTime = 0;
-        bPollEnable = false;
-        bLastUsbError = 0;
-        bMaxLUN = 0;
-        bTheLUN = 0;
-}
-
-/**
- * For driver use only.
- *
- * @param pcsw
- * @param pcbw
- * @return
- */
-bool BulkOnly::IsValidCSW(CommandStatusWrapper *pcsw, CommandBlockWrapperBase *pcbw) {
-        if(pcsw->dCSWSignature != MASS_CSW_SIGNATURE) {
-                Notify(PSTR("CSW:Sig error\r\n"), 0x80);
-                return false;
-        }
-        if(pcsw->dCSWTag != pcbw->dCBWTag) {
-                Notify(PSTR("CSW:Wrong tag\r\n"), 0x80);
-                return false;
-        }
-        return true;
-}
-
-/**
- * For driver use only.
- *
- * @param error
- * @param index
- * @return
- */
-uint8_t BulkOnly::HandleUsbError(uint8_t error, uint8_t index) {
-        uint8_t count = 3;
-
-        bLastUsbError = error;
-        //if (error)
-        //ClearEpHalt(index);
-        while(error && count) {
-                if(error != hrSUCCESS) {
-                        ErrorMessage<uint8_t > (PSTR("USB Error"), error);
-                        ErrorMessage<uint8_t > (PSTR("Index"), index);
-                }
-                switch(error) {
-                                // case hrWRONGPID:
-                        case hrSUCCESS:
-                                return MASS_ERR_SUCCESS;
-                        case hrBUSY:
-                                // SIE is busy, just hang out and try again.
-                                return MASS_ERR_UNIT_BUSY;
-                        case hrTIMEOUT:
-                        case hrJERR: return MASS_ERR_DEVICE_DISCONNECTED;
-                        case hrSTALL:
-                                if(index == 0)
-                                        return MASS_ERR_STALL;
-                                ClearEpHalt(index);
-                                if(index != epDataInIndex)
-                                        return MASS_ERR_WRITE_STALL;
-                                return MASS_ERR_STALL;
-
-                        case hrNAK:
-                                if(index == 0)
-                                        return MASS_ERR_UNIT_BUSY;
-                                return MASS_ERR_UNIT_BUSY;
-
-                        case hrTOGERR:
-                                // Handle a very super rare corner case, where toggles become de-synched.
-                                // I have only ran into one device that has this firmware bug, and this is
-                                // the only clean way to get back into sync with the buggy device firmware.
-                                //   --AJK
-                                if(bAddress && bConfNum) {
-                                        error = pUsb->setConf(bAddress, 0, bConfNum);
-
-                                        if(error)
-                                                break;
-                                }
-                                return MASS_ERR_SUCCESS;
-                        default:
-                                ErrorMessage<uint8_t > (PSTR("\r\nUSB"), error);
-                                return MASS_ERR_GENERAL_USB_ERROR;
-                }
-                count--;
-        } // while
-
-        return ((error && !count) ? MASS_ERR_GENERAL_USB_ERROR : MASS_ERR_SUCCESS);
-}
-
-#if MS_WANT_PARSER
-
-uint8_t BulkOnly::Transaction(CommandBlockWrapper *pcbw, uint16_t buf_size, void *buf) {
-        return Transaction(CommandBlockWrapper *pcbw, uint16_t buf_size, void *buf, 0);
-}
-#endif
-
-/**
- * For driver use only.
- *
- * @param pcbw
- * @param buf_size
- * @param buf
- * @param flags
- * @return
- */
-uint8_t BulkOnly::Transaction(CommandBlockWrapper *pcbw, uint16_t buf_size, void *buf
-#if MS_WANT_PARSER
-        , uint8_t flags
-#endif
-        ) {
-
-#if MS_WANT_PARSER
-        uint16_t bytes = (pcbw->dCBWDataTransferLength > buf_size) ? buf_size : pcbw->dCBWDataTransferLength;
-        printf("Transfersize %i\r\n", bytes);
-        delay(1000);
-
-        bool callback = (flags & MASS_TRANS_FLG_CALLBACK) == MASS_TRANS_FLG_CALLBACK;
-#else
-        uint16_t bytes = buf_size;
-#endif
-        bool write = (pcbw->bmCBWFlags & MASS_CMD_DIR_IN) != MASS_CMD_DIR_IN;
-        uint8_t ret = 0;
-        uint8_t usberr;
-        CommandStatusWrapper csw; // up here, we allocate ahead to save cpu cycles.
-        SetCurLUN(pcbw->bmCBWLUN);
-        ErrorMessage<uint32_t > (PSTR("CBW.dCBWTag"), pcbw->dCBWTag);
-
-        while((usberr = pUsb->outTransfer(bAddress, epInfo[epDataOutIndex].epAddr, sizeof (CommandBlockWrapper), (uint8_t*)pcbw)) == hrBUSY) delay(1);
-
-        ret = HandleUsbError(usberr, epDataOutIndex);
-        //ret = HandleUsbError(pUsb->outTransfer(bAddress, epInfo[epDataOutIndex].epAddr, sizeof (CommandBlockWrapper), (uint8_t*)pcbw), epDataOutIndex);
-        if(ret) {
-                ErrorMessage<uint8_t > (PSTR("============================ CBW"), ret);
-        } else {
-                if(bytes) {
-                        if(!write) {
-#if MS_WANT_PARSER
-                                if(callback) {
-                                        uint8_t rbuf[bytes];
-                                        while((usberr = pUsb->inTransfer(bAddress, epInfo[epDataInIndex].epAddr, &bytes, rbuf)) == hrBUSY) delay(1);
-                                        if(usberr == hrSUCCESS) ((USBReadParser*)buf)->Parse(bytes, rbuf, 0);
-                                } else {
-#endif
-                                        while((usberr = pUsb->inTransfer(bAddress, epInfo[epDataInIndex].epAddr, &bytes, (uint8_t*)buf)) == hrBUSY) delay(1);
-#if MS_WANT_PARSER
-
-                                }
-#endif
-                                ret = HandleUsbError(usberr, epDataInIndex);
-                        } else {
-                                while((usberr = pUsb->outTransfer(bAddress, epInfo[epDataOutIndex].epAddr, bytes, (uint8_t*)buf)) == hrBUSY) delay(1);
-                                ret = HandleUsbError(usberr, epDataOutIndex);
-                        }
-                        if(ret) {
-                                ErrorMessage<uint8_t > (PSTR("============================ DAT"), ret);
-                        }
-                }
-        }
-
-        {
-                bytes = sizeof (CommandStatusWrapper);
-                int tries = 2;
-                while(tries--) {
-                        while((usberr = pUsb->inTransfer(bAddress, epInfo[epDataInIndex].epAddr, &bytes, (uint8_t*) & csw)) == hrBUSY) delay(1);
-                        if(!usberr) break;
-                        ClearEpHalt(epDataInIndex);
-                        if(tries) ResetRecovery();
-                }
-                if(!ret) {
-                        Notify(PSTR("CBW:\t\tOK\r\n"), 0x80);
-                        Notify(PSTR("Data Stage:\tOK\r\n"), 0x80);
-                } else {
-                        // Throw away csw, IT IS NOT OF ANY USE.
-                        ResetRecovery();
-                        return ret;
-                }
-                ret = HandleUsbError(usberr, epDataInIndex);
-                if(ret) {
-                        ErrorMessage<uint8_t > (PSTR("============================ CSW"), ret);
-                }
-                if(usberr == hrSUCCESS) {
-                        if(IsValidCSW(&csw, pcbw)) {
-                                //ErrorMessage<uint32_t > (PSTR("CSW.dCBWTag"), csw.dCSWTag);
-                                //ErrorMessage<uint8_t > (PSTR("bCSWStatus"), csw.bCSWStatus);
-                                //ErrorMessage<uint32_t > (PSTR("dCSWDataResidue"), csw.dCSWDataResidue);
-                                Notify(PSTR("CSW:\t\tOK\r\n\r\n"), 0x80);
-                                return csw.bCSWStatus;
-                        } else {
-                                // NOTE! Sometimes this is caused by the reported residue being wrong.
-                                // Get a different device. It isn't compliant, and should have never passed Q&A.
-                                // I own one... 05e3:0701 Genesys Logic, Inc. USB 2.0 IDE Adapter.
-                                // Other devices that exhibit this behavior exist in the wild too.
-                                // Be sure to check quirks in the Linux source code before reporting a bug. --xxxajk
-                                Notify(PSTR("Invalid CSW\r\n"), 0x80);
-                                ResetRecovery();
-                                //return MASS_ERR_SUCCESS;
-                                return MASS_ERR_INVALID_CSW;
-                        }
-                }
-        }
-        return ret;
-}
-
-/**
- * For driver use only.
- *
- * @param lun Logical Unit Number
- * @return
- */
-uint8_t BulkOnly::SetCurLUN(uint8_t lun) {
-        if(lun > bMaxLUN)
-                return MASS_ERR_INVALID_LUN;
-        bTheLUN = lun;
-        return MASS_ERR_SUCCESS;
-};
-
-/**
- * For driver use only.
- *
- * @param status
- * @return
- */
-uint8_t BulkOnly::HandleSCSIError(uint8_t status) {
-        uint8_t ret = 0;
-
-        switch(status) {
-                case 0: return MASS_ERR_SUCCESS;
-
-                case 2:
-                        ErrorMessage<uint8_t > (PSTR("Phase Error"), status);
-                        ErrorMessage<uint8_t > (PSTR("LUN"), bTheLUN);
-                        ResetRecovery();
-                        return MASS_ERR_GENERAL_SCSI_ERROR;
-
-                case 1:
-                        ErrorMessage<uint8_t > (PSTR("SCSI Error"), status);
-                        ErrorMessage<uint8_t > (PSTR("LUN"), bTheLUN);
-                        RequestSenseResponce rsp;
-
-                        ret = RequestSense(bTheLUN, sizeof (RequestSenseResponce), (uint8_t*) & rsp);
-
-                        if(ret) {
-                                return MASS_ERR_GENERAL_SCSI_ERROR;
-                        }
-                        ErrorMessage<uint8_t > (PSTR("Response Code"), rsp.bResponseCode);
-                        if(rsp.bResponseCode & 0x80) {
-                                Notify(PSTR("Information field: "), 0x80);
-                                for(int i = 0; i < 4; i++) {
-                                        D_PrintHex<uint8_t > (rsp.CmdSpecificInformation[i], 0x80);
-                                        Notify(PSTR(" "), 0x80);
-                                }
-                                Notify(PSTR("\r\n"), 0x80);
-                        }
-                        ErrorMessage<uint8_t > (PSTR("Sense Key"), rsp.bmSenseKey);
-                        ErrorMessage<uint8_t > (PSTR("Add Sense Code"), rsp.bAdditionalSenseCode);
-                        ErrorMessage<uint8_t > (PSTR("Add Sense Qual"), rsp.bAdditionalSenseQualifier);
-                        // warning, this is not testing ASQ, only SK and ASC.
-                        switch(rsp.bmSenseKey) {
-                                case SCSI_S_UNIT_ATTENTION:
-                                        switch(rsp.bAdditionalSenseCode) {
-                                                case SCSI_ASC_MEDIA_CHANGED:
-                                                        return MASS_ERR_MEDIA_CHANGED;
-                                                default:
-                                                        return MASS_ERR_UNIT_NOT_READY;
-                                        }
-                                case SCSI_S_NOT_READY:
-                                        switch(rsp.bAdditionalSenseCode) {
-                                                case SCSI_ASC_MEDIUM_NOT_PRESENT:
-                                                        return MASS_ERR_NO_MEDIA;
-                                                default:
-                                                        return MASS_ERR_UNIT_NOT_READY;
-                                        }
-                                case SCSI_S_ILLEGAL_REQUEST:
-                                        switch(rsp.bAdditionalSenseCode) {
-                                                case SCSI_ASC_LBA_OUT_OF_RANGE:
-                                                        return MASS_ERR_BAD_LBA;
-                                                default:
-                                                        return MASS_ERR_CMD_NOT_SUPPORTED;
-                                        }
-                                default:
-                                        return MASS_ERR_GENERAL_SCSI_ERROR;
-                        }
-
-                        // case 4: return MASS_ERR_UNIT_BUSY; // Busy means retry later.
-                        //    case 0x05/0x14: we stalled out
-                        //    case 0x15/0x16: we naked out.
-                default:
-                        ErrorMessage<uint8_t > (PSTR("Gen SCSI Err"), status);
-                        ErrorMessage<uint8_t > (PSTR("LUN"), bTheLUN);
-                        return status;
-        } // switch
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-
-
-// Debugging code
-
-
-////////////////////////////////////////////////////////////////////////////////
-
-/**
- *
- * @param ep_ptr
- */
-void BulkOnly::PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR * ep_ptr) {
-        Notify(PSTR("Endpoint descriptor:"), 0x80);
-        Notify(PSTR("\r\nLength:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bLength, 0x80);
-        Notify(PSTR("\r\nType:\t\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bDescriptorType, 0x80);
-        Notify(PSTR("\r\nAddress:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bEndpointAddress, 0x80);
-        Notify(PSTR("\r\nAttributes:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bmAttributes, 0x80);
-        Notify(PSTR("\r\nMaxPktSize:\t"), 0x80);
-        D_PrintHex<uint16_t > (ep_ptr->wMaxPacketSize, 0x80);
-        Notify(PSTR("\r\nPoll Intrv:\t"), 0x80);
-        D_PrintHex<uint8_t > (ep_ptr->bInterval, 0x80);
-        Notify(PSTR("\r\n"), 0x80);
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-
-
-// misc/to kill/to-do
-
-
-////////////////////////////////////////////////////////////////////////////////
-
-/* We won't be needing this... */
-uint8_t BulkOnly::Read(uint8_t lun, uint32_t addr, uint16_t bsize, uint8_t blocks, USBReadParser * prs) {
-#if MS_WANT_PARSER
-        if(!LUNOk[lun]) return MASS_ERR_NO_MEDIA;
-        Notify(PSTR("\r\nRead (With parser)\r\n"), 0x80);
-        Notify(PSTR("---------\r\n"), 0x80);
-
-        CommandBlockWrapper cbw = CommandBlockWrapper();
-
-        cbw.dCBWSignature = MASS_CBW_SIGNATURE;
-        cbw.dCBWTag = ++dCBWTag;
-        cbw.dCBWDataTransferLength = ((uint32_t)bsize * blocks);
-        cbw.bmCBWFlags = MASS_CMD_DIR_IN,
-                cbw.bmCBWLUN = lun;
-        cbw.bmCBWCBLength = 10;
-
-        cbw.CBWCB[0] = SCSI_CMD_READ_10;
-        cbw.CBWCB[8] = blocks;
-        cbw.CBWCB[2] = ((addr >> 24) & 0xff);
-        cbw.CBWCB[3] = ((addr >> 16) & 0xff);
-        cbw.CBWCB[4] = ((addr >> 8) & 0xff);
-        cbw.CBWCB[5] = (addr & 0xff);
-
-        return HandleSCSIError(Transaction(&cbw, bsize, prs, 1));
-#else
-        return MASS_ERR_NOT_IMPLEMENTED;
-#endif
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/masstorage.h b/lib/usbhost/USB_Host_Shield_2.0/masstorage.h
deleted file mode 100644
index d39fd66f37..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/masstorage.h
+++ /dev/null
@@ -1,571 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#if !defined(__MASSTORAGE_H__)
-#define __MASSTORAGE_H__
-
-// Cruft removal, makes driver smaller, faster.
-#ifndef MS_WANT_PARSER
-#define MS_WANT_PARSER 0
-#endif
-
-#include "Usb.h"
-
-#define bmREQ_MASSOUT       USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
-#define bmREQ_MASSIN        USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_INTERFACE
-
-// Mass Storage Subclass Constants
-#define MASS_SUBCLASS_SCSI_NOT_REPORTED 0x00    // De facto use
-#define MASS_SUBCLASS_RBC               0x01
-#define MASS_SUBCLASS_ATAPI             0x02    // MMC-5 (ATAPI)
-#define MASS_SUBCLASS_OBSOLETE1         0x03    // Was QIC-157
-#define MASS_SUBCLASS_UFI               0x04    // Specifies how to interface Floppy Disk Drives to USB
-#define MASS_SUBCLASS_OBSOLETE2         0x05    // Was SFF-8070i
-#define MASS_SUBCLASS_SCSI              0x06    // SCSI Transparent Command Set
-#define MASS_SUBCLASS_LSDFS             0x07    // Specifies how host has to negotiate access before trying SCSI
-#define MASS_SUBCLASS_IEEE1667          0x08
-
-// Mass Storage Class Protocols
-#define MASS_PROTO_CBI                  0x00    // CBI (with command completion interrupt)
-#define MASS_PROTO_CBI_NO_INT           0x01    // CBI (without command completion interrupt)
-#define MASS_PROTO_OBSOLETE             0x02
-#define MASS_PROTO_BBB                  0x50    // Bulk Only Transport
-#define MASS_PROTO_UAS                  0x62
-
-// Request Codes
-#define MASS_REQ_ADSC                   0x00
-#define MASS_REQ_GET                    0xFC
-#define MASS_REQ_PUT                    0xFD
-#define MASS_REQ_GET_MAX_LUN            0xFE
-#define MASS_REQ_BOMSR                  0xFF    // Bulk-Only Mass Storage Reset
-
-#define MASS_CBW_SIGNATURE              0x43425355
-#define MASS_CSW_SIGNATURE              0x53425355
-
-#define MASS_CMD_DIR_OUT                0 // (0 << 7)
-#define MASS_CMD_DIR_IN                 0x80 //(1 << 7)
-
-/*
- * Reference documents from T10 (http://www.t10.org)
- * SCSI Primary Commands - 3 (SPC-3)
- * SCSI Block Commands - 2 (SBC-2)
- * Multi-Media Commands - 5 (MMC-5)
- */
-
-/* Group 1 commands (CDB's here are should all be 6-bytes) */
-#define SCSI_CMD_TEST_UNIT_READY        0x00
-#define SCSI_CMD_REQUEST_SENSE          0x03
-#define SCSI_CMD_FORMAT_UNIT            0x04
-#define SCSI_CMD_READ_6                 0x08
-#define SCSI_CMD_WRITE_6                0x0A
-#define SCSI_CMD_INQUIRY                0x12
-#define SCSI_CMD_MODE_SELECT_6          0x15
-#define SCSI_CMD_MODE_SENSE_6           0x1A
-#define SCSI_CMD_START_STOP_UNIT        0x1B
-#define SCSI_CMD_PREVENT_REMOVAL        0x1E
-/* Group 2 Commands (CDB's here are 10-bytes) */
-#define SCSI_CMD_READ_FORMAT_CAPACITIES 0x23
-#define SCSI_CMD_READ_CAPACITY_10       0x25
-#define SCSI_CMD_READ_10                0x28
-#define SCSI_CMD_WRITE_10               0x2A
-#define SCSI_CMD_SEEK_10                0x2B
-#define SCSI_CMD_ERASE_10               0x2C
-#define SCSI_CMD_WRITE_AND_VERIFY_10    0x2E
-#define SCSI_CMD_VERIFY_10              0x2F
-#define SCSI_CMD_SYNCHRONIZE_CACHE      0x35
-#define SCSI_CMD_WRITE_BUFFER           0x3B
-#define SCSI_CMD_READ_BUFFER            0x3C
-#define SCSI_CMD_READ_SUBCHANNEL        0x42
-#define SCSI_CMD_READ_TOC               0x43
-#define SCSI_CMD_READ_HEADER            0x44
-#define SCSI_CMD_PLAY_AUDIO_10          0x45
-#define SCSI_CMD_GET_CONFIGURATION      0x46
-#define SCSI_CMD_PLAY_AUDIO_MSF         0x47
-#define SCSI_CMD_PLAY_AUDIO_TI          0x48
-#define SCSI_CMD_PLAY_TRACK_REL_10      0x49
-#define SCSI_CMD_GET_EVENT_STATUS       0x4A
-#define SCSI_CMD_PAUSE_RESUME           0x4B
-#define SCSI_CMD_READ_DISC_INFORMATION  0x51
-#define SCSI_CMD_READ_TRACK_INFORMATION 0x52
-#define SCSI_CMD_RESERVE_TRACK          0x53
-#define SCSI_CMD_SEND_OPC_INFORMATION   0x54
-#define SCSI_CMD_MODE_SELECT_10         0x55
-#define SCSI_CMD_REPAIR_TRACK           0x58
-#define SCSI_CMD_MODE_SENSE_10          0x5A
-#define SCSI_CMD_CLOSE_TRACK_SESSION    0x5B
-#define SCSI_CMD_READ_BUFFER_CAPACITY   0x5C
-#define SCSI_CMD_SEND_CUE_SHEET         0x5D
-/* Group 5 Commands (CDB's here are 12-bytes) */
-#define SCSI_CMD_REPORT_LUNS            0xA0
-#define SCSI_CMD_BLANK                  0xA1
-#define SCSI_CMD_SECURITY_PROTOCOL_IN   0xA2
-#define SCSI_CMD_SEND_KEY               0xA3
-#define SCSI_CMD_REPORT_KEY             0xA4
-#define SCSI_CMD_PLAY_AUDIO_12          0xA5
-#define SCSI_CMD_LOAD_UNLOAD            0xA6
-#define SCSI_CMD_SET_READ_AHEAD         0xA7
-#define SCSI_CMD_READ_12                0xA8
-#define SCSI_CMD_PLAY_TRACK_REL_12      0xA9
-#define SCSI_CMD_WRITE_12               0xAA
-#define SCSI_CMD_READ_MEDIA_SERIAL_12   0xAB
-#define SCSI_CMD_GET_PERFORMANCE        0xAC
-#define SCSI_CMD_READ_DVD_STRUCTURE     0xAD
-#define SCSI_CMD_SECURITY_PROTOCOL_OUT  0xB5
-#define SCSI_CMD_SET_STREAMING          0xB6
-#define SCSI_CMD_READ_MSF               0xB9
-#define SCSI_CMD_SET_SPEED              0xBB
-#define SCSI_CMD_MECHANISM_STATUS       0xBD
-#define SCSI_CMD_READ_CD                0xBE
-#define SCSI_CMD_SEND_DISC_STRUCTURE    0xBF
-/* Vendor-unique Commands, included for completeness */
-#define SCSI_CMD_CD_PLAYBACK_STATUS     0xC4 /* SONY unique */
-#define SCSI_CMD_PLAYBACK_CONTROL       0xC9 /* SONY unique */
-#define SCSI_CMD_READ_CDDA              0xD8 /* Vendor unique */
-#define SCSI_CMD_READ_CDXA              0xDB /* Vendor unique */
-#define SCSI_CMD_READ_ALL_SUBCODES      0xDF /* Vendor unique */
-
-/* SCSI error codes */
-#define SCSI_S_NOT_READY                0x02
-#define SCSI_S_MEDIUM_ERROR             0x03
-#define SCSI_S_ILLEGAL_REQUEST          0x05
-#define SCSI_S_UNIT_ATTENTION           0x06
-#define SCSI_ASC_LBA_OUT_OF_RANGE       0x21
-#define SCSI_ASC_MEDIA_CHANGED          0x28
-#define SCSI_ASC_MEDIUM_NOT_PRESENT     0x3A
-
-/* USB error codes */
-#define MASS_ERR_SUCCESS                0x00
-#define MASS_ERR_PHASE_ERROR            0x02
-#define MASS_ERR_UNIT_NOT_READY         0x03
-#define MASS_ERR_UNIT_BUSY              0x04
-#define MASS_ERR_STALL                  0x05
-#define MASS_ERR_CMD_NOT_SUPPORTED      0x06
-#define MASS_ERR_INVALID_CSW            0x07
-#define MASS_ERR_NO_MEDIA               0x08
-#define MASS_ERR_BAD_LBA                0x09
-#define MASS_ERR_MEDIA_CHANGED          0x0A
-#define MASS_ERR_DEVICE_DISCONNECTED    0x11
-#define MASS_ERR_UNABLE_TO_RECOVER      0x12    // Reset recovery error
-#define MASS_ERR_INVALID_LUN            0x13
-#define MASS_ERR_WRITE_STALL            0x14
-#define MASS_ERR_READ_NAKS              0x15
-#define MASS_ERR_WRITE_NAKS             0x16
-#define MASS_ERR_WRITE_PROTECTED        0x17
-#define MASS_ERR_NOT_IMPLEMENTED        0xFD
-#define MASS_ERR_GENERAL_SCSI_ERROR     0xFE
-#define MASS_ERR_GENERAL_USB_ERROR      0xFF
-#define MASS_ERR_USER                   0xA0    // For subclasses to define their own error codes
-
-#define MASS_TRANS_FLG_CALLBACK         0x01    // Callback is involved
-#define MASS_TRANS_FLG_NO_STALL_CHECK   0x02    // STALL condition is not checked
-#define MASS_TRANS_FLG_NO_PHASE_CHECK   0x04    // PHASE_ERROR is not checked
-
-#define MASS_MAX_ENDPOINTS              3
-
-struct Capacity {
-        uint8_t data[8];
-        //uint32_t dwBlockAddress;
-        //uint32_t dwBlockLength;
-} __attribute__((packed));
-
-struct BASICCDB {
-        uint8_t Opcode;
-
-        unsigned unused : 5;
-        unsigned LUN : 3;
-
-        uint8_t info[12];
-} __attribute__((packed));
-
-typedef BASICCDB BASICCDB_t;
-
-struct CDB6 {
-        uint8_t Opcode;
-
-        unsigned LBAMSB : 5;
-        unsigned LUN : 3;
-
-        uint8_t LBAHB;
-        uint8_t LBALB;
-        uint8_t AllocationLength;
-        uint8_t Control;
-
-public:
-
-        CDB6(uint8_t _Opcode, uint8_t _LUN, uint32_t LBA, uint8_t _AllocationLength, uint8_t _Control) :
-        Opcode(_Opcode), LBAMSB(BGRAB2(LBA) & 0x1f), LUN(_LUN), LBAHB(BGRAB1(LBA)), LBALB(BGRAB0(LBA)),
-        AllocationLength(_AllocationLength), Control(_Control) {
-        }
-
-        CDB6(uint8_t _Opcode, uint8_t _LUN, uint8_t _AllocationLength, uint8_t _Control) :
-        Opcode(_Opcode), LBAMSB(0), LUN(_LUN), LBAHB(0), LBALB(0),
-        AllocationLength(_AllocationLength), Control(_Control) {
-        }
-} __attribute__((packed));
-
-typedef CDB6 CDB6_t;
-
-struct CDB10 {
-        uint8_t Opcode;
-
-        unsigned Service_Action : 5;
-        unsigned LUN : 3;
-
-        uint8_t LBA_L_M_MB;
-        uint8_t LBA_L_M_LB;
-        uint8_t LBA_L_L_MB;
-        uint8_t LBA_L_L_LB;
-
-        uint8_t Misc2;
-
-        uint8_t ALC_MB;
-        uint8_t ALC_LB;
-
-        uint8_t Control;
-public:
-
-        CDB10(uint8_t _Opcode, uint8_t _LUN) :
-        Opcode(_Opcode), Service_Action(0), LUN(_LUN),
-        LBA_L_M_MB(0), LBA_L_M_LB(0), LBA_L_L_MB(0), LBA_L_L_LB(0),
-        Misc2(0), ALC_MB(0), ALC_LB(0), Control(0) {
-        }
-
-        CDB10(uint8_t _Opcode, uint8_t _LUN, uint16_t xflen, uint32_t _LBA) :
-        Opcode(_Opcode), Service_Action(0), LUN(_LUN),
-        LBA_L_M_MB(BGRAB3(_LBA)), LBA_L_M_LB(BGRAB2(_LBA)), LBA_L_L_MB(BGRAB1(_LBA)), LBA_L_L_LB(BGRAB0(_LBA)),
-        Misc2(0), ALC_MB(BGRAB1(xflen)), ALC_LB(BGRAB0(xflen)), Control(0) {
-        }
-} __attribute__((packed));
-
-typedef CDB10 CDB10_t;
-
-struct CDB12 {
-        uint8_t Opcode;
-
-        unsigned Service_Action : 5;
-        unsigned Misc : 3;
-
-        uint8_t LBA_L_M_LB;
-        uint8_t LBA_L_L_MB;
-        uint8_t LBA_L_L_LB;
-
-        uint8_t ALC_M_LB;
-        uint8_t ALC_L_MB;
-        uint8_t ALC_L_LB;
-        uint8_t Control;
-} __attribute__((packed));
-
-typedef CDB12 CDB12_t;
-
-struct CDB_LBA32_16 {
-        uint8_t Opcode;
-
-        unsigned Service_Action : 5;
-        unsigned Misc : 3;
-
-        uint8_t LBA_L_M_MB;
-        uint8_t LBA_L_M_LB;
-        uint8_t LBA_L_L_MB;
-        uint8_t LBA_L_L_LB;
-
-        uint8_t A_M_M_MB;
-        uint8_t A_M_M_LB;
-        uint8_t A_M_L_MB;
-        uint8_t A_M_L_LB;
-
-        uint8_t ALC_M_MB;
-        uint8_t ALC_M_LB;
-        uint8_t ALC_L_MB;
-        uint8_t ALC_L_LB;
-
-        uint8_t Misc2;
-        uint8_t Control;
-} __attribute__((packed));
-
-struct CDB_LBA64_16 {
-        uint8_t Opcode;
-        uint8_t Misc;
-
-        uint8_t LBA_M_M_MB;
-        uint8_t LBA_M_M_LB;
-        uint8_t LBA_M_L_MB;
-        uint8_t LBA_M_L_LB;
-
-        uint8_t LBA_L_M_MB;
-        uint8_t LBA_L_M_LB;
-        uint8_t LBA_L_L_MB;
-        uint8_t LBA_L_L_LB;
-
-        uint8_t ALC_M_MB;
-        uint8_t ALC_M_LB;
-        uint8_t ALC_L_MB;
-        uint8_t ALC_L_LB;
-
-        uint8_t Misc2;
-        uint8_t Control;
-} __attribute__((packed));
-
-struct InquiryResponse {
-        uint8_t DeviceType : 5;
-        uint8_t PeripheralQualifier : 3;
-
-        unsigned Reserved : 7;
-        unsigned Removable : 1;
-
-        uint8_t Version;
-
-        unsigned ResponseDataFormat : 4;
-        unsigned HISUP : 1;
-        unsigned NormACA : 1;
-        unsigned TrmTsk : 1;
-        unsigned AERC : 1;
-
-        uint8_t AdditionalLength;
-        //uint8_t Reserved3[2];
-
-        unsigned PROTECT : 1;
-        unsigned Res : 2;
-        unsigned ThreePC : 1;
-        unsigned TPGS : 2;
-        unsigned ACC : 1;
-        unsigned SCCS : 1;
-
-        unsigned ADDR16 : 1;
-        unsigned R1 : 1;
-        unsigned R2 : 1;
-        unsigned MCHNGR : 1;
-        unsigned MULTIP : 1;
-        unsigned VS : 1;
-        unsigned ENCSERV : 1;
-        unsigned BQUE : 1;
-
-        unsigned SoftReset : 1;
-        unsigned CmdQue : 1;
-        unsigned Reserved4 : 1;
-        unsigned Linked : 1;
-        unsigned Sync : 1;
-        unsigned WideBus16Bit : 1;
-        unsigned WideBus32Bit : 1;
-        unsigned RelAddr : 1;
-
-        uint8_t VendorID[8];
-        uint8_t ProductID[16];
-        uint8_t RevisionID[4];
-} __attribute__((packed));
-
-struct CommandBlockWrapperBase {
-        uint32_t dCBWSignature;
-        uint32_t dCBWTag;
-        uint32_t dCBWDataTransferLength;
-        uint8_t bmCBWFlags;
-public:
-
-        CommandBlockWrapperBase() {
-        }
-
-        CommandBlockWrapperBase(uint32_t tag, uint32_t xflen, uint8_t flgs) :
-        dCBWSignature(MASS_CBW_SIGNATURE), dCBWTag(tag), dCBWDataTransferLength(xflen), bmCBWFlags(flgs) {
-        }
-} __attribute__((packed));
-
-struct CommandBlockWrapper : public CommandBlockWrapperBase {
-
-        struct {
-                uint8_t bmCBWLUN : 4;
-                uint8_t bmReserved1 : 4;
-        };
-
-        struct {
-                uint8_t bmCBWCBLength : 4;
-                uint8_t bmReserved2 : 4;
-        };
-
-        uint8_t CBWCB[16];
-
-public:
-        // All zeroed.
-
-        CommandBlockWrapper() :
-        CommandBlockWrapperBase(0, 0, 0), bmReserved1(0), bmReserved2(0) {
-                for(int i = 0; i < 16; i++) CBWCB[i] = 0;
-        }
-
-        // Generic Wrap, CDB zeroed.
-
-        CommandBlockWrapper(uint32_t tag, uint32_t xflen, uint8_t flgs, uint8_t lu, uint8_t cmdlen, uint8_t cmd) :
-        CommandBlockWrapperBase(tag, xflen, flgs),
-        bmCBWLUN(lu), bmReserved1(0), bmCBWCBLength(cmdlen), bmReserved2(0) {
-                for(int i = 0; i < 16; i++) CBWCB[i] = 0;
-                // Type punning can cause optimization problems and bugs.
-                // Using reinterpret_cast to a dreinterpretifferent object is the proper way to do this.
-                //(((BASICCDB_t *) CBWCB)->LUN) = cmd;
-                BASICCDB_t *x = reinterpret_cast<BASICCDB_t *>(CBWCB);
-                x->LUN = cmd;
-        }
-
-        // Wrap for CDB of 6
-
-        CommandBlockWrapper(uint32_t tag, uint32_t xflen, CDB6_t *cdb, uint8_t dir) :
-        CommandBlockWrapperBase(tag, xflen, dir),
-        bmCBWLUN(cdb->LUN), bmReserved1(0), bmCBWCBLength(6), bmReserved2(0) {
-                memcpy(&CBWCB, cdb, 6);
-        }
-        // Wrap for CDB of 10
-
-        CommandBlockWrapper(uint32_t tag, uint32_t xflen, CDB10_t *cdb, uint8_t dir) :
-        CommandBlockWrapperBase(tag, xflen, dir),
-        bmCBWLUN(cdb->LUN), bmReserved1(0), bmCBWCBLength(10), bmReserved2(0) {
-                memcpy(&CBWCB, cdb, 10);
-        }
-} __attribute__((packed));
-
-struct CommandStatusWrapper {
-        uint32_t dCSWSignature;
-        uint32_t dCSWTag;
-        uint32_t dCSWDataResidue;
-        uint8_t bCSWStatus;
-} __attribute__((packed));
-
-struct RequestSenseResponce {
-        uint8_t bResponseCode;
-        uint8_t bSegmentNumber;
-
-        uint8_t bmSenseKey : 4;
-        uint8_t bmReserved : 1;
-        uint8_t bmILI : 1;
-        uint8_t bmEOM : 1;
-        uint8_t bmFileMark : 1;
-
-        uint8_t Information[4];
-        uint8_t bAdditionalLength;
-        uint8_t CmdSpecificInformation[4];
-        uint8_t bAdditionalSenseCode;
-        uint8_t bAdditionalSenseQualifier;
-        uint8_t bFieldReplaceableUnitCode;
-        uint8_t SenseKeySpecific[3];
-} __attribute__((packed));
-
-class BulkOnly : public USBDeviceConfig, public UsbConfigXtracter {
-protected:
-        static const uint8_t epDataInIndex; // DataIn endpoint index
-        static const uint8_t epDataOutIndex; // DataOUT endpoint index
-        static const uint8_t epInterruptInIndex; // InterruptIN  endpoint index
-
-        USB *pUsb;
-        uint8_t bAddress;
-        uint8_t bConfNum; // configuration number
-        uint8_t bIface; // interface value
-        uint8_t bNumEP; // total number of EP in the configuration
-        uint32_t qNextPollTime; // next poll time
-        bool bPollEnable; // poll enable flag
-
-        EpInfo epInfo[MASS_MAX_ENDPOINTS];
-
-        uint32_t dCBWTag; // Tag
-        //uint32_t dCBWDataTransferLength; // Data Transfer Length
-        uint8_t bLastUsbError; // Last USB error
-        uint8_t bMaxLUN; // Max LUN
-        uint8_t bTheLUN; // Active LUN
-        uint32_t CurrentCapacity[MASS_MAX_SUPPORTED_LUN]; // Total sectors
-        uint16_t CurrentSectorSize[MASS_MAX_SUPPORTED_LUN]; // Sector size, clipped to 16 bits
-        bool LUNOk[MASS_MAX_SUPPORTED_LUN]; // use this to check for media changes.
-        bool WriteOk[MASS_MAX_SUPPORTED_LUN];
-        void PrintEndpointDescriptor(const USB_ENDPOINT_DESCRIPTOR* ep_ptr);
-
-
-        // Additional Initialization Method for Subclasses
-
-        virtual uint8_t OnInit() {
-                return 0;
-        };
-public:
-        BulkOnly(USB *p);
-
-        uint8_t GetLastUsbError() {
-                return bLastUsbError;
-        };
-
-        uint8_t GetbMaxLUN() {
-                return bMaxLUN; // Max LUN
-        }
-
-        uint8_t GetbTheLUN() {
-                return bTheLUN; // Active LUN
-        }
-
-        bool WriteProtected(uint8_t lun);
-        uint8_t MediaCTL(uint8_t lun, uint8_t ctl);
-        uint8_t Read(uint8_t lun, uint32_t addr, uint16_t bsize, uint8_t blocks, uint8_t *buf);
-        uint8_t Read(uint8_t lun, uint32_t addr, uint16_t bsize, uint8_t blocks, USBReadParser *prs);
-        uint8_t Write(uint8_t lun, uint32_t addr, uint16_t bsize, uint8_t blocks, const uint8_t *buf);
-        uint8_t LockMedia(uint8_t lun, uint8_t lock);
-
-        bool LUNIsGood(uint8_t lun);
-        uint32_t GetCapacity(uint8_t lun);
-        uint16_t GetSectorSize(uint8_t lun);
-
-        // USBDeviceConfig implementation
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t ConfigureDevice(uint8_t parent, uint8_t port, bool lowspeed);
-
-        uint8_t Release();
-        uint8_t Poll();
-
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        // UsbConfigXtracter implementation
-        void EndpointXtract(uint8_t conf, uint8_t iface, uint8_t alt, uint8_t proto, const USB_ENDPOINT_DESCRIPTOR *ep);
-
-        virtual bool DEVCLASSOK(uint8_t klass) {
-                return (klass == USB_CLASS_MASS_STORAGE);
-        }
-
-        uint8_t SCSITransaction6(CDB6_t *cdb, uint16_t buf_size, void *buf, uint8_t dir);
-        uint8_t SCSITransaction10(CDB10_t *cdb, uint16_t buf_size, void *buf, uint8_t dir);
-
-private:
-        uint8_t Inquiry(uint8_t lun, uint16_t size, uint8_t *buf);
-        uint8_t TestUnitReady(uint8_t lun);
-        uint8_t RequestSense(uint8_t lun, uint16_t size, uint8_t *buf);
-        uint8_t ModeSense6(uint8_t lun, uint8_t pc, uint8_t page, uint8_t subpage, uint8_t len, uint8_t *buf);
-        uint8_t GetMaxLUN(uint8_t *max_lun);
-        uint8_t SetCurLUN(uint8_t lun);
-        void Reset();
-        uint8_t ResetRecovery();
-        uint8_t ReadCapacity10(uint8_t lun, uint8_t *buf);
-        void ClearAllEP();
-        void CheckMedia();
-        bool CheckLUN(uint8_t lun);
-        uint8_t Page3F(uint8_t lun);
-        bool IsValidCBW(uint8_t size, uint8_t *pcbw);
-        bool IsMeaningfulCBW(uint8_t size, uint8_t *pcbw);
-
-        bool IsValidCSW(CommandStatusWrapper *pcsw, CommandBlockWrapperBase *pcbw);
-
-        uint8_t ClearEpHalt(uint8_t index);
-#if MS_WANT_PARSER
-        uint8_t Transaction(CommandBlockWrapper *cbw, uint16_t bsize, void *buf, uint8_t flags);
-#endif
-        uint8_t Transaction(CommandBlockWrapper *cbw, uint16_t bsize, void *buf);
-        uint8_t HandleUsbError(uint8_t error, uint8_t index);
-        uint8_t HandleSCSIError(uint8_t status);
-
-};
-
-#endif // __MASSTORAGE_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/max3421e.h b/lib/usbhost/USB_Host_Shield_2.0/max3421e.h
deleted file mode 100644
index 4e45a35e8d..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/max3421e.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(_usb_h_) || defined(_max3421e_h_)
-#error "Never include max3421e.h directly; include Usb.h instead"
-#else
-
-#define _max3421e_h_
-
-/* MAX3421E register/bit names and bitmasks */
-
-/* Arduino pin definitions */
-/* pin numbers to port numbers */
-
-#define SE0     0
-#define SE1     1
-#define FSHOST  2
-#define LSHOST  3
-
-/* MAX3421E command byte format: rrrrr0wa where 'r' is register number  */
-//
-// MAX3421E Registers in HOST mode.
-//
-#define rRCVFIFO    0x08    //1<<3
-#define rSNDFIFO    0x10    //2<<3
-#define rSUDFIFO    0x20    //4<<3
-#define rRCVBC      0x30    //6<<3
-#define rSNDBC      0x38    //7<<3
-
-#define rUSBIRQ     0x68    //13<<3
-/* USBIRQ Bits  */
-#define bmVBUSIRQ   0x40    //b6
-#define bmNOVBUSIRQ 0x20    //b5
-#define bmOSCOKIRQ  0x01    //b0
-
-#define rUSBIEN     0x70    //14<<3
-/* USBIEN Bits  */
-#define bmVBUSIE    0x40    //b6
-#define bmNOVBUSIE  0x20    //b5
-#define bmOSCOKIE   0x01    //b0
-
-#define rUSBCTL     0x78    //15<<3
-/* USBCTL Bits  */
-#define bmCHIPRES   0x20    //b5
-#define bmPWRDOWN   0x10    //b4
-
-#define rCPUCTL     0x80    //16<<3
-/* CPUCTL Bits  */
-#define bmPUSLEWID1 0x80    //b7
-#define bmPULSEWID0 0x40    //b6
-#define bmIE        0x01    //b0
-
-#define rPINCTL     0x88    //17<<3
-/* PINCTL Bits  */
-#define bmFDUPSPI   0x10    //b4
-#define bmINTLEVEL  0x08    //b3
-#define bmPOSINT    0x04    //b2
-#define bmGPXB      0x02    //b1
-#define bmGPXA      0x01    //b0
-// GPX pin selections
-#define GPX_OPERATE 0x00
-#define GPX_VBDET   0x01
-#define GPX_BUSACT  0x02
-#define GPX_SOF     0x03
-
-#define rREVISION   0x90    //18<<3
-
-#define rIOPINS1    0xa0    //20<<3
-
-/* IOPINS1 Bits */
-#define bmGPOUT0    0x01
-#define bmGPOUT1    0x02
-#define bmGPOUT2    0x04
-#define bmGPOUT3    0x08
-#define bmGPIN0     0x10
-#define bmGPIN1     0x20
-#define bmGPIN2     0x40
-#define bmGPIN3     0x80
-
-#define rIOPINS2    0xa8    //21<<3
-/* IOPINS2 Bits */
-#define bmGPOUT4    0x01
-#define bmGPOUT5    0x02
-#define bmGPOUT6    0x04
-#define bmGPOUT7    0x08
-#define bmGPIN4     0x10
-#define bmGPIN5     0x20
-#define bmGPIN6     0x40
-#define bmGPIN7     0x80
-
-#define rGPINIRQ    0xb0    //22<<3
-/* GPINIRQ Bits */
-#define bmGPINIRQ0 0x01
-#define bmGPINIRQ1 0x02
-#define bmGPINIRQ2 0x04
-#define bmGPINIRQ3 0x08
-#define bmGPINIRQ4 0x10
-#define bmGPINIRQ5 0x20
-#define bmGPINIRQ6 0x40
-#define bmGPINIRQ7 0x80
-
-#define rGPINIEN    0xb8    //23<<3
-/* GPINIEN Bits */
-#define bmGPINIEN0 0x01
-#define bmGPINIEN1 0x02
-#define bmGPINIEN2 0x04
-#define bmGPINIEN3 0x08
-#define bmGPINIEN4 0x10
-#define bmGPINIEN5 0x20
-#define bmGPINIEN6 0x40
-#define bmGPINIEN7 0x80
-
-#define rGPINPOL    0xc0    //24<<3
-/* GPINPOL Bits */
-#define bmGPINPOL0 0x01
-#define bmGPINPOL1 0x02
-#define bmGPINPOL2 0x04
-#define bmGPINPOL3 0x08
-#define bmGPINPOL4 0x10
-#define bmGPINPOL5 0x20
-#define bmGPINPOL6 0x40
-#define bmGPINPOL7 0x80
-
-#define rHIRQ       0xc8    //25<<3
-/* HIRQ Bits */
-#define bmBUSEVENTIRQ   0x01   // indicates BUS Reset Done or BUS Resume
-#define bmRWUIRQ        0x02
-#define bmRCVDAVIRQ     0x04
-#define bmSNDBAVIRQ     0x08
-#define bmSUSDNIRQ      0x10
-#define bmCONDETIRQ     0x20
-#define bmFRAMEIRQ      0x40
-#define bmHXFRDNIRQ     0x80
-
-#define rHIEN           0xd0    //26<<3
-
-/* HIEN Bits */
-#define bmBUSEVENTIE    0x01
-#define bmRWUIE         0x02
-#define bmRCVDAVIE      0x04
-#define bmSNDBAVIE      0x08
-#define bmSUSDNIE       0x10
-#define bmCONDETIE      0x20
-#define bmFRAMEIE       0x40
-#define bmHXFRDNIE      0x80
-
-#define rMODE           0xd8    //27<<3
-
-/* MODE Bits */
-#define bmHOST          0x01
-#define bmLOWSPEED      0x02
-#define bmHUBPRE        0x04
-#define bmSOFKAENAB     0x08
-#define bmSEPIRQ        0x10
-#define bmDELAYISO      0x20
-#define bmDMPULLDN      0x40
-#define bmDPPULLDN      0x80
-
-#define rPERADDR    0xe0    //28<<3
-
-#define rHCTL       0xe8    //29<<3
-/* HCTL Bits */
-#define bmBUSRST        0x01
-#define bmFRMRST        0x02
-#define bmSAMPLEBUS     0x04
-#define bmSIGRSM        0x08
-#define bmRCVTOG0       0x10
-#define bmRCVTOG1       0x20
-#define bmSNDTOG0       0x40
-#define bmSNDTOG1       0x80
-
-#define rHXFR       0xf0    //30<<3
-/* Host transfer token values for writing the HXFR register (R30)   */
-/* OR this bit field with the endpoint number in bits 3:0               */
-#define tokSETUP  0x10  // HS=0, ISO=0, OUTNIN=0, SETUP=1
-#define tokIN     0x00  // HS=0, ISO=0, OUTNIN=0, SETUP=0
-#define tokOUT    0x20  // HS=0, ISO=0, OUTNIN=1, SETUP=0
-#define tokINHS   0x80  // HS=1, ISO=0, OUTNIN=0, SETUP=0
-#define tokOUTHS  0xA0  // HS=1, ISO=0, OUTNIN=1, SETUP=0
-#define tokISOIN  0x40  // HS=0, ISO=1, OUTNIN=0, SETUP=0
-#define tokISOOUT 0x60  // HS=0, ISO=1, OUTNIN=1, SETUP=0
-
-#define rHRSL       0xf8    //31<<3
-
-/* HRSL Bits */
-#define bmRCVTOGRD  0x10
-#define bmSNDTOGRD  0x20
-#define bmKSTATUS   0x40
-#define bmJSTATUS   0x80
-#define bmSE0       0x00    //SE0 - disconnect state
-#define bmSE1       0xc0    //SE1 - illegal state
-
-/* Host error result codes, the 4 LSB's in the HRSL register */
-#define hrSUCCESS   0x00
-#define hrBUSY      0x01
-#define hrBADREQ    0x02
-#define hrUNDEF     0x03
-#define hrNAK       0x04
-#define hrSTALL     0x05
-#define hrTOGERR    0x06
-#define hrWRONGPID  0x07
-#define hrBADBC     0x08
-#define hrPIDERR    0x09
-#define hrPKTERR    0x0A
-#define hrCRCERR    0x0B
-#define hrKERR      0x0C
-#define hrJERR      0x0D
-#define hrTIMEOUT   0x0E
-#define hrBABBLE    0x0F
-
-#define MODE_FS_HOST    (bmDPPULLDN|bmDMPULLDN|bmHOST|bmSOFKAENAB)
-#define MODE_LS_HOST    (bmDPPULLDN|bmDMPULLDN|bmHOST|bmLOWSPEED|bmSOFKAENAB)
-
-
-#endif //_max3421e_h_
diff --git a/lib/usbhost/USB_Host_Shield_2.0/max_LCD.cpp b/lib/usbhost/USB_Host_Shield_2.0/max_LCD.cpp
deleted file mode 100644
index f0c64666fa..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/max_LCD.cpp
+++ /dev/null
@@ -1,255 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#include "max_LCD.h"
-#include <string.h>
-
-// pin definition and set/clear
-
-#define RS  0x04    // RS pin
-#define E   0x08    // E pin
-
-#define SET_RS  lcdPins |= RS
-#define CLR_RS  lcdPins &= ~RS
-#define SET_E   lcdPins |= E
-#define CLR_E   lcdPins &= ~E
-
-#define SENDlcdPins()   pUsb->gpioWr( lcdPins )
-
-#define LCD_sendcmd(a)  {   CLR_RS;             \
-                            sendbyte(a);    \
-                        }
-
-#define LCD_sendchar(a) {   SET_RS;             \
-                            sendbyte(a);    \
-                        }
-
-static byte lcdPins; //copy of LCD pins
-
-Max_LCD::Max_LCD(USB *pusb) : pUsb(pusb) {
-        lcdPins = 0;
-}
-
-void Max_LCD::init() {
-        _displayfunction = LCD_4BITMODE | LCD_1LINE | LCD_5x8DOTS;
-
-        //   MAX3421E::gpioWr(0x55);
-
-        begin(16, 1);
-}
-
-void Max_LCD::begin(uint8_t cols, uint8_t lines, uint8_t dotsize) {
-        if(lines > 1) {
-                _displayfunction |= LCD_2LINE;
-        }
-        _numlines = lines;
-        _currline = 0;
-
-        // for some 1 line displays you can select a 10 pixel high font
-        if((dotsize != 0) && (lines == 1)) {
-                _displayfunction |= LCD_5x10DOTS;
-        }
-
-        // SEE PAGE 45/46 FOR INITIALIZATION SPECIFICATION!
-        // according to datasheet, we need at least 40ms after power rises above 2.7V
-        // before sending commands. Arduino can turn on way befer 4.5V so we'll wait 50
-        delayMicroseconds(50000);
-        lcdPins = 0x30;
-        SET_E;
-        SENDlcdPins();
-        CLR_E;
-        SENDlcdPins();
-        delayMicroseconds(10000); // wait min 4.1ms
-        //second try
-        SET_E;
-        SENDlcdPins();
-        CLR_E;
-        SENDlcdPins();
-        delayMicroseconds(10000); // wait min 4.1ms
-        // third go!
-        SET_E;
-        SENDlcdPins();
-        CLR_E;
-        SENDlcdPins();
-        delayMicroseconds(10000);
-        // finally, set to 4-bit interface
-        lcdPins = 0x20;
-        //SET_RS;
-        SET_E;
-        SENDlcdPins();
-        //CLR_RS;
-        CLR_E;
-        SENDlcdPins();
-        delayMicroseconds(10000);
-        // finally, set # lines, font size, etc.
-        command(LCD_FUNCTIONSET | _displayfunction);
-
-        // turn the display on with no cursor or blinking default
-        _displaycontrol = LCD_DISPLAYON | LCD_CURSOROFF | LCD_BLINKOFF;
-        display();
-
-        // clear it off
-        clear();
-
-        // Initialize to default text direction (for romance languages)
-        _displaymode = LCD_ENTRYLEFT | LCD_ENTRYSHIFTDECREMENT;
-        // set the entry mode
-        command(LCD_ENTRYMODESET | _displaymode);
-}
-
-/********** high level commands, for the user! */
-void Max_LCD::clear() {
-        command(LCD_CLEARDISPLAY); // clear display, set cursor position to zero
-        delayMicroseconds(2000); // this command takes a long time!
-}
-
-void Max_LCD::home() {
-        command(LCD_RETURNHOME); // set cursor position to zero
-        delayMicroseconds(2000); // this command takes a long time!
-}
-
-void Max_LCD::setCursor(uint8_t col, uint8_t row) {
-        int row_offsets[] = {0x00, 0x40, 0x14, 0x54};
-        if(row > _numlines) {
-                row = _numlines - 1; // we count rows starting w/0
-        }
-
-        command(LCD_SETDDRAMADDR | (col + row_offsets[row]));
-}
-
-// Turn the display on/off (quickly)
-
-void Max_LCD::noDisplay() {
-        _displaycontrol &= ~LCD_DISPLAYON;
-        command(LCD_DISPLAYCONTROL | _displaycontrol);
-}
-
-void Max_LCD::display() {
-        _displaycontrol |= LCD_DISPLAYON;
-        command(LCD_DISPLAYCONTROL | _displaycontrol);
-}
-
-// Turns the underline cursor on/off
-
-void Max_LCD::noCursor() {
-        _displaycontrol &= ~LCD_CURSORON;
-        command(LCD_DISPLAYCONTROL | _displaycontrol);
-}
-
-void Max_LCD::cursor() {
-        _displaycontrol |= LCD_CURSORON;
-        command(LCD_DISPLAYCONTROL | _displaycontrol);
-}
-
-
-// Turn on and off the blinking cursor
-
-void Max_LCD::noBlink() {
-        _displaycontrol &= ~LCD_BLINKON;
-        command(LCD_DISPLAYCONTROL | _displaycontrol);
-}
-
-void Max_LCD::blink() {
-        _displaycontrol |= LCD_BLINKON;
-        command(LCD_DISPLAYCONTROL | _displaycontrol);
-}
-
-// These commands scroll the display without changing the RAM
-
-void Max_LCD::scrollDisplayLeft(void) {
-        command(LCD_CURSORSHIFT | LCD_DISPLAYMOVE | LCD_MOVELEFT);
-}
-
-void Max_LCD::scrollDisplayRight(void) {
-        command(LCD_CURSORSHIFT | LCD_DISPLAYMOVE | LCD_MOVERIGHT);
-}
-
-// This is for text that flows Left to Right
-
-void Max_LCD::leftToRight(void) {
-        _displaymode |= LCD_ENTRYLEFT;
-        command(LCD_ENTRYMODESET | _displaymode);
-}
-
-// This is for text that flows Right to Left
-
-void Max_LCD::rightToLeft(void) {
-        _displaymode &= ~LCD_ENTRYLEFT;
-        command(LCD_ENTRYMODESET | _displaymode);
-}
-
-// This will 'right justify' text from the cursor
-
-void Max_LCD::autoscroll(void) {
-        _displaymode |= LCD_ENTRYSHIFTINCREMENT;
-        command(LCD_ENTRYMODESET | _displaymode);
-}
-
-// This will 'left justify' text from the cursor
-
-void Max_LCD::noAutoscroll(void) {
-        _displaymode &= ~LCD_ENTRYSHIFTINCREMENT;
-        command(LCD_ENTRYMODESET | _displaymode);
-}
-
-// Allows us to fill the first 8 CGRAM locations
-// with custom characters
-
-void Max_LCD::createChar(uint8_t location, uint8_t charmap[]) {
-        location &= 0x7; // we only have 8 locations 0-7
-        command(LCD_SETCGRAMADDR | (location << 3));
-        for(int i = 0; i < 8; i++) {
-                write(charmap[i]);
-        }
-}
-
-/*********** mid level commands, for sending data/cmds */
-
-inline void Max_LCD::command(uint8_t value) {
-        LCD_sendcmd(value);
-        delayMicroseconds(100);
-}
-
-#if defined(ARDUINO) && ARDUINO >=100
-
-inline size_t Max_LCD::write(uint8_t value) {
-        LCD_sendchar(value);
-        return 1; // Assume success
-}
-#else
-
-inline void Max_LCD::write(uint8_t value) {
-        LCD_sendchar(value);
-}
-#endif
-
-void Max_LCD::sendbyte(uint8_t val) {
-        lcdPins &= 0x0f; //prepare place for the upper nibble
-        lcdPins |= (val & 0xf0); //copy upper nibble to LCD variable
-        SET_E; //send
-        SENDlcdPins();
-        delayMicroseconds(2);
-        CLR_E;
-        delayMicroseconds(2);
-        SENDlcdPins();
-        lcdPins &= 0x0f; //prepare place for the lower nibble
-        lcdPins |= (val << 4) & 0xf0; //copy lower nibble to LCD variable
-        SET_E; //send
-        SENDlcdPins();
-        CLR_E;
-        SENDlcdPins();
-        delayMicroseconds(100);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/max_LCD.h b/lib/usbhost/USB_Host_Shield_2.0/max_LCD.h
deleted file mode 100644
index 950c9c5aa3..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/max_LCD.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-//HD44780 compatible LCD display via MAX3421E GPOUT support header
-//pinout: D[4-7] -> GPOUT[4-7], RS-> GPOUT[2], E ->GPOUT[3]
-//
-
-#ifndef _Max_LCD_h_
-#define _Max_LCD_h_
-
-#include "Usb.h"
-#include "Print.h"
-
-// commands
-#define LCD_CLEARDISPLAY        0x01
-#define LCD_RETURNHOME          0x02
-#define LCD_ENTRYMODESET        0x04
-#define LCD_DISPLAYCONTROL      0x08
-#define LCD_CURSORSHIFT         0x10
-#define LCD_FUNCTIONSET         0x20
-#define LCD_SETCGRAMADDR        0x40
-#define LCD_SETDDRAMADDR        0x80
-
-// flags for display entry mode
-#define LCD_ENTRYRIGHT          0x00
-#define LCD_ENTRYLEFT           0x02
-#define LCD_ENTRYSHIFTINCREMENT 0x01
-#define LCD_ENTRYSHIFTDECREMENT 0x00
-
-// flags for display on/off control
-#define LCD_DISPLAYON           0x04
-#define LCD_DISPLAYOFF          0x00
-#define LCD_CURSORON            0x02
-#define LCD_CURSOROFF           0x00
-#define LCD_BLINKON             0x01
-#define LCD_BLINKOFF            0x00
-
-// flags for display/cursor shift
-#define LCD_DISPLAYMOVE         0x08
-#define LCD_CURSORMOVE          0x00
-#define LCD_MOVERIGHT           0x04
-#define LCD_MOVELEFT            0x00
-
-// flags for function set
-#define LCD_8BITMODE            0x10
-#define LCD_4BITMODE            0x00
-#define LCD_2LINE               0x08
-#define LCD_1LINE               0x00
-#define LCD_5x10DOTS            0x04
-#define LCD_5x8DOTS             0x00
-
-class Max_LCD : public Print {
-        USB *pUsb;
-
-public:
-        Max_LCD(USB *pusb);
-        void init();
-        void begin(uint8_t cols, uint8_t rows, uint8_t charsize = LCD_5x8DOTS);
-        void clear();
-        void home();
-        void noDisplay();
-        void display();
-        void noBlink();
-        void blink();
-        void noCursor();
-        void cursor();
-        void scrollDisplayLeft();
-        void scrollDisplayRight();
-        void leftToRight();
-        void rightToLeft();
-        void autoscroll();
-        void noAutoscroll();
-        void createChar(uint8_t, uint8_t[]);
-        void setCursor(uint8_t, uint8_t);
-        void command(uint8_t);
-
-#if defined(ARDUINO) && ARDUINO >=100
-        size_t write(uint8_t);
-        using Print::write;
-#else
-        void write(uint8_t);
-#endif
-
-private:
-        void sendbyte(uint8_t val);
-        uint8_t _displayfunction; //tokill
-        uint8_t _displaycontrol;
-        uint8_t _displaymode;
-        uint8_t _initialized;
-        uint8_t _numlines, _currline;
-};
-
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/message.cpp b/lib/usbhost/USB_Host_Shield_2.0/message.cpp
deleted file mode 100644
index bdcdd18331..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/message.cpp
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#include "Usb.h"
-// 0x80 is the default (i.e. trace) to turn off set this global to something lower.
-// this allows for 126 other debugging levels.
-// TO-DO: Allow assignment to a different serial port by software
-int UsbDEBUGlvl = 0x80;
-
-void E_Notifyc(char c, int lvl) {
-        if(UsbDEBUGlvl < lvl) return;
-#if defined(ARDUINO) && ARDUINO >=100
-        USB_HOST_SERIAL.print(c);
-#else
-        USB_HOST_SERIAL.print(c, BYTE);
-#endif
-        //USB_HOST_SERIAL.flush();
-}
-
-void E_Notify(char const * msg, int lvl) {
-        if(UsbDEBUGlvl < lvl) return;
-        if(!msg) return;
-        char c;
-
-        while((c = pgm_read_byte(msg++))) E_Notifyc(c, lvl);
-}
-
-void E_NotifyStr(char const * msg, int lvl) {
-        if(UsbDEBUGlvl < lvl) return;
-        if(!msg) return;
-        char c;
-
-        while((c = *msg++)) E_Notifyc(c, lvl);
-}
-
-void E_Notify(uint8_t b, int lvl) {
-        if(UsbDEBUGlvl < lvl) return;
-#if defined(ARDUINO) && ARDUINO >=100
-        USB_HOST_SERIAL.print(b);
-#else
-        USB_HOST_SERIAL.print(b, DEC);
-#endif
-        //USB_HOST_SERIAL.flush();
-}
-
-void E_Notify(double d, int lvl) {
-        if(UsbDEBUGlvl < lvl) return;
-        USB_HOST_SERIAL.print(d);
-        //USB_HOST_SERIAL.flush();
-}
-
-#ifdef DEBUG_USB_HOST
-
-void NotifyFailGetDevDescr(void) {
-        Notify(PSTR("\r\ngetDevDescr "), 0x80);
-}
-
-void NotifyFailSetDevTblEntry(void) {
-        Notify(PSTR("\r\nsetDevTblEn "), 0x80);
-}
-
-void NotifyFailGetConfDescr(void) {
-        Notify(PSTR("\r\ngetConf "), 0x80);
-}
-
-void NotifyFailSetConfDescr(void) {
-        Notify(PSTR("\r\nsetConf "), 0x80);
-}
-
-void NotifyFailGetDevDescr(uint8_t reason) {
-        NotifyFailGetDevDescr();
-        NotifyFail(reason);
-}
-
-void NotifyFailSetDevTblEntry(uint8_t reason) {
-        NotifyFailSetDevTblEntry();
-        NotifyFail(reason);
-
-}
-
-void NotifyFailGetConfDescr(uint8_t reason) {
-        NotifyFailGetConfDescr();
-        NotifyFail(reason);
-}
-
-void NotifyFailSetConfDescr(uint8_t reason) {
-        NotifyFailSetConfDescr();
-        NotifyFail(reason);
-}
-
-void NotifyFailUnknownDevice(uint16_t VID, uint16_t PID) {
-        Notify(PSTR("\r\nUnknown Device Connected - VID: "), 0x80);
-        D_PrintHex<uint16_t > (VID, 0x80);
-        Notify(PSTR(" PID: "), 0x80);
-        D_PrintHex<uint16_t > (PID, 0x80);
-}
-
-void NotifyFail(uint8_t rcode) {
-        D_PrintHex<uint8_t > (rcode, 0x80);
-        Notify(PSTR("\r\n"), 0x80);
-}
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/message.h b/lib/usbhost/USB_Host_Shield_2.0/message.h
deleted file mode 100644
index c26628e7f2..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/message.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(_usb_h_) || defined(__MESSAGE_H__)
-#error "Never include message.h directly; include Usb.h instead"
-#else
-#define __MESSAGE_H__
-
-extern int UsbDEBUGlvl;
-
-void E_Notify(char const * msg, int lvl);
-void E_Notify(uint8_t b, int lvl);
-void E_NotifyStr(char const * msg, int lvl);
-void E_Notifyc(char c, int lvl);
-
-#ifdef DEBUG_USB_HOST
-#define Notify E_Notify
-#define NotifyStr E_NotifyStr
-#define Notifyc E_Notifyc
-void NotifyFailGetDevDescr(uint8_t reason);
-void NotifyFailSetDevTblEntry(uint8_t reason);
-void NotifyFailGetConfDescr(uint8_t reason);
-void NotifyFailSetConfDescr(uint8_t reason);
-void NotifyFailGetDevDescr(void);
-void NotifyFailSetDevTblEntry(void);
-void NotifyFailGetConfDescr(void);
-void NotifyFailSetConfDescr(void);
-void NotifyFailUnknownDevice(uint16_t VID, uint16_t PID);
-void NotifyFail(uint8_t rcode);
-#else
-#define Notify(...) ((void)0)
-#define NotifyStr(...) ((void)0)
-#define Notifyc(...) ((void)0)
-#define NotifyFailGetDevDescr(...) ((void)0)
-#define NotifyFailSetDevTblEntry(...) ((void)0)
-#define NotifyFailGetConfDescr(...) ((void)0)
-#define NotifyFailGetDevDescr(...) ((void)0)
-#define NotifyFailSetDevTblEntry(...) ((void)0)
-#define NotifyFailGetConfDescr(...) ((void)0)
-#define NotifyFailSetConfDescr(...) ((void)0)
-#define NotifyFailUnknownDevice(...) ((void)0)
-#define NotifyFail(...) ((void)0)
-#endif
-
-template <class ERROR_TYPE>
-void ErrorMessage(uint8_t level, char const * msg, ERROR_TYPE rcode = 0) {
-#ifdef DEBUG_USB_HOST
-        Notify(msg, level);
-        Notify(PSTR(": "), level);
-        D_PrintHex<ERROR_TYPE > (rcode, level);
-        Notify(PSTR("\r\n"), level);
-#endif
-}
-
-template <class ERROR_TYPE>
-void ErrorMessage(char const * msg, ERROR_TYPE rcode = 0) {
-#ifdef DEBUG_USB_HOST
-        Notify(msg, 0x80);
-        Notify(PSTR(": "), 0x80);
-        D_PrintHex<ERROR_TYPE > (rcode, 0x80);
-        Notify(PSTR("\r\n"), 0x80);
-#endif
-}
-
-#endif // __MESSAGE_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/parsetools.cpp b/lib/usbhost/USB_Host_Shield_2.0/parsetools.cpp
deleted file mode 100644
index 74a8610597..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/parsetools.cpp
+++ /dev/null
@@ -1,67 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#include "Usb.h"
-
-bool MultiByteValueParser::Parse(uint8_t **pp, uint16_t *pcntdn) {
-        if(!pBuf) {
-                Notify(PSTR("Buffer pointer is NULL!\r\n"), 0x80);
-                return false;
-        }
-        for(; countDown && (*pcntdn); countDown--, (*pcntdn)--, (*pp)++)
-                pBuf[valueSize - countDown] = (**pp);
-
-        if(countDown)
-                return false;
-
-        countDown = valueSize;
-        return true;
-}
-
-bool PTPListParser::Parse(uint8_t **pp, uint16_t *pcntdn, PTP_ARRAY_EL_FUNC pf, const void *me) {
-        switch(nStage) {
-                case 0:
-                        pBuf->valueSize = lenSize;
-                        theParser.Initialize(pBuf);
-                        nStage = 1;
-
-                case 1:
-                        if(!theParser.Parse(pp, pcntdn))
-                                return false;
-
-                        arLen = 0;
-                        arLen = (pBuf->valueSize >= 4) ? *((uint32_t*)pBuf->pValue) : (uint32_t)(*((uint16_t*)pBuf->pValue));
-                        arLenCntdn = arLen;
-                        nStage = 2;
-
-                case 2:
-                        pBuf->valueSize = valSize;
-                        theParser.Initialize(pBuf);
-                        nStage = 3;
-
-                case 3:
-                        for(; arLenCntdn; arLenCntdn--) {
-                                if(!theParser.Parse(pp, pcntdn))
-                                        return false;
-
-                                if(pf)
-                                        pf(pBuf, (arLen - arLenCntdn), me);
-                        }
-
-                        nStage = 0;
-        }
-        return true;
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/parsetools.h b/lib/usbhost/USB_Host_Shield_2.0/parsetools.h
deleted file mode 100644
index 66e9531c39..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/parsetools.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#if !defined(_usb_h_) || defined(__PARSETOOLS_H__)
-#error "Never include parsetools.h directly; include Usb.h instead"
-#else
-#define __PARSETOOLS_H__
-
-struct MultiValueBuffer {
-        uint8_t valueSize;
-        void *pValue;
-} __attribute__((packed));
-
-class MultiByteValueParser {
-        uint8_t * pBuf;
-        uint8_t countDown;
-        uint8_t valueSize;
-
-public:
-
-        MultiByteValueParser() : pBuf(NULL), countDown(0), valueSize(0) {
-        };
-
-        const uint8_t* GetBuffer() {
-                return pBuf;
-        };
-
-        void Initialize(MultiValueBuffer * const pbuf) {
-                pBuf = (uint8_t*)pbuf->pValue;
-                countDown = valueSize = pbuf->valueSize;
-        };
-
-        bool Parse(uint8_t **pp, uint16_t *pcntdn);
-};
-
-class ByteSkipper {
-        uint8_t *pBuf;
-        uint8_t nStage;
-        uint16_t countDown;
-
-public:
-
-        ByteSkipper() : pBuf(NULL), nStage(0), countDown(0) {
-        };
-
-        void Initialize(MultiValueBuffer *pbuf) {
-                pBuf = (uint8_t*)pbuf->pValue;
-                countDown = 0;
-        };
-
-        bool Skip(uint8_t **pp, uint16_t *pcntdn, uint16_t bytes_to_skip) {
-                switch(nStage) {
-                        case 0:
-                                countDown = bytes_to_skip;
-                                nStage++;
-                        case 1:
-                                for(; countDown && (*pcntdn); countDown--, (*pp)++, (*pcntdn)--);
-
-                                if(!countDown)
-                                        nStage = 0;
-                };
-                return (!countDown);
-        };
-};
-
-// Pointer to a callback function triggered for each element of PTP array when used with PTPArrayParser
-typedef void (*PTP_ARRAY_EL_FUNC)(const MultiValueBuffer * const p, uint32_t count, const void *me);
-
-class PTPListParser {
-public:
-
-        enum ParseMode {
-                modeArray, modeRange/*, modeEnum*/
-        };
-
-private:
-        uint8_t nStage;
-        uint8_t enStage;
-
-        uint32_t arLen;
-        uint32_t arLenCntdn;
-
-        uint8_t lenSize; // size of the array length field in bytes
-        uint8_t valSize; // size of the array element in bytes
-
-        MultiValueBuffer *pBuf;
-
-        // The only parser for both size and array element parsing
-        MultiByteValueParser theParser;
-
-        uint8_t /*ParseMode*/ prsMode;
-
-public:
-
-        PTPListParser() :
-        nStage(0),
-        enStage(0),
-        arLen(0),
-        arLenCntdn(0),
-        lenSize(0),
-        valSize(0),
-        pBuf(NULL),
-        prsMode(modeArray) {
-        };
-
-        void Initialize(const uint8_t len_size, const uint8_t val_size, MultiValueBuffer * const p, const uint8_t mode = modeArray) {
-                pBuf = p;
-                lenSize = len_size;
-                valSize = val_size;
-                prsMode = mode;
-
-                if(prsMode == modeRange) {
-                        arLenCntdn = arLen = 3;
-                        nStage = 2;
-                } else {
-                        arLenCntdn = arLen = 0;
-                        nStage = 0;
-                }
-                enStage = 0;
-                theParser.Initialize(p);
-        };
-
-        bool Parse(uint8_t **pp, uint16_t *pcntdn, PTP_ARRAY_EL_FUNC pf, const void *me = NULL);
-};
-
-#endif // __PARSETOOLS_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/printhex.h b/lib/usbhost/USB_Host_Shield_2.0/printhex.h
deleted file mode 100644
index 369d7e1f7e..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/printhex.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#if !defined(_usb_h_) || defined(__PRINTHEX_H__)
-#error "Never include printhex.h directly; include Usb.h instead"
-#else
-#define __PRINTHEX_H__
-
-void E_Notifyc(char c, int lvl);
-
-template <class T>
-void PrintHex(T val, int lvl) {
-        int num_nibbles = sizeof (T) * 2;
-
-        do {
-                char v = 48 + (((val >> (num_nibbles - 1) * 4)) & 0x0f);
-                if(v > 57) v += 7;
-                E_Notifyc(v, lvl);
-        } while(--num_nibbles);
-}
-
-template <class T>
-void PrintBin(T val, int lvl) {
-        for(T mask = (((T)1) << ((sizeof (T) << 3) - 1)); mask; mask >>= 1)
-                if(val & mask)
-                        E_Notifyc('1', lvl);
-                else
-                        E_Notifyc('0', lvl);
-}
-
-template <class T>
-void SerialPrintHex(T val) {
-        int num_nibbles = sizeof (T) * 2;
-
-        do {
-                char v = 48 + (((val >> (num_nibbles - 1) * 4)) & 0x0f);
-                if(v > 57) v += 7;
-                USB_HOST_SERIAL.print(v);
-        } while(--num_nibbles);
-}
-
-template <class T>
-void PrintHex2(Print *prn, T val) {
-        T mask = (((T)1) << (((sizeof (T) << 1) - 1) << 2));
-
-        while(mask > 1) {
-                if(val < mask)
-                        prn->print("0");
-
-                mask >>= 4;
-        }
-        prn->print((T)val, HEX);
-}
-
-template <class T> void D_PrintHex(T val, int lvl) {
-#ifdef DEBUG_USB_HOST
-        PrintHex<T > (val, lvl);
-#endif
-}
-
-template <class T>
-void D_PrintBin(T val, int lvl) {
-#ifdef DEBUG_USB_HOST
-        PrintBin<T > (val, lvl);
-#endif
-}
-
-
-
-#endif // __PRINTHEX_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/settings.h b/lib/usbhost/USB_Host_Shield_2.0/settings.h
deleted file mode 100644
index 5c060354ba..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/settings.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#ifndef USB_HOST_SHIELD_SETTINGS_H
-#define USB_HOST_SHIELD_SETTINGS_H
-#include "macros.h"
-
-////////////////////////////////////////////////////////////////////////////////
-// DEBUGGING
-////////////////////////////////////////////////////////////////////////////////
-
-/* Set this to 1 to activate serial debugging */
-#define ENABLE_UHS_DEBUGGING 0
-
-/* This can be used to select which serial port to use for debugging if
- * multiple serial ports are available.
- * For example Serial3.
- */
-#ifndef USB_HOST_SERIAL
-#define USB_HOST_SERIAL Serial
-#endif
-
-////////////////////////////////////////////////////////////////////////////////
-// Manual board activation
-////////////////////////////////////////////////////////////////////////////////
-
-/* Set this to 1 if you are using an Arduino Mega ADK board with MAX3421e built-in */
-#define USE_UHS_MEGA_ADK 0 // If you are using Arduino 1.5.5 or newer there is no need to do this manually
-
-/* Set this to 1 if you are using a Black Widdow */
-#define USE_UHS_BLACK_WIDDOW 0
-
-/* Set this to a one to use the xmem2 lock. This is needed for multitasking and threading */
-#define USE_XMEM_SPI_LOCK 0
-
-////////////////////////////////////////////////////////////////////////////////
-// Wii IR camera
-////////////////////////////////////////////////////////////////////////////////
-
-/* Set this to 1 to activate code for the Wii IR camera */
-#define ENABLE_WII_IR_CAMERA 0
-
-////////////////////////////////////////////////////////////////////////////////
-// MASS STORAGE
-////////////////////////////////////////////////////////////////////////////////
-// <<<<<<<<<<<<<<<< IMPORTANT >>>>>>>>>>>>>>>
-// Set this to 1 to support single LUN devices, and save RAM. -- I.E. thumb drives.
-// Each LUN needs ~13 bytes to be able to track the state of each unit.
-#ifndef MASS_MAX_SUPPORTED_LUN
-#define MASS_MAX_SUPPORTED_LUN 8
-#endif
-
-////////////////////////////////////////////////////////////////////////////////
-// Set to 1 to use the faster spi4teensy3 driver.
-////////////////////////////////////////////////////////////////////////////////
-#ifndef USE_SPI4TEENSY3
-#define USE_SPI4TEENSY3 1
-#endif
-
-////////////////////////////////////////////////////////////////////////////////
-// AUTOMATIC Settings
-////////////////////////////////////////////////////////////////////////////////
-
-// No user serviceable parts below this line.
-// DO NOT change anything below here unless you are a developer!
-
-#include "version_helper.h"
-
-#if defined(__GNUC__) && defined(__AVR__)
-#ifndef GCC_VERSION
-#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
-#endif
-#if GCC_VERSION < 40602 // Test for GCC < 4.6.2
-#ifdef PROGMEM
-#undef PROGMEM
-#define PROGMEM __attribute__((section(".progmem.data"))) // Workaround for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34734#c4
-#ifdef PSTR
-#undef PSTR
-#define PSTR(s) (__extension__({static const char __c[] PROGMEM = (s); &__c[0];})) // Copied from pgmspace.h in avr-libc source
-#endif
-#endif
-#endif
-#endif
-
-#if !defined(DEBUG_USB_HOST) && ENABLE_UHS_DEBUGGING
-#define DEBUG_USB_HOST
-#endif
-
-#if !defined(WIICAMERA) && ENABLE_WII_IR_CAMERA
-#define WIICAMERA
-#endif
-
-// To use some other locking (e.g. freertos),
-// define XMEM_ACQUIRE_SPI and XMEM_RELEASE_SPI to point to your lock and unlock.
-// NOTE: NO argument is passed. You have to do this within your routine for
-// whatever you are using to lock and unlock.
-#if !defined(XMEM_ACQUIRE_SPI)
-#if USE_XMEM_SPI_LOCK || defined(USE_MULTIPLE_APP_API)
-#include <xmem.h>
-#else
-#define XMEM_ACQUIRE_SPI() (void(0))
-#define XMEM_RELEASE_SPI() (void(0))
-#endif
-#endif
-
-#if !defined(EXT_RAM) && defined(EXT_RAM_STACK) || defined(EXT_RAM_HEAP)
-#include <xmem.h>
-#else
-#define EXT_RAM 0
-#endif
-
-#if defined(CORE_TEENSY) && (defined(__MK20DX128__) || defined(__MK20DX256__))
-#define USING_SPI4TEENSY3 USE_SPI4TEENSY3
-#else
-#define USING_SPI4TEENSY3 0
-#endif
-
-#if ((defined(ARDUINO_SAM_DUE) && defined(__SAM3X8E__)) || defined(RBL_NRF51822) || defined(__ARDUINO_X86__) || ARDUINO >= 10600) && !USING_SPI4TEENSY3
-#include <SPI.h> // Use the Arduino SPI library for the Arduino Due, RedBearLab nRF51822, Intel Galileo 1 & 2, Intel Edison or if the SPI library with transaction is available
-#endif
-#if defined(__PIC32MX__) || defined(__PIC32MZ__)
-#include <../../../../hardware/pic32/libraries/SPI/SPI.h> // Hack to use the SPI library
-#endif
-
-#endif /* SETTINGS_H */
diff --git a/lib/usbhost/USB_Host_Shield_2.0/sink_parser.h b/lib/usbhost/USB_Host_Shield_2.0/sink_parser.h
deleted file mode 100644
index a23637d2b7..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/sink_parser.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(_usb_h_) || defined(__SINK_PARSER_H__)
-#error "Never include hexdump.h directly; include Usb.h instead"
-#else
-#define __SINK_PARSER_H__
-
-extern int UsbDEBUGlvl;
-
-// This parser does absolutely nothing with the data, just swallows it.
-
-template <class BASE_CLASS, class LEN_TYPE, class OFFSET_TYPE>
-class SinkParser : public BASE_CLASS {
-public:
-
-        SinkParser() {
-        };
-
-        void Initialize() {
-        };
-
-        void Parse(const LEN_TYPE len, const uint8_t *pbuf, const OFFSET_TYPE &offset) {
-        };
-};
-
-
-#endif // __HEXDUMP_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/usb_ch9.h b/lib/usbhost/USB_Host_Shield_2.0/usb_ch9.h
deleted file mode 100644
index 18f2d3e2e5..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/usb_ch9.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-#if !defined(_usb_h_) || defined(_ch9_h_)
-#error "Never include usb_ch9.h directly; include Usb.h instead"
-#else
-
-/* USB chapter 9 structures */
-#define _ch9_h_
-
-/* Misc.USB constants */
-#define DEV_DESCR_LEN   18      //device descriptor length
-#define CONF_DESCR_LEN  9       //configuration descriptor length
-#define INTR_DESCR_LEN  9       //interface descriptor length
-#define EP_DESCR_LEN    7       //endpoint descriptor length
-
-/* Standard Device Requests */
-
-#define USB_REQUEST_GET_STATUS                  0       // Standard Device Request - GET STATUS
-#define USB_REQUEST_CLEAR_FEATURE               1       // Standard Device Request - CLEAR FEATURE
-#define USB_REQUEST_SET_FEATURE                 3       // Standard Device Request - SET FEATURE
-#define USB_REQUEST_SET_ADDRESS                 5       // Standard Device Request - SET ADDRESS
-#define USB_REQUEST_GET_DESCRIPTOR              6       // Standard Device Request - GET DESCRIPTOR
-#define USB_REQUEST_SET_DESCRIPTOR              7       // Standard Device Request - SET DESCRIPTOR
-#define USB_REQUEST_GET_CONFIGURATION           8       // Standard Device Request - GET CONFIGURATION
-#define USB_REQUEST_SET_CONFIGURATION           9       // Standard Device Request - SET CONFIGURATION
-#define USB_REQUEST_GET_INTERFACE               10      // Standard Device Request - GET INTERFACE
-#define USB_REQUEST_SET_INTERFACE               11      // Standard Device Request - SET INTERFACE
-#define USB_REQUEST_SYNCH_FRAME                 12      // Standard Device Request - SYNCH FRAME
-
-#define USB_FEATURE_ENDPOINT_HALT               0       // CLEAR/SET FEATURE - Endpoint Halt
-#define USB_FEATURE_DEVICE_REMOTE_WAKEUP        1       // CLEAR/SET FEATURE - Device remote wake-up
-#define USB_FEATURE_TEST_MODE                   2       // CLEAR/SET FEATURE - Test mode
-
-/* Setup Data Constants */
-
-#define USB_SETUP_HOST_TO_DEVICE                0x00    // Device Request bmRequestType transfer direction - host to device transfer
-#define USB_SETUP_DEVICE_TO_HOST                0x80    // Device Request bmRequestType transfer direction - device to host transfer
-#define USB_SETUP_TYPE_STANDARD                 0x00    // Device Request bmRequestType type - standard
-#define USB_SETUP_TYPE_CLASS                    0x20    // Device Request bmRequestType type - class
-#define USB_SETUP_TYPE_VENDOR                   0x40    // Device Request bmRequestType type - vendor
-#define USB_SETUP_RECIPIENT_DEVICE              0x00    // Device Request bmRequestType recipient - device
-#define USB_SETUP_RECIPIENT_INTERFACE           0x01    // Device Request bmRequestType recipient - interface
-#define USB_SETUP_RECIPIENT_ENDPOINT            0x02    // Device Request bmRequestType recipient - endpoint
-#define USB_SETUP_RECIPIENT_OTHER               0x03    // Device Request bmRequestType recipient - other
-
-/* USB descriptors  */
-
-#define USB_DESCRIPTOR_DEVICE                   0x01    // bDescriptorType for a Device Descriptor.
-#define USB_DESCRIPTOR_CONFIGURATION            0x02    // bDescriptorType for a Configuration Descriptor.
-#define USB_DESCRIPTOR_STRING                   0x03    // bDescriptorType for a String Descriptor.
-#define USB_DESCRIPTOR_INTERFACE                0x04    // bDescriptorType for an Interface Descriptor.
-#define USB_DESCRIPTOR_ENDPOINT                 0x05    // bDescriptorType for an Endpoint Descriptor.
-#define USB_DESCRIPTOR_DEVICE_QUALIFIER         0x06    // bDescriptorType for a Device Qualifier.
-#define USB_DESCRIPTOR_OTHER_SPEED              0x07    // bDescriptorType for a Other Speed Configuration.
-#define USB_DESCRIPTOR_INTERFACE_POWER          0x08    // bDescriptorType for Interface Power.
-#define USB_DESCRIPTOR_OTG                      0x09    // bDescriptorType for an OTG Descriptor.
-
-#define HID_DESCRIPTOR_HID                      0x21
-
-
-
-/* OTG SET FEATURE Constants    */
-#define OTG_FEATURE_B_HNP_ENABLE                3       // SET FEATURE OTG - Enable B device to perform HNP
-#define OTG_FEATURE_A_HNP_SUPPORT               4       // SET FEATURE OTG - A device supports HNP
-#define OTG_FEATURE_A_ALT_HNP_SUPPORT           5       // SET FEATURE OTG - Another port on the A device supports HNP
-
-/* USB Endpoint Transfer Types  */
-#define USB_TRANSFER_TYPE_CONTROL               0x00    // Endpoint is a control endpoint.
-#define USB_TRANSFER_TYPE_ISOCHRONOUS           0x01    // Endpoint is an isochronous endpoint.
-#define USB_TRANSFER_TYPE_BULK                  0x02    // Endpoint is a bulk endpoint.
-#define USB_TRANSFER_TYPE_INTERRUPT             0x03    // Endpoint is an interrupt endpoint.
-#define bmUSB_TRANSFER_TYPE                     0x03    // bit mask to separate transfer type from ISO attributes
-
-
-/* Standard Feature Selectors for CLEAR_FEATURE Requests    */
-#define USB_FEATURE_ENDPOINT_STALL              0       // Endpoint recipient
-#define USB_FEATURE_DEVICE_REMOTE_WAKEUP        1       // Device recipient
-#define USB_FEATURE_TEST_MODE                   2       // Device recipient
-
-/* descriptor data structures */
-
-/* Device descriptor structure */
-typedef struct {
-        uint8_t bLength; // Length of this descriptor.
-        uint8_t bDescriptorType; // DEVICE descriptor type (USB_DESCRIPTOR_DEVICE).
-        uint16_t bcdUSB; // USB Spec Release Number (BCD).
-        uint8_t bDeviceClass; // Class code (assigned by the USB-IF). 0xFF-Vendor specific.
-        uint8_t bDeviceSubClass; // Subclass code (assigned by the USB-IF).
-        uint8_t bDeviceProtocol; // Protocol code (assigned by the USB-IF). 0xFF-Vendor specific.
-        uint8_t bMaxPacketSize0; // Maximum packet size for endpoint 0.
-        uint16_t idVendor; // Vendor ID (assigned by the USB-IF).
-        uint16_t idProduct; // Product ID (assigned by the manufacturer).
-        uint16_t bcdDevice; // Device release number (BCD).
-        uint8_t iManufacturer; // Index of String Descriptor describing the manufacturer.
-        uint8_t iProduct; // Index of String Descriptor describing the product.
-        uint8_t iSerialNumber; // Index of String Descriptor with the device's serial number.
-        uint8_t bNumConfigurations; // Number of possible configurations.
-} __attribute__((packed)) USB_DEVICE_DESCRIPTOR;
-
-/* Configuration descriptor structure */
-typedef struct {
-        uint8_t bLength; // Length of this descriptor.
-        uint8_t bDescriptorType; // CONFIGURATION descriptor type (USB_DESCRIPTOR_CONFIGURATION).
-        uint16_t wTotalLength; // Total length of all descriptors for this configuration.
-        uint8_t bNumInterfaces; // Number of interfaces in this configuration.
-        uint8_t bConfigurationValue; // Value of this configuration (1 based).
-        uint8_t iConfiguration; // Index of String Descriptor describing the configuration.
-        uint8_t bmAttributes; // Configuration characteristics.
-        uint8_t bMaxPower; // Maximum power consumed by this configuration.
-} __attribute__((packed)) USB_CONFIGURATION_DESCRIPTOR;
-
-/* Interface descriptor structure */
-typedef struct {
-        uint8_t bLength; // Length of this descriptor.
-        uint8_t bDescriptorType; // INTERFACE descriptor type (USB_DESCRIPTOR_INTERFACE).
-        uint8_t bInterfaceNumber; // Number of this interface (0 based).
-        uint8_t bAlternateSetting; // Value of this alternate interface setting.
-        uint8_t bNumEndpoints; // Number of endpoints in this interface.
-        uint8_t bInterfaceClass; // Class code (assigned by the USB-IF).  0xFF-Vendor specific.
-        uint8_t bInterfaceSubClass; // Subclass code (assigned by the USB-IF).
-        uint8_t bInterfaceProtocol; // Protocol code (assigned by the USB-IF).  0xFF-Vendor specific.
-        uint8_t iInterface; // Index of String Descriptor describing the interface.
-} __attribute__((packed)) USB_INTERFACE_DESCRIPTOR;
-
-/* Endpoint descriptor structure */
-typedef struct {
-        uint8_t bLength; // Length of this descriptor.
-        uint8_t bDescriptorType; // ENDPOINT descriptor type (USB_DESCRIPTOR_ENDPOINT).
-        uint8_t bEndpointAddress; // Endpoint address. Bit 7 indicates direction (0=OUT, 1=IN).
-        uint8_t bmAttributes; // Endpoint transfer type.
-        uint16_t wMaxPacketSize; // Maximum packet size.
-        uint8_t bInterval; // Polling interval in frames.
-} __attribute__((packed)) USB_ENDPOINT_DESCRIPTOR;
-
-/* HID descriptor */
-typedef struct {
-        uint8_t bLength;
-        uint8_t bDescriptorType;
-        uint16_t bcdHID; // HID class specification release
-        uint8_t bCountryCode;
-        uint8_t bNumDescriptors; // Number of additional class specific descriptors
-        uint8_t bDescrType; // Type of class descriptor
-        uint16_t wDescriptorLength; // Total size of the Report descriptor
-} __attribute__((packed)) USB_HID_DESCRIPTOR;
-
-typedef struct {
-        uint8_t bDescrType; // Type of class descriptor
-        uint16_t wDescriptorLength; // Total size of the Report descriptor
-} __attribute__((packed)) HID_CLASS_DESCRIPTOR_LEN_AND_TYPE;
-
-#endif // _ch9_h_
diff --git a/lib/usbhost/USB_Host_Shield_2.0/usbhost.h b/lib/usbhost/USB_Host_Shield_2.0/usbhost.h
deleted file mode 100644
index eba480e60c..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/usbhost.h
+++ /dev/null
@@ -1,529 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-/* MAX3421E-based USB Host Library header file */
-
-
-#if !defined(_usb_h_) || defined(_USBHOST_H_)
-#error "Never include usbhost.h directly; include Usb.h instead"
-#else
-#define _USBHOST_H_
-
-#if USING_SPI4TEENSY3
-#include <spi4teensy3.h>
-#include <sys/types.h>
-#endif
-
-/* SPI initialization */
-template< typename SPI_CLK, typename SPI_MOSI, typename SPI_MISO, typename SPI_SS > class SPi {
-public:
-#if USING_SPI4TEENSY3
-        static void init() {
-                // spi4teensy3 inits everything for us, except /SS
-                // CLK, MOSI and MISO are hard coded for now.
-                // spi4teensy3::init(0,0,0); // full speed, cpol 0, cpha 0
-                spi4teensy3::init(); // full speed, cpol 0, cpha 0
-                SPI_SS::SetDirWrite();
-                SPI_SS::Set();
-        }
-#elif SPI_HAS_TRANSACTION
-        static void init() {
-                SPI.begin(); // The SPI library with transaction will take care of setting up the pins - settings is set in beginTransaction()
-        }
-#elif !defined(SPDR)
-        static void init() {
-                SPI_SS::SetDirWrite();
-                SPI_SS::Set();
-                SPI.begin();
-#if defined(__MIPSEL__)
-                SPI.setClockDivider(1);
-#elif defined(__ARDUINO_X86__)
-                #ifdef SPI_CLOCK_1M // Hack used to check if setClockSpeed is available
-                    SPI.setClockSpeed(12000000); // The MAX3421E can handle up to 26MHz, but in practice this was the maximum that I could reliably use
-                #else
-                    SPI.setClockDivider(SPI_CLOCK_DIV2); // This will set the SPI frequency to 8MHz - it could be higher, but it is not supported in the old API
-                #endif
-#else
-                SPI.setClockDivider(4); // Set speed to 84MHz/4=21MHz - the MAX3421E can handle up to 26MHz
-#endif
-        }
-#elif defined(RBL_NRF51822)
-        static void init() {
-                SPI_SS::SetDirWrite();
-                SPI_SS::Set();
-                SPI.begin();
-                // SPI.setFrequency(SPI_FREQUENCY_8M);
-        }
-#else
-        static void init() {
-                //uint8_t tmp;
-                SPI_CLK::SetDirWrite();
-                SPI_MOSI::SetDirWrite();
-                SPI_MISO::SetDirRead();
-                SPI_SS::SetDirWrite();
-                /* mode 00 (CPOL=0, CPHA=0) master, fclk/2. Mode 11 (CPOL=11, CPHA=11) is also supported by MAX3421E */
-                SPCR = 0x50;
-                SPSR = 0x01; // 0x01
-                /**/
-                //tmp = SPSR;
-                //tmp = SPDR;
-        }
-#endif
-};
-
-/* SPI pin definitions. see avrpins.h   */
-#if defined(__AVR_ATmega1280__) || (__AVR_ATmega2560__) || defined(__AVR_ATmega32U4__) || defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
-typedef SPi< Pb1, Pb2, Pb3, Pb0 > spi;
-#elif  defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__)
-typedef SPi< Pb5, Pb3, Pb4, Pb2 > spi;
-#elif defined(__AVR_ATmega644__) || defined(__AVR_ATmega644P__) || defined(__AVR_ATmega1284__) || defined(__AVR_ATmega1284P__)
-typedef SPi< Pb7, Pb5, Pb6, Pb4 > spi;
-#elif (defined(CORE_TEENSY) && (defined(__MK20DX128__) || defined(__MK20DX256__))) || defined(__ARDUINO_X86__) || defined(__MIPSEL__)
-typedef SPi< P13, P11, P12, P10 > spi;
-#elif defined(ARDUINO_SAM_DUE) && defined(__SAM3X8E__)
-typedef SPi< P76, P75, P74, P10 > spi;
-#elif defined(RBL_NRF51822)
-typedef SPi< P16, P18, P17, P10 > spi;
-#else
-#error "No SPI entry in usbhost.h"
-#endif
-
-typedef enum {
-        vbus_on = 0,
-        vbus_off = GPX_VBDET
-} VBUS_t;
-
-template< typename SPI_SS, typename INTR > class MAX3421e /* : public spi */ {
-        static uint8_t vbusState;
-
-public:
-        MAX3421e();
-        void regWr(uint8_t reg, uint8_t data);
-        uint8_t* bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* data_p);
-        void gpioWr(uint8_t data);
-        uint8_t regRd(uint8_t reg);
-        uint8_t* bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* data_p);
-        uint8_t gpioRd();
-        uint16_t reset();
-        int8_t Init();
-        int8_t Init(int mseconds);
-
-        void vbusPower(VBUS_t state) {
-                regWr(rPINCTL, (bmFDUPSPI | bmINTLEVEL | state));
-        }
-
-        uint8_t getVbusState(void) {
-                return vbusState;
-        };
-        void busprobe();
-        uint8_t GpxHandler();
-        uint8_t IntHandler();
-        uint8_t Task();
-};
-
-template< typename SPI_SS, typename INTR >
-        uint8_t MAX3421e< SPI_SS, INTR >::vbusState = 0;
-
-/* constructor */
-template< typename SPI_SS, typename INTR >
-MAX3421e< SPI_SS, INTR >::MAX3421e() {
-        // Leaving ADK hardware setup in here, for now. This really belongs with the other parts.
-#ifdef BOARD_MEGA_ADK
-        // For Mega ADK, which has a Max3421e on-board, set MAX_RESET to output mode, and then set it to HIGH
-        P55::SetDirWrite();
-        P55::Set();
-#endif
-};
-
-/* write single byte into MAX3421 register */
-template< typename SPI_SS, typename INTR >
-void MAX3421e< SPI_SS, INTR >::regWr(uint8_t reg, uint8_t data) {
-        XMEM_ACQUIRE_SPI();
-#if SPI_HAS_TRANSACTION
-        SPI.beginTransaction(SPISettings(26000000, MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
-#endif
-        SPI_SS::Clear();
-
-#if USING_SPI4TEENSY3
-        uint8_t c[2];
-        c[0] = reg | 0x02;
-        c[1] = data;
-        spi4teensy3::send(c, 2);
-#elif SPI_HAS_TRANSACTION
-        uint8_t c[2];
-        c[0] = reg | 0x02;
-        c[1] = data;
-        SPI.transfer(c, 2);
-#elif !defined(SPDR)
-        SPI.transfer(reg | 0x02);
-        SPI.transfer(data);
-#else
-        SPDR = (reg | 0x02);
-        while(!(SPSR & (1 << SPIF)));
-        SPDR = data;
-        while(!(SPSR & (1 << SPIF)));
-#endif
-
-        SPI_SS::Set();
-#if SPI_HAS_TRANSACTION
-        SPI.endTransaction();
-#endif
-        XMEM_RELEASE_SPI();
-        return;
-};
-/* multiple-byte write                            */
-
-/* returns a pointer to memory position after last written */
-template< typename SPI_SS, typename INTR >
-uint8_t* MAX3421e< SPI_SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
-        XMEM_ACQUIRE_SPI();
-#if SPI_HAS_TRANSACTION
-        SPI.beginTransaction(SPISettings(26000000, MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
-#endif
-        SPI_SS::Clear();
-
-#if USING_SPI4TEENSY3
-        spi4teensy3::send(reg | 0x02);
-        spi4teensy3::send(data_p, nbytes);
-        data_p += nbytes;
-#elif SPI_HAS_TRANSACTION
-        SPI.transfer(reg | 0x02);
-        SPI.transfer(data_p, nbytes);
-        data_p += nbytes;
-#elif defined(__ARDUINO_X86__)
-        SPI.transfer(reg | 0x02);
-        SPI.transferBuffer(data_p, NULL, nbytes);
-        data_p += nbytes;
-#elif !defined(SPDR)
-        SPI.transfer(reg | 0x02);
-        while(nbytes) {
-                SPI.transfer(*data_p);
-                nbytes--;
-                data_p++; // advance data pointer
-        }
-#else
-        SPDR = (reg | 0x02); //set WR bit and send register number
-        while(nbytes) {
-                while(!(SPSR & (1 << SPIF))); //check if previous byte was sent
-                SPDR = (*data_p); // send next data byte
-                nbytes--;
-                data_p++; // advance data pointer
-        }
-        while(!(SPSR & (1 << SPIF)));
-#endif
-
-        SPI_SS::Set();
-#if SPI_HAS_TRANSACTION
-        SPI.endTransaction();
-#endif
-        XMEM_RELEASE_SPI();
-        return ( data_p);
-}
-/* GPIO write                                           */
-/*GPIO byte is split between 2 registers, so two writes are needed to write one byte */
-
-/* GPOUT bits are in the low nibble. 0-3 in IOPINS1, 4-7 in IOPINS2 */
-template< typename SPI_SS, typename INTR >
-void MAX3421e< SPI_SS, INTR >::gpioWr(uint8_t data) {
-        regWr(rIOPINS1, data);
-        data >>= 4;
-        regWr(rIOPINS2, data);
-        return;
-}
-
-/* single host register read    */
-template< typename SPI_SS, typename INTR >
-uint8_t MAX3421e< SPI_SS, INTR >::regRd(uint8_t reg) {
-        XMEM_ACQUIRE_SPI();
-#if SPI_HAS_TRANSACTION
-        SPI.beginTransaction(SPISettings(26000000, MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
-#endif
-        SPI_SS::Clear();
-
-#if USING_SPI4TEENSY3
-        spi4teensy3::send(reg);
-        uint8_t rv = spi4teensy3::receive();
-        SPI_SS::Set();
-#elif !defined(SPDR) || SPI_HAS_TRANSACTION
-        SPI.transfer(reg);
-        uint8_t rv = SPI.transfer(0); // Send empty byte
-        SPI_SS::Set();
-#else
-        SPDR = reg;
-        while(!(SPSR & (1 << SPIF)));
-        SPDR = 0; // Send empty byte
-        while(!(SPSR & (1 << SPIF)));
-        SPI_SS::Set();
-        uint8_t rv = SPDR;
-#endif
-
-#if SPI_HAS_TRANSACTION
-        SPI.endTransaction();
-#endif
-        XMEM_RELEASE_SPI();
-        return (rv);
-}
-/* multiple-byte register read  */
-
-/* returns a pointer to a memory position after last read   */
-template< typename SPI_SS, typename INTR >
-uint8_t* MAX3421e< SPI_SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
-        XMEM_ACQUIRE_SPI();
-#if SPI_HAS_TRANSACTION
-        SPI.beginTransaction(SPISettings(26000000, MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
-#endif
-        SPI_SS::Clear();
-
-#if USING_SPI4TEENSY3
-        spi4teensy3::send(reg);
-        spi4teensy3::receive(data_p, nbytes);
-        data_p += nbytes;
-#elif SPI_HAS_TRANSACTION
-        SPI.transfer(reg);
-        memset(data_p, 0, nbytes); // Make sure we send out empty bytes
-        SPI.transfer(data_p, nbytes);
-        data_p += nbytes;
-#elif defined(__ARDUINO_X86__)
-        SPI.transfer(reg);
-        SPI.transferBuffer(NULL, data_p, nbytes);
-        data_p += nbytes;
-#elif !defined(SPDR)
-        SPI.transfer(reg);
-        while(nbytes) {
-            *data_p++ = SPI.transfer(0);
-            nbytes--;
-        }
-#else
-        SPDR = reg;
-        while(!(SPSR & (1 << SPIF))); //wait
-        while(nbytes) {
-                SPDR = 0; // Send empty byte
-                nbytes--;
-                while(!(SPSR & (1 << SPIF)));
-#if 0
-                {
-                        *data_p = SPDR;
-                        printf("%2.2x ", *data_p);
-                }
-                data_p++;
-        }
-        printf("\r\n");
-#else
-                *data_p++ = SPDR;
-        }
-#endif
-#endif
-
-        SPI_SS::Set();
-#if SPI_HAS_TRANSACTION
-        SPI.endTransaction();
-#endif
-        XMEM_RELEASE_SPI();
-        return ( data_p);
-}
-/* GPIO read. See gpioWr for explanation */
-
-/* GPIN pins are in high nibbles of IOPINS1, IOPINS2    */
-template< typename SPI_SS, typename INTR >
-uint8_t MAX3421e< SPI_SS, INTR >::gpioRd() {
-        uint8_t gpin = 0;
-        gpin = regRd(rIOPINS2); //pins 4-7
-        gpin &= 0xf0; //clean lower nibble
-        gpin |= (regRd(rIOPINS1) >> 4); //shift low bits and OR with upper from previous operation.
-        return ( gpin);
-}
-
-/* reset MAX3421E. Returns number of cycles it took for PLL to stabilize after reset
-  or zero if PLL haven't stabilized in 65535 cycles */
-template< typename SPI_SS, typename INTR >
-uint16_t MAX3421e< SPI_SS, INTR >::reset() {
-        uint16_t i = 0;
-        regWr(rUSBCTL, bmCHIPRES);
-        regWr(rUSBCTL, 0x00);
-        while(++i) {
-                if((regRd(rUSBIRQ) & bmOSCOKIRQ)) {
-                        break;
-                }
-        }
-        return ( i);
-}
-
-/* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
-template< typename SPI_SS, typename INTR >
-int8_t MAX3421e< SPI_SS, INTR >::Init() {
-        XMEM_ACQUIRE_SPI();
-        // Moved here.
-        // you really should not init hardware in the constructor when it involves locks.
-        // Also avoids the vbus flicker issue confusing some devices.
-        /* pin and peripheral setup */
-        SPI_SS::SetDirWrite();
-        SPI_SS::Set();
-        spi::init();
-        INTR::SetDirRead();
-        XMEM_RELEASE_SPI();
-        /* MAX3421E - full-duplex SPI, level interrupt */
-        // GPX pin on. Moved here, otherwise we flicker the vbus.
-        regWr(rPINCTL, (bmFDUPSPI | bmINTLEVEL));
-
-        if(reset() == 0) { //OSCOKIRQ hasn't asserted in time
-                return ( -1);
-        }
-
-        regWr(rMODE, bmDPPULLDN | bmDMPULLDN | bmHOST); // set pull-downs, Host
-
-        regWr(rHIEN, bmCONDETIE | bmFRAMEIE); //connection detection
-
-        /* check if device is connected */
-        regWr(rHCTL, bmSAMPLEBUS); // sample USB bus
-        while(!(regRd(rHCTL) & bmSAMPLEBUS)); //wait for sample operation to finish
-
-        busprobe(); //check if anything is connected
-
-        regWr(rHIRQ, bmCONDETIRQ); //clear connection detect interrupt
-        regWr(rCPUCTL, 0x01); //enable interrupt pin
-
-        return ( 0);
-}
-
-/* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
-template< typename SPI_SS, typename INTR >
-int8_t MAX3421e< SPI_SS, INTR >::Init(int mseconds) {
-        XMEM_ACQUIRE_SPI();
-        // Moved here.
-        // you really should not init hardware in the constructor when it involves locks.
-        // Also avoids the vbus flicker issue confusing some devices.
-        /* pin and peripheral setup */
-        SPI_SS::SetDirWrite();
-        SPI_SS::Set();
-        spi::init();
-        INTR::SetDirRead();
-        XMEM_RELEASE_SPI();
-        /* MAX3421E - full-duplex SPI, level interrupt, vbus off */
-        regWr(rPINCTL, (bmFDUPSPI | bmINTLEVEL | GPX_VBDET));
-
-        if(reset() == 0) { //OSCOKIRQ hasn't asserted in time
-                return ( -1);
-        }
-
-        // Delay a minimum of 1 second to ensure any capacitors are drained.
-        // 1 second is required to make sure we do not smoke a Microdrive!
-        if(mseconds < 1000) mseconds = 1000;
-        delay(mseconds);
-
-        regWr(rMODE, bmDPPULLDN | bmDMPULLDN | bmHOST); // set pull-downs, Host
-
-        regWr(rHIEN, bmCONDETIE | bmFRAMEIE); //connection detection
-
-        /* check if device is connected */
-        regWr(rHCTL, bmSAMPLEBUS); // sample USB bus
-        while(!(regRd(rHCTL) & bmSAMPLEBUS)); //wait for sample operation to finish
-
-        busprobe(); //check if anything is connected
-
-        regWr(rHIRQ, bmCONDETIRQ); //clear connection detect interrupt
-        regWr(rCPUCTL, 0x01); //enable interrupt pin
-
-        // GPX pin on. This is done here so that busprobe will fail if we have a switch connected.
-        regWr(rPINCTL, (bmFDUPSPI | bmINTLEVEL));
-
-        return ( 0);
-}
-
-/* probe bus to determine device presence and speed and switch host to this speed */
-template< typename SPI_SS, typename INTR >
-void MAX3421e< SPI_SS, INTR >::busprobe() {
-        uint8_t bus_sample;
-        bus_sample = regRd(rHRSL); //Get J,K status
-        bus_sample &= (bmJSTATUS | bmKSTATUS); //zero the rest of the byte
-        switch(bus_sample) { //start full-speed or low-speed host
-                case( bmJSTATUS):
-                        if((regRd(rMODE) & bmLOWSPEED) == 0) {
-                                regWr(rMODE, MODE_FS_HOST); //start full-speed host
-                                vbusState = FSHOST;
-                        } else {
-                                regWr(rMODE, MODE_LS_HOST); //start low-speed host
-                                vbusState = LSHOST;
-                        }
-                        break;
-                case( bmKSTATUS):
-                        if((regRd(rMODE) & bmLOWSPEED) == 0) {
-                                regWr(rMODE, MODE_LS_HOST); //start low-speed host
-                                vbusState = LSHOST;
-                        } else {
-                                regWr(rMODE, MODE_FS_HOST); //start full-speed host
-                                vbusState = FSHOST;
-                        }
-                        break;
-                case( bmSE1): //illegal state
-                        vbusState = SE1;
-                        break;
-                case( bmSE0): //disconnected state
-                        regWr(rMODE, bmDPPULLDN | bmDMPULLDN | bmHOST | bmSEPIRQ);
-                        vbusState = SE0;
-                        break;
-        }//end switch( bus_sample )
-}
-
-/* MAX3421 state change task and interrupt handler */
-template< typename SPI_SS, typename INTR >
-uint8_t MAX3421e< SPI_SS, INTR >::Task(void) {
-        uint8_t rcode = 0;
-        uint8_t pinvalue;
-        //USB_HOST_SERIAL.print("Vbus state: ");
-        //USB_HOST_SERIAL.println( vbusState, HEX );
-        pinvalue = INTR::IsSet(); //Read();
-        //pinvalue = digitalRead( MAX_INT );
-        if(pinvalue == 0) {
-                rcode = IntHandler();
-        }
-        //    pinvalue = digitalRead( MAX_GPX );
-        //    if( pinvalue == LOW ) {
-        //        GpxHandler();
-        //    }
-        //    usbSM();                                //USB state machine
-        return ( rcode);
-}
-
-template< typename SPI_SS, typename INTR >
-uint8_t MAX3421e< SPI_SS, INTR >::IntHandler() {
-        uint8_t HIRQ;
-        uint8_t HIRQ_sendback = 0x00;
-        HIRQ = regRd(rHIRQ); //determine interrupt source
-        //if( HIRQ & bmFRAMEIRQ ) {               //->1ms SOF interrupt handler
-        //    HIRQ_sendback |= bmFRAMEIRQ;
-        //}//end FRAMEIRQ handling
-        if(HIRQ & bmCONDETIRQ) {
-                busprobe();
-                HIRQ_sendback |= bmCONDETIRQ;
-        }
-        /* End HIRQ interrupts handling, clear serviced IRQs    */
-        regWr(rHIRQ, HIRQ_sendback);
-        return ( HIRQ_sendback);
-}
-//template< typename SPI_SS, typename INTR >
-//uint8_t MAX3421e< SPI_SS, INTR >::GpxHandler()
-//{
-//    uint8_t GPINIRQ = regRd( rGPINIRQ );          //read GPIN IRQ register
-////    if( GPINIRQ & bmGPINIRQ7 ) {            //vbus overload
-////        vbusPwr( OFF );                     //attempt powercycle
-////        delay( 1000 );
-////        vbusPwr( ON );
-////        regWr( rGPINIRQ, bmGPINIRQ7 );
-////    }
-//    return( GPINIRQ );
-//}
-
-#endif // _USBHOST_H_
diff --git a/lib/usbhost/USB_Host_Shield_2.0/usbhub.cpp b/lib/usbhost/USB_Host_Shield_2.0/usbhub.cpp
deleted file mode 100644
index 7fed48e781..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/usbhub.cpp
+++ /dev/null
@@ -1,425 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#include "usbhub.h"
-
-bool USBHub::bResetInitiated = false;
-
-USBHub::USBHub(USB *p) :
-pUsb(p),
-bAddress(0),
-bNbrPorts(0),
-//bInitState(0),
-qNextPollTime(0),
-bPollEnable(false) {
-        epInfo[0].epAddr = 0;
-        epInfo[0].maxPktSize = 8;
-        epInfo[0].epAttribs = 0;
-        epInfo[0].bmNakPower = USB_NAK_MAX_POWER;
-
-        epInfo[1].epAddr = 1;
-        epInfo[1].maxPktSize = 8; //kludge
-        epInfo[1].epAttribs = 0;
-        epInfo[1].bmNakPower = USB_NAK_NOWAIT;
-
-        if(pUsb)
-                pUsb->RegisterDeviceClass(this);
-}
-
-uint8_t USBHub::Init(uint8_t parent, uint8_t port, bool lowspeed) {
-        uint8_t buf[32];
-        USB_DEVICE_DESCRIPTOR * udd = reinterpret_cast<USB_DEVICE_DESCRIPTOR*>(buf);
-        HubDescriptor* hd = reinterpret_cast<HubDescriptor*>(buf);
-        USB_CONFIGURATION_DESCRIPTOR * ucd = reinterpret_cast<USB_CONFIGURATION_DESCRIPTOR*>(buf);
-        uint8_t rcode;
-        UsbDevice *p = NULL;
-        EpInfo *oldep_ptr = NULL;
-        uint8_t len = 0;
-        uint16_t cd_len = 0;
-
-        //USBTRACE("\r\nHub Init Start ");
-        //D_PrintHex<uint8_t > (bInitState, 0x80);
-
-        AddressPool &addrPool = pUsb->GetAddressPool();
-
-        //switch (bInitState) {
-        //        case 0:
-        if(bAddress)
-                return USB_ERROR_CLASS_INSTANCE_ALREADY_IN_USE;
-
-        // Get pointer to pseudo device with address 0 assigned
-        p = addrPool.GetUsbDevicePtr(0);
-
-        if(!p)
-                return USB_ERROR_ADDRESS_NOT_FOUND_IN_POOL;
-
-        if(!p->epinfo)
-                return USB_ERROR_EPINFO_IS_NULL;
-
-        // Save old pointer to EP_RECORD of address 0
-        oldep_ptr = p->epinfo;
-
-        // Temporary assign new pointer to epInfo to p->epinfo in order to avoid toggle inconsistence
-        p->epinfo = epInfo;
-
-        p->lowspeed = lowspeed;
-
-        // Get device descriptor
-        rcode = pUsb->getDevDescr(0, 0, 8, (uint8_t*)buf);
-
-        p->lowspeed = false;
-
-        if(!rcode)
-                len = (buf[0] > 32) ? 32 : buf[0];
-
-        if(rcode) {
-                // Restore p->epinfo
-                p->epinfo = oldep_ptr;
-                return rcode;
-        }
-
-        // Extract device class from device descriptor
-        // If device class is not a hub return
-        if(udd->bDeviceClass != 0x09)
-                return USB_DEV_CONFIG_ERROR_DEVICE_NOT_SUPPORTED;
-
-        // Allocate new address according to device class
-        bAddress = addrPool.AllocAddress(parent, (udd->bDeviceClass == 0x09) ? true : false, port);
-
-        if(!bAddress)
-                return USB_ERROR_OUT_OF_ADDRESS_SPACE_IN_POOL;
-
-        // Extract Max Packet Size from the device descriptor
-        epInfo[0].maxPktSize = udd->bMaxPacketSize0;
-
-        // Assign new address to the device
-        rcode = pUsb->setAddr(0, 0, bAddress);
-
-        if(rcode) {
-                // Restore p->epinfo
-                p->epinfo = oldep_ptr;
-                addrPool.FreeAddress(bAddress);
-                bAddress = 0;
-                return rcode;
-        }
-
-        //USBTRACE2("\r\nHub address: ", bAddress );
-
-        // Restore p->epinfo
-        p->epinfo = oldep_ptr;
-
-        if(len)
-                rcode = pUsb->getDevDescr(bAddress, 0, len, (uint8_t*)buf);
-
-        if(rcode)
-                goto FailGetDevDescr;
-
-        // Assign epInfo to epinfo pointer
-        rcode = pUsb->setEpInfoEntry(bAddress, 2, epInfo);
-
-        if(rcode)
-                goto FailSetDevTblEntry;
-
-        //                bInitState = 1;
-
-        //        case 1:
-        // Get hub descriptor
-        rcode = GetHubDescriptor(0, 8, buf);
-
-        if(rcode)
-                goto FailGetHubDescr;
-
-        // Save number of ports for future use
-        bNbrPorts = hd->bNbrPorts;
-
-        //                bInitState = 2;
-
-        //        case 2:
-        // Read configuration Descriptor in Order To Obtain Proper Configuration Value
-        rcode = pUsb->getConfDescr(bAddress, 0, 8, 0, buf);
-
-        if(!rcode) {
-                cd_len = ucd->wTotalLength;
-                rcode = pUsb->getConfDescr(bAddress, 0, cd_len, 0, buf);
-        }
-        if(rcode)
-                goto FailGetConfDescr;
-
-        // The following code is of no practical use in real life applications.
-        // It only intended for the usb protocol sniffer to properly parse hub-class requests.
-        {
-                uint8_t buf2[24];
-
-                rcode = pUsb->getConfDescr(bAddress, 0, buf[0], 0, buf2);
-
-                if(rcode)
-                        goto FailGetConfDescr;
-        }
-
-        // Set Configuration Value
-        rcode = pUsb->setConf(bAddress, 0, buf[5]);
-
-        if(rcode)
-                goto FailSetConfDescr;
-
-        //                bInitState = 3;
-
-        //        case 3:
-        // Power on all ports
-        for(uint8_t j = 1; j <= bNbrPorts; j++)
-                SetPortFeature(HUB_FEATURE_PORT_POWER, j, 0); //HubPortPowerOn(j);
-
-        pUsb->SetHubPreMask();
-        bPollEnable = true;
-        //                bInitState = 0;
-        //}
-        //bInitState = 0;
-        //USBTRACE("...OK\r\n");
-        return 0;
-
-        // Oleg, No debugging?? -- xxxajk
-FailGetDevDescr:
-        goto Fail;
-
-FailSetDevTblEntry:
-        goto Fail;
-
-FailGetHubDescr:
-        goto Fail;
-
-FailGetConfDescr:
-        goto Fail;
-
-FailSetConfDescr:
-        goto Fail;
-
-Fail:
-        USBTRACE("...FAIL\r\n");
-        return rcode;
-}
-
-uint8_t USBHub::Release() {
-        pUsb->GetAddressPool().FreeAddress(bAddress);
-
-        if(bAddress == 0x41)
-                pUsb->SetHubPreMask();
-
-        bAddress = 0;
-        bNbrPorts = 0;
-        qNextPollTime = 0;
-        bPollEnable = false;
-        return 0;
-}
-
-uint8_t USBHub::Poll() {
-        uint8_t rcode = 0;
-
-        if(!bPollEnable)
-                return 0;
-
-        if(((long)(millis() - qNextPollTime) >= 0L)) {
-                rcode = CheckHubStatus();
-                qNextPollTime = millis() + 100;
-        }
-        return rcode;
-}
-
-uint8_t USBHub::CheckHubStatus() {
-        uint8_t rcode;
-        uint8_t buf[8];
-        uint16_t read = 1;
-
-        rcode = pUsb->inTransfer(bAddress, 1, &read, buf);
-
-        if(rcode)
-                return rcode;
-
-        //if (buf[0] & 0x01) // Hub Status Change
-        //{
-        //        pUsb->PrintHubStatus(addr);
-        //        rcode = GetHubStatus(1, 0, 1, 4, buf);
-        //        if (rcode)
-        //        {
-        //                USB_HOST_SERIAL.print("GetHubStatus Error");
-        //                USB_HOST_SERIAL.println(rcode, HEX);
-        //                return rcode;
-        //        }
-        //}
-        for(uint8_t port = 1, mask = 0x02; port < 8; mask <<= 1, port++) {
-                if(buf[0] & mask) {
-                        HubEvent evt;
-                        evt.bmEvent = 0;
-
-                        rcode = GetPortStatus(port, 4, evt.evtBuff);
-
-                        if(rcode)
-                                continue;
-
-                        rcode = PortStatusChange(port, evt);
-
-                        if(rcode == HUB_ERROR_PORT_HAS_BEEN_RESET)
-                                return 0;
-
-                        if(rcode)
-                                return rcode;
-                }
-        } // for
-
-        for(uint8_t port = 1; port <= bNbrPorts; port++) {
-                HubEvent evt;
-                evt.bmEvent = 0;
-
-                rcode = GetPortStatus(port, 4, evt.evtBuff);
-
-                if(rcode)
-                        continue;
-
-                if((evt.bmStatus & bmHUB_PORT_STATE_CHECK_DISABLED) != bmHUB_PORT_STATE_DISABLED)
-                        continue;
-
-                // Emulate connection event for the port
-                evt.bmChange |= bmHUB_PORT_STATUS_C_PORT_CONNECTION;
-
-                rcode = PortStatusChange(port, evt);
-
-                if(rcode == HUB_ERROR_PORT_HAS_BEEN_RESET)
-                        return 0;
-
-                if(rcode)
-                        return rcode;
-        } // for
-        return 0;
-}
-
-void USBHub::ResetHubPort(uint8_t port) {
-        HubEvent evt;
-        evt.bmEvent = 0;
-        uint8_t rcode;
-
-        ClearPortFeature(HUB_FEATURE_C_PORT_ENABLE, port, 0);
-        ClearPortFeature(HUB_FEATURE_C_PORT_CONNECTION, port, 0);
-        SetPortFeature(HUB_FEATURE_PORT_RESET, port, 0);
-
-
-        for(int i = 0; i < 3; i++) {
-                rcode = GetPortStatus(port, 4, evt.evtBuff);
-                if(rcode) break; // Some kind of error, bail.
-                if(evt.bmEvent == bmHUB_PORT_EVENT_RESET_COMPLETE || evt.bmEvent == bmHUB_PORT_EVENT_LS_RESET_COMPLETE) {
-                        break;
-                }
-                delay(100); // simulate polling.
-        }
-        ClearPortFeature(HUB_FEATURE_C_PORT_RESET, port, 0);
-        ClearPortFeature(HUB_FEATURE_C_PORT_CONNECTION, port, 0);
-        delay(20);
-}
-
-uint8_t USBHub::PortStatusChange(uint8_t port, HubEvent &evt) {
-        switch(evt.bmEvent) {
-                        // Device connected event
-                case bmHUB_PORT_EVENT_CONNECT:
-                case bmHUB_PORT_EVENT_LS_CONNECT:
-                        if(bResetInitiated)
-                                return 0;
-
-                        ClearPortFeature(HUB_FEATURE_C_PORT_ENABLE, port, 0);
-                        ClearPortFeature(HUB_FEATURE_C_PORT_CONNECTION, port, 0);
-                        SetPortFeature(HUB_FEATURE_PORT_RESET, port, 0);
-                        bResetInitiated = true;
-                        return HUB_ERROR_PORT_HAS_BEEN_RESET;
-
-                        // Device disconnected event
-                case bmHUB_PORT_EVENT_DISCONNECT:
-                        ClearPortFeature(HUB_FEATURE_C_PORT_ENABLE, port, 0);
-                        ClearPortFeature(HUB_FEATURE_C_PORT_CONNECTION, port, 0);
-                        bResetInitiated = false;
-
-                        UsbDeviceAddress a;
-                        a.devAddress = 0;
-                        a.bmHub = 0;
-                        a.bmParent = bAddress;
-                        a.bmAddress = port;
-                        pUsb->ReleaseDevice(a.devAddress);
-                        return 0;
-
-                        // Reset complete event
-                case bmHUB_PORT_EVENT_RESET_COMPLETE:
-                case bmHUB_PORT_EVENT_LS_RESET_COMPLETE:
-                        ClearPortFeature(HUB_FEATURE_C_PORT_RESET, port, 0);
-                        ClearPortFeature(HUB_FEATURE_C_PORT_CONNECTION, port, 0);
-
-                        delay(20);
-
-                        a.devAddress = bAddress;
-
-                        pUsb->Configuring(a.bmAddress, port, (evt.bmStatus & bmHUB_PORT_STATUS_PORT_LOW_SPEED));
-                        bResetInitiated = false;
-                        break;
-
-        } // switch (evt.bmEvent)
-        return 0;
-}
-
-void PrintHubPortStatus(USBHub *hubptr, uint8_t addr, uint8_t port, bool print_changes) {
-        uint8_t rcode = 0;
-        HubEvent evt;
-
-        rcode = hubptr->GetPortStatus(port, 4, evt.evtBuff);
-
-        if(rcode) {
-                USB_HOST_SERIAL.println("ERROR!");
-                return;
-        }
-        USB_HOST_SERIAL.print("\r\nPort ");
-        USB_HOST_SERIAL.println(port, DEC);
-
-        USB_HOST_SERIAL.println("Status");
-        USB_HOST_SERIAL.print("CONNECTION:\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_CONNECTION) > 0, DEC);
-        USB_HOST_SERIAL.print("ENABLE:\t\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_ENABLE) > 0, DEC);
-        USB_HOST_SERIAL.print("SUSPEND:\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_SUSPEND) > 0, DEC);
-        USB_HOST_SERIAL.print("OVER_CURRENT:\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_OVER_CURRENT) > 0, DEC);
-        USB_HOST_SERIAL.print("RESET:\t\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_RESET) > 0, DEC);
-        USB_HOST_SERIAL.print("POWER:\t\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_POWER) > 0, DEC);
-        USB_HOST_SERIAL.print("LOW_SPEED:\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_LOW_SPEED) > 0, DEC);
-        USB_HOST_SERIAL.print("HIGH_SPEED:\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_HIGH_SPEED) > 0, DEC);
-        USB_HOST_SERIAL.print("TEST:\t\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_TEST) > 0, DEC);
-        USB_HOST_SERIAL.print("INDICATOR:\t");
-        USB_HOST_SERIAL.println((evt.bmStatus & bmHUB_PORT_STATUS_PORT_INDICATOR) > 0, DEC);
-
-        if(!print_changes)
-                return;
-
-        USB_HOST_SERIAL.println("\r\nChange");
-        USB_HOST_SERIAL.print("CONNECTION:\t");
-        USB_HOST_SERIAL.println((evt.bmChange & bmHUB_PORT_STATUS_C_PORT_CONNECTION) > 0, DEC);
-        USB_HOST_SERIAL.print("ENABLE:\t\t");
-        USB_HOST_SERIAL.println((evt.bmChange & bmHUB_PORT_STATUS_C_PORT_ENABLE) > 0, DEC);
-        USB_HOST_SERIAL.print("SUSPEND:\t");
-        USB_HOST_SERIAL.println((evt.bmChange & bmHUB_PORT_STATUS_C_PORT_SUSPEND) > 0, DEC);
-        USB_HOST_SERIAL.print("OVER_CURRENT:\t");
-        USB_HOST_SERIAL.println((evt.bmChange & bmHUB_PORT_STATUS_C_PORT_OVER_CURRENT) > 0, DEC);
-        USB_HOST_SERIAL.print("RESET:\t\t");
-        USB_HOST_SERIAL.println((evt.bmChange & bmHUB_PORT_STATUS_C_PORT_RESET) > 0, DEC);
-}
diff --git a/lib/usbhost/USB_Host_Shield_2.0/usbhub.h b/lib/usbhost/USB_Host_Shield_2.0/usbhub.h
deleted file mode 100644
index 1ac949445a..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/usbhub.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-#if !defined(__USBHUB_H__)
-#define __USBHUB_H__
-
-#include "Usb.h"
-
-#define USB_DESCRIPTOR_HUB                      0x09 // Hub descriptor type
-
-// Hub Requests
-#define bmREQ_CLEAR_HUB_FEATURE                 USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_DEVICE
-#define bmREQ_CLEAR_PORT_FEATURE                USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_OTHER
-#define bmREQ_CLEAR_TT_BUFFER                   USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_OTHER
-#define bmREQ_GET_HUB_DESCRIPTOR                USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_DEVICE
-#define bmREQ_GET_HUB_STATUS                    USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_DEVICE
-#define bmREQ_GET_PORT_STATUS                   USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_OTHER
-#define bmREQ_RESET_TT                          USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_OTHER
-#define bmREQ_SET_HUB_DESCRIPTOR                USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_DEVICE
-#define bmREQ_SET_HUB_FEATURE                   USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_DEVICE
-#define bmREQ_SET_PORT_FEATURE                  USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_OTHER
-#define bmREQ_GET_TT_STATE                      USB_SETUP_DEVICE_TO_HOST|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_OTHER
-#define bmREQ_STOP_TT                           USB_SETUP_HOST_TO_DEVICE|USB_SETUP_TYPE_CLASS|USB_SETUP_RECIPIENT_OTHER
-
-// Hub Class Requests
-#define HUB_REQUEST_CLEAR_TT_BUFFER             8
-#define HUB_REQUEST_RESET_TT                    9
-#define HUB_REQUEST_GET_TT_STATE                10
-#define HUB_REQUEST_STOP_TT                     11
-
-// Hub Features
-#define HUB_FEATURE_C_HUB_LOCAL_POWER           0
-#define HUB_FEATURE_C_HUB_OVER_CURRENT          1
-#define HUB_FEATURE_PORT_CONNECTION             0
-#define HUB_FEATURE_PORT_ENABLE                 1
-#define HUB_FEATURE_PORT_SUSPEND                2
-#define HUB_FEATURE_PORT_OVER_CURRENT           3
-#define HUB_FEATURE_PORT_RESET                  4
-#define HUB_FEATURE_PORT_POWER                  8
-#define HUB_FEATURE_PORT_LOW_SPEED              9
-#define HUB_FEATURE_C_PORT_CONNECTION           16
-#define HUB_FEATURE_C_PORT_ENABLE               17
-#define HUB_FEATURE_C_PORT_SUSPEND              18
-#define HUB_FEATURE_C_PORT_OVER_CURRENT         19
-#define HUB_FEATURE_C_PORT_RESET                20
-#define HUB_FEATURE_PORT_TEST                   21
-#define HUB_FEATURE_PORT_INDICATOR              22
-
-// Hub Port Test Modes
-#define HUB_PORT_TEST_MODE_J                    1
-#define HUB_PORT_TEST_MODE_K                    2
-#define HUB_PORT_TEST_MODE_SE0_NAK              3
-#define HUB_PORT_TEST_MODE_PACKET               4
-#define HUB_PORT_TEST_MODE_FORCE_ENABLE         5
-
-// Hub Port Indicator Color
-#define HUB_PORT_INDICATOR_AUTO                 0
-#define HUB_PORT_INDICATOR_AMBER                1
-#define HUB_PORT_INDICATOR_GREEN                2
-#define HUB_PORT_INDICATOR_OFF                  3
-
-// Hub Port Status Bitmasks
-#define bmHUB_PORT_STATUS_PORT_CONNECTION       0x0001
-#define bmHUB_PORT_STATUS_PORT_ENABLE           0x0002
-#define bmHUB_PORT_STATUS_PORT_SUSPEND          0x0004
-#define bmHUB_PORT_STATUS_PORT_OVER_CURRENT     0x0008
-#define bmHUB_PORT_STATUS_PORT_RESET            0x0010
-#define bmHUB_PORT_STATUS_PORT_POWER            0x0100
-#define bmHUB_PORT_STATUS_PORT_LOW_SPEED        0x0200
-#define bmHUB_PORT_STATUS_PORT_HIGH_SPEED       0x0400
-#define bmHUB_PORT_STATUS_PORT_TEST             0x0800
-#define bmHUB_PORT_STATUS_PORT_INDICATOR        0x1000
-
-// Hub Port Status Change Bitmasks (used one byte instead of two)
-#define bmHUB_PORT_STATUS_C_PORT_CONNECTION     0x0001
-#define bmHUB_PORT_STATUS_C_PORT_ENABLE         0x0002
-#define bmHUB_PORT_STATUS_C_PORT_SUSPEND        0x0004
-#define bmHUB_PORT_STATUS_C_PORT_OVER_CURRENT   0x0008
-#define bmHUB_PORT_STATUS_C_PORT_RESET          0x0010
-
-// Hub Status Bitmasks (used one byte instead of two)
-#define bmHUB_STATUS_LOCAL_POWER_SOURCE         0x01
-#define bmHUB_STATUS_OVER_CURRENT               0x12
-
-// Hub Status Change Bitmasks (used one byte instead of two)
-#define bmHUB_STATUS_C_LOCAL_POWER_SOURCE       0x01
-#define bmHUB_STATUS_C_OVER_CURRENT             0x12
-
-
-// Hub Port Configuring Substates
-#define USB_STATE_HUB_PORT_CONFIGURING          0xb0
-#define USB_STATE_HUB_PORT_POWERED_OFF          0xb1
-#define USB_STATE_HUB_PORT_WAIT_FOR_POWER_GOOD  0xb2
-#define USB_STATE_HUB_PORT_DISCONNECTED         0xb3
-#define USB_STATE_HUB_PORT_DISABLED             0xb4
-#define USB_STATE_HUB_PORT_RESETTING            0xb5
-#define USB_STATE_HUB_PORT_ENABLED              0xb6
-
-// Additional Error Codes
-#define HUB_ERROR_PORT_HAS_BEEN_RESET           0xb1
-
-// The bit mask to check for all necessary state bits
-#define bmHUB_PORT_STATUS_ALL_MAIN              ((0UL | bmHUB_PORT_STATUS_C_PORT_CONNECTION | bmHUB_PORT_STATUS_C_PORT_ENABLE | bmHUB_PORT_STATUS_C_PORT_SUSPEND | bmHUB_PORT_STATUS_C_PORT_RESET) << 16) | bmHUB_PORT_STATUS_PORT_POWER | bmHUB_PORT_STATUS_PORT_ENABLE | bmHUB_PORT_STATUS_PORT_CONNECTION | bmHUB_PORT_STATUS_PORT_SUSPEND)
-
-// Bit mask to check for DISABLED state in HubEvent::bmStatus field
-#define bmHUB_PORT_STATE_CHECK_DISABLED         (0x0000 | bmHUB_PORT_STATUS_PORT_POWER | bmHUB_PORT_STATUS_PORT_ENABLE | bmHUB_PORT_STATUS_PORT_CONNECTION | bmHUB_PORT_STATUS_PORT_SUSPEND)
-
-// Hub Port States
-#define bmHUB_PORT_STATE_DISABLED               (0x0000 | bmHUB_PORT_STATUS_PORT_POWER | bmHUB_PORT_STATUS_PORT_CONNECTION)
-
-// Hub Port Events
-#define bmHUB_PORT_EVENT_CONNECT                (((0UL | bmHUB_PORT_STATUS_C_PORT_CONNECTION) << 16) | bmHUB_PORT_STATUS_PORT_POWER | bmHUB_PORT_STATUS_PORT_CONNECTION)
-#define bmHUB_PORT_EVENT_DISCONNECT             (((0UL | bmHUB_PORT_STATUS_C_PORT_CONNECTION) << 16) | bmHUB_PORT_STATUS_PORT_POWER)
-#define bmHUB_PORT_EVENT_RESET_COMPLETE         (((0UL | bmHUB_PORT_STATUS_C_PORT_RESET) << 16) | bmHUB_PORT_STATUS_PORT_POWER | bmHUB_PORT_STATUS_PORT_ENABLE | bmHUB_PORT_STATUS_PORT_CONNECTION)
-
-#define bmHUB_PORT_EVENT_LS_CONNECT             (((0UL | bmHUB_PORT_STATUS_C_PORT_CONNECTION) << 16) | bmHUB_PORT_STATUS_PORT_POWER | bmHUB_PORT_STATUS_PORT_CONNECTION | bmHUB_PORT_STATUS_PORT_LOW_SPEED)
-#define bmHUB_PORT_EVENT_LS_RESET_COMPLETE      (((0UL | bmHUB_PORT_STATUS_C_PORT_RESET) << 16) | bmHUB_PORT_STATUS_PORT_POWER | bmHUB_PORT_STATUS_PORT_ENABLE | bmHUB_PORT_STATUS_PORT_CONNECTION | bmHUB_PORT_STATUS_PORT_LOW_SPEED)
-#define bmHUB_PORT_EVENT_LS_PORT_ENABLED        (((0UL | bmHUB_PORT_STATUS_C_PORT_CONNECTION | bmHUB_PORT_STATUS_C_PORT_ENABLE) << 16) | bmHUB_PORT_STATUS_PORT_POWER | bmHUB_PORT_STATUS_PORT_ENABLE | bmHUB_PORT_STATUS_PORT_CONNECTION | bmHUB_PORT_STATUS_PORT_LOW_SPEED)
-
-struct HubDescriptor {
-        uint8_t bDescLength; // descriptor length
-        uint8_t bDescriptorType; // descriptor type
-        uint8_t bNbrPorts; // number of ports a hub equiped with
-
-        struct {
-                uint16_t LogPwrSwitchMode : 2;
-                uint16_t CompoundDevice : 1;
-                uint16_t OverCurrentProtectMode : 2;
-                uint16_t TTThinkTime : 2;
-                uint16_t PortIndicatorsSupported : 1;
-                uint16_t Reserved : 8;
-        } __attribute__((packed));
-
-        uint8_t bPwrOn2PwrGood;
-        uint8_t bHubContrCurrent;
-} __attribute__((packed));
-
-struct HubEvent {
-
-        union {
-
-                struct {
-                        uint16_t bmStatus; // port status bits
-                        uint16_t bmChange; // port status change bits
-                } __attribute__((packed));
-                uint32_t bmEvent;
-                uint8_t evtBuff[4];
-        };
-} __attribute__((packed));
-
-class USBHub : USBDeviceConfig {
-        static bool bResetInitiated; // True when reset is triggered
-
-        USB *pUsb; // USB class instance pointer
-
-        EpInfo epInfo[2]; // interrupt endpoint info structure
-
-        uint8_t bAddress; // address
-        uint8_t bNbrPorts; // number of ports
-        //        uint8_t bInitState; // initialization state variable
-        uint32_t qNextPollTime; // next poll time
-        bool bPollEnable; // poll enable flag
-
-        uint8_t CheckHubStatus();
-        uint8_t PortStatusChange(uint8_t port, HubEvent &evt);
-
-public:
-        USBHub(USB *p);
-
-        uint8_t ClearHubFeature(uint8_t fid);
-        uint8_t ClearPortFeature(uint8_t fid, uint8_t port, uint8_t sel = 0);
-        uint8_t GetHubDescriptor(uint8_t index, uint16_t nbytes, uint8_t *dataptr);
-        uint8_t GetHubStatus(uint16_t nbytes, uint8_t* dataptr);
-        uint8_t GetPortStatus(uint8_t port, uint16_t nbytes, uint8_t* dataptr);
-        uint8_t SetHubDescriptor(uint8_t port, uint16_t nbytes, uint8_t* dataptr);
-        uint8_t SetHubFeature(uint8_t fid);
-        uint8_t SetPortFeature(uint8_t fid, uint8_t port, uint8_t sel = 0);
-
-        void PrintHubStatus();
-
-        uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
-        uint8_t Release();
-        uint8_t Poll();
-        void ResetHubPort(uint8_t port);
-
-        virtual uint8_t GetAddress() {
-                return bAddress;
-        };
-
-        virtual bool DEVCLASSOK(uint8_t klass) {
-                return (klass == 0x09);
-        }
-
-};
-
-// Clear Hub Feature
-
-inline uint8_t USBHub::ClearHubFeature(uint8_t fid) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_CLEAR_HUB_FEATURE, USB_REQUEST_CLEAR_FEATURE, fid, 0, 0, 0, 0, NULL, NULL));
-}
-// Clear Port Feature
-
-inline uint8_t USBHub::ClearPortFeature(uint8_t fid, uint8_t port, uint8_t sel) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_CLEAR_PORT_FEATURE, USB_REQUEST_CLEAR_FEATURE, fid, 0, ((0x0000 | port) | (sel << 8)), 0, 0, NULL, NULL));
-}
-// Get Hub Descriptor
-
-inline uint8_t USBHub::GetHubDescriptor(uint8_t index, uint16_t nbytes, uint8_t *dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_GET_HUB_DESCRIPTOR, USB_REQUEST_GET_DESCRIPTOR, index, 0x29, 0, nbytes, nbytes, dataptr, NULL));
-}
-// Get Hub Status
-
-inline uint8_t USBHub::GetHubStatus(uint16_t nbytes, uint8_t* dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_GET_HUB_STATUS, USB_REQUEST_GET_STATUS, 0, 0, 0x0000, nbytes, nbytes, dataptr, NULL));
-}
-// Get Port Status
-
-inline uint8_t USBHub::GetPortStatus(uint8_t port, uint16_t nbytes, uint8_t* dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_GET_PORT_STATUS, USB_REQUEST_GET_STATUS, 0, 0, port, nbytes, nbytes, dataptr, NULL));
-}
-// Set Hub Descriptor
-
-inline uint8_t USBHub::SetHubDescriptor(uint8_t port, uint16_t nbytes, uint8_t* dataptr) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_SET_HUB_DESCRIPTOR, USB_REQUEST_SET_DESCRIPTOR, 0, 0, port, nbytes, nbytes, dataptr, NULL));
-}
-// Set Hub Feature
-
-inline uint8_t USBHub::SetHubFeature(uint8_t fid) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_SET_HUB_FEATURE, USB_REQUEST_SET_FEATURE, fid, 0, 0, 0, 0, NULL, NULL));
-}
-// Set Port Feature
-
-inline uint8_t USBHub::SetPortFeature(uint8_t fid, uint8_t port, uint8_t sel) {
-        return ( pUsb->ctrlReq(bAddress, 0, bmREQ_SET_PORT_FEATURE, USB_REQUEST_SET_FEATURE, fid, 0, (((0x0000 | sel) << 8) | port), 0, 0, NULL, NULL));
-}
-
-void PrintHubPortStatus(USB *usbptr, uint8_t addr, uint8_t port, bool print_changes = false);
-
-#endif // __USBHUB_H__
diff --git a/lib/usbhost/USB_Host_Shield_2.0/version_helper.h b/lib/usbhost/USB_Host_Shield_2.0/version_helper.h
deleted file mode 100644
index 0cb3b4adc0..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/version_helper.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
-
-This software may be distributed and modified under the terms of the GNU
-General Public License version 2 (GPL2) as published by the Free Software
-Foundation and appearing in the file GPL2.TXT included in the packaging of
-this file. Please note that GPL2 Section 2[b] requires that all works based
-on this software must also be made publicly available under the terms of
-the GPL2 ("Copyleft").
-
-Contact information
--------------------
-
-Circuits At Home, LTD
-Web      :  http://www.circuitsathome.com
-e-mail   :  support@circuitsathome.com
- */
-
-/*
- * Universal Arduino(tm) "IDE" fixups.
- * Includes fixes for versions as low as 0023, used by Digilent.
- */
-
-#if defined(ARDUINO) && ARDUINO >=100
-#include <Arduino.h>
-#else
-#include <WProgram.h>
-#include <pins_arduino.h>
-#ifdef __AVR__
-#include <avr/pgmspace.h>
-#include <avr/io.h>
-#else
-#endif
-#endif
-
-#ifndef __PGMSPACE_H_
-#define __PGMSPACE_H_ 1
-
-#include <inttypes.h>
-
-#ifndef PROGMEM
-#define PROGMEM
-#endif
-#ifndef PGM_P
-#define PGM_P  const char *
-#endif
-#ifndef PSTR
-#define PSTR(str) (str)
-#endif
-#ifndef F
-#define F(str) (str)
-#endif
-#ifndef _SFR_BYTE
-#define _SFR_BYTE(n) (n)
-#endif
-
-#ifndef memchr_P
-#define memchr_P(str, c, len) memchr((str), (c), (len))
-#endif
-#ifndef memcmp_P
-#define memcmp_P(a, b, n) memcmp((a), (b), (n))
-#endif
-#ifndef memcpy_P
-#define memcpy_P(dest, src, num) memcpy((dest), (src), (num))
-#endif
-#ifndef memmem_P
-#define memmem_P(a, alen, b, blen) memmem((a), (alen), (b), (blen))
-#endif
-#ifndef memrchr_P
-#define memrchr_P(str, val, len) memrchr((str), (val), (len))
-#endif
-#ifndef strcat_P
-#define strcat_P(dest, src) strcat((dest), (src))
-#endif
-#ifndef strchr_P
-#define strchr_P(str, c) strchr((str), (c))
-#endif
-#ifndef strchrnul_P
-#define strchrnul_P(str, c) strchrnul((str), (c))
-#endif
-#ifndef strcmp_P
-#define strcmp_P(a, b) strcmp((a), (b))
-#endif
-#ifndef strcpy_P
-#define strcpy_P(dest, src) strcpy((dest), (src))
-#endif
-#ifndef strcasecmp_P
-#define strcasecmp_P(a, b) strcasecmp((a), (b))
-#endif
-#ifndef strcasestr_P
-#define strcasestr_P(a, b) strcasestr((a), (b))
-#endif
-#ifndef strlcat_P
-#define strlcat_P(dest, src, len) strlcat((dest), (src), (len))
-#endif
-#ifndef strlcpy_P
-#define strlcpy_P(dest, src, len) strlcpy((dest), (src), (len))
-#endif
-#ifndef strlen_P
-#define strlen_P(s) strlen((const char *)(s))
-#endif
-#ifndef strnlen_P
-#define strnlen_P(str, len) strnlen((str), (len))
-#endif
-#ifndef strncmp_P
-#define strncmp_P(a, b, n) strncmp((a), (b), (n))
-#endif
-#ifndef strncasecmp_P
-#define strncasecmp_P(a, b, n) strncasecmp((a), (b), (n))
-#endif
-#ifndef strncat_P
-#define strncat_P(a, b, n) strncat((a), (b), (n))
-#endif
-#ifndef strncpy_P
-#define strncpy_P(a, b, n) strncmp((a), (b), (n))
-#endif
-#ifndef strpbrk_P
-#define strpbrk_P(str, chrs) strpbrk((str), (chrs))
-#endif
-#ifndef strrchr_P
-#define strrchr_P(str, c) strrchr((str), (c))
-#endif
-#ifndef strsep_P
-#define strsep_P(strp, delim) strsep((strp), (delim))
-#endif
-#ifndef strspn_P
-#define strspn_P(str, chrs) strspn((str), (chrs))
-#endif
-#ifndef strstr_P
-#define strstr_P(a, b) strstr((a), (b))
-#endif
-#ifndef sprintf_P
-#define sprintf_P(s, ...) sprintf((s), __VA_ARGS__)
-#endif
-#ifndef vfprintf_P
-#define vfprintf_P(s, ...) vfprintf((s), __VA_ARGS__)
-#endif
-#ifndef printf_P
-#define printf_P(...) printf(__VA_ARGS__)
-#endif
-#ifndef snprintf_P
-#define snprintf_P(s, n, ...) ((s), (n), __VA_ARGS__)
-#endif
-#ifndef vsprintf_P
-#define vsprintf_P(s, ...) ((s),__VA_ARGS__)
-#endif
-#ifndef vsnprintf_P
-#define vsnprintf_P(s, n, ...) ((s), (n),__VA_ARGS__)
-#endif
-#ifndef fprintf_P
-#define fprintf_P(s, ...) ((s), __VA_ARGS__)
-#endif
-
-#ifndef pgm_read_byte
-#define pgm_read_byte(addr) (*(const unsigned char *)(addr))
-#endif
-#ifndef pgm_read_word
-#define pgm_read_word(addr) (*(const unsigned short *)(addr))
-#endif
-#ifndef pgm_read_dword
-#define pgm_read_dword(addr) (*(const unsigned long *)(addr))
-#endif
-#ifndef pgm_read_float
-#define pgm_read_float(addr) (*(const float *)(addr))
-#endif
-
-#ifndef pgm_read_byte_near
-#define pgm_read_byte_near(addr) pgm_read_byte(addr)
-#endif
-#ifndef pgm_read_word_near
-#define pgm_read_word_near(addr) pgm_read_word(addr)
-#endif
-#ifndef pgm_read_dword_near
-#define pgm_read_dword_near(addr) pgm_read_dword(addr)
-#endif
-#ifndef pgm_read_float_near
-#define pgm_read_float_near(addr) pgm_read_float(addr)
-#endif
-#ifndef pgm_read_byte_far
-#define pgm_read_byte_far(addr) pgm_read_byte(addr)
-#endif
-#ifndef pgm_read_word_far
-#define pgm_read_word_far(addr) pgm_read_word(addr)
-#endif
-#ifndef pgm_read_dword_far
-#define pgm_read_dword_far(addr) pgm_read_dword(addr)
-#endif
-#ifndef pgm_read_float_far
-#define pgm_read_float_far(addr) pgm_read_float(addr)
-#endif
-
-#ifndef pgm_read_pointer
-#define pgm_read_pointer
-#endif
-#endif
diff --git a/lib/usbhost/USB_Host_Shield_2.0/xboxEnums.h b/lib/usbhost/USB_Host_Shield_2.0/xboxEnums.h
deleted file mode 100644
index 84b137bb6e..0000000000
--- a/lib/usbhost/USB_Host_Shield_2.0/xboxEnums.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright (C) 2012 Kristian Lauszus, TKJ Electronics. All rights reserved.
-
- This software may be distributed and modified under the terms of the GNU
- General Public License version 2 (GPL2) as published by the Free Software
- Foundation and appearing in the file GPL2.TXT included in the packaging of
- this file. Please note that GPL2 Section 2[b] requires that all works based
- on this software must also be made publicly available under the terms of
- the GPL2 ("Copyleft").
-
- Contact information
- -------------------
-
- Kristian Lauszus, TKJ Electronics
- Web      :  http://www.tkjelectronics.com
- e-mail   :  kristianl@tkjelectronics.com
- */
-
-#ifndef _xboxenums_h
-#define _xboxenums_h
-
-#include "controllerEnums.h"
-
-/** Enum used to set special LED modes supported by the Xbox controller. */
-enum LEDModeEnum {
-        ROTATING = 0x0A,
-        FASTBLINK = 0x0B,
-        SLOWBLINK = 0x0C,
-        ALTERNATING = 0x0D,
-};
-
-/** Used to set the LEDs on the controllers */
-const uint8_t XBOX_LEDS[] PROGMEM = {
-        0x00, // OFF
-        0x02, // LED1
-        0x03, // LED2
-        0x04, // LED3
-        0x05, // LED4
-        0x01, // ALL - Used to blink all LEDs
-};
-/** Buttons on the controllers */
-const uint16_t XBOX_BUTTONS[] PROGMEM = {
-        0x0100, // UP
-        0x0800, // RIGHT
-        0x0200, // DOWN
-        0x0400, // LEFT
-
-        0x2000, // BACK
-        0x1000, // START
-        0x4000, // L3
-        0x8000, // R3
-
-        0, 0, // Skip L2 and R2 as these are analog buttons
-        0x0001, // L1
-        0x0002, // R1
-
-        0x0020, // B
-        0x0010, // A
-        0x0040, // X
-        0x0080, // Y
-
-        0x0004, // XBOX
-        0x0008, // SYNC
-};
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Arduino.h b/lib/usbhost/arduino-1.0.1/cores/arduino/Arduino.h
deleted file mode 100644
index 830c9952fb..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Arduino.h
+++ /dev/null
@@ -1,215 +0,0 @@
-#ifndef Arduino_h
-#define Arduino_h
-
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#include <avr/pgmspace.h>
-#include <avr/io.h>
-#include <avr/interrupt.h>
-
-#include "binary.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#define HIGH 0x1
-#define LOW  0x0
-
-#define INPUT 0x0
-#define OUTPUT 0x1
-#define INPUT_PULLUP 0x2
-
-#define true 0x1
-#define false 0x0
-
-#define PI 3.1415926535897932384626433832795
-#define HALF_PI 1.5707963267948966192313216916398
-#define TWO_PI 6.283185307179586476925286766559
-#define DEG_TO_RAD 0.017453292519943295769236907684886
-#define RAD_TO_DEG 57.295779513082320876798154814105
-
-#define SERIAL  0x0
-#define DISPLAY 0x1
-
-#define LSBFIRST 0
-#define MSBFIRST 1
-
-#define CHANGE 1
-#define FALLING 2
-#define RISING 3
-
-#if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__)
-#define DEFAULT 0
-#define EXTERNAL 1
-#define INTERNAL 2
-#else  
-#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1284P__) 
-#define INTERNAL1V1 2
-#define INTERNAL2V56 3
-#else
-#define INTERNAL 3
-#endif
-#define DEFAULT 1
-#define EXTERNAL 0
-#endif
-
-// undefine stdlib's abs if encountered
-#ifdef abs
-#undef abs
-#endif
-
-#define min(a,b) ((a)<(b)?(a):(b))
-#define max(a,b) ((a)>(b)?(a):(b))
-#define abs(x) ((x)>0?(x):-(x))
-#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt)))
-#define round(x)     ((x)>=0?(long)((x)+0.5):(long)((x)-0.5))
-#define radians(deg) ((deg)*DEG_TO_RAD)
-#define degrees(rad) ((rad)*RAD_TO_DEG)
-#define sq(x) ((x)*(x))
-
-#define interrupts() sei()
-#define noInterrupts() cli()
-
-#define clockCyclesPerMicrosecond() ( F_CPU / 1000000L )
-#define clockCyclesToMicroseconds(a) ( (a) / clockCyclesPerMicrosecond() )
-#define microsecondsToClockCycles(a) ( (a) * clockCyclesPerMicrosecond() )
-
-#define lowByte(w) ((uint8_t) ((w) & 0xff))
-#define highByte(w) ((uint8_t) ((w) >> 8))
-
-#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
-#define bitSet(value, bit) ((value) |= (1UL << (bit)))
-#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
-#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit))
-
-
-typedef unsigned int word;
-
-#define bit(b) (1UL << (b))
-
-typedef uint8_t boolean;
-typedef uint8_t byte;
-
-void init(void);
-
-void pinMode(uint8_t, uint8_t);
-void digitalWrite(uint8_t, uint8_t);
-int digitalRead(uint8_t);
-int analogRead(uint8_t);
-void analogReference(uint8_t mode);
-void analogWrite(uint8_t, int);
-
-unsigned long millis(void);
-unsigned long micros(void);
-void delay(unsigned long);
-void delayMicroseconds(unsigned int us);
-unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout);
-
-void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val);
-uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder);
-
-void attachInterrupt(uint8_t, void (*)(void), int mode);
-void detachInterrupt(uint8_t);
-
-void setup(void);
-void loop(void);
-
-// Get the bit location within the hardware port of the given virtual pin.
-// This comes from the pins_*.c file for the active board configuration.
-
-#define analogInPinToBit(P) (P)
-
-// On the ATmega1280, the addresses of some of the port registers are
-// greater than 255, so we can't store them in uint8_t's.
-extern const uint16_t PROGMEM port_to_mode_PGM[];
-extern const uint16_t PROGMEM port_to_input_PGM[];
-extern const uint16_t PROGMEM port_to_output_PGM[];
-
-extern const uint8_t PROGMEM digital_pin_to_port_PGM[];
-// extern const uint8_t PROGMEM digital_pin_to_bit_PGM[];
-extern const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[];
-extern const uint8_t PROGMEM digital_pin_to_timer_PGM[];
-
-// Get the bit location within the hardware port of the given virtual pin.
-// This comes from the pins_*.c file for the active board configuration.
-// 
-// These perform slightly better as macros compared to inline functions
-//
-#define digitalPinToPort(P) ( pgm_read_byte( digital_pin_to_port_PGM + (P) ) )
-#define digitalPinToBitMask(P) ( pgm_read_byte( digital_pin_to_bit_mask_PGM + (P) ) )
-#define digitalPinToTimer(P) ( pgm_read_byte( digital_pin_to_timer_PGM + (P) ) )
-#define analogInPinToBit(P) (P)
-#define portOutputRegister(P) ( (volatile uint8_t *)( pgm_read_word( port_to_output_PGM + (P))) )
-#define portInputRegister(P) ( (volatile uint8_t *)( pgm_read_word( port_to_input_PGM + (P))) )
-#define portModeRegister(P) ( (volatile uint8_t *)( pgm_read_word( port_to_mode_PGM + (P))) )
-
-#define NOT_A_PIN 0
-#define NOT_A_PORT 0
-
-#ifdef ARDUINO_MAIN
-#define PA 1
-#define PB 2
-#define PC 3
-#define PD 4
-#define PE 5
-#define PF 6
-#define PG 7
-#define PH 8
-#define PJ 10
-#define PK 11
-#define PL 12
-#endif
-
-#define NOT_ON_TIMER 0
-#define TIMER0A 1
-#define TIMER0B 2
-#define TIMER1A 3
-#define TIMER1B 4
-#define TIMER2  5
-#define TIMER2A 6
-#define TIMER2B 7
-
-#define TIMER3A 8
-#define TIMER3B 9
-#define TIMER3C 10
-#define TIMER4A 11
-#define TIMER4B 12
-#define TIMER4C 13
-#define TIMER4D 14	
-#define TIMER5A 15
-#define TIMER5B 16
-#define TIMER5C 17
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#ifdef __cplusplus
-#include "WCharacter.h"
-#include "WString.h"
-#include "HardwareSerial.h"
-
-uint16_t makeWord(uint16_t w);
-uint16_t makeWord(byte h, byte l);
-
-#define word(...) makeWord(__VA_ARGS__)
-
-unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout = 1000000L);
-
-void tone(uint8_t _pin, unsigned int frequency, unsigned long duration = 0);
-void noTone(uint8_t _pin);
-
-// WMath prototypes
-long random(long);
-long random(long, long);
-void randomSeed(unsigned int);
-long map(long, long, long, long, long);
-
-#endif
-
-#include "pins_arduino.h"
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/CDC.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/CDC.cpp
deleted file mode 100644
index 1ee3a488a5..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/CDC.cpp
+++ /dev/null
@@ -1,233 +0,0 @@
-
-
-/* Copyright (c) 2011, Peter Barrett  
-**  
-** Permission to use, copy, modify, and/or distribute this software for  
-** any purpose with or without fee is hereby granted, provided that the  
-** above copyright notice and this permission notice appear in all copies.  
-** 
-** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL  
-** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED  
-** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR  
-** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES  
-** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,  
-** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  
-** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS  
-** SOFTWARE.  
-*/
-
-#include "Platform.h"
-#include "USBAPI.h"
-#include <avr/wdt.h>
-
-#if defined(USBCON)
-#ifdef CDC_ENABLED
-
-#if (RAMEND < 1000)
-#define SERIAL_BUFFER_SIZE 16
-#else
-#define SERIAL_BUFFER_SIZE 64
-#endif
-
-struct ring_buffer
-{
-	unsigned char buffer[SERIAL_BUFFER_SIZE];
-	volatile int head;
-	volatile int tail;
-};
-
-ring_buffer cdc_rx_buffer = { { 0 }, 0, 0};
-
-typedef struct
-{
-	u32	dwDTERate;
-	u8	bCharFormat;
-	u8 	bParityType;
-	u8 	bDataBits;
-	u8	lineState;
-} LineInfo;
-
-static volatile LineInfo _usbLineInfo = { 57600, 0x00, 0x00, 0x00, 0x00 };
-
-#define WEAK __attribute__ ((weak))
-
-extern const CDCDescriptor _cdcInterface PROGMEM;
-const CDCDescriptor _cdcInterface =
-{
-	D_IAD(0,2,CDC_COMMUNICATION_INTERFACE_CLASS,CDC_ABSTRACT_CONTROL_MODEL,1),
-
-	//	CDC communication interface
-	D_INTERFACE(CDC_ACM_INTERFACE,1,CDC_COMMUNICATION_INTERFACE_CLASS,CDC_ABSTRACT_CONTROL_MODEL,0),
-	D_CDCCS(CDC_HEADER,0x10,0x01),								// Header (1.10 bcd)
-	D_CDCCS(CDC_CALL_MANAGEMENT,1,1),							// Device handles call management (not)
-	D_CDCCS4(CDC_ABSTRACT_CONTROL_MANAGEMENT,6),				// SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported
-	D_CDCCS(CDC_UNION,CDC_ACM_INTERFACE,CDC_DATA_INTERFACE),	// Communication interface is master, data interface is slave 0
-	D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_ACM),USB_ENDPOINT_TYPE_INTERRUPT,0x10,0x40),
-
-	//	CDC data interface
-	D_INTERFACE(CDC_DATA_INTERFACE,2,CDC_DATA_INTERFACE_CLASS,0,0),
-	D_ENDPOINT(USB_ENDPOINT_OUT(CDC_ENDPOINT_OUT),USB_ENDPOINT_TYPE_BULK,0x40,0),
-	D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_IN ),USB_ENDPOINT_TYPE_BULK,0x40,0)
-};
-
-int WEAK CDC_GetInterface(u8* interfaceNum)
-{
-	interfaceNum[0] += 2;	// uses 2
-	return USB_SendControl(TRANSFER_PGM,&_cdcInterface,sizeof(_cdcInterface));
-}
-
-bool WEAK CDC_Setup(Setup& setup)
-{
-	u8 r = setup.bRequest;
-	u8 requestType = setup.bmRequestType;
-
-	if (REQUEST_DEVICETOHOST_CLASS_INTERFACE == requestType)
-	{
-		if (CDC_GET_LINE_CODING == r)
-		{
-			USB_SendControl(0,(void*)&_usbLineInfo,7);
-			return true;
-		}
-	}
-
-	if (REQUEST_HOSTTODEVICE_CLASS_INTERFACE == requestType)
-	{
-		if (CDC_SET_LINE_CODING == r)
-		{
-			USB_RecvControl((void*)&_usbLineInfo,7);
-			return true;
-		}
-
-		if (CDC_SET_CONTROL_LINE_STATE == r)
-		{
-			_usbLineInfo.lineState = setup.wValueL;
-
-			// auto-reset into the bootloader is triggered when the port, already 
-			// open at 1200 bps, is closed.  this is the signal to start the watchdog
-			// with a relatively long period so it can finish housekeeping tasks
-			// like servicing endpoints before the sketch ends
-			if (1200 == _usbLineInfo.dwDTERate) {
-				// We check DTR state to determine if host port is open (bit 0 of lineState).
-				if ((_usbLineInfo.lineState & 0x01) == 0) {
-					*(uint16_t *)0x0800 = 0x7777;
-					wdt_enable(WDTO_120MS);
-				} else {
-					// Most OSs do some intermediate steps when configuring ports and DTR can
-					// twiggle more than once before stabilizing.
-					// To avoid spurious resets we set the watchdog to 250ms and eventually
-					// cancel if DTR goes back high.
-	
-					wdt_disable();
-					wdt_reset();
-					*(uint16_t *)0x0800 = 0x0;
-				}
-			}
-			return true;
-		}
-	}
-	return false;
-}
-
-
-int _serialPeek = -1;
-void Serial_::begin(uint16_t baud_count)
-{
-}
-
-void Serial_::end(void)
-{
-}
-
-void Serial_::accept(void) 
-{
-	ring_buffer *buffer = &cdc_rx_buffer;
-	int c = USB_Recv(CDC_RX); 
-	int i = (unsigned int)(buffer->head+1) % SERIAL_BUFFER_SIZE;
-	
-	// if we should be storing the received character into the location
-	// just before the tail (meaning that the head would advance to the
-	// current location of the tail), we're about to overflow the buffer
-	// and so we don't write the character or advance the head.
-	if (i != buffer->tail) {
-		buffer->buffer[buffer->head] = c;
-		buffer->head = i;
-	}
-}
-
-int Serial_::available(void)
-{
-	ring_buffer *buffer = &cdc_rx_buffer;
-	return (unsigned int)(SERIAL_BUFFER_SIZE + buffer->head - buffer->tail) % SERIAL_BUFFER_SIZE;
-}
-
-int Serial_::peek(void)
-{
-	ring_buffer *buffer = &cdc_rx_buffer;
-	if (buffer->head == buffer->tail) {
-		return -1;
-	} else {
-		return buffer->buffer[buffer->tail];
-	}
-}
-
-int Serial_::read(void)
-{
-	ring_buffer *buffer = &cdc_rx_buffer;
-	// if the head isn't ahead of the tail, we don't have any characters
-	if (buffer->head == buffer->tail) {
-		return -1;
-	} else {
-		unsigned char c = buffer->buffer[buffer->tail];
-		buffer->tail = (unsigned int)(buffer->tail + 1) % SERIAL_BUFFER_SIZE;
-		return c;
-	}	
-}
-
-void Serial_::flush(void)
-{
-	USB_Flush(CDC_TX);
-}
-
-size_t Serial_::write(uint8_t c)
-{
-	/* only try to send bytes if the high-level CDC connection itself 
-	 is open (not just the pipe) - the OS should set lineState when the port
-	 is opened and clear lineState when the port is closed.
-	 bytes sent before the user opens the connection or after
-	 the connection is closed are lost - just like with a UART. */
-	
-	// TODO - ZE - check behavior on different OSes and test what happens if an
-	// open connection isn't broken cleanly (cable is yanked out, host dies
-	// or locks up, or host virtual serial port hangs)
-	if (_usbLineInfo.lineState > 0)	{
-		int r = USB_Send(CDC_TX,&c,1);
-		if (r > 0) {
-			return r;
-		} else {
-			setWriteError();
-			return 0;
-		}
-	}
-	setWriteError();
-	return 0;
-}
-
-// This operator is a convenient way for a sketch to check whether the
-// port has actually been configured and opened by the host (as opposed
-// to just being connected to the host).  It can be used, for example, in 
-// setup() before printing to ensure that an application on the host is
-// actually ready to receive and display the data.
-// We add a short delay before returning to fix a bug observed by Federico
-// where the port is configured (lineState != 0) but not quite opened.
-Serial_::operator bool() {
-	bool result = false;
-	if (_usbLineInfo.lineState > 0) 
-		result = true;
-	delay(10);
-	return result;
-}
-
-Serial_ Serial;
-
-#endif
-#endif /* if defined(USBCON) */
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Client.h b/lib/usbhost/arduino-1.0.1/cores/arduino/Client.h
deleted file mode 100644
index ea134838a2..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Client.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef client_h
-#define client_h
-#include "Print.h"
-#include "Stream.h"
-#include "IPAddress.h"
-
-class Client : public Stream {
-
-public:
-  virtual int connect(IPAddress ip, uint16_t port) =0;
-  virtual int connect(const char *host, uint16_t port) =0;
-  virtual size_t write(uint8_t) =0;
-  virtual size_t write(const uint8_t *buf, size_t size) =0;
-  virtual int available() = 0;
-  virtual int read() = 0;
-  virtual int read(uint8_t *buf, size_t size) = 0;
-  virtual int peek() = 0;
-  virtual void flush() = 0;
-  virtual void stop() = 0;
-  virtual uint8_t connected() = 0;
-  virtual operator bool() = 0;
-protected:
-  uint8_t* rawIPAddress(IPAddress& addr) { return addr.raw_address(); };
-};
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/HID.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/HID.cpp
deleted file mode 100644
index ac63608449..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/HID.cpp
+++ /dev/null
@@ -1,520 +0,0 @@
-
-
-/* Copyright (c) 2011, Peter Barrett  
-**  
-** Permission to use, copy, modify, and/or distribute this software for  
-** any purpose with or without fee is hereby granted, provided that the  
-** above copyright notice and this permission notice appear in all copies.  
-** 
-** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL  
-** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED  
-** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR  
-** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES  
-** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,  
-** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  
-** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS  
-** SOFTWARE.  
-*/
-
-#include "Platform.h"
-#include "USBAPI.h"
-#include "USBDesc.h"
-
-#if defined(USBCON)
-#ifdef HID_ENABLED
-
-//#define RAWHID_ENABLED
-
-//	Singletons for mouse and keyboard
-
-Mouse_ Mouse;
-Keyboard_ Keyboard;
-
-//================================================================================
-//================================================================================
-
-//	HID report descriptor
-
-#define LSB(_x) ((_x) & 0xFF)
-#define MSB(_x) ((_x) >> 8)
-
-#define RAWHID_USAGE_PAGE	0xFFC0
-#define RAWHID_USAGE		0x0C00
-#define RAWHID_TX_SIZE 64
-#define RAWHID_RX_SIZE 64
-
-extern const u8 _hidReportDescriptor[] PROGMEM;
-const u8 _hidReportDescriptor[] = {
-	
-	//	Mouse
-    0x05, 0x01,                    // USAGE_PAGE (Generic Desktop)	// 54
-    0x09, 0x02,                    // USAGE (Mouse)
-    0xa1, 0x01,                    // COLLECTION (Application)
-    0x09, 0x01,                    //   USAGE (Pointer)
-    0xa1, 0x00,                    //   COLLECTION (Physical)
-    0x85, 0x01,                    //     REPORT_ID (1)
-    0x05, 0x09,                    //     USAGE_PAGE (Button)
-    0x19, 0x01,                    //     USAGE_MINIMUM (Button 1)
-    0x29, 0x03,                    //     USAGE_MAXIMUM (Button 3)
-    0x15, 0x00,                    //     LOGICAL_MINIMUM (0)
-    0x25, 0x01,                    //     LOGICAL_MAXIMUM (1)
-    0x95, 0x03,                    //     REPORT_COUNT (3)
-    0x75, 0x01,                    //     REPORT_SIZE (1)
-    0x81, 0x02,                    //     INPUT (Data,Var,Abs)
-    0x95, 0x01,                    //     REPORT_COUNT (1)
-    0x75, 0x05,                    //     REPORT_SIZE (5)
-    0x81, 0x03,                    //     INPUT (Cnst,Var,Abs)
-    0x05, 0x01,                    //     USAGE_PAGE (Generic Desktop)
-    0x09, 0x30,                    //     USAGE (X)
-    0x09, 0x31,                    //     USAGE (Y)
-    0x09, 0x38,                    //     USAGE (Wheel)
-    0x15, 0x81,                    //     LOGICAL_MINIMUM (-127)
-    0x25, 0x7f,                    //     LOGICAL_MAXIMUM (127)
-    0x75, 0x08,                    //     REPORT_SIZE (8)
-    0x95, 0x03,                    //     REPORT_COUNT (3)
-    0x81, 0x06,                    //     INPUT (Data,Var,Rel)
-    0xc0,                          //   END_COLLECTION
-    0xc0,                          // END_COLLECTION
-
-	//	Keyboard
-    0x05, 0x01,                    // USAGE_PAGE (Generic Desktop)	// 47
-    0x09, 0x06,                    // USAGE (Keyboard)
-    0xa1, 0x01,                    // COLLECTION (Application)
-    0x85, 0x02,                    //   REPORT_ID (2)
-    0x05, 0x07,                    //   USAGE_PAGE (Keyboard)
-   
-	0x19, 0xe0,                    //   USAGE_MINIMUM (Keyboard LeftControl)
-    0x29, 0xe7,                    //   USAGE_MAXIMUM (Keyboard Right GUI)
-    0x15, 0x00,                    //   LOGICAL_MINIMUM (0)
-    0x25, 0x01,                    //   LOGICAL_MAXIMUM (1)
-    0x75, 0x01,                    //   REPORT_SIZE (1)
-    
-	0x95, 0x08,                    //   REPORT_COUNT (8)
-    0x81, 0x02,                    //   INPUT (Data,Var,Abs)
-    0x95, 0x01,                    //   REPORT_COUNT (1)
-    0x75, 0x08,                    //   REPORT_SIZE (8)
-    0x81, 0x03,                    //   INPUT (Cnst,Var,Abs)
-    
-	0x95, 0x06,                    //   REPORT_COUNT (6)
-    0x75, 0x08,                    //   REPORT_SIZE (8)
-    0x15, 0x00,                    //   LOGICAL_MINIMUM (0)
-    0x25, 0x65,                    //   LOGICAL_MAXIMUM (101)
-    0x05, 0x07,                    //   USAGE_PAGE (Keyboard)
-    
-	0x19, 0x00,                    //   USAGE_MINIMUM (Reserved (no event indicated))
-    0x29, 0x65,                    //   USAGE_MAXIMUM (Keyboard Application)
-    0x81, 0x00,                    //   INPUT (Data,Ary,Abs)
-    0xc0,                          // END_COLLECTION
-
-#if RAWHID_ENABLED
-	//	RAW HID
-	0x06, LSB(RAWHID_USAGE_PAGE), MSB(RAWHID_USAGE_PAGE),	// 30
-	0x0A, LSB(RAWHID_USAGE), MSB(RAWHID_USAGE),
-
-	0xA1, 0x01,				// Collection 0x01
-    0x85, 0x03,             // REPORT_ID (3)
-	0x75, 0x08,				// report size = 8 bits
-	0x15, 0x00,				// logical minimum = 0
-	0x26, 0xFF, 0x00,		// logical maximum = 255
-
-	0x95, 64,				// report count TX
-	0x09, 0x01,				// usage
-	0x81, 0x02,				// Input (array)
-
-	0x95, 64,				// report count RX
-	0x09, 0x02,				// usage
-	0x91, 0x02,				// Output (array)
-	0xC0					// end collection
-#endif
-};
-
-extern const HIDDescriptor _hidInterface PROGMEM;
-const HIDDescriptor _hidInterface =
-{
-	D_INTERFACE(HID_INTERFACE,1,3,0,0),
-	D_HIDREPORT(sizeof(_hidReportDescriptor)),
-	D_ENDPOINT(USB_ENDPOINT_IN (HID_ENDPOINT_INT),USB_ENDPOINT_TYPE_INTERRUPT,0x40,0x01)
-};
-
-//================================================================================
-//================================================================================
-//	Driver
-
-u8 _hid_protocol = 1;
-u8 _hid_idle = 1;
-
-#define WEAK __attribute__ ((weak))
-
-int WEAK HID_GetInterface(u8* interfaceNum)
-{
-	interfaceNum[0] += 1;	// uses 1
-	return USB_SendControl(TRANSFER_PGM,&_hidInterface,sizeof(_hidInterface));
-}
-
-int WEAK HID_GetDescriptor(int i)
-{
-	return USB_SendControl(TRANSFER_PGM,_hidReportDescriptor,sizeof(_hidReportDescriptor));
-}
-
-void WEAK HID_SendReport(u8 id, const void* data, int len)
-{
-	USB_Send(HID_TX, &id, 1);
-	USB_Send(HID_TX | TRANSFER_RELEASE,data,len);
-}
-
-bool WEAK HID_Setup(Setup& setup)
-{
-	u8 r = setup.bRequest;
-	u8 requestType = setup.bmRequestType;
-	if (REQUEST_DEVICETOHOST_CLASS_INTERFACE == requestType)
-	{
-		if (HID_GET_REPORT == r)
-		{
-			//HID_GetReport();
-			return true;
-		}
-		if (HID_GET_PROTOCOL == r)
-		{
-			//Send8(_hid_protocol);	// TODO
-			return true;
-		}
-	}
-	
-	if (REQUEST_HOSTTODEVICE_CLASS_INTERFACE == requestType)
-	{
-		if (HID_SET_PROTOCOL == r)
-		{
-			_hid_protocol = setup.wValueL;
-			return true;
-		}
-
-		if (HID_SET_IDLE == r)
-		{
-			_hid_idle = setup.wValueL;
-			return true;
-		}
-	}
-	return false;
-}
-
-//================================================================================
-//================================================================================
-//	Mouse
-
-Mouse_::Mouse_(void) : _buttons(0)
-{
-}
-
-void Mouse_::begin(void) 
-{
-}
-
-void Mouse_::end(void) 
-{
-}
-
-void Mouse_::click(uint8_t b)
-{
-	_buttons = b;
-	move(0,0,0);
-	_buttons = 0;
-	move(0,0,0);
-}
-
-void Mouse_::move(signed char x, signed char y, signed char wheel)
-{
-	u8 m[4];
-	m[0] = _buttons;
-	m[1] = x;
-	m[2] = y;
-	m[3] = wheel;
-	HID_SendReport(1,m,4);
-}
-
-void Mouse_::buttons(uint8_t b)
-{
-	if (b != _buttons)
-	{
-		_buttons = b;
-		move(0,0,0);
-	}
-}
-
-void Mouse_::press(uint8_t b) 
-{
-	buttons(_buttons | b);
-}
-
-void Mouse_::release(uint8_t b)
-{
-	buttons(_buttons & ~b);
-}
-
-bool Mouse_::isPressed(uint8_t b)
-{
-	if ((b & _buttons) > 0) 
-		return true;
-	return false;
-}
-
-//================================================================================
-//================================================================================
-//	Keyboard
-
-Keyboard_::Keyboard_(void) 
-{
-}
-
-void Keyboard_::begin(void) 
-{
-}
-
-void Keyboard_::end(void) 
-{
-}
-
-void Keyboard_::sendReport(KeyReport* keys)
-{
-	HID_SendReport(2,keys,sizeof(KeyReport));
-}
-
-extern
-const uint8_t _asciimap[128] PROGMEM;
-
-#define SHIFT 0x80
-const uint8_t _asciimap[128] =
-{
-	0x00,             // NUL
-	0x00,             // SOH
-	0x00,             // STX
-	0x00,             // ETX
-	0x00,             // EOT
-	0x00,             // ENQ
-	0x00,             // ACK  
-	0x00,             // BEL
-	0x2a,			// BS	Backspace
-	0x2b,			// TAB	Tab
-	0x28,			// LF	Enter
-	0x00,             // VT 
-	0x00,             // FF 
-	0x00,             // CR 
-	0x00,             // SO 
-	0x00,             // SI 
-	0x00,             // DEL
-	0x00,             // DC1
-	0x00,             // DC2
-	0x00,             // DC3
-	0x00,             // DC4
-	0x00,             // NAK
-	0x00,             // SYN
-	0x00,             // ETB
-	0x00,             // CAN
-	0x00,             // EM 
-	0x00,             // SUB
-	0x00,             // ESC
-	0x00,             // FS 
-	0x00,             // GS 
-	0x00,             // RS 
-	0x00,             // US 
-
-	0x2c,		   //  ' '
-	0x1e|SHIFT,	   // !
-	0x34|SHIFT,	   // "
-	0x20|SHIFT,    // #
-	0x21|SHIFT,    // $
-	0x22|SHIFT,    // %
-	0x24|SHIFT,    // &
-	0x34,          // '
-	0x26|SHIFT,    // (
-	0x27|SHIFT,    // )
-	0x25|SHIFT,    // *
-	0x2e|SHIFT,    // +
-	0x36,          // ,
-	0x2d,          // -
-	0x37,          // .
-	0x38,          // /
-	0x27,          // 0
-	0x1e,          // 1
-	0x1f,          // 2
-	0x20,          // 3
-	0x21,          // 4
-	0x22,          // 5
-	0x23,          // 6
-	0x24,          // 7
-	0x25,          // 8
-	0x26,          // 9
-	0x33|SHIFT,      // :
-	0x33,          // ;
-	0x36|SHIFT,      // <
-	0x2e,          // =
-	0x37|SHIFT,      // >
-	0x38|SHIFT,      // ?
-	0x1f|SHIFT,      // @
-	0x04|SHIFT,      // A
-	0x05|SHIFT,      // B
-	0x06|SHIFT,      // C
-	0x07|SHIFT,      // D
-	0x08|SHIFT,      // E
-	0x09|SHIFT,      // F
-	0x0a|SHIFT,      // G
-	0x0b|SHIFT,      // H
-	0x0c|SHIFT,      // I
-	0x0d|SHIFT,      // J
-	0x0e|SHIFT,      // K
-	0x0f|SHIFT,      // L
-	0x10|SHIFT,      // M
-	0x11|SHIFT,      // N
-	0x12|SHIFT,      // O
-	0x13|SHIFT,      // P
-	0x14|SHIFT,      // Q
-	0x15|SHIFT,      // R
-	0x16|SHIFT,      // S
-	0x17|SHIFT,      // T
-	0x18|SHIFT,      // U
-	0x19|SHIFT,      // V
-	0x1a|SHIFT,      // W
-	0x1b|SHIFT,      // X
-	0x1c|SHIFT,      // Y
-	0x1d|SHIFT,      // Z
-	0x2f,          // [
-	0x31,          // bslash
-	0x30,          // ]
-	0x23|SHIFT,    // ^
-	0x2d|SHIFT,    // _
-	0x35,          // `
-	0x04,          // a
-	0x05,          // b
-	0x06,          // c
-	0x07,          // d
-	0x08,          // e
-	0x09,          // f
-	0x0a,          // g
-	0x0b,          // h
-	0x0c,          // i
-	0x0d,          // j
-	0x0e,          // k
-	0x0f,          // l
-	0x10,          // m
-	0x11,          // n
-	0x12,          // o
-	0x13,          // p
-	0x14,          // q
-	0x15,          // r
-	0x16,          // s
-	0x17,          // t
-	0x18,          // u
-	0x19,          // v
-	0x1a,          // w
-	0x1b,          // x
-	0x1c,          // y
-	0x1d,          // z
-	0x2f|SHIFT,    // 
-	0x31|SHIFT,    // |
-	0x30|SHIFT,    // }
-	0x35|SHIFT,    // ~
-	0				// DEL
-};
-
-uint8_t USBPutChar(uint8_t c);
-
-// press() adds the specified key (printing, non-printing, or modifier)
-// to the persistent key report and sends the report.  Because of the way 
-// USB HID works, the host acts like the key remains pressed until we 
-// call release(), releaseAll(), or otherwise clear the report and resend.
-size_t Keyboard_::press(uint8_t k) 
-{
-	uint8_t i;
-	if (k >= 136) {			// it's a non-printing key (not a modifier)
-		k = k - 136;
-	} else if (k >= 128) {	// it's a modifier key
-		_keyReport.modifiers |= (1<<(k-128));
-		k = 0;
-	} else {				// it's a printing key
-		k = pgm_read_byte(_asciimap + k);
-		if (!k) {
-			setWriteError();
-			return 0;
-		}
-		if (k & 0x80) {						// it's a capital letter or other character reached with shift
-			_keyReport.modifiers |= 0x02;	// the left shift modifier
-			k &= 0x7F;
-		}
-	}
-	
-	// Add k to the key report only if it's not already present
-	// and if there is an empty slot.
-	if (_keyReport.keys[0] != k && _keyReport.keys[1] != k && 
-		_keyReport.keys[2] != k && _keyReport.keys[3] != k &&
-		_keyReport.keys[4] != k && _keyReport.keys[5] != k) {
-		
-		for (i=0; i<6; i++) {
-			if (_keyReport.keys[i] == 0x00) {
-				_keyReport.keys[i] = k;
-				break;
-			}
-		}
-		if (i == 6) {
-			setWriteError();
-			return 0;
-		}	
-	}
-	sendReport(&_keyReport);
-	return 1;
-}
-
-// release() takes the specified key out of the persistent key report and
-// sends the report.  This tells the OS the key is no longer pressed and that
-// it shouldn't be repeated any more.
-size_t Keyboard_::release(uint8_t k) 
-{
-	uint8_t i;
-	if (k >= 136) {			// it's a non-printing key (not a modifier)
-		k = k - 136;
-	} else if (k >= 128) {	// it's a modifier key
-		_keyReport.modifiers &= ~(1<<(k-128));
-		k = 0;
-	} else {				// it's a printing key
-		k = pgm_read_byte(_asciimap + k);
-		if (!k) {
-			return 0;
-		}
-		if (k & 0x80) {							// it's a capital letter or other character reached with shift
-			_keyReport.modifiers &= ~(0x02);	// the left shift modifier
-			k &= 0x7F;
-		}
-	}
-	
-	// Test the key report to see if k is present.  Clear it if it exists.
-	// Check all positions in case the key is present more than once (which it shouldn't be)
-	for (i=0; i<6; i++) {
-		if (0 != k && _keyReport.keys[i] == k) {
-			_keyReport.keys[i] = 0x00;
-		}
-	}
-
-	sendReport(&_keyReport);
-	return 1;
-}
-
-void Keyboard_::releaseAll(void)
-{
-	_keyReport.keys[0] = 0;
-	_keyReport.keys[1] = 0;	
-	_keyReport.keys[2] = 0;
-	_keyReport.keys[3] = 0;	
-	_keyReport.keys[4] = 0;
-	_keyReport.keys[5] = 0;	
-	_keyReport.modifiers = 0;
-	sendReport(&_keyReport);
-}
-
-size_t Keyboard_::write(uint8_t c)
-{	
-	uint8_t p = press(c);		// Keydown
-	uint8_t r = release(c);		// Keyup
-	return (p);					// just return the result of press() since release() almost always returns 1
-}
-
-#endif
-
-#endif /* if defined(USBCON) */
\ No newline at end of file
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/HardwareSerial.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/HardwareSerial.cpp
deleted file mode 100644
index f40ddee060..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/HardwareSerial.cpp
+++ /dev/null
@@ -1,428 +0,0 @@
-/*
-  HardwareSerial.cpp - Hardware serial library for Wiring
-  Copyright (c) 2006 Nicholas Zambetti.  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-  
-  Modified 23 November 2006 by David A. Mellis
-  Modified 28 September 2010 by Mark Sproul
-*/
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <inttypes.h>
-#include "Arduino.h"
-#include "wiring_private.h"
-
-// this next line disables the entire HardwareSerial.cpp, 
-// this is so I can support Attiny series and any other chip without a uart
-#if defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H) || defined(UBRR2H) || defined(UBRR3H)
-
-#include "HardwareSerial.h"
-
-// Define constants and variables for buffering incoming serial data.  We're
-// using a ring buffer (I think), in which head is the index of the location
-// to which to write the next incoming character and tail is the index of the
-// location from which to read.
-#if (RAMEND < 1000)
-  #define SERIAL_BUFFER_SIZE 16
-#else
-  #define SERIAL_BUFFER_SIZE 64
-#endif
-
-struct ring_buffer
-{
-  unsigned char buffer[SERIAL_BUFFER_SIZE];
-  volatile unsigned int head;
-  volatile unsigned int tail;
-};
-
-#if defined(USBCON)
-  ring_buffer rx_buffer = { { 0 }, 0, 0};
-  ring_buffer tx_buffer = { { 0 }, 0, 0};
-#endif
-#if defined(UBRRH) || defined(UBRR0H)
-  ring_buffer rx_buffer  =  { { 0 }, 0, 0 };
-  ring_buffer tx_buffer  =  { { 0 }, 0, 0 };
-#endif
-#if defined(UBRR1H)
-  ring_buffer rx_buffer1  =  { { 0 }, 0, 0 };
-  ring_buffer tx_buffer1  =  { { 0 }, 0, 0 };
-#endif
-#if defined(UBRR2H)
-  ring_buffer rx_buffer2  =  { { 0 }, 0, 0 };
-  ring_buffer tx_buffer2  =  { { 0 }, 0, 0 };
-#endif
-#if defined(UBRR3H)
-  ring_buffer rx_buffer3  =  { { 0 }, 0, 0 };
-  ring_buffer tx_buffer3  =  { { 0 }, 0, 0 };
-#endif
-
-inline void store_char(unsigned char c, ring_buffer *buffer)
-{
-  int i = (unsigned int)(buffer->head + 1) % SERIAL_BUFFER_SIZE;
-
-  // if we should be storing the received character into the location
-  // just before the tail (meaning that the head would advance to the
-  // current location of the tail), we're about to overflow the buffer
-  // and so we don't write the character or advance the head.
-  if (i != buffer->tail) {
-    buffer->buffer[buffer->head] = c;
-    buffer->head = i;
-  }
-}
-
-#if !defined(USART0_RX_vect) && defined(USART1_RX_vect)
-// do nothing - on the 32u4 the first USART is USART1
-#else
-#if !defined(USART_RX_vect) && !defined(SIG_USART0_RECV) && \
-    !defined(SIG_UART0_RECV) && !defined(USART0_RX_vect) && \
-	!defined(SIG_UART_RECV)
-  #error "Don't know what the Data Received vector is called for the first UART"
-#else
-  void serialEvent() __attribute__((weak));
-  void serialEvent() {}
-  #define serialEvent_implemented
-#if defined(USART_RX_vect)
-  SIGNAL(USART_RX_vect)
-#elif defined(SIG_USART0_RECV)
-  SIGNAL(SIG_USART0_RECV)
-#elif defined(SIG_UART0_RECV)
-  SIGNAL(SIG_UART0_RECV)
-#elif defined(USART0_RX_vect)
-  SIGNAL(USART0_RX_vect)
-#elif defined(SIG_UART_RECV)
-  SIGNAL(SIG_UART_RECV)
-#endif
-  {
-  #if defined(UDR0)
-    unsigned char c  =  UDR0;
-  #elif defined(UDR)
-    unsigned char c  =  UDR;
-  #else
-    #error UDR not defined
-  #endif
-    store_char(c, &rx_buffer);
-  }
-#endif
-#endif
-
-#if defined(USART1_RX_vect)
-  void serialEvent1() __attribute__((weak));
-  void serialEvent1() {}
-  #define serialEvent1_implemented
-  SIGNAL(USART1_RX_vect)
-  {
-    unsigned char c = UDR1;
-    store_char(c, &rx_buffer1);
-  }
-#elif defined(SIG_USART1_RECV)
-  #error SIG_USART1_RECV
-#endif
-
-#if defined(USART2_RX_vect) && defined(UDR2)
-  void serialEvent2() __attribute__((weak));
-  void serialEvent2() {}
-  #define serialEvent2_implemented
-  SIGNAL(USART2_RX_vect)
-  {
-    unsigned char c = UDR2;
-    store_char(c, &rx_buffer2);
-  }
-#elif defined(SIG_USART2_RECV)
-  #error SIG_USART2_RECV
-#endif
-
-#if defined(USART3_RX_vect) && defined(UDR3)
-  void serialEvent3() __attribute__((weak));
-  void serialEvent3() {}
-  #define serialEvent3_implemented
-  SIGNAL(USART3_RX_vect)
-  {
-    unsigned char c = UDR3;
-    store_char(c, &rx_buffer3);
-  }
-#elif defined(SIG_USART3_RECV)
-  #error SIG_USART3_RECV
-#endif
-
-void serialEventRun(void)
-{
-#ifdef serialEvent_implemented
-  if (Serial.available()) serialEvent();
-#endif
-#ifdef serialEvent1_implemented
-  if (Serial1.available()) serialEvent1();
-#endif
-#ifdef serialEvent2_implemented
-  if (Serial2.available()) serialEvent2();
-#endif
-#ifdef serialEvent3_implemented
-  if (Serial3.available()) serialEvent3();
-#endif
-}
-
-
-#if !defined(USART0_UDRE_vect) && defined(USART1_UDRE_vect)
-// do nothing - on the 32u4 the first USART is USART1
-#else
-#if !defined(UART0_UDRE_vect) && !defined(UART_UDRE_vect) && !defined(USART0_UDRE_vect) && !defined(USART_UDRE_vect)
-  #error "Don't know what the Data Register Empty vector is called for the first UART"
-#else
-#if defined(UART0_UDRE_vect)
-ISR(UART0_UDRE_vect)
-#elif defined(UART_UDRE_vect)
-ISR(UART_UDRE_vect)
-#elif defined(USART0_UDRE_vect)
-ISR(USART0_UDRE_vect)
-#elif defined(USART_UDRE_vect)
-ISR(USART_UDRE_vect)
-#endif
-{
-  if (tx_buffer.head == tx_buffer.tail) {
-	// Buffer empty, so disable interrupts
-#if defined(UCSR0B)
-    cbi(UCSR0B, UDRIE0);
-#else
-    cbi(UCSRB, UDRIE);
-#endif
-  }
-  else {
-    // There is more data in the output buffer. Send the next byte
-    unsigned char c = tx_buffer.buffer[tx_buffer.tail];
-    tx_buffer.tail = (tx_buffer.tail + 1) % SERIAL_BUFFER_SIZE;
-	
-  #if defined(UDR0)
-    UDR0 = c;
-  #elif defined(UDR)
-    UDR = c;
-  #else
-    #error UDR not defined
-  #endif
-  }
-}
-#endif
-#endif
-
-#ifdef USART1_UDRE_vect
-ISR(USART1_UDRE_vect)
-{
-  if (tx_buffer1.head == tx_buffer1.tail) {
-	// Buffer empty, so disable interrupts
-    cbi(UCSR1B, UDRIE1);
-  }
-  else {
-    // There is more data in the output buffer. Send the next byte
-    unsigned char c = tx_buffer1.buffer[tx_buffer1.tail];
-    tx_buffer1.tail = (tx_buffer1.tail + 1) % SERIAL_BUFFER_SIZE;
-	
-    UDR1 = c;
-  }
-}
-#endif
-
-#ifdef USART2_UDRE_vect
-ISR(USART2_UDRE_vect)
-{
-  if (tx_buffer2.head == tx_buffer2.tail) {
-	// Buffer empty, so disable interrupts
-    cbi(UCSR2B, UDRIE2);
-  }
-  else {
-    // There is more data in the output buffer. Send the next byte
-    unsigned char c = tx_buffer2.buffer[tx_buffer2.tail];
-    tx_buffer2.tail = (tx_buffer2.tail + 1) % SERIAL_BUFFER_SIZE;
-	
-    UDR2 = c;
-  }
-}
-#endif
-
-#ifdef USART3_UDRE_vect
-ISR(USART3_UDRE_vect)
-{
-  if (tx_buffer3.head == tx_buffer3.tail) {
-	// Buffer empty, so disable interrupts
-    cbi(UCSR3B, UDRIE3);
-  }
-  else {
-    // There is more data in the output buffer. Send the next byte
-    unsigned char c = tx_buffer3.buffer[tx_buffer3.tail];
-    tx_buffer3.tail = (tx_buffer3.tail + 1) % SERIAL_BUFFER_SIZE;
-	
-    UDR3 = c;
-  }
-}
-#endif
-
-
-// Constructors ////////////////////////////////////////////////////////////////
-
-HardwareSerial::HardwareSerial(ring_buffer *rx_buffer, ring_buffer *tx_buffer,
-  volatile uint8_t *ubrrh, volatile uint8_t *ubrrl,
-  volatile uint8_t *ucsra, volatile uint8_t *ucsrb,
-  volatile uint8_t *udr,
-  uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udrie, uint8_t u2x)
-{
-  _rx_buffer = rx_buffer;
-  _tx_buffer = tx_buffer;
-  _ubrrh = ubrrh;
-  _ubrrl = ubrrl;
-  _ucsra = ucsra;
-  _ucsrb = ucsrb;
-  _udr = udr;
-  _rxen = rxen;
-  _txen = txen;
-  _rxcie = rxcie;
-  _udrie = udrie;
-  _u2x = u2x;
-}
-
-// Public Methods //////////////////////////////////////////////////////////////
-
-void HardwareSerial::begin(unsigned long baud)
-{
-  uint16_t baud_setting;
-  bool use_u2x = true;
-
-#if F_CPU == 16000000UL
-  // hardcoded exception for compatibility with the bootloader shipped
-  // with the Duemilanove and previous boards and the firmware on the 8U2
-  // on the Uno and Mega 2560.
-  if (baud == 57600) {
-    use_u2x = false;
-  }
-#endif
-
-try_again:
-  
-  if (use_u2x) {
-    *_ucsra = 1 << _u2x;
-    baud_setting = (F_CPU / 4 / baud - 1) / 2;
-  } else {
-    *_ucsra = 0;
-    baud_setting = (F_CPU / 8 / baud - 1) / 2;
-  }
-  
-  if ((baud_setting > 4095) && use_u2x)
-  {
-    use_u2x = false;
-    goto try_again;
-  }
-
-  // assign the baud_setting, a.k.a. ubbr (USART Baud Rate Register)
-  *_ubrrh = baud_setting >> 8;
-  *_ubrrl = baud_setting;
-
-  sbi(*_ucsrb, _rxen);
-  sbi(*_ucsrb, _txen);
-  sbi(*_ucsrb, _rxcie);
-  cbi(*_ucsrb, _udrie);
-}
-
-void HardwareSerial::end()
-{
-  // wait for transmission of outgoing data
-  while (_tx_buffer->head != _tx_buffer->tail)
-    ;
-
-  cbi(*_ucsrb, _rxen);
-  cbi(*_ucsrb, _txen);
-  cbi(*_ucsrb, _rxcie);  
-  cbi(*_ucsrb, _udrie);
-  
-  // clear any received data
-  _rx_buffer->head = _rx_buffer->tail;
-}
-
-int HardwareSerial::available(void)
-{
-  return (unsigned int)(SERIAL_BUFFER_SIZE + _rx_buffer->head - _rx_buffer->tail) % SERIAL_BUFFER_SIZE;
-}
-
-int HardwareSerial::peek(void)
-{
-  if (_rx_buffer->head == _rx_buffer->tail) {
-    return -1;
-  } else {
-    return _rx_buffer->buffer[_rx_buffer->tail];
-  }
-}
-
-int HardwareSerial::read(void)
-{
-  // if the head isn't ahead of the tail, we don't have any characters
-  if (_rx_buffer->head == _rx_buffer->tail) {
-    return -1;
-  } else {
-    unsigned char c = _rx_buffer->buffer[_rx_buffer->tail];
-    _rx_buffer->tail = (unsigned int)(_rx_buffer->tail + 1) % SERIAL_BUFFER_SIZE;
-    return c;
-  }
-}
-
-void HardwareSerial::flush()
-{
-  while (_tx_buffer->head != _tx_buffer->tail)
-    ;
-}
-
-size_t HardwareSerial::write(uint8_t c)
-{
-  int i = (_tx_buffer->head + 1) % SERIAL_BUFFER_SIZE;
-	
-  // If the output buffer is full, there's nothing for it other than to 
-  // wait for the interrupt handler to empty it a bit
-  // ???: return 0 here instead?
-  while (i == _tx_buffer->tail)
-    ;
-	
-  _tx_buffer->buffer[_tx_buffer->head] = c;
-  _tx_buffer->head = i;
-	
-  sbi(*_ucsrb, _udrie);
-  
-  return 1;
-}
-
-HardwareSerial::operator bool() {
-	return true;
-}
-
-// Preinstantiate Objects //////////////////////////////////////////////////////
-
-#if defined(UBRRH) && defined(UBRRL)
-  HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRRH, &UBRRL, &UCSRA, &UCSRB, &UDR, RXEN, TXEN, RXCIE, UDRIE, U2X);
-#elif defined(UBRR0H) && defined(UBRR0L)
-  HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRR0H, &UBRR0L, &UCSR0A, &UCSR0B, &UDR0, RXEN0, TXEN0, RXCIE0, UDRIE0, U2X0);
-#elif defined(USBCON)
-  // do nothing - Serial object and buffers are initialized in CDC code
-#else
-  #error no serial port defined  (port 0)
-#endif
-
-#if defined(UBRR1H)
-  HardwareSerial Serial1(&rx_buffer1, &tx_buffer1, &UBRR1H, &UBRR1L, &UCSR1A, &UCSR1B, &UDR1, RXEN1, TXEN1, RXCIE1, UDRIE1, U2X1);
-#endif
-#if defined(UBRR2H)
-  HardwareSerial Serial2(&rx_buffer2, &tx_buffer2, &UBRR2H, &UBRR2L, &UCSR2A, &UCSR2B, &UDR2, RXEN2, TXEN2, RXCIE2, UDRIE2, U2X2);
-#endif
-#if defined(UBRR3H)
-  HardwareSerial Serial3(&rx_buffer3, &tx_buffer3, &UBRR3H, &UBRR3L, &UCSR3A, &UCSR3B, &UDR3, RXEN3, TXEN3, RXCIE3, UDRIE3, U2X3);
-#endif
-
-#endif // whole file
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/HardwareSerial.h b/lib/usbhost/arduino-1.0.1/cores/arduino/HardwareSerial.h
deleted file mode 100644
index bf4924c6d4..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/HardwareSerial.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
-  HardwareSerial.h - Hardware serial library for Wiring
-  Copyright (c) 2006 Nicholas Zambetti.  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-
-  Modified 28 September 2010 by Mark Sproul
-*/
-
-#ifndef HardwareSerial_h
-#define HardwareSerial_h
-
-#include <inttypes.h>
-
-#include "Stream.h"
-
-struct ring_buffer;
-
-class HardwareSerial : public Stream
-{
-  private:
-    ring_buffer *_rx_buffer;
-    ring_buffer *_tx_buffer;
-    volatile uint8_t *_ubrrh;
-    volatile uint8_t *_ubrrl;
-    volatile uint8_t *_ucsra;
-    volatile uint8_t *_ucsrb;
-    volatile uint8_t *_udr;
-    uint8_t _rxen;
-    uint8_t _txen;
-    uint8_t _rxcie;
-    uint8_t _udrie;
-    uint8_t _u2x;
-  public:
-    HardwareSerial(ring_buffer *rx_buffer, ring_buffer *tx_buffer,
-      volatile uint8_t *ubrrh, volatile uint8_t *ubrrl,
-      volatile uint8_t *ucsra, volatile uint8_t *ucsrb,
-      volatile uint8_t *udr,
-      uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udrie, uint8_t u2x);
-    void begin(unsigned long);
-    void end();
-    virtual int available(void);
-    virtual int peek(void);
-    virtual int read(void);
-    virtual void flush(void);
-    virtual size_t write(uint8_t);
-    using Print::write; // pull in write(str) and write(buf, size) from Print
-    operator bool();
-};
-
-#if defined(UBRRH) || defined(UBRR0H)
-  extern HardwareSerial Serial;
-#elif defined(USBCON)
-  #include "USBAPI.h"
-//  extern HardwareSerial Serial_;  
-#endif
-#if defined(UBRR1H)
-  extern HardwareSerial Serial1;
-#endif
-#if defined(UBRR2H)
-  extern HardwareSerial Serial2;
-#endif
-#if defined(UBRR3H)
-  extern HardwareSerial Serial3;
-#endif
-
-extern void serialEventRun(void) __attribute__((weak));
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/IPAddress.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/IPAddress.cpp
deleted file mode 100644
index fe3deb77a2..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/IPAddress.cpp
+++ /dev/null
@@ -1,56 +0,0 @@
-
-#include <Arduino.h>
-#include <IPAddress.h>
-
-IPAddress::IPAddress()
-{
-    memset(_address, 0, sizeof(_address));
-}
-
-IPAddress::IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet)
-{
-    _address[0] = first_octet;
-    _address[1] = second_octet;
-    _address[2] = third_octet;
-    _address[3] = fourth_octet;
-}
-
-IPAddress::IPAddress(uint32_t address)
-{
-    memcpy(_address, &address, sizeof(_address));
-}
-
-IPAddress::IPAddress(const uint8_t *address)
-{
-    memcpy(_address, address, sizeof(_address));
-}
-
-IPAddress& IPAddress::operator=(const uint8_t *address)
-{
-    memcpy(_address, address, sizeof(_address));
-    return *this;
-}
-
-IPAddress& IPAddress::operator=(uint32_t address)
-{
-    memcpy(_address, (const uint8_t *)&address, sizeof(_address));
-    return *this;
-}
-
-bool IPAddress::operator==(const uint8_t* addr)
-{
-    return memcmp(addr, _address, sizeof(_address)) == 0;
-}
-
-size_t IPAddress::printTo(Print& p) const
-{
-    size_t n = 0;
-    for (int i =0; i < 3; i++)
-    {
-        n += p.print(_address[i], DEC);
-        n += p.print('.');
-    }
-    n += p.print(_address[3], DEC);
-    return n;
-}
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/IPAddress.h b/lib/usbhost/arduino-1.0.1/cores/arduino/IPAddress.h
deleted file mode 100644
index 2585aec0e4..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/IPAddress.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- *
- * MIT License:
- * Copyright (c) 2011 Adrian McEwen
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- * 
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- * 
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * adrianm@mcqn.com 1/1/2011
- */
-
-#ifndef IPAddress_h
-#define IPAddress_h
-
-#include <Printable.h>
-
-// A class to make it easier to handle and pass around IP addresses
-
-class IPAddress : public Printable {
-private:
-    uint8_t _address[4];  // IPv4 address
-    // Access the raw byte array containing the address.  Because this returns a pointer
-    // to the internal structure rather than a copy of the address this function should only
-    // be used when you know that the usage of the returned uint8_t* will be transient and not
-    // stored.
-    uint8_t* raw_address() { return _address; };
-
-public:
-    // Constructors
-    IPAddress();
-    IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet);
-    IPAddress(uint32_t address);
-    IPAddress(const uint8_t *address);
-
-    // Overloaded cast operator to allow IPAddress objects to be used where a pointer
-    // to a four-byte uint8_t array is expected
-    operator uint32_t() { return *((uint32_t*)_address); };
-    bool operator==(const IPAddress& addr) { return (*((uint32_t*)_address)) == (*((uint32_t*)addr._address)); };
-    bool operator==(const uint8_t* addr);
-
-    // Overloaded index operator to allow getting and setting individual octets of the address
-    uint8_t operator[](int index) const { return _address[index]; };
-    uint8_t& operator[](int index) { return _address[index]; };
-
-    // Overloaded copy operators to allow initialisation of IPAddress objects from other types
-    IPAddress& operator=(const uint8_t *address);
-    IPAddress& operator=(uint32_t address);
-
-    virtual size_t printTo(Print& p) const;
-
-    friend class EthernetClass;
-    friend class UDP;
-    friend class Client;
-    friend class Server;
-    friend class DhcpClass;
-    friend class DNSClient;
-};
-
-const IPAddress INADDR_NONE(0,0,0,0);
-
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Platform.h b/lib/usbhost/arduino-1.0.1/cores/arduino/Platform.h
deleted file mode 100644
index 8b8f742771..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Platform.h
+++ /dev/null
@@ -1,23 +0,0 @@
-
-#ifndef __PLATFORM_H__
-#define __PLATFORM_H__
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-#include <avr/eeprom.h>
-#include <avr/interrupt.h>
-#include <util/delay.h>
-
-typedef unsigned char u8;
-typedef unsigned short u16;
-typedef unsigned long u32;
-
-#include "Arduino.h"
-
-#if defined(USBCON)
-	#include "USBDesc.h"
-	#include "USBCore.h"
-	#include "USBAPI.h"
-#endif /* if defined(USBCON) */
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Print.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/Print.cpp
deleted file mode 100644
index e541a6ce71..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Print.cpp
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- Print.cpp - Base class that provides print() and println()
- Copyright (c) 2008 David A. Mellis.  All right reserved.
- 
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
- 
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
- 
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- 
- Modified 23 November 2006 by David A. Mellis
- */
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <math.h>
-#include "Arduino.h"
-
-#include "Print.h"
-
-// Public Methods //////////////////////////////////////////////////////////////
-
-/* default implementation: may be overridden */
-size_t Print::write(const uint8_t *buffer, size_t size)
-{
-  size_t n = 0;
-  while (size--) {
-    n += write(*buffer++);
-  }
-  return n;
-}
-
-size_t Print::print(const __FlashStringHelper *ifsh)
-{
-  const char PROGMEM *p = (const char PROGMEM *)ifsh;
-  size_t n = 0;
-  while (1) {
-    unsigned char c = pgm_read_byte(p++);
-    if (c == 0) break;
-    n += write(c);
-  }
-  return n;
-}
-
-size_t Print::print(const String &s)
-{
-  size_t n = 0;
-  for (uint16_t i = 0; i < s.length(); i++) {
-    n += write(s[i]);
-  }
-  return n;
-}
-
-size_t Print::print(const char str[])
-{
-  return write(str);
-}
-
-size_t Print::print(char c)
-{
-  return write(c);
-}
-
-size_t Print::print(unsigned char b, int base)
-{
-  return print((unsigned long) b, base);
-}
-
-size_t Print::print(int n, int base)
-{
-  return print((long) n, base);
-}
-
-size_t Print::print(unsigned int n, int base)
-{
-  return print((unsigned long) n, base);
-}
-
-size_t Print::print(long n, int base)
-{
-  if (base == 0) {
-    return write(n);
-  } else if (base == 10) {
-    if (n < 0) {
-      int t = print('-');
-      n = -n;
-      return printNumber(n, 10) + t;
-    }
-    return printNumber(n, 10);
-  } else {
-    return printNumber(n, base);
-  }
-}
-
-size_t Print::print(unsigned long n, int base)
-{
-  if (base == 0) return write(n);
-  else return printNumber(n, base);
-}
-
-size_t Print::print(double n, int digits)
-{
-  return printFloat(n, digits);
-}
-
-size_t Print::println(const __FlashStringHelper *ifsh)
-{
-  size_t n = print(ifsh);
-  n += println();
-  return n;
-}
-
-size_t Print::print(const Printable& x)
-{
-  return x.printTo(*this);
-}
-
-size_t Print::println(void)
-{
-  size_t n = print('\r');
-  n += print('\n');
-  return n;
-}
-
-size_t Print::println(const String &s)
-{
-  size_t n = print(s);
-  n += println();
-  return n;
-}
-
-size_t Print::println(const char c[])
-{
-  size_t n = print(c);
-  n += println();
-  return n;
-}
-
-size_t Print::println(char c)
-{
-  size_t n = print(c);
-  n += println();
-  return n;
-}
-
-size_t Print::println(unsigned char b, int base)
-{
-  size_t n = print(b, base);
-  n += println();
-  return n;
-}
-
-size_t Print::println(int num, int base)
-{
-  size_t n = print(num, base);
-  n += println();
-  return n;
-}
-
-size_t Print::println(unsigned int num, int base)
-{
-  size_t n = print(num, base);
-  n += println();
-  return n;
-}
-
-size_t Print::println(long num, int base)
-{
-  size_t n = print(num, base);
-  n += println();
-  return n;
-}
-
-size_t Print::println(unsigned long num, int base)
-{
-  size_t n = print(num, base);
-  n += println();
-  return n;
-}
-
-size_t Print::println(double num, int digits)
-{
-  size_t n = print(num, digits);
-  n += println();
-  return n;
-}
-
-size_t Print::println(const Printable& x)
-{
-  size_t n = print(x);
-  n += println();
-  return n;
-}
-
-// Private Methods /////////////////////////////////////////////////////////////
-
-size_t Print::printNumber(unsigned long n, uint8_t base) {
-  char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte.
-  char *str = &buf[sizeof(buf) - 1];
-
-  *str = '\0';
-
-  // prevent crash if called with base == 1
-  if (base < 2) base = 10;
-
-  do {
-    unsigned long m = n;
-    n /= base;
-    char c = m - base * n;
-    *--str = c < 10 ? c + '0' : c + 'A' - 10;
-  } while(n);
-
-  return write(str);
-}
-
-size_t Print::printFloat(double number, uint8_t digits) 
-{ 
-  size_t n = 0;
-  
-  // Handle negative numbers
-  if (number < 0.0)
-  {
-     n += print('-');
-     number = -number;
-  }
-
-  // Round correctly so that print(1.999, 2) prints as "2.00"
-  double rounding = 0.5;
-  for (uint8_t i=0; i<digits; ++i)
-    rounding /= 10.0;
-  
-  number += rounding;
-
-  // Extract the integer part of the number and print it
-  unsigned long int_part = (unsigned long)number;
-  double remainder = number - (double)int_part;
-  n += print(int_part);
-
-  // Print the decimal point, but only if there are digits beyond
-  if (digits > 0) {
-    n += print("."); 
-  }
-
-  // Extract digits from the remainder one at a time
-  while (digits-- > 0)
-  {
-    remainder *= 10.0;
-    int toPrint = int(remainder);
-    n += print(toPrint);
-    remainder -= toPrint; 
-  } 
-  
-  return n;
-}
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Print.h b/lib/usbhost/arduino-1.0.1/cores/arduino/Print.h
deleted file mode 100644
index 1af6b723fc..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Print.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
-  Print.h - Base class that provides print() and println()
-  Copyright (c) 2008 David A. Mellis.  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-
-#ifndef Print_h
-#define Print_h
-
-#include <inttypes.h>
-#include <stdio.h> // for size_t
-
-#include "WString.h"
-#include "Printable.h"
-
-#define DEC 10
-#define HEX 16
-#define OCT 8
-#define BIN 2
-
-class Print
-{
-  private:
-    int write_error;
-    size_t printNumber(unsigned long, uint8_t);
-    size_t printFloat(double, uint8_t);
-  protected:
-    void setWriteError(int err = 1) { write_error = err; }
-  public:
-    Print() : write_error(0) {}
-  
-    int getWriteError() { return write_error; }
-    void clearWriteError() { setWriteError(0); }
-  
-    virtual size_t write(uint8_t) = 0;
-    size_t write(const char *str) { return write((const uint8_t *)str, strlen(str)); }
-    virtual size_t write(const uint8_t *buffer, size_t size);
-    
-    size_t print(const __FlashStringHelper *);
-    size_t print(const String &);
-    size_t print(const char[]);
-    size_t print(char);
-    size_t print(unsigned char, int = DEC);
-    size_t print(int, int = DEC);
-    size_t print(unsigned int, int = DEC);
-    size_t print(long, int = DEC);
-    size_t print(unsigned long, int = DEC);
-    size_t print(double, int = 2);
-    size_t print(const Printable&);
-
-    size_t println(const __FlashStringHelper *);
-    size_t println(const String &s);
-    size_t println(const char[]);
-    size_t println(char);
-    size_t println(unsigned char, int = DEC);
-    size_t println(int, int = DEC);
-    size_t println(unsigned int, int = DEC);
-    size_t println(long, int = DEC);
-    size_t println(unsigned long, int = DEC);
-    size_t println(double, int = 2);
-    size_t println(const Printable&);
-    size_t println(void);
-};
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Printable.h b/lib/usbhost/arduino-1.0.1/cores/arduino/Printable.h
deleted file mode 100644
index d03c9af62c..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Printable.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-  Printable.h - Interface class that allows printing of complex types
-  Copyright (c) 2011 Adrian McEwen.  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-
-#ifndef Printable_h
-#define Printable_h
-
-#include <new.h>
-
-class Print;
-
-/** The Printable class provides a way for new classes to allow themselves to be printed.
-    By deriving from Printable and implementing the printTo method, it will then be possible
-    for users to print out instances of this class by passing them into the usual
-    Print::print and Print::println methods.
-*/
-
-class Printable
-{
-  public:
-    virtual size_t printTo(Print& p) const = 0;
-};
-
-#endif
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Server.h b/lib/usbhost/arduino-1.0.1/cores/arduino/Server.h
deleted file mode 100644
index 9674c76269..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Server.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef server_h
-#define server_h
-
-class Server : public Print {
-public:
-  virtual void begin() =0;
-};
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Stream.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/Stream.cpp
deleted file mode 100644
index aafb7fcf97..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Stream.cpp
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- Stream.cpp - adds parsing methods to Stream class
- Copyright (c) 2008 David A. Mellis.  All right reserved.
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-
- Created July 2011
- parsing functions based on TextFinder library by Michael Margolis
- */
-
-#include "Arduino.h"
-#include "Stream.h"
-
-#define PARSE_TIMEOUT 1000  // default number of milli-seconds to wait
-#define NO_SKIP_CHAR  1  // a magic char not found in a valid ASCII numeric field
-
-// private method to read stream with timeout
-int Stream::timedRead()
-{
-  int c;
-  _startMillis = millis();
-  do {
-    c = read();
-    if (c >= 0) return c;
-  } while(millis() - _startMillis < _timeout);
-  return -1;     // -1 indicates timeout
-}
-
-// private method to peek stream with timeout
-int Stream::timedPeek()
-{
-  int c;
-  _startMillis = millis();
-  do {
-    c = peek();
-    if (c >= 0) return c;
-  } while(millis() - _startMillis < _timeout);
-  return -1;     // -1 indicates timeout
-}
-
-// returns peek of the next digit in the stream or -1 if timeout
-// discards non-numeric characters
-int Stream::peekNextDigit()
-{
-  int c;
-  while (1) {
-    c = timedPeek();
-    if (c < 0) return c;  // timeout
-    if (c == '-') return c;
-    if (c >= '0' && c <= '9') return c;
-    read();  // discard non-numeric
-  }
-}
-
-// Public Methods
-//////////////////////////////////////////////////////////////
-
-void Stream::setTimeout(unsigned long timeout)  // sets the maximum number of milliseconds to wait
-{
-  _timeout = timeout;
-}
-
- // find returns true if the target string is found
-bool  Stream::find(char *target)
-{
-  return findUntil(target, NULL);
-}
-
-// reads data from the stream until the target string of given length is found
-// returns true if target string is found, false if timed out
-bool Stream::find(char *target, size_t length)
-{
-  return findUntil(target, length, NULL, 0);
-}
-
-// as find but search ends if the terminator string is found
-bool  Stream::findUntil(char *target, char *terminator)
-{
-  return findUntil(target, strlen(target), terminator, strlen(terminator));
-}
-
-// reads data from the stream until the target string of the given length is found
-// search terminated if the terminator string is found
-// returns true if target string is found, false if terminated or timed out
-bool Stream::findUntil(char *target, size_t targetLen, char *terminator, size_t termLen)
-{
-  size_t index = 0;  // maximum target string length is 64k bytes!
-  size_t termIndex = 0;
-  int c;
-  
-  if( *target == 0)
-    return true;   // return true if target is a null string
-  while( (c = timedRead()) > 0){
-    
-    if(c != target[index])
-      index = 0; // reset index if any char does not match
-    
-    if( c == target[index]){
-      //////Serial.print("found "); Serial.write(c); Serial.print("index now"); Serial.println(index+1);
-      if(++index >= targetLen){ // return true if all chars in the target match
-        return true;
-      }
-    }
-    
-    if(termLen > 0 && c == terminator[termIndex]){
-      if(++termIndex >= termLen)
-        return false;       // return false if terminate string found before target string
-    }
-    else
-      termIndex = 0;
-  }
-  return false;
-}
-
-
-// returns the first valid (long) integer value from the current position.
-// initial characters that are not digits (or the minus sign) are skipped
-// function is terminated by the first character that is not a digit.
-long Stream::parseInt()
-{
-  return parseInt(NO_SKIP_CHAR); // terminate on first non-digit character (or timeout)
-}
-
-// as above but a given skipChar is ignored
-// this allows format characters (typically commas) in values to be ignored
-long Stream::parseInt(char skipChar)
-{
-  boolean isNegative = false;
-  long value = 0;
-  int c;
-
-  c = peekNextDigit();
-  // ignore non numeric leading characters
-  if(c < 0)
-    return 0; // zero returned if timeout
-
-  do{
-    if(c == skipChar)
-      ; // ignore this charactor
-    else if(c == '-')
-      isNegative = true;
-    else if(c >= '0' && c <= '9')        // is c a digit?
-      value = value * 10 + c - '0';
-    read();  // consume the character we got with peek
-    c = timedPeek();
-  }
-  while( (c >= '0' && c <= '9') || c == skipChar );
-
-  if(isNegative)
-    value = -value;
-  return value;
-}
-
-
-// as parseInt but returns a floating point value
-float Stream::parseFloat()
-{
-  return parseFloat(NO_SKIP_CHAR);
-}
-
-// as above but the given skipChar is ignored
-// this allows format characters (typically commas) in values to be ignored
-float Stream::parseFloat(char skipChar){
-  boolean isNegative = false;
-  boolean isFraction = false;
-  long value = 0;
-  char c;
-  float fraction = 1.0;
-
-  c = peekNextDigit();
-    // ignore non numeric leading characters
-  if(c < 0)
-    return 0; // zero returned if timeout
-
-  do{
-    if(c == skipChar)
-      ; // ignore
-    else if(c == '-')
-      isNegative = true;
-    else if (c == '.')
-      isFraction = true;
-    else if(c >= '0' && c <= '9')  {      // is c a digit?
-      value = value * 10 + c - '0';
-      if(isFraction)
-         fraction *= 0.1;
-    }
-    read();  // consume the character we got with peek
-    c = timedPeek();
-  }
-  while( (c >= '0' && c <= '9')  || c == '.' || c == skipChar );
-
-  if(isNegative)
-    value = -value;
-  if(isFraction)
-    return value * fraction;
-  else
-    return value;
-}
-
-// read characters from stream into buffer
-// terminates if length characters have been read, or timeout (see setTimeout)
-// returns the number of characters placed in the buffer
-// the buffer is NOT null terminated.
-//
-size_t Stream::readBytes(char *buffer, size_t length)
-{
-  size_t count = 0;
-  while (count < length) {
-    int c = timedRead();
-    if (c < 0) break;
-    *buffer++ = (char)c;
-    count++;
-  }
-  return count;
-}
-
-
-// as readBytes with terminator character
-// terminates if length characters have been read, timeout, or if the terminator character  detected
-// returns the number of characters placed in the buffer (0 means no valid data found)
-
-size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length)
-{
-  if (length < 1) return 0;
-  size_t index = 0;
-  while (index < length) {
-    int c = timedRead();
-    if (c < 0 || c == terminator) break;
-    *buffer++ = (char)c;
-    index++;
-  }
-  return index; // return number of characters, not including null terminator
-}
-
-String Stream::readString()
-{
-  String ret;
-  int c = timedRead();
-  while (c >= 0)
-  {
-    ret += (char)c;
-    c = timedRead();
-  }
-  return ret;
-}
-
-String Stream::readStringUntil(char terminator)
-{
-  String ret;
-  int c = timedRead();
-  while (c >= 0 && c != terminator)
-  {
-    ret += (char)c;
-    c = timedRead();
-  }
-  return ret;
-}
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Stream.h b/lib/usbhost/arduino-1.0.1/cores/arduino/Stream.h
deleted file mode 100644
index 58bbf752f3..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Stream.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
-  Stream.h - base class for character-based streams.
-  Copyright (c) 2010 David A. Mellis.  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-
-  parsing functions based on TextFinder library by Michael Margolis
-*/
-
-#ifndef Stream_h
-#define Stream_h
-
-#include <inttypes.h>
-#include "Print.h"
-
-// compatability macros for testing
-/*
-#define   getInt()            parseInt()
-#define   getInt(skipChar)    parseInt(skipchar)
-#define   getFloat()          parseFloat()
-#define   getFloat(skipChar)  parseFloat(skipChar)
-#define   getString( pre_string, post_string, buffer, length)
-readBytesBetween( pre_string, terminator, buffer, length)
-*/
-
-class Stream : public Print
-{
-  private:
-    unsigned long _timeout;      // number of milliseconds to wait for the next char before aborting timed read
-    unsigned long _startMillis;  // used for timeout measurement
-    int timedRead();    // private method to read stream with timeout
-    int timedPeek();    // private method to peek stream with timeout
-    int peekNextDigit(); // returns the next numeric digit in the stream or -1 if timeout
-
-  public:
-    virtual int available() = 0;
-    virtual int read() = 0;
-    virtual int peek() = 0;
-    virtual void flush() = 0;
-
-    Stream() {_timeout=1000;}
-
-// parsing methods
-
-  void setTimeout(unsigned long timeout);  // sets maximum milliseconds to wait for stream data, default is 1 second
-
-  bool find(char *target);   // reads data from the stream until the target string is found
-  // returns true if target string is found, false if timed out (see setTimeout)
-
-  bool find(char *target, size_t length);   // reads data from the stream until the target string of given length is found
-  // returns true if target string is found, false if timed out
-
-  bool findUntil(char *target, char *terminator);   // as find but search ends if the terminator string is found
-
-  bool findUntil(char *target, size_t targetLen, char *terminate, size_t termLen);   // as above but search ends if the terminate string is found
-
-
-  long parseInt(); // returns the first valid (long) integer value from the current position.
-  // initial characters that are not digits (or the minus sign) are skipped
-  // integer is terminated by the first character that is not a digit.
-
-  float parseFloat();               // float version of parseInt
-
-  size_t readBytes( char *buffer, size_t length); // read chars from stream into buffer
-  // terminates if length characters have been read or timeout (see setTimeout)
-  // returns the number of characters placed in the buffer (0 means no valid data found)
-
-  size_t readBytesUntil( char terminator, char *buffer, size_t length); // as readBytes with terminator character
-  // terminates if length characters have been read, timeout, or if the terminator character  detected
-  // returns the number of characters placed in the buffer (0 means no valid data found)
-
-  // Arduino String functions to be added here
-  String readString();
-  String readStringUntil(char terminator);
-
-  protected:
-  long parseInt(char skipChar); // as above but the given skipChar is ignored
-  // as above but the given skipChar is ignored
-  // this allows format characters (typically commas) in values to be ignored
-
-  float parseFloat(char skipChar);  // as above but the given skipChar is ignored
-};
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Tone.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/Tone.cpp
deleted file mode 100644
index 20eed3f483..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Tone.cpp
+++ /dev/null
@@ -1,601 +0,0 @@
-/* Tone.cpp
-
-  A Tone Generator Library
-
-  Written by Brett Hagman
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-
-Version Modified By Date     Comments
-------- ----------- -------- --------
-0001    B Hagman    09/08/02 Initial coding
-0002    B Hagman    09/08/18 Multiple pins
-0003    B Hagman    09/08/18 Moved initialization from constructor to begin()
-0004    B Hagman    09/09/26 Fixed problems with ATmega8
-0005    B Hagman    09/11/23 Scanned prescalars for best fit on 8 bit timers
-                    09/11/25 Changed pin toggle method to XOR
-                    09/11/25 Fixed timer0 from being excluded
-0006    D Mellis    09/12/29 Replaced objects with functions
-0007    M Sproul    10/08/29 Changed #ifdefs from cpu to register
-*************************************************/
-
-#include <avr/interrupt.h>
-#include <avr/pgmspace.h>
-#include "Arduino.h"
-#include "pins_arduino.h"
-
-#if defined(__AVR_ATmega8__) || defined(__AVR_ATmega128__)
-#define TCCR2A TCCR2
-#define TCCR2B TCCR2
-#define COM2A1 COM21
-#define COM2A0 COM20
-#define OCR2A OCR2
-#define TIMSK2 TIMSK
-#define OCIE2A OCIE2
-#define TIMER2_COMPA_vect TIMER2_COMP_vect
-#define TIMSK1 TIMSK
-#endif
-
-// timerx_toggle_count:
-//  > 0 - duration specified
-//  = 0 - stopped
-//  < 0 - infinitely (until stop() method called, or new play() called)
-
-#if !defined(__AVR_ATmega8__)
-volatile long timer0_toggle_count;
-volatile uint8_t *timer0_pin_port;
-volatile uint8_t timer0_pin_mask;
-#endif
-
-volatile long timer1_toggle_count;
-volatile uint8_t *timer1_pin_port;
-volatile uint8_t timer1_pin_mask;
-volatile long timer2_toggle_count;
-volatile uint8_t *timer2_pin_port;
-volatile uint8_t timer2_pin_mask;
-
-#if defined(TIMSK3)
-volatile long timer3_toggle_count;
-volatile uint8_t *timer3_pin_port;
-volatile uint8_t timer3_pin_mask;
-#endif
-
-#if defined(TIMSK4)
-volatile long timer4_toggle_count;
-volatile uint8_t *timer4_pin_port;
-volatile uint8_t timer4_pin_mask;
-#endif
-
-#if defined(TIMSK5)
-volatile long timer5_toggle_count;
-volatile uint8_t *timer5_pin_port;
-volatile uint8_t timer5_pin_mask;
-#endif
-
-
-// MLS: This does not make sense, the 3 options are the same
-#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
-
-#define AVAILABLE_TONE_PINS 1
-
-const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 3, 4, 5, 1, 0 */ };
-static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255, 255, 255, 255, 255 */ };
-
-#elif defined(__AVR_ATmega8__)
-
-#define AVAILABLE_TONE_PINS 1
-
-const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 1 */ };
-static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255 */ };
-
-#else
-
-#define AVAILABLE_TONE_PINS 1
-
-// Leave timer 0 to last.
-const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 1, 0 */ };
-static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255, 255 */ };
-
-#endif
-
-
-
-static int8_t toneBegin(uint8_t _pin)
-{
-  int8_t _timer = -1;
-
-  // if we're already using the pin, the timer should be configured.  
-  for (int i = 0; i < AVAILABLE_TONE_PINS; i++) {
-    if (tone_pins[i] == _pin) {
-      return pgm_read_byte(tone_pin_to_timer_PGM + i);
-    }
-  }
-  
-  // search for an unused timer.
-  for (int i = 0; i < AVAILABLE_TONE_PINS; i++) {
-    if (tone_pins[i] == 255) {
-      tone_pins[i] = _pin;
-      _timer = pgm_read_byte(tone_pin_to_timer_PGM + i);
-      break;
-    }
-  }
-  
-  if (_timer != -1)
-  {
-    // Set timer specific stuff
-    // All timers in CTC mode
-    // 8 bit timers will require changing prescalar values,
-    // whereas 16 bit timers are set to either ck/1 or ck/64 prescalar
-    switch (_timer)
-    {
-      #if defined(TCCR0A) && defined(TCCR0B)
-      case 0:
-        // 8 bit timer
-        TCCR0A = 0;
-        TCCR0B = 0;
-        bitWrite(TCCR0A, WGM01, 1);
-        bitWrite(TCCR0B, CS00, 1);
-        timer0_pin_port = portOutputRegister(digitalPinToPort(_pin));
-        timer0_pin_mask = digitalPinToBitMask(_pin);
-        break;
-      #endif
-
-      #if defined(TCCR1A) && defined(TCCR1B) && defined(WGM12)
-      case 1:
-        // 16 bit timer
-        TCCR1A = 0;
-        TCCR1B = 0;
-        bitWrite(TCCR1B, WGM12, 1);
-        bitWrite(TCCR1B, CS10, 1);
-        timer1_pin_port = portOutputRegister(digitalPinToPort(_pin));
-        timer1_pin_mask = digitalPinToBitMask(_pin);
-        break;
-      #endif
-
-      #if defined(TCCR2A) && defined(TCCR2B)
-      case 2:
-        // 8 bit timer
-        TCCR2A = 0;
-        TCCR2B = 0;
-        bitWrite(TCCR2A, WGM21, 1);
-        bitWrite(TCCR2B, CS20, 1);
-        timer2_pin_port = portOutputRegister(digitalPinToPort(_pin));
-        timer2_pin_mask = digitalPinToBitMask(_pin);
-        break;
-      #endif
-
-      #if defined(TCCR3A) && defined(TCCR3B) &&  defined(TIMSK3)
-      case 3:
-        // 16 bit timer
-        TCCR3A = 0;
-        TCCR3B = 0;
-        bitWrite(TCCR3B, WGM32, 1);
-        bitWrite(TCCR3B, CS30, 1);
-        timer3_pin_port = portOutputRegister(digitalPinToPort(_pin));
-        timer3_pin_mask = digitalPinToBitMask(_pin);
-        break;
-      #endif
-
-      #if defined(TCCR4A) && defined(TCCR4B) &&  defined(TIMSK4)
-      case 4:
-        // 16 bit timer
-        TCCR4A = 0;
-        TCCR4B = 0;
-        #if defined(WGM42)
-          bitWrite(TCCR4B, WGM42, 1);
-        #elif defined(CS43)
-          #warning this may not be correct
-          // atmega32u4
-          bitWrite(TCCR4B, CS43, 1);
-        #endif
-        bitWrite(TCCR4B, CS40, 1);
-        timer4_pin_port = portOutputRegister(digitalPinToPort(_pin));
-        timer4_pin_mask = digitalPinToBitMask(_pin);
-        break;
-      #endif
-
-      #if defined(TCCR5A) && defined(TCCR5B) &&  defined(TIMSK5)
-      case 5:
-        // 16 bit timer
-        TCCR5A = 0;
-        TCCR5B = 0;
-        bitWrite(TCCR5B, WGM52, 1);
-        bitWrite(TCCR5B, CS50, 1);
-        timer5_pin_port = portOutputRegister(digitalPinToPort(_pin));
-        timer5_pin_mask = digitalPinToBitMask(_pin);
-        break;
-      #endif
-    }
-  }
-
-  return _timer;
-}
-
-
-
-// frequency (in hertz) and duration (in milliseconds).
-
-void tone(uint8_t _pin, unsigned int frequency, unsigned long duration)
-{
-  uint8_t prescalarbits = 0b001;
-  long toggle_count = 0;
-  uint32_t ocr = 0;
-  int8_t _timer;
-
-  _timer = toneBegin(_pin);
-
-  if (_timer >= 0)
-  {
-    // Set the pinMode as OUTPUT
-    pinMode(_pin, OUTPUT);
-    
-    // if we are using an 8 bit timer, scan through prescalars to find the best fit
-    if (_timer == 0 || _timer == 2)
-    {
-      ocr = F_CPU / frequency / 2 - 1;
-      prescalarbits = 0b001;  // ck/1: same for both timers
-      if (ocr > 255)
-      {
-        ocr = F_CPU / frequency / 2 / 8 - 1;
-        prescalarbits = 0b010;  // ck/8: same for both timers
-
-        if (_timer == 2 && ocr > 255)
-        {
-          ocr = F_CPU / frequency / 2 / 32 - 1;
-          prescalarbits = 0b011;
-        }
-
-        if (ocr > 255)
-        {
-          ocr = F_CPU / frequency / 2 / 64 - 1;
-          prescalarbits = _timer == 0 ? 0b011 : 0b100;
-
-          if (_timer == 2 && ocr > 255)
-          {
-            ocr = F_CPU / frequency / 2 / 128 - 1;
-            prescalarbits = 0b101;
-          }
-
-          if (ocr > 255)
-          {
-            ocr = F_CPU / frequency / 2 / 256 - 1;
-            prescalarbits = _timer == 0 ? 0b100 : 0b110;
-            if (ocr > 255)
-            {
-              // can't do any better than /1024
-              ocr = F_CPU / frequency / 2 / 1024 - 1;
-              prescalarbits = _timer == 0 ? 0b101 : 0b111;
-            }
-          }
-        }
-      }
-
-#if defined(TCCR0B)
-      if (_timer == 0)
-      {
-        TCCR0B = prescalarbits;
-      }
-      else
-#endif
-#if defined(TCCR2B)
-      {
-        TCCR2B = prescalarbits;
-      }
-#else
-      {
-        // dummy place holder to make the above ifdefs work
-      }
-#endif
-    }
-    else
-    {
-      // two choices for the 16 bit timers: ck/1 or ck/64
-      ocr = F_CPU / frequency / 2 - 1;
-
-      prescalarbits = 0b001;
-      if (ocr > 0xffff)
-      {
-        ocr = F_CPU / frequency / 2 / 64 - 1;
-        prescalarbits = 0b011;
-      }
-
-      if (_timer == 1)
-      {
-#if defined(TCCR1B)
-        TCCR1B = (TCCR1B & 0b11111000) | prescalarbits;
-#endif
-      }
-#if defined(TCCR3B)
-      else if (_timer == 3)
-        TCCR3B = (TCCR3B & 0b11111000) | prescalarbits;
-#endif
-#if defined(TCCR4B)
-      else if (_timer == 4)
-        TCCR4B = (TCCR4B & 0b11111000) | prescalarbits;
-#endif
-#if defined(TCCR5B)
-      else if (_timer == 5)
-        TCCR5B = (TCCR5B & 0b11111000) | prescalarbits;
-#endif
-
-    }
-    
-
-    // Calculate the toggle count
-    if (duration > 0)
-    {
-      toggle_count = 2 * frequency * duration / 1000;
-    }
-    else
-    {
-      toggle_count = -1;
-    }
-
-    // Set the OCR for the given timer,
-    // set the toggle count,
-    // then turn on the interrupts
-    switch (_timer)
-    {
-
-#if defined(OCR0A) && defined(TIMSK0) && defined(OCIE0A)
-      case 0:
-        OCR0A = ocr;
-        timer0_toggle_count = toggle_count;
-        bitWrite(TIMSK0, OCIE0A, 1);
-        break;
-#endif
-
-      case 1:
-#if defined(OCR1A) && defined(TIMSK1) && defined(OCIE1A)
-        OCR1A = ocr;
-        timer1_toggle_count = toggle_count;
-        bitWrite(TIMSK1, OCIE1A, 1);
-#elif defined(OCR1A) && defined(TIMSK) && defined(OCIE1A)
-        // this combination is for at least the ATmega32
-        OCR1A = ocr;
-        timer1_toggle_count = toggle_count;
-        bitWrite(TIMSK, OCIE1A, 1);
-#endif
-        break;
-
-#if defined(OCR2A) && defined(TIMSK2) && defined(OCIE2A)
-      case 2:
-        OCR2A = ocr;
-        timer2_toggle_count = toggle_count;
-        bitWrite(TIMSK2, OCIE2A, 1);
-        break;
-#endif
-
-#if defined(TIMSK3)
-      case 3:
-        OCR3A = ocr;
-        timer3_toggle_count = toggle_count;
-        bitWrite(TIMSK3, OCIE3A, 1);
-        break;
-#endif
-
-#if defined(TIMSK4)
-      case 4:
-        OCR4A = ocr;
-        timer4_toggle_count = toggle_count;
-        bitWrite(TIMSK4, OCIE4A, 1);
-        break;
-#endif
-
-#if defined(OCR5A) && defined(TIMSK5) && defined(OCIE5A)
-      case 5:
-        OCR5A = ocr;
-        timer5_toggle_count = toggle_count;
-        bitWrite(TIMSK5, OCIE5A, 1);
-        break;
-#endif
-
-    }
-  }
-}
-
-
-// XXX: this function only works properly for timer 2 (the only one we use
-// currently).  for the others, it should end the tone, but won't restore
-// proper PWM functionality for the timer.
-void disableTimer(uint8_t _timer)
-{
-  switch (_timer)
-  {
-    case 0:
-      #if defined(TIMSK0)
-        TIMSK0 = 0;
-      #elif defined(TIMSK)
-        TIMSK = 0; // atmega32
-      #endif
-      break;
-
-#if defined(TIMSK1) && defined(OCIE1A)
-    case 1:
-      bitWrite(TIMSK1, OCIE1A, 0);
-      break;
-#endif
-
-    case 2:
-      #if defined(TIMSK2) && defined(OCIE2A)
-        bitWrite(TIMSK2, OCIE2A, 0); // disable interrupt
-      #endif
-      #if defined(TCCR2A) && defined(WGM20)
-        TCCR2A = (1 << WGM20);
-      #endif
-      #if defined(TCCR2B) && defined(CS22)
-        TCCR2B = (TCCR2B & 0b11111000) | (1 << CS22);
-      #endif
-      #if defined(OCR2A)
-        OCR2A = 0;
-      #endif
-      break;
-
-#if defined(TIMSK3)
-    case 3:
-      TIMSK3 = 0;
-      break;
-#endif
-
-#if defined(TIMSK4)
-    case 4:
-      TIMSK4 = 0;
-      break;
-#endif
-
-#if defined(TIMSK5)
-    case 5:
-      TIMSK5 = 0;
-      break;
-#endif
-  }
-}
-
-
-void noTone(uint8_t _pin)
-{
-  int8_t _timer = -1;
-  
-  for (int i = 0; i < AVAILABLE_TONE_PINS; i++) {
-    if (tone_pins[i] == _pin) {
-      _timer = pgm_read_byte(tone_pin_to_timer_PGM + i);
-      tone_pins[i] = 255;
-    }
-  }
-  
-  disableTimer(_timer);
-
-  digitalWrite(_pin, 0);
-}
-
-#if 0
-#if !defined(__AVR_ATmega8__)
-ISR(TIMER0_COMPA_vect)
-{
-  if (timer0_toggle_count != 0)
-  {
-    // toggle the pin
-    *timer0_pin_port ^= timer0_pin_mask;
-
-    if (timer0_toggle_count > 0)
-      timer0_toggle_count--;
-  }
-  else
-  {
-    disableTimer(0);
-    *timer0_pin_port &= ~(timer0_pin_mask);  // keep pin low after stop
-  }
-}
-#endif
-
-
-ISR(TIMER1_COMPA_vect)
-{
-  if (timer1_toggle_count != 0)
-  {
-    // toggle the pin
-    *timer1_pin_port ^= timer1_pin_mask;
-
-    if (timer1_toggle_count > 0)
-      timer1_toggle_count--;
-  }
-  else
-  {
-    disableTimer(1);
-    *timer1_pin_port &= ~(timer1_pin_mask);  // keep pin low after stop
-  }
-}
-#endif
-
-
-ISR(TIMER2_COMPA_vect)
-{
-
-  if (timer2_toggle_count != 0)
-  {
-    // toggle the pin
-    *timer2_pin_port ^= timer2_pin_mask;
-
-    if (timer2_toggle_count > 0)
-      timer2_toggle_count--;
-  }
-  else
-  {
-    // need to call noTone() so that the tone_pins[] entry is reset, so the
-    // timer gets initialized next time we call tone().
-    // XXX: this assumes timer 2 is always the first one used.
-    noTone(tone_pins[0]);
-//    disableTimer(2);
-//    *timer2_pin_port &= ~(timer2_pin_mask);  // keep pin low after stop
-  }
-}
-
-
-
-//#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
-#if 0
-
-ISR(TIMER3_COMPA_vect)
-{
-  if (timer3_toggle_count != 0)
-  {
-    // toggle the pin
-    *timer3_pin_port ^= timer3_pin_mask;
-
-    if (timer3_toggle_count > 0)
-      timer3_toggle_count--;
-  }
-  else
-  {
-    disableTimer(3);
-    *timer3_pin_port &= ~(timer3_pin_mask);  // keep pin low after stop
-  }
-}
-
-ISR(TIMER4_COMPA_vect)
-{
-  if (timer4_toggle_count != 0)
-  {
-    // toggle the pin
-    *timer4_pin_port ^= timer4_pin_mask;
-
-    if (timer4_toggle_count > 0)
-      timer4_toggle_count--;
-  }
-  else
-  {
-    disableTimer(4);
-    *timer4_pin_port &= ~(timer4_pin_mask);  // keep pin low after stop
-  }
-}
-
-ISR(TIMER5_COMPA_vect)
-{
-  if (timer5_toggle_count != 0)
-  {
-    // toggle the pin
-    *timer5_pin_port ^= timer5_pin_mask;
-
-    if (timer5_toggle_count > 0)
-      timer5_toggle_count--;
-  }
-  else
-  {
-    disableTimer(5);
-    *timer5_pin_port &= ~(timer5_pin_mask);  // keep pin low after stop
-  }
-}
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/USBAPI.h b/lib/usbhost/arduino-1.0.1/cores/arduino/USBAPI.h
deleted file mode 100644
index d5abdb690d..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/USBAPI.h
+++ /dev/null
@@ -1,195 +0,0 @@
-
-
-#ifndef __USBAPI__
-#define __USBAPI__
-
-#if defined(USBCON)
-
-//================================================================================
-//================================================================================
-//	USB
-
-class USBDevice_
-{
-public:
-	USBDevice_();
-	bool configured();
-
-	void attach();
-	void detach();	// Serial port goes down too...
-	void poll();
-};
-extern USBDevice_ USBDevice;
-
-//================================================================================
-//================================================================================
-//	Serial over CDC (Serial1 is the physical port)
-
-class Serial_ : public Stream
-{
-private:
-	ring_buffer *_cdc_rx_buffer;
-public:
-	void begin(uint16_t baud_count);
-	void end(void);
-
-	virtual int available(void);
-	virtual void accept(void);
-	virtual int peek(void);
-	virtual int read(void);
-	virtual void flush(void);
-	virtual size_t write(uint8_t);
-	operator bool();
-};
-extern Serial_ Serial;
-
-//================================================================================
-//================================================================================
-//	Mouse
-
-#define MOUSE_LEFT 1
-#define MOUSE_RIGHT 2
-#define MOUSE_MIDDLE 4
-#define MOUSE_ALL (MOUSE_LEFT | MOUSE_RIGHT | MOUSE_MIDDLE)
-
-class Mouse_
-{
-private:
-	uint8_t _buttons;
-	void buttons(uint8_t b);
-public:
-	Mouse_(void);
-	void begin(void);
-	void end(void);
-	void click(uint8_t b = MOUSE_LEFT);
-	void move(signed char x, signed char y, signed char wheel = 0);	
-	void press(uint8_t b = MOUSE_LEFT);		// press LEFT by default
-	void release(uint8_t b = MOUSE_LEFT);	// release LEFT by default
-	bool isPressed(uint8_t b = MOUSE_LEFT);	// check LEFT by default
-};
-extern Mouse_ Mouse;
-
-//================================================================================
-//================================================================================
-//	Keyboard
-
-#define KEY_LEFT_CTRL		0x80
-#define KEY_LEFT_SHIFT		0x81
-#define KEY_LEFT_ALT		0x82
-#define KEY_LEFT_GUI		0x83
-#define KEY_RIGHT_CTRL		0x84
-#define KEY_RIGHT_SHIFT		0x85
-#define KEY_RIGHT_ALT		0x86
-#define KEY_RIGHT_GUI		0x87
-
-#define KEY_UP_ARROW		0xDA
-#define KEY_DOWN_ARROW		0xD9
-#define KEY_LEFT_ARROW		0xD8
-#define KEY_RIGHT_ARROW		0xD7
-#define KEY_BACKSPACE		0xB2
-#define KEY_TAB				0xB3
-#define KEY_RETURN			0xB0
-#define KEY_ESC				0xB1
-#define KEY_INSERT			0xD1
-#define KEY_DELETE			0xD4
-#define KEY_PAGE_UP			0xD3
-#define KEY_PAGE_DOWN		0xD6
-#define KEY_HOME			0xD2
-#define KEY_END				0xD5
-#define KEY_CAPS_LOCK		0xC1
-#define KEY_F1				0xC2
-#define KEY_F2				0xC3
-#define KEY_F3				0xC4
-#define KEY_F4				0xC5
-#define KEY_F5				0xC6
-#define KEY_F6				0xC7
-#define KEY_F7				0xC8
-#define KEY_F8				0xC9
-#define KEY_F9				0xCA
-#define KEY_F10				0xCB
-#define KEY_F11				0xCC
-#define KEY_F12				0xCD
-
-//	Low level key report: up to 6 keys and shift, ctrl etc at once
-typedef struct
-{
-	uint8_t modifiers;
-	uint8_t reserved;
-	uint8_t keys[6];
-} KeyReport;
-
-class Keyboard_ : public Print
-{
-private:
-	KeyReport _keyReport;
-	void sendReport(KeyReport* keys);
-public:
-	Keyboard_(void);
-	void begin(void);
-	void end(void);
-	virtual size_t write(uint8_t k);
-	virtual size_t press(uint8_t k);
-	virtual size_t release(uint8_t k);
-	virtual void releaseAll(void);
-};
-extern Keyboard_ Keyboard;
-
-//================================================================================
-//================================================================================
-//	Low level API
-
-typedef struct
-{
-	uint8_t bmRequestType;
-	uint8_t bRequest;
-	uint8_t wValueL;
-	uint8_t wValueH;
-	uint16_t wIndex;
-	uint16_t wLength;
-} Setup;
-
-//================================================================================
-//================================================================================
-//	HID 'Driver'
-
-int		HID_GetInterface(uint8_t* interfaceNum);
-int		HID_GetDescriptor(int i);
-bool	HID_Setup(Setup& setup);
-void	HID_SendReport(uint8_t id, const void* data, int len);
-
-//================================================================================
-//================================================================================
-//	MSC 'Driver'
-
-int		MSC_GetInterface(uint8_t* interfaceNum);
-int		MSC_GetDescriptor(int i);
-bool	MSC_Setup(Setup& setup);
-bool	MSC_Data(uint8_t rx,uint8_t tx);
-
-//================================================================================
-//================================================================================
-//	CSC 'Driver'
-
-int		CDC_GetInterface(uint8_t* interfaceNum);
-int		CDC_GetDescriptor(int i);
-bool	CDC_Setup(Setup& setup);
-
-//================================================================================
-//================================================================================
-
-#define TRANSFER_PGM		0x80
-#define TRANSFER_RELEASE	0x40
-#define TRANSFER_ZERO		0x20
-
-int USB_SendControl(uint8_t flags, const void* d, int len);
-int USB_RecvControl(void* d, int len);
-
-uint8_t	USB_Available(uint8_t ep);
-int USB_Send(uint8_t ep, const void* data, int len);	// blocking
-int USB_Recv(uint8_t ep, void* data, int len);		// non-blocking
-int USB_Recv(uint8_t ep);							// non-blocking
-void USB_Flush(uint8_t ep);
-
-#endif
-
-#endif /* if defined(USBCON) */
\ No newline at end of file
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/USBCore.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/USBCore.cpp
deleted file mode 100644
index 6766be61ab..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/USBCore.cpp
+++ /dev/null
@@ -1,672 +0,0 @@
-
-
-/* Copyright (c) 2010, Peter Barrett  
-**  
-** Permission to use, copy, modify, and/or distribute this software for  
-** any purpose with or without fee is hereby granted, provided that the  
-** above copyright notice and this permission notice appear in all copies.  
-** 
-** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL  
-** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED  
-** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR  
-** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES  
-** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,  
-** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  
-** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS  
-** SOFTWARE.  
-*/
-
-#include "Platform.h"
-#include "USBAPI.h"
-#include "USBDesc.h"
-
-#if defined(USBCON)
-
-#define EP_TYPE_CONTROL				0x00
-#define EP_TYPE_BULK_IN				0x81
-#define EP_TYPE_BULK_OUT			0x80
-#define EP_TYPE_INTERRUPT_IN		0xC1
-#define EP_TYPE_INTERRUPT_OUT		0xC0
-#define EP_TYPE_ISOCHRONOUS_IN		0x41
-#define EP_TYPE_ISOCHRONOUS_OUT		0x40
-
-/** Pulse generation counters to keep track of the number of milliseconds remaining for each pulse type */
-#define TX_RX_LED_PULSE_MS 100
-volatile u8 TxLEDPulse; /**< Milliseconds remaining for data Tx LED pulse */
-volatile u8 RxLEDPulse; /**< Milliseconds remaining for data Rx LED pulse */
-
-//==================================================================
-//==================================================================
-
-extern const u16 STRING_LANGUAGE[] PROGMEM;
-extern const u16 STRING_IPRODUCT[] PROGMEM;
-extern const u16 STRING_IMANUFACTURER[] PROGMEM;
-extern const DeviceDescriptor USB_DeviceDescriptor PROGMEM;
-extern const DeviceDescriptor USB_DeviceDescriptorA PROGMEM;
-
-const u16 STRING_LANGUAGE[2] = {
-	(3<<8) | (2+2),
-	0x0409	// English
-};
-
-const u16 STRING_IPRODUCT[17] = {
-	(3<<8) | (2+2*16),
-#if USB_PID == 0x8036	
-	'A','r','d','u','i','n','o',' ','L','e','o','n','a','r','d','o'
-#else
-	'U','S','B',' ','I','O',' ','B','o','a','r','d',' ',' ',' ',' '
-#endif
-};
-
-const u16 STRING_IMANUFACTURER[12] = {
-	(3<<8) | (2+2*11),
-#if USB_VID == 0x2341
-	'A','r','d','u','i','n','o',' ','L','L','C'
-#else
-	'U','n','k','n','o','w','n',' ',' ',' ',' '
-#endif
-};
-
-#ifdef CDC_ENABLED
-#define DEVICE_CLASS 0x02
-#else
-#define DEVICE_CLASS 0x00
-#endif
-
-//	DEVICE DESCRIPTOR
-const DeviceDescriptor USB_DeviceDescriptor =
-	D_DEVICE(0x00,0x00,0x00,64,USB_VID,USB_PID,0x100,IMANUFACTURER,IPRODUCT,0,1);
-
-const DeviceDescriptor USB_DeviceDescriptorA =
-	D_DEVICE(DEVICE_CLASS,0x00,0x00,64,USB_VID,USB_PID,0x100,IMANUFACTURER,IPRODUCT,0,1);
-
-//==================================================================
-//==================================================================
-
-volatile u8 _usbConfiguration = 0;
-
-static inline void WaitIN(void)
-{
-	while (!(UEINTX & (1<<TXINI)));
-}
-
-static inline void ClearIN(void)
-{
-	UEINTX = ~(1<<TXINI);
-}
-
-static inline void WaitOUT(void)
-{
-	while (!(UEINTX & (1<<RXOUTI)))
-		;
-}
-
-static inline u8 WaitForINOrOUT()
-{
-	while (!(UEINTX & ((1<<TXINI)|(1<<RXOUTI))))
-		;
-	return (UEINTX & (1<<RXOUTI)) == 0;
-}
-
-static inline void ClearOUT(void)
-{
-	UEINTX = ~(1<<RXOUTI);
-}
-
-void Recv(volatile u8* data, u8 count)
-{
-	while (count--)
-		*data++ = UEDATX;
-	
-	RXLED1;					// light the RX LED
-	RxLEDPulse = TX_RX_LED_PULSE_MS;	
-}
-
-static inline u8 Recv8()
-{
-	RXLED1;					// light the RX LED
-	RxLEDPulse = TX_RX_LED_PULSE_MS;
-
-	return UEDATX;	
-}
-
-static inline void Send8(u8 d)
-{
-	UEDATX = d;
-}
-
-static inline void SetEP(u8 ep)
-{
-	UENUM = ep;
-}
-
-static inline u8 FifoByteCount()
-{
-	return UEBCLX;
-}
-
-static inline u8 ReceivedSetupInt()
-{
-	return UEINTX & (1<<RXSTPI);
-}
-
-static inline void ClearSetupInt()
-{
-	UEINTX = ~((1<<RXSTPI) | (1<<RXOUTI) | (1<<TXINI));
-}
-
-static inline void Stall()
-{
-	UECONX = (1<<STALLRQ) | (1<<EPEN);
-}
-
-static inline u8 ReadWriteAllowed()
-{
-	return UEINTX & (1<<RWAL);
-}
-
-static inline u8 Stalled()
-{
-	return UEINTX & (1<<STALLEDI);
-}
-
-static inline u8 FifoFree()
-{
-	return UEINTX & (1<<FIFOCON);
-}
-
-static inline void ReleaseRX()
-{
-	UEINTX = 0x6B;	// FIFOCON=0 NAKINI=1 RWAL=1 NAKOUTI=0 RXSTPI=1 RXOUTI=0 STALLEDI=1 TXINI=1
-}
-
-static inline void ReleaseTX()
-{
-	UEINTX = 0x3A;	// FIFOCON=0 NAKINI=0 RWAL=1 NAKOUTI=1 RXSTPI=1 RXOUTI=0 STALLEDI=1 TXINI=0
-}
-
-static inline u8 FrameNumber()
-{
-	return UDFNUML;
-}
-
-//==================================================================
-//==================================================================
-
-u8 USBGetConfiguration(void)
-{
-	return _usbConfiguration;
-}
-
-#define USB_RECV_TIMEOUT
-class LockEP
-{
-	u8 _sreg;
-public:
-	LockEP(u8 ep) : _sreg(SREG)
-	{
-		cli();
-		SetEP(ep & 7);
-	}
-	~LockEP()
-	{
-		SREG = _sreg;
-	}
-};
-
-//	Number of bytes, assumes a rx endpoint
-u8 USB_Available(u8 ep)
-{
-	LockEP lock(ep);
-	return FifoByteCount();
-}
-
-//	Non Blocking receive
-//	Return number of bytes read
-int USB_Recv(u8 ep, void* d, int len)
-{
-	if (!_usbConfiguration || len < 0)
-		return -1;
-	
-	LockEP lock(ep);
-	u8 n = FifoByteCount();
-	len = min(n,len);
-	n = len;
-	u8* dst = (u8*)d;
-	while (n--)
-		*dst++ = Recv8();
-	if (len && !FifoByteCount())	// release empty buffer
-		ReleaseRX();
-	
-	return len;
-}
-
-//	Recv 1 byte if ready
-int USB_Recv(u8 ep)
-{
-	u8 c;
-	if (USB_Recv(ep,&c,1) != 1)
-		return -1;
-	return c;
-}
-
-//	Space in send EP
-u8 USB_SendSpace(u8 ep)
-{
-	LockEP lock(ep);
-	if (!ReadWriteAllowed())
-		return 0;
-	return 64 - FifoByteCount();
-}
-
-//	Blocking Send of data to an endpoint
-int USB_Send(u8 ep, const void* d, int len)
-{
-	if (!_usbConfiguration)
-		return -1;
-
-	int r = len;
-	const u8* data = (const u8*)d;
-	u8 zero = ep & TRANSFER_ZERO;
-	u8 timeout = 250;		// 250ms timeout on send? TODO
-	while (len)
-	{
-		u8 n = USB_SendSpace(ep);
-		if (n == 0)
-		{
-			if (!(--timeout))
-				return -1;
-			delay(1);
-			continue;
-		}
-
-		if (n > len)
-			n = len;
-		len -= n;
-		{
-			LockEP lock(ep);
-			if (ep & TRANSFER_ZERO)
-			{
-				while (n--)
-					Send8(0);
-			}
-			else if (ep & TRANSFER_PGM)
-			{
-				while (n--)
-					Send8(pgm_read_byte(data++));
-			}
-			else
-			{
-				while (n--)
-					Send8(*data++);
-			}
-			if (!ReadWriteAllowed() || ((len == 0) && (ep & TRANSFER_RELEASE)))	// Release full buffer
-				ReleaseTX();
-		}
-	}
-	TXLED1;					// light the TX LED
-	TxLEDPulse = TX_RX_LED_PULSE_MS;
-	return r;
-}
-
-extern const u8 _initEndpoints[] PROGMEM;
-const u8 _initEndpoints[] = 
-{
-	0,
-	
-#ifdef CDC_ENABLED
-	EP_TYPE_INTERRUPT_IN,		// CDC_ENDPOINT_ACM
-	EP_TYPE_BULK_OUT,			// CDC_ENDPOINT_OUT
-	EP_TYPE_BULK_IN,			// CDC_ENDPOINT_IN
-#endif
-
-#ifdef HID_ENABLED
-	EP_TYPE_INTERRUPT_IN		// HID_ENDPOINT_INT
-#endif
-};
-
-#define EP_SINGLE_64 0x32	// EP0
-#define EP_DOUBLE_64 0x36	// Other endpoints
-
-static
-void InitEP(u8 index, u8 type, u8 size)
-{
-	UENUM = index;
-	UECONX = 1;
-	UECFG0X = type;
-	UECFG1X = size;
-}
-
-static
-void InitEndpoints()
-{
-	for (u8 i = 1; i < sizeof(_initEndpoints); i++)
-	{
-		UENUM = i;
-		UECONX = 1;
-		UECFG0X = pgm_read_byte(_initEndpoints+i);
-		UECFG1X = EP_DOUBLE_64;
-	}
-	UERST = 0x7E;	// And reset them
-	UERST = 0;
-}
-
-//	Handle CLASS_INTERFACE requests
-static
-bool ClassInterfaceRequest(Setup& setup)
-{
-	u8 i = setup.wIndex;
-
-#ifdef CDC_ENABLED
-	if (CDC_ACM_INTERFACE == i)
-		return CDC_Setup(setup);
-#endif
-
-#ifdef HID_ENABLED
-	if (HID_INTERFACE == i)
-		return HID_Setup(setup);
-#endif
-	return false;
-}
-
-int _cmark;
-int _cend;
-void InitControl(int end)
-{
-	SetEP(0);
-	_cmark = 0;
-	_cend = end;
-}
-
-static
-bool SendControl(u8 d)
-{
-	if (_cmark < _cend)
-	{
-		if (!WaitForINOrOUT())
-			return false;
-		Send8(d);
-		if (!((_cmark + 1) & 0x3F))
-			ClearIN();	// Fifo is full, release this packet
-	}
-	_cmark++;
-	return true;
-};
-
-//	Clipped by _cmark/_cend
-int USB_SendControl(u8 flags, const void* d, int len)
-{
-	int sent = len;
-	const u8* data = (const u8*)d;
-	bool pgm = flags & TRANSFER_PGM;
-	while (len--)
-	{
-		u8 c = pgm ? pgm_read_byte(data++) : *data++;
-		if (!SendControl(c))
-			return -1;
-	}
-	return sent;
-}
-
-//	Does not timeout or cross fifo boundaries
-//	Will only work for transfers <= 64 bytes
-//	TODO
-int USB_RecvControl(void* d, int len)
-{
-	WaitOUT();
-	Recv((u8*)d,len);
-	ClearOUT();
-	return len;
-}
-
-int SendInterfaces()
-{
-	int total = 0;
-	u8 interfaces = 0;
-
-#ifdef CDC_ENABLED
-	total = CDC_GetInterface(&interfaces);
-#endif
-
-#ifdef HID_ENABLED
-	total += HID_GetInterface(&interfaces);
-#endif
-
-	return interfaces;
-}
-
-//	Construct a dynamic configuration descriptor
-//	This really needs dynamic endpoint allocation etc
-//	TODO
-static
-bool SendConfiguration(int maxlen)
-{
-	//	Count and measure interfaces
-	InitControl(0);	
-	int interfaces = SendInterfaces();
-	ConfigDescriptor config = D_CONFIG(_cmark + sizeof(ConfigDescriptor),interfaces);
-
-	//	Now send them
-	InitControl(maxlen);
-	USB_SendControl(0,&config,sizeof(ConfigDescriptor));
-	SendInterfaces();
-	return true;
-}
-
-u8 _cdcComposite = 0;
-
-static
-bool SendDescriptor(Setup& setup)
-{
-	u8 t = setup.wValueH;
-	if (USB_CONFIGURATION_DESCRIPTOR_TYPE == t)
-		return SendConfiguration(setup.wLength);
-
-	InitControl(setup.wLength);
-#ifdef HID_ENABLED
-	if (HID_REPORT_DESCRIPTOR_TYPE == t)
-		return HID_GetDescriptor(t);
-#endif
-
-	u8 desc_length = 0;
-	const u8* desc_addr = 0;
-	if (USB_DEVICE_DESCRIPTOR_TYPE == t)
-	{
-		if (setup.wLength == 8)
-			_cdcComposite = 1;
-		desc_addr = _cdcComposite ?  (const u8*)&USB_DeviceDescriptorA : (const u8*)&USB_DeviceDescriptor;
-	}
-	else if (USB_STRING_DESCRIPTOR_TYPE == t)
-	{
-		if (setup.wValueL == 0)
-			desc_addr = (const u8*)&STRING_LANGUAGE;
-		else if (setup.wValueL == IPRODUCT) 
-			desc_addr = (const u8*)&STRING_IPRODUCT;
-		else if (setup.wValueL == IMANUFACTURER)
-			desc_addr = (const u8*)&STRING_IMANUFACTURER;
-		else
-			return false;
-	}
-
-	if (desc_addr == 0)
-		return false;
-	if (desc_length == 0)
-		desc_length = pgm_read_byte(desc_addr);
-
-	USB_SendControl(TRANSFER_PGM,desc_addr,desc_length);
-	return true;
-}
-
-//	Endpoint 0 interrupt
-ISR(USB_COM_vect)
-{
-    SetEP(0);
-	if (!ReceivedSetupInt())
-		return;
-
-	Setup setup;
-	Recv((u8*)&setup,8);
-	ClearSetupInt();
-
-	u8 requestType = setup.bmRequestType;
-	if (requestType & REQUEST_DEVICETOHOST)
-		WaitIN();
-	else
-		ClearIN();
-
-    bool ok = true;
-	if (REQUEST_STANDARD == (requestType & REQUEST_TYPE))
-	{
-		//	Standard Requests
-		u8 r = setup.bRequest;
-		if (GET_STATUS == r)
-		{
-			Send8(0);		// TODO
-			Send8(0);
-		}
-		else if (CLEAR_FEATURE == r)
-		{
-		}
-		else if (SET_FEATURE == r)
-		{
-		}
-		else if (SET_ADDRESS == r)
-		{
-			WaitIN();
-			UDADDR = setup.wValueL | (1<<ADDEN);
-		}
-		else if (GET_DESCRIPTOR == r)
-		{
-			ok = SendDescriptor(setup);
-		}
-		else if (SET_DESCRIPTOR == r)
-		{
-			ok = false;
-		}
-		else if (GET_CONFIGURATION == r)
-		{
-			Send8(1);
-		}
-		else if (SET_CONFIGURATION == r)
-		{
-			if (REQUEST_DEVICE == (requestType & REQUEST_RECIPIENT))
-			{
-				InitEndpoints();
-				_usbConfiguration = setup.wValueL;
-			} else
-				ok = false;
-		}
-		else if (GET_INTERFACE == r)
-		{
-		}
-		else if (SET_INTERFACE == r)
-		{
-		}
-	}
-	else
-	{
-		InitControl(setup.wLength);		//	Max length of transfer
-		ok = ClassInterfaceRequest(setup);
-	}
-
-	if (ok)
-		ClearIN();
-	else
-	{
-		Stall();
-	}
-}
-
-void USB_Flush(u8 ep)
-{
-	SetEP(ep);
-	if (FifoByteCount())
-		ReleaseTX();
-}
-
-//	General interrupt
-ISR(USB_GEN_vect)
-{
-	u8 udint = UDINT;
-	UDINT = 0;
-
-	//	End of Reset
-	if (udint & (1<<EORSTI))
-	{
-		InitEP(0,EP_TYPE_CONTROL,EP_SINGLE_64);	// init ep0
-		_usbConfiguration = 0;			// not configured yet
-		UEIENX = 1 << RXSTPE;			// Enable interrupts for ep0
-	}
-
-	//	Start of Frame - happens every millisecond so we use it for TX and RX LED one-shot timing, too
-	if (udint & (1<<SOFI))
-	{
-#ifdef CDC_ENABLED
-		USB_Flush(CDC_TX);				// Send a tx frame if found
-		while (USB_Available(CDC_RX))	// Handle received bytes (if any)
-			Serial.accept();
-#endif
-		
-		// check whether the one-shot period has elapsed.  if so, turn off the LED
-		if (TxLEDPulse && !(--TxLEDPulse))
-			TXLED0;
-		if (RxLEDPulse && !(--RxLEDPulse))
-			RXLED0;
-	}
-}
-
-//	VBUS or counting frames
-//	Any frame counting?
-u8 USBConnected()
-{
-	u8 f = UDFNUML;
-	delay(3);
-	return f != UDFNUML;
-}
-
-//=======================================================================
-//=======================================================================
-
-USBDevice_ USBDevice;
-
-USBDevice_::USBDevice_()
-{
-}
-
-void USBDevice_::attach()
-{
-	_usbConfiguration = 0;
-	UHWCON = 0x01;						// power internal reg
-	USBCON = (1<<USBE)|(1<<FRZCLK);		// clock frozen, usb enabled
-	PLLCSR = 0x12;						// Need 16 MHz xtal
-	while (!(PLLCSR & (1<<PLOCK)))		// wait for lock pll
-		;
-
-	// Some tests on specific versions of macosx (10.7.3), reported some
-	// strange behaviuors when the board is reset using the serial
-	// port touch at 1200 bps. This delay fixes this behaviour.
-	delay(1);
-
-	USBCON = ((1<<USBE)|(1<<OTGPADE));	// start USB clock
-	UDIEN = (1<<EORSTE)|(1<<SOFE);		// Enable interrupts for EOR (End of Reset) and SOF (start of frame)
-	UDCON = 0;							// enable attach resistor
-	
-	TX_RX_LED_INIT;
-}
-
-void USBDevice_::detach()
-{
-}
-
-//	Check for interrupts
-//	TODO: VBUS detection
-bool USBDevice_::configured()
-{
-	return _usbConfiguration;
-}
-
-void USBDevice_::poll()
-{
-}
-
-#endif /* if defined(USBCON) */
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/USBCore.h b/lib/usbhost/arduino-1.0.1/cores/arduino/USBCore.h
deleted file mode 100644
index 8d13806896..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/USBCore.h
+++ /dev/null
@@ -1,303 +0,0 @@
-
-// Copyright (c) 2010, Peter Barrett 
-/*
-** Permission to use, copy, modify, and/or distribute this software for  
-** any purpose with or without fee is hereby granted, provided that the  
-** above copyright notice and this permission notice appear in all copies.  
-**  
-** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL  
-** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED  
-** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR  
-** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES  
-** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,  
-** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  
-** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS  
-** SOFTWARE.  
-*/
-
-#ifndef __USBCORE_H__
-#define __USBCORE_H__
-
-//	Standard requests
-#define GET_STATUS			0
-#define CLEAR_FEATURE		1
-#define SET_FEATURE			3
-#define SET_ADDRESS			5
-#define GET_DESCRIPTOR		6
-#define SET_DESCRIPTOR		7
-#define GET_CONFIGURATION	8
-#define SET_CONFIGURATION	9
-#define GET_INTERFACE		10
-#define SET_INTERFACE		11
-
-
-// bmRequestType
-#define REQUEST_HOSTTODEVICE	0x00
-#define REQUEST_DEVICETOHOST	0x80
-#define REQUEST_DIRECTION		0x80
-
-#define REQUEST_STANDARD		0x00
-#define REQUEST_CLASS			0x20
-#define REQUEST_VENDOR			0x40
-#define REQUEST_TYPE			0x60
-
-#define REQUEST_DEVICE			0x00
-#define REQUEST_INTERFACE		0x01
-#define REQUEST_ENDPOINT		0x02
-#define REQUEST_OTHER			0x03
-#define REQUEST_RECIPIENT		0x03
-
-#define REQUEST_DEVICETOHOST_CLASS_INTERFACE  (REQUEST_DEVICETOHOST + REQUEST_CLASS + REQUEST_INTERFACE)
-#define REQUEST_HOSTTODEVICE_CLASS_INTERFACE  (REQUEST_HOSTTODEVICE + REQUEST_CLASS + REQUEST_INTERFACE)
-
-//	Class requests
-
-#define CDC_SET_LINE_CODING			0x20
-#define CDC_GET_LINE_CODING			0x21
-#define CDC_SET_CONTROL_LINE_STATE	0x22
-
-#define MSC_RESET					0xFF
-#define MSC_GET_MAX_LUN				0xFE
-
-#define HID_GET_REPORT				0x01
-#define HID_GET_IDLE				0x02
-#define HID_GET_PROTOCOL			0x03
-#define HID_SET_REPORT				0x09
-#define HID_SET_IDLE				0x0A
-#define HID_SET_PROTOCOL			0x0B
-
-//	Descriptors
-
-#define USB_DEVICE_DESC_SIZE 18
-#define USB_CONFIGUARTION_DESC_SIZE 9
-#define USB_INTERFACE_DESC_SIZE 9
-#define USB_ENDPOINT_DESC_SIZE 7
-
-#define USB_DEVICE_DESCRIPTOR_TYPE             1
-#define USB_CONFIGURATION_DESCRIPTOR_TYPE      2
-#define USB_STRING_DESCRIPTOR_TYPE             3
-#define USB_INTERFACE_DESCRIPTOR_TYPE          4
-#define USB_ENDPOINT_DESCRIPTOR_TYPE           5
-
-#define USB_DEVICE_CLASS_COMMUNICATIONS        0x02
-#define USB_DEVICE_CLASS_HUMAN_INTERFACE       0x03
-#define USB_DEVICE_CLASS_STORAGE               0x08
-#define USB_DEVICE_CLASS_VENDOR_SPECIFIC       0xFF
-
-#define USB_CONFIG_POWERED_MASK                0x40
-#define USB_CONFIG_BUS_POWERED                 0x80
-#define USB_CONFIG_SELF_POWERED                0xC0
-#define USB_CONFIG_REMOTE_WAKEUP               0x20
-
-// bMaxPower in Configuration Descriptor
-#define USB_CONFIG_POWER_MA(mA)                ((mA)/2)
-
-// bEndpointAddress in Endpoint Descriptor
-#define USB_ENDPOINT_DIRECTION_MASK            0x80
-#define USB_ENDPOINT_OUT(addr)                 ((addr) | 0x00)
-#define USB_ENDPOINT_IN(addr)                  ((addr) | 0x80)
-
-#define USB_ENDPOINT_TYPE_MASK                 0x03
-#define USB_ENDPOINT_TYPE_CONTROL              0x00
-#define USB_ENDPOINT_TYPE_ISOCHRONOUS          0x01
-#define USB_ENDPOINT_TYPE_BULK                 0x02
-#define USB_ENDPOINT_TYPE_INTERRUPT            0x03
-
-#define TOBYTES(x) ((x) & 0xFF),(((x) >> 8) & 0xFF)
-
-#define CDC_V1_10                               0x0110
-#define CDC_COMMUNICATION_INTERFACE_CLASS       0x02
-
-#define CDC_CALL_MANAGEMENT                     0x01
-#define CDC_ABSTRACT_CONTROL_MODEL              0x02
-#define CDC_HEADER                              0x00
-#define CDC_ABSTRACT_CONTROL_MANAGEMENT         0x02
-#define CDC_UNION                               0x06
-#define CDC_CS_INTERFACE                        0x24
-#define CDC_CS_ENDPOINT                         0x25
-#define CDC_DATA_INTERFACE_CLASS                0x0A
-
-#define MSC_SUBCLASS_SCSI						0x06 
-#define MSC_PROTOCOL_BULK_ONLY					0x50 
-
-#define HID_HID_DESCRIPTOR_TYPE					0x21
-#define HID_REPORT_DESCRIPTOR_TYPE				0x22
-#define HID_PHYSICAL_DESCRIPTOR_TYPE			0x23
-
-
-//	Device
-typedef struct {
-	u8 len;				// 18
-	u8 dtype;			// 1 USB_DEVICE_DESCRIPTOR_TYPE
-	u16 usbVersion;		// 0x200
-	u8	deviceClass;
-	u8	deviceSubClass;
-	u8	deviceProtocol;
-	u8	packetSize0;	// Packet 0
-	u16	idVendor;
-	u16	idProduct;
-	u16	deviceVersion;	// 0x100
-	u8	iManufacturer;
-	u8	iProduct;
-	u8	iSerialNumber;
-	u8	bNumConfigurations;
-} DeviceDescriptor;
-
-//	Config
-typedef struct {
-	u8	len;			// 9
-	u8	dtype;			// 2
-	u16 clen;			// total length
-	u8	numInterfaces;
-	u8	config;
-	u8	iconfig;
-	u8	attributes;
-	u8	maxPower;
-} ConfigDescriptor;
-
-//	String
-
-//	Interface
-typedef struct
-{
-	u8 len;		// 9
-	u8 dtype;	// 4
-	u8 number;
-	u8 alternate;
-	u8 numEndpoints;
-	u8 interfaceClass;
-	u8 interfaceSubClass;
-	u8 protocol;
-	u8 iInterface;
-} InterfaceDescriptor;
-
-//	Endpoint
-typedef struct
-{
-	u8 len;		// 7
-	u8 dtype;	// 5
-	u8 addr;
-	u8 attr;
-	u16 packetSize;
-	u8 interval;
-} EndpointDescriptor;
-
-// Interface Association Descriptor
-// Used to bind 2 interfaces together in CDC compostite device
-typedef struct
-{
-	u8 len;				// 8
-	u8 dtype;			// 11
-	u8 firstInterface;
-	u8 interfaceCount;
-	u8 functionClass;
-	u8 funtionSubClass;
-	u8 functionProtocol;
-	u8 iInterface;
-} IADDescriptor;
-
-//	CDC CS interface descriptor
-typedef struct
-{
-	u8 len;		// 5
-	u8 dtype;	// 0x24
-	u8 subtype;
-	u8 d0;
-	u8 d1;
-} CDCCSInterfaceDescriptor;
-
-typedef struct
-{
-	u8 len;		// 4
-	u8 dtype;	// 0x24
-	u8 subtype;
-	u8 d0;
-} CDCCSInterfaceDescriptor4;
-
-typedef struct 
-{
-    u8	len;
-    u8 	dtype;		// 0x24
-    u8 	subtype;	// 1
-    u8 	bmCapabilities;
-    u8 	bDataInterface;
-} CMFunctionalDescriptor;
-	
-typedef struct 
-{
-    u8	len;
-    u8 	dtype;		// 0x24
-    u8 	subtype;	// 1
-    u8 	bmCapabilities;
-} ACMFunctionalDescriptor;
-
-typedef struct 
-{
-	//	IAD
-	IADDescriptor				iad;	// Only needed on compound device
-
-	//	Control
-	InterfaceDescriptor			cif;	// 
-	CDCCSInterfaceDescriptor	header;
-	CMFunctionalDescriptor		callManagement;			// Call Management
-	ACMFunctionalDescriptor		controlManagement;		// ACM
-	CDCCSInterfaceDescriptor	functionalDescriptor;	// CDC_UNION
-	EndpointDescriptor			cifin;
-
-	//	Data
-	InterfaceDescriptor			dif;
-	EndpointDescriptor			in;
-	EndpointDescriptor			out;
-} CDCDescriptor;
-
-typedef struct 
-{
-	InterfaceDescriptor			msc;
-	EndpointDescriptor			in;
-	EndpointDescriptor			out;
-} MSCDescriptor;
-
-typedef struct
-{
-	u8 len;			// 9
-	u8 dtype;		// 0x21
-	u8 addr;
-	u8	versionL;	// 0x101
-	u8	versionH;	// 0x101
-	u8	country;
-	u8	desctype;	// 0x22 report
-	u8	descLenL;
-	u8	descLenH;
-} HIDDescDescriptor;
-
-typedef struct 
-{
-	InterfaceDescriptor			hid;
-	HIDDescDescriptor			desc;
-	EndpointDescriptor			in;
-} HIDDescriptor;
-
-
-#define D_DEVICE(_class,_subClass,_proto,_packetSize0,_vid,_pid,_version,_im,_ip,_is,_configs) \
-	{ 18, 1, 0x200, _class,_subClass,_proto,_packetSize0,_vid,_pid,_version,_im,_ip,_is,_configs }
-
-#define D_CONFIG(_totalLength,_interfaces) \
-	{ 9, 2, _totalLength,_interfaces, 1, 0, USB_CONFIG_BUS_POWERED, USB_CONFIG_POWER_MA(500) }
-
-#define D_INTERFACE(_n,_numEndpoints,_class,_subClass,_protocol) \
-	{ 9, 4, _n, 0, _numEndpoints, _class,_subClass, _protocol, 0 }
-
-#define D_ENDPOINT(_addr,_attr,_packetSize, _interval) \
-	{ 7, 5, _addr,_attr,_packetSize, _interval }
-
-#define D_IAD(_firstInterface, _count, _class, _subClass, _protocol) \
-	{ 8, 11, _firstInterface, _count, _class, _subClass, _protocol, 0 }
-
-#define D_HIDREPORT(_descriptorLength) \
-	{ 9, 0x21, 0x1, 0x1, 0, 1, 0x22, _descriptorLength, 0 }
-
-#define D_CDCCS(_subtype,_d0,_d1)	{ 5, 0x24, _subtype, _d0, _d1 }
-#define D_CDCCS4(_subtype,_d0)		{ 4, 0x24, _subtype, _d0 }
-
-
-#endif
\ No newline at end of file
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/USBDesc.h b/lib/usbhost/arduino-1.0.1/cores/arduino/USBDesc.h
deleted file mode 100644
index 900713e0f9..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/USBDesc.h
+++ /dev/null
@@ -1,63 +0,0 @@
-
-
-/* Copyright (c) 2011, Peter Barrett  
-**  
-** Permission to use, copy, modify, and/or distribute this software for  
-** any purpose with or without fee is hereby granted, provided that the  
-** above copyright notice and this permission notice appear in all copies.  
-** 
-** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL  
-** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED  
-** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR  
-** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES  
-** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,  
-** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  
-** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS  
-** SOFTWARE.  
-*/
-
-#define CDC_ENABLED
-#define HID_ENABLED
-
-
-#ifdef CDC_ENABLED
-#define CDC_INTERFACE_COUNT	2
-#define CDC_ENPOINT_COUNT	3
-#else
-#define CDC_INTERFACE_COUNT	0
-#define CDC_ENPOINT_COUNT	0
-#endif
-
-#ifdef HID_ENABLED
-#define HID_INTERFACE_COUNT	1
-#define HID_ENPOINT_COUNT	1
-#else
-#define HID_INTERFACE_COUNT	0
-#define HID_ENPOINT_COUNT	0
-#endif
-
-#define CDC_ACM_INTERFACE	0	// CDC ACM
-#define CDC_DATA_INTERFACE	1	// CDC Data
-#define CDC_FIRST_ENDPOINT	1
-#define CDC_ENDPOINT_ACM	(CDC_FIRST_ENDPOINT)							// CDC First
-#define CDC_ENDPOINT_OUT	(CDC_FIRST_ENDPOINT+1)
-#define CDC_ENDPOINT_IN		(CDC_FIRST_ENDPOINT+2)
-
-#define HID_INTERFACE		(CDC_ACM_INTERFACE + CDC_INTERFACE_COUNT)		// HID Interface
-#define HID_FIRST_ENDPOINT	(CDC_FIRST_ENDPOINT + CDC_ENPOINT_COUNT)
-#define HID_ENDPOINT_INT	(HID_FIRST_ENDPOINT)
-
-#define INTERFACE_COUNT		(MSC_INTERFACE + MSC_INTERFACE_COUNT)
-
-#ifdef CDC_ENABLED
-#define CDC_RX CDC_ENDPOINT_OUT
-#define CDC_TX CDC_ENDPOINT_IN
-#endif
-
-#ifdef HID_ENABLED
-#define HID_TX HID_ENDPOINT_INT
-#endif
-
-#define IMANUFACTURER	1
-#define IPRODUCT		2
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/Udp.h b/lib/usbhost/arduino-1.0.1/cores/arduino/Udp.h
deleted file mode 100644
index dc5644b9df..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/Udp.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *  Udp.cpp: Library to send/receive UDP packets.
- *
- * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray for mentioning these)
- * 1) UDP does not guarantee the order in which assembled UDP packets are received. This
- * might not happen often in practice, but in larger network topologies, a UDP
- * packet can be received out of sequence. 
- * 2) UDP does not guard against lost packets - so packets *can* disappear without the sender being
- * aware of it. Again, this may not be a concern in practice on small local networks.
- * For more information, see http://www.cafeaulait.org/course/week12/35.html
- *
- * MIT License:
- * Copyright (c) 2008 Bjoern Hartmann
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- * 
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- * 
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * bjoern@cs.stanford.edu 12/30/2008
- */
-
-#ifndef udp_h
-#define udp_h
-
-#include <Stream.h>
-#include <IPAddress.h>
-
-class UDP : public Stream {
-
-public:
-  virtual uint8_t begin(uint16_t) =0;	// initialize, start listening on specified port. Returns 1 if successful, 0 if there are no sockets available to use
-  virtual void stop() =0;  // Finish with the UDP socket
-
-  // Sending UDP packets
-  
-  // Start building up a packet to send to the remote host specific in ip and port
-  // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port
-  virtual int beginPacket(IPAddress ip, uint16_t port) =0;
-  // Start building up a packet to send to the remote host specific in host and port
-  // Returns 1 if successful, 0 if there was a problem resolving the hostname or port
-  virtual int beginPacket(const char *host, uint16_t port) =0;
-  // Finish off this packet and send it
-  // Returns 1 if the packet was sent successfully, 0 if there was an error
-  virtual int endPacket() =0;
-  // Write a single byte into the packet
-  virtual size_t write(uint8_t) =0;
-  // Write size bytes from buffer into the packet
-  virtual size_t write(const uint8_t *buffer, size_t size) =0;
-
-  // Start processing the next available incoming packet
-  // Returns the size of the packet in bytes, or 0 if no packets are available
-  virtual int parsePacket() =0;
-  // Number of bytes remaining in the current packet
-  virtual int available() =0;
-  // Read a single byte from the current packet
-  virtual int read() =0;
-  // Read up to len bytes from the current packet and place them into buffer
-  // Returns the number of bytes read, or 0 if none are available
-  virtual int read(unsigned char* buffer, size_t len) =0;
-  // Read up to len characters from the current packet and place them into buffer
-  // Returns the number of characters read, or 0 if none are available
-  virtual int read(char* buffer, size_t len) =0;
-  // Return the next byte from the current packet without moving on to the next byte
-  virtual int peek() =0;
-  virtual void flush() =0;	// Finish reading the current packet
-
-  // Return the IP address of the host who sent the current incoming packet
-  virtual IPAddress remoteIP() =0;
-  // Return the port of the host who sent the current incoming packet
-  virtual uint16_t remotePort() =0;
-protected:
-  uint8_t* rawIPAddress(IPAddress& addr) { return addr.raw_address(); };
-};
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/WCharacter.h b/lib/usbhost/arduino-1.0.1/cores/arduino/WCharacter.h
deleted file mode 100644
index 79733b50a5..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/WCharacter.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- WCharacter.h - Character utility functions for Wiring & Arduino
- Copyright (c) 2010 Hernando Barragan.  All right reserved.
- 
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
- 
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
- 
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef Character_h
-#define Character_h
-
-#include <ctype.h>
-
-// WCharacter.h prototypes
-inline boolean isAlphaNumeric(int c) __attribute__((always_inline));
-inline boolean isAlpha(int c) __attribute__((always_inline));
-inline boolean isAscii(int c) __attribute__((always_inline));
-inline boolean isWhitespace(int c) __attribute__((always_inline));
-inline boolean isControl(int c) __attribute__((always_inline));
-inline boolean isDigit(int c) __attribute__((always_inline));
-inline boolean isGraph(int c) __attribute__((always_inline));
-inline boolean isLowerCase(int c) __attribute__((always_inline));
-inline boolean isPrintable(int c) __attribute__((always_inline));
-inline boolean isPunct(int c) __attribute__((always_inline));
-inline boolean isSpace(int c) __attribute__((always_inline));
-inline boolean isUpperCase(int c) __attribute__((always_inline));
-inline boolean isHexadecimalDigit(int c) __attribute__((always_inline));
-inline int toAscii(int c) __attribute__((always_inline));
-inline int toLowerCase(int c) __attribute__((always_inline));
-inline int toUpperCase(int c)__attribute__((always_inline));
-
-
-// Checks for an alphanumeric character. 
-// It is equivalent to (isalpha(c) || isdigit(c)).
-inline boolean isAlphaNumeric(int c) 
-{
-  return ( isalnum(c) == 0 ? false : true);
-}
-
-
-// Checks for an alphabetic character. 
-// It is equivalent to (isupper(c) || islower(c)).
-inline boolean isAlpha(int c)
-{
-  return ( isalpha(c) == 0 ? false : true);
-}
-
-
-// Checks whether c is a 7-bit unsigned char value 
-// that fits into the ASCII character set.
-inline boolean isAscii(int c)
-{
-  return ( isascii (c) == 0 ? false : true);
-}
-
-
-// Checks for a blank character, that is, a space or a tab.
-inline boolean isWhitespace(int c)
-{
-  return ( isblank (c) == 0 ? false : true);
-}
-
-
-// Checks for a control character.
-inline boolean isControl(int c)
-{
-  return ( iscntrl (c) == 0 ? false : true);
-}
-
-
-// Checks for a digit (0 through 9).
-inline boolean isDigit(int c)
-{
-  return ( isdigit (c) == 0 ? false : true);
-}
-
-
-// Checks for any printable character except space.
-inline boolean isGraph(int c)
-{
-  return ( isgraph (c) == 0 ? false : true);
-}
-
-
-// Checks for a lower-case character.
-inline boolean isLowerCase(int c)
-{
-  return (islower (c) == 0 ? false : true);
-}
-
-
-// Checks for any printable character including space.
-inline boolean isPrintable(int c)
-{
-  return ( isprint (c) == 0 ? false : true);
-}
-
-
-// Checks for any printable character which is not a space 
-// or an alphanumeric character.
-inline boolean isPunct(int c)
-{
-  return ( ispunct (c) == 0 ? false : true);
-}
-
-
-// Checks for white-space characters. For the avr-libc library, 
-// these are: space, formfeed ('\f'), newline ('\n'), carriage 
-// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v').
-inline boolean isSpace(int c)
-{
-  return ( isspace (c) == 0 ? false : true);
-}
-
-
-// Checks for an uppercase letter.
-inline boolean isUpperCase(int c)
-{
-  return ( isupper (c) == 0 ? false : true);
-}
-
-
-// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 
-// 8 9 a b c d e f A B C D E F.
-inline boolean isHexadecimalDigit(int c)
-{
-  return ( isxdigit (c) == 0 ? false : true);
-}
-
-
-// Converts c to a 7-bit unsigned char value that fits into the 
-// ASCII character set, by clearing the high-order bits.
-inline int toAscii(int c)
-{
-  return toascii (c);
-}
-
-
-// Warning:
-// Many people will be unhappy if you use this function. 
-// This function will convert accented letters into random 
-// characters.
-
-// Converts the letter c to lower case, if possible.
-inline int toLowerCase(int c)
-{
-  return tolower (c);
-}
-
-
-// Converts the letter c to upper case, if possible.
-inline int toUpperCase(int c)
-{
-  return toupper (c);
-}
-
-#endif
\ No newline at end of file
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/WInterrupts.c b/lib/usbhost/arduino-1.0.1/cores/arduino/WInterrupts.c
deleted file mode 100644
index 8f3ec847f1..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/WInterrupts.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */
-
-/*
-  Part of the Wiring project - http://wiring.uniandes.edu.co
-
-  Copyright (c) 2004-05 Hernando Barragan
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-  
-  Modified 24 November 2006 by David A. Mellis
-  Modified 1 August 2010 by Mark Sproul
-*/
-
-#include <inttypes.h>
-#include <avr/io.h>
-#include <avr/interrupt.h>
-#include <avr/pgmspace.h>
-#include <stdio.h>
-
-#include "wiring_private.h"
-
-static volatile voidFuncPtr intFunc[EXTERNAL_NUM_INTERRUPTS];
-// volatile static voidFuncPtr twiIntFunc;
-
-void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode) {
-  if(interruptNum < EXTERNAL_NUM_INTERRUPTS) {
-    intFunc[interruptNum] = userFunc;
-    
-    // Configure the interrupt mode (trigger on low input, any change, rising
-    // edge, or falling edge).  The mode constants were chosen to correspond
-    // to the configuration bits in the hardware register, so we simply shift
-    // the mode into place.
-      
-    // Enable the interrupt.
-      
-    switch (interruptNum) {
-#if defined(__AVR_ATmega32U4__)
-	// I hate doing this, but the register assignment differs between the 1280/2560
-	// and the 32U4.  Since avrlib defines registers PCMSK1 and PCMSK2 that aren't 
-	// even present on the 32U4 this is the only way to distinguish between them.
-	case 0:
-		EICRA = (EICRA & ~((1<<ISC00) | (1<<ISC01))) | (mode << ISC00);
-		EIMSK |= (1<<INT0);
-		break;
-	case 1:
-		EICRA = (EICRA & ~((1<<ISC10) | (1<<ISC11))) | (mode << ISC10);
-		EIMSK |= (1<<INT1);
-		break;	
-#elif defined(EICRA) && defined(EICRB) && defined(EIMSK)
-    case 2:
-      EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
-      EIMSK |= (1 << INT0);
-      break;
-    case 3:
-      EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
-      EIMSK |= (1 << INT1);
-      break;
-    case 4:
-      EICRA = (EICRA & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
-      EIMSK |= (1 << INT2);
-      break;
-    case 5:
-      EICRA = (EICRA & ~((1 << ISC30) | (1 << ISC31))) | (mode << ISC30);
-      EIMSK |= (1 << INT3);
-      break;
-    case 0:
-      EICRB = (EICRB & ~((1 << ISC40) | (1 << ISC41))) | (mode << ISC40);
-      EIMSK |= (1 << INT4);
-      break;
-    case 1:
-      EICRB = (EICRB & ~((1 << ISC50) | (1 << ISC51))) | (mode << ISC50);
-      EIMSK |= (1 << INT5);
-      break;
-    case 6:
-      EICRB = (EICRB & ~((1 << ISC60) | (1 << ISC61))) | (mode << ISC60);
-      EIMSK |= (1 << INT6);
-      break;
-    case 7:
-      EICRB = (EICRB & ~((1 << ISC70) | (1 << ISC71))) | (mode << ISC70);
-      EIMSK |= (1 << INT7);
-      break;
-#else		
-    case 0:
-    #if defined(EICRA) && defined(ISC00) && defined(EIMSK)
-      EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
-      EIMSK |= (1 << INT0);
-    #elif defined(MCUCR) && defined(ISC00) && defined(GICR)
-      MCUCR = (MCUCR & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
-      GICR |= (1 << INT0);
-    #elif defined(MCUCR) && defined(ISC00) && defined(GIMSK)
-      MCUCR = (MCUCR & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00);
-      GIMSK |= (1 << INT0);
-    #else
-      #error attachInterrupt not finished for this CPU (case 0)
-    #endif
-      break;
-
-    case 1:
-    #if defined(EICRA) && defined(ISC10) && defined(ISC11) && defined(EIMSK)
-      EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
-      EIMSK |= (1 << INT1);
-    #elif defined(MCUCR) && defined(ISC10) && defined(ISC11) && defined(GICR)
-      MCUCR = (MCUCR & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
-      GICR |= (1 << INT1);
-    #elif defined(MCUCR) && defined(ISC10) && defined(GIMSK) && defined(GIMSK)
-      MCUCR = (MCUCR & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10);
-      GIMSK |= (1 << INT1);
-    #else
-      #warning attachInterrupt may need some more work for this cpu (case 1)
-    #endif
-      break;
-    
-    case 2:
-    #if defined(EICRA) && defined(ISC20) && defined(ISC21) && defined(EIMSK)
-      EICRA = (EICRA & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
-      EIMSK |= (1 << INT2);
-    #elif defined(MCUCR) && defined(ISC20) && defined(ISC21) && defined(GICR)
-      MCUCR = (MCUCR & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
-      GICR |= (1 << INT2);
-    #elif defined(MCUCR) && defined(ISC20) && defined(GIMSK) && defined(GIMSK)
-      MCUCR = (MCUCR & ~((1 << ISC20) | (1 << ISC21))) | (mode << ISC20);
-      GIMSK |= (1 << INT2);
-    #endif
-      break;
-#endif
-    }
-  }
-}
-
-void detachInterrupt(uint8_t interruptNum) {
-  if(interruptNum < EXTERNAL_NUM_INTERRUPTS) {
-    // Disable the interrupt.  (We can't assume that interruptNum is equal
-    // to the number of the EIMSK bit to clear, as this isn't true on the 
-    // ATmega8.  There, INT0 is 6 and INT1 is 7.)
-    switch (interruptNum) {
-#if defined(__AVR_ATmega32U4__)
-	case 0:
-		EIMSK &= ~(1<<INT0);
-		break;
-	case 1:
-		EIMSK &= ~(1<<INT1);
-		break;		
-#elif defined(EICRA) && defined(EICRB) && defined(EIMSK)
-    case 2:
-      EIMSK &= ~(1 << INT0);
-      break;
-    case 3:
-      EIMSK &= ~(1 << INT1);
-      break;
-    case 4:
-      EIMSK &= ~(1 << INT2);
-      break;
-    case 5:
-      EIMSK &= ~(1 << INT3);
-      break;
-    case 0:
-      EIMSK &= ~(1 << INT4);
-      break;
-    case 1:
-      EIMSK &= ~(1 << INT5);
-      break;
-    case 6:
-      EIMSK &= ~(1 << INT6);
-      break;
-    case 7:
-      EIMSK &= ~(1 << INT7);
-      break;
-#else
-    case 0:
-    #if defined(EIMSK) && defined(INT0)
-      EIMSK &= ~(1 << INT0);
-    #elif defined(GICR) && defined(ISC00)
-      GICR &= ~(1 << INT0); // atmega32
-    #elif defined(GIMSK) && defined(INT0)
-      GIMSK &= ~(1 << INT0);
-    #else
-      #error detachInterrupt not finished for this cpu
-    #endif
-      break;
-
-    case 1:
-    #if defined(EIMSK) && defined(INT1)
-      EIMSK &= ~(1 << INT1);
-    #elif defined(GICR) && defined(INT1)
-      GICR &= ~(1 << INT1); // atmega32
-    #elif defined(GIMSK) && defined(INT1)
-      GIMSK &= ~(1 << INT1);
-    #else
-      #warning detachInterrupt may need some more work for this cpu (case 1)
-    #endif
-      break;
-#endif
-    }
-      
-    intFunc[interruptNum] = 0;
-  }
-}
-
-/*
-void attachInterruptTwi(void (*userFunc)(void) ) {
-  twiIntFunc = userFunc;
-}
-*/
-
-#if defined(__AVR_ATmega32U4__)
-SIGNAL(INT0_vect) {
-	if(intFunc[EXTERNAL_INT_0])
-		intFunc[EXTERNAL_INT_0]();
-}
-
-SIGNAL(INT1_vect) {
-	if(intFunc[EXTERNAL_INT_1])
-		intFunc[EXTERNAL_INT_1]();
-}
-
-#elif defined(EICRA) && defined(EICRB)
-
-SIGNAL(INT0_vect) {
-  if(intFunc[EXTERNAL_INT_2])
-    intFunc[EXTERNAL_INT_2]();
-}
-
-SIGNAL(INT1_vect) {
-  if(intFunc[EXTERNAL_INT_3])
-    intFunc[EXTERNAL_INT_3]();
-}
-
-SIGNAL(INT2_vect) {
-  if(intFunc[EXTERNAL_INT_4])
-    intFunc[EXTERNAL_INT_4]();
-}
-
-SIGNAL(INT3_vect) {
-  if(intFunc[EXTERNAL_INT_5])
-    intFunc[EXTERNAL_INT_5]();
-}
-
-SIGNAL(INT4_vect) {
-  if(intFunc[EXTERNAL_INT_0])
-    intFunc[EXTERNAL_INT_0]();
-}
-
-SIGNAL(INT5_vect) {
-  if(intFunc[EXTERNAL_INT_1])
-    intFunc[EXTERNAL_INT_1]();
-}
-
-SIGNAL(INT6_vect) {
-  if(intFunc[EXTERNAL_INT_6])
-    intFunc[EXTERNAL_INT_6]();
-}
-
-SIGNAL(INT7_vect) {
-  if(intFunc[EXTERNAL_INT_7])
-    intFunc[EXTERNAL_INT_7]();
-}
-
-#else
-
-SIGNAL(INT0_vect) {
-  if(intFunc[EXTERNAL_INT_0])
-    intFunc[EXTERNAL_INT_0]();
-}
-
-SIGNAL(INT1_vect) {
-  if(intFunc[EXTERNAL_INT_1])
-    intFunc[EXTERNAL_INT_1]();
-}
-
-#if defined(EICRA) && defined(ISC20)
-SIGNAL(INT2_vect) {
-  if(intFunc[EXTERNAL_INT_2])
-    intFunc[EXTERNAL_INT_2]();
-}
-#endif
-
-#endif
-
-/*
-SIGNAL(SIG_2WIRE_SERIAL) {
-  if(twiIntFunc)
-    twiIntFunc();
-}
-*/
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/WMath.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/WMath.cpp
deleted file mode 100644
index 2120c4cc10..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/WMath.cpp
+++ /dev/null
@@ -1,60 +0,0 @@
-/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */
-
-/*
-  Part of the Wiring project - http://wiring.org.co
-  Copyright (c) 2004-06 Hernando Barragan
-  Modified 13 August 2006, David A. Mellis for Arduino - http://www.arduino.cc/
-  
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-  
-  $Id$
-*/
-
-extern "C" {
-  #include "stdlib.h"
-}
-
-void randomSeed(unsigned int seed)
-{
-  if (seed != 0) {
-    srandom(seed);
-  }
-}
-
-long random(long howbig)
-{
-  if (howbig == 0) {
-    return 0;
-  }
-  return random() % howbig;
-}
-
-long random(long howsmall, long howbig)
-{
-  if (howsmall >= howbig) {
-    return howsmall;
-  }
-  long diff = howbig - howsmall;
-  return random(diff) + howsmall;
-}
-
-long map(long x, long in_min, long in_max, long out_min, long out_max)
-{
-  return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min;
-}
-
-unsigned int makeWord(unsigned int w) { return w; }
-unsigned int makeWord(unsigned char h, unsigned char l) { return (h << 8) | l; }
\ No newline at end of file
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/WString.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/WString.cpp
deleted file mode 100644
index c6839fc0d9..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/WString.cpp
+++ /dev/null
@@ -1,645 +0,0 @@
-/*
-  WString.cpp - String library for Wiring & Arduino
-  ...mostly rewritten by Paul Stoffregen...
-  Copyright (c) 2009-10 Hernando Barragan.  All rights reserved.
-  Copyright 2011, Paul Stoffregen, paul@pjrc.com
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-
-#include "WString.h"
-
-
-/*********************************************/
-/*  Constructors                             */
-/*********************************************/
-
-String::String(const char *cstr)
-{
-	init();
-	if (cstr) copy(cstr, strlen(cstr));
-}
-
-String::String(const String &value)
-{
-	init();
-	*this = value;
-}
-
-#ifdef __GXX_EXPERIMENTAL_CXX0X__
-String::String(String &&rval)
-{
-	init();
-	move(rval);
-}
-String::String(StringSumHelper &&rval)
-{
-	init();
-	move(rval);
-}
-#endif
-
-String::String(char c)
-{
-	init();
-	char buf[2];
-	buf[0] = c;
-	buf[1] = 0;
-	*this = buf;
-}
-
-String::String(unsigned char value, unsigned char base)
-{
-	init();
-	char buf[9];
-	utoa(value, buf, base);
-	*this = buf;
-}
-
-String::String(int value, unsigned char base)
-{
-	init();
-	char buf[18];
-	itoa(value, buf, base);
-	*this = buf;
-}
-
-String::String(unsigned int value, unsigned char base)
-{
-	init();
-	char buf[17];
-	utoa(value, buf, base);
-	*this = buf;
-}
-
-String::String(long value, unsigned char base)
-{
-	init();
-	char buf[34];
-	ltoa(value, buf, base);
-	*this = buf;
-}
-
-String::String(unsigned long value, unsigned char base)
-{
-	init();
-	char buf[33];
-	ultoa(value, buf, base);
-	*this = buf;
-}
-
-String::~String()
-{
-	free(buffer);
-}
-
-/*********************************************/
-/*  Memory Management                        */
-/*********************************************/
-
-inline void String::init(void)
-{
-	buffer = NULL;
-	capacity = 0;
-	len = 0;
-	flags = 0;
-}
-
-void String::invalidate(void)
-{
-	if (buffer) free(buffer);
-	buffer = NULL;
-	capacity = len = 0;
-}
-
-unsigned char String::reserve(unsigned int size)
-{
-	if (buffer && capacity >= size) return 1;
-	if (changeBuffer(size)) {
-		if (len == 0) buffer[0] = 0;
-		return 1;
-	}
-	return 0;
-}
-
-unsigned char String::changeBuffer(unsigned int maxStrLen)
-{
-	char *newbuffer = (char *)realloc(buffer, maxStrLen + 1);
-	if (newbuffer) {
-		buffer = newbuffer;
-		capacity = maxStrLen;
-		return 1;
-	}
-	return 0;
-}
-
-/*********************************************/
-/*  Copy and Move                            */
-/*********************************************/
-
-String & String::copy(const char *cstr, unsigned int length)
-{
-	if (!reserve(length)) {
-		invalidate();
-		return *this;
-	}
-	len = length;
-	strcpy(buffer, cstr);
-	return *this;
-}
-
-#ifdef __GXX_EXPERIMENTAL_CXX0X__
-void String::move(String &rhs)
-{
-	if (buffer) {
-		if (capacity >= rhs.len) {
-			strcpy(buffer, rhs.buffer);
-			len = rhs.len;
-			rhs.len = 0;
-			return;
-		} else {
-			free(buffer);
-		}
-	}
-	buffer = rhs.buffer;
-	capacity = rhs.capacity;
-	len = rhs.len;
-	rhs.buffer = NULL;
-	rhs.capacity = 0;
-	rhs.len = 0;
-}
-#endif
-
-String & String::operator = (const String &rhs)
-{
-	if (this == &rhs) return *this;
-	
-	if (rhs.buffer) copy(rhs.buffer, rhs.len);
-	else invalidate();
-	
-	return *this;
-}
-
-#ifdef __GXX_EXPERIMENTAL_CXX0X__
-String & String::operator = (String &&rval)
-{
-	if (this != &rval) move(rval);
-	return *this;
-}
-
-String & String::operator = (StringSumHelper &&rval)
-{
-	if (this != &rval) move(rval);
-	return *this;
-}
-#endif
-
-String & String::operator = (const char *cstr)
-{
-	if (cstr) copy(cstr, strlen(cstr));
-	else invalidate();
-	
-	return *this;
-}
-
-/*********************************************/
-/*  concat                                   */
-/*********************************************/
-
-unsigned char String::concat(const String &s)
-{
-	return concat(s.buffer, s.len);
-}
-
-unsigned char String::concat(const char *cstr, unsigned int length)
-{
-	unsigned int newlen = len + length;
-	if (!cstr) return 0;
-	if (length == 0) return 1;
-	if (!reserve(newlen)) return 0;
-	strcpy(buffer + len, cstr);
-	len = newlen;
-	return 1;
-}
-
-unsigned char String::concat(const char *cstr)
-{
-	if (!cstr) return 0;
-	return concat(cstr, strlen(cstr));
-}
-
-unsigned char String::concat(char c)
-{
-	char buf[2];
-	buf[0] = c;
-	buf[1] = 0;
-	return concat(buf, 1);
-}
-
-unsigned char String::concat(unsigned char num)
-{
-	char buf[4];
-	itoa(num, buf, 10);
-	return concat(buf, strlen(buf));
-}
-
-unsigned char String::concat(int num)
-{
-	char buf[7];
-	itoa(num, buf, 10);
-	return concat(buf, strlen(buf));
-}
-
-unsigned char String::concat(unsigned int num)
-{
-	char buf[6];
-	utoa(num, buf, 10);
-	return concat(buf, strlen(buf));
-}
-
-unsigned char String::concat(long num)
-{
-	char buf[12];
-	ltoa(num, buf, 10);
-	return concat(buf, strlen(buf));
-}
-
-unsigned char String::concat(unsigned long num)
-{
-	char buf[11];
-	ultoa(num, buf, 10);
-	return concat(buf, strlen(buf));
-}
-
-/*********************************************/
-/*  Concatenate                              */
-/*********************************************/
-
-StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs)
-{
-	StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-	if (!a.concat(rhs.buffer, rhs.len)) a.invalidate();
-	return a;
-}
-
-StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr)
-{
-	StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-	if (!cstr || !a.concat(cstr, strlen(cstr))) a.invalidate();
-	return a;
-}
-
-StringSumHelper & operator + (const StringSumHelper &lhs, char c)
-{
-	StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-	if (!a.concat(c)) a.invalidate();
-	return a;
-}
-
-StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num)
-{
-	StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-	if (!a.concat(num)) a.invalidate();
-	return a;
-}
-
-StringSumHelper & operator + (const StringSumHelper &lhs, int num)
-{
-	StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-	if (!a.concat(num)) a.invalidate();
-	return a;
-}
-
-StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num)
-{
-	StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-	if (!a.concat(num)) a.invalidate();
-	return a;
-}
-
-StringSumHelper & operator + (const StringSumHelper &lhs, long num)
-{
-	StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-	if (!a.concat(num)) a.invalidate();
-	return a;
-}
-
-StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num)
-{
-	StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-	if (!a.concat(num)) a.invalidate();
-	return a;
-}
-
-/*********************************************/
-/*  Comparison                               */
-/*********************************************/
-
-int String::compareTo(const String &s) const
-{
-	if (!buffer || !s.buffer) {
-		if (s.buffer && s.len > 0) return 0 - *(unsigned char *)s.buffer;
-		if (buffer && len > 0) return *(unsigned char *)buffer;
-		return 0;
-	}
-	return strcmp(buffer, s.buffer);
-}
-
-unsigned char String::equals(const String &s2) const
-{
-	return (len == s2.len && compareTo(s2) == 0);
-}
-
-unsigned char String::equals(const char *cstr) const
-{
-	if (len == 0) return (cstr == NULL || *cstr == 0);
-	if (cstr == NULL) return buffer[0] == 0;
-	return strcmp(buffer, cstr) == 0;
-}
-
-unsigned char String::operator<(const String &rhs) const
-{
-	return compareTo(rhs) < 0;
-}
-
-unsigned char String::operator>(const String &rhs) const
-{
-	return compareTo(rhs) > 0;
-}
-
-unsigned char String::operator<=(const String &rhs) const
-{
-	return compareTo(rhs) <= 0;
-}
-
-unsigned char String::operator>=(const String &rhs) const
-{
-	return compareTo(rhs) >= 0;
-}
-
-unsigned char String::equalsIgnoreCase( const String &s2 ) const
-{
-	if (this == &s2) return 1;
-	if (len != s2.len) return 0;
-	if (len == 0) return 1;
-	const char *p1 = buffer;
-	const char *p2 = s2.buffer;
-	while (*p1) {
-		if (tolower(*p1++) != tolower(*p2++)) return 0;
-	} 
-	return 1;
-}
-
-unsigned char String::startsWith( const String &s2 ) const
-{
-	if (len < s2.len) return 0;
-	return startsWith(s2, 0);
-}
-
-unsigned char String::startsWith( const String &s2, unsigned int offset ) const
-{
-	if (offset > len - s2.len || !buffer || !s2.buffer) return 0;
-	return strncmp( &buffer[offset], s2.buffer, s2.len ) == 0;
-}
-
-unsigned char String::endsWith( const String &s2 ) const
-{
-	if ( len < s2.len || !buffer || !s2.buffer) return 0;
-	return strcmp(&buffer[len - s2.len], s2.buffer) == 0;
-}
-
-/*********************************************/
-/*  Character Access                         */
-/*********************************************/
-
-char String::charAt(unsigned int loc) const
-{
-	return operator[](loc);
-}
-
-void String::setCharAt(unsigned int loc, char c) 
-{
-	if (loc < len) buffer[loc] = c;
-}
-
-char & String::operator[](unsigned int index)
-{
-	static char dummy_writable_char;
-	if (index >= len || !buffer) {
-		dummy_writable_char = 0;
-		return dummy_writable_char;
-	}
-	return buffer[index];
-}
-
-char String::operator[]( unsigned int index ) const
-{
-	if (index >= len || !buffer) return 0;
-	return buffer[index];
-}
-
-void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const
-{
-	if (!bufsize || !buf) return;
-	if (index >= len) {
-		buf[0] = 0;
-		return;
-	}
-	unsigned int n = bufsize - 1;
-	if (n > len - index) n = len - index;
-	strncpy((char *)buf, buffer + index, n);
-	buf[n] = 0;
-}
-
-/*********************************************/
-/*  Search                                   */
-/*********************************************/
-
-int String::indexOf(char c) const
-{
-	return indexOf(c, 0);
-}
-
-int String::indexOf( char ch, unsigned int fromIndex ) const
-{
-	if (fromIndex >= len) return -1;
-	const char* temp = strchr(buffer + fromIndex, ch);
-	if (temp == NULL) return -1;
-	return temp - buffer;
-}
-
-int String::indexOf(const String &s2) const
-{
-	return indexOf(s2, 0);
-}
-
-int String::indexOf(const String &s2, unsigned int fromIndex) const
-{
-	if (fromIndex >= len) return -1;
-	const char *found = strstr(buffer + fromIndex, s2.buffer);
-	if (found == NULL) return -1;
-	return found - buffer;
-}
-
-int String::lastIndexOf( char theChar ) const
-{
-	return lastIndexOf(theChar, len - 1);
-}
-
-int String::lastIndexOf(char ch, unsigned int fromIndex) const
-{
-	if (fromIndex >= len) return -1;
-	char tempchar = buffer[fromIndex + 1];
-	buffer[fromIndex + 1] = '\0';
-	char* temp = strrchr( buffer, ch );
-	buffer[fromIndex + 1] = tempchar;
-	if (temp == NULL) return -1;
-	return temp - buffer;
-}
-
-int String::lastIndexOf(const String &s2) const
-{
-	return lastIndexOf(s2, len - s2.len);
-}
-
-int String::lastIndexOf(const String &s2, unsigned int fromIndex) const
-{
-  	if (s2.len == 0 || len == 0 || s2.len > len) return -1;
-	if (fromIndex >= len) fromIndex = len - 1;
-	int found = -1;
-	for (char *p = buffer; p <= buffer + fromIndex; p++) {
-		p = strstr(p, s2.buffer);
-		if (!p) break;
-		if ((unsigned int)(p - buffer) <= fromIndex) found = p - buffer;
-	}
-	return found;
-}
-
-String String::substring( unsigned int left ) const
-{
-	return substring(left, len);
-}
-
-String String::substring(unsigned int left, unsigned int right) const
-{
-	if (left > right) {
-		unsigned int temp = right;
-		right = left;
-		left = temp;
-	}
-	String out;
-	if (left > len) return out;
-	if (right > len) right = len;
-	char temp = buffer[right];  // save the replaced character
-	buffer[right] = '\0';	
-	out = buffer + left;  // pointer arithmetic
-	buffer[right] = temp;  //restore character
-	return out;
-}
-
-/*********************************************/
-/*  Modification                             */
-/*********************************************/
-
-void String::replace(char find, char replace)
-{
-	if (!buffer) return;
-	for (char *p = buffer; *p; p++) {
-		if (*p == find) *p = replace;
-	}
-}
-
-void String::replace(const String& find, const String& replace)
-{
-	if (len == 0 || find.len == 0) return;
-	int diff = replace.len - find.len;
-	char *readFrom = buffer;
-	char *foundAt;
-	if (diff == 0) {
-		while ((foundAt = strstr(readFrom, find.buffer)) != NULL) {
-			memcpy(foundAt, replace.buffer, replace.len);
-			readFrom = foundAt + replace.len;
-		}
-	} else if (diff < 0) {
-		char *writeTo = buffer;
-		while ((foundAt = strstr(readFrom, find.buffer)) != NULL) {
-			unsigned int n = foundAt - readFrom;
-			memcpy(writeTo, readFrom, n);
-			writeTo += n;
-			memcpy(writeTo, replace.buffer, replace.len);
-			writeTo += replace.len;
-			readFrom = foundAt + find.len;
-			len += diff;
-		}
-		strcpy(writeTo, readFrom);
-	} else {
-		unsigned int size = len; // compute size needed for result
-		while ((foundAt = strstr(readFrom, find.buffer)) != NULL) {
-			readFrom = foundAt + find.len;
-			size += diff;
-		}
-		if (size == len) return;
-		if (size > capacity && !changeBuffer(size)) return; // XXX: tell user!
-		int index = len - 1;
-		while (index >= 0 && (index = lastIndexOf(find, index)) >= 0) {
-			readFrom = buffer + index + find.len;
-			memmove(readFrom + diff, readFrom, len - (readFrom - buffer));
-			len += diff;
-			buffer[len] = 0;
-			memcpy(buffer + index, replace.buffer, replace.len);
-			index--;
-		}
-	}
-}
-
-void String::toLowerCase(void)
-{
-	if (!buffer) return;
-	for (char *p = buffer; *p; p++) {
-		*p = tolower(*p);
-	}
-}
-
-void String::toUpperCase(void)
-{
-	if (!buffer) return;
-	for (char *p = buffer; *p; p++) {
-		*p = toupper(*p);
-	}
-}
-
-void String::trim(void)
-{
-	if (!buffer || len == 0) return;
-	char *begin = buffer;
-	while (isspace(*begin)) begin++;
-	char *end = buffer + len - 1;
-	while (isspace(*end) && end >= begin) end--;
-	len = end + 1 - begin;
-	if (begin > buffer) memcpy(buffer, begin, len);
-	buffer[len] = 0;
-}
-
-/*********************************************/
-/*  Parsing / Conversion                     */
-/*********************************************/
-
-long String::toInt(void) const
-{
-	if (buffer) return atol(buffer);
-	return 0;
-}
-
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/WString.h b/lib/usbhost/arduino-1.0.1/cores/arduino/WString.h
deleted file mode 100644
index 947325e5f5..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/WString.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
-  WString.h - String library for Wiring & Arduino
-  ...mostly rewritten by Paul Stoffregen...
-  Copyright (c) 2009-10 Hernando Barragan.  All right reserved.
-  Copyright 2011, Paul Stoffregen, paul@pjrc.com
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-
-#ifndef String_class_h
-#define String_class_h
-#ifdef __cplusplus
-
-#include <stdlib.h>
-#include <string.h>
-#include <ctype.h>
-#include <avr/pgmspace.h>
-
-// When compiling programs with this class, the following gcc parameters
-// dramatically increase performance and memory (RAM) efficiency, typically
-// with little or no increase in code size.
-//     -felide-constructors
-//     -std=c++0x
-
-class __FlashStringHelper;
-#define F(string_literal) (reinterpret_cast<const __FlashStringHelper *>(PSTR(string_literal)))
-
-// An inherited class for holding the result of a concatenation.  These
-// result objects are assumed to be writable by subsequent concatenations.
-class StringSumHelper;
-
-// The string class
-class String
-{
-	// use a function pointer to allow for "if (s)" without the
-	// complications of an operator bool(). for more information, see:
-	// http://www.artima.com/cppsource/safebool.html
-	typedef void (String::*StringIfHelperType)() const;
-	void StringIfHelper() const {}
-
-public:
-	// constructors
-	// creates a copy of the initial value.
-	// if the initial value is null or invalid, or if memory allocation
-	// fails, the string will be marked as invalid (i.e. "if (s)" will
-	// be false).
-	String(const char *cstr = "");
-	String(const String &str);
-	#ifdef __GXX_EXPERIMENTAL_CXX0X__
-	String(String &&rval);
-	String(StringSumHelper &&rval);
-	#endif
-	explicit String(char c);
-	explicit String(unsigned char, unsigned char base=10);
-	explicit String(int, unsigned char base=10);
-	explicit String(unsigned int, unsigned char base=10);
-	explicit String(long, unsigned char base=10);
-	explicit String(unsigned long, unsigned char base=10);
-	~String(void);
-
-	// memory management
-	// return true on success, false on failure (in which case, the string
-	// is left unchanged).  reserve(0), if successful, will validate an
-	// invalid string (i.e., "if (s)" will be true afterwards)
-	unsigned char reserve(unsigned int size);
-	inline unsigned int length(void) const {return len;}
-
-	// creates a copy of the assigned value.  if the value is null or
-	// invalid, or if the memory allocation fails, the string will be 
-	// marked as invalid ("if (s)" will be false).
-	String & operator = (const String &rhs);
-	String & operator = (const char *cstr);
-	#ifdef __GXX_EXPERIMENTAL_CXX0X__
-	String & operator = (String &&rval);
-	String & operator = (StringSumHelper &&rval);
-	#endif
-
-	// concatenate (works w/ built-in types)
-	
-	// returns true on success, false on failure (in which case, the string
-	// is left unchanged).  if the argument is null or invalid, the 
-	// concatenation is considered unsucessful.  
-	unsigned char concat(const String &str);
-	unsigned char concat(const char *cstr);
-	unsigned char concat(char c);
-	unsigned char concat(unsigned char c);
-	unsigned char concat(int num);
-	unsigned char concat(unsigned int num);
-	unsigned char concat(long num);
-	unsigned char concat(unsigned long num);
-	
-	// if there's not enough memory for the concatenated value, the string
-	// will be left unchanged (but this isn't signalled in any way)
-	String & operator += (const String &rhs)	{concat(rhs); return (*this);}
-	String & operator += (const char *cstr)		{concat(cstr); return (*this);}
-	String & operator += (char c)			{concat(c); return (*this);}
-	String & operator += (unsigned char num)		{concat(num); return (*this);}
-	String & operator += (int num)			{concat(num); return (*this);}
-	String & operator += (unsigned int num)		{concat(num); return (*this);}
-	String & operator += (long num)			{concat(num); return (*this);}
-	String & operator += (unsigned long num)	{concat(num); return (*this);}
-
-	friend StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs);
-	friend StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr);
-	friend StringSumHelper & operator + (const StringSumHelper &lhs, char c);
-	friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num);
-	friend StringSumHelper & operator + (const StringSumHelper &lhs, int num);
-	friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num);
-	friend StringSumHelper & operator + (const StringSumHelper &lhs, long num);
-	friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num);
-
-	// comparison (only works w/ Strings and "strings")
-	operator StringIfHelperType() const { return buffer ? &String::StringIfHelper : 0; }
-	int compareTo(const String &s) const;
-	unsigned char equals(const String &s) const;
-	unsigned char equals(const char *cstr) const;
-	unsigned char operator == (const String &rhs) const {return equals(rhs);}
-	unsigned char operator == (const char *cstr) const {return equals(cstr);}
-	unsigned char operator != (const String &rhs) const {return !equals(rhs);}
-	unsigned char operator != (const char *cstr) const {return !equals(cstr);}
-	unsigned char operator <  (const String &rhs) const;
-	unsigned char operator >  (const String &rhs) const;
-	unsigned char operator <= (const String &rhs) const;
-	unsigned char operator >= (const String &rhs) const;
-	unsigned char equalsIgnoreCase(const String &s) const;
-	unsigned char startsWith( const String &prefix) const;
-	unsigned char startsWith(const String &prefix, unsigned int offset) const;
-	unsigned char endsWith(const String &suffix) const;
-
-	// character acccess
-	char charAt(unsigned int index) const;
-	void setCharAt(unsigned int index, char c);
-	char operator [] (unsigned int index) const;
-	char& operator [] (unsigned int index);
-	void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index=0) const;
-	void toCharArray(char *buf, unsigned int bufsize, unsigned int index=0) const
-		{getBytes((unsigned char *)buf, bufsize, index);}
-
-	// search
-	int indexOf( char ch ) const;
-	int indexOf( char ch, unsigned int fromIndex ) const;
-	int indexOf( const String &str ) const;
-	int indexOf( const String &str, unsigned int fromIndex ) const;
-	int lastIndexOf( char ch ) const;
-	int lastIndexOf( char ch, unsigned int fromIndex ) const;
-	int lastIndexOf( const String &str ) const;
-	int lastIndexOf( const String &str, unsigned int fromIndex ) const;
-	String substring( unsigned int beginIndex ) const;
-	String substring( unsigned int beginIndex, unsigned int endIndex ) const;
-
-	// modification
-	void replace(char find, char replace);
-	void replace(const String& find, const String& replace);
-	void toLowerCase(void);
-	void toUpperCase(void);
-	void trim(void);
-
-	// parsing/conversion
-	long toInt(void) const;
-
-protected:
-	char *buffer;	        // the actual char array
-	unsigned int capacity;  // the array length minus one (for the '\0')
-	unsigned int len;       // the String length (not counting the '\0')
-	unsigned char flags;    // unused, for future features
-protected:
-	void init(void);
-	void invalidate(void);
-	unsigned char changeBuffer(unsigned int maxStrLen);
-	unsigned char concat(const char *cstr, unsigned int length);
-
-	// copy and move
-	String & copy(const char *cstr, unsigned int length);
-	#ifdef __GXX_EXPERIMENTAL_CXX0X__
-	void move(String &rhs);
-	#endif
-};
-
-class StringSumHelper : public String
-{
-public:
-	StringSumHelper(const String &s) : String(s) {}
-	StringSumHelper(const char *p) : String(p) {}
-	StringSumHelper(char c) : String(c) {}
-	StringSumHelper(unsigned char num) : String(num) {}
-	StringSumHelper(int num) : String(num) {}
-	StringSumHelper(unsigned int num) : String(num) {}
-	StringSumHelper(long num) : String(num) {}
-	StringSumHelper(unsigned long num) : String(num) {}
-};
-
-#endif  // __cplusplus
-#endif  // String_class_h
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/binary.h b/lib/usbhost/arduino-1.0.1/cores/arduino/binary.h
deleted file mode 100644
index af1498033a..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/binary.h
+++ /dev/null
@@ -1,515 +0,0 @@
-#ifndef Binary_h
-#define Binary_h
-
-#define B0 0
-#define B00 0
-#define B000 0
-#define B0000 0
-#define B00000 0
-#define B000000 0
-#define B0000000 0
-#define B00000000 0
-#define B1 1
-#define B01 1
-#define B001 1
-#define B0001 1
-#define B00001 1
-#define B000001 1
-#define B0000001 1
-#define B00000001 1
-#define B10 2
-#define B010 2
-#define B0010 2
-#define B00010 2
-#define B000010 2
-#define B0000010 2
-#define B00000010 2
-#define B11 3
-#define B011 3
-#define B0011 3
-#define B00011 3
-#define B000011 3
-#define B0000011 3
-#define B00000011 3
-#define B100 4
-#define B0100 4
-#define B00100 4
-#define B000100 4
-#define B0000100 4
-#define B00000100 4
-#define B101 5
-#define B0101 5
-#define B00101 5
-#define B000101 5
-#define B0000101 5
-#define B00000101 5
-#define B110 6
-#define B0110 6
-#define B00110 6
-#define B000110 6
-#define B0000110 6
-#define B00000110 6
-#define B111 7
-#define B0111 7
-#define B00111 7
-#define B000111 7
-#define B0000111 7
-#define B00000111 7
-#define B1000 8
-#define B01000 8
-#define B001000 8
-#define B0001000 8
-#define B00001000 8
-#define B1001 9
-#define B01001 9
-#define B001001 9
-#define B0001001 9
-#define B00001001 9
-#define B1010 10
-#define B01010 10
-#define B001010 10
-#define B0001010 10
-#define B00001010 10
-#define B1011 11
-#define B01011 11
-#define B001011 11
-#define B0001011 11
-#define B00001011 11
-#define B1100 12
-#define B01100 12
-#define B001100 12
-#define B0001100 12
-#define B00001100 12
-#define B1101 13
-#define B01101 13
-#define B001101 13
-#define B0001101 13
-#define B00001101 13
-#define B1110 14
-#define B01110 14
-#define B001110 14
-#define B0001110 14
-#define B00001110 14
-#define B1111 15
-#define B01111 15
-#define B001111 15
-#define B0001111 15
-#define B00001111 15
-#define B10000 16
-#define B010000 16
-#define B0010000 16
-#define B00010000 16
-#define B10001 17
-#define B010001 17
-#define B0010001 17
-#define B00010001 17
-#define B10010 18
-#define B010010 18
-#define B0010010 18
-#define B00010010 18
-#define B10011 19
-#define B010011 19
-#define B0010011 19
-#define B00010011 19
-#define B10100 20
-#define B010100 20
-#define B0010100 20
-#define B00010100 20
-#define B10101 21
-#define B010101 21
-#define B0010101 21
-#define B00010101 21
-#define B10110 22
-#define B010110 22
-#define B0010110 22
-#define B00010110 22
-#define B10111 23
-#define B010111 23
-#define B0010111 23
-#define B00010111 23
-#define B11000 24
-#define B011000 24
-#define B0011000 24
-#define B00011000 24
-#define B11001 25
-#define B011001 25
-#define B0011001 25
-#define B00011001 25
-#define B11010 26
-#define B011010 26
-#define B0011010 26
-#define B00011010 26
-#define B11011 27
-#define B011011 27
-#define B0011011 27
-#define B00011011 27
-#define B11100 28
-#define B011100 28
-#define B0011100 28
-#define B00011100 28
-#define B11101 29
-#define B011101 29
-#define B0011101 29
-#define B00011101 29
-#define B11110 30
-#define B011110 30
-#define B0011110 30
-#define B00011110 30
-#define B11111 31
-#define B011111 31
-#define B0011111 31
-#define B00011111 31
-#define B100000 32
-#define B0100000 32
-#define B00100000 32
-#define B100001 33
-#define B0100001 33
-#define B00100001 33
-#define B100010 34
-#define B0100010 34
-#define B00100010 34
-#define B100011 35
-#define B0100011 35
-#define B00100011 35
-#define B100100 36
-#define B0100100 36
-#define B00100100 36
-#define B100101 37
-#define B0100101 37
-#define B00100101 37
-#define B100110 38
-#define B0100110 38
-#define B00100110 38
-#define B100111 39
-#define B0100111 39
-#define B00100111 39
-#define B101000 40
-#define B0101000 40
-#define B00101000 40
-#define B101001 41
-#define B0101001 41
-#define B00101001 41
-#define B101010 42
-#define B0101010 42
-#define B00101010 42
-#define B101011 43
-#define B0101011 43
-#define B00101011 43
-#define B101100 44
-#define B0101100 44
-#define B00101100 44
-#define B101101 45
-#define B0101101 45
-#define B00101101 45
-#define B101110 46
-#define B0101110 46
-#define B00101110 46
-#define B101111 47
-#define B0101111 47
-#define B00101111 47
-#define B110000 48
-#define B0110000 48
-#define B00110000 48
-#define B110001 49
-#define B0110001 49
-#define B00110001 49
-#define B110010 50
-#define B0110010 50
-#define B00110010 50
-#define B110011 51
-#define B0110011 51
-#define B00110011 51
-#define B110100 52
-#define B0110100 52
-#define B00110100 52
-#define B110101 53
-#define B0110101 53
-#define B00110101 53
-#define B110110 54
-#define B0110110 54
-#define B00110110 54
-#define B110111 55
-#define B0110111 55
-#define B00110111 55
-#define B111000 56
-#define B0111000 56
-#define B00111000 56
-#define B111001 57
-#define B0111001 57
-#define B00111001 57
-#define B111010 58
-#define B0111010 58
-#define B00111010 58
-#define B111011 59
-#define B0111011 59
-#define B00111011 59
-#define B111100 60
-#define B0111100 60
-#define B00111100 60
-#define B111101 61
-#define B0111101 61
-#define B00111101 61
-#define B111110 62
-#define B0111110 62
-#define B00111110 62
-#define B111111 63
-#define B0111111 63
-#define B00111111 63
-#define B1000000 64
-#define B01000000 64
-#define B1000001 65
-#define B01000001 65
-#define B1000010 66
-#define B01000010 66
-#define B1000011 67
-#define B01000011 67
-#define B1000100 68
-#define B01000100 68
-#define B1000101 69
-#define B01000101 69
-#define B1000110 70
-#define B01000110 70
-#define B1000111 71
-#define B01000111 71
-#define B1001000 72
-#define B01001000 72
-#define B1001001 73
-#define B01001001 73
-#define B1001010 74
-#define B01001010 74
-#define B1001011 75
-#define B01001011 75
-#define B1001100 76
-#define B01001100 76
-#define B1001101 77
-#define B01001101 77
-#define B1001110 78
-#define B01001110 78
-#define B1001111 79
-#define B01001111 79
-#define B1010000 80
-#define B01010000 80
-#define B1010001 81
-#define B01010001 81
-#define B1010010 82
-#define B01010010 82
-#define B1010011 83
-#define B01010011 83
-#define B1010100 84
-#define B01010100 84
-#define B1010101 85
-#define B01010101 85
-#define B1010110 86
-#define B01010110 86
-#define B1010111 87
-#define B01010111 87
-#define B1011000 88
-#define B01011000 88
-#define B1011001 89
-#define B01011001 89
-#define B1011010 90
-#define B01011010 90
-#define B1011011 91
-#define B01011011 91
-#define B1011100 92
-#define B01011100 92
-#define B1011101 93
-#define B01011101 93
-#define B1011110 94
-#define B01011110 94
-#define B1011111 95
-#define B01011111 95
-#define B1100000 96
-#define B01100000 96
-#define B1100001 97
-#define B01100001 97
-#define B1100010 98
-#define B01100010 98
-#define B1100011 99
-#define B01100011 99
-#define B1100100 100
-#define B01100100 100
-#define B1100101 101
-#define B01100101 101
-#define B1100110 102
-#define B01100110 102
-#define B1100111 103
-#define B01100111 103
-#define B1101000 104
-#define B01101000 104
-#define B1101001 105
-#define B01101001 105
-#define B1101010 106
-#define B01101010 106
-#define B1101011 107
-#define B01101011 107
-#define B1101100 108
-#define B01101100 108
-#define B1101101 109
-#define B01101101 109
-#define B1101110 110
-#define B01101110 110
-#define B1101111 111
-#define B01101111 111
-#define B1110000 112
-#define B01110000 112
-#define B1110001 113
-#define B01110001 113
-#define B1110010 114
-#define B01110010 114
-#define B1110011 115
-#define B01110011 115
-#define B1110100 116
-#define B01110100 116
-#define B1110101 117
-#define B01110101 117
-#define B1110110 118
-#define B01110110 118
-#define B1110111 119
-#define B01110111 119
-#define B1111000 120
-#define B01111000 120
-#define B1111001 121
-#define B01111001 121
-#define B1111010 122
-#define B01111010 122
-#define B1111011 123
-#define B01111011 123
-#define B1111100 124
-#define B01111100 124
-#define B1111101 125
-#define B01111101 125
-#define B1111110 126
-#define B01111110 126
-#define B1111111 127
-#define B01111111 127
-#define B10000000 128
-#define B10000001 129
-#define B10000010 130
-#define B10000011 131
-#define B10000100 132
-#define B10000101 133
-#define B10000110 134
-#define B10000111 135
-#define B10001000 136
-#define B10001001 137
-#define B10001010 138
-#define B10001011 139
-#define B10001100 140
-#define B10001101 141
-#define B10001110 142
-#define B10001111 143
-#define B10010000 144
-#define B10010001 145
-#define B10010010 146
-#define B10010011 147
-#define B10010100 148
-#define B10010101 149
-#define B10010110 150
-#define B10010111 151
-#define B10011000 152
-#define B10011001 153
-#define B10011010 154
-#define B10011011 155
-#define B10011100 156
-#define B10011101 157
-#define B10011110 158
-#define B10011111 159
-#define B10100000 160
-#define B10100001 161
-#define B10100010 162
-#define B10100011 163
-#define B10100100 164
-#define B10100101 165
-#define B10100110 166
-#define B10100111 167
-#define B10101000 168
-#define B10101001 169
-#define B10101010 170
-#define B10101011 171
-#define B10101100 172
-#define B10101101 173
-#define B10101110 174
-#define B10101111 175
-#define B10110000 176
-#define B10110001 177
-#define B10110010 178
-#define B10110011 179
-#define B10110100 180
-#define B10110101 181
-#define B10110110 182
-#define B10110111 183
-#define B10111000 184
-#define B10111001 185
-#define B10111010 186
-#define B10111011 187
-#define B10111100 188
-#define B10111101 189
-#define B10111110 190
-#define B10111111 191
-#define B11000000 192
-#define B11000001 193
-#define B11000010 194
-#define B11000011 195
-#define B11000100 196
-#define B11000101 197
-#define B11000110 198
-#define B11000111 199
-#define B11001000 200
-#define B11001001 201
-#define B11001010 202
-#define B11001011 203
-#define B11001100 204
-#define B11001101 205
-#define B11001110 206
-#define B11001111 207
-#define B11010000 208
-#define B11010001 209
-#define B11010010 210
-#define B11010011 211
-#define B11010100 212
-#define B11010101 213
-#define B11010110 214
-#define B11010111 215
-#define B11011000 216
-#define B11011001 217
-#define B11011010 218
-#define B11011011 219
-#define B11011100 220
-#define B11011101 221
-#define B11011110 222
-#define B11011111 223
-#define B11100000 224
-#define B11100001 225
-#define B11100010 226
-#define B11100011 227
-#define B11100100 228
-#define B11100101 229
-#define B11100110 230
-#define B11100111 231
-#define B11101000 232
-#define B11101001 233
-#define B11101010 234
-#define B11101011 235
-#define B11101100 236
-#define B11101101 237
-#define B11101110 238
-#define B11101111 239
-#define B11110000 240
-#define B11110001 241
-#define B11110010 242
-#define B11110011 243
-#define B11110100 244
-#define B11110101 245
-#define B11110110 246
-#define B11110111 247
-#define B11111000 248
-#define B11111001 249
-#define B11111010 250
-#define B11111011 251
-#define B11111100 252
-#define B11111101 253
-#define B11111110 254
-#define B11111111 255
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/main.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/main.cpp
deleted file mode 100644
index 3d4e079d2a..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/main.cpp
+++ /dev/null
@@ -1,20 +0,0 @@
-#include <Arduino.h>
-
-int main(void)
-{
-	init();
-
-#if defined(USBCON)
-	USBDevice.attach();
-#endif
-	
-	setup();
-    
-	for (;;) {
-		loop();
-		if (serialEventRun) serialEventRun();
-	}
-        
-	return 0;
-}
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/new.cpp b/lib/usbhost/arduino-1.0.1/cores/arduino/new.cpp
deleted file mode 100644
index 0f6d4220ef..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/new.cpp
+++ /dev/null
@@ -1,18 +0,0 @@
-#include <new.h>
-
-void * operator new(size_t size)
-{
-  return malloc(size);
-}
-
-void operator delete(void * ptr)
-{
-  free(ptr);
-} 
-
-int __cxa_guard_acquire(__guard *g) {return !*(char *)(g);};
-void __cxa_guard_release (__guard *g) {*(char *)g = 1;};
-void __cxa_guard_abort (__guard *) {}; 
-
-void __cxa_pure_virtual(void) {};
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/new.h b/lib/usbhost/arduino-1.0.1/cores/arduino/new.h
deleted file mode 100644
index cd940ce8b2..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/new.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Header to define new/delete operators as they aren't provided by avr-gcc by default
-   Taken from http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=59453 
- */
-
-#ifndef NEW_H
-#define NEW_H
-
-#include <stdlib.h>
-
-void * operator new(size_t size);
-void operator delete(void * ptr); 
-
-__extension__ typedef int __guard __attribute__((mode (__DI__)));
-
-extern "C" int __cxa_guard_acquire(__guard *);
-extern "C" void __cxa_guard_release (__guard *);
-extern "C" void __cxa_guard_abort (__guard *); 
-
-extern "C" void __cxa_pure_virtual(void);
-
-#endif
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring.c b/lib/usbhost/arduino-1.0.1/cores/arduino/wiring.c
deleted file mode 100644
index ac8bb6f9b4..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
-  wiring.c - Partial implementation of the Wiring API for the ATmega8.
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2005-2006 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  $Id$
-*/
-
-#include "wiring_private.h"
-
-// the prescaler is set so that timer0 ticks every 64 clock cycles, and the
-// the overflow handler is called every 256 ticks.
-#define MICROSECONDS_PER_TIMER0_OVERFLOW (clockCyclesToMicroseconds(64 * 256))
-
-// the whole number of milliseconds per timer0 overflow
-#define MILLIS_INC (MICROSECONDS_PER_TIMER0_OVERFLOW / 1000)
-
-// the fractional number of milliseconds per timer0 overflow. we shift right
-// by three to fit these numbers into a byte. (for the clock speeds we care
-// about - 8 and 16 MHz - this doesn't lose precision.)
-#define FRACT_INC ((MICROSECONDS_PER_TIMER0_OVERFLOW % 1000) >> 3)
-#define FRACT_MAX (1000 >> 3)
-
-volatile unsigned long timer0_overflow_count = 0;
-volatile unsigned long timer0_millis = 0;
-static unsigned char timer0_fract = 0;
-
-#if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__)
-SIGNAL(TIM0_OVF_vect)
-#else
-SIGNAL(TIMER0_OVF_vect)
-#endif
-{
-	// copy these to local variables so they can be stored in registers
-	// (volatile variables must be read from memory on every access)
-	unsigned long m = timer0_millis;
-	unsigned char f = timer0_fract;
-
-	m += MILLIS_INC;
-	f += FRACT_INC;
-	if (f >= FRACT_MAX) {
-		f -= FRACT_MAX;
-		m += 1;
-	}
-
-	timer0_fract = f;
-	timer0_millis = m;
-	timer0_overflow_count++;
-}
-
-unsigned long millis()
-{
-	unsigned long m;
-	uint8_t oldSREG = SREG;
-
-	// disable interrupts while we read timer0_millis or we might get an
-	// inconsistent value (e.g. in the middle of a write to timer0_millis)
-	cli();
-	m = timer0_millis;
-	SREG = oldSREG;
-
-	return m;
-}
-
-unsigned long micros() {
-	unsigned long m;
-	uint8_t oldSREG = SREG, t;
-	
-	cli();
-	m = timer0_overflow_count;
-#if defined(TCNT0)
-	t = TCNT0;
-#elif defined(TCNT0L)
-	t = TCNT0L;
-#else
-	#error TIMER 0 not defined
-#endif
-
-  
-#ifdef TIFR0
-	if ((TIFR0 & _BV(TOV0)) && (t < 255))
-		m++;
-#else
-	if ((TIFR & _BV(TOV0)) && (t < 255))
-		m++;
-#endif
-
-	SREG = oldSREG;
-	
-	return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond());
-}
-
-void delay(unsigned long ms)
-{
-	uint16_t start = (uint16_t)micros();
-
-	while (ms > 0) {
-		if (((uint16_t)micros() - start) >= 1000) {
-			ms--;
-			start += 1000;
-		}
-	}
-}
-
-/* Delay for the given number of microseconds.  Assumes a 8 or 16 MHz clock. */
-void delayMicroseconds(unsigned int us)
-{
-	// calling avrlib's delay_us() function with low values (e.g. 1 or
-	// 2 microseconds) gives delays longer than desired.
-	//delay_us(us);
-#if F_CPU >= 20000000L
-	// for the 20 MHz clock on rare Arduino boards
-
-	// for a one-microsecond delay, simply wait 2 cycle and return. The overhead
-	// of the function call yields a delay of exactly a one microsecond.
-	__asm__ __volatile__ (
-		"nop" "\n\t"
-		"nop"); //just waiting 2 cycle
-	if (--us == 0)
-		return;
-
-	// the following loop takes a 1/5 of a microsecond (4 cycles)
-	// per iteration, so execute it five times for each microsecond of
-	// delay requested.
-	us = (us<<2) + us; // x5 us
-
-	// account for the time taken in the preceeding commands.
-	us -= 2;
-
-#elif F_CPU >= 16000000L
-	// for the 16 MHz clock on most Arduino boards
-
-	// for a one-microsecond delay, simply return.  the overhead
-	// of the function call yields a delay of approximately 1 1/8 us.
-	if (--us == 0)
-		return;
-
-	// the following loop takes a quarter of a microsecond (4 cycles)
-	// per iteration, so execute it four times for each microsecond of
-	// delay requested.
-	us <<= 2;
-
-	// account for the time taken in the preceeding commands.
-	us -= 2;
-#else
-	// for the 8 MHz internal clock on the ATmega168
-
-	// for a one- or two-microsecond delay, simply return.  the overhead of
-	// the function calls takes more than two microseconds.  can't just
-	// subtract two, since us is unsigned; we'd overflow.
-	if (--us == 0)
-		return;
-	if (--us == 0)
-		return;
-
-	// the following loop takes half of a microsecond (4 cycles)
-	// per iteration, so execute it twice for each microsecond of
-	// delay requested.
-	us <<= 1;
-    
-	// partially compensate for the time taken by the preceeding commands.
-	// we can't subtract any more than this or we'd overflow w/ small delays.
-	us--;
-#endif
-
-	// busy wait
-	__asm__ __volatile__ (
-		"1: sbiw %0,1" "\n\t" // 2 cycles
-		"brne 1b" : "=w" (us) : "0" (us) // 2 cycles
-	);
-}
-
-void init()
-{
-	// this needs to be called before setup() or some functions won't
-	// work there
-	sei();
-	
-	// on the ATmega168, timer 0 is also used for fast hardware pwm
-	// (using phase-correct PWM would mean that timer 0 overflowed half as often
-	// resulting in different millis() behavior on the ATmega8 and ATmega168)
-#if defined(TCCR0A) && defined(WGM01)
-	sbi(TCCR0A, WGM01);
-	sbi(TCCR0A, WGM00);
-#endif  
-
-	// set timer 0 prescale factor to 64
-#if defined(__AVR_ATmega128__)
-	// CPU specific: different values for the ATmega128
-	sbi(TCCR0, CS02);
-#elif defined(TCCR0) && defined(CS01) && defined(CS00)
-	// this combination is for the standard atmega8
-	sbi(TCCR0, CS01);
-	sbi(TCCR0, CS00);
-#elif defined(TCCR0B) && defined(CS01) && defined(CS00)
-	// this combination is for the standard 168/328/1280/2560
-	sbi(TCCR0B, CS01);
-	sbi(TCCR0B, CS00);
-#elif defined(TCCR0A) && defined(CS01) && defined(CS00)
-	// this combination is for the __AVR_ATmega645__ series
-	sbi(TCCR0A, CS01);
-	sbi(TCCR0A, CS00);
-#else
-	#error Timer 0 prescale factor 64 not set correctly
-#endif
-
-	// enable timer 0 overflow interrupt
-#if defined(TIMSK) && defined(TOIE0)
-	sbi(TIMSK, TOIE0);
-#elif defined(TIMSK0) && defined(TOIE0)
-	sbi(TIMSK0, TOIE0);
-#else
-	#error	Timer 0 overflow interrupt not set correctly
-#endif
-
-	// timers 1 and 2 are used for phase-correct hardware pwm
-	// this is better for motors as it ensures an even waveform
-	// note, however, that fast pwm mode can achieve a frequency of up
-	// 8 MHz (with a 16 MHz clock) at 50% duty cycle
-
-#if defined(TCCR1B) && defined(CS11) && defined(CS10)
-	TCCR1B = 0;
-
-	// set timer 1 prescale factor to 64
-	sbi(TCCR1B, CS11);
-#if F_CPU >= 8000000L
-	sbi(TCCR1B, CS10);
-#endif
-#elif defined(TCCR1) && defined(CS11) && defined(CS10)
-	sbi(TCCR1, CS11);
-#if F_CPU >= 8000000L
-	sbi(TCCR1, CS10);
-#endif
-#endif
-	// put timer 1 in 8-bit phase correct pwm mode
-#if defined(TCCR1A) && defined(WGM10)
-	sbi(TCCR1A, WGM10);
-#elif defined(TCCR1)
-	#warning this needs to be finished
-#endif
-
-	// set timer 2 prescale factor to 64
-#if defined(TCCR2) && defined(CS22)
-	sbi(TCCR2, CS22);
-#elif defined(TCCR2B) && defined(CS22)
-	sbi(TCCR2B, CS22);
-#else
-	#warning Timer 2 not finished (may not be present on this CPU)
-#endif
-
-	// configure timer 2 for phase correct pwm (8-bit)
-#if defined(TCCR2) && defined(WGM20)
-	sbi(TCCR2, WGM20);
-#elif defined(TCCR2A) && defined(WGM20)
-	sbi(TCCR2A, WGM20);
-#else
-	#warning Timer 2 not finished (may not be present on this CPU)
-#endif
-
-#if defined(TCCR3B) && defined(CS31) && defined(WGM30)
-	sbi(TCCR3B, CS31);		// set timer 3 prescale factor to 64
-	sbi(TCCR3B, CS30);
-	sbi(TCCR3A, WGM30);		// put timer 3 in 8-bit phase correct pwm mode
-#endif
-
-#if defined(TCCR4A) && defined(TCCR4B) && defined(TCCR4D) /* beginning of timer4 block for 32U4 and similar */
-	sbi(TCCR4B, CS42);		// set timer4 prescale factor to 64
-	sbi(TCCR4B, CS41);
-	sbi(TCCR4B, CS40);
-	sbi(TCCR4D, WGM40);		// put timer 4 in phase- and frequency-correct PWM mode	
-	sbi(TCCR4A, PWM4A);		// enable PWM mode for comparator OCR4A
-	sbi(TCCR4C, PWM4D);		// enable PWM mode for comparator OCR4D
-#else /* beginning of timer4 block for ATMEGA1280 and ATMEGA2560 */
-#if defined(TCCR4B) && defined(CS41) && defined(WGM40)
-	sbi(TCCR4B, CS41);		// set timer 4 prescale factor to 64
-	sbi(TCCR4B, CS40);
-	sbi(TCCR4A, WGM40);		// put timer 4 in 8-bit phase correct pwm mode
-#endif
-#endif /* end timer4 block for ATMEGA1280/2560 and similar */	
-
-#if defined(TCCR5B) && defined(CS51) && defined(WGM50)
-	sbi(TCCR5B, CS51);		// set timer 5 prescale factor to 64
-	sbi(TCCR5B, CS50);
-	sbi(TCCR5A, WGM50);		// put timer 5 in 8-bit phase correct pwm mode
-#endif
-
-#if defined(ADCSRA)
-	// set a2d prescale factor to 128
-	// 16 MHz / 128 = 125 KHz, inside the desired 50-200 KHz range.
-	// XXX: this will not work properly for other clock speeds, and
-	// this code should use F_CPU to determine the prescale factor.
-	sbi(ADCSRA, ADPS2);
-	sbi(ADCSRA, ADPS1);
-	sbi(ADCSRA, ADPS0);
-
-	// enable a2d conversions
-	sbi(ADCSRA, ADEN);
-#endif
-
-	// the bootloader connects pins 0 and 1 to the USART; disconnect them
-	// here so they can be used as normal digital i/o; they will be
-	// reconnected in Serial.begin()
-#if defined(UCSRB)
-	UCSRB = 0;
-#elif defined(UCSR0B)
-	UCSR0B = 0;
-#endif
-}
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_analog.c b/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_analog.c
deleted file mode 100644
index 0e9881f6ac..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_analog.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
-  wiring_analog.c - analog input and output
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2005-2006 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  Modified 28 September 2010 by Mark Sproul
-
-  $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $
-*/
-
-#include "wiring_private.h"
-#include "pins_arduino.h"
-
-uint8_t analog_reference = DEFAULT;
-
-void analogReference(uint8_t mode)
-{
-	// can't actually set the register here because the default setting
-	// will connect AVCC and the AREF pin, which would cause a short if
-	// there's something connected to AREF.
-	analog_reference = mode;
-}
-
-int analogRead(uint8_t pin)
-{
-	uint8_t low, high;
-
-#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
-	if (pin >= 54) pin -= 54; // allow for channel or pin numbers
-#elif defined(__AVR_ATmega32U4__)
-	if (pin >= 18) pin -= 18; // allow for channel or pin numbers
-#elif defined(__AVR_ATmega1284__)
-	if (pin >= 24) pin -= 24; // allow for channel or pin numbers
-#else
-	if (pin >= 14) pin -= 14; // allow for channel or pin numbers
-#endif
-	
-#if defined(__AVR_ATmega32U4__)
-	pin = analogPinToChannel(pin);
-	ADCSRB = (ADCSRB & ~(1 << MUX5)) | (((pin >> 3) & 0x01) << MUX5);
-#elif defined(ADCSRB) && defined(MUX5)
-	// the MUX5 bit of ADCSRB selects whether we're reading from channels
-	// 0 to 7 (MUX5 low) or 8 to 15 (MUX5 high).
-	ADCSRB = (ADCSRB & ~(1 << MUX5)) | (((pin >> 3) & 0x01) << MUX5);
-#endif
-  
-	// set the analog reference (high two bits of ADMUX) and select the
-	// channel (low 4 bits).  this also sets ADLAR (left-adjust result)
-	// to 0 (the default).
-#if defined(ADMUX)
-	ADMUX = (analog_reference << 6) | (pin & 0x07);
-#endif
-
-	// without a delay, we seem to read from the wrong channel
-	//delay(1);
-
-#if defined(ADCSRA) && defined(ADCL)
-	// start the conversion
-	sbi(ADCSRA, ADSC);
-
-	// ADSC is cleared when the conversion finishes
-	while (bit_is_set(ADCSRA, ADSC));
-
-	// we have to read ADCL first; doing so locks both ADCL
-	// and ADCH until ADCH is read.  reading ADCL second would
-	// cause the results of each conversion to be discarded,
-	// as ADCL and ADCH would be locked when it completed.
-	low  = ADCL;
-	high = ADCH;
-#else
-	// we dont have an ADC, return 0
-	low  = 0;
-	high = 0;
-#endif
-
-	// combine the two bytes
-	return (high << 8) | low;
-}
-
-// Right now, PWM output only works on the pins with
-// hardware support.  These are defined in the appropriate
-// pins_*.c file.  For the rest of the pins, we default
-// to digital output.
-void analogWrite(uint8_t pin, int val)
-{
-	// We need to make sure the PWM output is enabled for those pins
-	// that support it, as we turn it off when digitally reading or
-	// writing with them.  Also, make sure the pin is in output mode
-	// for consistenty with Wiring, which doesn't require a pinMode
-	// call for the analog output pins.
-	pinMode(pin, OUTPUT);
-	if (val == 0)
-	{
-		digitalWrite(pin, LOW);
-	}
-	else if (val == 255)
-	{
-		digitalWrite(pin, HIGH);
-	}
-	else
-	{
-		switch(digitalPinToTimer(pin))
-		{
-			// XXX fix needed for atmega8
-			#if defined(TCCR0) && defined(COM00) && !defined(__AVR_ATmega8__)
-			case TIMER0A:
-				// connect pwm to pin on timer 0
-				sbi(TCCR0, COM00);
-				OCR0 = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR0A) && defined(COM0A1)
-			case TIMER0A:
-				// connect pwm to pin on timer 0, channel A
-				sbi(TCCR0A, COM0A1);
-				OCR0A = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR0A) && defined(COM0B1)
-			case TIMER0B:
-				// connect pwm to pin on timer 0, channel B
-				sbi(TCCR0A, COM0B1);
-				OCR0B = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR1A) && defined(COM1A1)
-			case TIMER1A:
-				// connect pwm to pin on timer 1, channel A
-				sbi(TCCR1A, COM1A1);
-				OCR1A = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR1A) && defined(COM1B1)
-			case TIMER1B:
-				// connect pwm to pin on timer 1, channel B
-				sbi(TCCR1A, COM1B1);
-				OCR1B = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR2) && defined(COM21)
-			case TIMER2:
-				// connect pwm to pin on timer 2
-				sbi(TCCR2, COM21);
-				OCR2 = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR2A) && defined(COM2A1)
-			case TIMER2A:
-				// connect pwm to pin on timer 2, channel A
-				sbi(TCCR2A, COM2A1);
-				OCR2A = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR2A) && defined(COM2B1)
-			case TIMER2B:
-				// connect pwm to pin on timer 2, channel B
-				sbi(TCCR2A, COM2B1);
-				OCR2B = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR3A) && defined(COM3A1)
-			case TIMER3A:
-				// connect pwm to pin on timer 3, channel A
-				sbi(TCCR3A, COM3A1);
-				OCR3A = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR3A) && defined(COM3B1)
-			case TIMER3B:
-				// connect pwm to pin on timer 3, channel B
-				sbi(TCCR3A, COM3B1);
-				OCR3B = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR3A) && defined(COM3C1)
-			case TIMER3C:
-				// connect pwm to pin on timer 3, channel C
-				sbi(TCCR3A, COM3C1);
-				OCR3C = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR4A)
-			case TIMER4A:
-				//connect pwm to pin on timer 4, channel A
-				sbi(TCCR4A, COM4A1);
-				#if defined(COM4A0)		// only used on 32U4
-				cbi(TCCR4A, COM4A0);
-				#endif
-				OCR4A = val;	// set pwm duty
-				break;
-			#endif
-			
-			#if defined(TCCR4A) && defined(COM4B1)
-			case TIMER4B:
-				// connect pwm to pin on timer 4, channel B
-				sbi(TCCR4A, COM4B1);
-				OCR4B = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR4A) && defined(COM4C1)
-			case TIMER4C:
-				// connect pwm to pin on timer 4, channel C
-				sbi(TCCR4A, COM4C1);
-				OCR4C = val; // set pwm duty
-				break;
-			#endif
-				
-			#if defined(TCCR4C) && defined(COM4D1)
-			case TIMER4D:				
-				// connect pwm to pin on timer 4, channel D
-				sbi(TCCR4C, COM4D1);
-				#if defined(COM4D0)		// only used on 32U4
-				cbi(TCCR4C, COM4D0);
-				#endif
-				OCR4D = val;	// set pwm duty
-				break;
-			#endif
-
-							
-			#if defined(TCCR5A) && defined(COM5A1)
-			case TIMER5A:
-				// connect pwm to pin on timer 5, channel A
-				sbi(TCCR5A, COM5A1);
-				OCR5A = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR5A) && defined(COM5B1)
-			case TIMER5B:
-				// connect pwm to pin on timer 5, channel B
-				sbi(TCCR5A, COM5B1);
-				OCR5B = val; // set pwm duty
-				break;
-			#endif
-
-			#if defined(TCCR5A) && defined(COM5C1)
-			case TIMER5C:
-				// connect pwm to pin on timer 5, channel C
-				sbi(TCCR5A, COM5C1);
-				OCR5C = val; // set pwm duty
-				break;
-			#endif
-
-			case NOT_ON_TIMER:
-			default:
-				if (val < 128) {
-					digitalWrite(pin, LOW);
-				} else {
-					digitalWrite(pin, HIGH);
-				}
-		}
-	}
-}
-
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_digital.c b/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_digital.c
deleted file mode 100644
index be323b1dfe..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_digital.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-  wiring_digital.c - digital input and output functions
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2005-2006 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  Modified 28 September 2010 by Mark Sproul
-
-  $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $
-*/
-
-#define ARDUINO_MAIN
-#include "wiring_private.h"
-#include "pins_arduino.h"
-
-void pinMode(uint8_t pin, uint8_t mode)
-{
-	uint8_t bit = digitalPinToBitMask(pin);
-	uint8_t port = digitalPinToPort(pin);
-	volatile uint8_t *reg, *out;
-
-	if (port == NOT_A_PIN) return;
-
-	// JWS: can I let the optimizer do this?
-	reg = portModeRegister(port);
-	out = portOutputRegister(port);
-
-	if (mode == INPUT) { 
-		uint8_t oldSREG = SREG;
-                cli();
-		*reg &= ~bit;
-		*out &= ~bit;
-		SREG = oldSREG;
-	} else if (mode == INPUT_PULLUP) {
-		uint8_t oldSREG = SREG;
-                cli();
-		*reg &= ~bit;
-		*out |= bit;
-		SREG = oldSREG;
-	} else {
-		uint8_t oldSREG = SREG;
-                cli();
-		*reg |= bit;
-		SREG = oldSREG;
-	}
-}
-
-// Forcing this inline keeps the callers from having to push their own stuff
-// on the stack. It is a good performance win and only takes 1 more byte per
-// user than calling. (It will take more bytes on the 168.)
-//
-// But shouldn't this be moved into pinMode? Seems silly to check and do on
-// each digitalread or write.
-//
-// Mark Sproul:
-// - Removed inline. Save 170 bytes on atmega1280
-// - changed to a switch statment; added 32 bytes but much easier to read and maintain.
-// - Added more #ifdefs, now compiles for atmega645
-//
-//static inline void turnOffPWM(uint8_t timer) __attribute__ ((always_inline));
-//static inline void turnOffPWM(uint8_t timer)
-static void turnOffPWM(uint8_t timer)
-{
-	switch (timer)
-	{
-		#if defined(TCCR1A) && defined(COM1A1)
-		case TIMER1A:   cbi(TCCR1A, COM1A1);    break;
-		#endif
-		#if defined(TCCR1A) && defined(COM1B1)
-		case TIMER1B:   cbi(TCCR1A, COM1B1);    break;
-		#endif
-		
-		#if defined(TCCR2) && defined(COM21)
-		case  TIMER2:   cbi(TCCR2, COM21);      break;
-		#endif
-		
-		#if defined(TCCR0A) && defined(COM0A1)
-		case  TIMER0A:  cbi(TCCR0A, COM0A1);    break;
-		#endif
-		
-		#if defined(TIMER0B) && defined(COM0B1)
-		case  TIMER0B:  cbi(TCCR0A, COM0B1);    break;
-		#endif
-		#if defined(TCCR2A) && defined(COM2A1)
-		case  TIMER2A:  cbi(TCCR2A, COM2A1);    break;
-		#endif
-		#if defined(TCCR2A) && defined(COM2B1)
-		case  TIMER2B:  cbi(TCCR2A, COM2B1);    break;
-		#endif
-		
-		#if defined(TCCR3A) && defined(COM3A1)
-		case  TIMER3A:  cbi(TCCR3A, COM3A1);    break;
-		#endif
-		#if defined(TCCR3A) && defined(COM3B1)
-		case  TIMER3B:  cbi(TCCR3A, COM3B1);    break;
-		#endif
-		#if defined(TCCR3A) && defined(COM3C1)
-		case  TIMER3C:  cbi(TCCR3A, COM3C1);    break;
-		#endif
-
-		#if defined(TCCR4A) && defined(COM4A1)
-		case  TIMER4A:  cbi(TCCR4A, COM4A1);    break;
-		#endif					
-		#if defined(TCCR4A) && defined(COM4B1)
-		case  TIMER4B:  cbi(TCCR4A, COM4B1);    break;
-		#endif
-		#if defined(TCCR4A) && defined(COM4C1)
-		case  TIMER4C:  cbi(TCCR4A, COM4C1);    break;
-		#endif			
-		#if defined(TCCR4C) && defined(COM4D1)
-		case TIMER4D:	cbi(TCCR4C, COM4D1);	break;
-		#endif			
-			
-		#if defined(TCCR5A)
-		case  TIMER5A:  cbi(TCCR5A, COM5A1);    break;
-		case  TIMER5B:  cbi(TCCR5A, COM5B1);    break;
-		case  TIMER5C:  cbi(TCCR5A, COM5C1);    break;
-		#endif
-	}
-}
-
-void digitalWrite(uint8_t pin, uint8_t val)
-{
-	uint8_t timer = digitalPinToTimer(pin);
-	uint8_t bit = digitalPinToBitMask(pin);
-	uint8_t port = digitalPinToPort(pin);
-	volatile uint8_t *out;
-
-	if (port == NOT_A_PIN) return;
-
-	// If the pin that support PWM output, we need to turn it off
-	// before doing a digital write.
-	if (timer != NOT_ON_TIMER) turnOffPWM(timer);
-
-	out = portOutputRegister(port);
-
-	uint8_t oldSREG = SREG;
-	cli();
-
-	if (val == LOW) {
-		*out &= ~bit;
-	} else {
-		*out |= bit;
-	}
-
-	SREG = oldSREG;
-}
-
-int digitalRead(uint8_t pin)
-{
-	uint8_t timer = digitalPinToTimer(pin);
-	uint8_t bit = digitalPinToBitMask(pin);
-	uint8_t port = digitalPinToPort(pin);
-
-	if (port == NOT_A_PIN) return LOW;
-
-	// If the pin that support PWM output, we need to turn it off
-	// before getting a digital reading.
-	if (timer != NOT_ON_TIMER) turnOffPWM(timer);
-
-	if (*portInputRegister(port) & bit) return HIGH;
-	return LOW;
-}
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_private.h b/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_private.h
deleted file mode 100644
index f0ceb0cc4d..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_private.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
-  wiring_private.h - Internal header file.
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2005-2006 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  $Id: wiring.h 239 2007-01-12 17:58:39Z mellis $
-*/
-
-#ifndef WiringPrivate_h
-#define WiringPrivate_h
-
-#include <avr/io.h>
-#include <avr/interrupt.h>
-#include <stdio.h>
-#include <stdarg.h>
-
-#include "Arduino.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#ifndef cbi
-#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
-#endif
-#ifndef sbi
-#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))
-#endif
-
-#define EXTERNAL_INT_0 0
-#define EXTERNAL_INT_1 1
-#define EXTERNAL_INT_2 2
-#define EXTERNAL_INT_3 3
-#define EXTERNAL_INT_4 4
-#define EXTERNAL_INT_5 5
-#define EXTERNAL_INT_6 6
-#define EXTERNAL_INT_7 7
-
-#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
-#define EXTERNAL_NUM_INTERRUPTS 8
-#elif defined(__AVR_ATmega1284P__) 
-#define EXTERNAL_NUM_INTERRUPTS 3
-#else
-#define EXTERNAL_NUM_INTERRUPTS 2
-#endif
-
-typedef void (*voidFuncPtr)(void);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_pulse.c b/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_pulse.c
deleted file mode 100644
index 0d968865d2..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_pulse.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
-  wiring_pulse.c - pulseIn() function
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2005-2006 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $
-*/
-
-#include "wiring_private.h"
-#include "pins_arduino.h"
-
-/* Measures the length (in microseconds) of a pulse on the pin; state is HIGH
- * or LOW, the type of pulse to measure.  Works on pulses from 2-3 microseconds
- * to 3 minutes in length, but must be called at least a few dozen microseconds
- * before the start of the pulse. */
-unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout)
-{
-	// cache the port and bit of the pin in order to speed up the
-	// pulse width measuring loop and achieve finer resolution.  calling
-	// digitalRead() instead yields much coarser resolution.
-	uint8_t bit = digitalPinToBitMask(pin);
-	uint8_t port = digitalPinToPort(pin);
-	uint8_t stateMask = (state ? bit : 0);
-	unsigned long width = 0; // keep initialization out of time critical area
-	
-	// convert the timeout from microseconds to a number of times through
-	// the initial loop; it takes 16 clock cycles per iteration.
-	unsigned long numloops = 0;
-	unsigned long maxloops = microsecondsToClockCycles(timeout) / 16;
-	
-	// wait for any previous pulse to end
-	while ((*portInputRegister(port) & bit) == stateMask)
-		if (numloops++ == maxloops)
-			return 0;
-	
-	// wait for the pulse to start
-	while ((*portInputRegister(port) & bit) != stateMask)
-		if (numloops++ == maxloops)
-			return 0;
-	
-	// wait for the pulse to stop
-	while ((*portInputRegister(port) & bit) == stateMask) {
-		if (numloops++ == maxloops)
-			return 0;
-		width++;
-	}
-
-	// convert the reading to microseconds. The loop has been determined
-	// to be 20 clock cycles long and have about 16 clocks between the edge
-	// and the start of the loop. There will be some error introduced by
-	// the interrupt handlers.
-	return clockCyclesToMicroseconds(width * 21 + 16); 
-}
diff --git a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_shift.c b/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_shift.c
deleted file mode 100644
index cfe786758c..0000000000
--- a/lib/usbhost/arduino-1.0.1/cores/arduino/wiring_shift.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
-  wiring_shift.c - shiftOut() function
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2005-2006 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $
-*/
-
-#include "wiring_private.h"
-
-uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) {
-	uint8_t value = 0;
-	uint8_t i;
-
-	for (i = 0; i < 8; ++i) {
-		digitalWrite(clockPin, HIGH);
-		if (bitOrder == LSBFIRST)
-			value |= digitalRead(dataPin) << i;
-		else
-			value |= digitalRead(dataPin) << (7 - i);
-		digitalWrite(clockPin, LOW);
-	}
-	return value;
-}
-
-void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val)
-{
-	uint8_t i;
-
-	for (i = 0; i < 8; i++)  {
-		if (bitOrder == LSBFIRST)
-			digitalWrite(dataPin, !!(val & (1 << i)));
-		else	
-			digitalWrite(dataPin, !!(val & (1 << (7 - i))));
-			
-		digitalWrite(clockPin, HIGH);
-		digitalWrite(clockPin, LOW);		
-	}
-}
diff --git a/lib/usbhost/arduino-1.0.1/variants/eightanaloginputs/pins_arduino.h b/lib/usbhost/arduino-1.0.1/variants/eightanaloginputs/pins_arduino.h
deleted file mode 100644
index 52b37efc40..0000000000
--- a/lib/usbhost/arduino-1.0.1/variants/eightanaloginputs/pins_arduino.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
-  pins_arduino.h - Pin definition functions for Arduino
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2007 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $
-*/
-
-#include "../standard/pins_arduino.h"
-#undef NUM_ANALOG_INPUTS
-#define NUM_ANALOG_INPUTS           8
diff --git a/lib/usbhost/arduino-1.0.1/variants/leonardo/pins_arduino.h b/lib/usbhost/arduino-1.0.1/variants/leonardo/pins_arduino.h
deleted file mode 100644
index 9f770d6cec..0000000000
--- a/lib/usbhost/arduino-1.0.1/variants/leonardo/pins_arduino.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
-  pins_arduino.h - Pin definition functions for Arduino
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2007 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $
-*/
-
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <avr/pgmspace.h>
-
-#define TX_RX_LED_INIT	DDRD |= (1<<5), DDRB |= (1<<0)
-#define TXLED0			PORTD |= (1<<5)
-#define TXLED1			PORTD &= ~(1<<5)
-#define RXLED0			PORTB |= (1<<0)
-#define RXLED1			PORTB &= ~(1<<0)
-
-static const uint8_t SDA = 2;
-static const uint8_t SCL = 3;
-
-// Map SPI port to 'new' pins D14..D17
-static const uint8_t SS   = 17;
-static const uint8_t MOSI = 16;
-static const uint8_t MISO = 14;
-static const uint8_t SCK  = 15;
-
-// Mapping of analog pins as digital I/O
-// A6-A11 share with digital pins
-static const uint8_t A0 = 18;
-static const uint8_t A1 = 19;
-static const uint8_t A2 = 20;
-static const uint8_t A3 = 21;
-static const uint8_t A4 = 22;
-static const uint8_t A5 = 23;
-static const uint8_t A6 = 24;	// D4
-static const uint8_t A7 = 25;	// D6
-static const uint8_t A8 = 26;	// D8
-static const uint8_t A9 = 27;	// D9
-static const uint8_t A10 = 28;	// D10
-static const uint8_t A11 = 29;	// D12
-
-#define digitalPinToPCICR(p)    ((((p) >= 8 && (p) <= 11) || ((p) >= 14 && (p) <= 17) || ((p) >= A8 && (p) <= A10)) ? (&PCICR) : ((uint8_t *)0))
-#define digitalPinToPCICRbit(p) 0
-#define digitalPinToPCMSK(p)    ((((p) >= 8 && (p) <= 11) || ((p) >= 14 && (p) <= 17) || ((p) >= A8 && (p) <= A10)) ? (&PCMSK0) : ((uint8_t *)0))
-#define digitalPinToPCMSKbit(p) ( ((p) >= 8 && (p) <= 11) ? (p) - 4 : ((p) == 14 ? 3 : ((p) == 15 ? 1 : ((p) == 16 ? 2 : ((p) == 17 ? 0 : (p - A8 + 4))))))
-
-//	__AVR_ATmega32U4__ has an unusual mapping of pins to channels
-extern const uint8_t PROGMEM analog_pin_to_channel_PGM[];
-#define analogPinToChannel(P)  ( pgm_read_byte( analog_pin_to_channel_PGM + (P) ) )
-
-#ifdef ARDUINO_MAIN
-
-// On the Arduino board, digital pins are also used
-// for the analog output (software PWM).  Analog input
-// pins are a separate set.
-
-// ATMEL ATMEGA32U4 / ARDUINO LEONARDO
-//
-// D0				PD2					RXD1/INT2
-// D1				PD3					TXD1/INT3
-// D2				PD1		SDA			SDA/INT1
-// D3#				PD0		PWM8/SCL	OC0B/SCL/INT0
-// D4		A6		PD4					ADC8
-// D5#				PC6		???			OC3A/#OC4A
-// D6#		A7		PD7		FastPWM		#OC4D/ADC10
-// D7				PE6					INT6/AIN0
-//
-// D8		A8		PB4					ADC11/PCINT4
-// D9#		A9		PB5		PWM16		OC1A/#OC4B/ADC12/PCINT5
-// D10#		A10		PB6		PWM16		OC1B/0c4B/ADC13/PCINT6
-// D11#				PB7		PWM8/16		0C0A/OC1C/#RTS/PCINT7
-// D12		A11		PD6					T1/#OC4D/ADC9
-// D13#				PC7		PWM10		CLK0/OC4A
-//
-// A0		D18		PF7					ADC7
-// A1		D19		PF6					ADC6
-// A2		D20 	PF5					ADC5
-// A3		D21 	PF4					ADC4
-// A4		D22		PF1					ADC1
-// A5		D23 	PF0					ADC0
-//
-// New pins D14..D17 to map SPI port to digital pins
-//
-// MISO		D14		PB3					MISO,PCINT3
-// SCK		D15		PB1					SCK,PCINT1
-// MOSI		D16		PB2					MOSI,PCINT2
-// SS		D17		PB0					RXLED,SS/PCINT0
-//
-// TXLED			PD5
-// RXLED		    PB0
-// HWB				PE2					HWB
-
-// these arrays map port names (e.g. port B) to the
-// appropriate addresses for various functions (e.g. reading
-// and writing)
-const uint16_t PROGMEM port_to_mode_PGM[] = {
-	NOT_A_PORT,
-	NOT_A_PORT,
-	(uint16_t) &DDRB,
-	(uint16_t) &DDRC,
-	(uint16_t) &DDRD,
-	(uint16_t) &DDRE,
-	(uint16_t) &DDRF,
-};
-
-const uint16_t PROGMEM port_to_output_PGM[] = {
-	NOT_A_PORT,
-	NOT_A_PORT,
-	(uint16_t) &PORTB,
-	(uint16_t) &PORTC,
-	(uint16_t) &PORTD,
-	(uint16_t) &PORTE,
-	(uint16_t) &PORTF,
-};
-
-const uint16_t PROGMEM port_to_input_PGM[] = {
-	NOT_A_PORT,
-	NOT_A_PORT,
-	(uint16_t) &PINB,
-	(uint16_t) &PINC,
-	(uint16_t) &PIND,
-	(uint16_t) &PINE,
-	(uint16_t) &PINF,
-};
-
-const uint8_t PROGMEM digital_pin_to_port_PGM[30] = {
-	PD, // D0 - PD2
-	PD,	// D1 - PD3
-	PD, // D2 - PD1
-	PD,	// D3 - PD0
-	PD,	// D4 - PD4
-	PC, // D5 - PC6
-	PD, // D6 - PD7
-	PE, // D7 - PE6
-	
-	PB, // D8 - PB4
-	PB,	// D9 - PB5
-	PB, // D10 - PB6
-	PB,	// D11 - PB7
-	PD, // D12 - PD6
-	PC, // D13 - PC7
-	
-	PB,	// D14 - MISO - PB3
-	PB,	// D15 - SCK - PB1
-	PB,	// D16 - MOSI - PB2
-	PB,	// D17 - SS - PB0
-	
-	PF,	// D18 - A0 - PF7
-	PF, // D19 - A1 - PF6
-	PF, // D20 - A2 - PF5
-	PF, // D21 - A3 - PF4
-	PF, // D22 - A4 - PF1
-	PF, // D23 - A5 - PF0
-	
-	PD, // D24 / D4 - A6 - PD4
-	PD, // D25 / D6 - A7 - PD7
-	PB, // D26 / D8 - A8 - PB4
-	PB, // D27 / D9 - A9 - PB5
-	PB, // D28 / D10 - A10 - PB6
-	PD, // D29 / D12 - A11 - PD6
-};
-
-const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[30] = {
-	_BV(2), // D0 - PD2
-	_BV(3),	// D1 - PD3
-	_BV(1), // D2 - PD1
-	_BV(0),	// D3 - PD0
-	_BV(4),	// D4 - PD4
-	_BV(6), // D5 - PC6
-	_BV(7), // D6 - PD7
-	_BV(6), // D7 - PE6
-	
-	_BV(4), // D8 - PB4
-	_BV(5),	// D9 - PB5
-	_BV(6), // D10 - PB6
-	_BV(7),	// D11 - PB7
-	_BV(6), // D12 - PD6
-	_BV(7), // D13 - PC7
-	
-	_BV(3),	// D14 - MISO - PB3
-	_BV(1),	// D15 - SCK - PB1
-	_BV(2),	// D16 - MOSI - PB2
-	_BV(0),	// D17 - SS - PB0
-	
-	_BV(7),	// D18 - A0 - PF7
-	_BV(6), // D19 - A1 - PF6
-	_BV(5), // D20 - A2 - PF5
-	_BV(4), // D21 - A3 - PF4
-	_BV(1), // D22 - A4 - PF1
-	_BV(0), // D23 - A5 - PF0
-	
-	_BV(4), // D24 / D4 - A6 - PD4
-	_BV(7), // D25 / D6 - A7 - PD7
-	_BV(4), // D26 / D8 - A8 - PB4
-	_BV(5), // D27 / D9 - A9 - PB5
-	_BV(6), // D28 / D10 - A10 - PB6
-	_BV(6), // D29 / D12 - A11 - PD6
-};
-
-const uint8_t PROGMEM digital_pin_to_timer_PGM[16] = {
-	NOT_ON_TIMER,	
-	NOT_ON_TIMER,
-	NOT_ON_TIMER,
-	TIMER0B,		/* 3 */
-	NOT_ON_TIMER,
-	TIMER3A,		/* 5 */
-	TIMER4D,		/* 6 */
-	NOT_ON_TIMER,	
-	
-	NOT_ON_TIMER,	
-	TIMER1A,		/* 9 */
-	TIMER1B,		/* 10 */
-	TIMER0A,		/* 11 */
-	
-	NOT_ON_TIMER,	
-	TIMER4A,		/* 13 */
-	
-	NOT_ON_TIMER,	
-	NOT_ON_TIMER,
-};
-
-const uint8_t PROGMEM analog_pin_to_channel_PGM[12] = {
-	7,	// A0				PF7					ADC7
-	6,	// A1				PF6					ADC6	
-	5,	// A2				PF5					ADC5	
-	4,	// A3				PF4					ADC4
-	1,	// A4				PF1					ADC1	
-	0,	// A5				PF0					ADC0	
-	8,	// A6		D4		PD4					ADC8
-	10,	// A7		D6		PD7					ADC10
-	11,	// A8		D8		PB4					ADC11
-	12,	// A9		D9		PB5					ADC12
-	13,	// A10		D10		PB6					ADC13
-	9	// A11		D12		PD6					ADC9
-};
-
-#endif /* ARDUINO_MAIN */
-#endif /* Pins_Arduino_h */
diff --git a/lib/usbhost/arduino-1.0.1/variants/mega/pins_arduino.h b/lib/usbhost/arduino-1.0.1/variants/mega/pins_arduino.h
deleted file mode 100644
index 5a9b4cb09b..0000000000
--- a/lib/usbhost/arduino-1.0.1/variants/mega/pins_arduino.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
-  pins_arduino.h - Pin definition functions for Arduino
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2007 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $
-*/
-
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <avr/pgmspace.h>
-
-#define NUM_DIGITAL_PINS            70
-#define NUM_ANALOG_INPUTS           16
-#define analogInputToDigitalPin(p)  ((p < 16) ? (p) + 54 : -1)
-#define digitalPinHasPWM(p)         (((p) >= 2 && (p) <= 13) || ((p) >= 44 && (p)<= 46))
-
-static const uint8_t SS   = 53;
-static const uint8_t MOSI = 51;
-static const uint8_t MISO = 50;
-static const uint8_t SCK  = 52;
-
-static const uint8_t SDA = 20;
-static const uint8_t SCL = 21;
-static const uint8_t LED_BUILTIN = 13;
-
-static const uint8_t A0 = 54;
-static const uint8_t A1 = 55;
-static const uint8_t A2 = 56;
-static const uint8_t A3 = 57;
-static const uint8_t A4 = 58;
-static const uint8_t A5 = 59;
-static const uint8_t A6 = 60;
-static const uint8_t A7 = 61;
-static const uint8_t A8 = 62;
-static const uint8_t A9 = 63;
-static const uint8_t A10 = 64;
-static const uint8_t A11 = 65;
-static const uint8_t A12 = 66;
-static const uint8_t A13 = 67;
-static const uint8_t A14 = 68;
-static const uint8_t A15 = 69;
-
-// A majority of the pins are NOT PCINTs, SO BE WARNED (i.e. you cannot use them as receive pins)
-// Only pins available for RECEIVE (TRANSMIT can be on any pin):
-// (I've deliberately left out pin mapping to the Hardware USARTs - seems senseless to me)
-// Pins: 10, 11, 12, 13,  50, 51, 52, 53,  62, 63, 64, 65, 66, 67, 68, 69
-
-#define digitalPinToPCICR(p)    ( (((p) >= 10) && ((p) <= 13)) || \
-                                  (((p) >= 50) && ((p) <= 53)) || \
-                                  (((p) >= 62) && ((p) <= 69)) ? (&PCICR) : ((uint8_t *)0) )
-
-#define digitalPinToPCICRbit(p) ( (((p) >= 10) && ((p) <= 13)) || (((p) >= 50) && ((p) <= 53)) ? 0 : \
-                                ( (((p) >= 62) && ((p) <= 69)) ? 2 : \
-                                0 ) )
-
-#define digitalPinToPCMSK(p)    ( (((p) >= 10) && ((p) <= 13)) || (((p) >= 50) && ((p) <= 53)) ? (&PCMSK0) : \
-                                ( (((p) >= 62) && ((p) <= 69)) ? (&PCMSK2) : \
-                                ((uint8_t *)0) ) )
-
-#define digitalPinToPCMSKbit(p) ( (((p) >= 10) && ((p) <= 13)) ? ((p) - 6) : \
-                                ( ((p) == 50) ? 3 : \
-                                ( ((p) == 51) ? 2 : \
-                                ( ((p) == 52) ? 1 : \
-                                ( ((p) == 53) ? 0 : \
-                                ( (((p) >= 62) && ((p) <= 69)) ? ((p) - 62) : \
-                                0 ) ) ) ) ) )
-
-#ifdef ARDUINO_MAIN
-
-const uint16_t PROGMEM port_to_mode_PGM[] = {
-	NOT_A_PORT,
-	(uint16_t) &DDRA,
-	(uint16_t) &DDRB,
-	(uint16_t) &DDRC,
-	(uint16_t) &DDRD,
-	(uint16_t) &DDRE,
-	(uint16_t) &DDRF,
-	(uint16_t) &DDRG,
-	(uint16_t) &DDRH,
-	NOT_A_PORT,
-	(uint16_t) &DDRJ,
-	(uint16_t) &DDRK,
-	(uint16_t) &DDRL,
-};
-
-const uint16_t PROGMEM port_to_output_PGM[] = {
-	NOT_A_PORT,
-	(uint16_t) &PORTA,
-	(uint16_t) &PORTB,
-	(uint16_t) &PORTC,
-	(uint16_t) &PORTD,
-	(uint16_t) &PORTE,
-	(uint16_t) &PORTF,
-	(uint16_t) &PORTG,
-	(uint16_t) &PORTH,
-	NOT_A_PORT,
-	(uint16_t) &PORTJ,
-	(uint16_t) &PORTK,
-	(uint16_t) &PORTL,
-};
-
-const uint16_t PROGMEM port_to_input_PGM[] = {
-	NOT_A_PIN,
-	(uint16_t) &PINA,
-	(uint16_t) &PINB,
-	(uint16_t) &PINC,
-	(uint16_t) &PIND,
-	(uint16_t) &PINE,
-	(uint16_t) &PINF,
-	(uint16_t) &PING,
-	(uint16_t) &PINH,
-	NOT_A_PIN,
-	(uint16_t) &PINJ,
-	(uint16_t) &PINK,
-	(uint16_t) &PINL,
-};
-
-const uint8_t PROGMEM digital_pin_to_port_PGM[] = {
-	// PORTLIST		
-	// -------------------------------------------		
-	PE	, // PE 0 ** 0 ** USART0_RX	
-	PE	, // PE 1 ** 1 ** USART0_TX	
-	PE	, // PE 4 ** 2 ** PWM2	
-	PE	, // PE 5 ** 3 ** PWM3	
-	PG	, // PG 5 ** 4 ** PWM4	
-	PE	, // PE 3 ** 5 ** PWM5	
-	PH	, // PH 3 ** 6 ** PWM6	
-	PH	, // PH 4 ** 7 ** PWM7	
-	PH	, // PH 5 ** 8 ** PWM8	
-	PH	, // PH 6 ** 9 ** PWM9	
-	PB	, // PB 4 ** 10 ** PWM10	
-	PB	, // PB 5 ** 11 ** PWM11	
-	PB	, // PB 6 ** 12 ** PWM12	
-	PB	, // PB 7 ** 13 ** PWM13	
-	PJ	, // PJ 1 ** 14 ** USART3_TX	
-	PJ	, // PJ 0 ** 15 ** USART3_RX	
-	PH	, // PH 1 ** 16 ** USART2_TX	
-	PH	, // PH 0 ** 17 ** USART2_RX	
-	PD	, // PD 3 ** 18 ** USART1_TX	
-	PD	, // PD 2 ** 19 ** USART1_RX	
-	PD	, // PD 1 ** 20 ** I2C_SDA	
-	PD	, // PD 0 ** 21 ** I2C_SCL	
-	PA	, // PA 0 ** 22 ** D22	
-	PA	, // PA 1 ** 23 ** D23	
-	PA	, // PA 2 ** 24 ** D24	
-	PA	, // PA 3 ** 25 ** D25	
-	PA	, // PA 4 ** 26 ** D26	
-	PA	, // PA 5 ** 27 ** D27	
-	PA	, // PA 6 ** 28 ** D28	
-	PA	, // PA 7 ** 29 ** D29	
-	PC	, // PC 7 ** 30 ** D30	
-	PC	, // PC 6 ** 31 ** D31	
-	PC	, // PC 5 ** 32 ** D32	
-	PC	, // PC 4 ** 33 ** D33	
-	PC	, // PC 3 ** 34 ** D34	
-	PC	, // PC 2 ** 35 ** D35	
-	PC	, // PC 1 ** 36 ** D36	
-	PC	, // PC 0 ** 37 ** D37	
-	PD	, // PD 7 ** 38 ** D38	
-	PG	, // PG 2 ** 39 ** D39	
-	PG	, // PG 1 ** 40 ** D40	
-	PG	, // PG 0 ** 41 ** D41	
-	PL	, // PL 7 ** 42 ** D42	
-	PL	, // PL 6 ** 43 ** D43	
-	PL	, // PL 5 ** 44 ** D44	
-	PL	, // PL 4 ** 45 ** D45	
-	PL	, // PL 3 ** 46 ** D46	
-	PL	, // PL 2 ** 47 ** D47	
-	PL	, // PL 1 ** 48 ** D48	
-	PL	, // PL 0 ** 49 ** D49	
-	PB	, // PB 3 ** 50 ** SPI_MISO	
-	PB	, // PB 2 ** 51 ** SPI_MOSI	
-	PB	, // PB 1 ** 52 ** SPI_SCK	
-	PB	, // PB 0 ** 53 ** SPI_SS	
-	PF	, // PF 0 ** 54 ** A0	
-	PF	, // PF 1 ** 55 ** A1	
-	PF	, // PF 2 ** 56 ** A2	
-	PF	, // PF 3 ** 57 ** A3	
-	PF	, // PF 4 ** 58 ** A4	
-	PF	, // PF 5 ** 59 ** A5	
-	PF	, // PF 6 ** 60 ** A6	
-	PF	, // PF 7 ** 61 ** A7	
-	PK	, // PK 0 ** 62 ** A8	
-	PK	, // PK 1 ** 63 ** A9	
-	PK	, // PK 2 ** 64 ** A10	
-	PK	, // PK 3 ** 65 ** A11	
-	PK	, // PK 4 ** 66 ** A12	
-	PK	, // PK 5 ** 67 ** A13	
-	PK	, // PK 6 ** 68 ** A14	
-	PK	, // PK 7 ** 69 ** A15	
-};
-
-const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = {
-	// PIN IN PORT		
-	// -------------------------------------------		
-	_BV( 0 )	, // PE 0 ** 0 ** USART0_RX	
-	_BV( 1 )	, // PE 1 ** 1 ** USART0_TX	
-	_BV( 4 )	, // PE 4 ** 2 ** PWM2	
-	_BV( 5 )	, // PE 5 ** 3 ** PWM3	
-	_BV( 5 )	, // PG 5 ** 4 ** PWM4	
-	_BV( 3 )	, // PE 3 ** 5 ** PWM5	
-	_BV( 3 )	, // PH 3 ** 6 ** PWM6	
-	_BV( 4 )	, // PH 4 ** 7 ** PWM7	
-	_BV( 5 )	, // PH 5 ** 8 ** PWM8	
-	_BV( 6 )	, // PH 6 ** 9 ** PWM9	
-	_BV( 4 )	, // PB 4 ** 10 ** PWM10	
-	_BV( 5 )	, // PB 5 ** 11 ** PWM11	
-	_BV( 6 )	, // PB 6 ** 12 ** PWM12	
-	_BV( 7 )	, // PB 7 ** 13 ** PWM13	
-	_BV( 1 )	, // PJ 1 ** 14 ** USART3_TX	
-	_BV( 0 )	, // PJ 0 ** 15 ** USART3_RX	
-	_BV( 1 )	, // PH 1 ** 16 ** USART2_TX	
-	_BV( 0 )	, // PH 0 ** 17 ** USART2_RX	
-	_BV( 3 )	, // PD 3 ** 18 ** USART1_TX	
-	_BV( 2 )	, // PD 2 ** 19 ** USART1_RX	
-	_BV( 1 )	, // PD 1 ** 20 ** I2C_SDA	
-	_BV( 0 )	, // PD 0 ** 21 ** I2C_SCL	
-	_BV( 0 )	, // PA 0 ** 22 ** D22	
-	_BV( 1 )	, // PA 1 ** 23 ** D23	
-	_BV( 2 )	, // PA 2 ** 24 ** D24	
-	_BV( 3 )	, // PA 3 ** 25 ** D25	
-	_BV( 4 )	, // PA 4 ** 26 ** D26	
-	_BV( 5 )	, // PA 5 ** 27 ** D27	
-	_BV( 6 )	, // PA 6 ** 28 ** D28	
-	_BV( 7 )	, // PA 7 ** 29 ** D29	
-	_BV( 7 )	, // PC 7 ** 30 ** D30	
-	_BV( 6 )	, // PC 6 ** 31 ** D31	
-	_BV( 5 )	, // PC 5 ** 32 ** D32	
-	_BV( 4 )	, // PC 4 ** 33 ** D33	
-	_BV( 3 )	, // PC 3 ** 34 ** D34	
-	_BV( 2 )	, // PC 2 ** 35 ** D35	
-	_BV( 1 )	, // PC 1 ** 36 ** D36	
-	_BV( 0 )	, // PC 0 ** 37 ** D37	
-	_BV( 7 )	, // PD 7 ** 38 ** D38	
-	_BV( 2 )	, // PG 2 ** 39 ** D39	
-	_BV( 1 )	, // PG 1 ** 40 ** D40	
-	_BV( 0 )	, // PG 0 ** 41 ** D41	
-	_BV( 7 )	, // PL 7 ** 42 ** D42	
-	_BV( 6 )	, // PL 6 ** 43 ** D43	
-	_BV( 5 )	, // PL 5 ** 44 ** D44	
-	_BV( 4 )	, // PL 4 ** 45 ** D45	
-	_BV( 3 )	, // PL 3 ** 46 ** D46	
-	_BV( 2 )	, // PL 2 ** 47 ** D47	
-	_BV( 1 )	, // PL 1 ** 48 ** D48	
-	_BV( 0 )	, // PL 0 ** 49 ** D49	
-	_BV( 3 )	, // PB 3 ** 50 ** SPI_MISO	
-	_BV( 2 )	, // PB 2 ** 51 ** SPI_MOSI	
-	_BV( 1 )	, // PB 1 ** 52 ** SPI_SCK	
-	_BV( 0 )	, // PB 0 ** 53 ** SPI_SS	
-	_BV( 0 )	, // PF 0 ** 54 ** A0	
-	_BV( 1 )	, // PF 1 ** 55 ** A1	
-	_BV( 2 )	, // PF 2 ** 56 ** A2	
-	_BV( 3 )	, // PF 3 ** 57 ** A3	
-	_BV( 4 )	, // PF 4 ** 58 ** A4	
-	_BV( 5 )	, // PF 5 ** 59 ** A5	
-	_BV( 6 )	, // PF 6 ** 60 ** A6	
-	_BV( 7 )	, // PF 7 ** 61 ** A7	
-	_BV( 0 )	, // PK 0 ** 62 ** A8	
-	_BV( 1 )	, // PK 1 ** 63 ** A9	
-	_BV( 2 )	, // PK 2 ** 64 ** A10	
-	_BV( 3 )	, // PK 3 ** 65 ** A11	
-	_BV( 4 )	, // PK 4 ** 66 ** A12	
-	_BV( 5 )	, // PK 5 ** 67 ** A13	
-	_BV( 6 )	, // PK 6 ** 68 ** A14	
-	_BV( 7 )	, // PK 7 ** 69 ** A15	
-};
-
-const uint8_t PROGMEM digital_pin_to_timer_PGM[] = {
-	// TIMERS		
-	// -------------------------------------------		
-	NOT_ON_TIMER	, // PE 0 ** 0 ** USART0_RX	
-	NOT_ON_TIMER	, // PE 1 ** 1 ** USART0_TX	
-	TIMER3B	, // PE 4 ** 2 ** PWM2	
-	TIMER3C	, // PE 5 ** 3 ** PWM3	
-	TIMER0B	, // PG 5 ** 4 ** PWM4	
-	TIMER3A	, // PE 3 ** 5 ** PWM5	
-	TIMER4A	, // PH 3 ** 6 ** PWM6	
-	TIMER4B	, // PH 4 ** 7 ** PWM7	
-	TIMER4C	, // PH 5 ** 8 ** PWM8	
-	TIMER2B	, // PH 6 ** 9 ** PWM9	
-	TIMER2A	, // PB 4 ** 10 ** PWM10	
-	TIMER1A	, // PB 5 ** 11 ** PWM11	
-	TIMER1B	, // PB 6 ** 12 ** PWM12	
-	TIMER0A	, // PB 7 ** 13 ** PWM13	
-	NOT_ON_TIMER	, // PJ 1 ** 14 ** USART3_TX	
-	NOT_ON_TIMER	, // PJ 0 ** 15 ** USART3_RX	
-	NOT_ON_TIMER	, // PH 1 ** 16 ** USART2_TX	
-	NOT_ON_TIMER	, // PH 0 ** 17 ** USART2_RX	
-	NOT_ON_TIMER	, // PD 3 ** 18 ** USART1_TX	
-	NOT_ON_TIMER	, // PD 2 ** 19 ** USART1_RX	
-	NOT_ON_TIMER	, // PD 1 ** 20 ** I2C_SDA	
-	NOT_ON_TIMER	, // PD 0 ** 21 ** I2C_SCL	
-	NOT_ON_TIMER	, // PA 0 ** 22 ** D22	
-	NOT_ON_TIMER	, // PA 1 ** 23 ** D23	
-	NOT_ON_TIMER	, // PA 2 ** 24 ** D24	
-	NOT_ON_TIMER	, // PA 3 ** 25 ** D25	
-	NOT_ON_TIMER	, // PA 4 ** 26 ** D26	
-	NOT_ON_TIMER	, // PA 5 ** 27 ** D27	
-	NOT_ON_TIMER	, // PA 6 ** 28 ** D28	
-	NOT_ON_TIMER	, // PA 7 ** 29 ** D29	
-	NOT_ON_TIMER	, // PC 7 ** 30 ** D30	
-	NOT_ON_TIMER	, // PC 6 ** 31 ** D31	
-	NOT_ON_TIMER	, // PC 5 ** 32 ** D32	
-	NOT_ON_TIMER	, // PC 4 ** 33 ** D33	
-	NOT_ON_TIMER	, // PC 3 ** 34 ** D34	
-	NOT_ON_TIMER	, // PC 2 ** 35 ** D35	
-	NOT_ON_TIMER	, // PC 1 ** 36 ** D36	
-	NOT_ON_TIMER	, // PC 0 ** 37 ** D37	
-	NOT_ON_TIMER	, // PD 7 ** 38 ** D38	
-	NOT_ON_TIMER	, // PG 2 ** 39 ** D39	
-	NOT_ON_TIMER	, // PG 1 ** 40 ** D40	
-	NOT_ON_TIMER	, // PG 0 ** 41 ** D41	
-	NOT_ON_TIMER	, // PL 7 ** 42 ** D42	
-	NOT_ON_TIMER	, // PL 6 ** 43 ** D43	
-	TIMER5C	, // PL 5 ** 44 ** D44	
-	TIMER5B	, // PL 4 ** 45 ** D45	
-	TIMER5A	, // PL 3 ** 46 ** D46	
-	NOT_ON_TIMER	, // PL 2 ** 47 ** D47	
-	NOT_ON_TIMER	, // PL 1 ** 48 ** D48	
-	NOT_ON_TIMER	, // PL 0 ** 49 ** D49	
-	NOT_ON_TIMER	, // PB 3 ** 50 ** SPI_MISO	
-	NOT_ON_TIMER	, // PB 2 ** 51 ** SPI_MOSI	
-	NOT_ON_TIMER	, // PB 1 ** 52 ** SPI_SCK	
-	NOT_ON_TIMER	, // PB 0 ** 53 ** SPI_SS	
-	NOT_ON_TIMER	, // PF 0 ** 54 ** A0	
-	NOT_ON_TIMER	, // PF 1 ** 55 ** A1	
-	NOT_ON_TIMER	, // PF 2 ** 56 ** A2	
-	NOT_ON_TIMER	, // PF 3 ** 57 ** A3	
-	NOT_ON_TIMER	, // PF 4 ** 58 ** A4	
-	NOT_ON_TIMER	, // PF 5 ** 59 ** A5	
-	NOT_ON_TIMER	, // PF 6 ** 60 ** A6	
-	NOT_ON_TIMER	, // PF 7 ** 61 ** A7	
-	NOT_ON_TIMER	, // PK 0 ** 62 ** A8	
-	NOT_ON_TIMER	, // PK 1 ** 63 ** A9	
-	NOT_ON_TIMER	, // PK 2 ** 64 ** A10	
-	NOT_ON_TIMER	, // PK 3 ** 65 ** A11	
-	NOT_ON_TIMER	, // PK 4 ** 66 ** A12	
-	NOT_ON_TIMER	, // PK 5 ** 67 ** A13	
-	NOT_ON_TIMER	, // PK 6 ** 68 ** A14	
-	NOT_ON_TIMER	, // PK 7 ** 69 ** A15	
-};
-
-#endif
-
-#endif
\ No newline at end of file
diff --git a/lib/usbhost/arduino-1.0.1/variants/standard/pins_arduino.h b/lib/usbhost/arduino-1.0.1/variants/standard/pins_arduino.h
deleted file mode 100644
index 30b4266306..0000000000
--- a/lib/usbhost/arduino-1.0.1/variants/standard/pins_arduino.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
-  pins_arduino.h - Pin definition functions for Arduino
-  Part of Arduino - http://www.arduino.cc/
-
-  Copyright (c) 2007 David A. Mellis
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General
-  Public License along with this library; if not, write to the
-  Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-  Boston, MA  02111-1307  USA
-
-  $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $
-*/
-
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <avr/pgmspace.h>
-
-#define NUM_DIGITAL_PINS            20
-#define NUM_ANALOG_INPUTS           6
-#define analogInputToDigitalPin(p)  ((p < 6) ? (p) + 14 : -1)
-
-#if defined(__AVR_ATmega8__)
-#define digitalPinHasPWM(p)         ((p) == 9 || (p) == 10 || (p) == 11)
-#else
-#define digitalPinHasPWM(p)         ((p) == 3 || (p) == 5 || (p) == 6 || (p) == 9 || (p) == 10 || (p) == 11)
-#endif
-
-static const uint8_t SS   = 10;
-static const uint8_t MOSI = 11;
-static const uint8_t MISO = 12;
-static const uint8_t SCK  = 13;
-
-static const uint8_t SDA = 18;
-static const uint8_t SCL = 19;
-static const uint8_t LED_BUILTIN = 13;
-
-static const uint8_t A0 = 14;
-static const uint8_t A1 = 15;
-static const uint8_t A2 = 16;
-static const uint8_t A3 = 17;
-static const uint8_t A4 = 18;
-static const uint8_t A5 = 19;
-static const uint8_t A6 = 20;
-static const uint8_t A7 = 21;
-
-#define digitalPinToPCICR(p)    (((p) >= 0 && (p) <= 21) ? (&PCICR) : ((uint8_t *)0))
-#define digitalPinToPCICRbit(p) (((p) <= 7) ? 2 : (((p) <= 13) ? 0 : 1))
-#define digitalPinToPCMSK(p)    (((p) <= 7) ? (&PCMSK2) : (((p) <= 13) ? (&PCMSK0) : (((p) <= 21) ? (&PCMSK1) : ((uint8_t *)0))))
-#define digitalPinToPCMSKbit(p) (((p) <= 7) ? (p) : (((p) <= 13) ? ((p) - 8) : ((p) - 14)))
-
-#ifdef ARDUINO_MAIN
-
-// On the Arduino board, digital pins are also used
-// for the analog output (software PWM).  Analog input
-// pins are a separate set.
-
-// ATMEL ATMEGA8 & 168 / ARDUINO
-//
-//                  +-\/-+
-//            PC6  1|    |28  PC5 (AI 5)
-//      (D 0) PD0  2|    |27  PC4 (AI 4)
-//      (D 1) PD1  3|    |26  PC3 (AI 3)
-//      (D 2) PD2  4|    |25  PC2 (AI 2)
-// PWM+ (D 3) PD3  5|    |24  PC1 (AI 1)
-//      (D 4) PD4  6|    |23  PC0 (AI 0)
-//            VCC  7|    |22  GND
-//            GND  8|    |21  AREF
-//            PB6  9|    |20  AVCC
-//            PB7 10|    |19  PB5 (D 13)
-// PWM+ (D 5) PD5 11|    |18  PB4 (D 12)
-// PWM+ (D 6) PD6 12|    |17  PB3 (D 11) PWM
-//      (D 7) PD7 13|    |16  PB2 (D 10) PWM
-//      (D 8) PB0 14|    |15  PB1 (D 9) PWM
-//                  +----+
-//
-// (PWM+ indicates the additional PWM pins on the ATmega168.)
-
-// ATMEL ATMEGA1280 / ARDUINO
-//
-// 0-7 PE0-PE7   works
-// 8-13 PB0-PB5  works
-// 14-21 PA0-PA7 works 
-// 22-29 PH0-PH7 works
-// 30-35 PG5-PG0 works
-// 36-43 PC7-PC0 works
-// 44-51 PJ7-PJ0 works
-// 52-59 PL7-PL0 works
-// 60-67 PD7-PD0 works
-// A0-A7 PF0-PF7
-// A8-A15 PK0-PK7
-
-
-// these arrays map port names (e.g. port B) to the
-// appropriate addresses for various functions (e.g. reading
-// and writing)
-const uint16_t PROGMEM port_to_mode_PGM[] = {
-	NOT_A_PORT,
-	NOT_A_PORT,
-	(uint16_t) &DDRB,
-	(uint16_t) &DDRC,
-	(uint16_t) &DDRD,
-};
-
-const uint16_t PROGMEM port_to_output_PGM[] = {
-	NOT_A_PORT,
-	NOT_A_PORT,
-	(uint16_t) &PORTB,
-	(uint16_t) &PORTC,
-	(uint16_t) &PORTD,
-};
-
-const uint16_t PROGMEM port_to_input_PGM[] = {
-	NOT_A_PORT,
-	NOT_A_PORT,
-	(uint16_t) &PINB,
-	(uint16_t) &PINC,
-	(uint16_t) &PIND,
-};
-
-const uint8_t PROGMEM digital_pin_to_port_PGM[] = {
-	PD, /* 0 */
-	PD,
-	PD,
-	PD,
-	PD,
-	PD,
-	PD,
-	PD,
-	PB, /* 8 */
-	PB,
-	PB,
-	PB,
-	PB,
-	PB,
-	PC, /* 14 */
-	PC,
-	PC,
-	PC,
-	PC,
-	PC,
-};
-
-const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = {
-	_BV(0), /* 0, port D */
-	_BV(1),
-	_BV(2),
-	_BV(3),
-	_BV(4),
-	_BV(5),
-	_BV(6),
-	_BV(7),
-	_BV(0), /* 8, port B */
-	_BV(1),
-	_BV(2),
-	_BV(3),
-	_BV(4),
-	_BV(5),
-	_BV(0), /* 14, port C */
-	_BV(1),
-	_BV(2),
-	_BV(3),
-	_BV(4),
-	_BV(5),
-};
-
-const uint8_t PROGMEM digital_pin_to_timer_PGM[] = {
-	NOT_ON_TIMER, /* 0 - port D */
-	NOT_ON_TIMER,
-	NOT_ON_TIMER,
-	// on the ATmega168, digital pin 3 has hardware pwm
-#if defined(__AVR_ATmega8__)
-	NOT_ON_TIMER,
-#else
-	TIMER2B,
-#endif
-	NOT_ON_TIMER,
-	// on the ATmega168, digital pins 5 and 6 have hardware pwm
-#if defined(__AVR_ATmega8__)
-	NOT_ON_TIMER,
-	NOT_ON_TIMER,
-#else
-	TIMER0B,
-	TIMER0A,
-#endif
-	NOT_ON_TIMER,
-	NOT_ON_TIMER, /* 8 - port B */
-	TIMER1A,
-	TIMER1B,
-#if defined(__AVR_ATmega8__)
-	TIMER2,
-#else
-	TIMER2A,
-#endif
-	NOT_ON_TIMER,
-	NOT_ON_TIMER,
-	NOT_ON_TIMER,
-	NOT_ON_TIMER, /* 14 - port C */
-	NOT_ON_TIMER,
-	NOT_ON_TIMER,
-	NOT_ON_TIMER,
-	NOT_ON_TIMER,
-};
-
-#endif
-
-#endif
diff --git a/lib/vusb b/lib/vusb
deleted file mode 160000
-Subproject 819dbc1e5d5926b17e27e00ca6d3d2988adae04